Merge patch series "Hyperflash Boot fixes for J7200/J721E"
Anurag Dutta <a-dutta@ti.com> says:
Hi All,
In u-boot, hbmc is broken and has been removed from j7200
configs. This series re-enables the hbmc driver and introduces a series
of hyperflash boot fixes. At present, in u-boot, the parent device (fss)
gets registered as a syscon device. This is done because the MMIO
mux driver in u-boot did not support the mux functionality when the
parent device is not a syscon. In this series, we make relevant changes
in the hbmc driver as well as dts' so that we can use the reg-mux driver for
selecting the appropriate state of the mux.
Test logs:
1) j721e-idk-gw hyperflash boot test: https://gist.github.com/anuragdutta731/50aae6fec707a3ffad6d985de6757fe4
2) j7200-evm hyperflash boot test: https://gist.github.com/anuragdutta731/c3a4d60f8bfd9c425d6c44b36eb7322b
Link: https://lore.kernel.org/r/20241129113136.383277-1-a-dutta@ti.com
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 4ecf76e..c577a72 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@
windows_vm: windows-2022
ubuntu_vm: ubuntu-24.04
macos_vm: macOS-14
- ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240808-03Dec2024
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -245,8 +245,6 @@
ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
- grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
@@ -268,8 +266,8 @@
fi
pip install -r tools/buildman/requirements.txt
tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
- cp ~/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
- cp ~/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
+ cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
+ cp /opt/grub/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
cp /opt/grub/grubriscv64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
cp /opt/grub/grubaa64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
cp /opt/grub/grubarm.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 2164ad7..57037e2 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -4,6 +4,7 @@
DEFAULT_TAG: ""
MIRROR_DOCKER: docker.io
SJG_LAB: ""
+ PLATFORM: linux/amd64,linux/arm64
default:
tags:
@@ -11,7 +12,7 @@
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240808-03Dec2024
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -34,8 +35,6 @@
- ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
@@ -62,8 +61,8 @@
fi
- tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
--board ${TEST_PY_BD} ${OVERRIDE}
- - cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
- - cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
+ - cp /opt/grub/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
+ - cp /opt/grub/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
- cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
- cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
- cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
diff --git a/Kconfig b/Kconfig
index 1f5b0f1..2e63896 100644
--- a/Kconfig
+++ b/Kconfig
@@ -595,27 +595,6 @@
WARNING: Please make sure that this value is a multiple of the OS
page size.
-config SYS_HAS_SRAM
- bool
- default y if TARGET_PIC32MZDASK
- default y if TARGET_DEVKIT8000
- help
- Enable this to allow support for the on board SRAM.
- SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
- SRAM size is controlled by CONFIG_SYS_SRAM_SIZE.
-
-config SYS_SRAM_BASE
- hex
- default 0x80000000 if TARGET_PIC32MZDASK
- default 0x40200000 if TARGET_DEVKIT8000
- default 0x0
-
-config SYS_SRAM_SIZE
- hex
- default 0x00080000 if TARGET_PIC32MZDASK
- default 0x10000 if TARGET_DEVKIT8000
- default 0x0
-
config SYS_MONITOR_LEN
int "Maximum size in bytes reserved for U-Boot in memory"
default 1048576 if X86
diff --git a/MAINTAINERS b/MAINTAINERS
index 8c6c0c2..ba31f86 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1736,6 +1736,11 @@
T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git
F: drivers/mtd/ubi/
+UFETCH
+M: Caleb Connolly <caleb.connolly@linaro.org>
+S: Maintained
+F: cmd/ufetch.c
+
UFS
M: Neil Armstrong <neil.armstrong@linaro.org>
M: Bhupesh Sharma <bhupesh.linux@gmail.com>
diff --git a/Makefile b/Makefile
index 22953bd..54fdf67 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@@ -21,7 +21,7 @@
ifeq ("", "$(CROSS_COMPILE)")
MK_ARCH="${shell uname -m}"
else
- MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\?[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
+ MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
endif
unexport HOST_ARCH
ifeq ("x86_64", $(MK_ARCH))
@@ -1149,13 +1149,6 @@
@echo >&2 "See doc/develop/devicetree/control.rst for more info."
@echo >&2 "===================================================="
endif
-ifneq ($(CONFIG_SPL_FIT_GENERATOR),)
- @echo >&2 "===================== WARNING ======================"
- @echo >&2 "This board uses CONFIG_SPL_FIT_GENERATOR. Please migrate"
- @echo >&2 "to binman instead, to avoid the proliferation of"
- @echo >&2 "arch-specific scripts with no tests."
- @echo >&2 "===================================================="
-endif
$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
@@ -1392,12 +1385,21 @@
default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
endif
+binman_dtb := $(shell echo $(CONFIG_BINMAN_DTB))
+ifeq ($(strip $(binman_dtb)),)
+ifeq ($(CONFIG_OF_EMBED),y)
+binman_dtb = ./dts/dt.dtb
+else
+binman_dtb = ./u-boot.dtb
+endif
+endif
+
quiet_cmd_binman = BINMAN $@
cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
$(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
--toolpath $(objtree)/tools \
$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
- build -u -d u-boot.dtb -O . -m \
+ build -u -d $(binman_dtb) -O . -m \
--allow-missing --fake-ext-blobs \
$(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
@@ -1427,17 +1429,6 @@
u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
$(call if_changed,objcopy)
-# Boards with more complex image requirements can provide an .its source file
-# or a generator script
-# NOTE: Please do not use this. We are migrating away from Makefile rules to use
-# binman instead.
-ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
-U_BOOT_ITS := u-boot.its
-$(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE
- $(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
- $(patsubst %,$(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
-endif
-
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index 3a04a9f..2c1ab04 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -43,7 +43,6 @@
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
- platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
return 1;
}
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7282c41..ea414fe 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1177,7 +1177,6 @@
select SUNXI_GPIO
select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64
- select USB if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
select SPL_USE_TINY_PRINTF if SPL
@@ -1203,6 +1202,7 @@
imply SYSRESET
imply SYSRESET_WATCHDOG
imply SYSRESET_WATCHDOG_AUTO
+ imply USB
imply USB_GADGET
imply WDT
@@ -1324,6 +1324,7 @@
config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform"
select ARM64
+ select BINMAN
select CLK
select DM
select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index e6be635..5d6953f 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -825,7 +825,7 @@
void dcache_disable(void)
{
- uint32_t sctlr;
+ unsigned long sctlr;
sctlr = get_sctlr();
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index d568efa..82ecf02 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -94,3 +94,8 @@
secure_ram_addr(psci_arch_init)();
}
#endif
+
+void allow_unaligned(void)
+{
+ set_sctlr(get_sctlr() & ~CR_A);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6ad59ae..99d775f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -275,6 +275,7 @@
zynqmp-mini-qspi-x1-stacked.dtb \
zynqmp-mini-qspi-x2-single.dtb \
zynqmp-mini-qspi-x2-stacked.dtb \
+ zynqmp-binman-mini.dtb \
zynqmp-sc-revB.dtb \
zynqmp-sc-revC.dtb \
zynqmp-sm-k24-revA.dtb \
@@ -320,6 +321,7 @@
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-03-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-04-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-05-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman.dtb
zynqmp-sc-vek280-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vek280-revA.dtbo
zynqmp-sc-vek280-revB-dtbs := zynqmp-sc-revC.dtb zynqmp-sc-vek280-revB.dtbo
@@ -370,6 +372,7 @@
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman-som.dtb
dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini.dtb \
@@ -936,8 +939,7 @@
fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \
fsl-imx8qxp-mek.dtb \
- imx8-deneb.dtb \
- imx8-giedi.dtb
+ imx8-capricorn-cxg3.dtb \
dtb-$(CONFIG_ARCH_IMX8ULP) += \
imx8ulp-evk.dtb
@@ -1157,9 +1159,7 @@
stm32mp257f-ev1.dtb
dtb-$(CONFIG_SOC_K3_AM654) += \
- k3-am654-base-board.dtb \
- k3-am654-r5-base-board.dtb \
- k3-am654-icssg2.dtbo
+ k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb \
@@ -1184,7 +1184,9 @@
k3-am625-verdin-r5.dtb \
k3-am625-r5-phycore-som-2gb.dtb
-dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-r5-sk.dtb
+dtb-$(CONFIG_SOC_K3_AM62A7) += \
+ k3-am62a7-r5-sk.dtb \
+ k3-am62a7-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb
diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
index 3aa5d8b..6d7148f 100644
--- a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
+++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
@@ -3,17 +3,6 @@
* Copyright (c) 2023 Linaro Ltd.
*/
-&soc {
- /* TODO: Remove this node once it appears in upstream dts */
- trng: rng@12081400 {
- compatible = "samsung,exynos850-trng";
- reg = <0x12081400 0x100>;
- clocks = <&cmu_core CLK_GOUT_SSS_ACLK>,
- <&cmu_core CLK_GOUT_SSS_PCLK>;
- clock-names = "secss", "pclk";
- };
-};
-
&pmu_system_controller {
bootph-all;
samsung,uart-debug-1;
diff --git a/arch/arm/dts/imx8-capricorn-cxg3.dts b/arch/arm/dts/imx8-capricorn-cxg3.dts
new file mode 100644
index 0000000..2f85975
--- /dev/null
+++ b/arch/arm/dts/imx8-capricorn-cxg3.dts
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+#include "imx8-capricorn.dtsi"
+
+/ {
+ model = "Siemens CXG3";
+
+ leds_default: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ run {
+ label = "run";
+ gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ flt {
+ label = "flt";
+ gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ svc {
+ label = "svc";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ com1_tx {
+ label = "com1-tx";
+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ com1_rx {
+ label = "com1-rx";
+ gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ com2_tx {
+ label = "com2-tx";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ com2_rx {
+ label = "com2-rx";
+ gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ cloud {
+ label = "cloud";
+ gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ wlan {
+ label = "wlan";
+ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ apps {
+ label = "apps";
+ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ dbg2 {
+ label = "dbg2";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ dbg3 {
+ label = "dbg3";
+ gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ dbg4 {
+ label = "dbg4";
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ muxcgrp: imx8qxp-som {
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021
+ SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021
+ SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021
+ SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021
+ SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021
+ SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021
+ SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021
+ SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021
+ SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021
+ SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021
+ SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021
+ SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
+ SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021
+ >;
+ };
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8-capricorn-u-boot.dtsi b/arch/arm/dts/imx8-capricorn-u-boot.dtsi
new file mode 100644
index 0000000..ad5309b
--- /dev/null
+++ b/arch/arm/dts/imx8-capricorn-u-boot.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+#include "imx8qxp-u-boot.dtsi"
+
+&{/imx8qx-pm} {
+ bootph-all;
+};
+
+&A35_0 {
+ bootph-all;
+};
+
+&mu {
+ bootph-all;
+};
+
+&clk {
+ bootph-all;
+};
+
+&iomuxc {
+ bootph-all;
+};
+
+&pd_lsio {
+ bootph-all;
+};
+
+&pd_lsio_gpio0 {
+ bootph-all;
+};
+
+&pd_lsio_gpio1 {
+ bootph-all;
+};
+
+&pd_lsio_gpio2 {
+ bootph-all;
+};
+
+&pd_lsio_gpio3 {
+ bootph-all;
+};
+
+&pd_lsio_gpio4 {
+ bootph-all;
+};
+
+&pd_lsio_gpio5 {
+ bootph-all;
+};
+
+&pd_lsio_gpio6 {
+ bootph-all;
+};
+
+&pd_lsio_gpio7 {
+ bootph-all;
+};
+
+&pd_dma {
+ bootph-all;
+};
+
+&pd_dma_lpuart0 {
+ bootph-all;
+};
+
+&pd_dma_lpuart2 {
+ bootph-all;
+};
+
+&pd_conn {
+ bootph-all;
+};
+
+&pd_conn_sdch0 {
+ bootph-all;
+};
+
+&pd_conn_sdch1 {
+ bootph-all;
+};
+
+&pd_conn_sdch2 {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&gpio1 {
+ bootph-all;
+};
+
+&gpio2 {
+ bootph-all;
+};
+
+&gpio3 {
+ bootph-all;
+};
+
+&gpio4 {
+ bootph-all;
+};
+
+&gpio5 {
+ bootph-all;
+};
+
+&gpio6 {
+ bootph-all;
+};
+
+&gpio7 {
+ bootph-all;
+};
+
+&lpuart0 {
+ bootph-all;
+};
+
+&lpuart2 {
+ bootph-all;
+};
+
+&usdhc1 {
+ bootph-all;
+};
+
+&usdhc2 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi
similarity index 64%
rename from arch/arm/dts/imx8qxp-capricorn.dtsi
rename to arch/arm/dts/imx8-capricorn.dtsi
index db5653e..3734a9d 100644
--- a/arch/arm/dts/imx8qxp-capricorn.dtsi
+++ b/arch/arm/dts/imx8-capricorn.dtsi
@@ -9,124 +9,25 @@
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
-#include "imx8qxp-capricorn-u-boot.dtsi"
+#include "imx8-capricorn-u-boot.dtsi"
/ {
- model = "Siemens Giedi";
- compatible = "siemens,capricorn", "fsl,imx8qxp";
-
chosen {
bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
stdout-path = &lpuart2;
};
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- run {
- label = "run";
- gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- flt {
- label = "flt";
- gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- svc {
- label = "svc";
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- com1_tx {
- label = "com1-tx";
- gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- com1_rx {
- label = "com1-rx";
- gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- com2_tx {
- label = "com2-tx";
- gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- com2_rx {
- label = "com2-rx";
- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- cloud {
- label = "cloud";
- gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- wlan {
- label = "wlan";
- gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- dbg1 {
- label = "dbg1";
- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- dbg2 {
- label = "dbg2";
- gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- dbg3 {
- label = "dbg3";
- gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- dbg4 {
- label = "dbg4";
- gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
+ /* create device for u-boot wdt command */
+ scu-wdt {
+ compatible = "siemens,scu-wdt";
};
+
};
&iomuxc {
pinctrl-names = "default";
muxcgrp: imx8qxp-som {
- pinctrl_gpio_leds: gpioledsgrp {
- fsl,pins = <
- SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021
- SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021
- SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021
- SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021
- SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021
- SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021
- SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021
- SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021
- SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021
- SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021
- SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021
- SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
- SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021
- >;
- };
-
pinctrl_lpi2c0: lpi2c0grp {
fsl,pins = <
SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020
diff --git a/arch/arm/dts/imx8-deneb.dts b/arch/arm/dts/imx8-deneb.dts
deleted file mode 100644
index 04c764a..0000000
--- a/arch/arm/dts/imx8-deneb.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2019 Siemens AG
- */
-
-#include "imx8qxp-capricorn.dtsi"
-
-/ {
- model = "Siemens Deneb";
-};
diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts
deleted file mode 100644
index 0dbfef2..0000000
--- a/arch/arm/dts/imx8-giedi.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2019 Siemens AG
- */
-
-#include "imx8qxp-capricorn.dtsi"
-
-/ {
- model = "Siemens Giedi";
-};
diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
index a235e08..3a4f7d0 100644
--- a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
@@ -16,6 +16,12 @@
dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
};
+ clk_pcie100: clk-pcie100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@@ -35,6 +41,15 @@
bootph-pre-ram;
};
+&pcie_phy {
+ clocks = <&clk_pcie100>;
+};
+
+&pcie0 {
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk_pcie100>;
+};
+
&pinctrl_hog_sbc {
bootph-pre-ram;
};
@@ -77,6 +92,7 @@
&gpio2 {
bootph-pre-ram;
+ bootph-some-ram;
dsi-reset-hog {
bootph-pre-ram;
@@ -144,8 +160,17 @@
bootph-pre-ram;
};
+&usbmisc1 {
+ bootph-pre-ram;
+};
+
+&usbphynop1 {
+ bootph-pre-ram;
+};
+
&usbotg1 {
dr_mode = "peripheral";
+ bootph-pre-ram;
};
&usdhc2 {
diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
index 516e52e..512dbc9 100644
--- a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
@@ -14,6 +14,10 @@
};
};
+&pinctrl_i2c1 {
+ bootph-pre-ram;
+};
+
&pinctrl_uart3 {
bootph-pre-ram;
};
@@ -54,6 +58,10 @@
bootph-pre-ram;
};
+&i2c1 {
+ bootph-pre-ram;
+};
+
&uart3 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
index 805b5f5..1e82e71 100644
--- a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
@@ -64,6 +64,7 @@
&gpio3 {
bootph-pre-ram;
+ bootph-some-ram;
bl-enable-hog {
bootph-pre-ram;
@@ -92,6 +93,7 @@
&gpio4 {
bootph-pre-ram;
+ bootph-some-ram;
dsi-reset-hog {
bootph-pre-ram;
diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
index c065fb8..546490a 100644
--- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
@@ -9,6 +9,8 @@
aliases {
eeprom0 = &eeprom0;
eeprom1 = &eeprom1;
+ eeprom0wl = &eeprom0wl;
+ eeprom1wl = &eeprom1wl;
mmc0 = &usdhc2; /* MicroSD */
mmc1 = &usdhc3; /* eMMC */
mmc2 = &usdhc1; /* SDIO */
diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
deleted file mode 100644
index cba5618..0000000
--- a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2019 Siemens AG
- */
-
-#include "imx8qxp-u-boot.dtsi"
-
-&{/imx8qx-pm} {
-
- bootph-pre-ram;
-};
-
-&mu {
- bootph-pre-ram;
-};
-
-&clk {
- bootph-pre-ram;
-};
-
-&iomuxc {
- bootph-pre-ram;
-};
-
-&pd_lsio {
- bootph-pre-ram;
-};
-
-&pd_lsio_gpio0 {
- bootph-pre-ram;
-};
-
-&pd_lsio_gpio1 {
- bootph-pre-ram;
-};
-
-&pd_lsio_gpio2 {
- bootph-pre-ram;
-};
-
-&pd_lsio_gpio3 {
- bootph-pre-ram;
-};
-
-&pd_lsio_gpio4 {
- bootph-pre-ram;
-};
-
-&pd_lsio_gpio5 {
- bootph-pre-ram;
-};
-
-&pd_lsio_gpio6 {
- bootph-pre-ram;
-};
-
-&pd_lsio_gpio7 {
- bootph-pre-ram;
-};
-
-&pd_dma {
- bootph-pre-ram;
-};
-
-&pd_dma_lpuart0 {
- bootph-pre-ram;
-};
-
-&pd_dma_lpuart2 {
- bootph-pre-ram;
-};
-
-&pd_conn {
- bootph-pre-ram;
-};
-
-&pd_conn_sdch0 {
- bootph-pre-ram;
-};
-
-&pd_conn_sdch1 {
- bootph-pre-ram;
-};
-
-&pd_conn_sdch2 {
- bootph-pre-ram;
-};
-
-&gpio0 {
- bootph-pre-ram;
-};
-
-&gpio1 {
- bootph-pre-ram;
-};
-
-&gpio2 {
- bootph-pre-ram;
-};
-
-&gpio3 {
- bootph-pre-ram;
-};
-
-&gpio4 {
- bootph-pre-ram;
-};
-
-&gpio5 {
- bootph-pre-ram;
-};
-
-&gpio6 {
- bootph-pre-ram;
-};
-
-&gpio7 {
- bootph-pre-ram;
-};
-
-&lpuart0 {
- bootph-pre-ram;
-};
-
-&lpuart2 {
- bootph-pre-ram;
-};
-
-&usdhc1 {
- bootph-pre-ram;
-};
-
-&usdhc2 {
- bootph-pre-ram;
-};
diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi
index 62791c3..8058caa 100644
--- a/arch/arm/dts/imx8qxp-u-boot.dtsi
+++ b/arch/arm/dts/imx8qxp-u-boot.dtsi
@@ -120,6 +120,7 @@
};
};
+#ifdef CONFIG_XPL_BUILD
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
@@ -130,4 +131,5 @@
type = "blob-ext";
};
};
+#endif
};
diff --git a/arch/arm/dts/imx91-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx91-11x11-evk-u-boot.dtsi
new file mode 100644
index 0000000..54b4d0a
--- /dev/null
+++ b/arch/arm/dts/imx91-11x11-evk-u-boot.dtsi
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx91-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog3>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&aips1 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&aips2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&aips3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&iomuxc {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_usdhc1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpuart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpi2c2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpi2c3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_lpi2c1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_lpi2c2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_lpi2c3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&fec {
+ compatible = "fsl,imx91-fec", "fsl,imx93-fec", "fsl,imx8mq-fec";
+ phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+ðphy1 {
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+};
+
+&s4muap {
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&clk {
+ bootph-all;
+ bootph-pre-ram;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+ /delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&osc_24m {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&clk_ext1 {
+ bootph-all;
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx91-u-boot.dtsi b/arch/arm/dts/imx91-u-boot.dtsi
new file mode 100644
index 0000000..5b639c9
--- /dev/null
+++ b/arch/arm/dts/imx91-u-boot.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Mathieu Othacehe <m.othacehe@gmail.com>
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&A55_0 {
+ clocks = <&clk IMX93_CLK_A55_SEL>;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ ddr-1d-imem-fw {
+ filename = "lpddr4_imem_1d_v202201.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+
+ ddr-1d-dmem-fw {
+ filename = "lpddr4_dmem_1d_v202201.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+
+ ddr-2d-imem-fw {
+ filename = "lpddr4_imem_2d_v202201.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+
+ ddr-2d-dmem-fw {
+ filename = "lpddr4_dmem_2d_v202201.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x204A0000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ u-boot-container {
+ filename = "u-boot-container.bin";
+
+ mkimage {
+ args = "-n u-boot-container.cfgout -T imx8image -e 0x0";
+
+ blob {
+ filename = "u-boot.bin";
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ filename = "spl.bin";
+ offset = <0x0>;
+ align-size = <0x400>;
+ align = <0x400>;
+ };
+
+ uboot: blob-ext@2 {
+ filename = "u-boot-container.bin";
+ };
+ };
+};
diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
index 6897c91..0c3ca29 100644
--- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
@@ -2,15 +2,22 @@
/*
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Christoph Stoidner <c.stoidner@phytec.de>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
*
* Product homepage:
- * phyBOARD-Segin carrier board is reused for the i.MX93 design.
- * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
+ https://www.phytec.de/produkte/system-on-modules/phycore-imx-91-93/
*/
#include "imx93-u-boot.dtsi"
/ {
+ /*
+ * The phyCORE-i.MX93 u-boot uses the imx93-phyboard-segin.dts as
+ * reference, but does only make use of its SoM (phyCORE) contained
+ * periphery.
+ */
+ model = "PHYTEC phyCORE-i.MX93";
+
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
@@ -139,6 +146,13 @@
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
+ /*
+ * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
+ */
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
};
&usdhc2 {
@@ -215,6 +229,48 @@
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
>;
};
+
+ /*
+ * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
+ * are added to imx93-phycore-som.dtsi
+ */
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ bootph-pre-ram;
+ bootph-some-ram;
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ bootph-pre-ram;
+ bootph-some-ram;
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
+ >;
+ };
};
&lpi2c3 {
@@ -305,4 +361,13 @@
};
};
};
+
+ eeprom@50 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ vcc-supply = <&buck4>;
+ };
};
diff --git a/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
index cbcc7f3..848bc35 100644
--- a/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
@@ -5,13 +5,3 @@
*/
#include "k3-am62-lp-sk-binman.dtsi"
-
-/ {
- chosen {
- tick-timer = &main_timer0;
- };
-};
-
-&main_timer0 {
- clock-frequency = <25000000>;
-};
diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts
index b8e5f49..135e8d4 100644
--- a/arch/arm/dts/k3-am62-r5-lp-sk.dts
+++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts
@@ -12,6 +12,7 @@
/ {
aliases {
+ tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
@@ -72,6 +73,14 @@
};
};
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ clocks-names;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clock-frequency = <25000000>;
+};
+
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
index 63f2eed..31456d2 100644
--- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
@@ -137,6 +137,20 @@
};
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ /*
+ * The GUID is generated dynamically by taking a namespace UUID and hashing
+ * it with the board compatible and fw_image name:
+ * mkeficapsule guidgen k3-am625-r5-phycore-som-2gb.dtb PHYCORE_AM62X_TIBOOT3
+ */
+ image-guid = "C7D64D6D-10B2-54BC-A3BF-06A9DC3653D9";
+ };
+};
+
#endif /* CONFIG_TARGET_PHYCORE_AM62X_R5 */
#ifdef CONFIG_TARGET_PHYCORE_AM62X_A53
@@ -460,4 +474,29 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+&capsule_tispl {
+ efi-capsule {
+ /*
+ * The GUID is generated dynamically by taking a namespace UUID and hashing
+ * it with the board compatible and fw_image name:
+ * mkeficapsule guidgen k3-am625-phyboard-lyra-rdk.dtb PHYCORE_AM62X_SPL
+ */
+ image-guid = "09841C3F-F177-5D57-B1F6-754D92879205";
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ /*
+ * The GUID is generated dynamically by taking a namespace UUID and hashing
+ * it with the board compatible and fw_image name:
+ * mkeficapsule guidgen k3-am625-phyboard-lyra-rdk.dtb PHYCORE_AM62X_UBOOT
+ */
+ image-guid = "D11A9016-515E-503A-8872-3FF65384D0C4";
+ };
+};
+
#endif /* CONFIG_TARGET_PHYCORE_AM62X_A53 */
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index d2dd754..34c501d 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -12,6 +12,7 @@
/ {
aliases {
+ tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
@@ -70,6 +71,14 @@
};
};
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ clocks-names;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clock-frequency = <25000000>;
+};
+
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
index 1fc0d40..487ccf0 100644
--- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
@@ -6,16 +6,6 @@
#include "k3-am625-sk-binman.dtsi"
-/ {
- chosen {
- tick-timer = &main_timer0;
- };
-};
-
-&main_timer0 {
- clock-frequency = <25000000>;
-};
-
&main_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
new file mode 100644
index 0000000..640361e
--- /dev/null
+++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Based on k3-am62a-sk-binman.dtsi
+ *
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_PHYCORE_AM62AX_R5
+
+&rcfg_yaml_tifs {
+ config = "tifs-rm-cfg.yaml";
+};
+
+&binman {
+ tiboot3-am62ax-hs-phycore-som.bin {
+ filename = "tiboot3-am62ax-hs-phycore-som.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+ <&combined_dm_cfg>, <&sysfw_inner_cert>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl>;
+ content-sysfw = <&ti_fs_enc>;
+ content-sysfw-data = <&combined_tifs_cfg>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert>;
+ content-dm-data = <&combined_dm_cfg>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c3a800>;
+ };
+ u_boot_spl: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
+ tiboot3-am62ax-hs-fs-phycore-som.bin {
+ filename = "tiboot3-am62ax-hs-fs-phycore-som.bin";
+ symlink = "tiboot3.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl_fs>;
+ content-sysfw = <&ti_fs_enc_fs>;
+ content-sysfw-data = <&combined_tifs_cfg_fs>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+ content-dm-data = <&combined_dm_cfg_fs>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c3a800>;
+ };
+ u_boot_spl_fs: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc_fs: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert_fs: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg_fs: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
+ tiboot3-am62ax-gp-phycore-som.bin {
+ filename = "tiboot3-am62ax-gp-phycore-som.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+ <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+ combined;
+ dm-data;
+ content-sbl = <&u_boot_spl_unsigned>;
+ load = <0x43c00000>;
+ content-sysfw = <&ti_fs_gp>;
+ load-sysfw = <0x40000>;
+ content-sysfw-data = <&combined_tifs_cfg_gp>;
+ load-sysfw-data = <0x67000>;
+ content-dm-data = <&combined_dm_cfg_gp>;
+ load-dm-data = <0x43c3a800>;
+ sw-rev = <1>;
+ keyfile = "ti-degenerate-key.pem";
+ };
+ u_boot_spl_unsigned: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_gp: ti-fs-gp.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+#endif
+
+#ifdef CONFIG_TARGET_PHYCORE_AM62AX_A53
+
+#define SPL_AM62A7_PHYBOARD_LYRA_DTB "spl/dts/ti/k3-am62a7-phyboard-lyra-rdk.dtb"
+#define AM62A7_PHYBOARD_LYRA_DTB "u-boot.dtb"
+
+&binman {
+ ti-dm {
+ filename = "ti-dm.bin";
+ blob-ext {
+ filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
+ };
+ };
+
+ tifsstub-hs {
+ filename = "tifsstub.bin_hs";
+ ti-secure-rom {
+ content = <&tifsstub_hs_cert>;
+ core = "secure";
+ load = <0x60000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "custMpk.pem";
+ countersign;
+ tifsstub;
+ };
+ tifsstub_hs_cert: tifsstub-hs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_hs_enc: tifsstub-hs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
+ tifsstub-fs {
+ filename = "tifsstub.bin_fs";
+ tifsstub_fs_cert: tifsstub-fs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_fs_enc: tifsstub-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ };
+
+ tifsstub-gp {
+ filename = "tifsstub.bin_gp";
+ ti-secure-rom {
+ content = <&tifsstub_gp>;
+ core = "secure";
+ load = <0x60000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "ti-degenerate-key.pem";
+ tifsstub;
+ };
+ tifsstub_gp: tifsstub-gp.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
+ ti-spl {
+ insert-template = <&ti_spl_template>;
+
+ fit {
+ images {
+ tifsstub-hs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-hs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_hs";
+ };
+ };
+
+ tifsstub-fs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-fs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_fs";
+ };
+ };
+
+ tifsstub-gp {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-gp";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_gp";
+ };
+ };
+ dm {
+ ti-secure {
+ content = <&dm>;
+ keyfile = "custMpk.pem";
+ };
+ dm: ti-dm {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am62a7-phyboard-lyra-rdk";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&spl_am62a7_phyboard_lyra_dtb>;
+ keyfile = "custMpk.pem";
+ };
+ spl_am62a7_phyboard_lyra_dtb: blob-ext {
+ filename = SPL_AM62A7_PHYBOARD_LYRA_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am62a7-phyboard-lyra-rdk";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl",
+ "tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ u-boot {
+ insert-template = <&u_boot_template>;
+
+ fit {
+ images {
+ uboot {
+ description = "U-Boot for AM62Ax board";
+ };
+
+ fdt-0 {
+ description = "k3-am62a7-phyboard-lyra-rdk";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&am62a7_phyboard_lyra_dtb>;
+ keyfile = "custMpk.pem";
+ };
+ am62a7_phyboard_lyra_dtb: blob-ext {
+ filename = AM62A7_PHYBOARD_LYRA_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am62a7-phyboard-lyra-rdk";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ ti-spl_unsigned {
+ insert-template = <&ti_spl_unsigned_template>;
+
+ fit {
+ images {
+ tifsstub-hs {
+ description = "tifsstub";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-hs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_hs";
+ };
+ };
+
+ tifsstub-fs {
+ description = "tifsstub";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-fs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_fs";
+ };
+ };
+
+ tifsstub-gp {
+ description = "tifsstub";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-gp";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_gp";
+ };
+ };
+ dm {
+ ti-dm {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am62a7-phyboard-lyra-rdk";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ spl_am62a7_phyboard_lyra_dtb_unsigned: blob {
+ filename = SPL_AM62A7_PHYBOARD_LYRA_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am62a7-phyboard-lyra-rdk";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl",
+ "tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ u-boot_unsigned {
+ insert-template = <&u_boot_unsigned_template>;
+
+ fit {
+ images {
+ uboot {
+ description = "U-Boot for AM62Ax board";
+ };
+
+ fdt-0 {
+ description = "k3-am62a7-phyboard-lyra-rdk";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename = AM62A7_PHYBOARD_LYRA_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am62a7-phyboard-lyra-rdk";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+#endif
diff --git a/arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsi b/arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsi
new file mode 100644
index 0000000..00330b4
--- /dev/null
+++ b/arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsi
@@ -0,0 +1,2798 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * This file was generated with the
+ * AM62Ax SysConfig DDR Subsystem Register Configuration Tool v0.09.08
+ * Fri Mar 24 2024 11:56:13 GMT-0700 (Pacific Daylight Time)
+ * DDR Type: LPDDR4
+ * F0 = 50MHz F1 = NA F2 = 1866MHz
+ * Density (per channel): 8Gb
+ * Number of Ranks: 1
+ */
+
+#define DDRSS_PLL_FHS_CNT 3
+#define DDRSS_PLL_FREQUENCY_1 933000000
+#define DDRSS_PLL_FREQUENCY_2 933000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x0005B18F
+#define DDRSS_CTL_12_DATA 0x0038EF90
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000E94
+#define DDRSS_CTL_15_DATA 0x0005B18F
+#define DDRSS_CTL_16_DATA 0x0038EF90
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000E94
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00004B4B
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x00000000
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000040C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x00001040
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x00001040
+#define DDRSS_CTL_45_DATA 0x00000000
+#define DDRSS_CTL_46_DATA 0x05000804
+#define DDRSS_CTL_47_DATA 0x00000700
+#define DDRSS_CTL_48_DATA 0x09090004
+#define DDRSS_CTL_49_DATA 0x00000303
+#define DDRSS_CTL_50_DATA 0x00720014
+#define DDRSS_CTL_51_DATA 0x09140050
+#define DDRSS_CTL_52_DATA 0x00004D22
+#define DDRSS_CTL_53_DATA 0x00720014
+#define DDRSS_CTL_54_DATA 0x09140050
+#define DDRSS_CTL_55_DATA 0x09004D22
+#define DDRSS_CTL_56_DATA 0x000A0A09
+#define DDRSS_CTL_57_DATA 0x040006DB
+#define DDRSS_CTL_58_DATA 0x090F2005
+#define DDRSS_CTL_59_DATA 0x00001B13
+#define DDRSS_CTL_60_DATA 0x0E00FFCD
+#define DDRSS_CTL_61_DATA 0x090F200F
+#define DDRSS_CTL_62_DATA 0x00001B13
+#define DDRSS_CTL_63_DATA 0x0E00FFCD
+#define DDRSS_CTL_64_DATA 0x0304200F
+#define DDRSS_CTL_65_DATA 0x04050002
+#define DDRSS_CTL_66_DATA 0x24232423
+#define DDRSS_CTL_67_DATA 0x01010008
+#define DDRSS_CTL_68_DATA 0x04464607
+#define DDRSS_CTL_69_DATA 0x03282803
+#define DDRSS_CTL_70_DATA 0x00002828
+#define DDRSS_CTL_71_DATA 0x00000101
+#define DDRSS_CTL_72_DATA 0x00000000
+#define DDRSS_CTL_73_DATA 0x01000000
+#define DDRSS_CTL_74_DATA 0x000E0803
+#define DDRSS_CTL_75_DATA 0x000000BB
+#define DDRSS_CTL_76_DATA 0x0000020B
+#define DDRSS_CTL_77_DATA 0x00001C64
+#define DDRSS_CTL_78_DATA 0x0000020B
+#define DDRSS_CTL_79_DATA 0x00001C64
+#define DDRSS_CTL_80_DATA 0x00000005
+#define DDRSS_CTL_81_DATA 0x00000007
+#define DDRSS_CTL_82_DATA 0x00000010
+#define DDRSS_CTL_83_DATA 0x00000106
+#define DDRSS_CTL_84_DATA 0x00000386
+#define DDRSS_CTL_85_DATA 0x00000106
+#define DDRSS_CTL_86_DATA 0x00000386
+#define DDRSS_CTL_87_DATA 0x03004000
+#define DDRSS_CTL_88_DATA 0x00001201
+#define DDRSS_CTL_89_DATA 0x000E0005
+#define DDRSS_CTL_90_DATA 0x2608000E
+#define DDRSS_CTL_91_DATA 0x0A050526
+#define DDRSS_CTL_92_DATA 0x1B0E0A03
+#define DDRSS_CTL_93_DATA 0x1B0E0A04
+#define DDRSS_CTL_94_DATA 0x04010104
+#define DDRSS_CTL_95_DATA 0x00010401
+#define DDRSS_CTL_96_DATA 0x000F000F
+#define DDRSS_CTL_97_DATA 0x02190219
+#define DDRSS_CTL_98_DATA 0x02190219
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x03030000
+#define DDRSS_CTL_101_DATA 0x05050501
+#define DDRSS_CTL_102_DATA 0x04041C04
+#define DDRSS_CTL_103_DATA 0x0E0A0E0A
+#define DDRSS_CTL_104_DATA 0x0A04041C
+#define DDRSS_CTL_105_DATA 0x030E0A0E
+#define DDRSS_CTL_106_DATA 0x00000404
+#define DDRSS_CTL_107_DATA 0x00000301
+#define DDRSS_CTL_108_DATA 0x00000001
+#define DDRSS_CTL_109_DATA 0x00000000
+#define DDRSS_CTL_110_DATA 0x40020100
+#define DDRSS_CTL_111_DATA 0x00038010
+#define DDRSS_CTL_112_DATA 0x00050004
+#define DDRSS_CTL_113_DATA 0x00000004
+#define DDRSS_CTL_114_DATA 0x00040003
+#define DDRSS_CTL_115_DATA 0x00040005
+#define DDRSS_CTL_116_DATA 0x00030000
+#define DDRSS_CTL_117_DATA 0x00050004
+#define DDRSS_CTL_118_DATA 0x00000004
+#define DDRSS_CTL_119_DATA 0x00002EC0
+#define DDRSS_CTL_120_DATA 0x00002EC0
+#define DDRSS_CTL_121_DATA 0x00002EC0
+#define DDRSS_CTL_122_DATA 0x00002EC0
+#define DDRSS_CTL_123_DATA 0x00002EC0
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000051D
+#define DDRSS_CTL_126_DATA 0x00071900
+#define DDRSS_CTL_127_DATA 0x00071900
+#define DDRSS_CTL_128_DATA 0x00071900
+#define DDRSS_CTL_129_DATA 0x00071900
+#define DDRSS_CTL_130_DATA 0x00071900
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x0000C6BC
+#define DDRSS_CTL_133_DATA 0x00071900
+#define DDRSS_CTL_134_DATA 0x00071900
+#define DDRSS_CTL_135_DATA 0x00071900
+#define DDRSS_CTL_136_DATA 0x00071900
+#define DDRSS_CTL_137_DATA 0x00071900
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x0000C6BC
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x00000000
+#define DDRSS_CTL_157_DATA 0x00000000
+#define DDRSS_CTL_158_DATA 0x03050000
+#define DDRSS_CTL_159_DATA 0x040A040A
+#define DDRSS_CTL_160_DATA 0x00000000
+#define DDRSS_CTL_161_DATA 0x08010000
+#define DDRSS_CTL_162_DATA 0x000E0808
+#define DDRSS_CTL_163_DATA 0x01000000
+#define DDRSS_CTL_164_DATA 0x0E080808
+#define DDRSS_CTL_165_DATA 0x00000000
+#define DDRSS_CTL_166_DATA 0x08080801
+#define DDRSS_CTL_167_DATA 0x0000080E
+#define DDRSS_CTL_168_DATA 0x00040003
+#define DDRSS_CTL_169_DATA 0x00000007
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x00000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x01000000
+#define DDRSS_CTL_177_DATA 0x00000000
+#define DDRSS_CTL_178_DATA 0x00001700
+#define DDRSS_CTL_179_DATA 0x0000100E
+#define DDRSS_CTL_180_DATA 0x00000002
+#define DDRSS_CTL_181_DATA 0x00000000
+#define DDRSS_CTL_182_DATA 0x00000001
+#define DDRSS_CTL_183_DATA 0x00000002
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00008000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00008000
+#define DDRSS_CTL_188_DATA 0x00000C00
+#define DDRSS_CTL_189_DATA 0x00008000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x0005000A
+#define DDRSS_CTL_196_DATA 0x0404000D
+#define DDRSS_CTL_197_DATA 0x0000000D
+#define DDRSS_CTL_198_DATA 0x00BB0176
+#define DDRSS_CTL_199_DATA 0x0E0E01D3
+#define DDRSS_CTL_200_DATA 0x000001D3
+#define DDRSS_CTL_201_DATA 0x00BB0176
+#define DDRSS_CTL_202_DATA 0x0E0E01D3
+#define DDRSS_CTL_203_DATA 0x000001D3
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000004
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000064
+#define DDRSS_CTL_212_DATA 0x00000036
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000064
+#define DDRSS_CTL_215_DATA 0x00000036
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000004
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000064
+#define DDRSS_CTL_221_DATA 0x00000036
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000064
+#define DDRSS_CTL_224_DATA 0x00000036
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x000000B1
+#define DDRSS_CTL_229_DATA 0x000000B1
+#define DDRSS_CTL_230_DATA 0x00000031
+#define DDRSS_CTL_231_DATA 0x000000B1
+#define DDRSS_CTL_232_DATA 0x000000B1
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x55005555
+#define DDRSS_CTL_258_DATA 0x00002755
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000027
+#define DDRSS_CTL_262_DATA 0x00000027
+#define DDRSS_CTL_263_DATA 0x00000027
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x0000002B
+#define DDRSS_CTL_267_DATA 0x0000002B
+#define DDRSS_CTL_268_DATA 0x0000002B
+#define DDRSS_CTL_269_DATA 0x0000002B
+#define DDRSS_CTL_270_DATA 0x0000002B
+#define DDRSS_CTL_271_DATA 0x0000002B
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_274_DATA 0x00000016
+#define DDRSS_CTL_275_DATA 0x00000016
+#define DDRSS_CTL_276_DATA 0x00000000
+#define DDRSS_CTL_277_DATA 0x00000016
+#define DDRSS_CTL_278_DATA 0x00000016
+#define DDRSS_CTL_279_DATA 0x00000020
+#define DDRSS_CTL_280_DATA 0x00010000
+#define DDRSS_CTL_281_DATA 0x00000100
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000101
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x00000000
+#define DDRSS_CTL_291_DATA 0x00000000
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x0C181511
+#define DDRSS_CTL_297_DATA 0x00000304
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00000000
+#define DDRSS_CTL_306_DATA 0x00000000
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x00000000
+#define DDRSS_CTL_309_DATA 0x00000000
+#define DDRSS_CTL_310_DATA 0x00000000
+#define DDRSS_CTL_311_DATA 0x00020000
+#define DDRSS_CTL_312_DATA 0x00400100
+#define DDRSS_CTL_313_DATA 0x00080032
+#define DDRSS_CTL_314_DATA 0x01000200
+#define DDRSS_CTL_315_DATA 0x074A0040
+#define DDRSS_CTL_316_DATA 0x00020038
+#define DDRSS_CTL_317_DATA 0x00400100
+#define DDRSS_CTL_318_DATA 0x0038074A
+#define DDRSS_CTL_319_DATA 0x00030000
+#define DDRSS_CTL_320_DATA 0x005E005E
+#define DDRSS_CTL_321_DATA 0x00000100
+#define DDRSS_CTL_322_DATA 0x01010000
+#define DDRSS_CTL_323_DATA 0x00000101
+#define DDRSS_CTL_324_DATA 0x1FFF0000
+#define DDRSS_CTL_325_DATA 0x000FFF00
+#define DDRSS_CTL_326_DATA 0xFFFFFFFF
+#define DDRSS_CTL_327_DATA 0x00FFFF00
+#define DDRSS_CTL_328_DATA 0x0B000000
+#define DDRSS_CTL_329_DATA 0x0001FFFF
+#define DDRSS_CTL_330_DATA 0x01010101
+#define DDRSS_CTL_331_DATA 0x01010101
+#define DDRSS_CTL_332_DATA 0x00000118
+#define DDRSS_CTL_333_DATA 0x00000C01
+#define DDRSS_CTL_334_DATA 0x00040100
+#define DDRSS_CTL_335_DATA 0x00040100
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x01030303
+#define DDRSS_CTL_339_DATA 0x00000001
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x00000000
+#define DDRSS_CTL_372_DATA 0x00000000
+#define DDRSS_CTL_373_DATA 0x00000000
+#define DDRSS_CTL_374_DATA 0x00000000
+#define DDRSS_CTL_375_DATA 0x00000000
+#define DDRSS_CTL_376_DATA 0x00000000
+#define DDRSS_CTL_377_DATA 0x00000000
+#define DDRSS_CTL_378_DATA 0x00000000
+#define DDRSS_CTL_379_DATA 0x00000000
+#define DDRSS_CTL_380_DATA 0x00000000
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x01000101
+#define DDRSS_CTL_384_DATA 0x01010001
+#define DDRSS_CTL_385_DATA 0x00010101
+#define DDRSS_CTL_386_DATA 0x01090903
+#define DDRSS_CTL_387_DATA 0x05020201
+#define DDRSS_CTL_388_DATA 0x0E081B1B
+#define DDRSS_CTL_389_DATA 0x0008030E
+#define DDRSS_CTL_390_DATA 0x0B12030E
+#define DDRSS_CTL_391_DATA 0x0B120314
+#define DDRSS_CTL_392_DATA 0x12120814
+#define DDRSS_CTL_393_DATA 0x01000000
+#define DDRSS_CTL_394_DATA 0x07030701
+#define DDRSS_CTL_395_DATA 0x04000103
+#define DDRSS_CTL_396_DATA 0x1B000004
+#define DDRSS_CTL_397_DATA 0x00000176
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00000200
+#define DDRSS_CTL_400_DATA 0x00000200
+#define DDRSS_CTL_401_DATA 0x00000200
+#define DDRSS_CTL_402_DATA 0x00000693
+#define DDRSS_CTL_403_DATA 0x00000E9C
+#define DDRSS_CTL_404_DATA 0x03050202
+#define DDRSS_CTL_405_DATA 0x37200201
+#define DDRSS_CTL_406_DATA 0x000038C8
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00000200
+#define DDRSS_CTL_409_DATA 0x00000200
+#define DDRSS_CTL_410_DATA 0x00000200
+#define DDRSS_CTL_411_DATA 0x0000FF84
+#define DDRSS_CTL_412_DATA 0x000237D0
+#define DDRSS_CTL_413_DATA 0x111F0402
+#define DDRSS_CTL_414_DATA 0x37200C0D
+#define DDRSS_CTL_415_DATA 0x000038C8
+#define DDRSS_CTL_416_DATA 0x00000200
+#define DDRSS_CTL_417_DATA 0x00000200
+#define DDRSS_CTL_418_DATA 0x00000200
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x0000FF84
+#define DDRSS_CTL_421_DATA 0x000237D0
+#define DDRSS_CTL_422_DATA 0x111F0402
+#define DDRSS_CTL_423_DATA 0x00200C0D
+#define DDRSS_CTL_424_DATA 0x00000000
+#define DDRSS_CTL_425_DATA 0x02000A00
+#define DDRSS_CTL_426_DATA 0x00050003
+#define DDRSS_CTL_427_DATA 0x00010101
+#define DDRSS_CTL_428_DATA 0x00010101
+#define DDRSS_CTL_429_DATA 0x00010001
+#define DDRSS_CTL_430_DATA 0x00000101
+#define DDRSS_CTL_431_DATA 0x02000201
+#define DDRSS_CTL_432_DATA 0x02010000
+#define DDRSS_CTL_433_DATA 0x06000200
+#define DDRSS_CTL_434_DATA 0x00002222
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x00050001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x00000000
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x01010000
+#define DDRSS_PI_27_DATA 0x0A000100
+#define DDRSS_PI_28_DATA 0x00000028
+#define DDRSS_PI_29_DATA 0x05000000
+#define DDRSS_PI_30_DATA 0x00320000
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x01010102
+#define DDRSS_PI_34_DATA 0x00000000
+#define DDRSS_PI_35_DATA 0x00000000
+#define DDRSS_PI_36_DATA 0x00000000
+#define DDRSS_PI_37_DATA 0x00000001
+#define DDRSS_PI_38_DATA 0x000000AA
+#define DDRSS_PI_39_DATA 0x00000055
+#define DDRSS_PI_40_DATA 0x000000B5
+#define DDRSS_PI_41_DATA 0x0000004A
+#define DDRSS_PI_42_DATA 0x00000056
+#define DDRSS_PI_43_DATA 0x000000A9
+#define DDRSS_PI_44_DATA 0x000000A9
+#define DDRSS_PI_45_DATA 0x000000B5
+#define DDRSS_PI_46_DATA 0x00000000
+#define DDRSS_PI_47_DATA 0x00000000
+#define DDRSS_PI_48_DATA 0x00050500
+#define DDRSS_PI_49_DATA 0x0000001A
+#define DDRSS_PI_50_DATA 0x000007D0
+#define DDRSS_PI_51_DATA 0x00000300
+#define DDRSS_PI_52_DATA 0x00000000
+#define DDRSS_PI_53_DATA 0x00000000
+#define DDRSS_PI_54_DATA 0x01000000
+#define DDRSS_PI_55_DATA 0x00010101
+#define DDRSS_PI_56_DATA 0x01000000
+#define DDRSS_PI_57_DATA 0x03000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00001705
+#define DDRSS_PI_60_DATA 0x00000000
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x00000000
+#define DDRSS_PI_63_DATA 0x0A0A140A
+#define DDRSS_PI_64_DATA 0x10020101
+#define DDRSS_PI_65_DATA 0x01000210
+#define DDRSS_PI_66_DATA 0x05000404
+#define DDRSS_PI_67_DATA 0x00010001
+#define DDRSS_PI_68_DATA 0x0001000E
+#define DDRSS_PI_69_DATA 0x01010500
+#define DDRSS_PI_70_DATA 0x00010000
+#define DDRSS_PI_71_DATA 0x00000034
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x0000FFFF
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x00000000
+#define DDRSS_PI_77_DATA 0x00000000
+#define DDRSS_PI_78_DATA 0x00000000
+#define DDRSS_PI_79_DATA 0x01000000
+#define DDRSS_PI_80_DATA 0x01010001
+#define DDRSS_PI_81_DATA 0x02000008
+#define DDRSS_PI_82_DATA 0x01000200
+#define DDRSS_PI_83_DATA 0x00000100
+#define DDRSS_PI_84_DATA 0x02000100
+#define DDRSS_PI_85_DATA 0x02000200
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000000
+#define DDRSS_PI_92_DATA 0x00000000
+#define DDRSS_PI_93_DATA 0x00000000
+#define DDRSS_PI_94_DATA 0x00000000
+#define DDRSS_PI_95_DATA 0x00000000
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00000000
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x01000400
+#define DDRSS_PI_100_DATA 0x0E0D0F10
+#define DDRSS_PI_101_DATA 0x080A1413
+#define DDRSS_PI_102_DATA 0x01000009
+#define DDRSS_PI_103_DATA 0x00000302
+#define DDRSS_PI_104_DATA 0x00000008
+#define DDRSS_PI_105_DATA 0x08000000
+#define DDRSS_PI_106_DATA 0x00000100
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x0000AA00
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00010000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000000
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00000000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00000008
+#define DDRSS_PI_137_DATA 0x00000000
+#define DDRSS_PI_138_DATA 0x00000000
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x00000000
+#define DDRSS_PI_145_DATA 0x00010000
+#define DDRSS_PI_146_DATA 0x00000000
+#define DDRSS_PI_147_DATA 0x00000000
+#define DDRSS_PI_148_DATA 0x0000000A
+#define DDRSS_PI_149_DATA 0x000186A0
+#define DDRSS_PI_150_DATA 0x00000100
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00000000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x01000000
+#define DDRSS_PI_157_DATA 0x00010003
+#define DDRSS_PI_158_DATA 0x02000101
+#define DDRSS_PI_159_DATA 0x01030001
+#define DDRSS_PI_160_DATA 0x00010400
+#define DDRSS_PI_161_DATA 0x06000105
+#define DDRSS_PI_162_DATA 0x01070001
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000000
+#define DDRSS_PI_165_DATA 0x00000000
+#define DDRSS_PI_166_DATA 0x00010001
+#define DDRSS_PI_167_DATA 0x00000000
+#define DDRSS_PI_168_DATA 0x00000000
+#define DDRSS_PI_169_DATA 0x00000000
+#define DDRSS_PI_170_DATA 0x00000000
+#define DDRSS_PI_171_DATA 0x00010000
+#define DDRSS_PI_172_DATA 0x00000004
+#define DDRSS_PI_173_DATA 0x00000000
+#define DDRSS_PI_174_DATA 0x00010000
+#define DDRSS_PI_175_DATA 0x00000000
+#define DDRSS_PI_176_DATA 0x00080000
+#define DDRSS_PI_177_DATA 0x01180118
+#define DDRSS_PI_178_DATA 0x00262601
+#define DDRSS_PI_179_DATA 0x00000034
+#define DDRSS_PI_180_DATA 0x0000005E
+#define DDRSS_PI_181_DATA 0x0002005E
+#define DDRSS_PI_182_DATA 0x02000200
+#define DDRSS_PI_183_DATA 0x00000004
+#define DDRSS_PI_184_DATA 0x0000100C
+#define DDRSS_PI_185_DATA 0x00104000
+#define DDRSS_PI_186_DATA 0x00400000
+#define DDRSS_PI_187_DATA 0x0000000E
+#define DDRSS_PI_188_DATA 0x000000BB
+#define DDRSS_PI_189_DATA 0x0000020B
+#define DDRSS_PI_190_DATA 0x00001C64
+#define DDRSS_PI_191_DATA 0x0000020B
+#define DDRSS_PI_192_DATA 0x04001C64
+#define DDRSS_PI_193_DATA 0x01010404
+#define DDRSS_PI_194_DATA 0x00001501
+#define DDRSS_PI_195_DATA 0x00270027
+#define DDRSS_PI_196_DATA 0x01000100
+#define DDRSS_PI_197_DATA 0x00000100
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x05090903
+#define DDRSS_PI_200_DATA 0x01011B1B
+#define DDRSS_PI_201_DATA 0x01010101
+#define DDRSS_PI_202_DATA 0x000C0C0A
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x04000000
+#define DDRSS_PI_206_DATA 0x0C021212
+#define DDRSS_PI_207_DATA 0x0404020C
+#define DDRSS_PI_208_DATA 0x00090031
+#define DDRSS_PI_209_DATA 0x001B0043
+#define DDRSS_PI_210_DATA 0x001B0043
+#define DDRSS_PI_211_DATA 0x01010101
+#define DDRSS_PI_212_DATA 0x0003000D
+#define DDRSS_PI_213_DATA 0x000301D3
+#define DDRSS_PI_214_DATA 0x010001D3
+#define DDRSS_PI_215_DATA 0x000E000E
+#define DDRSS_PI_216_DATA 0x01D40100
+#define DDRSS_PI_217_DATA 0x010001D4
+#define DDRSS_PI_218_DATA 0x01D401D4
+#define DDRSS_PI_219_DATA 0x32103200
+#define DDRSS_PI_220_DATA 0x01013210
+#define DDRSS_PI_221_DATA 0x0A070601
+#define DDRSS_PI_222_DATA 0x1C11090D
+#define DDRSS_PI_223_DATA 0x1C110913
+#define DDRSS_PI_224_DATA 0x000C0013
+#define DDRSS_PI_225_DATA 0x00001000
+#define DDRSS_PI_226_DATA 0x00000C00
+#define DDRSS_PI_227_DATA 0x00001000
+#define DDRSS_PI_228_DATA 0x00000C00
+#define DDRSS_PI_229_DATA 0x02001000
+#define DDRSS_PI_230_DATA 0x0021000D
+#define DDRSS_PI_231_DATA 0x002101D3
+#define DDRSS_PI_232_DATA 0x000001D3
+#define DDRSS_PI_233_DATA 0x00001900
+#define DDRSS_PI_234_DATA 0x32000056
+#define DDRSS_PI_235_DATA 0x06000101
+#define DDRSS_PI_236_DATA 0x00250204
+#define DDRSS_PI_237_DATA 0x3212005A
+#define DDRSS_PI_238_DATA 0x17000101
+#define DDRSS_PI_239_DATA 0x00250C12
+#define DDRSS_PI_240_DATA 0x3212005A
+#define DDRSS_PI_241_DATA 0x17000101
+#define DDRSS_PI_242_DATA 0x00000C12
+#define DDRSS_PI_243_DATA 0x05030900
+#define DDRSS_PI_244_DATA 0x00040900
+#define DDRSS_PI_245_DATA 0x0000062B
+#define DDRSS_PI_246_DATA 0x20010004
+#define DDRSS_PI_247_DATA 0x0A0A0A03
+#define DDRSS_PI_248_DATA 0x280F0000
+#define DDRSS_PI_249_DATA 0x24090023
+#define DDRSS_PI_250_DATA 0x0000E638
+#define DDRSS_PI_251_DATA 0x20070050
+#define DDRSS_PI_252_DATA 0x1B131B1C
+#define DDRSS_PI_253_DATA 0x280F0000
+#define DDRSS_PI_254_DATA 0x24090023
+#define DDRSS_PI_255_DATA 0x0000E638
+#define DDRSS_PI_256_DATA 0x20070050
+#define DDRSS_PI_257_DATA 0x1B131B1C
+#define DDRSS_PI_258_DATA 0x00000000
+#define DDRSS_PI_259_DATA 0x00000176
+#define DDRSS_PI_260_DATA 0x00000E9C
+#define DDRSS_PI_261_DATA 0x000038C8
+#define DDRSS_PI_262_DATA 0x000237D0
+#define DDRSS_PI_263_DATA 0x000038C8
+#define DDRSS_PI_264_DATA 0x000237D0
+#define DDRSS_PI_265_DATA 0x0219000F
+#define DDRSS_PI_266_DATA 0x03030219
+#define DDRSS_PI_267_DATA 0x00000003
+#define DDRSS_PI_268_DATA 0x00000000
+#define DDRSS_PI_269_DATA 0x0A040503
+#define DDRSS_PI_270_DATA 0x00000A04
+#define DDRSS_PI_271_DATA 0x00002710
+#define DDRSS_PI_272_DATA 0x000186A0
+#define DDRSS_PI_273_DATA 0x00000005
+#define DDRSS_PI_274_DATA 0x00000064
+#define DDRSS_PI_275_DATA 0x0000000F
+#define DDRSS_PI_276_DATA 0x0005B18F
+#define DDRSS_PI_277_DATA 0x000186A0
+#define DDRSS_PI_278_DATA 0x00000005
+#define DDRSS_PI_279_DATA 0x00000E94
+#define DDRSS_PI_280_DATA 0x00000219
+#define DDRSS_PI_281_DATA 0x0005B18F
+#define DDRSS_PI_282_DATA 0x000186A0
+#define DDRSS_PI_283_DATA 0x00000005
+#define DDRSS_PI_284_DATA 0x00000E94
+#define DDRSS_PI_285_DATA 0x01000219
+#define DDRSS_PI_286_DATA 0x00320040
+#define DDRSS_PI_287_DATA 0x00010008
+#define DDRSS_PI_288_DATA 0x074A0040
+#define DDRSS_PI_289_DATA 0x00010038
+#define DDRSS_PI_290_DATA 0x074A0040
+#define DDRSS_PI_291_DATA 0x00000338
+#define DDRSS_PI_292_DATA 0x0028005D
+#define DDRSS_PI_293_DATA 0x03040404
+#define DDRSS_PI_294_DATA 0x00000303
+#define DDRSS_PI_295_DATA 0x01010000
+#define DDRSS_PI_296_DATA 0x04040202
+#define DDRSS_PI_297_DATA 0x67670808
+#define DDRSS_PI_298_DATA 0x67676767
+#define DDRSS_PI_299_DATA 0x67676767
+#define DDRSS_PI_300_DATA 0x67676767
+#define DDRSS_PI_301_DATA 0x00006767
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x55000000
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x3C00005A
+#define DDRSS_PI_309_DATA 0x00005500
+#define DDRSS_PI_310_DATA 0x00005A00
+#define DDRSS_PI_311_DATA 0x0055003C
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x3C00005A
+#define DDRSS_PI_314_DATA 0x00005500
+#define DDRSS_PI_315_DATA 0x00005A00
+#define DDRSS_PI_316_DATA 0x1716153C
+#define DDRSS_PI_317_DATA 0x13121118
+#define DDRSS_PI_318_DATA 0x06050414
+#define DDRSS_PI_319_DATA 0x02010007
+#define DDRSS_PI_320_DATA 0x00000003
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000000
+#define DDRSS_PI_323_DATA 0x01000000
+#define DDRSS_PI_324_DATA 0x04020201
+#define DDRSS_PI_325_DATA 0x00080804
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000004
+#define DDRSS_PI_330_DATA 0x00000000
+#define DDRSS_PI_331_DATA 0x00000031
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000000
+#define DDRSS_PI_335_DATA 0x20002B27
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x00000064
+#define DDRSS_PI_338_DATA 0x00000036
+#define DDRSS_PI_339_DATA 0x000000B1
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x55000000
+#define DDRSS_PI_343_DATA 0x20162B27
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PI_345_DATA 0x00000064
+#define DDRSS_PI_346_DATA 0x00000036
+#define DDRSS_PI_347_DATA 0x000000B1
+#define DDRSS_PI_348_DATA 0x00000000
+#define DDRSS_PI_349_DATA 0x00000000
+#define DDRSS_PI_350_DATA 0x55000000
+#define DDRSS_PI_351_DATA 0x20162B27
+#define DDRSS_PI_352_DATA 0x00000000
+#define DDRSS_PI_353_DATA 0x00000004
+#define DDRSS_PI_354_DATA 0x00000000
+#define DDRSS_PI_355_DATA 0x00000031
+#define DDRSS_PI_356_DATA 0x00000000
+#define DDRSS_PI_357_DATA 0x00000000
+#define DDRSS_PI_358_DATA 0x00000000
+#define DDRSS_PI_359_DATA 0x20002B27
+#define DDRSS_PI_360_DATA 0x00000000
+#define DDRSS_PI_361_DATA 0x00000064
+#define DDRSS_PI_362_DATA 0x00000036
+#define DDRSS_PI_363_DATA 0x000000B1
+#define DDRSS_PI_364_DATA 0x00000000
+#define DDRSS_PI_365_DATA 0x00000000
+#define DDRSS_PI_366_DATA 0x55000000
+#define DDRSS_PI_367_DATA 0x20162B27
+#define DDRSS_PI_368_DATA 0x00000000
+#define DDRSS_PI_369_DATA 0x00000064
+#define DDRSS_PI_370_DATA 0x00000036
+#define DDRSS_PI_371_DATA 0x000000B1
+#define DDRSS_PI_372_DATA 0x00000000
+#define DDRSS_PI_373_DATA 0x00000000
+#define DDRSS_PI_374_DATA 0x55000000
+#define DDRSS_PI_375_DATA 0x20162B27
+#define DDRSS_PI_376_DATA 0x00000000
+#define DDRSS_PI_377_DATA 0x00000004
+#define DDRSS_PI_378_DATA 0x00000000
+#define DDRSS_PI_379_DATA 0x00000031
+#define DDRSS_PI_380_DATA 0x00000000
+#define DDRSS_PI_381_DATA 0x00000000
+#define DDRSS_PI_382_DATA 0x00000000
+#define DDRSS_PI_383_DATA 0x20002B27
+#define DDRSS_PI_384_DATA 0x00000000
+#define DDRSS_PI_385_DATA 0x00000064
+#define DDRSS_PI_386_DATA 0x00000036
+#define DDRSS_PI_387_DATA 0x000000B1
+#define DDRSS_PI_388_DATA 0x00000000
+#define DDRSS_PI_389_DATA 0x00000000
+#define DDRSS_PI_390_DATA 0x55000000
+#define DDRSS_PI_391_DATA 0x20162B27
+#define DDRSS_PI_392_DATA 0x00000000
+#define DDRSS_PI_393_DATA 0x00000064
+#define DDRSS_PI_394_DATA 0x00000036
+#define DDRSS_PI_395_DATA 0x000000B1
+#define DDRSS_PI_396_DATA 0x00000000
+#define DDRSS_PI_397_DATA 0x00000000
+#define DDRSS_PI_398_DATA 0x55000000
+#define DDRSS_PI_399_DATA 0x20162B27
+#define DDRSS_PI_400_DATA 0x00000000
+#define DDRSS_PI_401_DATA 0x00000004
+#define DDRSS_PI_402_DATA 0x00000000
+#define DDRSS_PI_403_DATA 0x00000031
+#define DDRSS_PI_404_DATA 0x00000000
+#define DDRSS_PI_405_DATA 0x00000000
+#define DDRSS_PI_406_DATA 0x00000000
+#define DDRSS_PI_407_DATA 0x20002B27
+#define DDRSS_PI_408_DATA 0x00000000
+#define DDRSS_PI_409_DATA 0x00000064
+#define DDRSS_PI_410_DATA 0x00000036
+#define DDRSS_PI_411_DATA 0x000000B1
+#define DDRSS_PI_412_DATA 0x00000000
+#define DDRSS_PI_413_DATA 0x00000000
+#define DDRSS_PI_414_DATA 0x55000000
+#define DDRSS_PI_415_DATA 0x20162B27
+#define DDRSS_PI_416_DATA 0x00000000
+#define DDRSS_PI_417_DATA 0x00000064
+#define DDRSS_PI_418_DATA 0x00000036
+#define DDRSS_PI_419_DATA 0x000000B1
+#define DDRSS_PI_420_DATA 0x00000000
+#define DDRSS_PI_421_DATA 0x00000000
+#define DDRSS_PI_422_DATA 0x55000000
+#define DDRSS_PI_423_DATA 0x20162B27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01030000
+#define DDRSS_PHY_6_DATA 0x00010000
+#define DDRSS_PHY_7_DATA 0x01030004
+#define DDRSS_PHY_8_DATA 0x01000000
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x00000000
+#define DDRSS_PHY_12_DATA 0x01010000
+#define DDRSS_PHY_13_DATA 0x00010000
+#define DDRSS_PHY_14_DATA 0x00C00001
+#define DDRSS_PHY_15_DATA 0x00CC0008
+#define DDRSS_PHY_16_DATA 0x00660601
+#define DDRSS_PHY_17_DATA 0x00000003
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x00000001
+#define DDRSS_PHY_20_DATA 0x0000AAAA
+#define DDRSS_PHY_21_DATA 0x00005555
+#define DDRSS_PHY_22_DATA 0x0000B5B5
+#define DDRSS_PHY_23_DATA 0x00004A4A
+#define DDRSS_PHY_24_DATA 0x00005656
+#define DDRSS_PHY_25_DATA 0x0000A9A9
+#define DDRSS_PHY_26_DATA 0x0000B7B7
+#define DDRSS_PHY_27_DATA 0x00004848
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x00000000
+#define DDRSS_PHY_30_DATA 0x08000000
+#define DDRSS_PHY_31_DATA 0x0F000008
+#define DDRSS_PHY_32_DATA 0x00000F0F
+#define DDRSS_PHY_33_DATA 0x00E4E400
+#define DDRSS_PHY_34_DATA 0x00071020
+#define DDRSS_PHY_35_DATA 0x000C0020
+#define DDRSS_PHY_36_DATA 0x00062000
+#define DDRSS_PHY_37_DATA 0x00000000
+#define DDRSS_PHY_38_DATA 0x55555555
+#define DDRSS_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS_PHY_40_DATA 0x55555555
+#define DDRSS_PHY_41_DATA 0xAAAAAAAA
+#define DDRSS_PHY_42_DATA 0x00005555
+#define DDRSS_PHY_43_DATA 0x01000100
+#define DDRSS_PHY_44_DATA 0x00800180
+#define DDRSS_PHY_45_DATA 0x00000001
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000000
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x00000000
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x081F07FF
+#define DDRSS_PHY_75_DATA 0x10200080
+#define DDRSS_PHY_76_DATA 0x00000008
+#define DDRSS_PHY_77_DATA 0x00000401
+#define DDRSS_PHY_78_DATA 0x00000000
+#define DDRSS_PHY_79_DATA 0x01CC0C01
+#define DDRSS_PHY_80_DATA 0x1003CC0C
+#define DDRSS_PHY_81_DATA 0x20000140
+#define DDRSS_PHY_82_DATA 0x07FF0200
+#define DDRSS_PHY_83_DATA 0x0000DD01
+#define DDRSS_PHY_84_DATA 0x00100303
+#define DDRSS_PHY_85_DATA 0x00000000
+#define DDRSS_PHY_86_DATA 0x00000000
+#define DDRSS_PHY_87_DATA 0x00041000
+#define DDRSS_PHY_88_DATA 0x00100010
+#define DDRSS_PHY_89_DATA 0x00100010
+#define DDRSS_PHY_90_DATA 0x00100010
+#define DDRSS_PHY_91_DATA 0x00100010
+#define DDRSS_PHY_92_DATA 0x02040010
+#define DDRSS_PHY_93_DATA 0x00000005
+#define DDRSS_PHY_94_DATA 0x51516042
+#define DDRSS_PHY_95_DATA 0x31C06000
+#define DDRSS_PHY_96_DATA 0x07AB0340
+#define DDRSS_PHY_97_DATA 0x00C0C001
+#define DDRSS_PHY_98_DATA 0x0D000000
+#define DDRSS_PHY_99_DATA 0x000D0C0C
+#define DDRSS_PHY_100_DATA 0x42100010
+#define DDRSS_PHY_101_DATA 0x010C073E
+#define DDRSS_PHY_102_DATA 0x000F0C32
+#define DDRSS_PHY_103_DATA 0x01000140
+#define DDRSS_PHY_104_DATA 0x011E0120
+#define DDRSS_PHY_105_DATA 0x00000C00
+#define DDRSS_PHY_106_DATA 0x000002DD
+#define DDRSS_PHY_107_DATA 0x00030200
+#define DDRSS_PHY_108_DATA 0x02800000
+#define DDRSS_PHY_109_DATA 0x80800000
+#define DDRSS_PHY_110_DATA 0x000D2010
+#define DDRSS_PHY_111_DATA 0x76543210
+#define DDRSS_PHY_112_DATA 0x00000008
+#define DDRSS_PHY_113_DATA 0x045D045D
+#define DDRSS_PHY_114_DATA 0x045D045D
+#define DDRSS_PHY_115_DATA 0x045D045D
+#define DDRSS_PHY_116_DATA 0x045D045D
+#define DDRSS_PHY_117_DATA 0x0000045D
+#define DDRSS_PHY_118_DATA 0x0000A000
+#define DDRSS_PHY_119_DATA 0x00A000A0
+#define DDRSS_PHY_120_DATA 0x00A000A0
+#define DDRSS_PHY_121_DATA 0x00A000A0
+#define DDRSS_PHY_122_DATA 0x00A000A0
+#define DDRSS_PHY_123_DATA 0x00A000A0
+#define DDRSS_PHY_124_DATA 0x00A000A0
+#define DDRSS_PHY_125_DATA 0x00A000A0
+#define DDRSS_PHY_126_DATA 0x00A000A0
+#define DDRSS_PHY_127_DATA 0x00B200A0
+#define DDRSS_PHY_128_DATA 0x01000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00080200
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x20202020
+#define DDRSS_PHY_134_DATA 0x20202020
+#define DDRSS_PHY_135_DATA 0xF0F02020
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01030000
+#define DDRSS_PHY_262_DATA 0x00010000
+#define DDRSS_PHY_263_DATA 0x01030004
+#define DDRSS_PHY_264_DATA 0x01000000
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x00000000
+#define DDRSS_PHY_268_DATA 0x01010000
+#define DDRSS_PHY_269_DATA 0x00010000
+#define DDRSS_PHY_270_DATA 0x00C00001
+#define DDRSS_PHY_271_DATA 0x00CC0008
+#define DDRSS_PHY_272_DATA 0x00660601
+#define DDRSS_PHY_273_DATA 0x00000003
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x00000001
+#define DDRSS_PHY_276_DATA 0x0000AAAA
+#define DDRSS_PHY_277_DATA 0x00005555
+#define DDRSS_PHY_278_DATA 0x0000B5B5
+#define DDRSS_PHY_279_DATA 0x00004A4A
+#define DDRSS_PHY_280_DATA 0x00005656
+#define DDRSS_PHY_281_DATA 0x0000A9A9
+#define DDRSS_PHY_282_DATA 0x0000B7B7
+#define DDRSS_PHY_283_DATA 0x00004848
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x00000000
+#define DDRSS_PHY_286_DATA 0x08000000
+#define DDRSS_PHY_287_DATA 0x0F000008
+#define DDRSS_PHY_288_DATA 0x00000F0F
+#define DDRSS_PHY_289_DATA 0x00E4E400
+#define DDRSS_PHY_290_DATA 0x00071020
+#define DDRSS_PHY_291_DATA 0x000C0020
+#define DDRSS_PHY_292_DATA 0x00062000
+#define DDRSS_PHY_293_DATA 0x00000000
+#define DDRSS_PHY_294_DATA 0x55555555
+#define DDRSS_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS_PHY_296_DATA 0x55555555
+#define DDRSS_PHY_297_DATA 0xAAAAAAAA
+#define DDRSS_PHY_298_DATA 0x00005555
+#define DDRSS_PHY_299_DATA 0x01000100
+#define DDRSS_PHY_300_DATA 0x00800180
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000000
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x00000000
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x081F07FF
+#define DDRSS_PHY_331_DATA 0x10200080
+#define DDRSS_PHY_332_DATA 0x00000008
+#define DDRSS_PHY_333_DATA 0x00000401
+#define DDRSS_PHY_334_DATA 0x00000000
+#define DDRSS_PHY_335_DATA 0x01CC0C01
+#define DDRSS_PHY_336_DATA 0x1003CC0C
+#define DDRSS_PHY_337_DATA 0x20000140
+#define DDRSS_PHY_338_DATA 0x07FF0200
+#define DDRSS_PHY_339_DATA 0x0000DD01
+#define DDRSS_PHY_340_DATA 0x00100303
+#define DDRSS_PHY_341_DATA 0x00000000
+#define DDRSS_PHY_342_DATA 0x00000000
+#define DDRSS_PHY_343_DATA 0x00041000
+#define DDRSS_PHY_344_DATA 0x00100010
+#define DDRSS_PHY_345_DATA 0x00100010
+#define DDRSS_PHY_346_DATA 0x00100010
+#define DDRSS_PHY_347_DATA 0x00100010
+#define DDRSS_PHY_348_DATA 0x02040010
+#define DDRSS_PHY_349_DATA 0x00000005
+#define DDRSS_PHY_350_DATA 0x51516042
+#define DDRSS_PHY_351_DATA 0x31C06000
+#define DDRSS_PHY_352_DATA 0x07AB0340
+#define DDRSS_PHY_353_DATA 0x00C0C001
+#define DDRSS_PHY_354_DATA 0x0D000000
+#define DDRSS_PHY_355_DATA 0x000D0C0C
+#define DDRSS_PHY_356_DATA 0x42100010
+#define DDRSS_PHY_357_DATA 0x010C073E
+#define DDRSS_PHY_358_DATA 0x000F0C32
+#define DDRSS_PHY_359_DATA 0x01000140
+#define DDRSS_PHY_360_DATA 0x011E0120
+#define DDRSS_PHY_361_DATA 0x00000C00
+#define DDRSS_PHY_362_DATA 0x000002DD
+#define DDRSS_PHY_363_DATA 0x00030200
+#define DDRSS_PHY_364_DATA 0x02800000
+#define DDRSS_PHY_365_DATA 0x80800000
+#define DDRSS_PHY_366_DATA 0x000D2010
+#define DDRSS_PHY_367_DATA 0x76543210
+#define DDRSS_PHY_368_DATA 0x00000008
+#define DDRSS_PHY_369_DATA 0x045D045D
+#define DDRSS_PHY_370_DATA 0x045D045D
+#define DDRSS_PHY_371_DATA 0x045D045D
+#define DDRSS_PHY_372_DATA 0x045D045D
+#define DDRSS_PHY_373_DATA 0x0000045D
+#define DDRSS_PHY_374_DATA 0x0000A000
+#define DDRSS_PHY_375_DATA 0x00A000A0
+#define DDRSS_PHY_376_DATA 0x00A000A0
+#define DDRSS_PHY_377_DATA 0x00A000A0
+#define DDRSS_PHY_378_DATA 0x00A000A0
+#define DDRSS_PHY_379_DATA 0x00A000A0
+#define DDRSS_PHY_380_DATA 0x00A000A0
+#define DDRSS_PHY_381_DATA 0x00A000A0
+#define DDRSS_PHY_382_DATA 0x00A000A0
+#define DDRSS_PHY_383_DATA 0x00B200A0
+#define DDRSS_PHY_384_DATA 0x01000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00080200
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x20202020
+#define DDRSS_PHY_390_DATA 0x20202020
+#define DDRSS_PHY_391_DATA 0xF0F02020
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x04F00000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00030200
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x01030000
+#define DDRSS_PHY_518_DATA 0x00010000
+#define DDRSS_PHY_519_DATA 0x01030004
+#define DDRSS_PHY_520_DATA 0x01000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x01010000
+#define DDRSS_PHY_525_DATA 0x00010000
+#define DDRSS_PHY_526_DATA 0x00C00001
+#define DDRSS_PHY_527_DATA 0x00CC0008
+#define DDRSS_PHY_528_DATA 0x00660601
+#define DDRSS_PHY_529_DATA 0x00000003
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000001
+#define DDRSS_PHY_532_DATA 0x0000AAAA
+#define DDRSS_PHY_533_DATA 0x00005555
+#define DDRSS_PHY_534_DATA 0x0000B5B5
+#define DDRSS_PHY_535_DATA 0x00004A4A
+#define DDRSS_PHY_536_DATA 0x00005656
+#define DDRSS_PHY_537_DATA 0x0000A9A9
+#define DDRSS_PHY_538_DATA 0x0000B7B7
+#define DDRSS_PHY_539_DATA 0x00004848
+#define DDRSS_PHY_540_DATA 0x00000000
+#define DDRSS_PHY_541_DATA 0x00000000
+#define DDRSS_PHY_542_DATA 0x08000000
+#define DDRSS_PHY_543_DATA 0x0F000008
+#define DDRSS_PHY_544_DATA 0x00000F0F
+#define DDRSS_PHY_545_DATA 0x00E4E400
+#define DDRSS_PHY_546_DATA 0x00071020
+#define DDRSS_PHY_547_DATA 0x000C0020
+#define DDRSS_PHY_548_DATA 0x00062000
+#define DDRSS_PHY_549_DATA 0x00000000
+#define DDRSS_PHY_550_DATA 0x55555555
+#define DDRSS_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS_PHY_552_DATA 0x55555555
+#define DDRSS_PHY_553_DATA 0xAAAAAAAA
+#define DDRSS_PHY_554_DATA 0x00005555
+#define DDRSS_PHY_555_DATA 0x01000100
+#define DDRSS_PHY_556_DATA 0x00800180
+#define DDRSS_PHY_557_DATA 0x00000001
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x081F07FF
+#define DDRSS_PHY_587_DATA 0x10200080
+#define DDRSS_PHY_588_DATA 0x00000008
+#define DDRSS_PHY_589_DATA 0x00000401
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x01CC0C01
+#define DDRSS_PHY_592_DATA 0x1003CC0C
+#define DDRSS_PHY_593_DATA 0x20000140
+#define DDRSS_PHY_594_DATA 0x07FF0200
+#define DDRSS_PHY_595_DATA 0x0000DD01
+#define DDRSS_PHY_596_DATA 0x00100303
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00041000
+#define DDRSS_PHY_600_DATA 0x00100010
+#define DDRSS_PHY_601_DATA 0x00100010
+#define DDRSS_PHY_602_DATA 0x00100010
+#define DDRSS_PHY_603_DATA 0x00100010
+#define DDRSS_PHY_604_DATA 0x02040010
+#define DDRSS_PHY_605_DATA 0x00000005
+#define DDRSS_PHY_606_DATA 0x51516042
+#define DDRSS_PHY_607_DATA 0x31C06000
+#define DDRSS_PHY_608_DATA 0x07AB0340
+#define DDRSS_PHY_609_DATA 0x00C0C001
+#define DDRSS_PHY_610_DATA 0x0D000000
+#define DDRSS_PHY_611_DATA 0x000D0C0C
+#define DDRSS_PHY_612_DATA 0x42100010
+#define DDRSS_PHY_613_DATA 0x010C073E
+#define DDRSS_PHY_614_DATA 0x000F0C32
+#define DDRSS_PHY_615_DATA 0x01000140
+#define DDRSS_PHY_616_DATA 0x011E0120
+#define DDRSS_PHY_617_DATA 0x00000C00
+#define DDRSS_PHY_618_DATA 0x000002DD
+#define DDRSS_PHY_619_DATA 0x00030200
+#define DDRSS_PHY_620_DATA 0x02800000
+#define DDRSS_PHY_621_DATA 0x80800000
+#define DDRSS_PHY_622_DATA 0x000D2010
+#define DDRSS_PHY_623_DATA 0x76543210
+#define DDRSS_PHY_624_DATA 0x00000008
+#define DDRSS_PHY_625_DATA 0x045D045D
+#define DDRSS_PHY_626_DATA 0x045D045D
+#define DDRSS_PHY_627_DATA 0x045D045D
+#define DDRSS_PHY_628_DATA 0x045D045D
+#define DDRSS_PHY_629_DATA 0x0000045D
+#define DDRSS_PHY_630_DATA 0x0000A000
+#define DDRSS_PHY_631_DATA 0x00A000A0
+#define DDRSS_PHY_632_DATA 0x00A000A0
+#define DDRSS_PHY_633_DATA 0x00A000A0
+#define DDRSS_PHY_634_DATA 0x00A000A0
+#define DDRSS_PHY_635_DATA 0x00A000A0
+#define DDRSS_PHY_636_DATA 0x00A000A0
+#define DDRSS_PHY_637_DATA 0x00A000A0
+#define DDRSS_PHY_638_DATA 0x00A000A0
+#define DDRSS_PHY_639_DATA 0x00B200A0
+#define DDRSS_PHY_640_DATA 0x01000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00080200
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x20202020
+#define DDRSS_PHY_646_DATA 0x20202020
+#define DDRSS_PHY_647_DATA 0xF0F02020
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x04F00000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00030200
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x01030000
+#define DDRSS_PHY_774_DATA 0x00010000
+#define DDRSS_PHY_775_DATA 0x01030004
+#define DDRSS_PHY_776_DATA 0x01000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x01010000
+#define DDRSS_PHY_781_DATA 0x00010000
+#define DDRSS_PHY_782_DATA 0x00C00001
+#define DDRSS_PHY_783_DATA 0x00CC0008
+#define DDRSS_PHY_784_DATA 0x00660601
+#define DDRSS_PHY_785_DATA 0x00000003
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000001
+#define DDRSS_PHY_788_DATA 0x0000AAAA
+#define DDRSS_PHY_789_DATA 0x00005555
+#define DDRSS_PHY_790_DATA 0x0000B5B5
+#define DDRSS_PHY_791_DATA 0x00004A4A
+#define DDRSS_PHY_792_DATA 0x00005656
+#define DDRSS_PHY_793_DATA 0x0000A9A9
+#define DDRSS_PHY_794_DATA 0x0000B7B7
+#define DDRSS_PHY_795_DATA 0x00004848
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x08000000
+#define DDRSS_PHY_799_DATA 0x0F000008
+#define DDRSS_PHY_800_DATA 0x00000F0F
+#define DDRSS_PHY_801_DATA 0x00E4E400
+#define DDRSS_PHY_802_DATA 0x00071020
+#define DDRSS_PHY_803_DATA 0x000C0020
+#define DDRSS_PHY_804_DATA 0x00062000
+#define DDRSS_PHY_805_DATA 0x00000000
+#define DDRSS_PHY_806_DATA 0x55555555
+#define DDRSS_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS_PHY_808_DATA 0x55555555
+#define DDRSS_PHY_809_DATA 0xAAAAAAAA
+#define DDRSS_PHY_810_DATA 0x00005555
+#define DDRSS_PHY_811_DATA 0x01000100
+#define DDRSS_PHY_812_DATA 0x00800180
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x081F07FF
+#define DDRSS_PHY_843_DATA 0x10200080
+#define DDRSS_PHY_844_DATA 0x00000008
+#define DDRSS_PHY_845_DATA 0x00000401
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x01CC0C01
+#define DDRSS_PHY_848_DATA 0x1003CC0C
+#define DDRSS_PHY_849_DATA 0x20000140
+#define DDRSS_PHY_850_DATA 0x07FF0200
+#define DDRSS_PHY_851_DATA 0x0000DD01
+#define DDRSS_PHY_852_DATA 0x00100303
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00041000
+#define DDRSS_PHY_856_DATA 0x00100010
+#define DDRSS_PHY_857_DATA 0x00100010
+#define DDRSS_PHY_858_DATA 0x00100010
+#define DDRSS_PHY_859_DATA 0x00100010
+#define DDRSS_PHY_860_DATA 0x02040010
+#define DDRSS_PHY_861_DATA 0x00000005
+#define DDRSS_PHY_862_DATA 0x51516042
+#define DDRSS_PHY_863_DATA 0x31C06000
+#define DDRSS_PHY_864_DATA 0x07AB0340
+#define DDRSS_PHY_865_DATA 0x00C0C001
+#define DDRSS_PHY_866_DATA 0x0D000000
+#define DDRSS_PHY_867_DATA 0x000D0C0C
+#define DDRSS_PHY_868_DATA 0x42100010
+#define DDRSS_PHY_869_DATA 0x010C073E
+#define DDRSS_PHY_870_DATA 0x000F0C32
+#define DDRSS_PHY_871_DATA 0x01000140
+#define DDRSS_PHY_872_DATA 0x011E0120
+#define DDRSS_PHY_873_DATA 0x00000C00
+#define DDRSS_PHY_874_DATA 0x000002DD
+#define DDRSS_PHY_875_DATA 0x00030200
+#define DDRSS_PHY_876_DATA 0x02800000
+#define DDRSS_PHY_877_DATA 0x80800000
+#define DDRSS_PHY_878_DATA 0x000D2010
+#define DDRSS_PHY_879_DATA 0x76543210
+#define DDRSS_PHY_880_DATA 0x00000008
+#define DDRSS_PHY_881_DATA 0x045D045D
+#define DDRSS_PHY_882_DATA 0x045D045D
+#define DDRSS_PHY_883_DATA 0x045D045D
+#define DDRSS_PHY_884_DATA 0x045D045D
+#define DDRSS_PHY_885_DATA 0x0000045D
+#define DDRSS_PHY_886_DATA 0x0000A000
+#define DDRSS_PHY_887_DATA 0x00A000A0
+#define DDRSS_PHY_888_DATA 0x00A000A0
+#define DDRSS_PHY_889_DATA 0x00A000A0
+#define DDRSS_PHY_890_DATA 0x00A000A0
+#define DDRSS_PHY_891_DATA 0x00A000A0
+#define DDRSS_PHY_892_DATA 0x00A000A0
+#define DDRSS_PHY_893_DATA 0x00A000A0
+#define DDRSS_PHY_894_DATA 0x00A000A0
+#define DDRSS_PHY_895_DATA 0x00B200A0
+#define DDRSS_PHY_896_DATA 0x01000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00080200
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x20202020
+#define DDRSS_PHY_902_DATA 0x20202020
+#define DDRSS_PHY_903_DATA 0xF0F02020
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x0000002A
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x00000015
+#define DDRSS_PHY_1048_DATA 0x0000002A
+#define DDRSS_PHY_1049_DATA 0x00000033
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x0000000C
+#define DDRSS_PHY_1052_DATA 0x00000033
+#define DDRSS_PHY_1053_DATA 0x0A418820
+#define DDRSS_PHY_1054_DATA 0x003F0000
+#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1056_DATA 0x20202003
+#define DDRSS_PHY_1057_DATA 0x00202020
+#define DDRSS_PHY_1058_DATA 0x20008008
+#define DDRSS_PHY_1059_DATA 0x00000810
+#define DDRSS_PHY_1060_DATA 0x00000F00
+#define DDRSS_PHY_1061_DATA 0x000405CC
+#define DDRSS_PHY_1062_DATA 0x03000004
+#define DDRSS_PHY_1063_DATA 0x00030000
+#define DDRSS_PHY_1064_DATA 0x00000300
+#define DDRSS_PHY_1065_DATA 0x00000300
+#define DDRSS_PHY_1066_DATA 0x00000300
+#define DDRSS_PHY_1067_DATA 0x00000300
+#define DDRSS_PHY_1068_DATA 0x42080010
+#define DDRSS_PHY_1069_DATA 0x0000803E
+#define DDRSS_PHY_1070_DATA 0x00000001
+#define DDRSS_PHY_1071_DATA 0x01000002
+#define DDRSS_PHY_1072_DATA 0x00008000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000000
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000100
+#define DDRSS_PHY_1286_DATA 0x00000200
+#define DDRSS_PHY_1287_DATA 0x00000000
+#define DDRSS_PHY_1288_DATA 0x00000000
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00400000
+#define DDRSS_PHY_1292_DATA 0x00000080
+#define DDRSS_PHY_1293_DATA 0x00DCBA98
+#define DDRSS_PHY_1294_DATA 0x03000000
+#define DDRSS_PHY_1295_DATA 0x00200000
+#define DDRSS_PHY_1296_DATA 0x00000000
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x00000000
+#define DDRSS_PHY_1300_DATA 0x00000000
+#define DDRSS_PHY_1301_DATA 0x0000002A
+#define DDRSS_PHY_1302_DATA 0x00000015
+#define DDRSS_PHY_1303_DATA 0x00000015
+#define DDRSS_PHY_1304_DATA 0x0000002A
+#define DDRSS_PHY_1305_DATA 0x00000033
+#define DDRSS_PHY_1306_DATA 0x0000000C
+#define DDRSS_PHY_1307_DATA 0x0000000C
+#define DDRSS_PHY_1308_DATA 0x00000033
+#define DDRSS_PHY_1309_DATA 0x0A418820
+#define DDRSS_PHY_1310_DATA 0x00000000
+#define DDRSS_PHY_1311_DATA 0x000F0000
+#define DDRSS_PHY_1312_DATA 0x20202003
+#define DDRSS_PHY_1313_DATA 0x00202020
+#define DDRSS_PHY_1314_DATA 0x20008008
+#define DDRSS_PHY_1315_DATA 0x00000810
+#define DDRSS_PHY_1316_DATA 0x00000F00
+#define DDRSS_PHY_1317_DATA 0x000405CC
+#define DDRSS_PHY_1318_DATA 0x03000004
+#define DDRSS_PHY_1319_DATA 0x00030000
+#define DDRSS_PHY_1320_DATA 0x00000300
+#define DDRSS_PHY_1321_DATA 0x00000300
+#define DDRSS_PHY_1322_DATA 0x00000300
+#define DDRSS_PHY_1323_DATA 0x00000300
+#define DDRSS_PHY_1324_DATA 0x42080010
+#define DDRSS_PHY_1325_DATA 0x0000803E
+#define DDRSS_PHY_1326_DATA 0x00000001
+#define DDRSS_PHY_1327_DATA 0x01000002
+#define DDRSS_PHY_1328_DATA 0x00008000
+#define DDRSS_PHY_1329_DATA 0x00000000
+#define DDRSS_PHY_1330_DATA 0x00000000
+#define DDRSS_PHY_1331_DATA 0x00000000
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000000
+#define DDRSS_PHY_1334_DATA 0x00000000
+#define DDRSS_PHY_1335_DATA 0x00000000
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x00000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x00000000
+#define DDRSS_PHY_1346_DATA 0x00000000
+#define DDRSS_PHY_1347_DATA 0x00000000
+#define DDRSS_PHY_1348_DATA 0x00000000
+#define DDRSS_PHY_1349_DATA 0x00000000
+#define DDRSS_PHY_1350_DATA 0x00000000
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000000
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x00000000
+#define DDRSS_PHY_1360_DATA 0x00000000
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00000000
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000000
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000000
+#define DDRSS_PHY_1372_DATA 0x00000000
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00000000
+#define DDRSS_PHY_1375_DATA 0x00000000
+#define DDRSS_PHY_1376_DATA 0x00000000
+#define DDRSS_PHY_1377_DATA 0x00000000
+#define DDRSS_PHY_1378_DATA 0x00000000
+#define DDRSS_PHY_1379_DATA 0x00000000
+#define DDRSS_PHY_1380_DATA 0x00000000
+#define DDRSS_PHY_1381_DATA 0x00000000
+#define DDRSS_PHY_1382_DATA 0x00000000
+#define DDRSS_PHY_1383_DATA 0x00000000
+#define DDRSS_PHY_1384_DATA 0x00000000
+#define DDRSS_PHY_1385_DATA 0x00000000
+#define DDRSS_PHY_1386_DATA 0x00000000
+#define DDRSS_PHY_1387_DATA 0x00000000
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x00000000
+#define DDRSS_PHY_1390_DATA 0x00000000
+#define DDRSS_PHY_1391_DATA 0x00000000
+#define DDRSS_PHY_1392_DATA 0x00000000
+#define DDRSS_PHY_1393_DATA 0x00000000
+#define DDRSS_PHY_1394_DATA 0x00000000
+#define DDRSS_PHY_1395_DATA 0x00000000
+#define DDRSS_PHY_1396_DATA 0x00000000
+#define DDRSS_PHY_1397_DATA 0x00000000
+#define DDRSS_PHY_1398_DATA 0x00000000
+#define DDRSS_PHY_1399_DATA 0x00000000
+#define DDRSS_PHY_1400_DATA 0x00000000
+#define DDRSS_PHY_1401_DATA 0x00000000
+#define DDRSS_PHY_1402_DATA 0x00000000
+#define DDRSS_PHY_1403_DATA 0x00000000
+#define DDRSS_PHY_1404_DATA 0x00000000
+#define DDRSS_PHY_1405_DATA 0x00000000
+#define DDRSS_PHY_1406_DATA 0x00000000
+#define DDRSS_PHY_1407_DATA 0x00000000
+#define DDRSS_PHY_1408_DATA 0x00000000
+#define DDRSS_PHY_1409_DATA 0x00000000
+#define DDRSS_PHY_1410_DATA 0x00000000
+#define DDRSS_PHY_1411_DATA 0x00000000
+#define DDRSS_PHY_1412_DATA 0x00000000
+#define DDRSS_PHY_1413_DATA 0x00000000
+#define DDRSS_PHY_1414_DATA 0x00000000
+#define DDRSS_PHY_1415_DATA 0x00000000
+#define DDRSS_PHY_1416_DATA 0x00000000
+#define DDRSS_PHY_1417_DATA 0x00000000
+#define DDRSS_PHY_1418_DATA 0x00000000
+#define DDRSS_PHY_1419_DATA 0x00000000
+#define DDRSS_PHY_1420_DATA 0x00000000
+#define DDRSS_PHY_1421_DATA 0x00000000
+#define DDRSS_PHY_1422_DATA 0x00000000
+#define DDRSS_PHY_1423_DATA 0x00000000
+#define DDRSS_PHY_1424_DATA 0x00000000
+#define DDRSS_PHY_1425_DATA 0x00000000
+#define DDRSS_PHY_1426_DATA 0x00000000
+#define DDRSS_PHY_1427_DATA 0x00000000
+#define DDRSS_PHY_1428_DATA 0x00000000
+#define DDRSS_PHY_1429_DATA 0x00000000
+#define DDRSS_PHY_1430_DATA 0x00000000
+#define DDRSS_PHY_1431_DATA 0x00000000
+#define DDRSS_PHY_1432_DATA 0x00000000
+#define DDRSS_PHY_1433_DATA 0x00000000
+#define DDRSS_PHY_1434_DATA 0x00000000
+#define DDRSS_PHY_1435_DATA 0x00000000
+#define DDRSS_PHY_1436_DATA 0x00000000
+#define DDRSS_PHY_1437_DATA 0x00000000
+#define DDRSS_PHY_1438_DATA 0x00000000
+#define DDRSS_PHY_1439_DATA 0x00000000
+#define DDRSS_PHY_1440_DATA 0x00000000
+#define DDRSS_PHY_1441_DATA 0x00000000
+#define DDRSS_PHY_1442_DATA 0x00000000
+#define DDRSS_PHY_1443_DATA 0x00000000
+#define DDRSS_PHY_1444_DATA 0x00000000
+#define DDRSS_PHY_1445_DATA 0x00000000
+#define DDRSS_PHY_1446_DATA 0x00000000
+#define DDRSS_PHY_1447_DATA 0x00000000
+#define DDRSS_PHY_1448_DATA 0x00000000
+#define DDRSS_PHY_1449_DATA 0x00000000
+#define DDRSS_PHY_1450_DATA 0x00000000
+#define DDRSS_PHY_1451_DATA 0x00000000
+#define DDRSS_PHY_1452_DATA 0x00000000
+#define DDRSS_PHY_1453_DATA 0x00000000
+#define DDRSS_PHY_1454_DATA 0x00000000
+#define DDRSS_PHY_1455_DATA 0x00000000
+#define DDRSS_PHY_1456_DATA 0x00000000
+#define DDRSS_PHY_1457_DATA 0x00000000
+#define DDRSS_PHY_1458_DATA 0x00000000
+#define DDRSS_PHY_1459_DATA 0x00000000
+#define DDRSS_PHY_1460_DATA 0x00000000
+#define DDRSS_PHY_1461_DATA 0x00000000
+#define DDRSS_PHY_1462_DATA 0x00000000
+#define DDRSS_PHY_1463_DATA 0x00000000
+#define DDRSS_PHY_1464_DATA 0x00000000
+#define DDRSS_PHY_1465_DATA 0x00000000
+#define DDRSS_PHY_1466_DATA 0x00000000
+#define DDRSS_PHY_1467_DATA 0x00000000
+#define DDRSS_PHY_1468_DATA 0x00000000
+#define DDRSS_PHY_1469_DATA 0x00000000
+#define DDRSS_PHY_1470_DATA 0x00000000
+#define DDRSS_PHY_1471_DATA 0x00000000
+#define DDRSS_PHY_1472_DATA 0x00000000
+#define DDRSS_PHY_1473_DATA 0x00000000
+#define DDRSS_PHY_1474_DATA 0x00000000
+#define DDRSS_PHY_1475_DATA 0x00000000
+#define DDRSS_PHY_1476_DATA 0x00000000
+#define DDRSS_PHY_1477_DATA 0x00000000
+#define DDRSS_PHY_1478_DATA 0x00000000
+#define DDRSS_PHY_1479_DATA 0x00000000
+#define DDRSS_PHY_1480_DATA 0x00000000
+#define DDRSS_PHY_1481_DATA 0x00000000
+#define DDRSS_PHY_1482_DATA 0x00000000
+#define DDRSS_PHY_1483_DATA 0x00000000
+#define DDRSS_PHY_1484_DATA 0x00000000
+#define DDRSS_PHY_1485_DATA 0x00000000
+#define DDRSS_PHY_1486_DATA 0x00000000
+#define DDRSS_PHY_1487_DATA 0x00000000
+#define DDRSS_PHY_1488_DATA 0x00000000
+#define DDRSS_PHY_1489_DATA 0x00000000
+#define DDRSS_PHY_1490_DATA 0x00000000
+#define DDRSS_PHY_1491_DATA 0x00000000
+#define DDRSS_PHY_1492_DATA 0x00000000
+#define DDRSS_PHY_1493_DATA 0x00000000
+#define DDRSS_PHY_1494_DATA 0x00000000
+#define DDRSS_PHY_1495_DATA 0x00000000
+#define DDRSS_PHY_1496_DATA 0x00000000
+#define DDRSS_PHY_1497_DATA 0x00000000
+#define DDRSS_PHY_1498_DATA 0x00000000
+#define DDRSS_PHY_1499_DATA 0x00000000
+#define DDRSS_PHY_1500_DATA 0x00000000
+#define DDRSS_PHY_1501_DATA 0x00000000
+#define DDRSS_PHY_1502_DATA 0x00000000
+#define DDRSS_PHY_1503_DATA 0x00000000
+#define DDRSS_PHY_1504_DATA 0x00000000
+#define DDRSS_PHY_1505_DATA 0x00000000
+#define DDRSS_PHY_1506_DATA 0x00000000
+#define DDRSS_PHY_1507_DATA 0x00000000
+#define DDRSS_PHY_1508_DATA 0x00000000
+#define DDRSS_PHY_1509_DATA 0x00000000
+#define DDRSS_PHY_1510_DATA 0x00000000
+#define DDRSS_PHY_1511_DATA 0x00000000
+#define DDRSS_PHY_1512_DATA 0x00000000
+#define DDRSS_PHY_1513_DATA 0x00000000
+#define DDRSS_PHY_1514_DATA 0x00000000
+#define DDRSS_PHY_1515_DATA 0x00000000
+#define DDRSS_PHY_1516_DATA 0x00000000
+#define DDRSS_PHY_1517_DATA 0x00000000
+#define DDRSS_PHY_1518_DATA 0x00000000
+#define DDRSS_PHY_1519_DATA 0x00000000
+#define DDRSS_PHY_1520_DATA 0x00000000
+#define DDRSS_PHY_1521_DATA 0x00000000
+#define DDRSS_PHY_1522_DATA 0x00000000
+#define DDRSS_PHY_1523_DATA 0x00000000
+#define DDRSS_PHY_1524_DATA 0x00000000
+#define DDRSS_PHY_1525_DATA 0x00000000
+#define DDRSS_PHY_1526_DATA 0x00000000
+#define DDRSS_PHY_1527_DATA 0x00000000
+#define DDRSS_PHY_1528_DATA 0x00000000
+#define DDRSS_PHY_1529_DATA 0x00000000
+#define DDRSS_PHY_1530_DATA 0x00000000
+#define DDRSS_PHY_1531_DATA 0x00000000
+#define DDRSS_PHY_1532_DATA 0x00000000
+#define DDRSS_PHY_1533_DATA 0x00000000
+#define DDRSS_PHY_1534_DATA 0x00000000
+#define DDRSS_PHY_1535_DATA 0x00000000
+#define DDRSS_PHY_1536_DATA 0x00000000
+#define DDRSS_PHY_1537_DATA 0x00000000
+#define DDRSS_PHY_1538_DATA 0x00000000
+#define DDRSS_PHY_1539_DATA 0x00000000
+#define DDRSS_PHY_1540_DATA 0x00000000
+#define DDRSS_PHY_1541_DATA 0x00000100
+#define DDRSS_PHY_1542_DATA 0x00000200
+#define DDRSS_PHY_1543_DATA 0x00000000
+#define DDRSS_PHY_1544_DATA 0x00000000
+#define DDRSS_PHY_1545_DATA 0x00000000
+#define DDRSS_PHY_1546_DATA 0x00000000
+#define DDRSS_PHY_1547_DATA 0x00400000
+#define DDRSS_PHY_1548_DATA 0x00000080
+#define DDRSS_PHY_1549_DATA 0x00DCBA98
+#define DDRSS_PHY_1550_DATA 0x03000000
+#define DDRSS_PHY_1551_DATA 0x00200000
+#define DDRSS_PHY_1552_DATA 0x00000000
+#define DDRSS_PHY_1553_DATA 0x00000000
+#define DDRSS_PHY_1554_DATA 0x00000000
+#define DDRSS_PHY_1555_DATA 0x00000000
+#define DDRSS_PHY_1556_DATA 0x00000000
+#define DDRSS_PHY_1557_DATA 0x0000002A
+#define DDRSS_PHY_1558_DATA 0x00000015
+#define DDRSS_PHY_1559_DATA 0x00000015
+#define DDRSS_PHY_1560_DATA 0x0000002A
+#define DDRSS_PHY_1561_DATA 0x00000033
+#define DDRSS_PHY_1562_DATA 0x0000000C
+#define DDRSS_PHY_1563_DATA 0x0000000C
+#define DDRSS_PHY_1564_DATA 0x00000033
+#define DDRSS_PHY_1565_DATA 0x0A418820
+#define DDRSS_PHY_1566_DATA 0x10000000
+#define DDRSS_PHY_1567_DATA 0x000F0000
+#define DDRSS_PHY_1568_DATA 0x20202003
+#define DDRSS_PHY_1569_DATA 0x00202020
+#define DDRSS_PHY_1570_DATA 0x20008008
+#define DDRSS_PHY_1571_DATA 0x00000810
+#define DDRSS_PHY_1572_DATA 0x00000F00
+#define DDRSS_PHY_1573_DATA 0x000405CC
+#define DDRSS_PHY_1574_DATA 0x03000004
+#define DDRSS_PHY_1575_DATA 0x00030000
+#define DDRSS_PHY_1576_DATA 0x00000300
+#define DDRSS_PHY_1577_DATA 0x00000300
+#define DDRSS_PHY_1578_DATA 0x00000300
+#define DDRSS_PHY_1579_DATA 0x00000300
+#define DDRSS_PHY_1580_DATA 0x42080010
+#define DDRSS_PHY_1581_DATA 0x0000803E
+#define DDRSS_PHY_1582_DATA 0x00000001
+#define DDRSS_PHY_1583_DATA 0x01000002
+#define DDRSS_PHY_1584_DATA 0x00008000
+#define DDRSS_PHY_1585_DATA 0x00000000
+#define DDRSS_PHY_1586_DATA 0x00000000
+#define DDRSS_PHY_1587_DATA 0x00000000
+#define DDRSS_PHY_1588_DATA 0x00000000
+#define DDRSS_PHY_1589_DATA 0x00000000
+#define DDRSS_PHY_1590_DATA 0x00000000
+#define DDRSS_PHY_1591_DATA 0x00000000
+#define DDRSS_PHY_1592_DATA 0x00000000
+#define DDRSS_PHY_1593_DATA 0x00000000
+#define DDRSS_PHY_1594_DATA 0x00000000
+#define DDRSS_PHY_1595_DATA 0x00000000
+#define DDRSS_PHY_1596_DATA 0x00000000
+#define DDRSS_PHY_1597_DATA 0x00000000
+#define DDRSS_PHY_1598_DATA 0x00000000
+#define DDRSS_PHY_1599_DATA 0x00000000
+#define DDRSS_PHY_1600_DATA 0x00000000
+#define DDRSS_PHY_1601_DATA 0x00000000
+#define DDRSS_PHY_1602_DATA 0x00000000
+#define DDRSS_PHY_1603_DATA 0x00000000
+#define DDRSS_PHY_1604_DATA 0x00000000
+#define DDRSS_PHY_1605_DATA 0x00000000
+#define DDRSS_PHY_1606_DATA 0x00000000
+#define DDRSS_PHY_1607_DATA 0x00000000
+#define DDRSS_PHY_1608_DATA 0x00000000
+#define DDRSS_PHY_1609_DATA 0x00000000
+#define DDRSS_PHY_1610_DATA 0x00000000
+#define DDRSS_PHY_1611_DATA 0x00000000
+#define DDRSS_PHY_1612_DATA 0x00000000
+#define DDRSS_PHY_1613_DATA 0x00000000
+#define DDRSS_PHY_1614_DATA 0x00000000
+#define DDRSS_PHY_1615_DATA 0x00000000
+#define DDRSS_PHY_1616_DATA 0x00000000
+#define DDRSS_PHY_1617_DATA 0x00000000
+#define DDRSS_PHY_1618_DATA 0x00000000
+#define DDRSS_PHY_1619_DATA 0x00000000
+#define DDRSS_PHY_1620_DATA 0x00000000
+#define DDRSS_PHY_1621_DATA 0x00000000
+#define DDRSS_PHY_1622_DATA 0x00000000
+#define DDRSS_PHY_1623_DATA 0x00000000
+#define DDRSS_PHY_1624_DATA 0x00000000
+#define DDRSS_PHY_1625_DATA 0x00000000
+#define DDRSS_PHY_1626_DATA 0x00000000
+#define DDRSS_PHY_1627_DATA 0x00000000
+#define DDRSS_PHY_1628_DATA 0x00000000
+#define DDRSS_PHY_1629_DATA 0x00000000
+#define DDRSS_PHY_1630_DATA 0x00000000
+#define DDRSS_PHY_1631_DATA 0x00000000
+#define DDRSS_PHY_1632_DATA 0x00000000
+#define DDRSS_PHY_1633_DATA 0x00000000
+#define DDRSS_PHY_1634_DATA 0x00000000
+#define DDRSS_PHY_1635_DATA 0x00000000
+#define DDRSS_PHY_1636_DATA 0x00000000
+#define DDRSS_PHY_1637_DATA 0x00000000
+#define DDRSS_PHY_1638_DATA 0x00000000
+#define DDRSS_PHY_1639_DATA 0x00000000
+#define DDRSS_PHY_1640_DATA 0x00000000
+#define DDRSS_PHY_1641_DATA 0x00000000
+#define DDRSS_PHY_1642_DATA 0x00000000
+#define DDRSS_PHY_1643_DATA 0x00000000
+#define DDRSS_PHY_1644_DATA 0x00000000
+#define DDRSS_PHY_1645_DATA 0x00000000
+#define DDRSS_PHY_1646_DATA 0x00000000
+#define DDRSS_PHY_1647_DATA 0x00000000
+#define DDRSS_PHY_1648_DATA 0x00000000
+#define DDRSS_PHY_1649_DATA 0x00000000
+#define DDRSS_PHY_1650_DATA 0x00000000
+#define DDRSS_PHY_1651_DATA 0x00000000
+#define DDRSS_PHY_1652_DATA 0x00000000
+#define DDRSS_PHY_1653_DATA 0x00000000
+#define DDRSS_PHY_1654_DATA 0x00000000
+#define DDRSS_PHY_1655_DATA 0x00000000
+#define DDRSS_PHY_1656_DATA 0x00000000
+#define DDRSS_PHY_1657_DATA 0x00000000
+#define DDRSS_PHY_1658_DATA 0x00000000
+#define DDRSS_PHY_1659_DATA 0x00000000
+#define DDRSS_PHY_1660_DATA 0x00000000
+#define DDRSS_PHY_1661_DATA 0x00000000
+#define DDRSS_PHY_1662_DATA 0x00000000
+#define DDRSS_PHY_1663_DATA 0x00000000
+#define DDRSS_PHY_1664_DATA 0x00000000
+#define DDRSS_PHY_1665_DATA 0x00000000
+#define DDRSS_PHY_1666_DATA 0x00000000
+#define DDRSS_PHY_1667_DATA 0x00000000
+#define DDRSS_PHY_1668_DATA 0x00000000
+#define DDRSS_PHY_1669_DATA 0x00000000
+#define DDRSS_PHY_1670_DATA 0x00000000
+#define DDRSS_PHY_1671_DATA 0x00000000
+#define DDRSS_PHY_1672_DATA 0x00000000
+#define DDRSS_PHY_1673_DATA 0x00000000
+#define DDRSS_PHY_1674_DATA 0x00000000
+#define DDRSS_PHY_1675_DATA 0x00000000
+#define DDRSS_PHY_1676_DATA 0x00000000
+#define DDRSS_PHY_1677_DATA 0x00000000
+#define DDRSS_PHY_1678_DATA 0x00000000
+#define DDRSS_PHY_1679_DATA 0x00000000
+#define DDRSS_PHY_1680_DATA 0x00000000
+#define DDRSS_PHY_1681_DATA 0x00000000
+#define DDRSS_PHY_1682_DATA 0x00000000
+#define DDRSS_PHY_1683_DATA 0x00000000
+#define DDRSS_PHY_1684_DATA 0x00000000
+#define DDRSS_PHY_1685_DATA 0x00000000
+#define DDRSS_PHY_1686_DATA 0x00000000
+#define DDRSS_PHY_1687_DATA 0x00000000
+#define DDRSS_PHY_1688_DATA 0x00000000
+#define DDRSS_PHY_1689_DATA 0x00000000
+#define DDRSS_PHY_1690_DATA 0x00000000
+#define DDRSS_PHY_1691_DATA 0x00000000
+#define DDRSS_PHY_1692_DATA 0x00000000
+#define DDRSS_PHY_1693_DATA 0x00000000
+#define DDRSS_PHY_1694_DATA 0x00000000
+#define DDRSS_PHY_1695_DATA 0x00000000
+#define DDRSS_PHY_1696_DATA 0x00000000
+#define DDRSS_PHY_1697_DATA 0x00000000
+#define DDRSS_PHY_1698_DATA 0x00000000
+#define DDRSS_PHY_1699_DATA 0x00000000
+#define DDRSS_PHY_1700_DATA 0x00000000
+#define DDRSS_PHY_1701_DATA 0x00000000
+#define DDRSS_PHY_1702_DATA 0x00000000
+#define DDRSS_PHY_1703_DATA 0x00000000
+#define DDRSS_PHY_1704_DATA 0x00000000
+#define DDRSS_PHY_1705_DATA 0x00000000
+#define DDRSS_PHY_1706_DATA 0x00000000
+#define DDRSS_PHY_1707_DATA 0x00000000
+#define DDRSS_PHY_1708_DATA 0x00000000
+#define DDRSS_PHY_1709_DATA 0x00000000
+#define DDRSS_PHY_1710_DATA 0x00000000
+#define DDRSS_PHY_1711_DATA 0x00000000
+#define DDRSS_PHY_1712_DATA 0x00000000
+#define DDRSS_PHY_1713_DATA 0x00000000
+#define DDRSS_PHY_1714_DATA 0x00000000
+#define DDRSS_PHY_1715_DATA 0x00000000
+#define DDRSS_PHY_1716_DATA 0x00000000
+#define DDRSS_PHY_1717_DATA 0x00000000
+#define DDRSS_PHY_1718_DATA 0x00000000
+#define DDRSS_PHY_1719_DATA 0x00000000
+#define DDRSS_PHY_1720_DATA 0x00000000
+#define DDRSS_PHY_1721_DATA 0x00000000
+#define DDRSS_PHY_1722_DATA 0x00000000
+#define DDRSS_PHY_1723_DATA 0x00000000
+#define DDRSS_PHY_1724_DATA 0x00000000
+#define DDRSS_PHY_1725_DATA 0x00000000
+#define DDRSS_PHY_1726_DATA 0x00000000
+#define DDRSS_PHY_1727_DATA 0x00000000
+#define DDRSS_PHY_1728_DATA 0x00000000
+#define DDRSS_PHY_1729_DATA 0x00000000
+#define DDRSS_PHY_1730_DATA 0x00000000
+#define DDRSS_PHY_1731_DATA 0x00000000
+#define DDRSS_PHY_1732_DATA 0x00000000
+#define DDRSS_PHY_1733_DATA 0x00000000
+#define DDRSS_PHY_1734_DATA 0x00000000
+#define DDRSS_PHY_1735_DATA 0x00000000
+#define DDRSS_PHY_1736_DATA 0x00000000
+#define DDRSS_PHY_1737_DATA 0x00000000
+#define DDRSS_PHY_1738_DATA 0x00000000
+#define DDRSS_PHY_1739_DATA 0x00000000
+#define DDRSS_PHY_1740_DATA 0x00000000
+#define DDRSS_PHY_1741_DATA 0x00000000
+#define DDRSS_PHY_1742_DATA 0x00000000
+#define DDRSS_PHY_1743_DATA 0x00000000
+#define DDRSS_PHY_1744_DATA 0x00000000
+#define DDRSS_PHY_1745_DATA 0x00000000
+#define DDRSS_PHY_1746_DATA 0x00000000
+#define DDRSS_PHY_1747_DATA 0x00000000
+#define DDRSS_PHY_1748_DATA 0x00000000
+#define DDRSS_PHY_1749_DATA 0x00000000
+#define DDRSS_PHY_1750_DATA 0x00000000
+#define DDRSS_PHY_1751_DATA 0x00000000
+#define DDRSS_PHY_1752_DATA 0x00000000
+#define DDRSS_PHY_1753_DATA 0x00000000
+#define DDRSS_PHY_1754_DATA 0x00000000
+#define DDRSS_PHY_1755_DATA 0x00000000
+#define DDRSS_PHY_1756_DATA 0x00000000
+#define DDRSS_PHY_1757_DATA 0x00000000
+#define DDRSS_PHY_1758_DATA 0x00000000
+#define DDRSS_PHY_1759_DATA 0x00000000
+#define DDRSS_PHY_1760_DATA 0x00000000
+#define DDRSS_PHY_1761_DATA 0x00000000
+#define DDRSS_PHY_1762_DATA 0x00000000
+#define DDRSS_PHY_1763_DATA 0x00000000
+#define DDRSS_PHY_1764_DATA 0x00000000
+#define DDRSS_PHY_1765_DATA 0x00000000
+#define DDRSS_PHY_1766_DATA 0x00000000
+#define DDRSS_PHY_1767_DATA 0x00000000
+#define DDRSS_PHY_1768_DATA 0x00000000
+#define DDRSS_PHY_1769_DATA 0x00000000
+#define DDRSS_PHY_1770_DATA 0x00000000
+#define DDRSS_PHY_1771_DATA 0x00000000
+#define DDRSS_PHY_1772_DATA 0x00000000
+#define DDRSS_PHY_1773_DATA 0x00000000
+#define DDRSS_PHY_1774_DATA 0x00000000
+#define DDRSS_PHY_1775_DATA 0x00000000
+#define DDRSS_PHY_1776_DATA 0x00000000
+#define DDRSS_PHY_1777_DATA 0x00000000
+#define DDRSS_PHY_1778_DATA 0x00000000
+#define DDRSS_PHY_1779_DATA 0x00000000
+#define DDRSS_PHY_1780_DATA 0x00000000
+#define DDRSS_PHY_1781_DATA 0x00000000
+#define DDRSS_PHY_1782_DATA 0x00000000
+#define DDRSS_PHY_1783_DATA 0x00000000
+#define DDRSS_PHY_1784_DATA 0x00000000
+#define DDRSS_PHY_1785_DATA 0x00000000
+#define DDRSS_PHY_1786_DATA 0x00000000
+#define DDRSS_PHY_1787_DATA 0x00000000
+#define DDRSS_PHY_1788_DATA 0x00000000
+#define DDRSS_PHY_1789_DATA 0x00000000
+#define DDRSS_PHY_1790_DATA 0x00000000
+#define DDRSS_PHY_1791_DATA 0x00000000
+#define DDRSS_PHY_1792_DATA 0x00000000
+#define DDRSS_PHY_1793_DATA 0x00010100
+#define DDRSS_PHY_1794_DATA 0x00000000
+#define DDRSS_PHY_1795_DATA 0x00000000
+#define DDRSS_PHY_1796_DATA 0x00000000
+#define DDRSS_PHY_1797_DATA 0x00000000
+#define DDRSS_PHY_1798_DATA 0x00050000
+#define DDRSS_PHY_1799_DATA 0x04000000
+#define DDRSS_PHY_1800_DATA 0x00000055
+#define DDRSS_PHY_1801_DATA 0x00000000
+#define DDRSS_PHY_1802_DATA 0x00000000
+#define DDRSS_PHY_1803_DATA 0x00000000
+#define DDRSS_PHY_1804_DATA 0x00000000
+#define DDRSS_PHY_1805_DATA 0x00002001
+#define DDRSS_PHY_1806_DATA 0x00004003
+#define DDRSS_PHY_1807_DATA 0x50020028
+#define DDRSS_PHY_1808_DATA 0x01010000
+#define DDRSS_PHY_1809_DATA 0x80080001
+#define DDRSS_PHY_1810_DATA 0x10200000
+#define DDRSS_PHY_1811_DATA 0x00000008
+#define DDRSS_PHY_1812_DATA 0x00000000
+#define DDRSS_PHY_1813_DATA 0x06000000
+#define DDRSS_PHY_1814_DATA 0x010F0F0E
+#define DDRSS_PHY_1815_DATA 0x00040101
+#define DDRSS_PHY_1816_DATA 0x0000010F
+#define DDRSS_PHY_1817_DATA 0x00000000
+#define DDRSS_PHY_1818_DATA 0x00000064
+#define DDRSS_PHY_1819_DATA 0x00000000
+#define DDRSS_PHY_1820_DATA 0x00000000
+#define DDRSS_PHY_1821_DATA 0x0F0F0F01
+#define DDRSS_PHY_1822_DATA 0x0F0F0F02
+#define DDRSS_PHY_1823_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1824_DATA 0x0F0F0804
+#define DDRSS_PHY_1825_DATA 0x00800120
+#define DDRSS_PHY_1826_DATA 0x00041B42
+#define DDRSS_PHY_1827_DATA 0x00004201
+#define DDRSS_PHY_1828_DATA 0x00000000
+#define DDRSS_PHY_1829_DATA 0x00000000
+#define DDRSS_PHY_1830_DATA 0x00000000
+#define DDRSS_PHY_1831_DATA 0x00000000
+#define DDRSS_PHY_1832_DATA 0x00000000
+#define DDRSS_PHY_1833_DATA 0x00000000
+#define DDRSS_PHY_1834_DATA 0x03010100
+#define DDRSS_PHY_1835_DATA 0x00540007
+#define DDRSS_PHY_1836_DATA 0x000040A2
+#define DDRSS_PHY_1837_DATA 0x00024410
+#define DDRSS_PHY_1838_DATA 0x00004410
+#define DDRSS_PHY_1839_DATA 0x00004410
+#define DDRSS_PHY_1840_DATA 0x00004410
+#define DDRSS_PHY_1841_DATA 0x00004410
+#define DDRSS_PHY_1842_DATA 0x00004410
+#define DDRSS_PHY_1843_DATA 0x00004410
+#define DDRSS_PHY_1844_DATA 0x00004410
+#define DDRSS_PHY_1845_DATA 0x00004410
+#define DDRSS_PHY_1846_DATA 0x00004410
+#define DDRSS_PHY_1847_DATA 0x00000000
+#define DDRSS_PHY_1848_DATA 0x00000076
+#define DDRSS_PHY_1849_DATA 0x00000400
+#define DDRSS_PHY_1850_DATA 0x00000008
+#define DDRSS_PHY_1851_DATA 0x00000000
+#define DDRSS_PHY_1852_DATA 0x00000000
+#define DDRSS_PHY_1853_DATA 0x00000000
+#define DDRSS_PHY_1854_DATA 0x00000000
+#define DDRSS_PHY_1855_DATA 0x00000000
+#define DDRSS_PHY_1856_DATA 0x03000000
+#define DDRSS_PHY_1857_DATA 0x00000000
+#define DDRSS_PHY_1858_DATA 0x00000000
+#define DDRSS_PHY_1859_DATA 0x00000000
+#define DDRSS_PHY_1860_DATA 0x04102006
+#define DDRSS_PHY_1861_DATA 0x00041020
+#define DDRSS_PHY_1862_DATA 0x01C98C98
+#define DDRSS_PHY_1863_DATA 0x3F400000
+#define DDRSS_PHY_1864_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1865_DATA 0x0000001F
+#define DDRSS_PHY_1866_DATA 0x00000000
+#define DDRSS_PHY_1867_DATA 0x00000000
+#define DDRSS_PHY_1868_DATA 0x00000000
+#define DDRSS_PHY_1869_DATA 0x00000001
+#define DDRSS_PHY_1870_DATA 0x00000000
+#define DDRSS_PHY_1871_DATA 0x00000000
+#define DDRSS_PHY_1872_DATA 0x00000000
+#define DDRSS_PHY_1873_DATA 0x00000000
+#define DDRSS_PHY_1874_DATA 0x76543210
+#define DDRSS_PHY_1875_DATA 0x06010198
+#define DDRSS_PHY_1876_DATA 0x00000000
+#define DDRSS_PHY_1877_DATA 0x00000000
+#define DDRSS_PHY_1878_DATA 0x00000000
+#define DDRSS_PHY_1879_DATA 0x00040700
+#define DDRSS_PHY_1880_DATA 0x00000000
+#define DDRSS_PHY_1881_DATA 0x00000000
+#define DDRSS_PHY_1882_DATA 0x00000000
+#define DDRSS_PHY_1883_DATA 0x00000000
+#define DDRSS_PHY_1884_DATA 0x00000000
+#define DDRSS_PHY_1885_DATA 0x00000002
+#define DDRSS_PHY_1886_DATA 0x00000000
+#define DDRSS_PHY_1887_DATA 0x00000000
+#define DDRSS_PHY_1888_DATA 0x0001F7C4
+#define DDRSS_PHY_1889_DATA 0x04000004
+#define DDRSS_PHY_1890_DATA 0x00000000
+#define DDRSS_PHY_1891_DATA 0x00001142
+#define DDRSS_PHY_1892_DATA 0x01020000
+#define DDRSS_PHY_1893_DATA 0x00000080
+#define DDRSS_PHY_1894_DATA 0x03900390
+#define DDRSS_PHY_1895_DATA 0x03900390
+#define DDRSS_PHY_1896_DATA 0x03900390
+#define DDRSS_PHY_1897_DATA 0x03900390
+#define DDRSS_PHY_1898_DATA 0x03000300
+#define DDRSS_PHY_1899_DATA 0x03000300
+#define DDRSS_PHY_1900_DATA 0x00000300
+#define DDRSS_PHY_1901_DATA 0x00000300
+#define DDRSS_PHY_1902_DATA 0x00000300
+#define DDRSS_PHY_1903_DATA 0x00000300
+#define DDRSS_PHY_1904_DATA 0x00000005
+#define DDRSS_PHY_1905_DATA 0x3183BF77
+#define DDRSS_PHY_1906_DATA 0x00000000
+#define DDRSS_PHY_1907_DATA 0x0C000DFF
+#define DDRSS_PHY_1908_DATA 0x30000DFF
+#define DDRSS_PHY_1909_DATA 0x3F0DFF11
+#define DDRSS_PHY_1910_DATA 0x00EF0000
+#define DDRSS_PHY_1911_DATA 0x780DFFCC
+#define DDRSS_PHY_1912_DATA 0x00000C11
+#define DDRSS_PHY_1913_DATA 0x00018011
+#define DDRSS_PHY_1914_DATA 0x0089FF00
+#define DDRSS_PHY_1915_DATA 0x000C3F11
+#define DDRSS_PHY_1916_DATA 0x01990000
+#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1918_DATA 0x01990000
+#define DDRSS_PHY_1919_DATA 0x3F0DFF11
+#define DDRSS_PHY_1920_DATA 0x00EF0000
+#define DDRSS_PHY_1921_DATA 0x00018011
+#define DDRSS_PHY_1922_DATA 0x0089FF00
+#define DDRSS_PHY_1923_DATA 0x20040006
diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
new file mode 100644
index 0000000..41692c8
--- /dev/null
+++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * phyCORE-AM62Ax dts file for SPLs
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ *
+ * Product homepage:
+ * https://www.phytec.com/product/phycore-am62ax
+ */
+
+#include "k3-am62a-phycore-som-binman.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &main_timer0;
+ };
+
+ aliases {
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ memory@80000000 {
+ bootph-all;
+ };
+};
+
+&cbass_main {
+ bootph-all;
+};
+
+&cbass_mcu {
+ bootph-all;
+};
+
+&cbass_wakeup {
+ bootph-all;
+};
+
+&chipid {
+ bootph-all;
+};
+
+&cpsw3g {
+ bootph-all;
+ ethernet-ports {
+ bootph-all;
+ };
+};
+
+&cpsw3g_mdio {
+ bootph-all;
+};
+
+&cpsw3g_phy1 {
+ bootph-all;
+};
+
+&cpsw3g_phy3 {
+ bootph-all;
+};
+
+&cpsw_port1 {
+ bootph-all;
+};
+
+&cpsw_port2 {
+ bootph-all;
+};
+
+&dmsc {
+ bootph-all;
+};
+
+&dmss {
+ bootph-all;
+};
+
+&fss {
+ bootph-all;
+};
+
+&k3_pds {
+ bootph-all;
+};
+
+&k3_clks {
+ bootph-all;
+};
+
+&k3_reset {
+ bootph-all;
+};
+
+&main_bcdma {
+ bootph-all;
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt", "cfg", "tchan", "rchan";
+};
+
+&main_conf {
+ bootph-all;
+};
+
+&main_gpio0 {
+ bootph-all;
+};
+
+&main_i2c0 {
+ bootph-all;
+};
+
+&main_i2c0_pins_default {
+ bootph-all;
+};
+
+&main_mdio1_pins_default {
+ bootph-all;
+};
+
+&main_mmc0_pins_default {
+ bootph-all;
+};
+
+&main_mmc1_pins_default {
+ bootph-all;
+};
+
+&main_pktdma {
+ bootph-all;
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x20000>,
+ <0x00 0x484a0000 0x00 0x4000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
+};
+
+&main_pmx0 {
+ bootph-all;
+};
+
+&main_rgmii1_pins_default {
+ bootph-all;
+};
+
+&main_timer0 {
+ bootph-all;
+};
+
+&main_uart0 {
+ bootph-all;
+};
+
+&main_uart0_pins_default {
+ bootph-all;
+};
+
+&main_uart1 {
+ bootph-all;
+};
+
+&mcu_pmx0 {
+ bootph-all;
+};
+
+&ospi0_pins_default {
+ bootph-all;
+};
+
+&ospi0 {
+ bootph-all;
+ flash@0 {
+ bootph-all;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x00000 0x80000>;
+ };
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x080000 0x200000>;
+ };
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x40000>;
+ };
+ partition@6c0000 {
+ label = "ospi.env.backup";
+ reg = <0x6c0000 0x40000>;
+ };
+ };
+ };
+};
+
+&phy_gmii_sel {
+ bootph-all;
+};
+
+&sdhci0 {
+ bootph-all;
+};
+
+&sdhci1 {
+ bootph-all;
+};
+
+&secure_proxy_main {
+ bootph-all;
+};
+
+&usbss0 {
+ bootph-all;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ bootph-all;
+};
+
+&vcc_3v3_mmc {
+ bootph-all;
+};
+
+&wkup_conf {
+ bootph-all;
+};
+
+&wkup_uart0 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
new file mode 100644
index 0000000..0060c7a
--- /dev/null
+++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * phyCORE-AM62Ax dts file for R5 SPL
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ *
+ * Product homepage:
+ * https://www.phytec.com/product/phycore-am62ax
+ */
+
+#include "k3-am62a7-phyboard-lyra-rdk.dts"
+#include "k3-am62a-phycore-som-ddr4-2gb.dtsi"
+#include "k3-am62a-ddr.dtsi"
+
+#include "k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ serial0 = &wkup_uart0;
+ serial3 = &main_uart1;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <36>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ bootph-pre-ram;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ bootph-pre-ram;
+ };
+};
+
+&cbass_main {
+ bootph-pre-ram;
+ sa3_secproxy: secproxy@44880000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg = <0x00 0x44880000 0x00 0x20000>,
+ <0x0 0x44860000 0x0 0x20000>,
+ <0x0 0x43600000 0x0 0x10000>;
+ reg-names = "rt", "scfg", "target_data";
+ bootph-pre-ram;
+ };
+
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>,
+ <&sa3_secproxy 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&main_bcdma {
+ ti,sci = <&dm_tifs>;
+};
+
+&main_pktdma {
+ ti,sci = <&dm_tifs>;
+};
+
+&main_pmx0 {
+ bootph-pre-ram;
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&mcu_pmx0 {
+ status = "okay";
+ bootph-pre-ram;
+
+ wkup_uart0_pins_default: wkup-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
+ AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
+ AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
+ AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
+ >;
+ bootph-pre-ram;
+ };
+};
+
+&ospi0 {
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x00 0x60000000 0x00 0x08000000>;
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "okay";
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index 464227b..49e6253 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -12,6 +12,7 @@
/ {
aliases {
+ tick-timer = &main_timer0;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
@@ -71,6 +72,15 @@
};
};
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ clocks-names;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clock-frequency = <25000000>;
+ bootph-pre-ram;
+};
+
&wkup_uart0_pins_default {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
index c42dec1..7dfbeb1 100644
--- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
@@ -9,7 +9,6 @@
/ {
chosen {
stdout-path = "serial2:115200n8";
- tick-timer = &main_timer0;
};
memory@80000000 {
@@ -17,10 +16,6 @@
};
};
-&main_timer0 {
- bootph-all;
-};
-
&cbass_main {
bootph-all;
};
diff --git a/arch/arm/dts/k3-am62p5-r5-sk.dts b/arch/arm/dts/k3-am62p5-r5-sk.dts
index baf1a83..b18b4ce 100644
--- a/arch/arm/dts/k3-am62p5-r5-sk.dts
+++ b/arch/arm/dts/k3-am62p5-r5-sk.dts
@@ -78,6 +78,14 @@
};
};
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ clocks-names;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clock-frequency = <25000000>;
+};
+
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
diff --git a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi
index 88d6c40..3710564 100644
--- a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi
@@ -118,6 +118,19 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ /*
+ * The GUID is generated dynamically by taking a namespace UUID and hashing
+ * it with the board compatible and fw_image name:
+ * mkeficapsule guidgen k3-am642-r5-phycore-som-2gb.dtb PHYCORE_AM64X_TIBOOT3
+ */
+ image-guid = "B0A6B4FA-5DF0-5CD1-90EC-B60BDE798486";
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_PHYCORE_AM64X_A53
@@ -502,4 +515,29 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+&capsule_tispl {
+ efi-capsule {
+ /*
+ * The GUID is generated dynamically by taking a namespace UUID and hashing
+ * it with the board compatible and fw_image name:
+ * mkeficapsule guidgen k3-am642-phyboard-electra-rdk.dtb PHYCORE_AM64X_SPL
+ */
+ image-guid = "D0F34382-C2C4-509C-A1D4-BC1CB1B992A8";
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ /*
+ * The GUID is generated dynamically by taking a namespace UUID and hashing
+ * it with the board compatible and fw_image name:
+ * mkeficapsule guidgen k3-am642-phyboard-electra-rdk.dtb PHYCORE_AM64X_UBOOT
+ */
+ image-guid = "0BB40539-DB41-5407-B4D4-EAD057FE10F4";
+ };
+};
+
#endif /* CONFIG_TARGET_PHYCORE_AM64X_A53 */
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
deleted file mode 100644
index 5ebb87f..0000000
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ /dev/null
@@ -1,1568 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC Family Main Domain peripherals
- *
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-#include <dt-bindings/phy/phy-am654-serdes.h>
-
-&cbass_main {
- msmc_ram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x0 0x70000000 0x0 0x200000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x70000000 0x200000>;
-
- atf-sram@0 {
- reg = <0x0 0x20000>;
- };
-
- sysfw-sram@f0000 {
- reg = <0xf0000 0x10000>;
- };
-
- l3cache-sram@100000 {
- reg = <0x100000 0x100000>;
- };
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0x90000>, /* GICR */
- <0x00 0x6f000000 0x00 0x2000>, /* GICC */
- <0x00 0x6f010000 0x00 0x1000>, /* GICH */
- <0x00 0x6f020000 0x00 0x2000>; /* GICV */
- /*
- * vcpumntirq:
- * virtual CPU interface maintenance interrupt
- */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- serdes0: serdes@900000 {
- compatible = "ti,phy-am654-serdes";
- reg = <0x0 0x900000 0x0 0x2000>;
- reg-names = "serdes";
- #phy-cells = <2>;
- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
- clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
- assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
- ti,serdes-clk = <&serdes0_clk>;
- #clock-cells = <1>;
- mux-controls = <&serdes_mux 0>;
- };
-
- serdes1: serdes@910000 {
- compatible = "ti,phy-am654-serdes";
- reg = <0x0 0x910000 0x0 0x2000>;
- reg-names = "serdes";
- #phy-cells = <2>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
- clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
- assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
- assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
- ti,serdes-clk = <&serdes1_clk>;
- #clock-cells = <1>;
- mux-controls = <&serdes_mux 1>;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- crypto: crypto@4e00000 {
- compatible = "ti,am654-sa2ul";
- reg = <0x0 0x4e00000 0x0 0x1200>;
- power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
-
- dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
- <&main_udmap 0x4003>;
- dma-names = "tx", "rx1", "rx2";
-
- rng: rng@4e10000 {
- compatible = "inside-secure,safexcel-eip76";
- reg = <0x0 0x4e10000 0x0 0x7d>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled"; /* Used by OP-TEE */
- };
- };
-
- /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
- main_timerio_input: pinctrl@104200 {
- compatible = "pinctrl-single";
- reg = <0x0 0x104200 0x0 0x30>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000001ff>;
- };
-
- /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
- main_timerio_output: pinctrl@104280 {
- compatible = "pinctrl-single";
- reg = <0x0 0x104280 0x0 0x20>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- };
-
- main_pmx0: pinctrl@11c000 {
- compatible = "pinctrl-single";
- reg = <0x0 0x11c000 0x0 0x2e4>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_pmx1: pinctrl@11c2e8 {
- compatible = "pinctrl-single";
- reg = <0x0 0x11c2e8 0x0 0x24>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_i2c0: i2c@2000000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2000000 0x0 0x100>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 110 1>;
- power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c1: i2c@2010000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2010000 0x0 0x100>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 111 1>;
- power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c2: i2c@2020000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2020000 0x0 0x100>;
- interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 112 1>;
- power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- main_i2c3: i2c@2030000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x2030000 0x0 0x100>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 113 1>;
- power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- ecap0: pwm@3100000 {
- compatible = "ti,am654-ecap", "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x0 0x03100000 0x0 0x60>;
- power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 39 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_spi0: spi@2100000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2100000 0x0 0x400>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 137 1>;
- power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
- dma-names = "tx0", "rx0";
- status = "disabled";
- };
-
- main_spi1: spi@2110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2110000 0x0 0x400>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 138 1>;
- power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- assigned-clocks = <&k3_clks 137 1>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- main_spi2: spi@2120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2120000 0x0 0x400>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 139 1>;
- power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- main_spi3: spi@2130000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2130000 0x0 0x400>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 140 1>;
- power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- main_spi4: spi@2140000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x2140000 0x0 0x400>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 141 1>;
- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- main_timer0: timer@2400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 23 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 23 0>;
- assigned-clock-parents = <&k3_clks 23 1>;
- power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 24 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 24 0>;
- assigned-clock-parents = <&k3_clks 24 1>;
- power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 27 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 27 0>;
- assigned-clock-parents = <&k3_clks 27 1>;
- power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 28 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 28 0>;
- assigned-clock-parents = <&k3_clks 28 1>;
- power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 29 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 29 0>;
- assigned-clock-parents = <&k3_clks 29 1>;
- power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 30 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 30 0>;
- assigned-clock-parents = <&k3_clks 30 1>;
- power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 31 0>;
- assigned-clocks = <&k3_clks 31 0>;
- assigned-clock-parents = <&k3_clks 31 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 32 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 32 0>;
- assigned-clock-parents = <&k3_clks 32 1>;
- power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer8: timer@2480000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2480000 0x00 0x400>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 33 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 33 0>;
- assigned-clock-parents = <&k3_clks 33 1>;
- power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer9: timer@2490000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2490000 0x00 0x400>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 34 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 34 0>;
- assigned-clock-parents = <&k3_clks 34 1>;
- power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer10: timer@24a0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24a0000 0x00 0x400>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 25 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 25 0>;
- assigned-clock-parents = <&k3_clks 25 1>;
- power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer11: timer@24b0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24b0000 0x00 0x400>;
- interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 26 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 26 0>;
- assigned-clock-parents = <&k3_clks 26 1>;
- power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- sdhci0: mmc@4f80000 {
- compatible = "ti,am654-sdhci-5.1";
- reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
- power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
- clock-names = "clk_ahb", "clk_xin";
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x5>;
- ti,otap-del-sel-ddr52 = <0x5>;
- ti,otap-del-sel-hs200 = <0x5>;
- ti,otap-del-sel-hs400 = <0x0>;
- ti,trm-icp = <0x8>;
- dma-coherent;
- };
-
- sdhci1: mmc@4fa0000 {
- compatible = "ti,am654-sdhci-5.1";
- reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
- clock-names = "clk_ahb", "clk_xin";
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x4>;
- ti,otap-del-sel-ddr52 = <0x4>;
- ti,otap-del-sel-hs200 = <0x7>;
- ti,clkbuf-sel = <0x7>;
- ti,trm-icp = <0x8>;
- dma-coherent;
- };
-
- scm_conf: scm-conf@100000 {
- compatible = "syscon", "simple-mfd";
- reg = <0 0x00100000 0 0x1c000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x00100000 0x1c000>;
-
- serdes0_clk: clock@4080 {
- compatible = "syscon";
- reg = <0x00004080 0x4>;
- };
-
- serdes1_clk: clock@4090 {
- compatible = "syscon";
- reg = <0x00004090 0x4>;
- };
-
- serdes_mux: mux-controller {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
- <0x4090 0x3>; /* SERDES1 lane select */
- };
-
- dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
- compatible = "syscon";
- reg = <0x000041e0 0x14>;
- };
-
- ehrpwm_tbclk: clock-controller@4140 {
- compatible = "ti,am654-ehrpwm-tbclk";
- reg = <0x4140 0x18>;
- #clock-cells = <1>;
- };
- };
-
- dwc3_0: dwc3@4000000 {
- compatible = "ti,am654-dwc3";
- reg = <0x0 0x4000000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x4000000 0x20000>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
- assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
- assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
- <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
-
- usb0: usb@10000 {
- compatible = "snps,dwc3";
- reg = <0x10000 0x10000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- phys = <&usb0_phy>;
- phy-names = "usb2-phy";
- snps,dis_u3_susphy_quirk;
- };
- };
-
- usb0_phy: phy@4100000 {
- compatible = "ti,am654-usb2", "ti,omap-usb2";
- reg = <0x0 0x4100000 0x0 0x54>;
- syscon-phy-power = <&scm_conf 0x4000>;
- clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
- clock-names = "wkupclk", "refclk";
- #phy-cells = <0>;
- };
-
- dwc3_1: dwc3@4020000 {
- compatible = "ti,am654-dwc3";
- reg = <0x0 0x4020000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x4020000 0x20000>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 152 2>;
- assigned-clocks = <&k3_clks 152 2>;
- assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
-
- usb1: usb@10000 {
- compatible = "snps,dwc3";
- reg = <0x10000 0x10000>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- phys = <&usb1_phy>;
- phy-names = "usb2-phy";
- };
- };
-
- usb1_phy: phy@4110000 {
- compatible = "ti,am654-usb2", "ti,omap-usb2";
- reg = <0x0 0x4110000 0x0 0x54>;
- syscon-phy-power = <&scm_conf 0x4020>;
- clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
- clock-names = "wkupclk", "refclk";
- #phy-cells = <0>;
- };
-
- intr_main_gpio: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x0 0x00a00000 0x0 0x400>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <100>;
- ti,interrupt-ranges = <0 392 32>;
- };
-
- main_navss: bus@30800000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
- dma-coherent;
- dma-ranges;
-
- ti,sci-dev-id = <118>;
-
- intr_main_navss: interrupt-controller@310e0000 {
- compatible = "ti,sci-intr";
- reg = <0x0 0x310e0000 0x0 0x2000>;
- ti,intr-trigger-type = <4>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <182>;
- ti,interrupt-ranges = <0 64 64>,
- <64 448 64>;
- };
-
- inta_main_udmass: interrupt-controller@33d00000 {
- compatible = "ti,sci-inta";
- reg = <0x0 0x33d00000 0x0 0x100000>;
- interrupt-controller;
- interrupt-parent = <&intr_main_navss>;
- msi-controller;
- #interrupt-cells = <0>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <179>;
- ti,interrupt-ranges = <0 0 256>;
- };
-
- secure_proxy_main: mailbox@32c00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x32c00000 0x00 0x100000>,
- <0x00 0x32400000 0x00 0x100000>,
- <0x00 0x32800000 0x00 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- hwspinlock: spinlock@30e00000 {
- compatible = "ti,am654-hwspinlock";
- reg = <0x00 0x30e00000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster0: mailbox@31f80000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f80000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster1: mailbox@31f81000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f81000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster2: mailbox@31f82000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f82000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster3: mailbox@31f83000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f83000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster4: mailbox@31f84000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f84000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster5: mailbox@31f85000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f85000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster6: mailbox@31f86000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f86000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster7: mailbox@31f87000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f87000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster8: mailbox@31f88000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f88000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster9: mailbox@31f89000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f89000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster10: mailbox@31f8a000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8a000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- mailbox0_cluster11: mailbox@31f8b000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f8b000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- status = "disabled";
- };
-
- ringacc: ringacc@3c000000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x3c000000 0x0 0x400000>,
- <0x0 0x38000000 0x0 0x400000>,
- <0x0 0x31120000 0x0 0x100>,
- <0x0 0x33000000 0x0 0x40000>,
- <0x0 0x31080000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- ti,num-rings = <818>;
- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <187>;
- msi-parent = <&inta_main_udmass>;
- };
-
- main_udmap: dma-controller@31150000 {
- compatible = "ti,am654-navss-main-udmap";
- reg = <0x0 0x31150000 0x0 0x100>,
- <0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&inta_main_udmass>;
- #dma-cells = <1>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <188>;
- ti,ringacc = <&ringacc>;
-
- ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
- <0xd>; /* TX_CHAN */
- ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
- <0xa>; /* RX_CHAN */
- ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
- };
-
- cpts@310d0000 {
- compatible = "ti,am65-cpts";
- reg = <0x0 0x310d0000 0x0 0x400>;
- reg-names = "cpts";
- clocks = <&main_cpts_mux>;
- clock-names = "cpts";
- interrupts-extended = <&intr_main_navss 391>;
- interrupt-names = "cpts";
- ti,cpts-periodic-outputs = <6>;
- ti,cpts-ext-ts-inputs = <8>;
-
- main_cpts_mux: refclk-mux {
- #clock-cells = <0>;
- clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
- <&k3_clks 118 6>, <&k3_clks 118 3>,
- <&k3_clks 118 8>, <&k3_clks 118 14>,
- <&k3_clks 120 3>, <&k3_clks 121 3>;
- assigned-clocks = <&main_cpts_mux>;
- assigned-clock-parents = <&k3_clks 118 5>;
- };
- };
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,am654-gpio", "ti,keystone-gpio";
- reg = <0x0 0x600000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&intr_main_gpio>;
- interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <96>;
- ti,davinci-gpio-unbanked = <0>;
- clocks = <&k3_clks 57 0>;
- clock-names = "gpio";
- };
-
- main_gpio1: gpio@601000 {
- compatible = "ti,am654-gpio", "ti,keystone-gpio";
- reg = <0x0 0x601000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&intr_main_gpio>;
- interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <90>;
- ti,davinci-gpio-unbanked = <0>;
- clocks = <&k3_clks 58 0>;
- clock-names = "gpio";
- };
-
- pcie0_rc: pcie@5500000 {
- compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
- reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
- <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&scm_conf 0x210>;
- ti,syscon-pcie-mode = <&scm_conf 0x4060>;
- bus-range = <0x0 0xff>;
- num-viewport = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
- msi-map = <0x0 &gic_its 0x0 0x10000>;
- device_type = "pci";
- status = "disabled";
- };
-
- pcie0_ep: pcie-ep@5500000 {
- compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
- reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&scm_conf 0x4060>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- pcie1_rc: pcie@5600000 {
- compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
- reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
- <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&scm_conf 0x210>;
- ti,syscon-pcie-mode = <&scm_conf 0x4070>;
- bus-range = <0x0 0xff>;
- num-viewport = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
- msi-map = <0x0 &gic_its 0x10000 0x10000>;
- device_type = "pci";
- status = "disabled";
- };
-
- pcie1_ep: pcie-ep@5600000 {
- compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
- reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&scm_conf 0x4070>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- max-link-speed = <2>;
- dma-coherent;
- interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- mcasp0: mcasp@2b00000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b00000 0x0 0x2000>,
- <0x0 0x02b08000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 104 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp1: mcasp@2b10000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b10000 0x0 0x2000>,
- <0x0 0x02b18000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 105 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp2: mcasp@2b20000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x0 0x02b20000 0x0 0x2000>,
- <0x0 0x02b28000 0x0 0x1000>;
- reg-names = "mpu","dat";
- interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 106 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- cal: cal@6f03000 {
- compatible = "ti,am654-cal";
- reg = <0x0 0x06f03000 0x0 0x400>,
- <0x0 0x06f03800 0x0 0x40>;
- reg-names = "cal_top",
- "cal_rx_core0";
- interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
- ti,camerrx-control = <&scm_conf 0x40c0>;
- clock-names = "fck";
- clocks = <&k3_clks 2 0>;
- power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- csi2_0: port@0 {
- reg = <0>;
- };
- };
- };
-
- dss: dss@4a00000 {
- compatible = "ti,am65x-dss";
- reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
- <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
- <0x0 0x04a06000 0x0 0x1000>, /* vid */
- <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
- <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
- <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
- <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2";
-
- ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
-
- power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
-
- clocks = <&k3_clks 67 1>,
- <&k3_clks 216 1>,
- <&k3_clks 67 2>;
- clock-names = "fck", "vp1", "vp2";
-
- /*
- * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
- * DIV1. See "Figure 12-3365. DSS Integration"
- * in AM65x TRM for details.
- */
- assigned-clocks = <&k3_clks 67 2>;
- assigned-clock-parents = <&k3_clks 67 5>;
-
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
-
- dma-coherent;
-
- dss_ports: ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- ehrpwm0: pwm@3000000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3000000 0x0 0x100>;
- power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm1: pwm@3010000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3010000 0x0 0x100>;
- power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm2: pwm@3020000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3020000 0x0 0x100>;
- power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm3: pwm@3030000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3030000 0x0 0x100>;
- power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm4: pwm@3040000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3040000 0x0 0x100>;
- power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ehrpwm5: pwm@3050000 {
- compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x3050000 0x0 0x100>;
- power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- icssg0: icssg@b000000 {
- compatible = "ti,am654-icssg";
- reg = <0x00 0xb000000 0x00 0x80000>;
- power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0xb000000 0x80000>;
-
- icssg0_mem: memories@0 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1",
- "shrdram2";
- };
-
- icssg0_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg0_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
- <&k3_clks 62 3>; /* icssg0_iclk */
- assigned-clocks = <&icssg0_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 62 3>;
- };
-
- icssg0_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */
- <&icssg0_coreclk_mux>; /* core_clk */
- assigned-clocks = <&icssg0_iepclk_mux>;
- assigned-clock-parents = <&icssg0_coreclk_mux>;
- };
- };
- };
-
- icssg0_iep0: iep@2e000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2e000 0x1000>;
- clocks = <&icssg0_iepclk_mux>;
- };
-
- icssg0_iep1: iep@2f000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2f000 0x1000>;
- clocks = <&icssg0_iepclk_mux>;
- };
-
- icssg0_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg0_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg0_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru0_0: pru@34000 {
- compatible = "ti,am654-pru";
- reg = <0x34000 0x4000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru0_0-fw";
- };
-
- rtu0_0: rtu@4000 {
- compatible = "ti,am654-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu0_0-fw";
- };
-
- tx_pru0_0: txpru@a000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru0_0-fw";
- };
-
- pru0_1: pru@38000 {
- compatible = "ti,am654-pru";
- reg = <0x38000 0x4000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru0_1-fw";
- };
-
- rtu0_1: rtu@6000 {
- compatible = "ti,am654-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu0_1-fw";
- };
-
- tx_pru0_1: txpru@c000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru0_1-fw";
- };
-
- icssg0_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- clocks = <&k3_clks 62 3>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <0>;
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-
- icssg1: icssg@b100000 {
- compatible = "ti,am654-icssg";
- reg = <0x00 0xb100000 0x00 0x80000>;
- power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0xb100000 0x80000>;
-
- icssg1_mem: memories@0 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1",
- "shrdram2";
- };
-
- icssg1_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg1_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
- <&k3_clks 63 3>; /* icssg1_iclk */
- assigned-clocks = <&icssg1_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 63 3>;
- };
-
- icssg1_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */
- <&icssg1_coreclk_mux>; /* core_clk */
- assigned-clocks = <&icssg1_iepclk_mux>;
- assigned-clock-parents = <&icssg1_coreclk_mux>;
- };
- };
- };
-
- icssg1_iep0: iep@2e000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2e000 0x1000>;
- clocks = <&icssg1_iepclk_mux>;
- };
-
- icssg1_iep1: iep@2f000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2f000 0x1000>;
- clocks = <&icssg1_iepclk_mux>;
- };
-
- icssg1_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg1_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg1_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru1_0: pru@34000 {
- compatible = "ti,am654-pru";
- reg = <0x34000 0x4000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru1_0-fw";
- };
-
- rtu1_0: rtu@4000 {
- compatible = "ti,am654-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu1_0-fw";
- };
-
- tx_pru1_0: txpru@a000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru1_0-fw";
- };
-
- pru1_1: pru@38000 {
- compatible = "ti,am654-pru";
- reg = <0x38000 0x4000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru1_1-fw";
- };
-
- rtu1_1: rtu@6000 {
- compatible = "ti,am654-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu1_1-fw";
- };
-
- tx_pru1_1: txpru@c000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru1_1-fw";
- };
-
- icssg1_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- clocks = <&k3_clks 63 3>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <0>;
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-
- icssg2: icssg@b200000 {
- compatible = "ti,am654-icssg";
- reg = <0x00 0xb200000 0x00 0x80000>;
- power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0xb200000 0x80000>;
-
- icssg2_mem: memories@0 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1",
- "shrdram2";
- };
-
- icssg2_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg2_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
- <&k3_clks 64 3>; /* icssg1_iclk */
- assigned-clocks = <&icssg2_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 64 3>;
- };
-
- icssg2_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */
- <&icssg2_coreclk_mux>; /* core_clk */
- assigned-clocks = <&icssg2_iepclk_mux>;
- assigned-clock-parents = <&icssg2_coreclk_mux>;
- };
- };
- };
-
- icssg2_iep0: iep@2e000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2e000 0x1000>;
- clocks = <&icssg2_iepclk_mux>;
- };
-
- icssg2_iep1: iep@2f000 {
- compatible = "ti,am654-icss-iep";
- reg = <0x2f000 0x1000>;
- clocks = <&icssg2_iepclk_mux>;
- };
-
- icssg2_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg2_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg2_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru2_0: pru@34000 {
- compatible = "ti,am654-pru";
- reg = <0x34000 0x4000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru2_0-fw";
- };
-
- rtu2_0: rtu@4000 {
- compatible = "ti,am654-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu2_0-fw";
- };
-
- tx_pru2_0: txpru@a000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru2_0-fw";
- };
-
- pru2_1: pru@38000 {
- compatible = "ti,am654-pru";
- reg = <0x38000 0x4000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-pru2_1-fw";
- };
-
- rtu2_1: rtu@6000 {
- compatible = "ti,am654-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-rtu2_1-fw";
- };
-
- tx_pru2_1: txpru@c000 {
- compatible = "ti,am654-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am65x-txpru2_1-fw";
- };
-
- icssg2_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- clocks = <&k3_clks 64 3>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <0>;
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
deleted file mode 100644
index edd5cfb..0000000
--- a/arch/arm/dts/k3-am65-mcu.dtsi
+++ /dev/null
@@ -1,440 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC Family MCU Domain peripherals
- *
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu {
- mcu_conf: scm-conf@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x40f00000 0x0 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x40f00000 0x20000>;
-
- phy_gmii_sel: phy@4040 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4040 0x4>;
- #phy-cells = <1>;
- };
- };
-
- /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
- mcu_timerio_input: pinctrl@40f04200 {
- compatible = "pinctrl-single";
- reg = <0x0 0x40f04200 0x0 0x10>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000101>;
- };
-
- /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
- mcu_timerio_output: pinctrl@40f04280 {
- compatible = "pinctrl-single";
- reg = <0x0 0x40f04280 0x0 0x8>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000003>;
- };
-
- mcu_uart0: serial@40a00000 {
- compatible = "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x100>;
- interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <96000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_ram: sram@41c00000 {
- compatible = "mmio-sram";
- reg = <0x00 0x41c00000 0x00 0x80000>;
- ranges = <0x0 0x00 0x41c00000 0x80000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- mcu_i2c0: i2c@40b00000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x0 0x40b00000 0x0 0x100>;
- interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 114 1>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcu_spi0: spi@40300000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x40300000 0x0 0x400>;
- interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 142 1>;
- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@40310000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x40310000 0x0 0x400>;
- interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 143 1>;
- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mcu_spi2: spi@40320000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x0 0x40320000 0x0 0x400>;
- interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 144 1>;
- power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- tscadc0: tscadc@40200000 {
- compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
- reg = <0x0 0x40200000 0x0 0x1000>;
- interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 0 2>;
- assigned-clocks = <&k3_clks 0 2>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- dmas = <&mcu_udmap 0x7100>,
- <&mcu_udmap 0x7101 >;
- dma-names = "fifo0", "fifo1";
- status = "disabled";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am654-adc", "ti,am3359-adc";
- };
- };
-
- tscadc1: tscadc@40210000 {
- compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
- reg = <0x0 0x40210000 0x0 0x1000>;
- interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 1 2>;
- assigned-clocks = <&k3_clks 1 2>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- dmas = <&mcu_udmap 0x7102>,
- <&mcu_udmap 0x7103>;
- dma-names = "fifo0", "fifo1";
- status = "disabled";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am654-adc", "ti,am3359-adc";
- };
- };
-
- /*
- * The MCU domain timer interrupts are routed only to the ESM module,
- * and not currently available for Linux. The MCU domain timers are
- * of limited use without interrupts, and likely reserved by the ESM.
- */
- mcu_timer0: timer@40400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40400000 0x00 0x400>;
- clocks = <&k3_clks 35 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer1: timer@40410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40410000 0x00 0x400>;
- clocks = <&k3_clks 36 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer2: timer@40420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40420000 0x00 0x400>;
- clocks = <&k3_clks 37 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer3: timer@40430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x40430000 0x00 0x400>;
- clocks = <&k3_clks 38 0>;
- clock-names = "fck";
- power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_navss: bus@28380000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
- dma-coherent;
- dma-ranges;
-
- ti,sci-dev-id = <119>;
-
- mcu_ringacc: ringacc@2b800000 {
- compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg",
- "proxy_target", "cfg";
- ti,num-rings = <286>;
- ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <195>;
- msi-parent = <&inta_main_udmass>;
- };
-
- mcu_udmap: dma-controller@285c0000 {
- compatible = "ti,am654-navss-mcu-udmap";
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
- msi-parent = <&inta_main_udmass>;
- #dma-cells = <1>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <194>;
- ti,ringacc = <&mcu_ringacc>;
-
- ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
- <0xd>; /* TX_CHAN */
- ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
- <0xa>; /* RX_CHAN */
- ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
- };
- };
-
- secure_proxy_mcu: mailbox@2a480000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x0 0x2a480000 0x0 0x80000>,
- <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- m_can0: can@40528000 {
- compatible = "bosch,m_can";
- reg = <0x0 0x40528000 0x0 0x400>,
- <0x0 0x40500000 0x0 0x4400>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
- clock-names = "hclk", "cclk";
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- m_can1: can@40568000 {
- compatible = "bosch,m_can";
- reg = <0x0 0x40568000 0x0 0x400>,
- <0x0 0x40540000 0x0 0x4400>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
- clock-names = "hclk", "cclk";
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- fss: bus@47000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ospi0: spi@47040000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x0 0x47040000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
- interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 248 0>;
- assigned-clocks = <&k3_clks 248 0>;
- assigned-clock-parents = <&k3_clks 248 2>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ospi1: spi@47050000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x0 0x47050000 0x0 0x100>,
- <0x7 0x00000000 0x1 0x00000000>;
- interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 249 6>;
- power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- mcu_cpsw: ethernet@46000000 {
- compatible = "ti,am654-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x0 0x46000000 0x0 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
- dma-coherent;
- clocks = <&k3_clks 5 10>;
- clock-names = "fck";
- power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&mcu_udmap 0xf000>,
- <&mcu_udmap 0xf001>,
- <&mcu_udmap 0xf002>,
- <&mcu_udmap 0xf003>,
- <&mcu_udmap 0xf004>,
- <&mcu_udmap 0xf005>,
- <&mcu_udmap 0xf006>,
- <&mcu_udmap 0xf007>,
- <&mcu_udmap 0x7000>;
- dma-names = "tx0", "tx1", "tx2", "tx3",
- "tx4", "tx5", "tx6", "tx7",
- "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
- phys = <&phy_gmii_sel 1>;
- };
- };
-
- davinci_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 5 10>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpts@3d000 {
- compatible = "ti,am65-cpts";
- reg = <0x0 0x3d000 0x0 0x400>;
- clocks = <&mcu_cpsw_cpts_mux>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
-
- mcu_cpsw_cpts_mux: refclk-mux {
- #clock-cells = <0>;
- clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
- <&k3_clks 118 6>, <&k3_clks 118 3>,
- <&k3_clks 118 8>, <&k3_clks 118 14>,
- <&k3_clks 120 3>, <&k3_clks 121 3>;
- assigned-clocks = <&mcu_cpsw_cpts_mux>;
- assigned-clock-parents = <&k3_clks 118 5>;
- };
- };
- };
-
- mcu_r5fss0: r5fss@41000000 {
- compatible = "ti,am654-r5fss";
- ti,cluster-mode = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x41000000 0x00 0x41000000 0x20000>,
- <0x41400000 0x00 0x41400000 0x20000>;
- power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
-
- mcu_r5fss0_core0: r5f@41000000 {
- compatible = "ti,am654-r5f";
- reg = <0x41000000 0x00008000>,
- <0x41010000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <159>;
- ti,sci-proc-ids = <0x01 0xff>;
- resets = <&k3_reset 159 1>;
- firmware-name = "am65x-mcu-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- mcu_r5fss0_core1: r5f@41400000 {
- compatible = "ti,am654-r5f";
- reg = <0x41400000 0x00008000>,
- <0x41410000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <245>;
- ti,sci-proc-ids = <0x02 0xff>;
- resets = <&k3_reset 245 1>;
- firmware-name = "am65x-mcu-r5f0_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- mcu_rti1: watchdog@40610000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x0 0x40610000 0x0 0x100>;
- clocks = <&k3_clks 135 0>;
- power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
- assigned-clocks = <&k3_clks 135 0>;
- assigned-clock-parents = <&k3_clks 135 4>;
- };
-};
diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi
deleted file mode 100644
index fd2b998..0000000
--- a/arch/arm/dts/k3-am65-wakeup.dtsi
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
- *
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_wakeup {
- dmsc: system-controller@44083000 {
- compatible = "ti,am654-sci";
- ti,host-id = <12>;
-
- mbox-names = "rx", "tx";
-
- mboxes = <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
-
- reg-names = "debug_messages";
- reg = <0x44083000 0x1000>;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- };
-
- k3_clks: clock-controller {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
- };
-
- chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x43000014 0x4>;
- };
-
- wkup_pmx0: pinctrl@4301c000 {
- compatible = "pinctrl-single";
- reg = <0x4301c000 0x118>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- wkup_uart0: serial@42300000 {
- compatible = "ti,am654-uart";
- reg = <0x42300000 0x100>;
- interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- wkup_i2c0: i2c@42120000 {
- compatible = "ti,am654-i2c", "ti,omap4-i2c";
- reg = <0x42120000 0x100>;
- interrupts = <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "fck";
- clocks = <&k3_clks 115 1>;
- power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- intr_wkup_gpio: interrupt-controller@42200000 {
- compatible = "ti,sci-intr";
- reg = <0x42200000 0x200>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <156>;
- ti,interrupt-ranges = <0 712 16>;
- };
-
- wkup_gpio0: gpio@42110000 {
- compatible = "ti,am654-gpio", "ti,keystone-gpio";
- reg = <0x42110000 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&intr_wkup_gpio>;
- interrupts = <60>, <61>, <62>, <63>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <56>;
- ti,davinci-gpio-unbanked = <0>;
- clocks = <&k3_clks 59 0>;
- clock-names = "gpio";
- };
-
- wkup_vtm0: temperature-sensor@42050000 {
- compatible = "ti,am654-vtm";
- reg = <0x42050000 0x25c>;
- power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-};
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
deleted file mode 100644
index 4d7b615..0000000
--- a/arch/arm/dts/k3-am65.dtsi
+++ /dev/null
@@ -1,110 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC Family
- *
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
- model = "Texas Instruments K3 AM654 SoC";
- compatible = "ti,am654";
- interrupt-parent = <&gic500>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- psci: psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
- };
-
- a53_timer0: timer-cl0-cpu0 {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
- };
-
- pmu: pmu {
- compatible = "arm,cortex-a53-pmu";
- /* Recommendation from GIC500 TRM Table A.3 */
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cbass_main: bus@100000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
- <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
- <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
- <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
- <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
- <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
- /* MCUSS Range */
- <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
- <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
- <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
- <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
- <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
- <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
-
- cbass_mcu: bus@28380000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
- <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
- <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
- <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
- <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
- <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
- <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
- <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
- <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
- <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
- <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
- <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
-
- cbass_wakeup: bus@42040000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- /* WKUP Basic peripherals */
- ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
- };
- };
- };
-};
-
-/* Now include the peripherals for each bus segments */
-#include "k3-am65-main.dtsi"
-#include "k3-am65-mcu.dtsi"
-#include "k3-am65-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts
deleted file mode 100644
index 1637ec5..0000000
--- a/arch/arm/dts/k3-am654-base-board.dts
+++ /dev/null
@@ -1,630 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-am654.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
- compatible = "ti,am654-evm", "ti,am654";
- model = "Texas Instruments AM654 Base Board";
-
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &main_i2c0;
- i2c3 = &main_i2c1;
- i2c4 = &main_i2c2;
- ethernet0 = &cpsw_port1;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: secure-ddr@9e800000 {
- reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
-
- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa0000000 0 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa0100000 0 0xf00000>;
- no-map;
- };
-
- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa1000000 0 0x100000>;
- no-map;
- };
-
- mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa1100000 0 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@a2000000 {
- reg = <0x00 0xa2000000 0x00 0x00100000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&push_button_pins_default>;
-
- switch-5 {
- label = "GPIO Key USER1";
- linux,code = <BTN_0>;
- gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
- };
-
- switch-6 {
- label = "GPIO Key USER2";
- linux,code = <BTN_1>;
- gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
- };
- };
-
- evm_12v0: regulator-0 {
- /* main supply */
- compatible = "regulator-fixed";
- regulator-name = "evm_12v0";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc3v3_io: regulator-1 {
- /* Output of TPS54334 */
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&evm_12v0>;
- };
-
- vdd_mmc1_sd: regulator-2 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vcc3v3_io>;
- gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
- };
-
- vtt_supply: regulator-3 {
- compatible = "regulator-fixed";
- regulator-name = "vtt";
- pinctrl-names = "default";
- pinctrl-0 = <&ddr_vtt_pins_default>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc3v3_io>;
- gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&wkup_pmx0 {
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
- AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
- AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
- >;
- };
-
- ddr_vtt_pins_default: ddr-vtt-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
- >;
- };
-
- wkup_i2c0_pins_default: wkup-i2c0-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
- >;
- };
-
- push_button_pins_default: push-button-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
- AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
- >;
- };
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
- AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
- AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
- AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
- AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
- AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
- AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
- AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
- AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
- AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
- AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
- >;
- };
-
- wkup_pca554_default: wkup-pca554-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
- >;
- };
-
- mcu_uart0_pins_default: mcu-uart0-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
- AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
- >;
- };
-
- mcu_cpsw_pins_default: mcu-cpsw-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
- AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
- AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
- AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
- AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
- AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
- AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
- AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
- AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
- AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
- AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
- AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
- >;
- };
-
- mcu_mdio_pins_default: mcu-mdio1-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
- AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
- >;
- };
-
- mcu_i2c0_pins_default: mcu-i2c0-default-pins {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */
- >;
- };
-};
-
-&main_pmx0 {
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
- >;
- };
-
- main_i2c2_pins_default: main-i2c2-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
- AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
- >;
- };
-
- main_spi0_pins_default: main-spi0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
- AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
- AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
- AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
- >;
- };
-
- main_mmc0_pins_default: main-mmc0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
- AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
- >;
- };
-
- usb1_pins_default: usb1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
- >;
- };
-};
-
-&main_pmx1 {
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
- AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
- AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
- >;
- };
-
- ecap0_pins_default: ecap0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
- >;
- };
-};
-
-&wkup_uart0 {
- /* Wakeup UART is used by System firmware */
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&mcu_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
-};
-
-&main_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&wkup_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@50 {
- /* AT24CM01 */
- compatible = "atmel,24c1024";
- reg = <0x50>;
- };
-
- vdd_mpu: regulator@60 {
- compatible = "ti,tps62363";
- reg = <0x60>;
- regulator-name = "VDD_MPU";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1770000>;
- regulator-always-on;
- regulator-boot-on;
- ti,vsel0-state-high;
- ti,vsel1-state-high;
- ti,enable-vout-discharge;
- };
-
- gpio@38 {
- compatible = "nxp,pca9554";
- reg = <0x38>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- pca9554: gpio@39 {
- compatible = "nxp,pca9554";
- reg = <0x39>;
- gpio-controller;
- #gpio-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_pca554_default>;
- interrupt-parent = <&wkup_gpio0>;
- interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-};
-
-&mcu_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_i2c0_pins_default>;
- clock-frequency = <400000>;
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- pca9555: gpio@21 {
- compatible = "nxp,pca9555";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
-};
-
-&main_i2c2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c2_pins_default>;
- clock-frequency = <400000>;
-};
-
-&ecap0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ecap0_pins_default>;
-};
-
-&main_spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_spi0_pins_default>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,pindir-d0-out-d1-in;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- spi-max-frequency = <48000000>;
- };
-};
-
-&sdhci0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
- bus-width = <8>;
- non-removable;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-/*
- * Because of erratas i2025 and i2026 for silicon revision 1.0, the
- * SD card interface might fail. Boards with sr1.0 are recommended to
- * disable sdhci1
- */
-&sdhci1 {
- vmmc-supply = <&vdd_mmc1_sd>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&usb1 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins_default>;
- dr_mode = "otg";
-};
-
-&dwc3_0 {
- status = "disabled";
-};
-
-&usb0_phy {
- status = "disabled";
-};
-
-&tscadc0 {
- status = "okay";
- adc {
- ti,adc-channels = <0 1 2 3 4 5 6 7>;
- };
-};
-
-&tscadc1 {
- status = "okay";
- adc {
- ti,adc-channels = <0 1 2 3 4 5 6 7>;
- };
-};
-
-&serdes0 {
- status = "disabled";
-};
-
-&serdes1 {
- status = "disabled";
-};
-
-&mailbox0_cluster0 {
- status = "okay";
- interrupts = <436>;
-
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-tx = <1 0 0>;
- ti,mbox-rx = <0 0 0>;
- };
-};
-
-&mailbox0_cluster1 {
- status = "okay";
- interrupts = <432>;
-
- mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
- ti,mbox-tx = <1 0 0>;
- ti,mbox-rx = <0 0 0>;
- };
-};
-
-&mcu_r5fss0_core0 {
- memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
- <&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
-};
-
-&mcu_r5fss0_core1 {
- memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
- <&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
-};
-
-&ospi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ospi.tiboot3";
- reg = <0x0 0x80000>;
- };
-
- partition@80000 {
- label = "ospi.tispl";
- reg = <0x80000 0x200000>;
- };
-
- partition@280000 {
- label = "ospi.u-boot";
- reg = <0x280000 0x400000>;
- };
-
- partition@680000 {
- label = "ospi.env";
- reg = <0x680000 0x20000>;
- };
-
- partition@6a0000 {
- label = "ospi.env.backup";
- reg = <0x6a0000 0x20000>;
- };
-
- partition@6c0000 {
- label = "ospi.sysfw";
- reg = <0x6c0000 0x100000>;
- };
-
- partition@800000 {
- label = "ospi.rootfs";
- reg = <0x800000 0x37c0000>;
- };
-
- partition@3fe0000 {
- label = "ospi.phypattern";
- reg = <0x3fe0000 0x20000>;
- };
- };
- };
-};
-
-&mcu_cpsw {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default>;
-};
-
-&davinci_mdio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_mdio_pins_default>;
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&phy0>;
-};
-
-&dss {
- status = "disabled";
-};
diff --git a/arch/arm/dts/k3-am654-icssg2.dtso b/arch/arm/dts/k3-am654-icssg2.dtso
deleted file mode 100644
index faefa2f..0000000
--- a/arch/arm/dts/k3-am654-icssg2.dtso
+++ /dev/null
@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/**
- * DT overlay for enabling ICSSG2 on AM654 EVM
- *
- * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-pinctrl.h"
-
-&{/} {
- aliases {
- ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
- ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
- };
-
- /* Ethernet node on PRU-ICSSG2 */
- icssg2_eth: icssg2-eth {
- compatible = "ti,am654-icssg-prueth";
- pinctrl-names = "default";
- pinctrl-0 = <&icssg2_rgmii_pins_default>;
- sram = <&msmc_ram>;
- ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
- <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
- firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
- "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
- "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
- "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
- "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
- "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
-
- ti,pruss-gp-mux-sel = <2>, /* MII mode */
- <2>,
- <2>,
- <2>, /* MII mode */
- <2>,
- <2>;
-
- ti,mii-g-rt = <&icssg2_mii_g_rt>;
- ti,mii-rt = <&icssg2_mii_rt>;
- ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
-
- interrupt-parent = <&icssg2_intc>;
- interrupts = <24 0 2>, <25 1 3>;
- interrupt-names = "tx_ts0", "tx_ts1";
-
- dmas = <&main_udmap 0xc300>, /* egress slice 0 */
- <&main_udmap 0xc301>, /* egress slice 0 */
- <&main_udmap 0xc302>, /* egress slice 0 */
- <&main_udmap 0xc303>, /* egress slice 0 */
- <&main_udmap 0xc304>, /* egress slice 1 */
- <&main_udmap 0xc305>, /* egress slice 1 */
- <&main_udmap 0xc306>, /* egress slice 1 */
- <&main_udmap 0xc307>, /* egress slice 1 */
- <&main_udmap 0x4300>, /* ingress slice 0 */
- <&main_udmap 0x4301>; /* ingress slice 1 */
-
- dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
- "tx1-0", "tx1-1", "tx1-2", "tx1-3",
- "rx0", "rx1";
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
- icssg2_emac0: port@0 {
- reg = <0>;
- phy-handle = <&icssg2_phy0>;
- phy-mode = "rgmii-id";
- ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
- /* Filled in by bootloader */
- local-mac-address = [00 00 00 00 00 00];
- };
- icssg2_emac1: port@1 {
- reg = <1>;
- phy-handle = <&icssg2_phy1>;
- phy-mode = "rgmii-id";
- ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
- /* Filled in by bootloader */
- local-mac-address = [00 00 00 00 00 00];
- };
- };
- };
-};
-
-&main_pmx0 {
-
- icssg2_mdio_pins_default: icssg2-mdio-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
- AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
- >;
- };
-
- icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
- AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
- AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
- AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
- AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
- AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
- AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
- AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
- AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
- AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
- AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
- AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
-
- AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
- AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
- AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
- AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
- AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
- AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
- AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
- AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
- AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
- AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
- AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
- AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
- >;
- };
-};
-
-&icssg2_mdio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&icssg2_mdio_pins_default>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg2_phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-
- icssg2_phy1: ethernet-phy@3 {
- reg = <3>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
diff --git a/arch/arm/dts/k3-am654-industrial-thermal.dtsi b/arch/arm/dts/k3-am654-industrial-thermal.dtsi
deleted file mode 100644
index 9021c73..0000000
--- a/arch/arm/dts/k3-am654-industrial-thermal.dtsi
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/thermal/thermal.h>
-
-mpu0_thermal: mpu0-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 0>;
-
- trips {
- mpu0_crit: mpu0-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
-
-mpu1_thermal: mpu1-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 1>;
-
- trips {
- mpu1_crit: mpu1-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
-
-mcu_thermal: mcu-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <500>; /* milliseconds */
- thermal-sensors = <&wkup_vtm0 2>;
-
- trips {
- mcu_crit: mcu-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
-};
diff --git a/arch/arm/dts/k3-am654.dtsi b/arch/arm/dts/k3-am654.dtsi
deleted file mode 100644
index 888567b..0000000
--- a/arch/arm/dts/k3-am654.dtsi
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC family in Quad core configuration
- *
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "k3-am65.dtsi"
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu-map {
- cluster0: cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
- };
-
- cluster1: cluster1 {
- core0 {
- cpu = <&cpu2>;
- };
-
- core1 {
- cpu = <&cpu3>;
- };
- };
- };
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53";
- reg = <0x000>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53";
- reg = <0x001>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- };
-
- cpu2: cpu@100 {
- compatible = "arm,cortex-a53";
- reg = <0x100>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_1>;
- };
-
- cpu3: cpu@101 {
- compatible = "arm,cortex-a53";
- reg = <0x101>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_1>;
- };
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- cache-size = <0x80000>;
- cache-line-size = <64>;
- cache-sets = <512>;
- next-level-cache = <&msmc_l3>;
- };
-
- L2_1: l2-cache1 {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- cache-size = <0x80000>;
- cache-line-size = <64>;
- cache-sets = <512>;
- next-level-cache = <&msmc_l3>;
- };
-
- msmc_l3: l3-cache0 {
- compatible = "cache";
- cache-level = <3>;
- cache-unified;
- };
-
- thermal_zones: thermal-zones {
- #include "k3-am654-industrial-thermal.dtsi"
- };
-};
diff --git a/arch/arm/dts/k3-am65x-binman.dtsi b/arch/arm/dts/k3-am65x-binman.dtsi
index d0cd488..350775e 100644
--- a/arch/arm/dts/k3-am65x-binman.dtsi
+++ b/arch/arm/dts/k3-am65x-binman.dtsi
@@ -95,10 +95,10 @@
#ifdef CONFIG_TARGET_AM654_A53_EVM
-#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
+#define SPL_AM654_EVM_DTB "spl/dts/ti/k3-am654-base-board.dtb"
#define AM654_EVM_DTB "u-boot.dtb"
-#define AM654_EVM_ICSSG2_DTBO "arch/arm/dts/k3-am654-icssg2.dtbo"
+#define AM654_EVM_ICSSG2_DTBO "ti/k3-am654-icssg2.dtbo"
&binman {
ti-spl {
diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
index 4b8d73a..4ca05f3 100644
--- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi
@@ -109,10 +109,6 @@
bootph-all;
};
-&ospi0 {
- status = "disabled";
-};
-
&ospi1 {
status = "disabled";
};
diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
index 3b2d7af..b61d22b 100644
--- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts
+++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
@@ -10,3 +10,8 @@
#include "k3-j721s2-ddr.dtsi"
#include "k3-am68-sk-base-board-u-boot.dtsi"
#include "k3-j721s2-r5.dtsi"
+
+&wkup_vtm0 {
+ bootph-pre-ram;
+ vdd-supply-2 = <&tps62873a>;
+};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index aeb5040..ecb1dd4 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -23,11 +23,12 @@
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
- clocks = <&k3_clks 61 1>, <&k3_clks 202 2>;
- clock-names = "gtc", "core";
- assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
- assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
- assigned-clock-rates = <2000000000>, <200000000>;
+ clocks = <&k3_clks 61 1>, <&k3_clks 202 2>, <&k3_clks 4 1> ;
+ clock-names = "gtc", "core", "msmc";
+ assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 4 1>,
+ <&k3_clks 323 0>;
+ assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>;
+ assigned-clock-rates = <2000000000>, <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
@@ -53,6 +54,10 @@
};
&mcu_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ clocks-names;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
clock-frequency = <250000000>;
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi
index 688a6cf..786a41c 100644
--- a/arch/arm/dts/k3-j721e-r5.dtsi
+++ b/arch/arm/dts/k3-j721e-r5.dtsi
@@ -42,7 +42,11 @@
};
&mcu_timer0 {
- status = "okay";
+ /delete-property/ clocks;
+ /delete-property/ clocks-names;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clock-frequency = <166666666>;
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index 506ad9b..09afdf3 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -13,6 +13,10 @@
&tps659411 {
bootph-pre-ram;
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
};
&wkup_vtm0 {
diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi
index 634676c..a820f51 100644
--- a/arch/arm/dts/k3-j721s2-r5.dtsi
+++ b/arch/arm/dts/k3-j721s2-r5.dtsi
@@ -43,6 +43,10 @@
};
&mcu_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ clocks-names;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
clock-frequency = <250000000>;
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-j722s-r5-evm.dts b/arch/arm/dts/k3-j722s-r5-evm.dts
index 5e5c2e3..08286ed 100644
--- a/arch/arm/dts/k3-j722s-r5-evm.dts
+++ b/arch/arm/dts/k3-j722s-r5-evm.dts
@@ -77,6 +77,14 @@
};
};
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ clocks-names;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ clock-frequency = <25000000>;
+};
+
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
status = "okay";
diff --git a/arch/arm/dts/k3-j784s4-r5.dtsi b/arch/arm/dts/k3-j784s4-r5.dtsi
index 0cd0ccc..a139411 100644
--- a/arch/arm/dts/k3-j784s4-r5.dtsi
+++ b/arch/arm/dts/k3-j784s4-r5.dtsi
@@ -41,7 +41,10 @@
};
&mcu_timer0 {
- status = "okay";
+ /delete-property/ clocks;
+ /delete-property/ clocks-names;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
clock-frequency = <250000000>;
bootph-pre-ram;
};
@@ -104,3 +107,9 @@
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
+
+&wkup_vtm0 {
+ bootph-pre-ram;
+ vdd-supply-2 = <&tps62873a>;
+};
+
diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi
deleted file mode 100644
index 648e7f4..0000000
--- a/arch/arm/dts/meson-a1.dtsi
+++ /dev/null
@@ -1,518 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- */
-
-#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
-#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
-#include <dt-bindings/gpio/meson-a1-gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/power/meson-a1-power.h>
-#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
-
-/ {
- compatible = "amlogic,a1";
-
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x0>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x1>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- };
- };
-
- efuse: efuse {
- compatible = "amlogic,meson-gxbb-efuse";
- clocks = <&clkc_periphs CLKID_OTP>;
- #address-cells = <1>;
- #size-cells = <1>;
- secure-monitor = <&sm>;
- power-domains = <&pwrc PWRC_OTP_ID>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- linux,cma {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x800000>;
- alignment = <0x0 0x400000>;
- linux,cma-default;
- };
- };
-
- sm: secure-monitor {
- compatible = "amlogic,meson-gxbb-sm";
-
- pwrc: power-controller {
- compatible = "amlogic,meson-a1-pwrc";
- #power-domain-cells = <1>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- spifc: spi@fd000400 {
- compatible = "amlogic,a1-spifc";
- reg = <0x0 0xfd000400 0x0 0x290>;
- clocks = <&clkc_periphs CLKID_SPIFC>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&pwrc PWRC_SPIFC_ID>;
- status = "disabled";
- };
-
- apb: bus@fe000000 {
- compatible = "simple-bus";
- reg = <0x0 0xfe000000 0x0 0x1000000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
-
- reset: reset-controller@0 {
- compatible = "amlogic,meson-a1-reset";
- reg = <0x0 0x0 0x0 0x8c>;
- #reset-cells = <1>;
- };
-
- periphs_pinctrl: pinctrl@400 {
- compatible = "amlogic,meson-a1-periphs-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio: bank@400 {
- reg = <0x0 0x0400 0x0 0x003c>,
- <0x0 0x0480 0x0 0x0118>;
- reg-names = "mux", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&periphs_pinctrl 0 0 62>;
- };
-
- i2c0_f11_pins: i2c0-f11 {
- mux {
- groups = "i2c0_sck_f11",
- "i2c0_sda_f12";
- function = "i2c0";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c0_f9_pins: i2c0-f9 {
- mux {
- groups = "i2c0_sck_f9",
- "i2c0_sda_f10";
- function = "i2c0";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_x_pins: i2c1-x {
- mux {
- groups = "i2c1_sck_x",
- "i2c1_sda_x";
- function = "i2c1";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_a_pins: i2c1-a {
- mux {
- groups = "i2c1_sck_a",
- "i2c1_sda_a";
- function = "i2c1";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_x0_pins: i2c2-x0 {
- mux {
- groups = "i2c2_sck_x0",
- "i2c2_sda_x1";
- function = "i2c2";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_x15_pins: i2c2-x15 {
- mux {
- groups = "i2c2_sck_x15",
- "i2c2_sda_x16";
- function = "i2c2";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_a4_pins: i2c2-a4 {
- mux {
- groups = "i2c2_sck_a4",
- "i2c2_sda_a5";
- function = "i2c2";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_a8_pins: i2c2-a8 {
- mux {
- groups = "i2c2_sck_a8",
- "i2c2_sda_a9";
- function = "i2c2";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c3_x_pins: i2c3-x {
- mux {
- groups = "i2c3_sck_x",
- "i2c3_sda_x";
- function = "i2c3";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c3_f_pins: i2c3-f {
- mux {
- groups = "i2c3_sck_f",
- "i2c3_sda_f";
- function = "i2c3";
- bias-pull-up;
- drive-strength-microamp = <3000>;
- };
- };
-
- uart_a_pins: uart-a {
- mux {
- groups = "uart_a_tx",
- "uart_a_rx";
- function = "uart_a";
- };
- };
-
- uart_a_cts_rts_pins: uart-a-cts-rts {
- mux {
- groups = "uart_a_cts",
- "uart_a_rts";
- function = "uart_a";
- bias-pull-down;
- };
- };
-
- sdio_pins: sdio {
- mux0 {
- groups = "sdcard_d0_x",
- "sdcard_d1_x",
- "sdcard_d2_x",
- "sdcard_d3_x",
- "sdcard_cmd_x";
- function = "sdcard";
- bias-pull-up;
- };
-
- mux1 {
- groups = "sdcard_clk_x";
- function = "sdcard";
- bias-disable;
- };
- };
-
- sdio_clk_gate_pins: sdio-clk-gate {
- mux {
- groups = "sdcard_clk_x";
- function = "sdcard";
- bias-pull-down;
- };
- };
-
- spifc_pins: spifc {
- mux {
- groups = "spif_mo",
- "spif_mi",
- "spif_clk",
- "spif_cs",
- "spif_hold_n",
- "spif_wp_n";
- function = "spif";
- };
- };
- };
-
- gpio_intc: interrupt-controller@440 {
- compatible = "amlogic,meson-a1-gpio-intc",
- "amlogic,meson-gpio-intc";
- reg = <0x0 0x0440 0x0 0x14>;
- interrupt-controller;
- #interrupt-cells = <2>;
- amlogic,channel-interrupts =
- <49 50 51 52 53 54 55 56>;
- };
-
- clkc_periphs: clock-controller@800 {
- compatible = "amlogic,a1-peripherals-clkc";
- reg = <0 0x800 0 0x104>;
- #clock-cells = <1>;
- clocks = <&clkc_pll CLKID_FCLK_DIV2>,
- <&clkc_pll CLKID_FCLK_DIV3>,
- <&clkc_pll CLKID_FCLK_DIV5>,
- <&clkc_pll CLKID_FCLK_DIV7>,
- <&clkc_pll CLKID_HIFI_PLL>,
- <&xtal>;
- clock-names = "fclk_div2", "fclk_div3",
- "fclk_div5", "fclk_div7",
- "hifi_pll", "xtal";
- };
-
- i2c0: i2c@1400 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x1400 0x0 0x20>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc_periphs CLKID_I2C_M_A>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- };
-
- uart_AO: serial@1c00 {
- compatible = "amlogic,meson-a1-uart",
- "amlogic,meson-ao-uart";
- reg = <0x0 0x1c00 0x0 0x18>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&xtal>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- uart_AO_B: serial@2000 {
- compatible = "amlogic,meson-a1-uart",
- "amlogic,meson-ao-uart";
- reg = <0x0 0x2000 0x0 0x18>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&xtal>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- saradc: adc@2c00 {
- compatible = "amlogic,meson-g12a-saradc",
- "amlogic,meson-saradc";
- reg = <0x0 0x2c00 0x0 0x48>;
- #io-channel-cells = <1>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>,
- <&clkc_periphs CLKID_SARADC_EN>,
- <&clkc_periphs CLKID_SARADC>,
- <&clkc_periphs CLKID_SARADC_SEL>;
- clock-names = "clkin", "core",
- "adc_clk", "adc_sel";
- status = "disabled";
- };
-
- i2c1: i2c@5c00 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x5c00 0x0 0x20>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc_periphs CLKID_I2C_M_B>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- };
-
- i2c2: i2c@6800 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x6800 0x0 0x20>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc_periphs CLKID_I2C_M_C>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- };
-
- i2c3: i2c@6c00 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x6c00 0x0 0x20>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc_periphs CLKID_I2C_M_D>;
- power-domains = <&pwrc PWRC_I2C_ID>;
- };
-
- usb2_phy1: phy@4000 {
- compatible = "amlogic,a1-usb2-phy";
- clocks = <&clkc_periphs CLKID_USB_PHY_IN>;
- clock-names = "xtal";
- reg = <0x0 0x4000 0x0 0x60>;
- resets = <&reset RESET_USBPHY>;
- reset-names = "phy";
- #phy-cells = <0>;
- power-domains = <&pwrc PWRC_USB_ID>;
- };
-
- hwrng: rng@5118 {
- compatible = "amlogic,meson-rng";
- reg = <0x0 0x5118 0x0 0x4>;
- power-domains = <&pwrc PWRC_OTP_ID>;
- };
-
- sec_AO: ao-secure@5a20 {
- compatible = "amlogic,meson-gx-ao-secure", "syscon";
- reg = <0x0 0x5a20 0x0 0x140>;
- amlogic,has-chip-id;
- };
-
- clkc_pll: pll-clock-controller@7c80 {
- compatible = "amlogic,a1-pll-clkc";
- reg = <0 0x7c80 0 0x18c>;
- #clock-cells = <1>;
- clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
- <&clkc_periphs CLKID_HIFIPLL_IN>;
- clock-names = "fixpll_in", "hifipll_in";
- };
-
- sd_emmc: sd@10000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0x10000 0x0 0x800>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
- <&clkc_periphs CLKID_SD_EMMC>,
- <&clkc_pll CLKID_FCLK_DIV2>;
- clock-names = "core",
- "clkin0",
- "clkin1";
- assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
- assigned-clock-parents = <&xtal>;
- resets = <&reset RESET_SD_EMMC_A>;
- power-domains = <&pwrc PWRC_SD_EMMC_ID>;
- status = "disabled";
- };
- };
-
- usb: usb@fe004400 {
- status = "disabled";
- compatible = "amlogic,meson-a1-usb-ctrl";
- reg = <0x0 0xfe004400 0x0 0xa0>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&clkc_periphs CLKID_USB_CTRL>,
- <&clkc_periphs CLKID_USB_BUS>,
- <&clkc_periphs CLKID_USB_CTRL_IN>;
- clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
- resets = <&reset RESET_USBCTRL>;
- reset-name = "usb_ctrl";
-
- dr_mode = "otg";
-
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy1";
-
- dwc3: usb@ff400000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xff400000 0x0 0x100000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,dis_u2_susphy_quirk;
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,parkmode-disable-ss-quirk;
- };
-
- dwc2: usb@ff500000 {
- compatible = "amlogic,meson-a1-usb", "snps,dwc2";
- reg = <0x0 0xff500000 0x0 0x40000>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy";
- clocks = <&clkc_periphs CLKID_USB_PHY>;
- clock-names = "otg";
- dr_mode = "peripheral";
- g-rx-fifo-size = <192>;
- g-np-tx-fifo-size = <128>;
- g-tx-fifo-size = <128 128 16 16 16>;
- };
- };
-
- gic: interrupt-controller@ff901000 {
- compatible = "arm,gic-400";
- reg = <0x0 0xff901000 0x0 0x1000>,
- <0x0 0xff902000 0x0 0x2000>,
- <0x0 0xff904000 0x0 0x2000>,
- <0x0 0xff906000 0x0 0x2000>;
- interrupt-controller;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- #interrupt-cells = <3>;
- #address-cells = <0>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- xtal: xtal-clk {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xtal";
- #clock-cells = <0>;
- };
-};
diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
index c3704d7..531767c 100644
--- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
@@ -13,6 +13,14 @@
};
};
+&avb1 {
+ status = "disabled";
+};
+
+&avb2 {
+ status = "disabled";
+};
+
&rpc {
flash@0 {
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
old mode 100755
new mode 100644
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
old mode 100755
new mode 100644
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
old mode 100755
new mode 100644
diff --git a/arch/arm/dts/zynqmp-binman-mini.dts b/arch/arm/dts/zynqmp-binman-mini.dts
new file mode 100644
index 0000000..8f3d18e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-binman-mini.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp-u-boot.dtsi"
diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts
new file mode 100644
index 0000000..3d9d847
--- /dev/null
+++ b/arch/arm/dts/zynqmp-binman-som.dts
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SOMs (k24/k26)
+ *
+ * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <config.h>
+
+/dts-v1/;
+/ {
+ binman: binman {
+ multiple-images;
+ fit-dtb.blob {
+ filename = "fit-dtb.blob";
+ pad-byte = <0>;
+ fit {
+ fit,align = <0x8>;
+ fit,external-offset = <0x0>;
+ description = "DTBs for SOMs+CCs";
+ fit,fdt-list-val = "zynqmp-smk-k26-revA", "zynqmp-smk-k26-revA-sck-kr-g-revA",
+ "zynqmp-smk-k26-revA-sck-kr-g-revB", "zynqmp-smk-k26-revA-sck-kv-g-revA",
+ "zynqmp-smk-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kv-g-revA",
+ "zynqmp-sm-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kr-g-revB",
+ "zynqmp-smk-k24-revA-sck-kd-g-revA", "zynqmp-smk-k24-revA-sck-kv-g-revB",
+ "zynqmp-smk-k24-revA-sck-kr-g-revB", "zynqmp-sm-k24-revA-sck-kd-g-revA",
+ "zynqmp-sm-k24-revA-sck-kv-g-revB", "zynqmp-sm-k24-revA-sck-kr-g-revB";
+
+ images {
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ hash-1 {
+ algo = "md5";
+ };
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ description = "SOM itself";
+ fdt = "fdt-1";
+ };
+ conf-2 {
+ description = "zynqmp-smk-k26-.*-sck-kr-g-revA";
+ fdt = "fdt-2";
+ };
+ conf-3 {
+ description = "zynqmp-smk-k26-.*-sck-kr-g-.*";
+ fdt = "fdt-3";
+ };
+ conf-4 {
+ description = "zynqmp-smk-k26-.*-sck-kv-g-rev[AZ]";
+ fdt = "fdt-4";
+ };
+ conf-5 {
+ description = "zynqmp-smk-k26-.*-sck-kv-g-.*";
+ fdt = "fdt-5";
+ };
+ conf-6 {
+ description = "zynqmp-sm-k26-.*-sck-kv-g-rev[AZ]";
+ fdt = "fdt-6";
+ };
+ conf-7 {
+ description = "zynqmp-sm-k26-.*-sck-kv-g-.*";
+ fdt = "fdt-7";
+ };
+ conf-8 {
+ description = "zynqmp-sm-k26-.*-sck-kr-g-.*";
+ fdt = "fdt-8";
+ };
+ conf-9 {
+ description = "zynqmp-smk-k24-.*-sck-kd-g-.*";
+ fdt = "fdt-9";
+ };
+ conf-10 {
+ description = "zynqmp-smk-k24-.*-sck-kv-g-.*";
+ fdt = "fdt-10";
+ };
+ conf-11 {
+ description = "zynqmp-smk-k24-.*-sck-kr-g-.*";
+ fdt = "fdt-11";
+ };
+ conf-12 {
+ description = "zynqmp-sm-k24-.*-sck-kd-g-.*";
+ fdt = "fdt-12";
+ };
+ conf-13 {
+ description = "zynqmp-sm-k24-.*-sck-kv-g-.*";
+ fdt = "fdt-13";
+ };
+ conf-14 {
+ description = "zynqmp-sm-k24-.*-sck-kr-g-.*";
+ fdt = "fdt-14";
+ };
+ };
+ };
+ };
+
+ /* u-boot.itb generation in a static way */
+ itb {
+ filename = "u-boot.itb";
+ pad-byte = <0>;
+
+ fit {
+ description = "Configuration for Xilinx ZynqMP SoC";
+ fit,align = <0x8>;
+ fit,external-offset = <0x0>;
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm64";
+ compression = "none";
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
+ entry = /bits/ 64 <CONFIG_TEXT_BASE>;
+ hash {
+ algo = "md5";
+ };
+ u-boot-nodtb {
+ };
+ };
+ atf {
+ description = "Trusted Firmware-A";
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ hash {
+ algo = "md5";
+ };
+ atf-bl31 {
+ optional;
+ };
+ };
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ tee-os {
+ optional;
+ };
+ };
+ fdt {
+ description = "Multi DTB fit image";
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0 0x100000>;
+ hash {
+ algo = "md5";
+ };
+ fdt-blob {
+ filename = "fit-dtb.blob";
+ type = "blob-ext";
+ };
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ description = "Multi DTB with TF-A/TEE";
+ firmware = "atf";
+ loadables = "tee", "uboot", "fdt";
+ };
+ };
+ };
+ };
+
+ /* boot.bin generated with version string inside */
+ bootimage {
+ filename = "boot.bin";
+ pad-byte = <0>;
+
+ blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl/boot.bin";
+ };
+ /* Optional version string at offset 0x70 */
+ blob-ext@2 {
+ offset = <0x70>;
+ filename = "version.bin";
+ overlap;
+ optional;
+ };
+ /* Optional version string at offset 0x94 */
+ blob-ext@3 {
+ offset = <0x94>;
+ filename = "version.bin";
+ overlap;
+ optional;
+ };
+ };
+
+#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS
+ /* Full QSPI image for recovery app */
+ image {
+ filename = "qspi.bin";
+ pad-byte = <0>;
+
+ blob-ext@1 {
+ offset = <0x0>;
+ filename = "boot.bin";
+ };
+ blob-ext@2 {
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+ filename = "u-boot.itb";
+ };
+ fdtmap {
+ };
+ };
+#endif
+ };
+};
diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts
new file mode 100644
index 0000000..675f6bf
--- /dev/null
+++ b/arch/arm/dts/zynqmp-binman.dts
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP platforms
+ *
+ * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <config.h>
+
+/dts-v1/;
+/ {
+ binman: binman {
+ multiple-images;
+
+ /* u-boot.itb generation in a static way */
+ itb {
+ filename = "u-boot.itb";
+ pad-byte = <0>;
+
+ fit {
+ description = "Configuration for Xilinx ZynqMP SoC";
+ fit,align = <0x8>;
+ fit,external-offset = <0x0>;
+ fit,fdt-list = "of-list";
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm64";
+ compression = "none";
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
+ entry = /bits/ 64 <CONFIG_TEXT_BASE>;
+ hash {
+ algo = "md5";
+ };
+ u-boot-nodtb {
+ };
+ };
+ atf {
+ description = "Trusted Firmware-A";
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ hash {
+ algo = "md5";
+ };
+ atf-bl31 {
+ optional;
+ };
+ };
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ tee-os {
+ optional;
+ };
+ };
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0 0x100000>;
+ hash-1 {
+ algo = "md5";
+ };
+ };
+ };
+ configurations {
+ default = "@conf-DEFAULT-SEQ";
+ @conf-SEQ {
+ description = "NAME";
+ firmware = "atf";
+ loadables = "tee", "uboot";
+ fdt = "fdt-SEQ";
+ };
+ };
+ };
+ };
+
+ itb-single {
+ filename = "u-boot-single.itb";
+ pad-byte = <0>;
+
+ fit {
+ description = "Configuration for Xilinx ZynqMP SoC";
+ fit,align = <0x8>;
+ fit,external-offset = <0x0>;
+ fit,fdt-list = "of-list";
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm64";
+ compression = "none";
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
+ entry = /bits/ 64 <CONFIG_TEXT_BASE>;
+ hash {
+ algo = "md5";
+ };
+ u-boot-nodtb {
+ };
+ };
+ atf {
+ description = "Trusted Firmware-A";
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ hash {
+ algo = "md5";
+ };
+ atf-bl31 {
+ optional;
+ };
+ };
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+ tee-os {
+ optional;
+ };
+ };
+ fdt {
+ description = "DT";
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0 0x100000>;
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
+ hash-1 {
+ algo = "md5";
+ };
+
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ description = "Single DT";
+ firmware = "atf";
+ loadables = "tee", "uboot";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+
+#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS
+ /* QSPI image for testing QSPI boot mode */
+ image {
+ filename = "qspi.bin";
+ pad-byte = <0>;
+
+ blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl/boot.bin";
+ };
+ blob-ext@2 {
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+ filename = "u-boot.itb";
+ };
+ fdtmap {
+ };
+ };
+
+ image-single {
+ filename = "qspi-single.bin";
+ pad-byte = <0>;
+
+ blob-ext@1 {
+ offset = <0x0>;
+ filename = "spl/boot.bin";
+ };
+ blob-ext@2 {
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+ filename = "u-boot-single.itb";
+ };
+ fdtmap {
+ };
+ };
+#endif
+ };
+};
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index dd4569e..60d1b1a 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -70,6 +70,22 @@
clocks = <&zynqmp_clk ACPU>;
};
+&cpu0_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu1_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu2_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu3_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
&fpd_dma_chan1 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
index 4de29d5..d56e863 100644
--- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -80,7 +80,10 @@
"", "";
};
- /* usb5744@2d */
+ hub: usb-hub@2d { /* u36 */
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
};
/* USB 3.0 */
@@ -99,18 +102,6 @@
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
-#if 0
- usbhub0: usb-hub { /* u36 */
- i2c-bus = <&i2c1>;
- compatible = "microchip,usb5744";
- reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
- };
-
- usb2244: usb-sd { /* u41 */
- compatible = "microchip,usb2244";
- reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
- };
-#endif
};
&dwc3_0 {
@@ -118,6 +109,26 @@
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ i2c-bus = <&hub>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ i2c-bus = <&hub>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
};
&gem1 { /* mdio mio50/51 */
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index 6349a0e..9d0c0c2 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -105,11 +105,19 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+ hub_1: usb-hub@2d {
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
};
usbhub_i2c1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+ hub_2: usb-hub@2d {
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
};
/* Bus 2/3 are not connected */
};
@@ -145,18 +153,6 @@
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
-#if 0
- usbhub0: usb-hub { /* u43 */
- i2c-bus = <&usbhub_i2c0>;
- compatible = "microchip,usb5744";
- reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
- };
-
- usb2244: usb-sd { /* u38 */
- compatible = "microchip,usb2244";
- reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
- };
-#endif
};
&dwc3_0 {
@@ -164,6 +160,26 @@
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ i2c-bus = <&hub_1>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ i2c-bus = <&hub_1>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
};
&usb1 { /* mio64 - mio75 */
@@ -174,13 +190,6 @@
phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
-#if 0
- usbhub1: usb-hub { /* u84 */
- i2c-bus = <&usbhub_i2c1>;
- compatible = "microchip,usb5744";
- reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
- };
-#endif
};
&dwc3_1 {
@@ -188,6 +197,26 @@
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub1_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub1_3_0>;
+ i2c-bus = <&hub_2>;
+ reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub1_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub1_2_0>;
+ i2c-bus = <&hub_2>;
+ reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+ };
};
&gem0 { /* mdio mio50/51 */
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index b0d737d..0d915d4 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -117,11 +117,19 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+ hub_1: usb-hub@2d {
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
};
usbhub_i2c1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+ hub_2: usb-hub@2d {
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
};
/* Bus 2/3 are not connected */
};
@@ -165,18 +173,6 @@
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
-#if 0
- usbhub0: usb-hub { /* u43 */
- i2c-bus = <&usbhub_i2c0>;
- compatible = "microchip,usb5744";
- reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
- };
-
- usb2244: usb-sd { /* u38 */
- compatible = "microchip,usb2244";
- reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
- };
-#endif
};
&dwc3_0 {
@@ -184,6 +180,26 @@
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ i2c-bus = <&hub_1>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ i2c-bus = <&hub_1>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
};
&usb1 { /* mio64 - mio75 */
@@ -194,14 +210,6 @@
phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
assigned-clock-rates = <250000000>, <20000000>;
-
-#if 0
- usbhub1: usb-hub { /* u84 */
- i2c-bus = <&usbhub_i2c1>;
- compatible = "microchip,usb5744";
- reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
- };
-#endif
};
&dwc3_1 {
@@ -209,6 +217,26 @@
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub1_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub1_3_0>;
+ i2c-bus = <&hub_2>;
+ reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub1_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub1_2_0>;
+ i2c-bus = <&hub_2>;
+ reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+ };
};
&gem0 { /* mdio mio50/51 */
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
index 561b546..a98a888 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
@@ -129,12 +129,6 @@
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
-#if 0
- usbhub: usb5744 { /* u43 */
- compatible = "microchip,usb5744";
- reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
- };
-#endif
};
&dwc3_0 {
@@ -142,6 +136,24 @@
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+ };
};
&sdhci1 { /* on CC with tuned parameters */
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
index 64683e0..7490efe 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
@@ -92,7 +92,10 @@
label = "ina260-u14";
reg = <0x40>;
};
- /* u43 - 0x2d - USB hub */
+ hub: usb-hub@2d {
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
@@ -131,14 +134,6 @@
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
assigned-clock-rates = <250000000>, <20000000>;
-#if 0
- usb5744: usb-hub { /* u43 */
- status = "okay";
- compatible = "microchip,usb5744";
- i2c-bus = <&i2c1>;
- reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
- };
-#endif
};
&dwc3_0 {
@@ -146,6 +141,26 @@
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ i2c-bus = <&hub>;
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ i2c-bus = <&hub>;
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+ };
};
&sdhci1 { /* on CC with tuned parameters */
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 8c43ade..620f518 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts
index 719a4e4..b804abe 100644
--- a/arch/arm/dts/zynqmp-smk-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
diff --git a/arch/arm/dts/zynqmp-u-boot.dtsi b/arch/arm/dts/zynqmp-u-boot.dtsi
new file mode 100644
index 0000000..9a7527e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/ {
+ binman: binman {
+ };
+};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 3132fa5..dd63d22 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -960,6 +960,7 @@
&pcie {
status = "okay";
+ phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
};
&psgtr {
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index 095c972..b75b2a7 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -15,8 +15,7 @@
/ {
model = "ZynqMP ZCU1275 RevA";
- compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275",
- "xlnx,zynqmp";
+ compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
aliases {
serial0 = &uart0;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 6a29f61..70ca5e6 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -168,8 +168,8 @@
bootph-all;
};
- pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
@@ -441,6 +441,34 @@
};
};
+ cpu0_debug: debug@fec10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfec10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
+
+ cpu1_debug: debug@fed10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfed10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ };
+
+ cpu2_debug: debug@fee10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfee10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ };
+
+ cpu3_debug: debug@fef10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfef10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ };
+
/* GDMA */
fpd_dma_chan1: dma-controller@fd500000 {
status = "disabled";
@@ -885,7 +913,6 @@
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
/* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
- /* dma-coherent; */
};
sdhci0: mmc@ff160000 {
@@ -1065,9 +1092,9 @@
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ref";
/* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
- clock-names = "ref";
snps,resume-hs-terminations;
/* dma-coherent; */
};
@@ -1097,9 +1124,9 @@
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ref";
/* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
- clock-names = "ref";
snps,resume-hs-terminations;
/* dma-coherent; */
};
@@ -1176,11 +1203,14 @@
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;
resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
- dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dma-names = "vid0", "vid1", "vid2", "gfx0",
+ "aud0", "aud1";
dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
- <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
+ <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>;
ports {
#address-cells = <1>;
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index b0468a1..0d7a573 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -71,6 +71,11 @@
#define MXC_CPU_IMX9302 0xC9 /* dummy ID */
#define MXC_CPU_IMX9301 0xCA /* dummy ID */
+#define MXC_CPU_IMX91 0xCB /* dummy ID */
+#define MXC_CPU_IMX9121 0xCC /* dummy ID */
+#define MXC_CPU_IMX9111 0xCD /* dummy ID */
+#define MXC_CPU_IMX9101 0xCE /* dummy ID */
+
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
#define MXC_SOC_IMX8M 0x80
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
index 76f1211..60d48b1 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -205,10 +205,17 @@
u32 mux_type;
};
+enum clk_soc {
+ CLK_SOC_ALL = 0,
+ CLK_SOC_IMX93 = 1,
+ CLK_SOC_IMX91 = 2,
+};
+
struct imx_clk_setting {
u32 clk_root;
enum ccm_clk_src src;
u32 div;
+ enum clk_soc soc;
};
int clock_init_early(void);
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h
index 4073202..ca763f5 100644
--- a/arch/arm/include/asm/arch-imx9/gpio.h
+++ b/arch/arm/include/asm/arch-imx9/gpio.h
@@ -6,6 +6,8 @@
#ifndef __ASM_ARCH_IMX9_GPIO_H
#define __ASM_ARCH_IMX9_GPIO_H
+#include <linux/types.h>
+
struct gpio_regs {
u32 gpio_pdor;
u32 gpio_psor;
diff --git a/arch/arm/include/asm/arch-imx9/imx91_pins.h b/arch/arm/include/asm/arch-imx9/imx91_pins.h
new file mode 100644
index 0000000..2624670
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx91_pins.h
@@ -0,0 +1,770 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX91_PINS_H__
+#define __ASM_ARCH_IMX91_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+ MX91_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x01B0, 0x0000, 0x00, 0x03D8, 0x00, 0x00),
+ MX91_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x01B0, 0x0000, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x01B0, 0x0000, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x01B0, 0x0000, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TDI__GPIO3_IO28 = IOMUX_PAD(0x01B0, 0x0000, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TDI__LPUART5_RX = IOMUX_PAD(0x01B0, 0x0000, 0x06, 0x0488, 0x00, 0x00),
+
+ MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS = IOMUX_PAD(0x01B4, 0x0004, 0x00, 0x03DC, 0x00, 0x00),
+ MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 = IOMUX_PAD(0x01B4, 0x0004, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 = IOMUX_PAD(0x01B4, 0x0004, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B = IOMUX_PAD(0x01B4, 0x0004, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK = IOMUX_PAD(0x01B8, 0x0008, 0x00, 0x03D4, 0x00, 0x00),
+ MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 = IOMUX_PAD(0x01B8, 0x0008, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 = IOMUX_PAD(0x01B8, 0x0008, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B = IOMUX_PAD(0x01B8, 0x0008, 0x06, 0x0484, 0x00, 0x00),
+
+ MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO = IOMUX_PAD(0x01BC, 0x000C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT = IOMUX_PAD(0x01BC, 0x000C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX = IOMUX_PAD(0x01BC, 0x000C, 0x03, 0x0364, 0x00, 0x00),
+ MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 = IOMUX_PAD(0x01BC, 0x000C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 = IOMUX_PAD(0x01BC, 0x000C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX = IOMUX_PAD(0x01BC, 0x000C, 0x06, 0x048C, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO00__GPIO2_IO0 = IOMUX_PAD(0x01C0, 0x0010, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO00__LPI2C3_SDA = IOMUX_PAD(0x01C0, 0x0010, 0x01, 0x03F4, 0x00, 0x00),
+ MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x01C0, 0x0010, 0x02, 0x04BC, 0x00, 0x00),
+ MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK = IOMUX_PAD(0x01C0, 0x0010, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO00__LPSPI6_PCS0 = IOMUX_PAD(0x01C0, 0x0010, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO00__LPUART5_TX = IOMUX_PAD(0x01C0, 0x0010, 0x05, 0x048C, 0x01, 0x00),
+ MX91_PAD_GPIO_IO00__LPI2C5_SDA = IOMUX_PAD(0x01C0, 0x0010, 0x06, 0x0404, 0x00, 0x00),
+ MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 = IOMUX_PAD(0x01C0, 0x0010, 0x07, 0x036C, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO01__GPIO2_IO1 = IOMUX_PAD(0x01C4, 0x0014, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO01__LPI2C3_SCL = IOMUX_PAD(0x01C4, 0x0014, 0x01, 0x03F0, 0x00, 0x00),
+ MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 = IOMUX_PAD(0x01C4, 0x0014, 0x02, 0x0490, 0x00, 0x00),
+ MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE = IOMUX_PAD(0x01C4, 0x0014, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO01__LPSPI6_SIN = IOMUX_PAD(0x01C4, 0x0014, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO01__LPUART5_RX = IOMUX_PAD(0x01C4, 0x0014, 0x05, 0x0488, 0x01, 0x00),
+ MX91_PAD_GPIO_IO01__LPI2C5_SCL = IOMUX_PAD(0x01C4, 0x0014, 0x06, 0x0400, 0x00, 0x00),
+ MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 = IOMUX_PAD(0x01C4, 0x0014, 0x07, 0x0370, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO02__GPIO2_IO2 = IOMUX_PAD(0x01C8, 0x0018, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO02__LPI2C4_SDA = IOMUX_PAD(0x01C8, 0x0018, 0x01, 0x03FC, 0x00, 0x00),
+ MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 0x02, 0x04C0, 0x00, 0x00),
+ MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO02__LPSPI6_SOUT = IOMUX_PAD(0x01C8, 0x0018, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO02__LPUART5_CTS_B = IOMUX_PAD(0x01C8, 0x0018, 0x05, 0x0484, 0x01, 0x00),
+ MX91_PAD_GPIO_IO02__LPI2C6_SDA = IOMUX_PAD(0x01C8, 0x0018, 0x06, 0x040C, 0x00, 0x00),
+ MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 = IOMUX_PAD(0x01C8, 0x0018, 0x07, 0x0374, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO03__GPIO2_IO3 = IOMUX_PAD(0x01CC, 0x001C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO03__LPI2C4_SCL = IOMUX_PAD(0x01CC, 0x001C, 0x01, 0x03F8, 0x00, 0x00),
+ MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 0x02, 0x04B8, 0x00, 0x00),
+ MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO03__LPSPI6_SCK = IOMUX_PAD(0x01CC, 0x001C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO03__LPUART5_RTS_B = IOMUX_PAD(0x01CC, 0x001C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO03__LPI2C6_SCL = IOMUX_PAD(0x01CC, 0x001C, 0x06, 0x0408, 0x00, 0x00),
+ MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 = IOMUX_PAD(0x01CC, 0x001C, 0x07, 0x0378, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO04__GPIO2_IO4 = IOMUX_PAD(0x01D0, 0x0020, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO04__TPM3_CH0 = IOMUX_PAD(0x01D0, 0x0020, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO04__PDM_CLK = IOMUX_PAD(0x01D0, 0x0020, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 = IOMUX_PAD(0x01D0, 0x0020, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO04__LPSPI7_PCS0 = IOMUX_PAD(0x01D0, 0x0020, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO04__LPUART6_TX = IOMUX_PAD(0x01D0, 0x0020, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO04__LPI2C6_SDA = IOMUX_PAD(0x01D0, 0x0020, 0x06, 0x040C, 0x01, 0x00),
+ MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 = IOMUX_PAD(0x01D0, 0x0020, 0x07, 0x037C, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO05__GPIO2_IO5 = IOMUX_PAD(0x01D4, 0x0024, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO05__TPM4_CH0 = IOMUX_PAD(0x01D4, 0x0024, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 = IOMUX_PAD(0x01D4, 0x0024, 0x02, 0x04C4, 0x00, 0x00),
+ MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 = IOMUX_PAD(0x01D4, 0x0024, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO05__LPSPI7_SIN = IOMUX_PAD(0x01D4, 0x0024, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO05__LPUART6_RX = IOMUX_PAD(0x01D4, 0x0024, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO05__LPI2C6_SCL = IOMUX_PAD(0x01D4, 0x0024, 0x06, 0x0408, 0x01, 0x00),
+ MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 = IOMUX_PAD(0x01D4, 0x0024, 0x07, 0x0380, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO06__GPIO2_IO6 = IOMUX_PAD(0x01D8, 0x0028, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO06__TPM5_CH0 = IOMUX_PAD(0x01D8, 0x0028, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 = IOMUX_PAD(0x01D8, 0x0028, 0x02, 0x04C8, 0x00, 0x00),
+ MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 = IOMUX_PAD(0x01D8, 0x0028, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO06__LPSPI7_SOUT = IOMUX_PAD(0x01D8, 0x0028, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO06__LPUART6_CTS_B = IOMUX_PAD(0x01D8, 0x0028, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO06__LPI2C7_SDA = IOMUX_PAD(0x01D8, 0x0028, 0x06, 0x0414, 0x00, 0x00),
+ MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 = IOMUX_PAD(0x01D8, 0x0028, 0x07, 0x0384, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO07__GPIO2_IO7 = IOMUX_PAD(0x01DC, 0x002C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO07__LPSPI3_PCS1 = IOMUX_PAD(0x01DC, 0x002C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 = IOMUX_PAD(0x01DC, 0x002C, 0x02, 0x0494, 0x00, 0x00),
+ MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 = IOMUX_PAD(0x01DC, 0x002C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO07__LPSPI7_SCK = IOMUX_PAD(0x01DC, 0x002C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO07__LPUART6_RTS_B = IOMUX_PAD(0x01DC, 0x002C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO07__LPI2C7_SCL = IOMUX_PAD(0x01DC, 0x002C, 0x06, 0x0410, 0x00, 0x00),
+ MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 = IOMUX_PAD(0x01DC, 0x002C, 0x07, 0x0388, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO08__GPIO2_IO8 = IOMUX_PAD(0x01E0, 0x0030, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO08__LPSPI3_PCS0 = IOMUX_PAD(0x01E0, 0x0030, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 = IOMUX_PAD(0x01E0, 0x0030, 0x02, 0x0498, 0x00, 0x00),
+ MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 = IOMUX_PAD(0x01E0, 0x0030, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO08__TPM6_CH0 = IOMUX_PAD(0x01E0, 0x0030, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO08__LPUART7_TX = IOMUX_PAD(0x01E0, 0x0030, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO08__LPI2C7_SDA = IOMUX_PAD(0x01E0, 0x0030, 0x06, 0x0414, 0x01, 0x00),
+ MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 = IOMUX_PAD(0x01E0, 0x0030, 0x07, 0x038C, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO09__GPIO2_IO9 = IOMUX_PAD(0x01E4, 0x0034, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO09__LPSPI3_SIN = IOMUX_PAD(0x01E4, 0x0034, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 = IOMUX_PAD(0x01E4, 0x0034, 0x02, 0x049C, 0x00, 0x00),
+ MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 = IOMUX_PAD(0x01E4, 0x0034, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO09__TPM3_EXTCLK = IOMUX_PAD(0x01E4, 0x0034, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO09__LPUART7_RX = IOMUX_PAD(0x01E4, 0x0034, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO09__LPI2C7_SCL = IOMUX_PAD(0x01E4, 0x0034, 0x06, 0x0410, 0x01, 0x00),
+ MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 = IOMUX_PAD(0x01E4, 0x0034, 0x07, 0x0390, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO10__GPIO2_IO10 = IOMUX_PAD(0x01E8, 0x0038, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO10__LPSPI3_SOUT = IOMUX_PAD(0x01E8, 0x0038, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 = IOMUX_PAD(0x01E8, 0x0038, 0x02, 0x04A0, 0x00, 0x00),
+ MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 = IOMUX_PAD(0x01E8, 0x0038, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO10__TPM4_EXTCLK = IOMUX_PAD(0x01E8, 0x0038, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO10__LPUART7_CTS_B = IOMUX_PAD(0x01E8, 0x0038, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO10__LPI2C8_SDA = IOMUX_PAD(0x01E8, 0x0038, 0x06, 0x041C, 0x00, 0x00),
+ MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x01E8, 0x0038, 0x07, 0x0394, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO11__GPIO2_IO11 = IOMUX_PAD(0x01EC, 0x003C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO11__LPSPI3_SCK = IOMUX_PAD(0x01EC, 0x003C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 = IOMUX_PAD(0x01EC, 0x003C, 0x02, 0x04A4, 0x00, 0x00),
+ MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 = IOMUX_PAD(0x01EC, 0x003C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO11__TPM5_EXTCLK = IOMUX_PAD(0x01EC, 0x003C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO11__LPUART7_RTS_B = IOMUX_PAD(0x01EC, 0x003C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO11__LPI2C8_SCL = IOMUX_PAD(0x01EC, 0x003C, 0x06, 0x0418, 0x00, 0x00),
+ MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x01EC, 0x003C, 0x07, 0x0398, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO12__GPIO2_IO12 = IOMUX_PAD(0x01F0, 0x0040, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO12__TPM3_CH2 = IOMUX_PAD(0x01F0, 0x0040, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 = IOMUX_PAD(0x01F0, 0x0040, 0x02, 0x04CC, 0x00, 0x00),
+ MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 = IOMUX_PAD(0x01F0, 0x0040, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO12__LPSPI8_PCS0 = IOMUX_PAD(0x01F0, 0x0040, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO12__LPUART8_TX = IOMUX_PAD(0x01F0, 0x0040, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO12__LPI2C8_SDA = IOMUX_PAD(0x01F0, 0x0040, 0x06, 0x041C, 0x01, 0x00),
+ MX91_PAD_GPIO_IO12__SAI3_RX_SYNC = IOMUX_PAD(0x01F0, 0x0040, 0x07, 0x04DC, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO13__GPIO2_IO13 = IOMUX_PAD(0x01F4, 0x0044, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO13__TPM4_CH2 = IOMUX_PAD(0x01F4, 0x0044, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 = IOMUX_PAD(0x01F4, 0x0044, 0x02, 0x04D0, 0x00, 0x00),
+ MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 = IOMUX_PAD(0x01F4, 0x0044, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO13__LPSPI8_SIN = IOMUX_PAD(0x01F4, 0x0044, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO13__LPUART8_RX = IOMUX_PAD(0x01F4, 0x0044, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO13__LPI2C8_SCL = IOMUX_PAD(0x01F4, 0x0044, 0x06, 0x0418, 0x01, 0x00),
+ MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x01F4, 0x0044, 0x07, 0x039C, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO14__GPIO2_IO14 = IOMUX_PAD(0x01F8, 0x0048, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO14__LPUART3_TX = IOMUX_PAD(0x01F8, 0x0048, 0x01, 0x0474, 0x00, 0x00),
+ MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 = IOMUX_PAD(0x01F8, 0x0048, 0x02, 0x04A8, 0x00, 0x00),
+ MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 = IOMUX_PAD(0x01F8, 0x0048, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO14__LPSPI8_SOUT = IOMUX_PAD(0x01F8, 0x0048, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO14__LPUART8_CTS_B = IOMUX_PAD(0x01F8, 0x0048, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO14__LPUART4_TX = IOMUX_PAD(0x01F8, 0x0048, 0x06, 0x0480, 0x00, 0x00),
+ MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x01F8, 0x0048, 0x07, 0x03A0, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO15__GPIO2_IO15 = IOMUX_PAD(0x01FC, 0x004C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO15__LPUART3_RX = IOMUX_PAD(0x01FC, 0x004C, 0x01, 0x0470, 0x00, 0x00),
+ MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 = IOMUX_PAD(0x01FC, 0x004C, 0x02, 0x04AC, 0x00, 0x00),
+ MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 = IOMUX_PAD(0x01FC, 0x004C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO15__LPSPI8_SCK = IOMUX_PAD(0x01FC, 0x004C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO15__LPUART8_RTS_B = IOMUX_PAD(0x01FC, 0x004C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO15__LPUART4_RX = IOMUX_PAD(0x01FC, 0x004C, 0x06, 0x047C, 0x00, 0x00),
+ MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x01FC, 0x004C, 0x07, 0x03A4, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO16__GPIO2_IO16 = IOMUX_PAD(0x0200, 0x0050, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO16__SAI3_TX_BCLK = IOMUX_PAD(0x0200, 0x0050, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 = IOMUX_PAD(0x0200, 0x0050, 0x02, 0x04CC, 0x01, 0x00),
+ MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 = IOMUX_PAD(0x0200, 0x0050, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO16__LPUART3_CTS_B = IOMUX_PAD(0x0200, 0x0050, 0x04, 0x046C, 0x00, 0x00),
+ MX91_PAD_GPIO_IO16__LPSPI4_PCS2 = IOMUX_PAD(0x0200, 0x0050, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO16__LPUART4_CTS_B = IOMUX_PAD(0x0200, 0x0050, 0x06, 0x0478, 0x00, 0x00),
+ MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x0200, 0x0050, 0x07, 0x03A8, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO17__GPIO2_IO17 = IOMUX_PAD(0x0204, 0x0054, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO17__SAI3_MCLK = IOMUX_PAD(0x0204, 0x0054, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 = IOMUX_PAD(0x0204, 0x0054, 0x02, 0x04B0, 0x00, 0x00),
+ MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 = IOMUX_PAD(0x0204, 0x0054, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO17__LPUART3_RTS_B = IOMUX_PAD(0x0204, 0x0054, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO17__LPSPI4_PCS1 = IOMUX_PAD(0x0204, 0x0054, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO17__LPUART4_RTS_B = IOMUX_PAD(0x0204, 0x0054, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x0204, 0x0054, 0x07, 0x03AC, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO18__GPIO2_IO18 = IOMUX_PAD(0x0208, 0x0058, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO18__SAI3_RX_BCLK = IOMUX_PAD(0x0208, 0x0058, 0x01, 0x04D8, 0x00, 0x00),
+ MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 = IOMUX_PAD(0x0208, 0x0058, 0x02, 0x04B4, 0x00, 0x00),
+ MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 = IOMUX_PAD(0x0208, 0x0058, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO18__LPSPI5_PCS0 = IOMUX_PAD(0x0208, 0x0058, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO18__LPSPI4_PCS0 = IOMUX_PAD(0x0208, 0x0058, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO18__TPM5_CH2 = IOMUX_PAD(0x0208, 0x0058, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x0208, 0x0058, 0x07, 0x03B0, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO19__GPIO2_IO19 = IOMUX_PAD(0x020C, 0x005C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO19__SAI3_RX_SYNC = IOMUX_PAD(0x020C, 0x005C, 0x01, 0x04DC, 0x01, 0x00),
+ MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 = IOMUX_PAD(0x020C, 0x005C, 0x02, 0x04D0, 0x01, 0x00),
+ MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 = IOMUX_PAD(0x020C, 0x005C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO19__LPSPI5_SIN = IOMUX_PAD(0x020C, 0x005C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO19__LPSPI4_SIN = IOMUX_PAD(0x020C, 0x005C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO19__TPM6_CH2 = IOMUX_PAD(0x020C, 0x005C, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 = IOMUX_PAD(0x020C, 0x005C, 0x07, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO20__GPIO2_IO20 = IOMUX_PAD(0x0210, 0x0060, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 = IOMUX_PAD(0x0210, 0x0060, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 = IOMUX_PAD(0x0210, 0x0060, 0x02, 0x04C4, 0x01, 0x00),
+ MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 = IOMUX_PAD(0x0210, 0x0060, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO20__LPSPI5_SOUT = IOMUX_PAD(0x0210, 0x0060, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO20__LPSPI4_SOUT = IOMUX_PAD(0x0210, 0x0060, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO20__TPM3_CH1 = IOMUX_PAD(0x0210, 0x0060, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x0210, 0x0060, 0x07, 0x03B4, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO21__GPIO2_IO21 = IOMUX_PAD(0x0214, 0x0064, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 = IOMUX_PAD(0x0214, 0x0064, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO21__PDM_CLK = IOMUX_PAD(0x0214, 0x0064, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 = IOMUX_PAD(0x0214, 0x0064, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO21__LPSPI5_SCK = IOMUX_PAD(0x0214, 0x0064, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO21__LPSPI4_SCK = IOMUX_PAD(0x0214, 0x0064, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO21__TPM4_CH1 = IOMUX_PAD(0x0214, 0x0064, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO21__SAI3_RX_BCLK = IOMUX_PAD(0x0214, 0x0064, 0x07, 0x04D8, 0x01, 0x00),
+
+ MX91_PAD_GPIO_IO22__GPIO2_IO22 = IOMUX_PAD(0x0218, 0x0068, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO22__USDHC3_CLK = IOMUX_PAD(0x0218, 0x0068, 0x01, 0x04E8, 0x00, 0x00),
+ MX91_PAD_GPIO_IO22__SPDIF_IN = IOMUX_PAD(0x0218, 0x0068, 0x02, 0x04E4, 0x00, 0x00),
+ MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 = IOMUX_PAD(0x0218, 0x0068, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO22__TPM5_CH1 = IOMUX_PAD(0x0218, 0x0068, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO22__TPM6_EXTCLK = IOMUX_PAD(0x0218, 0x0068, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO22__LPI2C5_SDA = IOMUX_PAD(0x0218, 0x0068, 0x06, 0x0404, 0x01, 0x00),
+ MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x0218, 0x0068, 0x07, 0x03B8, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO23__GPIO2_IO23 = IOMUX_PAD(0x021C, 0x006C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO23__USDHC3_CMD = IOMUX_PAD(0x021C, 0x006C, 0x01, 0x04EC, 0x00, 0x00),
+ MX91_PAD_GPIO_IO23__SPDIF_OUT = IOMUX_PAD(0x021C, 0x006C, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 = IOMUX_PAD(0x021C, 0x006C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO23__TPM6_CH1 = IOMUX_PAD(0x021C, 0x006C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO23__LPI2C5_SCL = IOMUX_PAD(0x021C, 0x006C, 0x06, 0x0400, 0x01, 0x00),
+ MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x021C, 0x006C, 0x07, 0x03BC, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO24__GPIO2_IO24 = IOMUX_PAD(0x0220, 0x0070, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO24__USDHC3_DATA0 = IOMUX_PAD(0x0220, 0x0070, 0x01, 0x04F0, 0x00, 0x00),
+ MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 = IOMUX_PAD(0x0220, 0x0070, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO24__TPM3_CH3 = IOMUX_PAD(0x0220, 0x0070, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO24__JTAG_MUX_TDO = IOMUX_PAD(0x0220, 0x0070, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO24__LPSPI6_PCS1 = IOMUX_PAD(0x0220, 0x0070, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x0220, 0x0070, 0x07, 0x03C0, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO25__GPIO2_IO25 = IOMUX_PAD(0x0224, 0x0074, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO25__USDHC3_DATA1 = IOMUX_PAD(0x0224, 0x0074, 0x01, 0x04F4, 0x00, 0x00),
+ MX91_PAD_GPIO_IO25__CAN2_TX = IOMUX_PAD(0x0224, 0x0074, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 = IOMUX_PAD(0x0224, 0x0074, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO25__TPM4_CH3 = IOMUX_PAD(0x0224, 0x0074, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO25__JTAG_MUX_TCK = IOMUX_PAD(0x0224, 0x0074, 0x05, 0x03D4, 0x01, 0x00),
+ MX91_PAD_GPIO_IO25__LPSPI7_PCS1 = IOMUX_PAD(0x0224, 0x0074, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x0224, 0x0074, 0x07, 0x03C4, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO26__GPIO2_IO26 = IOMUX_PAD(0x0228, 0x0078, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO26__USDHC3_DATA2 = IOMUX_PAD(0x0228, 0x0078, 0x01, 0x04F8, 0x00, 0x00),
+ MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 = IOMUX_PAD(0x0228, 0x0078, 0x02, 0x04C8, 0x01, 0x00),
+ MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 = IOMUX_PAD(0x0228, 0x0078, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO26__TPM5_CH3 = IOMUX_PAD(0x0228, 0x0078, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO26__JTAG_MUX_TDI = IOMUX_PAD(0x0228, 0x0078, 0x05, 0x03D8, 0x01, 0x00),
+ MX91_PAD_GPIO_IO26__LPSPI8_PCS1 = IOMUX_PAD(0x0228, 0x0078, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO26__SAI3_TX_SYNC = IOMUX_PAD(0x0228, 0x0078, 0x07, 0x04E0, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO27__GPIO2_IO27 = IOMUX_PAD(0x022C, 0x007C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO27__USDHC3_DATA3 = IOMUX_PAD(0x022C, 0x007C, 0x01, 0x04FC, 0x00, 0x00),
+ MX91_PAD_GPIO_IO27__CAN2_RX = IOMUX_PAD(0x022C, 0x007C, 0x02, 0x0364, 0x01, 0x00),
+ MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 = IOMUX_PAD(0x022C, 0x007C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO27__TPM6_CH3 = IOMUX_PAD(0x022C, 0x007C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO27__JTAG_MUX_TMS = IOMUX_PAD(0x022C, 0x007C, 0x05, 0x03DC, 0x01, 0x00),
+ MX91_PAD_GPIO_IO27__LPSPI5_PCS1 = IOMUX_PAD(0x022C, 0x007C, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x022C, 0x007C, 0x07, 0x03C8, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO28__GPIO2_IO28 = IOMUX_PAD(0x0230, 0x0080, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO28__LPI2C3_SDA = IOMUX_PAD(0x0230, 0x0080, 0x01, 0x03F4, 0x01, 0x00),
+ MX91_PAD_GPIO_IO28__CAN1_TX = IOMUX_PAD(0x0230, 0x0080, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 = IOMUX_PAD(0x0230, 0x0080, 0x07, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_GPIO_IO29__GPIO2_IO29 = IOMUX_PAD(0x0234, 0x0084, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_GPIO_IO29__LPI2C3_SCL = IOMUX_PAD(0x0234, 0x0084, 0x01, 0x03F0, 0x01, 0x00),
+ MX91_PAD_GPIO_IO29__CAN1_RX = IOMUX_PAD(0x0234, 0x0084, 0x02, 0x0360, 0x00, 0x00),
+ MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 = IOMUX_PAD(0x0234, 0x0084, 0x07, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0238, 0x0088, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 = IOMUX_PAD(0x0238, 0x0088, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_CCM_CLKO1__GPIO3_IO26 = IOMUX_PAD(0x0238, 0x0088, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_CCM_CLKO2__GPIO3_IO27 = IOMUX_PAD(0x023C, 0x008C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x023C, 0x008C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x023C, 0x008C, 0x04, 0x03C8, 0x01, 0x00),
+
+ MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 = IOMUX_PAD(0x0240, 0x0090, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 = IOMUX_PAD(0x0240, 0x0090, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_CCM_CLKO3__GPIO4_IO28 = IOMUX_PAD(0x0240, 0x0090, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 = IOMUX_PAD(0x0244, 0x0094, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 = IOMUX_PAD(0x0244, 0x0094, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_CCM_CLKO4__GPIO4_IO29 = IOMUX_PAD(0x0244, 0x0094, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_ENET1_MDC__ENET1_MDC = IOMUX_PAD(0x0248, 0x0098, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDC__LPUART3_DCB_B = IOMUX_PAD(0x0248, 0x0098, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDC__I3C2_SCL = IOMUX_PAD(0x0248, 0x0098, 0x02, 0x03CC, 0x00, 0x00),
+ MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 = IOMUX_PAD(0x0248, 0x0098, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 = IOMUX_PAD(0x0248, 0x0098, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDC__GPIO4_IO0 = IOMUX_PAD(0x0248, 0x0098, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDC__LPI2C1_SCL = IOMUX_PAD(0x0248, 0x0098, 0x06, 0x03E0, 0x00, 0x00),
+
+ MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x024C, 0x009C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDIO__LPUART3_RIN_B = IOMUX_PAD(0x024C, 0x009C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDIO__I3C2_SDA = IOMUX_PAD(0x024C, 0x009C, 0x02, 0x03D0, 0x00, 0x00),
+ MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 = IOMUX_PAD(0x024C, 0x009C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 = IOMUX_PAD(0x024C, 0x009C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDIO__GPIO4_IO1 = IOMUX_PAD(0x024C, 0x009C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_MDIO__LPI2C1_SDA = IOMUX_PAD(0x024C, 0x009C, 0x06, 0x03E4, 0x00, 0x00),
+
+ MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x0250, 0x00A0, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD3__CAN2_TX = IOMUX_PAD(0x0250, 0x00A0, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 = IOMUX_PAD(0x0250, 0x00A0, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 = IOMUX_PAD(0x0250, 0x00A0, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD3__GPIO4_IO3 = IOMUX_PAD(0x0250, 0x00A0, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD3__LPI2C2_SCL = IOMUX_PAD(0x0250, 0x00A0, 0x06, 0x03E8, 0x00, 0x00),
+
+ MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x0254, 0x00A4, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK = IOMUX_PAD(0x0254, 0x00A4, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD2__CAN2_RX = IOMUX_PAD(0x0254, 0x00A4, 0x02, 0x0364, 0x02, 0x00),
+ MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 = IOMUX_PAD(0x0254, 0x00A4, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 = IOMUX_PAD(0x0254, 0x00A4, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD2__GPIO4_IO3 = IOMUX_PAD(0x0254, 0x00A4, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD2__LPI2C2_SDA = IOMUX_PAD(0x0254, 0x00A4, 0x06, 0x03EC, 0x00, 0x00),
+
+ MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x0258, 0x00A8, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD1__LPUART3_RTS_B = IOMUX_PAD(0x0258, 0x00A8, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD1__I3C2_PUR = IOMUX_PAD(0x0258, 0x00A8, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 = IOMUX_PAD(0x0258, 0x00A8, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 = IOMUX_PAD(0x0258, 0x00A8, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD1__GPIO4_IO4 = IOMUX_PAD(0x0258, 0x00A8, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD1__I3C2_PUR_B = IOMUX_PAD(0x0258, 0x00A8, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x025C, 0x00AC, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD0__LPUART3_TX = IOMUX_PAD(0x025C, 0x00AC, 0x01, 0x0474, 0x01, 0x00),
+ MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 = IOMUX_PAD(0x025C, 0x00AC, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TD0__GPIO4_IO5 = IOMUX_PAD(0x025C, 0x00AC, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x0260, 0x00B0, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B = IOMUX_PAD(0x0260, 0x00B0, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 = IOMUX_PAD(0x0260, 0x00B0, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 = IOMUX_PAD(0x0260, 0x00B0, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK = IOMUX_PAD(0x0260, 0x00B0, 0x02, 0x043C, 0x00, 0x00),
+
+ MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x0264, 0x00B4, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x0264, 0x00B4, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 = IOMUX_PAD(0x0264, 0x00B4, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TXC__GPIO4_IO7 = IOMUX_PAD(0x0264, 0x00B4, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_TXC__LPSPI2_SIN = IOMUX_PAD(0x0264, 0x00B4, 0x02, 0x0440, 0x00, 0x00),
+
+ MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x0268, 0x00B8, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B = IOMUX_PAD(0x0268, 0x00B8, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 = IOMUX_PAD(0x0268, 0x00B8, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 = IOMUX_PAD(0x0268, 0x00B8, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 = IOMUX_PAD(0x0268, 0x00B8, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 = IOMUX_PAD(0x0268, 0x00B8, 0x02, 0x0434, 0x00, 0x00),
+
+ MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC = IOMUX_PAD(0x026C, 0x00BC, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x026C, 0x00BC, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 = IOMUX_PAD(0x026C, 0x00BC, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RXC__GPIO4_IO9 = IOMUX_PAD(0x026C, 0x00BC, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RXC__LPSPI2_SOUT = IOMUX_PAD(0x026C, 0x00BC, 0x02, 0x0444, 0x00, 0x00),
+
+ MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x0270, 0x00C0, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RD0__LPUART3_RX = IOMUX_PAD(0x0270, 0x00C0, 0x01, 0x0470, 0x01, 0x00),
+ MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 = IOMUX_PAD(0x0270, 0x00C0, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RD0__GPIO4_IO10 = IOMUX_PAD(0x0270, 0x00C0, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x0274, 0x00C4, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RD1__LPUART3_CTS_B = IOMUX_PAD(0x0274, 0x00C4, 0x01, 0x046C, 0x01, 0x00),
+ MX91_PAD_ENET1_RD1__LPTMR2_ALT1 = IOMUX_PAD(0x0274, 0x00C4, 0x03, 0x0448, 0x00, 0x00),
+ MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 = IOMUX_PAD(0x0274, 0x00C4, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RD1__GPIO4_IO11 = IOMUX_PAD(0x0274, 0x00C4, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x0278, 0x00C8, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RD2__LPTMR2_ALT2 = IOMUX_PAD(0x0278, 0x00C8, 0x03, 0x044C, 0x00, 0x00),
+ MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 = IOMUX_PAD(0x0278, 0x00C8, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RD2__GPIO4_IO12 = IOMUX_PAD(0x0278, 0x00C8, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x027C, 0x00CC, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER = IOMUX_PAD(0x027C, 0x00CC, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RD3__LPTMR2_ALT3 = IOMUX_PAD(0x027C, 0x00CC, 0x03, 0x0450, 0x00, 0x00),
+ MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 = IOMUX_PAD(0x027C, 0x00CC, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET1_RD3__GPIO4_IO13 = IOMUX_PAD(0x027C, 0x00CC, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_ENET2_MDC__ENET2_MDC = IOMUX_PAD(0x0280, 0x00D0, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDC__LPUART4_DCB_B = IOMUX_PAD(0x0280, 0x00D0, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDC__SAI2_RX_SYNC = IOMUX_PAD(0x0280, 0x00D0, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 = IOMUX_PAD(0x0280, 0x00D0, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDC__GPIO4_IO14 = IOMUX_PAD(0x0280, 0x00D0, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x0280, 0x00D0, 0x06, 0x04BC, 0x01, 0x00),
+
+ MX91_PAD_ENET2_MDIO__ENET2_MDIO = IOMUX_PAD(0x0284, 0x00D4, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDIO__LPUART4_RIN_B = IOMUX_PAD(0x0284, 0x00D4, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK = IOMUX_PAD(0x0284, 0x00D4, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 = IOMUX_PAD(0x0284, 0x00D4, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDIO__GPIO4_IO15 = IOMUX_PAD(0x0284, 0x00D4, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 = IOMUX_PAD(0x0284, 0x00D4, 0x06, 0x0490, 0x01, 0x00),
+
+ MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 = IOMUX_PAD(0x0288, 0x00D8, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 = IOMUX_PAD(0x0288, 0x00D8, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD3__GPIO4_IO16 = IOMUX_PAD(0x0288, 0x00D8, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x0288, 0x00D8, 0x06, 0x04C0, 0x01, 0x00),
+ MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 = IOMUX_PAD(0x0288, 0x00D8, 0x00, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 = IOMUX_PAD(0x028C, 0x00DC, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 = IOMUX_PAD(0x028C, 0x00DC, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 = IOMUX_PAD(0x028C, 0x00DC, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD2__GPIO4_IO17 = IOMUX_PAD(0x028C, 0x00DC, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x028C, 0x00DC, 0x06, 0x04B8, 0x01, 0x00),
+
+ MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 = IOMUX_PAD(0x0290, 0x00E0, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD1__LPUART4_RTS_B = IOMUX_PAD(0x0290, 0x00E0, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 = IOMUX_PAD(0x0290, 0x00E0, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD1__GPIO4_IO18 = IOMUX_PAD(0x0290, 0x00E0, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 = IOMUX_PAD(0x0290, 0x00E0, 0x06, 0x0494, 0x01, 0x00),
+
+ MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 = IOMUX_PAD(0x0294, 0x00E4, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD0__LPUART4_TX = IOMUX_PAD(0x0294, 0x00E4, 0x01, 0x0480, 0x01, 0x00),
+ MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 = IOMUX_PAD(0x0294, 0x00E4, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD0__GPIO4_IO19 = IOMUX_PAD(0x0294, 0x00E4, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 = IOMUX_PAD(0x0294, 0x00E4, 0x06, 0x0498, 0x01, 0x00),
+
+ MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL = IOMUX_PAD(0x0298, 0x00E8, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B = IOMUX_PAD(0x0298, 0x00E8, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC = IOMUX_PAD(0x0298, 0x00E8, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 = IOMUX_PAD(0x0298, 0x00E8, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 = IOMUX_PAD(0x0298, 0x00E8, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 = IOMUX_PAD(0x0298, 0x00E8, 0x06, 0x049C, 0x01, 0x00),
+
+ MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC = IOMUX_PAD(0x029C, 0x00EC, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TXC__ENET2_TX_ER = IOMUX_PAD(0x029C, 0x00EC, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x029C, 0x00EC, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 = IOMUX_PAD(0x029C, 0x00EC, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TXC__GPIO4_IO21 = IOMUX_PAD(0x029C, 0x00EC, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 = IOMUX_PAD(0x029C, 0x00EC, 0x06, 0x04A0, 0x01, 0x00),
+
+ MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL = IOMUX_PAD(0x02A0, 0x00F0, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B = IOMUX_PAD(0x02A0, 0x00F0, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 = IOMUX_PAD(0x02A0, 0x00F0, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 = IOMUX_PAD(0x02A0, 0x00F0, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 = IOMUX_PAD(0x02A0, 0x00F0, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 = IOMUX_PAD(0x02A0, 0x00F0, 0x06, 0x04A4, 0x01, 0x00),
+
+ MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC = IOMUX_PAD(0x02A4, 0x00F4, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RXC__ENET2_RX_ER = IOMUX_PAD(0x02A4, 0x00F4, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 = IOMUX_PAD(0x02A4, 0x00F4, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RXC__GPIO4_IO23 = IOMUX_PAD(0x02A4, 0x00F4, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 = IOMUX_PAD(0x02A4, 0x00F4, 0x06, 0x04A8, 0x01, 0x00),
+
+ MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 = IOMUX_PAD(0x02A8, 0x00F8, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD0__LPUART4_RX = IOMUX_PAD(0x02A8, 0x00F8, 0x01, 0x047C, 0x01, 0x00),
+ MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 = IOMUX_PAD(0x02A8, 0x00F8, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD0__GPIO4_IO24 = IOMUX_PAD(0x02A8, 0x00F8, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 = IOMUX_PAD(0x02A8, 0x00F8, 0x06, 0x04AC, 0x01, 0x00),
+
+ MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 = IOMUX_PAD(0x02AC, 0x00FC, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD1__SPDIF_IN = IOMUX_PAD(0x02AC, 0x00FC, 0x01, 0x04E4, 0x01, 0x00),
+ MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 = IOMUX_PAD(0x02AC, 0x00FC, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD1__GPIO4_IO25 = IOMUX_PAD(0x02AC, 0x00FC, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 = IOMUX_PAD(0x02AC, 0x00FC, 0x06, 0x04B0, 0x01, 0x00),
+
+ MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 = IOMUX_PAD(0x02B0, 0x0100, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD2__LPUART4_CTS_B = IOMUX_PAD(0x02B0, 0x0100, 0x01, 0x0478, 0x01, 0x00),
+ MX91_PAD_ENET2_RD2__SAI2_MCLK = IOMUX_PAD(0x02B0, 0x0100, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD2__MQS2_RIGHT = IOMUX_PAD(0x02B0, 0x0100, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 = IOMUX_PAD(0x02B0, 0x0100, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD2__GPIO4_IO26 = IOMUX_PAD(0x02B0, 0x0100, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 = IOMUX_PAD(0x02B0, 0x0100, 0x06, 0x04B4, 0x01, 0x00),
+
+ MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 = IOMUX_PAD(0x02B4, 0x0104, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD3__SPDIF_OUT = IOMUX_PAD(0x02B4, 0x0104, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD3__SPDIF_IN = IOMUX_PAD(0x02B4, 0x0104, 0x02, 0x04E4, 0x02, 0x00),
+ MX91_PAD_ENET2_RD3__MQS2_LEFT = IOMUX_PAD(0x02B4, 0x0104, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 = IOMUX_PAD(0x02B4, 0x0104, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_ENET2_RD3__GPIO4_IO27 = IOMUX_PAD(0x02B4, 0x0104, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 = IOMUX_PAD(0x02B8, 0x0108, 0x04, 0x038C, 0x01, 0x00),
+ MX91_PAD_SD1_CLK__GPIO3_IO8 = IOMUX_PAD(0x02B8, 0x0108, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02B8, 0x0108, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_CLK__LPSPI2_SCK = IOMUX_PAD(0x02B8, 0x0108, 0x03, 0x043C, 0x01, 0x00),
+
+ MX91_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02BC, 0x010C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 = IOMUX_PAD(0x02BC, 0x010C, 0x04, 0x0390, 0x01, 0x00),
+ MX91_PAD_SD1_CMD__GPIO3_IO9 = IOMUX_PAD(0x02BC, 0x010C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_CMD__LPSPI2_SIN = IOMUX_PAD(0x02BC, 0x010C, 0x03, 0x0440, 0x01, 0x00),
+
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02C0, 0x0110, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x02C0, 0x0110, 0x04, 0x0394, 0x01, 0x00),
+ MX91_PAD_SD1_DATA0__GPIO3_IO10 = IOMUX_PAD(0x02C0, 0x0110, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA0__LPSPI2_PCS0 = IOMUX_PAD(0x02C0, 0x0110, 0x03, 0x0434, 0x01, 0x00),
+
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02C4, 0x0114, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x02C4, 0x0114, 0x04, 0x0398, 0x01, 0x00),
+ MX91_PAD_SD1_DATA1__GPIO3_IO11 = IOMUX_PAD(0x02C4, 0x0114, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x02C4, 0x0114, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA1__LPSPI2_SOUT = IOMUX_PAD(0x02C4, 0x0114, 0x03, 0x0444, 0x01, 0x00),
+
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02C8, 0x0118, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 = IOMUX_PAD(0x02C8, 0x0118, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA2__GPIO3_IO12 = IOMUX_PAD(0x02C8, 0x0118, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02C8, 0x0118, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA2__LPSPI2_PCS1 = IOMUX_PAD(0x02C8, 0x0118, 0x03, 0x0438, 0x00, 0x00),
+
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x02CC, 0x011C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B = IOMUX_PAD(0x02CC, 0x011C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x02CC, 0x011C, 0x04, 0x039C, 0x01, 0x00),
+ MX91_PAD_SD1_DATA3__GPIO3_IO13 = IOMUX_PAD(0x02CC, 0x011C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA3__LPSPI1_PCS1 = IOMUX_PAD(0x02CC, 0x011C, 0x03, 0x0424, 0x00, 0x00),
+
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x02D0, 0x0120, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 = IOMUX_PAD(0x02D0, 0x0120, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x02D0, 0x0120, 0x04, 0x03A0, 0x01, 0x00),
+ MX91_PAD_SD1_DATA4__GPIO3_IO14 = IOMUX_PAD(0x02D0, 0x0120, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA4__LPSPI1_PCS0 = IOMUX_PAD(0x02D0, 0x0120, 0x03, 0x0420, 0x00, 0x00),
+
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x02D4, 0x0124, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 = IOMUX_PAD(0x02D4, 0x0124, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA5__USDHC1_RESET_B = IOMUX_PAD(0x02D4, 0x0124, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x02D4, 0x0124, 0x04, 0x03A4, 0x01, 0x00),
+ MX91_PAD_SD1_DATA5__GPIO3_IO15 = IOMUX_PAD(0x02D4, 0x0124, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA5__LPSPI1_SIN = IOMUX_PAD(0x02D4, 0x0124, 0x03, 0x042C, 0x00, 0x00),
+
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x02D8, 0x0128, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 = IOMUX_PAD(0x02D8, 0x0128, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA6__USDHC1_CD_B = IOMUX_PAD(0x02D8, 0x0128, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x02D8, 0x0128, 0x04, 0x03A8, 0x01, 0x00),
+ MX91_PAD_SD1_DATA6__GPIO3_IO16 = IOMUX_PAD(0x02D8, 0x0128, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA6__LPSPI1_SCK = IOMUX_PAD(0x02D8, 0x0128, 0x03, 0x0428, 0x00, 0x00),
+
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x02DC, 0x012C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 = IOMUX_PAD(0x02DC, 0x012C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA7__USDHC1_WP = IOMUX_PAD(0x02DC, 0x012C, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x02DC, 0x012C, 0x04, 0x03AC, 0x01, 0x00),
+ MX91_PAD_SD1_DATA7__GPIO3_IO17 = IOMUX_PAD(0x02DC, 0x012C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_DATA7__LPSPI1_SOUT = IOMUX_PAD(0x02DC, 0x012C, 0x03, 0x0430, 0x00, 0x00),
+
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x02E0, 0x0130, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS = IOMUX_PAD(0x02E0, 0x0130, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x02E0, 0x0130, 0x04, 0x03B0, 0x01, 0x00),
+ MX91_PAD_SD1_STROBE__GPIO3_IO18 = IOMUX_PAD(0x02E0, 0x0130, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT = IOMUX_PAD(0x02E4, 0x0134, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_VSELECT__USDHC2_WP = IOMUX_PAD(0x02E4, 0x0134, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 = IOMUX_PAD(0x02E4, 0x0134, 0x02, 0x0450, 0x01, 0x00),
+ MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 = IOMUX_PAD(0x02E4, 0x0134, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_VSELECT__GPIO3_IO19 = IOMUX_PAD(0x02E4, 0x0134, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x02E4, 0x0134, 0x06, 0x0368, 0x00, 0x00),
+
+ MX91_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x02E8, 0x0138, 0x00, 0x04E8, 0x01, 0x00),
+ MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK = IOMUX_PAD(0x02E8, 0x0138, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD3_CLK__LPUART1_CTS_B = IOMUX_PAD(0x02E8, 0x0138, 0x02, 0x0454, 0x00, 0x00),
+ MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x02E8, 0x0138, 0x04, 0x03B4, 0x01, 0x00),
+ MX91_PAD_SD3_CLK__GPIO3_IO20 = IOMUX_PAD(0x02E8, 0x0138, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x02EC, 0x013C, 0x00, 0x04EC, 0x01, 0x00),
+ MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B = IOMUX_PAD(0x02EC, 0x013C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD3_CMD__LPUART1_RTS_B = IOMUX_PAD(0x02EC, 0x013C, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 = IOMUX_PAD(0x02EC, 0x013C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD3_CMD__GPIO3_IO21 = IOMUX_PAD(0x02EC, 0x013C, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x02F0, 0x0140, 0x00, 0x04F0, 0x01, 0x00),
+ MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 = IOMUX_PAD(0x02F0, 0x0140, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD3_DATA0__LPUART2_CTS_B = IOMUX_PAD(0x02F0, 0x0140, 0x02, 0x0460, 0x00, 0x00),
+ MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x02F0, 0x0140, 0x04, 0x03B8, 0x01, 0x00),
+ MX91_PAD_SD3_DATA0__GPIO3_IO22 = IOMUX_PAD(0x02F0, 0x0140, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x02F4, 0x0144, 0x00, 0x04F4, 0x01, 0x00),
+ MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 = IOMUX_PAD(0x02F4, 0x0144, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD3_DATA1__LPUART2_RTS_B = IOMUX_PAD(0x02F4, 0x0144, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x02F4, 0x0144, 0x04, 0x03BC, 0x01, 0x00),
+ MX91_PAD_SD3_DATA1__GPIO3_IO23 = IOMUX_PAD(0x02F4, 0x0144, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x02F8, 0x0148, 0x00, 0x04F8, 0x01, 0x00),
+ MX91_PAD_SD3_DATA2__LPI2C4_SDA = IOMUX_PAD(0x02F8, 0x0148, 0x02, 0x03FC, 0x01, 0x00),
+ MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 = IOMUX_PAD(0x02F8, 0x0148, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x02F8, 0x0148, 0x04, 0x03C0, 0x01, 0x00),
+ MX91_PAD_SD3_DATA2__GPIO3_IO24 = IOMUX_PAD(0x02F8, 0x0148, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x02FC, 0x014C, 0x00, 0x04FC, 0x01, 0x00),
+ MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 = IOMUX_PAD(0x02FC, 0x014C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD3_DATA3__LPI2C4_SCL = IOMUX_PAD(0x02FC, 0x014C, 0x02, 0x03F8, 0x01, 0x00),
+ MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x02FC, 0x014C, 0x04, 0x03C4, 0x01, 0x00),
+ MX91_PAD_SD3_DATA3__GPIO3_IO25 = IOMUX_PAD(0x02FC, 0x014C, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0300, 0x0150, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0300, 0x0150, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CD_B__I3C2_SCL = IOMUX_PAD(0x0300, 0x0150, 0x02, 0x03CC, 0x01, 0x00),
+ MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 = IOMUX_PAD(0x0300, 0x0150, 0x04, 0x036C, 0x01, 0x00),
+ MX91_PAD_SD2_CD_B__GPIO3_IO0 = IOMUX_PAD(0x0300, 0x0150, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CD_B__LPI2C1_SCL = IOMUX_PAD(0x0300, 0x0150, 0x03, 0x03E0, 0x01, 0x00),
+
+ MX91_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0304, 0x0154, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0304, 0x0154, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CLK__I2C1_SDA = IOMUX_PAD(0x0304, 0x0154, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CLK__I3C2_SDA = IOMUX_PAD(0x0304, 0x0154, 0x02, 0x03D0, 0x01, 0x00),
+ MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 = IOMUX_PAD(0x0304, 0x0154, 0x04, 0x0370, 0x01, 0x00),
+ MX91_PAD_SD2_CLK__GPIO3_IO1 = IOMUX_PAD(0x0304, 0x0154, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0304, 0x0154, 0x06, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CLK__LPI2C1_SDA = IOMUX_PAD(0x0304, 0x0154, 0x03, 0x03E4, 0x01, 0x00),
+
+ MX91_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0308, 0x0158, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x0308, 0x0158, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CMD__I3C2_PUR = IOMUX_PAD(0x0308, 0x0158, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CMD__I3C2_PUR_B = IOMUX_PAD(0x0308, 0x0158, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 = IOMUX_PAD(0x0308, 0x0158, 0x04, 0x0374, 0x01, 0x00),
+ MX91_PAD_SD2_CMD__GPIO3_IO2 = IOMUX_PAD(0x0308, 0x0158, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0308, 0x0158, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x030C, 0x015C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x030C, 0x015C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA0__CAN2_TX = IOMUX_PAD(0x030C, 0x015C, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 = IOMUX_PAD(0x030C, 0x015C, 0x04, 0x0378, 0x01, 0x00),
+ MX91_PAD_SD2_DATA0__GPIO3_IO3 = IOMUX_PAD(0x030C, 0x015C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA0__LPUART1_TX = IOMUX_PAD(0x030C, 0x015C, 0x03, 0x045C, 0x00, 0x00),
+ MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x030C, 0x015C, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0310, 0x0160, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0310, 0x0160, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA1__CAN2_RX = IOMUX_PAD(0x0310, 0x0160, 0x02, 0x0364, 0x03, 0x00),
+ MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 = IOMUX_PAD(0x0310, 0x0160, 0x04, 0x037C, 0x01, 0x00),
+ MX91_PAD_SD2_DATA1__GPIO3_IO4 = IOMUX_PAD(0x0310, 0x0160, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA1__LPUART1_RX = IOMUX_PAD(0x0310, 0x0160, 0x03, 0x0458, 0x00, 0x00),
+ MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0310, 0x0160, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0314, 0x0164, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x0314, 0x0164, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA2__MQS2_RIGHT = IOMUX_PAD(0x0314, 0x0164, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 = IOMUX_PAD(0x0314, 0x0164, 0x04, 0x0380, 0x01, 0x00),
+ MX91_PAD_SD2_DATA2__GPIO3_IO5 = IOMUX_PAD(0x0314, 0x0164, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA2__LPUART2_TX = IOMUX_PAD(0x0314, 0x0164, 0x03, 0x0468, 0x00, 0x00),
+ MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0314, 0x0164, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0318, 0x0168, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA3__LPTMR2_ALT1 = IOMUX_PAD(0x0318, 0x0168, 0x01, 0x0448, 0x01, 0x00),
+ MX91_PAD_SD2_DATA3__MQS2_LEFT = IOMUX_PAD(0x0318, 0x0168, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 = IOMUX_PAD(0x0318, 0x0168, 0x04, 0x0384, 0x01, 0x00),
+ MX91_PAD_SD2_DATA3__GPIO3_IO6 = IOMUX_PAD(0x0318, 0x0168, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_DATA3__LPUART2_RX = IOMUX_PAD(0x0318, 0x0168, 0x03, 0x0464, 0x00, 0x00),
+ MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0318, 0x0168, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x031C, 0x016C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 = IOMUX_PAD(0x031C, 0x016C, 0x01, 0x044C, 0x01, 0x00),
+ MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 = IOMUX_PAD(0x031C, 0x016C, 0x04, 0x0388, 0x01, 0x00),
+ MX91_PAD_SD2_RESET_B__GPIO3_IO7 = IOMUX_PAD(0x031C, 0x016C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x031C, 0x016C, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_I2C1_SCL__LPI2C1_SCL = IOMUX_PAD(0x0320, 0x0170, 0x00, 0x03E0, 0x02, 0x00),
+ MX91_PAD_I2C1_SCL__I3C1_SCL = IOMUX_PAD(0x0320, 0x0170, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C1_SCL__LPUART1_DCB_B = IOMUX_PAD(0x0320, 0x0170, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C1_SCL__TPM2_CH0 = IOMUX_PAD(0x0320, 0x0170, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C1_SCL__GPIO1_IO0 = IOMUX_PAD(0x0320, 0x0170, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_I2C1_SDA__LPI2C1_SDA = IOMUX_PAD(0x0324, 0x0174, 0x00, 0x03E4, 0x02, 0x00),
+ MX91_PAD_I2C1_SDA__I3C1_SDA = IOMUX_PAD(0x0324, 0x0174, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C1_SDA__LPUART1_RIN_B = IOMUX_PAD(0x0324, 0x0174, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C1_SDA__TPM2_CH1 = IOMUX_PAD(0x0324, 0x0174, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C1_SDA__GPIO1_IO1 = IOMUX_PAD(0x0324, 0x0174, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_I2C2_SCL__LPI2C2_SCL = IOMUX_PAD(0x0328, 0x0178, 0x00, 0x03E8, 0x01, 0x00),
+ MX91_PAD_I2C2_SCL__I3C1_PUR = IOMUX_PAD(0x0328, 0x0178, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C2_SCL__LPUART2_DCB_B = IOMUX_PAD(0x0328, 0x0178, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C2_SCL__TPM2_CH2 = IOMUX_PAD(0x0328, 0x0178, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C2_SCL__SAI1_RX_SYNC = IOMUX_PAD(0x0328, 0x0178, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C2_SCL__GPIO1_IO3 = IOMUX_PAD(0x0328, 0x0178, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C2_SCL__I3C1_PUR_B = IOMUX_PAD(0x0328, 0x0178, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_I2C2_SDA__LPI2C2_SDA = IOMUX_PAD(0x032C, 0x017C, 0x00, 0x03EC, 0x01, 0x00),
+ MX91_PAD_I2C2_SDA__LPUART2_RIN_B = IOMUX_PAD(0x032C, 0x017C, 0x02, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C2_SDA__TPM2_CH3 = IOMUX_PAD(0x032C, 0x017C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C2_SDA__SAI1_RX_BCLK = IOMUX_PAD(0x032C, 0x017C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_I2C2_SDA__GPIO1_IO3 = IOMUX_PAD(0x032C, 0x017C, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_UART1_RXD__LPUART1_RX = IOMUX_PAD(0x0330, 0x0180, 0x00, 0x0458, 0x01, 0x00),
+ MX91_PAD_UART1_RXD__ELE_UART_RX = IOMUX_PAD(0x0330, 0x0180, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_UART1_RXD__LPSPI2_SIN = IOMUX_PAD(0x0330, 0x0180, 0x02, 0x0440, 0x02, 0x00),
+ MX91_PAD_UART1_RXD__TPM1_CH0 = IOMUX_PAD(0x0330, 0x0180, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_UART1_RXD__GPIO1_IO4 = IOMUX_PAD(0x0330, 0x0180, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_UART1_TXD__LPUART1_TX = IOMUX_PAD(0x0334, 0x0184, 0x00, 0x045C, 0x01, 0x00),
+ MX91_PAD_UART1_TXD__ELE_UART_TX = IOMUX_PAD(0x0334, 0x0184, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_UART1_TXD__LPSPI2_PCS0 = IOMUX_PAD(0x0334, 0x0184, 0x02, 0x0434, 0x02, 0x00),
+ MX91_PAD_UART1_TXD__TPM1_CH1 = IOMUX_PAD(0x0334, 0x0184, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_UART1_TXD__GPIO1_IO5 = IOMUX_PAD(0x0334, 0x0184, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_UART2_RXD__LPUART2_RX = IOMUX_PAD(0x0338, 0x0188, 0x00, 0x0464, 0x01, 0x00),
+ MX91_PAD_UART2_RXD__LPUART1_CTS_B = IOMUX_PAD(0x0338, 0x0188, 0x01, 0x0454, 0x01, 0x00),
+ MX91_PAD_UART2_RXD__LPSPI2_SOUT = IOMUX_PAD(0x0338, 0x0188, 0x02, 0x0444, 0x02, 0x00),
+ MX91_PAD_UART2_RXD__TPM1_CH2 = IOMUX_PAD(0x0338, 0x0188, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_UART2_RXD__SAI1_MCLK = IOMUX_PAD(0x0338, 0x0188, 0x04, 0x04D4, 0x00, 0x00),
+ MX91_PAD_UART2_RXD__GPIO1_IO6 = IOMUX_PAD(0x0338, 0x0188, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_UART2_TXD__LPUART2_TX = IOMUX_PAD(0x033C, 0x018C, 0x00, 0x0468, 0x01, 0x00),
+ MX91_PAD_UART2_TXD__LPUART1_RTS_B = IOMUX_PAD(0x033C, 0x018C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_UART2_TXD__LPSPI2_SCK = IOMUX_PAD(0x033C, 0x018C, 0x02, 0x043C, 0x02, 0x00),
+ MX91_PAD_UART2_TXD__TPM1_CH3 = IOMUX_PAD(0x033C, 0x018C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_UART2_TXD__GPIO1_IO7 = IOMUX_PAD(0x033C, 0x018C, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_UART2_TXD__SAI3_TX_SYNC = IOMUX_PAD(0x033C, 0x018C, 0x07, 0x04E0, 0x02, 0x00),
+
+ MX91_PAD_PDM_CLK__PDM_CLK = IOMUX_PAD(0x0340, 0x0190, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_CLK__MQS1_LEFT = IOMUX_PAD(0x0340, 0x0190, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_CLK__LPTMR1_ALT1 = IOMUX_PAD(0x0340, 0x0190, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_CLK__GPIO1_IO8 = IOMUX_PAD(0x0340, 0x0190, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_CLK__CAN1_TX = IOMUX_PAD(0x0340, 0x0190, 0x06, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 = IOMUX_PAD(0x0344, 0x0194, 0x00, 0x04C4, 0x02, 0x00),
+ MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT = IOMUX_PAD(0x0344, 0x0194, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 = IOMUX_PAD(0x0344, 0x0194, 0x02, 0x0424, 0x01, 0x00),
+ MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK = IOMUX_PAD(0x0344, 0x0194, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 = IOMUX_PAD(0x0344, 0x0194, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 = IOMUX_PAD(0x0344, 0x0194, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_BIT_STREAM0__CAN1_RX = IOMUX_PAD(0x0344, 0x0194, 0x06, 0x0360, 0x01, 0x00),
+
+ MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 = IOMUX_PAD(0x0348, 0x0198, 0x00, 0x04C8, 0x02, 0x00),
+ MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 = IOMUX_PAD(0x0348, 0x0198, 0x02, 0x0438, 0x01, 0x00),
+ MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK = IOMUX_PAD(0x0348, 0x0198, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 = IOMUX_PAD(0x0348, 0x0198, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 = IOMUX_PAD(0x0348, 0x0198, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0348, 0x0198, 0x06, 0x0368, 0x01, 0x00),
+
+ MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x034C, 0x019C, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 = IOMUX_PAD(0x034C, 0x019C, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 = IOMUX_PAD(0x034C, 0x019C, 0x02, 0x0420, 0x01, 0x00),
+ MX91_PAD_SAI1_TXFS__LPUART2_DTR_B = IOMUX_PAD(0x034C, 0x019C, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXFS__MQS1_LEFT = IOMUX_PAD(0x034C, 0x019C, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXFS__GPIO1_IO11 = IOMUX_PAD(0x034C, 0x019C, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x0350, 0x01A0, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXC__LPUART2_CTS_B = IOMUX_PAD(0x0350, 0x01A0, 0x01, 0x0460, 0x01, 0x00),
+ MX91_PAD_SAI1_TXC__LPSPI1_SIN = IOMUX_PAD(0x0350, 0x01A0, 0x02, 0x042C, 0x01, 0x00),
+ MX91_PAD_SAI1_TXC__LPUART1_DSR_B = IOMUX_PAD(0x0350, 0x01A0, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXC__CAN1_RX = IOMUX_PAD(0x0350, 0x01A0, 0x04, 0x0360, 0x02, 0x00),
+ MX91_PAD_SAI1_TXC__GPIO1_IO12 = IOMUX_PAD(0x0350, 0x01A0, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x0354, 0x01A4, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXD0__LPUART2_RTS_B = IOMUX_PAD(0x0354, 0x01A4, 0x01, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXD0__LPSPI1_SCK = IOMUX_PAD(0x0354, 0x01A4, 0x02, 0x0428, 0x01, 0x00),
+ MX91_PAD_SAI1_TXD0__LPUART1_DTR_B = IOMUX_PAD(0x0354, 0x01A4, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXD0__CAN1_TX = IOMUX_PAD(0x0354, 0x01A4, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXD0__GPIO1_IO13 = IOMUX_PAD(0x0354, 0x01A4, 0x05, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_TXD0__SAI1_MCLK = IOMUX_PAD(0x0354, 0x01A4, 0x06, 0x04D4, 0x01, 0x00),
+
+ MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x0358, 0x01A8, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_RXD0__SAI1_MCLK = IOMUX_PAD(0x0358, 0x01A8, 0x01, 0x04D4, 0x02, 0x00),
+ MX91_PAD_SAI1_RXD0__LPSPI1_SOUT = IOMUX_PAD(0x0358, 0x01A8, 0x02, 0x0430, 0x01, 0x00),
+ MX91_PAD_SAI1_RXD0__LPUART2_DSR_B = IOMUX_PAD(0x0358, 0x01A8, 0x03, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_RXD0__MQS1_RIGHT = IOMUX_PAD(0x0358, 0x01A8, 0x04, 0x0000, 0x00, 0x00),
+ MX91_PAD_SAI1_RXD0__GPIO1_IO14 = IOMUX_PAD(0x0358, 0x01A8, 0x05, 0x0000, 0x00, 0x00),
+
+ MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY = IOMUX_PAD(0x035C, 0x01AC, 0x00, 0x0000, 0x00, 0x00),
+ MX91_PAD_WDOG_ANY__GPIO1_IO15 = IOMUX_PAD(0x035C, 0x01AC, 0x05, 0x0000, 0x00, 0x00),
+};
+#endif /* __ASM_ARCH_IMX91_PINS_H__ */
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index 0492abd..149c7b7 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -86,7 +86,7 @@
#define IOMUX_CONFIG_LPSR 0x20
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
-#ifdef CONFIG_IMX93
+#if defined(CONFIG_IMX93) || defined(CONFIG_IMX91)
#define PAD_CTL_FSEL2 (0x2 << 7)
#define PAD_CTL_FSEL3 (0x3 << 7)
#define PAD_CTL_PUE (0x1 << 9)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 31ace97..109a806 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -97,6 +97,12 @@
#define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
#define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
+#define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
+#define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111))
+#define is_imx9101() (is_cpu_type(MXC_CPU_IMX9101))
+#define is_imx91() (is_cpu_type(MXC_CPU_IMX91) || is_cpu_type(MXC_CPU_IMX9111) || \
+ is_cpu_type(MXC_CPU_IMX9101) || is_cpu_type(MXC_CPU_IMX9121))
+
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 52f6c9b..dbf9ab4 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -171,7 +171,7 @@
return 3 & (el >> 2);
}
-static inline unsigned int get_sctlr(void)
+static inline unsigned long get_sctlr(void)
{
unsigned int el;
unsigned long val;
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index 1e7dc10..9cf6037 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -16,8 +16,8 @@
config ASPEED_AST2500
bool "Support Aspeed AST2500 SoC"
- depends on DM_RESET
select CPU_ARM1176
+ select DM_RESET
help
The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
It is used as Board Management Controller on many server boards,
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 59d11b3..9a43bed 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -54,15 +54,8 @@
select BOARD_LATE_INIT
select IMX8QXP
-config TARGET_DENEB
- bool "Support i.MX8QXP Capricorn Deneb board"
- select BINMAN
- select BOARD_LATE_INIT
- select FACTORYSET
- select IMX8QXP
-
-config TARGET_GIEDI
- bool "Support i.MX8QXP Capricorn Giedi board"
+config TARGET_CAPRICORN
+ bool "Support i.MX8QXP Capricorn board"
select BINMAN
select BOARD_LATE_INIT
select FACTORYSET
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 5c10541..54c6b11 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -16,6 +16,12 @@
select IMX9
select ARMV8_SPL_EXCEPTION_VECTORS
+config IMX91
+ bool
+ select IMX9
+ select ARMV8_SPL_EXCEPTION_VECTORS
+
+
config SYS_SOC
default "imx9"
@@ -23,6 +29,12 @@
prompt "NXP i.MX9 board select"
optional
+config TARGET_IMX91_11X11_EVK
+ bool "imx91_11x11_evk"
+ select OF_BOARD_FIXUP
+ select IMX91
+ imply OF_UPSTREAM
+
config TARGET_IMX93_9X9_QSB
bool "imx93_qsb"
select OF_BOARD_FIXUP
@@ -45,9 +57,12 @@
bool "phycore_imx93"
select IMX93
select IMX9_LPDDR4X
+ select OF_BOARD_FIXUP
+ select OF_BOARD_SETUP
endchoice
+source "board/freescale/imx91_evk/Kconfig"
source "board/freescale/imx93_evk/Kconfig"
source "board/freescale/imx93_qsb/Kconfig"
source "board/phytec/phycore_imx93/Kconfig"
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index c00be19..e65cabe 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -30,6 +30,7 @@
INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
+ INT_PLL_RATE(800000000U, 1, 200, 6), /* 800Mhz */
};
static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
@@ -37,12 +38,14 @@
FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
FRAC_PLL_RATE(800000000U, 1, 200, 6, 0, 1), /* 800Mhz */
FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
+ FRAC_PLL_RATE(600000000U, 1, 200, 8, 0, 1), /* 600Mhz */
FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
FRAC_PLL_RATE(233000000U, 1, 174, 18, 3, 4), /* 233Mhz */
+ FRAC_PLL_RATE(200000000U, 1, 200, 24, 0, 1), /* 200Mhz */
};
/* return in khz */
@@ -723,7 +726,7 @@
/* SWO TRACE to 133M */
{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 systetick to 24M */
- {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
+ {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1, CLK_SOC_IMX93},
/* NIC to 250M */
{NIC_CLK_ROOT, SYS_PLL_PFD0, 4},
/* NIC_APB to 133M */
@@ -753,13 +756,17 @@
* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
* generating MII clock at 2.5M
*/
- {WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2},
+ {WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2, CLK_SOC_IMX93},
+ /* Wakeup AXI 250M*/
+ {WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD0, 4, CLK_SOC_IMX91},
/* SWO TRACE to 133M */
{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 systetick to 24M */
- {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
+ {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1, CLK_SOC_IMX93},
/* NIC to 400M */
- {NIC_CLK_ROOT, SYS_PLL_PFD1, 2},
+ {NIC_CLK_ROOT, SYS_PLL_PFD1, 2, CLK_SOC_IMX93},
+ /* NIC to 333M */
+ {NIC_CLK_ROOT, SYS_PLL_PFD0, 3, CLK_SOC_IMX91},
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
@@ -769,8 +776,12 @@
int i;
for (i = 0; i < ARRAY_SIZE(imx_clk_ld_settings); i++) {
- ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
- imx_clk_ld_settings[i].src, imx_clk_ld_settings[i].div);
+ if (imx_clk_ld_settings[i].soc == CLK_SOC_ALL ||
+ (is_imx91() && imx_clk_ld_settings[i].soc == CLK_SOC_IMX91) ||
+ (is_imx93() && imx_clk_ld_settings[i].soc == CLK_SOC_IMX93)) {
+ ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
+ imx_clk_ld_settings[i].src, imx_clk_ld_settings[i].div);
+ }
}
}
@@ -779,8 +790,12 @@
int i;
for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) {
- ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
- imx_clk_settings[i].src, imx_clk_settings[i].div);
+ if (imx_clk_settings[i].soc == CLK_SOC_ALL ||
+ (is_imx91() && imx_clk_settings[i].soc == CLK_SOC_IMX91) ||
+ (is_imx93() && imx_clk_settings[i].soc == CLK_SOC_IMX93)) {
+ ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
+ imx_clk_settings[i].src, imx_clk_settings[i].div);
+ }
}
}
@@ -857,7 +872,7 @@
return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
}
-#if defined(CONFIG_IMX93) && defined(CONFIG_DWC_ETH_QOS)
+#if (CONFIG_IS_ENABLED(IMX93) || CONFIG_IS_ENABLED(IMX91)) && CONFIG_IS_ENABLED(DWC_ETH_QOS)
static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type)
{
struct blk_ctrl_wakeupmix_regs *bctrl =
@@ -901,12 +916,12 @@
int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
{
- if (IS_ENABLED(CONFIG_IMX93) &&
+ if ((IS_ENABLED(CONFIG_IMX93) || IS_ENABLED(CONFIG_IMX91)) &&
IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
device_is_compatible(dev, "nxp,imx93-dwmac-eqos"))
return imx93_eqos_interface_init(dev, interface_type);
- if (IS_ENABLED(CONFIG_IMX93) &&
+ if ((IS_ENABLED(CONFIG_IMX93) || IS_ENABLED(CONFIG_IMX91)) &&
IS_ENABLED(CONFIG_FEC_MXC) &&
device_is_compatible(dev, "fsl,imx93-fec"))
return 0;
diff --git a/arch/arm/mach-imx/imx9/container.cfg b/arch/arm/mach-imx/imx9/container.cfg
index 72fe791..91a9731 100644
--- a/arch/arm/mach-imx/imx9/container.cfg
+++ b/arch/arm/mach-imx/imx9/container.cfg
@@ -6,6 +6,10 @@
BOOT_FROM SD 0x400
SOC_TYPE IMX9
CONTAINER
+#ifdef CONFIG_IMX91
+IMAGE A55 bl31.bin 0x204C0000
+#else
IMAGE A55 bl31.bin 0x204E0000
+#endif
IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
-IMAGE A55 tee.bin 0x96000000
\ No newline at end of file
+IMAGE A55 tee.bin 0x96000000
diff --git a/arch/arm/mach-imx/imx9/imximage.cfg b/arch/arm/mach-imx/imx9/imximage.cfg
index d327d6a..118dfb3 100644
--- a/arch/arm/mach-imx/imx9/imximage.cfg
+++ b/arch/arm/mach-imx/imx9/imximage.cfg
@@ -5,6 +5,10 @@
BOOT_FROM SD 0x400
SOC_TYPE IMX9
+#ifdef CONFIG_IMX91
+APPEND mx91a0-ahab-container.img
+#else
APPEND mx93a1-ahab-container.img
+#endif
CONTAINER
-IMAGE A55 u-boot-spl-ddr.bin 0x2049A000
\ No newline at end of file
+IMAGE A55 u-boot-spl-ddr.bin CONFIG_SPL_TEXT_BASE
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 21e0e7d..bb13ca7 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -118,6 +118,8 @@
if (is_imx93())
max_speed = MHZ(1700);
+ else if (is_imx91())
+ max_speed = MHZ(1400);
/* In case the fuse of speed grade not programmed */
if (speed > max_speed)
@@ -195,7 +197,30 @@
bool npu_disable = !!(val & BIT(13));
bool core1_disable = !!(val & BIT(15));
- u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+ u32 pack_9x9_fused = BIT(4) | BIT(5) | BIT(17) | BIT(19) | BIT(24);
+ u32 nxp_recog = (val & GENMASK(23, 16)) >> 16;
+
+ /* For iMX91 */
+ if (type == MXC_CPU_IMX91) {
+ switch (nxp_recog) {
+ case 0x9:
+ case 0xA:
+ type = MXC_CPU_IMX9111;
+ break;
+ case 0xD:
+ case 0xE:
+ type = MXC_CPU_IMX9121;
+ break;
+ case 0xF:
+ case 0x10:
+ type = MXC_CPU_IMX9101;
+ break;
+ default:
+ break; /* 9131 as default */
+ }
+
+ return type;
+ }
/* Low performance 93 part */
if (((val >> 6) & 0x3F) == 0xE && npu_disable)
@@ -217,8 +242,14 @@
u32 get_cpu_rev(void)
{
u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+ u32 type;
+
+ if ((gd->arch.soc_rev & 0xFFFF) == 0x9300)
+ type = MXC_CPU_IMX93;
+ else
+ type = MXC_CPU_IMX91;
- return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) |
+ return (get_cpu_variant_type(type) << 12) |
(CHIP_REV_1_0 + rev);
}
@@ -539,7 +570,8 @@
cpurev = get_cpu_rev();
- printf("CPU: i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
+ printf("CPU: i.MX%s rev%d.%d\n", is_imx93() ? "93" : "91",
+ (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
return 0;
}
@@ -634,7 +666,7 @@
return 0;
}
-#ifdef CONFIG_OF_BOARD_FIXUP
+#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93)
#ifndef CONFIG_XPL_BUILD
int board_fix_fdt(void *fdt)
{
@@ -893,7 +925,9 @@
void soc_power_init(void)
{
mix_power_init(MIX_PD_MEDIAMIX);
- mix_power_init(MIX_PD_MLMIX);
+
+ if (is_imx93())
+ mix_power_init(MIX_PD_MLMIX);
disable_isolation();
}
@@ -919,6 +953,9 @@
(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
u32 val, i;
+ if (is_imx91())
+ return -ENODEV;
+
if (m33_is_rom_kicked())
return -EPERM;
@@ -1007,7 +1044,7 @@
u32 speed = get_cpu_speed_grade_hz();
enum imx9_soc_voltage_mode voltage = VOLT_OVER_DRIVE;
- if (is_imx93()) {
+ if (is_imx93() || is_imx91()) {
if (speed == 1700000000)
voltage = VOLT_OVER_DRIVE;
else if (speed == 1400000000)
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index ef0f8b5..d7593ec 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -484,7 +484,7 @@
}
}
-#if DEBUG
+#ifdef DEBUG
int trdc_mbc_control_dump(ulong trdc_reg, u32 mbc_x, u32 glbac_id)
{
struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
diff --git a/arch/arm/mach-k3/am62ax/Kconfig b/arch/arm/mach-k3/am62ax/Kconfig
index bbd5497..f8cdcdc 100644
--- a/arch/arm/mach-k3/am62ax/Kconfig
+++ b/arch/arm/mach-k3/am62ax/Kconfig
@@ -30,8 +30,29 @@
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
+config TARGET_PHYCORE_AM62AX_A53
+ bool "PHYTEC phyCORE-AM62Ax running on A53"
+ select ARM64
+ select BINMAN
+ select OF_SYSTEM_SETUP
+ imply OF_UPSTREAM
+ imply BOARD
+ imply SPL_BOARD
+
+config TARGET_PHYCORE_AM62AX_R5
+ bool "PHYTEC phyCORE-AM62Ax running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
endchoice
source "board/ti/am62ax/Kconfig"
+source "board/phytec/phycore_am62ax/Kconfig"
endif
diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile
index e2ef881..4e35e0c 100644
--- a/arch/arm/mach-k3/am62ax/Makefile
+++ b/arch/arm/mach-k3/am62ax/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o
obj-$(CONFIG_XPL_BUILD) += am62a7_init.o
+obj-y += boot.o
diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c
index 0f62f39..5c0d3ee 100644
--- a/arch/arm/mach-k3/am62ax/am62a7_init.c
+++ b/arch/arm/mach-k3/am62ax/am62a7_init.c
@@ -171,102 +171,7 @@
debug("am62a_init: %s done\n", __func__);
}
-static u32 __get_backup_bootmedia(u32 devstat)
-{
- u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
- u32 bkup_bootmode_cfg =
- (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
-
- switch (bkup_bootmode) {
- case BACKUP_BOOT_DEVICE_UART:
- return BOOT_DEVICE_UART;
-
- case BACKUP_BOOT_DEVICE_USB:
- return BOOT_DEVICE_USB;
-
- case BACKUP_BOOT_DEVICE_ETHERNET:
- return BOOT_DEVICE_ETHERNET;
-
- case BACKUP_BOOT_DEVICE_MMC:
- if (bkup_bootmode_cfg)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BACKUP_BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BACKUP_BOOT_DEVICE_I2C:
- return BOOT_DEVICE_I2C;
-
- case BACKUP_BOOT_DEVICE_DFU:
- if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
- };
-
- return BOOT_DEVICE_RAM;
-}
-
-static u32 __get_primary_bootmedia(u32 devstat)
-{
- u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
- u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
- MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
-
- switch (bootmode) {
- case BOOT_DEVICE_OSPI:
- fallthrough;
- case BOOT_DEVICE_QSPI:
- fallthrough;
- case BOOT_DEVICE_XSPI:
- fallthrough;
- case BOOT_DEVICE_SPI:
- return BOOT_DEVICE_SPI;
-
- case BOOT_DEVICE_ETHERNET_RGMII:
- fallthrough;
- case BOOT_DEVICE_ETHERNET_RMII:
- return BOOT_DEVICE_ETHERNET;
-
- case BOOT_DEVICE_EMMC:
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_SPI_NAND:
- return BOOT_DEVICE_SPINAND;
-
- case BOOT_DEVICE_MMC:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
- MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
- return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1;
-
- case BOOT_DEVICE_DFU:
- if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
- MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
- return BOOT_DEVICE_USB;
- return BOOT_DEVICE_DFU;
-
- case BOOT_DEVICE_NOBOOT:
- return BOOT_DEVICE_RAM;
- }
-
- return bootmode;
-}
-
u32 spl_boot_device(void)
{
- u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
- u32 bootmedia;
-
- if (bootindex == K3_PRIMARY_BOOTMODE)
- bootmedia = __get_primary_bootmedia(devstat);
- else
- bootmedia = __get_backup_bootmedia(devstat);
-
- debug("am62a_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
- __func__, devstat, bootmedia, bootindex);
- return bootmedia;
+ return get_boot_device();
}
diff --git a/arch/arm/mach-k3/am62ax/boot.c b/arch/arm/mach-k3/am62ax/boot.c
new file mode 100644
index 0000000..af7fce1
--- /dev/null
+++ b/arch/arm/mach-k3/am62ax/boot.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/am62a_spl.h>
+
+static u32 __get_backup_bootmedia(u32 devstat)
+{
+ u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
+ u32 bkup_bootmode_cfg =
+ (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
+
+ switch (bkup_bootmode) {
+ case BACKUP_BOOT_DEVICE_UART:
+ return BOOT_DEVICE_UART;
+
+ case BACKUP_BOOT_DEVICE_USB:
+ return BOOT_DEVICE_USB;
+
+ case BACKUP_BOOT_DEVICE_ETHERNET:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BACKUP_BOOT_DEVICE_MMC:
+ if (bkup_bootmode_cfg)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BACKUP_BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BACKUP_BOOT_DEVICE_I2C:
+ return BOOT_DEVICE_I2C;
+
+ case BACKUP_BOOT_DEVICE_DFU:
+ if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+ };
+
+ return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 devstat)
+{
+ u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+ u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+ switch (bootmode) {
+ case BOOT_DEVICE_OSPI:
+ fallthrough;
+ case BOOT_DEVICE_QSPI:
+ fallthrough;
+ case BOOT_DEVICE_XSPI:
+ fallthrough;
+ case BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BOOT_DEVICE_ETHERNET_RGMII:
+ fallthrough;
+ case BOOT_DEVICE_ETHERNET_RMII:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BOOT_DEVICE_EMMC:
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_SPI_NAND:
+ return BOOT_DEVICE_SPINAND;
+
+ case BOOT_DEVICE_MMC:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_DFU:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+
+ case BOOT_DEVICE_NOBOOT:
+ return BOOT_DEVICE_RAM;
+ }
+
+ return bootmode;
+}
+
+u32 get_boot_device(void)
+{
+ u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+ u32 bootmode = *(u32 *)(K3_BOOT_PARAM_TABLE_INDEX_OCRAM);
+ u32 bootmedia;
+
+ if (bootmode == K3_PRIMARY_BOOTMODE)
+ bootmedia = __get_primary_bootmedia(devstat);
+ else
+ bootmedia = __get_backup_bootmedia(devstat);
+
+ debug("%s: devstat = 0x%x bootmedia = 0x%x bootmode = %d\n",
+ __func__, devstat, bootmedia, bootmode);
+
+ return bootmedia;
+}
diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c
index 34ed01c..2d35a7c 100644
--- a/arch/arm/mach-k3/am62px/am62p5_init.c
+++ b/arch/arm/mach-k3/am62px/am62p5_init.c
@@ -159,6 +159,8 @@
}
spl_enable_cache();
+
+ setup_qos();
debug("am62px_init: %s done\n", __func__);
}
diff --git a/arch/arm/mach-k3/am62x/Kconfig b/arch/arm/mach-k3/am62x/Kconfig
index 8b0cdd7..81199ad 100644
--- a/arch/arm/mach-k3/am62x/Kconfig
+++ b/arch/arm/mach-k3/am62x/Kconfig
@@ -42,6 +42,7 @@
select SPL_RAM
select K3_DDRSS
select BINMAN
+ select PHYTEC_K3_DDR_PATCH
imply SYS_K3_SPL_ATF
config TARGET_VERDIN_AM62_A53
diff --git a/arch/arm/mach-k3/am65x/Kconfig b/arch/arm/mach-k3/am65x/Kconfig
index f17b641..72a8298 100644
--- a/arch/arm/mach-k3/am65x/Kconfig
+++ b/arch/arm/mach-k3/am65x/Kconfig
@@ -16,6 +16,7 @@
select BOARD_LATE_INIT
select BINMAN
imply TI_I2C_BOARD_DETECT
+ select OF_UPSTREAM
config TARGET_AM654_R5_EVM
bool "TI K3 based AM654 EVM running on R5"
diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c
index e9ed8cb..805b28a 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -19,6 +19,7 @@
#include <fdtdec.h>
#include <mmc.h>
#include <remoteproc.h>
+#include <k3-avs.h>
#include "../sysfw-loader.h"
#include "../common.h"
@@ -39,6 +40,12 @@
#define NB_THREADMAP_BIT0 BIT(0)
#define NB_THREADMAP_BIT1 BIT(1)
+/* TISCI DEV ID for A72, MSMC Clock */
+#define DEV_A72SS0_CORE0_0_ID 202
+#define DEV_A72SS0_CORE0_0_ARM_CLK_CLK_ID 2
+#define DEV_A72SS0_CORE0_ID 4
+#define DEV_A72SS0_CORE0_MSMC_CLK_ID 1
+
#ifdef CONFIG_K3_LOAD_SYSFW
struct fwl_data cbass_hc_cfg0_fwls[] = {
#if defined(CONFIG_TARGET_J721E_R5_EVM)
@@ -147,6 +154,78 @@
writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
}
+#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
+static int get_clock_index_by_dev_id(ofnode node, u32 dev_id, u32 clk_id)
+{
+ ofnode clknode;
+ int count, i;
+ struct ofnode_phandle_args phandle_args;
+
+ clknode = ofnode_by_compatible(ofnode_null(), "ti,k2g-sci-clk");
+ if (!ofnode_valid(clknode)) {
+ printf("%s: clock-controller not found\n", __func__);
+ return -ENODEV;
+ }
+
+ count = ofnode_count_phandle_with_args(node, "assigned-clocks", "#clock-cells", 0);
+ for (i = 0; i < count; i++) {
+ if (ofnode_parse_phandle_with_args(node, "assigned-clocks",
+ "#clock-cells", 0, i, &phandle_args)) {
+ printf("%s: Could not parse assigned-clocks at index %d\n", __func__, i);
+ continue;
+ }
+ if (ofnode_equal(clknode, phandle_args.node) &&
+ phandle_args.args[0] == dev_id && phandle_args.args[1] == clk_id)
+ return i;
+ }
+ return -1;
+}
+
+static int fdt_fixup_a72ss_clock_frequency(void)
+{
+ int index, size;
+ u32 *rates;
+ ofnode node;
+
+ node = ofnode_by_compatible(ofnode_null(), "ti,am654-rproc");
+ if (!ofnode_valid(node)) {
+ printf("%s: A72 not found\n", __func__);
+ return -ENODEV;
+ }
+
+ rates = fdt_getprop_w(ofnode_to_fdt(node), ofnode_to_offset(node),
+ "assigned-clock-rates", &size);
+ if (!rates) {
+ printf("%s: Wrong A72 assigned-clocks-rates configuration\n", __func__);
+ return -1;
+ }
+
+ /* Update A72 Clock Frequency to OPP_LOW spec */
+ index = get_clock_index_by_dev_id(node,
+ DEV_A72SS0_CORE0_0_ID,
+ DEV_A72SS0_CORE0_0_ARM_CLK_CLK_ID);
+ if (index < 0 || index >= (size / sizeof(u32))) {
+ printf("%s: Wrong A72 assigned-clocks configuration\n", __func__);
+ return -1;
+ }
+ rates[index] = cpu_to_fdt32(1000000000);
+ printf("Changed A72 CPU frequency to %dHz in DT\n", 1000000000);
+
+ /* Update MSMC Clock Frequency to OPP_LOW spec */
+ index = get_clock_index_by_dev_id(node,
+ DEV_A72SS0_CORE0_ID,
+ DEV_A72SS0_CORE0_MSMC_CLK_ID);
+ if (index < 0 || index >= (size / sizeof(u32))) {
+ printf("%s: Wrong A72 assigned-clocks configuration\n", __func__);
+ return -1;
+ }
+ rates[index] = cpu_to_fdt32(500000000);
+ printf("Changed MSMC frequency to %dHz in DT\n", 500000000);
+
+ return 0;
+}
+#endif
+
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
@@ -301,8 +380,19 @@
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
&dev);
- if (ret)
+ if (ret) {
printf("AVS init failed: %d\n", ret);
+ } else if (IS_ENABLED(CONFIG_K3_OPP_LOW)) {
+ ret = k3_avs_check_opp(dev, J721E_VDD_MPU, AM6_OPP_LOW);
+ if (ret) {
+ printf("OPP_LOW: k3_avs_check_opp failed: %d\n", ret);
+ } else {
+ ret = fdt_fixup_a72ss_clock_frequency();
+ if (ret)
+ printf("OPP_LOW: fdt_fixup_a72ss_clock_frequency failed: %d\n",
+ ret);
+ }
+ }
#endif
#if defined(CONFIG_K3_J721E_DDRSS)
diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c
index 01b0068..0313e11 100644
--- a/arch/arm/mach-k3/j722s/j722s_init.c
+++ b/arch/arm/mach-k3/j722s/j722s_init.c
@@ -165,6 +165,7 @@
{
k3_spl_init();
k3_mem_init();
+ setup_qos();
}
static u32 __get_backup_bootmedia(u32 devstat)
diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 07b5d7d..8a41cd3 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -233,9 +233,19 @@
void board_init_f(ulong dummy)
{
+ struct udevice *dev;
+ int ret;
+
k3_spl_init();
k3_mem_init();
+ if (IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_AVS0)) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
+ &dev);
+ if (ret)
+ printf("AVS init failed: %d\n", ret);
+ }
+
if (IS_ENABLED(CONFIG_CPU_V7R))
setup_navss_nb();
diff --git a/arch/arm/mach-k3/r5/Kconfig b/arch/arm/mach-k3/r5/Kconfig
index 878087f..1233588 100644
--- a/arch/arm/mach-k3/r5/Kconfig
+++ b/arch/arm/mach-k3/r5/Kconfig
@@ -1,6 +1,13 @@
config K3_LOAD_SYSFW
bool
+config K3_OPP_LOW
+ depends on ARCH_K3 && K3_AVS0
+ bool "Enable OPP_LOW on supported TI K3 SoCs"
+ help
+ Enabling this will allow Socs with the proper efuse to run at a lower
+ MPU core voltage and adjust frequency according to SoC TRM
+
config K3_QOS
bool "Enable Quality of Service (QoS) Settings for TI K3 SoCs"
default y if SOC_K3_AM62A7
diff --git a/arch/arm/mach-k3/r5/am62px/Makefile b/arch/arm/mach-k3/r5/am62px/Makefile
index 091d4fa..066c3ce 100644
--- a/arch/arm/mach-k3/r5/am62px/Makefile
+++ b/arch/arm/mach-k3/r5/am62px/Makefile
@@ -4,3 +4,4 @@
obj-y += clk-data.o
obj-y += dev-data.o
+obj-y += am62p_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/am62px/am62p_qos.h b/arch/arm/mach-k3/r5/am62px/am62p_qos.h
new file mode 100644
index 0000000..99e2ee4
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/am62p_qos.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
+#define PULSAR_UL_MAIN_0_CPU0_RMST 0x45D15000
+#define PULSAR_UL_MAIN_0_CPU0_WMST 0x45D15400
+#define PULSAR_UL_MAIN_0_CPU0_PMST 0x45D15800
+#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45D29800
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45D2A000
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D30000
+#define K3_DSS_UL_MAIN_1_VBUSM_DMA 0x45D30400
+#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D34000
+#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D34400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D34800
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D34C00
+#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D35000
+#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D35400
diff --git a/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c b/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
new file mode 100644
index 0000000..d25512a
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am62p Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/k3-qos.h>
+#include "am62p_qos.h"
+
+struct k3_qos_data qos_data[] = {
+ /* modules_qosConfig0 - 1 endpoints, 4 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* modules_qosConfig1 - 1 endpoints, 4 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers. orderID x is remapped to orderID x again
+ * This is to ensure orderID from MAP register is unchanged
+ */
+
+ /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 0 groups */
+
+ /* K3_DSS_UL_MAIN_1_VBUSM_DMA - 0 groups */
+};
+
+u32 qos_count = ARRAY_SIZE(qos_data);
diff --git a/arch/arm/mach-k3/r5/j722s/Makefile b/arch/arm/mach-k3/r5/j722s/Makefile
index 2a0dbf5..2f0b35a 100644
--- a/arch/arm/mach-k3/r5/j722s/Makefile
+++ b/arch/arm/mach-k3/r5/j722s/Makefile
@@ -4,3 +4,4 @@
obj-y += clk-data.o
obj-y += dev-data.o
+obj-y += j722s_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j722s/j722s_qos.h b/arch/arm/mach-k3/r5/j722s/j722s_qos.h
new file mode 100644
index 0000000..88fa208
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/j722s_qos.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
+#define PULSAR_UL_MAIN_0_CPU0_RMST 0x45D15000
+#define PULSAR_UL_MAIN_0_CPU0_WMST 0x45D15400
+#define PULSAR_UL_MAIN_0_CPU0_PMST 0x45D15800
+#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00
+#define USB3P0SS64_16FFC_MAIN_0_MSTR0 0x45D24800
+#define USB3P0SS64_16FFC_MAIN_0_MSTW0 0x45D24C00
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400
+#define SAM67_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800
+#define SAM67_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000
+#define PCIE_G2X1_64_MAIN_0_PCIE_MST_RD 0x45D29000
+#define PCIE_G2X1_64_MAIN_0_PCIE_MST_WR 0x45D29400
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45D29800
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45D2A000
+#define SAM67_C7XV_WRAP_MAIN_1_C7XV_SOC 0x45D2C000
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D30000
+#define K3_DSS_UL_MAIN_1_VBUSM_DMA 0x45D30400
+#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D34000
+#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D34400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D34800
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D34C00
+#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D35000
+#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D35400
diff --git a/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c b/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
new file mode 100644
index 0000000..1d59f49
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * j722s Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/k3-qos.h>
+#include "j722s_qos.h"
+
+struct k3_qos_data qos_data[] = {
+ /* modules_qosConfig0 - 1 endpoints, 4 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* modules_qosConfig1 - 1 endpoints, 4 channels */
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 0),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 1),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 2),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+ {
+ .reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 3),
+ .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+ },
+
+ /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers. orderID x is remapped to orderID x again
+ * This is to ensure orderID from MAP register is unchanged
+ */
+
+ /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 0 groups */
+
+ /* K3_DSS_UL_MAIN_1_VBUSM_DMA - 0 groups */
+};
+
+u32 qos_count = ARRAY_SIZE(qos_data);
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index aea1362..92d61e8 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -132,6 +132,20 @@
even if no eFuses were burnt. This option restores the interface if
possible.
+config BL31_LOAD_ADDR
+ hex "Load address of BL31 image (mostly TF-A)"
+ default 0xfffea000
+ help
+ The load address for the BL31 image. This value is used to build the
+ FIT image header that places BL31 in memory where it will run.
+
+config BL32_LOAD_ADDR
+ hex "Load address of BL32 image (mostly secure OS)"
+ default 0
+ help
+ The load address for the BL32 image. This value is used to build the
+ FIT image header that places BL32 in memory where it will run.
+
config ZYNQ_SDHCI_MAX_FREQ
default 200000000
diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
deleted file mode 100755
index cdecb1c..0000000
--- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
+++ /dev/null
@@ -1,240 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0+
-#
-# script to generate FIT image source for Xilinx ZynqMP boards with
-# ARM Trusted Firmware and multiple device trees (given on the command line)
-#
-# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
-
-BL33="u-boot-nodtb.bin"
-[ -z "$BL31" ] && BL31="bl31.bin"
-BL31_ELF="${BL31%.*}.elf"
-[ -f ${BL31_ELF} ] && ATF_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL31_ELF}" | \
-awk '/Entry point/ { print $3 }'`
-
-[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000"
-ATF_LOAD_ADDR_LOW=`printf 0x%x $((ATF_LOAD_ADDR & 0xffffffff))`
-ATF_LOAD_ADDR_HIGH=`printf 0x%x $((ATF_LOAD_ADDR >> 32))`
-
-[ -z "$BL32" ] && BL32="tee.bin"
-BL32_ELF="${BL32%.*}.elf"
-[ -f ${BL32_ELF} ] && TEE_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL32_ELF}" | \
-awk '/Entry point/ { print $3 }'`
-
-[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0x60000000"
-TEE_LOAD_ADDR_LOW=`printf 0x%x $((TEE_LOAD_ADDR & 0xffffffff))`
-TEE_LOAD_ADDR_HIGH=`printf 0x%x $((TEE_LOAD_ADDR >> 32))`
-
-if [ -z "$BL33_LOAD_ADDR" ];then
- BL33_LOAD_ADDR=`awk '/CONFIG_TEXT_BASE/ { print $3 }' include/generated/autoconf.h`
-fi
-BL33_LOAD_ADDR_LOW=`printf 0x%x $((BL33_LOAD_ADDR & 0xffffffff))`
-BL33_LOAD_ADDR_HIGH=`printf 0x%x $((BL33_LOAD_ADDR >> 32))`
-
-DTB_LOAD_ADDR=`awk '/CONFIG_XILINX_OF_BOARD_DTB_ADDR/ { print $3 }' include/generated/autoconf.h`
-if [ ! -z "$DTB_LOAD_ADDR" ]; then
- DTB_LOAD_ADDR_LOW=`printf 0x%x $((DTB_LOAD_ADDR & 0xffffffff))`
- DTB_LOAD_ADDR_HIGH=`printf 0x%x $((DTB_LOAD_ADDR >> 32))`
- DTB_LOAD="load = <$DTB_LOAD_ADDR_HIGH $DTB_LOAD_ADDR_LOW>;"
-else
- DTB_LOAD=""
-fi
-
-if [ -z "$*" ]; then
- DT=arch/arm/dts/${DEVICE_TREE}.dtb
-else
- DT=$*
-fi
-
-if [ ! -f $BL31 ]; then
- echo "WARNING: BL31 file $BL31 NOT found, U-Boot will run in EL3" >&2
- BL31=/dev/null
-fi
-
-cat << __HEADER_EOF
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-
-/dts-v1/;
-
-/ {
- description = "Configuration for Xilinx ZynqMP SoC";
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- data = /incbin/("$BL33");
- type = "firmware";
- os = "u-boot";
- arch = "arm64";
- compression = "none";
- load = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>;
- entry = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>;
- hash {
- algo = "md5";
- };
- };
-__HEADER_EOF
-
-if [ -f $BL31 ]; then
-cat << __ATF
- atf {
- description = "Trusted Firmware-A";
- data = /incbin/("$BL31");
- type = "firmware";
- os = "arm-trusted-firmware";
- arch = "arm64";
- compression = "none";
- load = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>;
- entry = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>;
- hash {
- algo = "md5";
- };
- };
-__ATF
-fi
-
-if [ -f $BL32 ]; then
-cat << __TEE
- tee {
- description = "TEE firmware";
- data = /incbin/("$BL32");
- type = "firmware";
- os = "tee";
- arch = "arm64";
- compression = "none";
- load = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>;
- entry = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>;
- hash {
- algo = "md5";
- };
- };
-__TEE
-fi
-
-MULTI_DTB=`awk '/CONFIG_MULTI_DTB_FIT / { print $3 }' include/generated/autoconf.h`
-
-if [ 1"$MULTI_DTB" -eq 11 ]; then
- cat << __FDT_IMAGE_EOF
- fdt_1 {
- description = "Multi DTB fit image";
- data = /incbin/("fit-dtb.blob");
- type = "flat_dt";
- arch = "arm64";
- compression = "none";
- $DTB_LOAD
- hash {
- algo = "md5";
- };
- };
- };
- configurations {
- default = "config_1";
-__FDT_IMAGE_EOF
-
-if [ ! -f $BL31 ]; then
-cat << __CONF_SECTION1_EOF
- config_1 {
- description = "Multi DTB without TF-A";
- firmware = "uboot";
- loadables = "fdt_1";
- };
-__CONF_SECTION1_EOF
-else
-if [ -f $BL32 ]; then
-cat << __CONF_SECTION1_EOF
- config_1 {
- description = "Multi DTB with TF-A and TEE";
- firmware = "atf";
- loadables = "uboot", "tee", "fdt_1";
- };
-__CONF_SECTION1_EOF
-else
-cat << __CONF_SECTION1_EOF
- config_1 {
- description = "Multi DTB with TF-A";
- firmware = "atf";
- loadables = "uboot", "fdt_1";
- };
-__CONF_SECTION1_EOF
-fi
-fi
-
-cat << __ITS_EOF
- };
-};
-__ITS_EOF
-
-else
-
-DEFAULT=1
-cnt=1
-for dtname in $DT
-do
- cat << __FDT_IMAGE_EOF
- fdt_$cnt {
- description = "$(basename $dtname .dtb)";
- data = /incbin/("$dtname");
- type = "flat_dt";
- arch = "arm64";
- compression = "none";
- $DTB_LOAD
- hash {
- algo = "md5";
- };
- };
-__FDT_IMAGE_EOF
-
-[ "x$(basename $dtname .dtb)" = "x${DEVICE_TREE}" ] && DEFAULT=$cnt
-
-cnt=$((cnt+1))
-done
-
-cat << __CONF_HEADER_EOF
- };
- configurations {
- default = "config_$DEFAULT";
-
-__CONF_HEADER_EOF
-
-cnt=1
-for dtname in $DT
-do
-if [ ! -f $BL31 ]; then
-cat << __CONF_SECTION1_EOF
- config_$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "uboot";
- fdt = "fdt_$cnt";
- };
-__CONF_SECTION1_EOF
-else
-if [ -f $BL32 ]; then
-cat << __CONF_SECTION1_EOF
- config_$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "atf";
- loadables = "uboot", "tee";
- fdt = "fdt_$cnt";
- };
-__CONF_SECTION1_EOF
-else
-cat << __CONF_SECTION1_EOF
- config_$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "atf";
- loadables = "uboot";
- fdt = "fdt_$cnt";
- };
-__CONF_SECTION1_EOF
-fi
-fi
-
-cnt=$((cnt+1))
-done
-
-cat << __ITS_EOF
- };
-};
-__ITS_EOF
-
-fi
diff --git a/arch/sandbox/cpu/cache.c b/arch/sandbox/cpu/cache.c
index c8a5e64..96b3da4 100644
--- a/arch/sandbox/cpu/cache.c
+++ b/arch/sandbox/cpu/cache.c
@@ -4,12 +4,18 @@
*/
#include <cpu_func.h>
+#include <mapmem.h>
#include <asm/state.h>
void flush_cache(unsigned long addr, unsigned long size)
{
+ void *ptr;
+
+ ptr = map_sysmem(addr, size);
+
/* Clang uses (char *) parameters, GCC (void *) */
- __builtin___clear_cache((void *)addr, (void *)(addr + size));
+ __builtin___clear_cache(map_sysmem(addr, size), ptr + size);
+ unmap_sysmem(ptr);
}
void invalidate_icache_all(void)
diff --git a/arch/sandbox/dts/other.dts b/arch/sandbox/dts/other.dts
index 395a792..515d634 100644
--- a/arch/sandbox/dts/other.dts
+++ b/arch/sandbox/dts/other.dts
@@ -8,13 +8,15 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+
/ {
compatible = "sandbox-other";
#address-cells = <1>;
#size-cells = <1>;
node {
- target = <&target 3 4>;
+ other-phandle = <&target>;
subnode {
compatible = "sandbox-other2";
@@ -25,9 +27,34 @@
};
};
+ other-a-test {
+ other-test-gpios = <&other_gpio_a 1>, <&other_gpio_a 4>,
+ <&other_gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
+ <0>, <&other_gpio_a 12>;
+ other-phandle-value = <&other_gpio_c 10>, <0xFFFFFFFF 20>, <&other_gpio_a 30>;
+ other-phandle-nodes = <&other_phandle_node_1>, <&other_phandle_node_2>;
+ };
+
+ other_gpio_a: other-gpio-a {
+ #gpio-cells = <1>;
+ };
+
+ other_gpio_b: other-gpio-b {
+ #gpio-cells = <5>;
+ };
+
+ other_gpio_c: other-gpio-c {
+ #gpio-cells = <2>;
+ };
+
+ other_phandle_node_1: other-phandle-node-1 {
+ };
+
+ other_phandle_node_2: other-phandle-node-2 {
+ };
+
target: target {
compatible = "sandbox-other2";
- #gpio-cells = <2>;
str-prop = "other";
reg = <0x8000 0x100>;
status = "disabled";
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index dee2801..ae52b37 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -44,6 +44,7 @@
mmc5 = "/mmc5";
mmc6 = "/mmc6";
mmc7 = "/mmc7";
+ mmc8 = "/mmc8";
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
@@ -101,11 +102,12 @@
bootscr-ram-offset = /bits/ 64 <0x12345678>;
bootscr-flash-offset = /bits/ 64 <0>;
bootscr-flash-size = /bits/ 64 <0x2000>;
- boot-led = "sandbox:green";
- activity-led = "sandbox:red";
+ boot-led = <&sandbox_led_green>;
+ activity-led = <&sandbox_led_red>;
testing-bool;
testing-int = <123>;
testing-str = "testing";
+ testing-phandle = <&phandle_node_1>;
};
};
@@ -296,6 +298,12 @@
compatible = "sandbox,dsi-host";
};
+ phandle_node_1: phandle-node-1 {
+ };
+
+ phandle_node_2: phandle-node-2 {
+ };
+
a-test {
reg = <0 1>;
compatible = "denx,u-boot-fdt-test";
@@ -334,6 +342,7 @@
interrupts-extended = <&irq 3 0>;
acpi,name = "GHIJ";
phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
+ phandle-nodes = <&phandle_node_1>, <&phandle_node_2>;
mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
<&muxcontroller0 2>, <&muxcontroller0 3>,
@@ -980,12 +989,12 @@
leds {
compatible = "gpio-leds";
- iracibble {
+ sandbox_led_red: iracibble {
gpios = <&gpio_a 1 0>;
label = "sandbox:red";
};
- martinet {
+ sandbox_led_green: martinet {
gpios = <&gpio_a 2 0>;
label = "sandbox:green";
};
@@ -1138,13 +1147,20 @@
filename = "mmc6.img";
};
- /* This is used for Android tests */
+ /* This is used for Android boot image v4 tests */
mmc7 {
status = "disabled";
compatible = "sandbox,mmc";
filename = "mmc7.img";
};
+ /* This is used for Android boot image v2 tests. */
+ mmc8 {
+ status = "disabled";
+ compatible = "sandbox,mmc";
+ filename = "mmc8.img";
+ };
+
pch {
compatible = "sandbox,pch";
};
diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c
index 5aad2ae..48b2ef2 100644
--- a/arch/x86/cpu/intel_common/cpu_from_spl.c
+++ b/arch/x86/cpu/intel_common/cpu_from_spl.c
@@ -24,7 +24,9 @@
int ret;
#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
- gd->arch.hob_list = handoff_get();
+ struct spl_handoff *ho = gd->spl_handoff;
+
+ gd->arch.hob_list = ho->arch.hob_list;
#endif
ret = x86_cpu_reinit_f();
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
index 4c4c833..75fa8f9 100644
--- a/arch/x86/lib/fsp2/fsp_dram.c
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -59,7 +59,7 @@
#endif
} else {
#if CONFIG_IS_ENABLED(HANDOFF)
- struct spl_handoff *ho = handoff_get();
+ struct spl_handoff *ho = gd->spl_handoff;
if (!ho) {
log_debug("No SPL handoff found\n");
@@ -82,7 +82,7 @@
return gd->ram_size;
#if CONFIG_IS_ENABLED(HANDOFF)
- struct spl_handoff *ho = handoff_get();
+ struct spl_handoff *ho = gd->spl_handoff;
log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index cf998096..584b545 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -16,8 +16,8 @@
select VIRTIO_BLK if VIRTIO_MMIO
select VIRTIO_NET if VIRTIO_MMIO
select DM_ETH if VIRTIO_NET
+ imply DM_RTC
imply RTC_PL031
- select DM_RTC if RTC_PL031
imply EFI_SET_TIME if DM_RTC
select LINUX_KERNEL_IMAGE_HEADER
select POSITION_INDEPENDENT
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index b85fd806..1adee9a 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -281,7 +281,7 @@
setup_iomux_enet();
#ifdef CONFIG_FEC_MXC
- bus = fec_get_miibus(base, -1);
+ bus = fec_get_miibus(NULL, base, -1);
if (!bus)
return -EINVAL;
/* scan phy 4,5,6,7 */
diff --git a/board/coreboot/coreboot/sysinfo.c b/board/coreboot/coreboot/sysinfo.c
index e0bdc7a..d6b1953 100644
--- a/board/coreboot/coreboot/sysinfo.c
+++ b/board/coreboot/coreboot/sysinfo.c
@@ -24,21 +24,21 @@
const char *str = NULL;
switch (id) {
- case SYSINFO_ID_BOARD_MODEL:
+ case SYSID_BOARD_MODEL:
if (priv->t1)
str = smbios_string(priv->system,
priv->t1->product_name);
break;
- case SYSINFO_ID_BOARD_MANUFACTURER:
+ case SYSID_BOARD_MANUFACTURER:
if (priv->t1)
str = smbios_string(priv->system,
priv->t1->manufacturer);
break;
- case SYSINFO_ID_PRIOR_STAGE_VERSION:
+ case SYSID_PRIOR_STAGE_VERSION:
if (priv->t0)
str = smbios_string(priv->bios, priv->t0->bios_ver);
break;
- case SYSINFO_ID_PRIOR_STAGE_DATE:
+ case SYSID_PRIOR_STAGE_DATE:
if (priv->t0)
str = smbios_string(priv->bios,
priv->t0->bios_release_date);
diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c
index b5f8390..9e35dc5 100644
--- a/board/data_modul/common/common.c
+++ b/board/data_modul/common/common.c
@@ -47,6 +47,9 @@
"dmo,ram-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
+ if (ret < 0)
+ return BIT(2) | BIT(0);
+
for (i = 0; i < ret; i++)
memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c
index 17aafd7..a9ef049 100644
--- a/board/data_modul/imx8mm_edm_sbc/spl.c
+++ b/board/data_modul/imx8mm_edm_sbc/spl.c
@@ -61,8 +61,10 @@
{
if (boot_dev_spl == MMC3_BOOT)
return BOOT_DEVICE_MMC2; /* eMMC */
- else
+ else if (boot_dev_spl == MMC2_BOOT)
return BOOT_DEVICE_MMC1; /* SD */
+ else
+ return BOOT_DEVICE_BOARD;
}
void board_boot_order(u32 *spl_boot_list)
@@ -76,7 +78,7 @@
else
spl_boot_list[1] = BOOT_DEVICE_MMC1; /* SD */
- spl_boot_list[2] = BOOT_DEVICE_UART; /* YModem */
+ spl_boot_list[2] = BOOT_DEVICE_BOARD; /* SDP */
spl_boot_list[3] = BOOT_DEVICE_NONE;
}
diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c
index 32c50b4..7101080 100644
--- a/board/dhelectronics/common/dh_common.c
+++ b/board/dhelectronics/common/dh_common.c
@@ -7,9 +7,27 @@
#include <dm.h>
#include <i2c_eeprom.h>
#include <net.h>
+#include <u-boot/crc.h>
#include "dh_common.h"
+static int on_dh_som_serial_number(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ env_set("SN", value);
+ return 0;
+}
+
+U_BOOT_ENV_CALLBACK(dh_som_serial_number, on_dh_som_serial_number);
+
+static int on_SN(const char *name, const char *value, enum env_op op, int flags)
+{
+ env_set("dh_som_serial_number", value);
+ return 0;
+}
+
+U_BOOT_ENV_CALLBACK(SN, on_SN);
+
bool dh_mac_is_in_env(const char *env)
{
unsigned char enetaddr[6];
@@ -30,6 +48,149 @@
return 0;
}
+int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias)
+{
+ struct eeprom_id_page *eip = (struct eeprom_id_page *)eeprom_buffer;
+ struct udevice *dev;
+ size_t payload_len;
+ int eeprom_size;
+ u16 crc16_calc;
+ u16 crc16_eip;
+ u8 crc8_calc;
+ ofnode node;
+ int ret;
+
+ node = ofnode_path(alias);
+
+ ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
+ if (ret)
+ return ret;
+
+ eeprom_size = i2c_eeprom_size(dev);
+ if (eeprom_size < 0) {
+ printf("%s: Error getting EEPROM ID page size! ret = %d\n", __func__, ret);
+ return eeprom_size;
+ }
+
+ if (eeprom_size == 0 || eeprom_size > DH_EEPROM_ID_PAGE_MAX_SIZE) {
+ eeprom_size = DH_EEPROM_ID_PAGE_MAX_SIZE;
+ printf("Get invalid EEPROM ID page size %d bytes! Try to read %d bytes.\n",
+ eeprom_size, DH_EEPROM_ID_PAGE_MAX_SIZE);
+ }
+
+ ret = i2c_eeprom_read(dev, 0x0, eeprom_buffer, eeprom_size);
+ if (ret) {
+ printf("%s: Error reading EEPROM ID page! ret = %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* Validate header ID */
+ if (eip->hdr.id[0] != 'D' || eip->hdr.id[1] != 'H' || eip->hdr.id[2] != 'E') {
+ printf("%s: Error validating header ID! (got %c%c%c (0x%02x 0x%02x 0x%02x) != expected DHE)\n",
+ __func__, isprint(eip->hdr.id[0]) ? eip->hdr.id[0] : '.',
+ isprint(eip->hdr.id[1]) ? eip->hdr.id[1] : '.',
+ isprint(eip->hdr.id[2]) ? eip->hdr.id[2] : '.',
+ eip->hdr.id[0], eip->hdr.id[1], eip->hdr.id[2]);
+ return -EINVAL;
+ }
+
+ /* Validate header checksum */
+ crc8_calc = crc8(0xff, eeprom_buffer, offsetof(struct eeprom_id_page, hdr.crc8_hdr));
+ if (eip->hdr.crc8_hdr != crc8_calc) {
+ printf("%s: Error validating header checksum! (got 0x%02x != calc 0x%02x)\n",
+ __func__, eip->hdr.crc8_hdr, crc8_calc);
+ return -EINVAL;
+ }
+
+ /*
+ * Validate header version
+ * The payload is defined by the version specified in the header.
+ * Currently only version 0x10 is defined, so take the length of
+ * the only defined payload as the payload length.
+ */
+ if (eip->hdr.version != DH_EEPROM_ID_PAGE_V1_0) {
+ printf("%s: Error validating version! (0x%02X is not supported)\n",
+ __func__, eip->hdr.version);
+ return -EINVAL;
+ }
+ payload_len = sizeof(eip->pl);
+
+ /* Validate payload checksum */
+ crc16_eip = (eip->hdr.crc16_pl[1] << 8) | eip->hdr.crc16_pl[0];
+ crc16_calc = crc16(0xffff, eeprom_buffer + sizeof(eip->hdr), payload_len);
+ if (crc16_eip != crc16_calc) {
+ printf("%s: Error validating data checksum! (got 0x%02x != calc 0x%02x)\n",
+ __func__, crc16_eip, crc16_calc);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len,
+ struct eeprom_id_page *eip)
+{
+ const char fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ?
+ DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR;
+ const u8 soc_coded = eip->pl.item_prefix & 0xf;
+ char soc_chr;
+
+ if (!eip)
+ return -EINVAL;
+
+ /* Copy requested data */
+ switch (request) {
+ case DH_MAC0:
+ if (!is_valid_ethaddr(eip->pl.mac0))
+ return -EINVAL;
+
+ if (data_len >= sizeof(eip->pl.mac0))
+ memcpy(data, eip->pl.mac0, sizeof(eip->pl.mac0));
+ else
+ return -EINVAL;
+ break;
+ case DH_MAC1:
+ if (!is_valid_ethaddr(eip->pl.mac1))
+ return -EINVAL;
+
+ if (data_len >= sizeof(eip->pl.mac1))
+ memcpy(data, eip->pl.mac1, sizeof(eip->pl.mac1));
+ else
+ return -EINVAL;
+ break;
+ case DH_ITEM_NUMBER:
+ if (data_len < 8) /* String length must be 7 characters + string termination */
+ return -EINVAL;
+
+ if (soc_coded == DH_ITEM_PREFIX_NXP)
+ soc_chr = DH_ITEM_PREFIX_NXP_CHR;
+ else if (soc_coded == DH_ITEM_PREFIX_ST)
+ soc_chr = DH_ITEM_PREFIX_ST_CHR;
+ else
+ return -EINVAL;
+
+ snprintf(data, data_len, "%c%c%05d", fin_chr, soc_chr,
+ (eip->pl.item_num[0] << 16) | (eip->pl.item_num[1] << 8) |
+ eip->pl.item_num[2]);
+ break;
+ case DH_SERIAL_NUMBER:
+ /*
+ * data_len must be greater than the size of eip->pl.serial,
+ * because there is a string termination needed.
+ */
+ if (data_len <= sizeof(eip->pl.serial))
+ return -EINVAL;
+
+ data[sizeof(eip->pl.serial)] = 0;
+ memcpy(data, eip->pl.serial, sizeof(eip->pl.serial));
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
{
struct udevice *dev;
@@ -62,7 +223,7 @@
return 0;
}
-__weak int dh_setup_mac_address(void)
+__weak int dh_setup_mac_address(struct eeprom_id_page *eip)
{
unsigned char enetaddr[6];
@@ -72,6 +233,9 @@
if (dh_get_mac_is_enabled("ethernet0"))
return 0;
+ if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip))
+ return eth_env_set_enetaddr("ethaddr", enetaddr);
+
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
return eth_env_set_enetaddr("ethaddr", enetaddr);
diff --git a/board/dhelectronics/common/dh_common.h b/board/dhelectronics/common/dh_common.h
index a2de5b1..c4693c6 100644
--- a/board/dhelectronics/common/dh_common.h
+++ b/board/dhelectronics/common/dh_common.h
@@ -3,6 +3,52 @@
* Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
*/
+#define DH_EEPROM_ID_PAGE_MAX_SIZE 64
+
+enum eip_request_values {
+ DH_MAC0,
+ DH_MAC1,
+ DH_ITEM_NUMBER,
+ DH_SERIAL_NUMBER,
+};
+
+/* DH item: Vendor coding */
+#define DH_ITEM_PREFIX_NXP 0x01
+#define DH_ITEM_PREFIX_NXP_CHR 'I'
+#define DH_ITEM_PREFIX_ST 0x02
+#define DH_ITEM_PREFIX_ST_CHR 'S'
+
+/*
+ * DH item: Finished state coding
+ * Bit = 0 means half finished
+ * Prefix is 'H'
+ * Bit = 1 means finished with a customer image flashed
+ * Prefix is 'F'
+ */
+#define DH_ITEM_PREFIX_FIN_BIT BIT(7)
+#define DH_ITEM_PREFIX_FIN_HALF_CHR 'H'
+#define DH_ITEM_PREFIX_FIN_FLASHED_CHR 'F'
+
+struct eeprom_id_page {
+ /* Header */
+ struct {
+ u8 id[3]; /* Identifier 'D', 'H', 'E' - 'D' is at index 0 */
+ u8 version; /* 0x10 -- Version 1.0 */
+ u8 crc16_pl[2]; /* Checksum payload, [1] is MSbyte */
+ u8 crc8_hdr; /* Checksum header */
+ } hdr;
+ /* Payload */
+ struct {
+ u8 mac0[6];
+ u8 mac1[6];
+ u8 item_prefix; /* H/F is coded in MSbits, Vendor coding starts at LSbits */
+ u8 item_num[3]; /* [2] is MSbyte */
+ u8 serial[9]; /* [8] is MSbyte */
+ } pl;
+};
+
+#define DH_EEPROM_ID_PAGE_V1_0 0x10
+
/*
* dh_mac_is_in_env - Check if MAC address is already set
*
@@ -29,8 +75,39 @@
int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias);
/*
+ * dh_read_eeprom_id_page() - Read EEPROM ID page content into given buffer
+ * @eeprom_buffer: Buffer for EEPROM ID page content
+ * @alias: Alias for EEPROM ID page device tree node
+ *
+ * Read the content of the EEPROM ID page into the given buffer (parameter
+ * eeprom_buffer). The EEPROM ID page device is selected via alias device
+ * tree name (parameter alias). The data of the EEPROM ID page is verified.
+ * An error is returned for reading failures and invalid data.
+ *
+ * Return: 0 if OK, other value on error
+ */
+int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias);
+
+/*
+ * dh_get_value_from_eeprom_buffer() - Get value from EEPROM buffer
+ * @eip_request_values: Requested value as enum
+ * @data: Buffer where value is to be stored
+ * @data_len: Length of the value buffer
+ * @eip: Pointer to EEPROM ID page struct from which the data is parsed
+ *
+ * Gets the value specified by the parameter eip_request_values from the EEPROM
+ * data struct (parameter eip). The data is written to the specified data
+ * buffer (parameter data). If the length of the data (parameter data_len) is
+ * not sufficient to copy the data into the buffer, an error is returned.
+ *
+ * Return: 0 if OK, other value on error
+ */
+int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len,
+ struct eeprom_id_page *eip);
+
+/*
* dh_setup_mac_address - Try to get MAC address from various locations and write it to env
*
* Return: 0 if OK, other value on error
*/
-int dh_setup_mac_address(void);
+int dh_setup_mac_address(struct eeprom_id_page *eip);
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index f2b14bf..234824b 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -84,7 +84,7 @@
}
#endif
-int dh_setup_mac_address(void)
+int dh_setup_mac_address(struct eeprom_id_page *eip)
{
unsigned char enetaddr[6];
@@ -171,7 +171,7 @@
u32 hw_code;
char buf[16];
- dh_setup_mac_address();
+ dh_setup_mac_address(NULL);
hw_code = board_get_hwcode();
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 78aae41..4af3cbe 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -40,7 +40,7 @@
return 0;
}
-static int dh_imx8_setup_ethaddr(void)
+static int dh_imx8_setup_ethaddr(struct eeprom_id_page *eip)
{
unsigned char enetaddr[6];
@@ -53,6 +53,9 @@
if (!dh_imx_get_mac_from_fuse(enetaddr))
goto out;
+ if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip))
+ goto out;
+
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
goto out;
@@ -62,7 +65,7 @@
return eth_env_set_enetaddr("ethaddr", enetaddr);
}
-static int dh_imx8_setup_eth1addr(void)
+static int dh_imx8_setup_eth1addr(struct eeprom_id_page *eip)
{
unsigned char enetaddr[6];
@@ -75,6 +78,9 @@
if (!dh_imx_get_mac_from_fuse(enetaddr))
goto increment_out;
+ if (!dh_get_value_from_eeprom_buffer(DH_MAC1, enetaddr, sizeof(enetaddr), eip))
+ goto out;
+
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom1"))
goto out;
@@ -95,21 +101,58 @@
return eth_env_set_enetaddr("eth1addr", enetaddr);
}
-int dh_setup_mac_address(void)
+int dh_setup_mac_address(struct eeprom_id_page *eip)
{
int ret;
- ret = dh_imx8_setup_ethaddr();
+ ret = dh_imx8_setup_ethaddr(eip);
if (ret)
printf("%s: Unable to setup ethaddr! ret = %d\n", __func__, ret);
- ret = dh_imx8_setup_eth1addr();
+ ret = dh_imx8_setup_eth1addr(eip);
if (ret)
printf("%s: Unable to setup eth1addr! ret = %d\n", __func__, ret);
return ret;
}
+void dh_add_item_number_and_serial_to_env(struct eeprom_id_page *eip)
+{
+ char *item_number_env;
+ char item_number[8]; /* String with 7 characters + string termination */
+ char *serial_env;
+ char serial[10]; /* String with 9 characters + string termination */
+ int ret;
+
+ ret = dh_get_value_from_eeprom_buffer(DH_ITEM_NUMBER, item_number, sizeof(item_number),
+ eip);
+ if (ret) {
+ printf("%s: Unable to get DHSOM item number from EEPROM ID page! ret = %d\n",
+ __func__, ret);
+ } else {
+ item_number_env = env_get("dh_som_item_number");
+ if (!item_number_env)
+ env_set("dh_som_item_number", item_number);
+ else if (strcmp(item_number_env, item_number))
+ printf("Warning: Environment dh_som_item_number differs from EEPROM ID page value (%s != %s)\n",
+ item_number_env, item_number);
+ }
+
+ ret = dh_get_value_from_eeprom_buffer(DH_SERIAL_NUMBER, serial, sizeof(serial),
+ eip);
+ if (ret) {
+ printf("%s: Unable to get DHSOM serial number from EEPROM ID page! ret = %d\n",
+ __func__, ret);
+ } else {
+ serial_env = env_get("dh_som_serial_number");
+ if (!serial_env)
+ env_set("dh_som_serial_number", serial);
+ else if (strcmp(serial_env, serial))
+ printf("Warning: Environment dh_som_serial_number differs from EEPROM ID page value (%s != %s)\n",
+ serial_env, serial);
+ }
+}
+
int board_init(void)
{
return 0;
@@ -117,7 +160,27 @@
int board_late_init(void)
{
- dh_setup_mac_address();
+ u8 eeprom_buffer[DH_EEPROM_ID_PAGE_MAX_SIZE] = { 0 };
+ struct eeprom_id_page *eip = (struct eeprom_id_page *)eeprom_buffer;
+ int ret;
+
+ ret = dh_read_eeprom_id_page(eeprom_buffer, "eeprom0wl");
+ if (ret) {
+ /*
+ * The EEPROM ID page is available on SoM rev. 200 and greater.
+ * For SoM rev. 100 the return value will be -ENODEV. Suppress
+ * the error message for that, because the absence cannot be
+ * treated as an error.
+ */
+ if (ret != -ENODEV)
+ printf("%s: Cannot read valid data from EEPROM ID page! ret = %d\n",
+ __func__, ret);
+ dh_setup_mac_address(NULL);
+ } else {
+ dh_setup_mac_address(eip);
+ dh_add_item_number_and_serial_to_env(eip);
+ }
+
return 0;
}
diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c
index 6095cb0..e0e18b4 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -48,7 +48,7 @@
};
struct efi_capsule_update_info update_info = {
- .num_images = ARRAY_SIZE(fw_images)
+ .num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
diff --git a/board/freescale/imx91_evk/Kconfig b/board/freescale/imx91_evk/Kconfig
new file mode 100644
index 0000000..caaa82b
--- /dev/null
+++ b/board/freescale/imx91_evk/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_IMX91_11X11_EVK
+
+config SYS_BOARD
+ default "imx91_evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx91_evk"
+
+config IMX91_EVK_LPDDR4
+ bool "Using LPDDR4 Timing and PMIC voltage"
+ default y
+ select IMX9_LPDDR4X
+ help
+ Select the LPDDR4 timing and 1.1V VDDQ
+
+endif
diff --git a/board/freescale/imx91_evk/MAINTAINERS b/board/freescale/imx91_evk/MAINTAINERS
new file mode 100644
index 0000000..f7d39bf
--- /dev/null
+++ b/board/freescale/imx91_evk/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX91 11x11 EVK BOARD
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/imx91_evk/
+F: include/configs/imx91_evk.h
+F: configs/imx91_11x11_evk_defconfig
+F: configs/imx91_11x11_evk_inline_ecc_defconfig
diff --git a/board/freescale/imx91_evk/Makefile b/board/freescale/imx91_evk/Makefile
new file mode 100644
index 0000000..a96228a
--- /dev/null
+++ b/board/freescale/imx91_evk/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx91_evk.o
+
+ifdef CONFIG_XPL_BUILD
+obj-y += spl.o
+ifdef CONFIG_IMX9_DRAM_INLINE_ECC
+obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts_ecc.o lpddr4_timing_1600mts_ecc.o
+else
+obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts.o lpddr4_timing_1600mts.o
+endif
+endif
diff --git a/board/freescale/imx91_evk/imx91_evk.c b/board/freescale/imx91_evk/imx91_evk.c
new file mode 100644
index 0000000..83bfca2
--- /dev/null
+++ b/board/freescale/imx91_evk/imx91_evk.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+
+ env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+ env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board_name", "11X11_EVK");
+ env_set("board_rev", "iMX93");
+#endif
+ return 0;
+}
diff --git a/board/freescale/imx91_evk/imx91_evk.env b/board/freescale/imx91_evk/imx91_evk.env
new file mode 100644
index 0000000..92486c6
--- /dev/null
+++ b/board/freescale/imx91_evk/imx91_evk.env
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+boot_targets=mmc0 mmc1
+boot_fit=no
+bootm_size=0x10000000
+cntr_addr=0x98000000
+cntr_file=os_cntr_signed.bin
+console=ttyLP0,115200 earlycon
+fdt_addr_r=0x83000000
+fdt_addr=0x83000000
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+image=Image
+mmcpart=1
+mmcroot=/dev/mmcblk1p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}
+prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
+auth_os=auth_cntr ${cntr_addr}
+boot_os=booti ${loadaddr} - ${fdt_addr_r}
+mmcboot=
+ echo Booting from mmc ...;
+ run mmcargs;
+ if test ${sec_boot} = yes; then
+ if run auth_os; then
+ run boot_os;
+ else
+ echo ERR: failed to authenticate;
+ fi;
+ else
+ if run loadfdt; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs
+ ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=
+ echo Booting from net ...;
+ run netargs;
+ if test ${ip_dyn} = yes; then
+ setenv get_cmd dhcp;
+ else
+ setenv get_cmd tftp;
+ fi;
+ if test ${sec_boot} = yes; then
+ ${get_cmd} ${cntr_addr} ${cntr_file};
+ if run auth_os; then
+ run boot_os;
+ else
+ echo ERR: failed to authenticate;
+ fi;
+ else
+ ${get_cmd} ${loadaddr} ${image};
+ if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+ run boot_os;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
diff --git a/board/freescale/imx91_evk/lpddr4_timing_1600mts.c b/board/freescale/imx91_evk/lpddr4_timing_1600mts.c
new file mode 100644
index 0000000..45e19da
--- /dev/null
+++ b/board/freescale/imx91_evk/lpddr4_timing_1600mts.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x44100001},
+ {0x4e300000, 0x8000ff},
+ {0x4e300008, 0x0},
+ {0x4e300080, 0x80000512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x02121100},
+ {0x4e300104, 0xF866000C},
+ {0x4e300108, 0xF2FA8088},
+ {0x4e30010C, 0x0061E1A0},
+ {0x4e300124, 0x0C340000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30700000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x00000011},
+ {0x4e300254, 0x00900090},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ {0x4e300300, 0x0F220F09},
+ {0x4e300304, 0x00901008},
+ {0x4e300308, 0x063C061A},
+ },
+ {
+ {0x01, 0xA4},
+ {0x02, 0x52},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00091000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x81820A48},
+ {0x4e30010C, 0x00310110},
+ {0x4e300124, 0x061A0000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30100000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000009},
+ {0x4e300254, 0x00440044},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 1,
+ },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x4},
+ {0x100a1, 0x5},
+ {0x100a2, 0x6},
+ {0x100a3, 0x7},
+ {0x100a4, 0x0},
+ {0x100a5, 0x1},
+ {0x100a6, 0x2},
+ {0x100a7, 0x3},
+ {0x110a0, 0x3},
+ {0x110a1, 0x2},
+ {0x110a2, 0x0},
+ {0x110a3, 0x1},
+ {0x110a4, 0x7},
+ {0x110a5, 0x6},
+ {0x110a6, 0x4},
+ {0x110a7, 0x5},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x200c5, 0xb},
+ {0x1200c5, 0x3},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x1},
+ {0x12002e, 0x1},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x2007d, 0x212},
+ {0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0x600},
+ {0x1014d, 0x600},
+ {0x1104d, 0x600},
+ {0x1114d, 0x600},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0xe3f},
+ {0x10149, 0xe3f},
+ {0x11049, 0xe3f},
+ {0x11149, 0xe3f},
+ {0x110049, 0xe3f},
+ {0x110149, 0xe3f},
+ {0x111049, 0xe3f},
+ {0x111149, 0xe3f},
+ {0x210049, 0xe3f},
+ {0x210149, 0xe3f},
+ {0x211049, 0xe3f},
+ {0x211149, 0xe3f},
+ {0x43, 0x7f},
+ {0x1043, 0x7f},
+ {0x2043, 0x7f},
+ {0x20018, 0x1},
+ {0x20075, 0x4},
+ {0x20050, 0x11},
+ {0x2009b, 0x2},
+ {0x20008, 0x190},
+ {0x120008, 0xc8},
+ {0x220008, 0x9c},
+ {0x20088, 0x9},
+ {0x200b2, 0x10c},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x1200b2, 0x10c},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x10c},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x600},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5655},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0x20021, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x41},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x2007d, 0x0},
+ {0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
+ {0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x2009b, 0x0},
+ {0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
+ {0x20088, 0x0},
+ {0x200b2, 0x0},
+ {0x10043, 0x0},
+ {0x10143, 0x0},
+ {0x11043, 0x0},
+ {0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
+ {0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
+ {0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
+ {0x90047, 0x0},
+ {0x90048, 0x0},
+ {0x90049, 0x0},
+ {0x9004a, 0x0},
+ {0x9004b, 0x0},
+ {0x9004c, 0x0},
+ {0x9004d, 0x0},
+ {0x9004e, 0x0},
+ {0x9004f, 0x0},
+ {0x90050, 0x0},
+ {0x90051, 0x0},
+ {0x90052, 0x0},
+ {0x90053, 0x0},
+ {0x90054, 0x0},
+ {0x90055, 0x0},
+ {0x90056, 0x0},
+ {0x90057, 0x0},
+ {0x90058, 0x0},
+ {0x90059, 0x0},
+ {0x9005a, 0x0},
+ {0x9005b, 0x0},
+ {0x9005c, 0x0},
+ {0x9005d, 0x0},
+ {0x9005e, 0x0},
+ {0x9005f, 0x0},
+ {0x90060, 0x0},
+ {0x90061, 0x0},
+ {0x90062, 0x0},
+ {0x90063, 0x0},
+ {0x90064, 0x0},
+ {0x90065, 0x0},
+ {0x90066, 0x0},
+ {0x90067, 0x0},
+ {0x90068, 0x0},
+ {0x90069, 0x0},
+ {0x9006a, 0x0},
+ {0x9006b, 0x0},
+ {0x9006c, 0x0},
+ {0x9006d, 0x0},
+ {0x9006e, 0x0},
+ {0x9006f, 0x0},
+ {0x90070, 0x0},
+ {0x90071, 0x0},
+ {0x90072, 0x0},
+ {0x90073, 0x0},
+ {0x90074, 0x0},
+ {0x90075, 0x0},
+ {0x90076, 0x0},
+ {0x90077, 0x0},
+ {0x90078, 0x0},
+ {0x90079, 0x0},
+ {0x9007a, 0x0},
+ {0x9007b, 0x0},
+ {0x9007c, 0x0},
+ {0x9007d, 0x0},
+ {0x9007e, 0x0},
+ {0x9007f, 0x0},
+ {0x90080, 0x0},
+ {0x90081, 0x0},
+ {0x90082, 0x0},
+ {0x90083, 0x0},
+ {0x90084, 0x0},
+ {0x90085, 0x0},
+ {0x90086, 0x0},
+ {0x90087, 0x0},
+ {0x90088, 0x0},
+ {0x90089, 0x0},
+ {0x9008a, 0x0},
+ {0x9008b, 0x0},
+ {0x9008c, 0x0},
+ {0x9008d, 0x0},
+ {0x9008e, 0x0},
+ {0x9008f, 0x0},
+ {0x90090, 0x0},
+ {0x90091, 0x0},
+ {0x90092, 0x0},
+ {0x90093, 0x0},
+ {0x90094, 0x0},
+ {0x90095, 0x0},
+ {0x90096, 0x0},
+ {0x90097, 0x0},
+ {0x90098, 0x0},
+ {0x90099, 0x0},
+ {0x9009a, 0x0},
+ {0x9009b, 0x0},
+ {0x9009c, 0x0},
+ {0x9009d, 0x0},
+ {0x9009e, 0x0},
+ {0x9009f, 0x0},
+ {0x900a0, 0x0},
+ {0x900a1, 0x0},
+ {0x900a2, 0x0},
+ {0x900a3, 0x0},
+ {0x900a4, 0x0},
+ {0x900a5, 0x0},
+ {0x900a6, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x0},
+ {0x900a9, 0x0},
+ {0x40000, 0x0},
+ {0x40020, 0x0},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x0},
+ {0x40021, 0x0},
+ {0x40041, 0x0},
+ {0x40061, 0x0},
+ {0x40002, 0x0},
+ {0x40022, 0x0},
+ {0x40042, 0x0},
+ {0x40062, 0x0},
+ {0x40003, 0x0},
+ {0x40023, 0x0},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x0},
+ {0x40024, 0x0},
+ {0x40044, 0x0},
+ {0x40064, 0x0},
+ {0x40005, 0x0},
+ {0x40025, 0x0},
+ {0x40045, 0x0},
+ {0x40065, 0x0},
+ {0x40006, 0x0},
+ {0x40026, 0x0},
+ {0x40046, 0x0},
+ {0x40066, 0x0},
+ {0x40007, 0x0},
+ {0x40027, 0x0},
+ {0x40047, 0x0},
+ {0x40067, 0x0},
+ {0x40008, 0x0},
+ {0x40028, 0x0},
+ {0x40048, 0x0},
+ {0x40068, 0x0},
+ {0x40009, 0x0},
+ {0x40029, 0x0},
+ {0x40049, 0x0},
+ {0x40069, 0x0},
+ {0x4000a, 0x0},
+ {0x4002a, 0x0},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x0},
+ {0x4002b, 0x0},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x0},
+ {0x4002c, 0x0},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0x0},
+ {0x4002d, 0x0},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x0},
+ {0x4002e, 0x0},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x0},
+ {0x4002f, 0x0},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x0},
+ {0x40030, 0x0},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x0},
+ {0x40031, 0x0},
+ {0x40051, 0x0},
+ {0x40071, 0x0},
+ {0x40012, 0x0},
+ {0x40032, 0x0},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x0},
+ {0x40033, 0x0},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x0},
+ {0x40034, 0x0},
+ {0x40054, 0x0},
+ {0x40074, 0x0},
+ {0x40015, 0x0},
+ {0x40035, 0x0},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x0},
+ {0x40036, 0x0},
+ {0x40056, 0x0},
+ {0x40076, 0x0},
+ {0x40017, 0x0},
+ {0x40037, 0x0},
+ {0x40057, 0x0},
+ {0x40077, 0x0},
+ {0x40018, 0x0},
+ {0x40038, 0x0},
+ {0x40058, 0x0},
+ {0x40078, 0x0},
+ {0x40019, 0x0},
+ {0x40039, 0x0},
+ {0x40059, 0x0},
+ {0x40079, 0x0},
+ {0x4001a, 0x0},
+ {0x4003a, 0x0},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x0},
+ {0x900ac, 0x0},
+ {0x900ad, 0x0},
+ {0x900ae, 0x0},
+ {0x900af, 0x0},
+ {0x900b0, 0x0},
+ {0x900b1, 0x0},
+ {0x900b2, 0x0},
+ {0x900b3, 0x0},
+ {0x900b4, 0x0},
+ {0x900b5, 0x0},
+ {0x900b6, 0x0},
+ {0x900b7, 0x0},
+ {0x900b8, 0x0},
+ {0x900b9, 0x0},
+ {0x900ba, 0x0},
+ {0x900bb, 0x0},
+ {0x900bc, 0x0},
+ {0x900bd, 0x0},
+ {0x900be, 0x0},
+ {0x900bf, 0x0},
+ {0x900c0, 0x0},
+ {0x900c1, 0x0},
+ {0x900c2, 0x0},
+ {0x900c3, 0x0},
+ {0x900c4, 0x0},
+ {0x900c5, 0x0},
+ {0x900c6, 0x0},
+ {0x900c7, 0x0},
+ {0x900c8, 0x0},
+ {0x900c9, 0x0},
+ {0x900ca, 0x0},
+ {0x900cb, 0x0},
+ {0x900cc, 0x0},
+ {0x900cd, 0x0},
+ {0x900ce, 0x0},
+ {0x900cf, 0x0},
+ {0x900d0, 0x0},
+ {0x900d1, 0x0},
+ {0x900d2, 0x0},
+ {0x900d3, 0x0},
+ {0x900d4, 0x0},
+ {0x900d5, 0x0},
+ {0x900d6, 0x0},
+ {0x900d7, 0x0},
+ {0x900d8, 0x0},
+ {0x900d9, 0x0},
+ {0x900da, 0x0},
+ {0x900db, 0x0},
+ {0x900dc, 0x0},
+ {0x900dd, 0x0},
+ {0x900de, 0x0},
+ {0x900df, 0x0},
+ {0x900e0, 0x0},
+ {0x900e1, 0x0},
+ {0x900e2, 0x0},
+ {0x900e3, 0x0},
+ {0x900e4, 0x0},
+ {0x900e5, 0x0},
+ {0x900e6, 0x0},
+ {0x900e7, 0x0},
+ {0x900e8, 0x0},
+ {0x900e9, 0x0},
+ {0x900ea, 0x0},
+ {0x900eb, 0x0},
+ {0x900ec, 0x0},
+ {0x900ed, 0x0},
+ {0x900ee, 0x0},
+ {0x900ef, 0x0},
+ {0x900f0, 0x0},
+ {0x900f1, 0x0},
+ {0x900f2, 0x0},
+ {0x900f3, 0x0},
+ {0x900f4, 0x0},
+ {0x900f5, 0x0},
+ {0x900f6, 0x0},
+ {0x900f7, 0x0},
+ {0x900f8, 0x0},
+ {0x900f9, 0x0},
+ {0x900fa, 0x0},
+ {0x900fb, 0x0},
+ {0x900fc, 0x0},
+ {0x900fd, 0x0},
+ {0x900fe, 0x0},
+ {0x900ff, 0x0},
+ {0x90100, 0x0},
+ {0x90101, 0x0},
+ {0x90102, 0x0},
+ {0x90103, 0x0},
+ {0x90104, 0x0},
+ {0x90105, 0x0},
+ {0x90106, 0x0},
+ {0x90107, 0x0},
+ {0x90108, 0x0},
+ {0x90109, 0x0},
+ {0x9010a, 0x0},
+ {0x9010b, 0x0},
+ {0x9010c, 0x0},
+ {0x9010d, 0x0},
+ {0x9010e, 0x0},
+ {0x9010f, 0x0},
+ {0x90110, 0x0},
+ {0x90111, 0x0},
+ {0x90112, 0x0},
+ {0x90113, 0x0},
+ {0x90114, 0x0},
+ {0x90115, 0x0},
+ {0x90116, 0x0},
+ {0x90117, 0x0},
+ {0x90118, 0x0},
+ {0x90119, 0x0},
+ {0x9011a, 0x0},
+ {0x9011b, 0x0},
+ {0x9011c, 0x0},
+ {0x9011d, 0x0},
+ {0x9011e, 0x0},
+ {0x9011f, 0x0},
+ {0x90120, 0x0},
+ {0x90121, 0x0},
+ {0x90122, 0x0},
+ {0x90123, 0x0},
+ {0x90124, 0x0},
+ {0x90125, 0x0},
+ {0x90126, 0x0},
+ {0x90127, 0x0},
+ {0x90128, 0x0},
+ {0x90129, 0x0},
+ {0x9012a, 0x0},
+ {0x9012b, 0x0},
+ {0x9012c, 0x0},
+ {0x9012d, 0x0},
+ {0x9012e, 0x0},
+ {0x9012f, 0x0},
+ {0x90130, 0x0},
+ {0x90131, 0x0},
+ {0x90132, 0x0},
+ {0x90133, 0x0},
+ {0x90134, 0x0},
+ {0x90135, 0x0},
+ {0x90136, 0x0},
+ {0x90137, 0x0},
+ {0x90138, 0x0},
+ {0x90139, 0x0},
+ {0x9013a, 0x0},
+ {0x9013b, 0x0},
+ {0x9013c, 0x0},
+ {0x9013d, 0x0},
+ {0x9013e, 0x0},
+ {0x9013f, 0x0},
+ {0x90140, 0x0},
+ {0x90141, 0x0},
+ {0x90142, 0x0},
+ {0x90143, 0x0},
+ {0x90144, 0x0},
+ {0x90145, 0x0},
+ {0x90146, 0x0},
+ {0x90147, 0x0},
+ {0x90148, 0x0},
+ {0x90149, 0x0},
+ {0x9014a, 0x0},
+ {0x9014b, 0x0},
+ {0x9014c, 0x0},
+ {0x9014d, 0x0},
+ {0x9014e, 0x0},
+ {0x9014f, 0x0},
+ {0x90150, 0x0},
+ {0x90151, 0x0},
+ {0x90152, 0x0},
+ {0x90153, 0x0},
+ {0x90154, 0x0},
+ {0x90155, 0x0},
+ {0x90156, 0x0},
+ {0x90157, 0x0},
+ {0x90158, 0x0},
+ {0x90159, 0x0},
+ {0x9015a, 0x0},
+ {0x9015b, 0x0},
+ {0x9015c, 0x0},
+ {0x9015d, 0x0},
+ {0x9015e, 0x0},
+ {0x9015f, 0x0},
+ {0x90160, 0x0},
+ {0x90161, 0x0},
+ {0x90162, 0x0},
+ {0x90163, 0x0},
+ {0x90164, 0x0},
+ {0x90165, 0x0},
+ {0x90166, 0x0},
+ {0x90167, 0x0},
+ {0x90168, 0x0},
+ {0x90169, 0x0},
+ {0x9016a, 0x0},
+ {0x9016b, 0x0},
+ {0x9016c, 0x0},
+ {0x9016d, 0x0},
+ {0x9016e, 0x0},
+ {0x9016f, 0x0},
+ {0x90170, 0x0},
+ {0x90171, 0x0},
+ {0x90172, 0x0},
+ {0x90173, 0x0},
+ {0x90174, 0x0},
+ {0x90175, 0x0},
+ {0x90176, 0x0},
+ {0x90177, 0x0},
+ {0x90178, 0x0},
+ {0x90179, 0x0},
+ {0x9017a, 0x0},
+ {0x9017b, 0x0},
+ {0x9017c, 0x0},
+ {0x9017d, 0x0},
+ {0x9017e, 0x0},
+ {0x9017f, 0x0},
+ {0x90180, 0x0},
+ {0x90181, 0x0},
+ {0x90182, 0x0},
+ {0x90183, 0x0},
+ {0x90184, 0x0},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x0},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x0},
+ {0x90017, 0x0},
+ {0x9001f, 0x0},
+ {0x90026, 0x0},
+ {0x400d0, 0x0},
+ {0x400d1, 0x0},
+ {0x400d2, 0x0},
+ {0x400d3, 0x0},
+ {0x400d4, 0x0},
+ {0x400d5, 0x0},
+ {0x400d6, 0x0},
+ {0x400d7, 0x0},
+ {0x200be, 0x0},
+ {0x2000b, 0x0},
+ {0x2000c, 0x0},
+ {0x2000d, 0x0},
+ {0x2000e, 0x0},
+ {0x12000b, 0x0},
+ {0x12000c, 0x0},
+ {0x12000d, 0x0},
+ {0x12000e, 0x0},
+ {0x22000b, 0x0},
+ {0x22000c, 0x0},
+ {0x22000d, 0x0},
+ {0x22000e, 0x0},
+ {0x9000c, 0x0},
+ {0x9000d, 0x0},
+ {0x9000e, 0x0},
+ {0x9000f, 0x0},
+ {0x90010, 0x0},
+ {0x90011, 0x0},
+ {0x90012, 0x0},
+ {0x90013, 0x0},
+ {0x20010, 0x0},
+ {0x20011, 0x0},
+ {0x120010, 0x0},
+ {0x120011, 0x0},
+ {0x40080, 0x0},
+ {0x40081, 0x0},
+ {0x40082, 0x0},
+ {0x40083, 0x0},
+ {0x40084, 0x0},
+ {0x40085, 0x0},
+ {0x140080, 0x0},
+ {0x140081, 0x0},
+ {0x140082, 0x0},
+ {0x140083, 0x0},
+ {0x140084, 0x0},
+ {0x140085, 0x0},
+ {0x240080, 0x0},
+ {0x240081, 0x0},
+ {0x240082, 0x0},
+ {0x240083, 0x0},
+ {0x240084, 0x0},
+ {0x240085, 0x0},
+ {0x400fd, 0x0},
+ {0x400f1, 0x0},
+ {0x10011, 0x0},
+ {0x10012, 0x0},
+ {0x10013, 0x0},
+ {0x10018, 0x0},
+ {0x10002, 0x0},
+ {0x100b2, 0x0},
+ {0x101b4, 0x0},
+ {0x102b4, 0x0},
+ {0x103b4, 0x0},
+ {0x104b4, 0x0},
+ {0x105b4, 0x0},
+ {0x106b4, 0x0},
+ {0x107b4, 0x0},
+ {0x108b4, 0x0},
+ {0x11011, 0x0},
+ {0x11012, 0x0},
+ {0x11013, 0x0},
+ {0x11018, 0x0},
+ {0x11002, 0x0},
+ {0x110b2, 0x0},
+ {0x111b4, 0x0},
+ {0x112b4, 0x0},
+ {0x113b4, 0x0},
+ {0x114b4, 0x0},
+ {0x115b4, 0x0},
+ {0x116b4, 0x0},
+ {0x117b4, 0x0},
+ {0x118b4, 0x0},
+ {0x20089, 0x0},
+ {0xc0080, 0x0},
+ {0x200cb, 0x0},
+ {0x10068, 0x0},
+ {0x10069, 0x0},
+ {0x10168, 0x0},
+ {0x10169, 0x0},
+ {0x10268, 0x0},
+ {0x10269, 0x0},
+ {0x10368, 0x0},
+ {0x10369, 0x0},
+ {0x10468, 0x0},
+ {0x10469, 0x0},
+ {0x10568, 0x0},
+ {0x10569, 0x0},
+ {0x10668, 0x0},
+ {0x10669, 0x0},
+ {0x10768, 0x0},
+ {0x10769, 0x0},
+ {0x10868, 0x0},
+ {0x10869, 0x0},
+ {0x100aa, 0x0},
+ {0x10062, 0x0},
+ {0x10001, 0x0},
+ {0x100a0, 0x0},
+ {0x100a1, 0x0},
+ {0x100a2, 0x0},
+ {0x100a3, 0x0},
+ {0x100a4, 0x0},
+ {0x100a5, 0x0},
+ {0x100a6, 0x0},
+ {0x100a7, 0x0},
+ {0x11068, 0x0},
+ {0x11069, 0x0},
+ {0x11168, 0x0},
+ {0x11169, 0x0},
+ {0x11268, 0x0},
+ {0x11269, 0x0},
+ {0x11368, 0x0},
+ {0x11369, 0x0},
+ {0x11468, 0x0},
+ {0x11469, 0x0},
+ {0x11568, 0x0},
+ {0x11569, 0x0},
+ {0x11668, 0x0},
+ {0x11669, 0x0},
+ {0x11768, 0x0},
+ {0x11769, 0x0},
+ {0x11868, 0x0},
+ {0x11869, 0x0},
+ {0x110aa, 0x0},
+ {0x11062, 0x0},
+ {0x11001, 0x0},
+ {0x110a0, 0x0},
+ {0x110a1, 0x0},
+ {0x110a2, 0x0},
+ {0x110a3, 0x0},
+ {0x110a4, 0x0},
+ {0x110a5, 0x0},
+ {0x110a6, 0x0},
+ {0x110a7, 0x0},
+ {0x80, 0x0},
+ {0x1080, 0x0},
+ {0x2080, 0x0},
+ {0x10020, 0x0},
+ {0x10080, 0x0},
+ {0x10081, 0x0},
+ {0x100d0, 0x0},
+ {0x100d1, 0x0},
+ {0x1008c, 0x0},
+ {0x1008d, 0x0},
+ {0x10180, 0x0},
+ {0x10181, 0x0},
+ {0x101d0, 0x0},
+ {0x101d1, 0x0},
+ {0x1018c, 0x0},
+ {0x1018d, 0x0},
+ {0x100c0, 0x0},
+ {0x100c1, 0x0},
+ {0x101c0, 0x0},
+ {0x101c1, 0x0},
+ {0x102c0, 0x0},
+ {0x102c1, 0x0},
+ {0x103c0, 0x0},
+ {0x103c1, 0x0},
+ {0x104c0, 0x0},
+ {0x104c1, 0x0},
+ {0x105c0, 0x0},
+ {0x105c1, 0x0},
+ {0x106c0, 0x0},
+ {0x106c1, 0x0},
+ {0x107c0, 0x0},
+ {0x107c1, 0x0},
+ {0x108c0, 0x0},
+ {0x108c1, 0x0},
+ {0x100ae, 0x0},
+ {0x100af, 0x0},
+ {0x11020, 0x0},
+ {0x11080, 0x0},
+ {0x11081, 0x0},
+ {0x110d0, 0x0},
+ {0x110d1, 0x0},
+ {0x1108c, 0x0},
+ {0x1108d, 0x0},
+ {0x11180, 0x0},
+ {0x11181, 0x0},
+ {0x111d0, 0x0},
+ {0x111d1, 0x0},
+ {0x1118c, 0x0},
+ {0x1118d, 0x0},
+ {0x110c0, 0x0},
+ {0x110c1, 0x0},
+ {0x111c0, 0x0},
+ {0x111c1, 0x0},
+ {0x112c0, 0x0},
+ {0x112c1, 0x0},
+ {0x113c0, 0x0},
+ {0x113c1, 0x0},
+ {0x114c0, 0x0},
+ {0x114c1, 0x0},
+ {0x115c0, 0x0},
+ {0x115c1, 0x0},
+ {0x116c0, 0x0},
+ {0x116c1, 0x0},
+ {0x117c0, 0x0},
+ {0x117c1, 0x0},
+ {0x118c0, 0x0},
+ {0x118c1, 0x0},
+ {0x110ae, 0x0},
+ {0x110af, 0x0},
+ {0x90201, 0x0},
+ {0x90202, 0x0},
+ {0x90203, 0x0},
+ {0x90205, 0x0},
+ {0x90206, 0x0},
+ {0x90207, 0x0},
+ {0x90208, 0x0},
+ {0x20020, 0x0},
+ {0x100080, 0x0},
+ {0x101080, 0x0},
+ {0x102080, 0x0},
+ {0x110020, 0x0},
+ {0x110080, 0x0},
+ {0x110081, 0x0},
+ {0x1100d0, 0x0},
+ {0x1100d1, 0x0},
+ {0x11008c, 0x0},
+ {0x11008d, 0x0},
+ {0x110180, 0x0},
+ {0x110181, 0x0},
+ {0x1101d0, 0x0},
+ {0x1101d1, 0x0},
+ {0x11018c, 0x0},
+ {0x11018d, 0x0},
+ {0x1100c0, 0x0},
+ {0x1100c1, 0x0},
+ {0x1101c0, 0x0},
+ {0x1101c1, 0x0},
+ {0x1102c0, 0x0},
+ {0x1102c1, 0x0},
+ {0x1103c0, 0x0},
+ {0x1103c1, 0x0},
+ {0x1104c0, 0x0},
+ {0x1104c1, 0x0},
+ {0x1105c0, 0x0},
+ {0x1105c1, 0x0},
+ {0x1106c0, 0x0},
+ {0x1106c1, 0x0},
+ {0x1107c0, 0x0},
+ {0x1107c1, 0x0},
+ {0x1108c0, 0x0},
+ {0x1108c1, 0x0},
+ {0x1100ae, 0x0},
+ {0x1100af, 0x0},
+ {0x111020, 0x0},
+ {0x111080, 0x0},
+ {0x111081, 0x0},
+ {0x1110d0, 0x0},
+ {0x1110d1, 0x0},
+ {0x11108c, 0x0},
+ {0x11108d, 0x0},
+ {0x111180, 0x0},
+ {0x111181, 0x0},
+ {0x1111d0, 0x0},
+ {0x1111d1, 0x0},
+ {0x11118c, 0x0},
+ {0x11118d, 0x0},
+ {0x1110c0, 0x0},
+ {0x1110c1, 0x0},
+ {0x1111c0, 0x0},
+ {0x1111c1, 0x0},
+ {0x1112c0, 0x0},
+ {0x1112c1, 0x0},
+ {0x1113c0, 0x0},
+ {0x1113c1, 0x0},
+ {0x1114c0, 0x0},
+ {0x1114c1, 0x0},
+ {0x1115c0, 0x0},
+ {0x1115c1, 0x0},
+ {0x1116c0, 0x0},
+ {0x1116c1, 0x0},
+ {0x1117c0, 0x0},
+ {0x1117c1, 0x0},
+ {0x1118c0, 0x0},
+ {0x1118c1, 0x0},
+ {0x1110ae, 0x0},
+ {0x1110af, 0x0},
+ {0x190201, 0x0},
+ {0x190202, 0x0},
+ {0x190203, 0x0},
+ {0x190205, 0x0},
+ {0x190206, 0x0},
+ {0x190207, 0x0},
+ {0x190208, 0x0},
+ {0x120020, 0x0},
+ {0x200080, 0x0},
+ {0x201080, 0x0},
+ {0x202080, 0x0},
+ {0x210020, 0x0},
+ {0x210080, 0x0},
+ {0x210081, 0x0},
+ {0x2100d0, 0x0},
+ {0x2100d1, 0x0},
+ {0x21008c, 0x0},
+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
+ {0x20077, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
+ {0x400c0, 0x0},
+ {0x10040, 0x0},
+ {0x10140, 0x0},
+ {0x10240, 0x0},
+ {0x10340, 0x0},
+ {0x10440, 0x0},
+ {0x10540, 0x0},
+ {0x10640, 0x0},
+ {0x10740, 0x0},
+ {0x10840, 0x0},
+ {0x11040, 0x0},
+ {0x11140, 0x0},
+ {0x11240, 0x0},
+ {0x11340, 0x0},
+ {0x11440, 0x0},
+ {0x11540, 0x0},
+ {0x11640, 0x0},
+ {0x11740, 0x0},
+ {0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x640},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x52a4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x52a4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xa400},
+ {0x54033, 0x3352},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xa400},
+ {0x54039, 0x3352},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x320},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3309},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3309},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4800},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4800},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3309},
+ {0x54034, 0x4600},
+ {0x54035, 0x11},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3309},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x11},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x640},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54010, 0x2080},
+ {0x54012, 0x110},
+ {0x54019, 0x52a4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x52a4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xa400},
+ {0x54033, 0x3352},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xa400},
+ {0x54039, 0x3352},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x30},
+ {0x90051, 0x65a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x45a},
+ {0x90055, 0x9},
+ {0x90056, 0x0},
+ {0x90057, 0x448},
+ {0x90058, 0x109},
+ {0x90059, 0x40},
+ {0x9005a, 0x633},
+ {0x9005b, 0x179},
+ {0x9005c, 0x1},
+ {0x9005d, 0x618},
+ {0x9005e, 0x109},
+ {0x9005f, 0x40c0},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x8},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x4040},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x0},
+ {0x90069, 0x4},
+ {0x9006a, 0x48},
+ {0x9006b, 0x40},
+ {0x9006c, 0x633},
+ {0x9006d, 0x149},
+ {0x9006e, 0x0},
+ {0x9006f, 0x658},
+ {0x90070, 0x109},
+ {0x90071, 0x10},
+ {0x90072, 0x4},
+ {0x90073, 0x18},
+ {0x90074, 0x0},
+ {0x90075, 0x4},
+ {0x90076, 0x78},
+ {0x90077, 0x549},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0xd49},
+ {0x9007b, 0x633},
+ {0x9007c, 0x159},
+ {0x9007d, 0x94a},
+ {0x9007e, 0x633},
+ {0x9007f, 0x159},
+ {0x90080, 0x441},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x42},
+ {0x90084, 0x633},
+ {0x90085, 0x149},
+ {0x90086, 0x1},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x0},
+ {0x9008a, 0xe0},
+ {0x9008b, 0x109},
+ {0x9008c, 0xa},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x9},
+ {0x90090, 0x3c0},
+ {0x90091, 0x149},
+ {0x90092, 0x9},
+ {0x90093, 0x3c0},
+ {0x90094, 0x159},
+ {0x90095, 0x18},
+ {0x90096, 0x10},
+ {0x90097, 0x109},
+ {0x90098, 0x0},
+ {0x90099, 0x3c0},
+ {0x9009a, 0x109},
+ {0x9009b, 0x18},
+ {0x9009c, 0x4},
+ {0x9009d, 0x48},
+ {0x9009e, 0x18},
+ {0x9009f, 0x4},
+ {0x900a0, 0x58},
+ {0x900a1, 0xb},
+ {0x900a2, 0x10},
+ {0x900a3, 0x109},
+ {0x900a4, 0x1},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x5},
+ {0x900a8, 0x7c0},
+ {0x900a9, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x790},
+ {0x900ac, 0x11a},
+ {0x900ad, 0x8},
+ {0x900ae, 0x7aa},
+ {0x900af, 0x2a},
+ {0x900b0, 0x10},
+ {0x900b1, 0x7b2},
+ {0x900b2, 0x2a},
+ {0x900b3, 0x0},
+ {0x900b4, 0x7c8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x10},
+ {0x900b7, 0x10},
+ {0x900b8, 0x109},
+ {0x900b9, 0x10},
+ {0x900ba, 0x2a8},
+ {0x900bb, 0x129},
+ {0x900bc, 0x8},
+ {0x900bd, 0x370},
+ {0x900be, 0x129},
+ {0x900bf, 0xa},
+ {0x900c0, 0x3c8},
+ {0x900c1, 0x1a9},
+ {0x900c2, 0xc},
+ {0x900c3, 0x408},
+ {0x900c4, 0x199},
+ {0x900c5, 0x14},
+ {0x900c6, 0x790},
+ {0x900c7, 0x11a},
+ {0x900c8, 0x8},
+ {0x900c9, 0x4},
+ {0x900ca, 0x18},
+ {0x900cb, 0xe},
+ {0x900cc, 0x408},
+ {0x900cd, 0x199},
+ {0x900ce, 0x8},
+ {0x900cf, 0x8568},
+ {0x900d0, 0x108},
+ {0x900d1, 0x18},
+ {0x900d2, 0x790},
+ {0x900d3, 0x16a},
+ {0x900d4, 0x8},
+ {0x900d5, 0x1d8},
+ {0x900d6, 0x169},
+ {0x900d7, 0x10},
+ {0x900d8, 0x8558},
+ {0x900d9, 0x168},
+ {0x900da, 0x1ff8},
+ {0x900db, 0x85a8},
+ {0x900dc, 0x1e8},
+ {0x900dd, 0x50},
+ {0x900de, 0x798},
+ {0x900df, 0x16a},
+ {0x900e0, 0x60},
+ {0x900e1, 0x7a0},
+ {0x900e2, 0x16a},
+ {0x900e3, 0x8},
+ {0x900e4, 0x8310},
+ {0x900e5, 0x168},
+ {0x900e6, 0x8},
+ {0x900e7, 0xa310},
+ {0x900e8, 0x168},
+ {0x900e9, 0xa},
+ {0x900ea, 0x408},
+ {0x900eb, 0x169},
+ {0x900ec, 0x6e},
+ {0x900ed, 0x0},
+ {0x900ee, 0x68},
+ {0x900ef, 0x0},
+ {0x900f0, 0x408},
+ {0x900f1, 0x169},
+ {0x900f2, 0x0},
+ {0x900f3, 0x8310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x0},
+ {0x900f6, 0xa310},
+ {0x900f7, 0x168},
+ {0x900f8, 0x1ff8},
+ {0x900f9, 0x85a8},
+ {0x900fa, 0x1e8},
+ {0x900fb, 0x68},
+ {0x900fc, 0x798},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x78},
+ {0x900ff, 0x7a0},
+ {0x90100, 0x16a},
+ {0x90101, 0x68},
+ {0x90102, 0x790},
+ {0x90103, 0x16a},
+ {0x90104, 0x8},
+ {0x90105, 0x8b10},
+ {0x90106, 0x168},
+ {0x90107, 0x8},
+ {0x90108, 0xab10},
+ {0x90109, 0x168},
+ {0x9010a, 0xa},
+ {0x9010b, 0x408},
+ {0x9010c, 0x169},
+ {0x9010d, 0x58},
+ {0x9010e, 0x0},
+ {0x9010f, 0x68},
+ {0x90110, 0x0},
+ {0x90111, 0x408},
+ {0x90112, 0x169},
+ {0x90113, 0x0},
+ {0x90114, 0x8b10},
+ {0x90115, 0x168},
+ {0x90116, 0x1},
+ {0x90117, 0xab10},
+ {0x90118, 0x168},
+ {0x90119, 0x0},
+ {0x9011a, 0x1d8},
+ {0x9011b, 0x169},
+ {0x9011c, 0x80},
+ {0x9011d, 0x790},
+ {0x9011e, 0x16a},
+ {0x9011f, 0x18},
+ {0x90120, 0x7aa},
+ {0x90121, 0x6a},
+ {0x90122, 0xa},
+ {0x90123, 0x0},
+ {0x90124, 0x1e9},
+ {0x90125, 0x8},
+ {0x90126, 0x8080},
+ {0x90127, 0x108},
+ {0x90128, 0xf},
+ {0x90129, 0x408},
+ {0x9012a, 0x169},
+ {0x9012b, 0xc},
+ {0x9012c, 0x0},
+ {0x9012d, 0x68},
+ {0x9012e, 0x9},
+ {0x9012f, 0x0},
+ {0x90130, 0x1a9},
+ {0x90131, 0x0},
+ {0x90132, 0x408},
+ {0x90133, 0x169},
+ {0x90134, 0x0},
+ {0x90135, 0x8080},
+ {0x90136, 0x108},
+ {0x90137, 0x8},
+ {0x90138, 0x7aa},
+ {0x90139, 0x6a},
+ {0x9013a, 0x0},
+ {0x9013b, 0x8568},
+ {0x9013c, 0x108},
+ {0x9013d, 0xb7},
+ {0x9013e, 0x790},
+ {0x9013f, 0x16a},
+ {0x90140, 0x1f},
+ {0x90141, 0x0},
+ {0x90142, 0x68},
+ {0x90143, 0x8},
+ {0x90144, 0x8558},
+ {0x90145, 0x168},
+ {0x90146, 0xf},
+ {0x90147, 0x408},
+ {0x90148, 0x169},
+ {0x90149, 0xd},
+ {0x9014a, 0x0},
+ {0x9014b, 0x68},
+ {0x9014c, 0x0},
+ {0x9014d, 0x408},
+ {0x9014e, 0x169},
+ {0x9014f, 0x0},
+ {0x90150, 0x8558},
+ {0x90151, 0x168},
+ {0x90152, 0x8},
+ {0x90153, 0x3c8},
+ {0x90154, 0x1a9},
+ {0x90155, 0x3},
+ {0x90156, 0x370},
+ {0x90157, 0x129},
+ {0x90158, 0x20},
+ {0x90159, 0x2aa},
+ {0x9015a, 0x9},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x104},
+ {0x90164, 0x8},
+ {0x90165, 0x448},
+ {0x90166, 0x109},
+ {0x90167, 0xf},
+ {0x90168, 0x7c0},
+ {0x90169, 0x109},
+ {0x9016a, 0x0},
+ {0x9016b, 0xe8},
+ {0x9016c, 0x109},
+ {0x9016d, 0x47},
+ {0x9016e, 0x630},
+ {0x9016f, 0x109},
+ {0x90170, 0x8},
+ {0x90171, 0x618},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0xe0},
+ {0x90175, 0x109},
+ {0x90176, 0x0},
+ {0x90177, 0x7c8},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0x8140},
+ {0x9017b, 0x10c},
+ {0x9017c, 0x0},
+ {0x9017d, 0x478},
+ {0x9017e, 0x109},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x0},
+ {0x90006, 0x8},
+ {0x90007, 0x7c8},
+ {0x90008, 0x109},
+ {0x90009, 0x0},
+ {0x9000a, 0x400},
+ {0x9000b, 0x106},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2b},
+ {0x90026, 0x69},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x200be, 0x3},
+ {0x2000b, 0x1c2},
+ {0x2000c, 0x64},
+ {0x2000d, 0x3e8},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xe1},
+ {0x12000c, 0x32},
+ {0x12000d, 0x1f4},
+ {0x12000e, 0x10},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x400f1, 0xe},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 800mts 1D */
+ .drate = 800,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 1600mts 2D */
+ .drate = 1600,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_1600mts = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 1600, 800, 625, },
+ .fsp_cfg = ddr_dram_fsp_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c b/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c
new file mode 100644
index 0000000..4594ab6
--- /dev/null
+++ b/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x44100001},
+ {0x4e300000, 0x8000ef},
+ {0x4e300008, 0x0},
+ {0x4e300080, 0x80000512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1012},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30d00},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0xc0000000},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x02121100},
+ {0x4e300104, 0xF866000C},
+ {0x4e300108, 0xF2FA8088},
+ {0x4e30010C, 0x0061E1A0},
+ {0x4e300124, 0x0C340000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30700000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x00000011},
+ {0x4e300254, 0x00900090},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ {0x4e300300, 0x0F220F09},
+ {0x4e300304, 0x00901008},
+ {0x4e300308, 0x063C061A},
+ },
+ {
+ {0x01, 0xA4},
+ {0x02, 0x52},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00091000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x81820A48},
+ {0x4e30010C, 0x00310110},
+ {0x4e300124, 0x061A0000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30100000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000009},
+ {0x4e300254, 0x00440044},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 1,
+ },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x4},
+ {0x100a1, 0x5},
+ {0x100a2, 0x6},
+ {0x100a3, 0x7},
+ {0x100a4, 0x0},
+ {0x100a5, 0x1},
+ {0x100a6, 0x2},
+ {0x100a7, 0x3},
+ {0x110a0, 0x3},
+ {0x110a1, 0x2},
+ {0x110a2, 0x0},
+ {0x110a3, 0x1},
+ {0x110a4, 0x7},
+ {0x110a5, 0x6},
+ {0x110a6, 0x4},
+ {0x110a7, 0x5},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x200c5, 0xb},
+ {0x1200c5, 0x3},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x1},
+ {0x12002e, 0x1},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x2007d, 0x212},
+ {0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0x600},
+ {0x1014d, 0x600},
+ {0x1104d, 0x600},
+ {0x1114d, 0x600},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0xe3f},
+ {0x10149, 0xe3f},
+ {0x11049, 0xe3f},
+ {0x11149, 0xe3f},
+ {0x110049, 0xe3f},
+ {0x110149, 0xe3f},
+ {0x111049, 0xe3f},
+ {0x111149, 0xe3f},
+ {0x210049, 0xe3f},
+ {0x210149, 0xe3f},
+ {0x211049, 0xe3f},
+ {0x211149, 0xe3f},
+ {0x43, 0x7f},
+ {0x1043, 0x7f},
+ {0x2043, 0x7f},
+ {0x20018, 0x1},
+ {0x20075, 0x4},
+ {0x20050, 0x11},
+ {0x2009b, 0x2},
+ {0x20008, 0x190},
+ {0x120008, 0xc8},
+ {0x220008, 0x9c},
+ {0x20088, 0x9},
+ {0x200b2, 0x10c},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x1200b2, 0x10c},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x10c},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x600},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5655},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0x20021, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x41},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x2007d, 0x0},
+ {0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
+ {0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x2009b, 0x0},
+ {0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
+ {0x20088, 0x0},
+ {0x200b2, 0x0},
+ {0x10043, 0x0},
+ {0x10143, 0x0},
+ {0x11043, 0x0},
+ {0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
+ {0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
+ {0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
+ {0x90047, 0x0},
+ {0x90048, 0x0},
+ {0x90049, 0x0},
+ {0x9004a, 0x0},
+ {0x9004b, 0x0},
+ {0x9004c, 0x0},
+ {0x9004d, 0x0},
+ {0x9004e, 0x0},
+ {0x9004f, 0x0},
+ {0x90050, 0x0},
+ {0x90051, 0x0},
+ {0x90052, 0x0},
+ {0x90053, 0x0},
+ {0x90054, 0x0},
+ {0x90055, 0x0},
+ {0x90056, 0x0},
+ {0x90057, 0x0},
+ {0x90058, 0x0},
+ {0x90059, 0x0},
+ {0x9005a, 0x0},
+ {0x9005b, 0x0},
+ {0x9005c, 0x0},
+ {0x9005d, 0x0},
+ {0x9005e, 0x0},
+ {0x9005f, 0x0},
+ {0x90060, 0x0},
+ {0x90061, 0x0},
+ {0x90062, 0x0},
+ {0x90063, 0x0},
+ {0x90064, 0x0},
+ {0x90065, 0x0},
+ {0x90066, 0x0},
+ {0x90067, 0x0},
+ {0x90068, 0x0},
+ {0x90069, 0x0},
+ {0x9006a, 0x0},
+ {0x9006b, 0x0},
+ {0x9006c, 0x0},
+ {0x9006d, 0x0},
+ {0x9006e, 0x0},
+ {0x9006f, 0x0},
+ {0x90070, 0x0},
+ {0x90071, 0x0},
+ {0x90072, 0x0},
+ {0x90073, 0x0},
+ {0x90074, 0x0},
+ {0x90075, 0x0},
+ {0x90076, 0x0},
+ {0x90077, 0x0},
+ {0x90078, 0x0},
+ {0x90079, 0x0},
+ {0x9007a, 0x0},
+ {0x9007b, 0x0},
+ {0x9007c, 0x0},
+ {0x9007d, 0x0},
+ {0x9007e, 0x0},
+ {0x9007f, 0x0},
+ {0x90080, 0x0},
+ {0x90081, 0x0},
+ {0x90082, 0x0},
+ {0x90083, 0x0},
+ {0x90084, 0x0},
+ {0x90085, 0x0},
+ {0x90086, 0x0},
+ {0x90087, 0x0},
+ {0x90088, 0x0},
+ {0x90089, 0x0},
+ {0x9008a, 0x0},
+ {0x9008b, 0x0},
+ {0x9008c, 0x0},
+ {0x9008d, 0x0},
+ {0x9008e, 0x0},
+ {0x9008f, 0x0},
+ {0x90090, 0x0},
+ {0x90091, 0x0},
+ {0x90092, 0x0},
+ {0x90093, 0x0},
+ {0x90094, 0x0},
+ {0x90095, 0x0},
+ {0x90096, 0x0},
+ {0x90097, 0x0},
+ {0x90098, 0x0},
+ {0x90099, 0x0},
+ {0x9009a, 0x0},
+ {0x9009b, 0x0},
+ {0x9009c, 0x0},
+ {0x9009d, 0x0},
+ {0x9009e, 0x0},
+ {0x9009f, 0x0},
+ {0x900a0, 0x0},
+ {0x900a1, 0x0},
+ {0x900a2, 0x0},
+ {0x900a3, 0x0},
+ {0x900a4, 0x0},
+ {0x900a5, 0x0},
+ {0x900a6, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x0},
+ {0x900a9, 0x0},
+ {0x40000, 0x0},
+ {0x40020, 0x0},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x0},
+ {0x40021, 0x0},
+ {0x40041, 0x0},
+ {0x40061, 0x0},
+ {0x40002, 0x0},
+ {0x40022, 0x0},
+ {0x40042, 0x0},
+ {0x40062, 0x0},
+ {0x40003, 0x0},
+ {0x40023, 0x0},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x0},
+ {0x40024, 0x0},
+ {0x40044, 0x0},
+ {0x40064, 0x0},
+ {0x40005, 0x0},
+ {0x40025, 0x0},
+ {0x40045, 0x0},
+ {0x40065, 0x0},
+ {0x40006, 0x0},
+ {0x40026, 0x0},
+ {0x40046, 0x0},
+ {0x40066, 0x0},
+ {0x40007, 0x0},
+ {0x40027, 0x0},
+ {0x40047, 0x0},
+ {0x40067, 0x0},
+ {0x40008, 0x0},
+ {0x40028, 0x0},
+ {0x40048, 0x0},
+ {0x40068, 0x0},
+ {0x40009, 0x0},
+ {0x40029, 0x0},
+ {0x40049, 0x0},
+ {0x40069, 0x0},
+ {0x4000a, 0x0},
+ {0x4002a, 0x0},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x0},
+ {0x4002b, 0x0},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x0},
+ {0x4002c, 0x0},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0x0},
+ {0x4002d, 0x0},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x0},
+ {0x4002e, 0x0},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x0},
+ {0x4002f, 0x0},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x0},
+ {0x40030, 0x0},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x0},
+ {0x40031, 0x0},
+ {0x40051, 0x0},
+ {0x40071, 0x0},
+ {0x40012, 0x0},
+ {0x40032, 0x0},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x0},
+ {0x40033, 0x0},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x0},
+ {0x40034, 0x0},
+ {0x40054, 0x0},
+ {0x40074, 0x0},
+ {0x40015, 0x0},
+ {0x40035, 0x0},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x0},
+ {0x40036, 0x0},
+ {0x40056, 0x0},
+ {0x40076, 0x0},
+ {0x40017, 0x0},
+ {0x40037, 0x0},
+ {0x40057, 0x0},
+ {0x40077, 0x0},
+ {0x40018, 0x0},
+ {0x40038, 0x0},
+ {0x40058, 0x0},
+ {0x40078, 0x0},
+ {0x40019, 0x0},
+ {0x40039, 0x0},
+ {0x40059, 0x0},
+ {0x40079, 0x0},
+ {0x4001a, 0x0},
+ {0x4003a, 0x0},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x0},
+ {0x900ac, 0x0},
+ {0x900ad, 0x0},
+ {0x900ae, 0x0},
+ {0x900af, 0x0},
+ {0x900b0, 0x0},
+ {0x900b1, 0x0},
+ {0x900b2, 0x0},
+ {0x900b3, 0x0},
+ {0x900b4, 0x0},
+ {0x900b5, 0x0},
+ {0x900b6, 0x0},
+ {0x900b7, 0x0},
+ {0x900b8, 0x0},
+ {0x900b9, 0x0},
+ {0x900ba, 0x0},
+ {0x900bb, 0x0},
+ {0x900bc, 0x0},
+ {0x900bd, 0x0},
+ {0x900be, 0x0},
+ {0x900bf, 0x0},
+ {0x900c0, 0x0},
+ {0x900c1, 0x0},
+ {0x900c2, 0x0},
+ {0x900c3, 0x0},
+ {0x900c4, 0x0},
+ {0x900c5, 0x0},
+ {0x900c6, 0x0},
+ {0x900c7, 0x0},
+ {0x900c8, 0x0},
+ {0x900c9, 0x0},
+ {0x900ca, 0x0},
+ {0x900cb, 0x0},
+ {0x900cc, 0x0},
+ {0x900cd, 0x0},
+ {0x900ce, 0x0},
+ {0x900cf, 0x0},
+ {0x900d0, 0x0},
+ {0x900d1, 0x0},
+ {0x900d2, 0x0},
+ {0x900d3, 0x0},
+ {0x900d4, 0x0},
+ {0x900d5, 0x0},
+ {0x900d6, 0x0},
+ {0x900d7, 0x0},
+ {0x900d8, 0x0},
+ {0x900d9, 0x0},
+ {0x900da, 0x0},
+ {0x900db, 0x0},
+ {0x900dc, 0x0},
+ {0x900dd, 0x0},
+ {0x900de, 0x0},
+ {0x900df, 0x0},
+ {0x900e0, 0x0},
+ {0x900e1, 0x0},
+ {0x900e2, 0x0},
+ {0x900e3, 0x0},
+ {0x900e4, 0x0},
+ {0x900e5, 0x0},
+ {0x900e6, 0x0},
+ {0x900e7, 0x0},
+ {0x900e8, 0x0},
+ {0x900e9, 0x0},
+ {0x900ea, 0x0},
+ {0x900eb, 0x0},
+ {0x900ec, 0x0},
+ {0x900ed, 0x0},
+ {0x900ee, 0x0},
+ {0x900ef, 0x0},
+ {0x900f0, 0x0},
+ {0x900f1, 0x0},
+ {0x900f2, 0x0},
+ {0x900f3, 0x0},
+ {0x900f4, 0x0},
+ {0x900f5, 0x0},
+ {0x900f6, 0x0},
+ {0x900f7, 0x0},
+ {0x900f8, 0x0},
+ {0x900f9, 0x0},
+ {0x900fa, 0x0},
+ {0x900fb, 0x0},
+ {0x900fc, 0x0},
+ {0x900fd, 0x0},
+ {0x900fe, 0x0},
+ {0x900ff, 0x0},
+ {0x90100, 0x0},
+ {0x90101, 0x0},
+ {0x90102, 0x0},
+ {0x90103, 0x0},
+ {0x90104, 0x0},
+ {0x90105, 0x0},
+ {0x90106, 0x0},
+ {0x90107, 0x0},
+ {0x90108, 0x0},
+ {0x90109, 0x0},
+ {0x9010a, 0x0},
+ {0x9010b, 0x0},
+ {0x9010c, 0x0},
+ {0x9010d, 0x0},
+ {0x9010e, 0x0},
+ {0x9010f, 0x0},
+ {0x90110, 0x0},
+ {0x90111, 0x0},
+ {0x90112, 0x0},
+ {0x90113, 0x0},
+ {0x90114, 0x0},
+ {0x90115, 0x0},
+ {0x90116, 0x0},
+ {0x90117, 0x0},
+ {0x90118, 0x0},
+ {0x90119, 0x0},
+ {0x9011a, 0x0},
+ {0x9011b, 0x0},
+ {0x9011c, 0x0},
+ {0x9011d, 0x0},
+ {0x9011e, 0x0},
+ {0x9011f, 0x0},
+ {0x90120, 0x0},
+ {0x90121, 0x0},
+ {0x90122, 0x0},
+ {0x90123, 0x0},
+ {0x90124, 0x0},
+ {0x90125, 0x0},
+ {0x90126, 0x0},
+ {0x90127, 0x0},
+ {0x90128, 0x0},
+ {0x90129, 0x0},
+ {0x9012a, 0x0},
+ {0x9012b, 0x0},
+ {0x9012c, 0x0},
+ {0x9012d, 0x0},
+ {0x9012e, 0x0},
+ {0x9012f, 0x0},
+ {0x90130, 0x0},
+ {0x90131, 0x0},
+ {0x90132, 0x0},
+ {0x90133, 0x0},
+ {0x90134, 0x0},
+ {0x90135, 0x0},
+ {0x90136, 0x0},
+ {0x90137, 0x0},
+ {0x90138, 0x0},
+ {0x90139, 0x0},
+ {0x9013a, 0x0},
+ {0x9013b, 0x0},
+ {0x9013c, 0x0},
+ {0x9013d, 0x0},
+ {0x9013e, 0x0},
+ {0x9013f, 0x0},
+ {0x90140, 0x0},
+ {0x90141, 0x0},
+ {0x90142, 0x0},
+ {0x90143, 0x0},
+ {0x90144, 0x0},
+ {0x90145, 0x0},
+ {0x90146, 0x0},
+ {0x90147, 0x0},
+ {0x90148, 0x0},
+ {0x90149, 0x0},
+ {0x9014a, 0x0},
+ {0x9014b, 0x0},
+ {0x9014c, 0x0},
+ {0x9014d, 0x0},
+ {0x9014e, 0x0},
+ {0x9014f, 0x0},
+ {0x90150, 0x0},
+ {0x90151, 0x0},
+ {0x90152, 0x0},
+ {0x90153, 0x0},
+ {0x90154, 0x0},
+ {0x90155, 0x0},
+ {0x90156, 0x0},
+ {0x90157, 0x0},
+ {0x90158, 0x0},
+ {0x90159, 0x0},
+ {0x9015a, 0x0},
+ {0x9015b, 0x0},
+ {0x9015c, 0x0},
+ {0x9015d, 0x0},
+ {0x9015e, 0x0},
+ {0x9015f, 0x0},
+ {0x90160, 0x0},
+ {0x90161, 0x0},
+ {0x90162, 0x0},
+ {0x90163, 0x0},
+ {0x90164, 0x0},
+ {0x90165, 0x0},
+ {0x90166, 0x0},
+ {0x90167, 0x0},
+ {0x90168, 0x0},
+ {0x90169, 0x0},
+ {0x9016a, 0x0},
+ {0x9016b, 0x0},
+ {0x9016c, 0x0},
+ {0x9016d, 0x0},
+ {0x9016e, 0x0},
+ {0x9016f, 0x0},
+ {0x90170, 0x0},
+ {0x90171, 0x0},
+ {0x90172, 0x0},
+ {0x90173, 0x0},
+ {0x90174, 0x0},
+ {0x90175, 0x0},
+ {0x90176, 0x0},
+ {0x90177, 0x0},
+ {0x90178, 0x0},
+ {0x90179, 0x0},
+ {0x9017a, 0x0},
+ {0x9017b, 0x0},
+ {0x9017c, 0x0},
+ {0x9017d, 0x0},
+ {0x9017e, 0x0},
+ {0x9017f, 0x0},
+ {0x90180, 0x0},
+ {0x90181, 0x0},
+ {0x90182, 0x0},
+ {0x90183, 0x0},
+ {0x90184, 0x0},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x0},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x0},
+ {0x90017, 0x0},
+ {0x9001f, 0x0},
+ {0x90026, 0x0},
+ {0x400d0, 0x0},
+ {0x400d1, 0x0},
+ {0x400d2, 0x0},
+ {0x400d3, 0x0},
+ {0x400d4, 0x0},
+ {0x400d5, 0x0},
+ {0x400d6, 0x0},
+ {0x400d7, 0x0},
+ {0x200be, 0x0},
+ {0x2000b, 0x0},
+ {0x2000c, 0x0},
+ {0x2000d, 0x0},
+ {0x2000e, 0x0},
+ {0x12000b, 0x0},
+ {0x12000c, 0x0},
+ {0x12000d, 0x0},
+ {0x12000e, 0x0},
+ {0x22000b, 0x0},
+ {0x22000c, 0x0},
+ {0x22000d, 0x0},
+ {0x22000e, 0x0},
+ {0x9000c, 0x0},
+ {0x9000d, 0x0},
+ {0x9000e, 0x0},
+ {0x9000f, 0x0},
+ {0x90010, 0x0},
+ {0x90011, 0x0},
+ {0x90012, 0x0},
+ {0x90013, 0x0},
+ {0x20010, 0x0},
+ {0x20011, 0x0},
+ {0x120010, 0x0},
+ {0x120011, 0x0},
+ {0x40080, 0x0},
+ {0x40081, 0x0},
+ {0x40082, 0x0},
+ {0x40083, 0x0},
+ {0x40084, 0x0},
+ {0x40085, 0x0},
+ {0x140080, 0x0},
+ {0x140081, 0x0},
+ {0x140082, 0x0},
+ {0x140083, 0x0},
+ {0x140084, 0x0},
+ {0x140085, 0x0},
+ {0x240080, 0x0},
+ {0x240081, 0x0},
+ {0x240082, 0x0},
+ {0x240083, 0x0},
+ {0x240084, 0x0},
+ {0x240085, 0x0},
+ {0x400fd, 0x0},
+ {0x400f1, 0x0},
+ {0x10011, 0x0},
+ {0x10012, 0x0},
+ {0x10013, 0x0},
+ {0x10018, 0x0},
+ {0x10002, 0x0},
+ {0x100b2, 0x0},
+ {0x101b4, 0x0},
+ {0x102b4, 0x0},
+ {0x103b4, 0x0},
+ {0x104b4, 0x0},
+ {0x105b4, 0x0},
+ {0x106b4, 0x0},
+ {0x107b4, 0x0},
+ {0x108b4, 0x0},
+ {0x11011, 0x0},
+ {0x11012, 0x0},
+ {0x11013, 0x0},
+ {0x11018, 0x0},
+ {0x11002, 0x0},
+ {0x110b2, 0x0},
+ {0x111b4, 0x0},
+ {0x112b4, 0x0},
+ {0x113b4, 0x0},
+ {0x114b4, 0x0},
+ {0x115b4, 0x0},
+ {0x116b4, 0x0},
+ {0x117b4, 0x0},
+ {0x118b4, 0x0},
+ {0x20089, 0x0},
+ {0xc0080, 0x0},
+ {0x200cb, 0x0},
+ {0x10068, 0x0},
+ {0x10069, 0x0},
+ {0x10168, 0x0},
+ {0x10169, 0x0},
+ {0x10268, 0x0},
+ {0x10269, 0x0},
+ {0x10368, 0x0},
+ {0x10369, 0x0},
+ {0x10468, 0x0},
+ {0x10469, 0x0},
+ {0x10568, 0x0},
+ {0x10569, 0x0},
+ {0x10668, 0x0},
+ {0x10669, 0x0},
+ {0x10768, 0x0},
+ {0x10769, 0x0},
+ {0x10868, 0x0},
+ {0x10869, 0x0},
+ {0x100aa, 0x0},
+ {0x10062, 0x0},
+ {0x10001, 0x0},
+ {0x100a0, 0x0},
+ {0x100a1, 0x0},
+ {0x100a2, 0x0},
+ {0x100a3, 0x0},
+ {0x100a4, 0x0},
+ {0x100a5, 0x0},
+ {0x100a6, 0x0},
+ {0x100a7, 0x0},
+ {0x11068, 0x0},
+ {0x11069, 0x0},
+ {0x11168, 0x0},
+ {0x11169, 0x0},
+ {0x11268, 0x0},
+ {0x11269, 0x0},
+ {0x11368, 0x0},
+ {0x11369, 0x0},
+ {0x11468, 0x0},
+ {0x11469, 0x0},
+ {0x11568, 0x0},
+ {0x11569, 0x0},
+ {0x11668, 0x0},
+ {0x11669, 0x0},
+ {0x11768, 0x0},
+ {0x11769, 0x0},
+ {0x11868, 0x0},
+ {0x11869, 0x0},
+ {0x110aa, 0x0},
+ {0x11062, 0x0},
+ {0x11001, 0x0},
+ {0x110a0, 0x0},
+ {0x110a1, 0x0},
+ {0x110a2, 0x0},
+ {0x110a3, 0x0},
+ {0x110a4, 0x0},
+ {0x110a5, 0x0},
+ {0x110a6, 0x0},
+ {0x110a7, 0x0},
+ {0x80, 0x0},
+ {0x1080, 0x0},
+ {0x2080, 0x0},
+ {0x10020, 0x0},
+ {0x10080, 0x0},
+ {0x10081, 0x0},
+ {0x100d0, 0x0},
+ {0x100d1, 0x0},
+ {0x1008c, 0x0},
+ {0x1008d, 0x0},
+ {0x10180, 0x0},
+ {0x10181, 0x0},
+ {0x101d0, 0x0},
+ {0x101d1, 0x0},
+ {0x1018c, 0x0},
+ {0x1018d, 0x0},
+ {0x100c0, 0x0},
+ {0x100c1, 0x0},
+ {0x101c0, 0x0},
+ {0x101c1, 0x0},
+ {0x102c0, 0x0},
+ {0x102c1, 0x0},
+ {0x103c0, 0x0},
+ {0x103c1, 0x0},
+ {0x104c0, 0x0},
+ {0x104c1, 0x0},
+ {0x105c0, 0x0},
+ {0x105c1, 0x0},
+ {0x106c0, 0x0},
+ {0x106c1, 0x0},
+ {0x107c0, 0x0},
+ {0x107c1, 0x0},
+ {0x108c0, 0x0},
+ {0x108c1, 0x0},
+ {0x100ae, 0x0},
+ {0x100af, 0x0},
+ {0x11020, 0x0},
+ {0x11080, 0x0},
+ {0x11081, 0x0},
+ {0x110d0, 0x0},
+ {0x110d1, 0x0},
+ {0x1108c, 0x0},
+ {0x1108d, 0x0},
+ {0x11180, 0x0},
+ {0x11181, 0x0},
+ {0x111d0, 0x0},
+ {0x111d1, 0x0},
+ {0x1118c, 0x0},
+ {0x1118d, 0x0},
+ {0x110c0, 0x0},
+ {0x110c1, 0x0},
+ {0x111c0, 0x0},
+ {0x111c1, 0x0},
+ {0x112c0, 0x0},
+ {0x112c1, 0x0},
+ {0x113c0, 0x0},
+ {0x113c1, 0x0},
+ {0x114c0, 0x0},
+ {0x114c1, 0x0},
+ {0x115c0, 0x0},
+ {0x115c1, 0x0},
+ {0x116c0, 0x0},
+ {0x116c1, 0x0},
+ {0x117c0, 0x0},
+ {0x117c1, 0x0},
+ {0x118c0, 0x0},
+ {0x118c1, 0x0},
+ {0x110ae, 0x0},
+ {0x110af, 0x0},
+ {0x90201, 0x0},
+ {0x90202, 0x0},
+ {0x90203, 0x0},
+ {0x90205, 0x0},
+ {0x90206, 0x0},
+ {0x90207, 0x0},
+ {0x90208, 0x0},
+ {0x20020, 0x0},
+ {0x100080, 0x0},
+ {0x101080, 0x0},
+ {0x102080, 0x0},
+ {0x110020, 0x0},
+ {0x110080, 0x0},
+ {0x110081, 0x0},
+ {0x1100d0, 0x0},
+ {0x1100d1, 0x0},
+ {0x11008c, 0x0},
+ {0x11008d, 0x0},
+ {0x110180, 0x0},
+ {0x110181, 0x0},
+ {0x1101d0, 0x0},
+ {0x1101d1, 0x0},
+ {0x11018c, 0x0},
+ {0x11018d, 0x0},
+ {0x1100c0, 0x0},
+ {0x1100c1, 0x0},
+ {0x1101c0, 0x0},
+ {0x1101c1, 0x0},
+ {0x1102c0, 0x0},
+ {0x1102c1, 0x0},
+ {0x1103c0, 0x0},
+ {0x1103c1, 0x0},
+ {0x1104c0, 0x0},
+ {0x1104c1, 0x0},
+ {0x1105c0, 0x0},
+ {0x1105c1, 0x0},
+ {0x1106c0, 0x0},
+ {0x1106c1, 0x0},
+ {0x1107c0, 0x0},
+ {0x1107c1, 0x0},
+ {0x1108c0, 0x0},
+ {0x1108c1, 0x0},
+ {0x1100ae, 0x0},
+ {0x1100af, 0x0},
+ {0x111020, 0x0},
+ {0x111080, 0x0},
+ {0x111081, 0x0},
+ {0x1110d0, 0x0},
+ {0x1110d1, 0x0},
+ {0x11108c, 0x0},
+ {0x11108d, 0x0},
+ {0x111180, 0x0},
+ {0x111181, 0x0},
+ {0x1111d0, 0x0},
+ {0x1111d1, 0x0},
+ {0x11118c, 0x0},
+ {0x11118d, 0x0},
+ {0x1110c0, 0x0},
+ {0x1110c1, 0x0},
+ {0x1111c0, 0x0},
+ {0x1111c1, 0x0},
+ {0x1112c0, 0x0},
+ {0x1112c1, 0x0},
+ {0x1113c0, 0x0},
+ {0x1113c1, 0x0},
+ {0x1114c0, 0x0},
+ {0x1114c1, 0x0},
+ {0x1115c0, 0x0},
+ {0x1115c1, 0x0},
+ {0x1116c0, 0x0},
+ {0x1116c1, 0x0},
+ {0x1117c0, 0x0},
+ {0x1117c1, 0x0},
+ {0x1118c0, 0x0},
+ {0x1118c1, 0x0},
+ {0x1110ae, 0x0},
+ {0x1110af, 0x0},
+ {0x190201, 0x0},
+ {0x190202, 0x0},
+ {0x190203, 0x0},
+ {0x190205, 0x0},
+ {0x190206, 0x0},
+ {0x190207, 0x0},
+ {0x190208, 0x0},
+ {0x120020, 0x0},
+ {0x200080, 0x0},
+ {0x201080, 0x0},
+ {0x202080, 0x0},
+ {0x210020, 0x0},
+ {0x210080, 0x0},
+ {0x210081, 0x0},
+ {0x2100d0, 0x0},
+ {0x2100d1, 0x0},
+ {0x21008c, 0x0},
+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
+ {0x20077, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
+ {0x400c0, 0x0},
+ {0x10040, 0x0},
+ {0x10140, 0x0},
+ {0x10240, 0x0},
+ {0x10340, 0x0},
+ {0x10440, 0x0},
+ {0x10540, 0x0},
+ {0x10640, 0x0},
+ {0x10740, 0x0},
+ {0x10840, 0x0},
+ {0x11040, 0x0},
+ {0x11140, 0x0},
+ {0x11240, 0x0},
+ {0x11340, 0x0},
+ {0x11440, 0x0},
+ {0x11540, 0x0},
+ {0x11640, 0x0},
+ {0x11740, 0x0},
+ {0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x640},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x52a4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x52a4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xa400},
+ {0x54033, 0x3352},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xa400},
+ {0x54039, 0x3352},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x320},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3309},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3309},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4800},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4800},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3309},
+ {0x54034, 0x4600},
+ {0x54035, 0x11},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3309},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x11},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x640},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54010, 0x2080},
+ {0x54012, 0x110},
+ {0x54019, 0x52a4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x52a4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xa400},
+ {0x54033, 0x3352},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xa400},
+ {0x54039, 0x3352},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x30},
+ {0x90051, 0x65a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x45a},
+ {0x90055, 0x9},
+ {0x90056, 0x0},
+ {0x90057, 0x448},
+ {0x90058, 0x109},
+ {0x90059, 0x40},
+ {0x9005a, 0x633},
+ {0x9005b, 0x179},
+ {0x9005c, 0x1},
+ {0x9005d, 0x618},
+ {0x9005e, 0x109},
+ {0x9005f, 0x40c0},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x8},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x4040},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x0},
+ {0x90069, 0x4},
+ {0x9006a, 0x48},
+ {0x9006b, 0x40},
+ {0x9006c, 0x633},
+ {0x9006d, 0x149},
+ {0x9006e, 0x0},
+ {0x9006f, 0x658},
+ {0x90070, 0x109},
+ {0x90071, 0x10},
+ {0x90072, 0x4},
+ {0x90073, 0x18},
+ {0x90074, 0x0},
+ {0x90075, 0x4},
+ {0x90076, 0x78},
+ {0x90077, 0x549},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0xd49},
+ {0x9007b, 0x633},
+ {0x9007c, 0x159},
+ {0x9007d, 0x94a},
+ {0x9007e, 0x633},
+ {0x9007f, 0x159},
+ {0x90080, 0x441},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x42},
+ {0x90084, 0x633},
+ {0x90085, 0x149},
+ {0x90086, 0x1},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x0},
+ {0x9008a, 0xe0},
+ {0x9008b, 0x109},
+ {0x9008c, 0xa},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x9},
+ {0x90090, 0x3c0},
+ {0x90091, 0x149},
+ {0x90092, 0x9},
+ {0x90093, 0x3c0},
+ {0x90094, 0x159},
+ {0x90095, 0x18},
+ {0x90096, 0x10},
+ {0x90097, 0x109},
+ {0x90098, 0x0},
+ {0x90099, 0x3c0},
+ {0x9009a, 0x109},
+ {0x9009b, 0x18},
+ {0x9009c, 0x4},
+ {0x9009d, 0x48},
+ {0x9009e, 0x18},
+ {0x9009f, 0x4},
+ {0x900a0, 0x58},
+ {0x900a1, 0xb},
+ {0x900a2, 0x10},
+ {0x900a3, 0x109},
+ {0x900a4, 0x1},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x5},
+ {0x900a8, 0x7c0},
+ {0x900a9, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x790},
+ {0x900ac, 0x11a},
+ {0x900ad, 0x8},
+ {0x900ae, 0x7aa},
+ {0x900af, 0x2a},
+ {0x900b0, 0x10},
+ {0x900b1, 0x7b2},
+ {0x900b2, 0x2a},
+ {0x900b3, 0x0},
+ {0x900b4, 0x7c8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x10},
+ {0x900b7, 0x10},
+ {0x900b8, 0x109},
+ {0x900b9, 0x10},
+ {0x900ba, 0x2a8},
+ {0x900bb, 0x129},
+ {0x900bc, 0x8},
+ {0x900bd, 0x370},
+ {0x900be, 0x129},
+ {0x900bf, 0xa},
+ {0x900c0, 0x3c8},
+ {0x900c1, 0x1a9},
+ {0x900c2, 0xc},
+ {0x900c3, 0x408},
+ {0x900c4, 0x199},
+ {0x900c5, 0x14},
+ {0x900c6, 0x790},
+ {0x900c7, 0x11a},
+ {0x900c8, 0x8},
+ {0x900c9, 0x4},
+ {0x900ca, 0x18},
+ {0x900cb, 0xe},
+ {0x900cc, 0x408},
+ {0x900cd, 0x199},
+ {0x900ce, 0x8},
+ {0x900cf, 0x8568},
+ {0x900d0, 0x108},
+ {0x900d1, 0x18},
+ {0x900d2, 0x790},
+ {0x900d3, 0x16a},
+ {0x900d4, 0x8},
+ {0x900d5, 0x1d8},
+ {0x900d6, 0x169},
+ {0x900d7, 0x10},
+ {0x900d8, 0x8558},
+ {0x900d9, 0x168},
+ {0x900da, 0x1ff8},
+ {0x900db, 0x85a8},
+ {0x900dc, 0x1e8},
+ {0x900dd, 0x50},
+ {0x900de, 0x798},
+ {0x900df, 0x16a},
+ {0x900e0, 0x60},
+ {0x900e1, 0x7a0},
+ {0x900e2, 0x16a},
+ {0x900e3, 0x8},
+ {0x900e4, 0x8310},
+ {0x900e5, 0x168},
+ {0x900e6, 0x8},
+ {0x900e7, 0xa310},
+ {0x900e8, 0x168},
+ {0x900e9, 0xa},
+ {0x900ea, 0x408},
+ {0x900eb, 0x169},
+ {0x900ec, 0x6e},
+ {0x900ed, 0x0},
+ {0x900ee, 0x68},
+ {0x900ef, 0x0},
+ {0x900f0, 0x408},
+ {0x900f1, 0x169},
+ {0x900f2, 0x0},
+ {0x900f3, 0x8310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x0},
+ {0x900f6, 0xa310},
+ {0x900f7, 0x168},
+ {0x900f8, 0x1ff8},
+ {0x900f9, 0x85a8},
+ {0x900fa, 0x1e8},
+ {0x900fb, 0x68},
+ {0x900fc, 0x798},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x78},
+ {0x900ff, 0x7a0},
+ {0x90100, 0x16a},
+ {0x90101, 0x68},
+ {0x90102, 0x790},
+ {0x90103, 0x16a},
+ {0x90104, 0x8},
+ {0x90105, 0x8b10},
+ {0x90106, 0x168},
+ {0x90107, 0x8},
+ {0x90108, 0xab10},
+ {0x90109, 0x168},
+ {0x9010a, 0xa},
+ {0x9010b, 0x408},
+ {0x9010c, 0x169},
+ {0x9010d, 0x58},
+ {0x9010e, 0x0},
+ {0x9010f, 0x68},
+ {0x90110, 0x0},
+ {0x90111, 0x408},
+ {0x90112, 0x169},
+ {0x90113, 0x0},
+ {0x90114, 0x8b10},
+ {0x90115, 0x168},
+ {0x90116, 0x1},
+ {0x90117, 0xab10},
+ {0x90118, 0x168},
+ {0x90119, 0x0},
+ {0x9011a, 0x1d8},
+ {0x9011b, 0x169},
+ {0x9011c, 0x80},
+ {0x9011d, 0x790},
+ {0x9011e, 0x16a},
+ {0x9011f, 0x18},
+ {0x90120, 0x7aa},
+ {0x90121, 0x6a},
+ {0x90122, 0xa},
+ {0x90123, 0x0},
+ {0x90124, 0x1e9},
+ {0x90125, 0x8},
+ {0x90126, 0x8080},
+ {0x90127, 0x108},
+ {0x90128, 0xf},
+ {0x90129, 0x408},
+ {0x9012a, 0x169},
+ {0x9012b, 0xc},
+ {0x9012c, 0x0},
+ {0x9012d, 0x68},
+ {0x9012e, 0x9},
+ {0x9012f, 0x0},
+ {0x90130, 0x1a9},
+ {0x90131, 0x0},
+ {0x90132, 0x408},
+ {0x90133, 0x169},
+ {0x90134, 0x0},
+ {0x90135, 0x8080},
+ {0x90136, 0x108},
+ {0x90137, 0x8},
+ {0x90138, 0x7aa},
+ {0x90139, 0x6a},
+ {0x9013a, 0x0},
+ {0x9013b, 0x8568},
+ {0x9013c, 0x108},
+ {0x9013d, 0xb7},
+ {0x9013e, 0x790},
+ {0x9013f, 0x16a},
+ {0x90140, 0x1f},
+ {0x90141, 0x0},
+ {0x90142, 0x68},
+ {0x90143, 0x8},
+ {0x90144, 0x8558},
+ {0x90145, 0x168},
+ {0x90146, 0xf},
+ {0x90147, 0x408},
+ {0x90148, 0x169},
+ {0x90149, 0xd},
+ {0x9014a, 0x0},
+ {0x9014b, 0x68},
+ {0x9014c, 0x0},
+ {0x9014d, 0x408},
+ {0x9014e, 0x169},
+ {0x9014f, 0x0},
+ {0x90150, 0x8558},
+ {0x90151, 0x168},
+ {0x90152, 0x8},
+ {0x90153, 0x3c8},
+ {0x90154, 0x1a9},
+ {0x90155, 0x3},
+ {0x90156, 0x370},
+ {0x90157, 0x129},
+ {0x90158, 0x20},
+ {0x90159, 0x2aa},
+ {0x9015a, 0x9},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x104},
+ {0x90164, 0x8},
+ {0x90165, 0x448},
+ {0x90166, 0x109},
+ {0x90167, 0xf},
+ {0x90168, 0x7c0},
+ {0x90169, 0x109},
+ {0x9016a, 0x0},
+ {0x9016b, 0xe8},
+ {0x9016c, 0x109},
+ {0x9016d, 0x47},
+ {0x9016e, 0x630},
+ {0x9016f, 0x109},
+ {0x90170, 0x8},
+ {0x90171, 0x618},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0xe0},
+ {0x90175, 0x109},
+ {0x90176, 0x0},
+ {0x90177, 0x7c8},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0x8140},
+ {0x9017b, 0x10c},
+ {0x9017c, 0x0},
+ {0x9017d, 0x478},
+ {0x9017e, 0x109},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x0},
+ {0x90006, 0x8},
+ {0x90007, 0x7c8},
+ {0x90008, 0x109},
+ {0x90009, 0x0},
+ {0x9000a, 0x400},
+ {0x9000b, 0x106},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2b},
+ {0x90026, 0x69},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x200be, 0x3},
+ {0x2000b, 0x1c2},
+ {0x2000c, 0x64},
+ {0x2000d, 0x3e8},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xe1},
+ {0x12000c, 0x32},
+ {0x12000d, 0x1f4},
+ {0x12000e, 0x10},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x400f1, 0xe},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 800mts 1D */
+ .drate = 800,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 1600mts 2D */
+ .drate = 1600,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_1600mts = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 1600, 800, 625, },
+ .fsp_cfg = ddr_dram_fsp_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx91_evk/lpddr4_timing_2400mts.c b/board/freescale/imx91_evk/lpddr4_timing_2400mts.c
new file mode 100644
index 0000000..e0e6f5d
--- /dev/null
+++ b/board/freescale/imx91_evk/lpddr4_timing_2400mts.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x44100001},
+ {0x4e300000, 0x8000ff},
+ {0x4e300008, 0x0},
+ {0x4e300080, 0x80000512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x135C2110},
+ {0x4e300104, 0xF8990011},
+ {0x4e300108, 0x636E08CC},
+ {0x4e30010C, 0x0061E070},
+ {0x4e300124, 0x124E0000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x31D00000},
+ {0x4e300170, 0x8B0B0608},
+ {0x4e300250, 0x0000001A},
+ {0x4e300254, 0x00DC00DC},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ {0x4e300300, 0x1633160D},
+ {0x4e300304, 0x00DC180C},
+ {0x4e300308, 0x0C3C0927},
+ },
+ {
+ {0x01, 0xC4},
+ {0x02, 0x24},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x010D1100},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0xBABAC068},
+ {0x4e30010C, 0x00610158},
+ {0x4e300124, 0x09270000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30400000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x0000000D},
+ {0x4e300254, 0x006A006A},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0xA4},
+ {0x02, 0x52},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 1,
+ },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x4},
+ {0x100a1, 0x5},
+ {0x100a2, 0x6},
+ {0x100a3, 0x7},
+ {0x100a4, 0x0},
+ {0x100a5, 0x1},
+ {0x100a6, 0x2},
+ {0x100a7, 0x3},
+ {0x110a0, 0x3},
+ {0x110a1, 0x2},
+ {0x110a2, 0x0},
+ {0x110a3, 0x1},
+ {0x110a4, 0x7},
+ {0x110a5, 0x6},
+ {0x110a6, 0x4},
+ {0x110a7, 0x5},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x200c5, 0xa},
+ {0x1200c5, 0x2},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x1},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x2007d, 0x212},
+ {0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0x600},
+ {0x1014d, 0x600},
+ {0x1104d, 0x600},
+ {0x1114d, 0x600},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0xe3f},
+ {0x10149, 0xe3f},
+ {0x11049, 0xe3f},
+ {0x11149, 0xe3f},
+ {0x110049, 0xe3f},
+ {0x110149, 0xe3f},
+ {0x111049, 0xe3f},
+ {0x111149, 0xe3f},
+ {0x210049, 0xe3f},
+ {0x210149, 0xe3f},
+ {0x211049, 0xe3f},
+ {0x211149, 0xe3f},
+ {0x43, 0x7f},
+ {0x1043, 0x7f},
+ {0x2043, 0x7f},
+ {0x20018, 0x1},
+ {0x20075, 0x4},
+ {0x20050, 0x11},
+ {0x2009b, 0x2},
+ {0x20008, 0x258},
+ {0x120008, 0x12c},
+ {0x220008, 0x9c},
+ {0x20088, 0x9},
+ {0x200b2, 0x10c},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x1200b2, 0x10c},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x10c},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x600},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5655},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0x20021, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x41},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x2007d, 0x0},
+ {0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
+ {0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x2009b, 0x0},
+ {0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
+ {0x20088, 0x0},
+ {0x200b2, 0x0},
+ {0x10043, 0x0},
+ {0x10143, 0x0},
+ {0x11043, 0x0},
+ {0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
+ {0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
+ {0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
+ {0x90047, 0x0},
+ {0x90048, 0x0},
+ {0x90049, 0x0},
+ {0x9004a, 0x0},
+ {0x9004b, 0x0},
+ {0x9004c, 0x0},
+ {0x9004d, 0x0},
+ {0x9004e, 0x0},
+ {0x9004f, 0x0},
+ {0x90050, 0x0},
+ {0x90051, 0x0},
+ {0x90052, 0x0},
+ {0x90053, 0x0},
+ {0x90054, 0x0},
+ {0x90055, 0x0},
+ {0x90056, 0x0},
+ {0x90057, 0x0},
+ {0x90058, 0x0},
+ {0x90059, 0x0},
+ {0x9005a, 0x0},
+ {0x9005b, 0x0},
+ {0x9005c, 0x0},
+ {0x9005d, 0x0},
+ {0x9005e, 0x0},
+ {0x9005f, 0x0},
+ {0x90060, 0x0},
+ {0x90061, 0x0},
+ {0x90062, 0x0},
+ {0x90063, 0x0},
+ {0x90064, 0x0},
+ {0x90065, 0x0},
+ {0x90066, 0x0},
+ {0x90067, 0x0},
+ {0x90068, 0x0},
+ {0x90069, 0x0},
+ {0x9006a, 0x0},
+ {0x9006b, 0x0},
+ {0x9006c, 0x0},
+ {0x9006d, 0x0},
+ {0x9006e, 0x0},
+ {0x9006f, 0x0},
+ {0x90070, 0x0},
+ {0x90071, 0x0},
+ {0x90072, 0x0},
+ {0x90073, 0x0},
+ {0x90074, 0x0},
+ {0x90075, 0x0},
+ {0x90076, 0x0},
+ {0x90077, 0x0},
+ {0x90078, 0x0},
+ {0x90079, 0x0},
+ {0x9007a, 0x0},
+ {0x9007b, 0x0},
+ {0x9007c, 0x0},
+ {0x9007d, 0x0},
+ {0x9007e, 0x0},
+ {0x9007f, 0x0},
+ {0x90080, 0x0},
+ {0x90081, 0x0},
+ {0x90082, 0x0},
+ {0x90083, 0x0},
+ {0x90084, 0x0},
+ {0x90085, 0x0},
+ {0x90086, 0x0},
+ {0x90087, 0x0},
+ {0x90088, 0x0},
+ {0x90089, 0x0},
+ {0x9008a, 0x0},
+ {0x9008b, 0x0},
+ {0x9008c, 0x0},
+ {0x9008d, 0x0},
+ {0x9008e, 0x0},
+ {0x9008f, 0x0},
+ {0x90090, 0x0},
+ {0x90091, 0x0},
+ {0x90092, 0x0},
+ {0x90093, 0x0},
+ {0x90094, 0x0},
+ {0x90095, 0x0},
+ {0x90096, 0x0},
+ {0x90097, 0x0},
+ {0x90098, 0x0},
+ {0x90099, 0x0},
+ {0x9009a, 0x0},
+ {0x9009b, 0x0},
+ {0x9009c, 0x0},
+ {0x9009d, 0x0},
+ {0x9009e, 0x0},
+ {0x9009f, 0x0},
+ {0x900a0, 0x0},
+ {0x900a1, 0x0},
+ {0x900a2, 0x0},
+ {0x900a3, 0x0},
+ {0x900a4, 0x0},
+ {0x900a5, 0x0},
+ {0x900a6, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x0},
+ {0x900a9, 0x0},
+ {0x40000, 0x0},
+ {0x40020, 0x0},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x0},
+ {0x40021, 0x0},
+ {0x40041, 0x0},
+ {0x40061, 0x0},
+ {0x40002, 0x0},
+ {0x40022, 0x0},
+ {0x40042, 0x0},
+ {0x40062, 0x0},
+ {0x40003, 0x0},
+ {0x40023, 0x0},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x0},
+ {0x40024, 0x0},
+ {0x40044, 0x0},
+ {0x40064, 0x0},
+ {0x40005, 0x0},
+ {0x40025, 0x0},
+ {0x40045, 0x0},
+ {0x40065, 0x0},
+ {0x40006, 0x0},
+ {0x40026, 0x0},
+ {0x40046, 0x0},
+ {0x40066, 0x0},
+ {0x40007, 0x0},
+ {0x40027, 0x0},
+ {0x40047, 0x0},
+ {0x40067, 0x0},
+ {0x40008, 0x0},
+ {0x40028, 0x0},
+ {0x40048, 0x0},
+ {0x40068, 0x0},
+ {0x40009, 0x0},
+ {0x40029, 0x0},
+ {0x40049, 0x0},
+ {0x40069, 0x0},
+ {0x4000a, 0x0},
+ {0x4002a, 0x0},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x0},
+ {0x4002b, 0x0},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x0},
+ {0x4002c, 0x0},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0x0},
+ {0x4002d, 0x0},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x0},
+ {0x4002e, 0x0},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x0},
+ {0x4002f, 0x0},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x0},
+ {0x40030, 0x0},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x0},
+ {0x40031, 0x0},
+ {0x40051, 0x0},
+ {0x40071, 0x0},
+ {0x40012, 0x0},
+ {0x40032, 0x0},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x0},
+ {0x40033, 0x0},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x0},
+ {0x40034, 0x0},
+ {0x40054, 0x0},
+ {0x40074, 0x0},
+ {0x40015, 0x0},
+ {0x40035, 0x0},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x0},
+ {0x40036, 0x0},
+ {0x40056, 0x0},
+ {0x40076, 0x0},
+ {0x40017, 0x0},
+ {0x40037, 0x0},
+ {0x40057, 0x0},
+ {0x40077, 0x0},
+ {0x40018, 0x0},
+ {0x40038, 0x0},
+ {0x40058, 0x0},
+ {0x40078, 0x0},
+ {0x40019, 0x0},
+ {0x40039, 0x0},
+ {0x40059, 0x0},
+ {0x40079, 0x0},
+ {0x4001a, 0x0},
+ {0x4003a, 0x0},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x0},
+ {0x900ac, 0x0},
+ {0x900ad, 0x0},
+ {0x900ae, 0x0},
+ {0x900af, 0x0},
+ {0x900b0, 0x0},
+ {0x900b1, 0x0},
+ {0x900b2, 0x0},
+ {0x900b3, 0x0},
+ {0x900b4, 0x0},
+ {0x900b5, 0x0},
+ {0x900b6, 0x0},
+ {0x900b7, 0x0},
+ {0x900b8, 0x0},
+ {0x900b9, 0x0},
+ {0x900ba, 0x0},
+ {0x900bb, 0x0},
+ {0x900bc, 0x0},
+ {0x900bd, 0x0},
+ {0x900be, 0x0},
+ {0x900bf, 0x0},
+ {0x900c0, 0x0},
+ {0x900c1, 0x0},
+ {0x900c2, 0x0},
+ {0x900c3, 0x0},
+ {0x900c4, 0x0},
+ {0x900c5, 0x0},
+ {0x900c6, 0x0},
+ {0x900c7, 0x0},
+ {0x900c8, 0x0},
+ {0x900c9, 0x0},
+ {0x900ca, 0x0},
+ {0x900cb, 0x0},
+ {0x900cc, 0x0},
+ {0x900cd, 0x0},
+ {0x900ce, 0x0},
+ {0x900cf, 0x0},
+ {0x900d0, 0x0},
+ {0x900d1, 0x0},
+ {0x900d2, 0x0},
+ {0x900d3, 0x0},
+ {0x900d4, 0x0},
+ {0x900d5, 0x0},
+ {0x900d6, 0x0},
+ {0x900d7, 0x0},
+ {0x900d8, 0x0},
+ {0x900d9, 0x0},
+ {0x900da, 0x0},
+ {0x900db, 0x0},
+ {0x900dc, 0x0},
+ {0x900dd, 0x0},
+ {0x900de, 0x0},
+ {0x900df, 0x0},
+ {0x900e0, 0x0},
+ {0x900e1, 0x0},
+ {0x900e2, 0x0},
+ {0x900e3, 0x0},
+ {0x900e4, 0x0},
+ {0x900e5, 0x0},
+ {0x900e6, 0x0},
+ {0x900e7, 0x0},
+ {0x900e8, 0x0},
+ {0x900e9, 0x0},
+ {0x900ea, 0x0},
+ {0x900eb, 0x0},
+ {0x900ec, 0x0},
+ {0x900ed, 0x0},
+ {0x900ee, 0x0},
+ {0x900ef, 0x0},
+ {0x900f0, 0x0},
+ {0x900f1, 0x0},
+ {0x900f2, 0x0},
+ {0x900f3, 0x0},
+ {0x900f4, 0x0},
+ {0x900f5, 0x0},
+ {0x900f6, 0x0},
+ {0x900f7, 0x0},
+ {0x900f8, 0x0},
+ {0x900f9, 0x0},
+ {0x900fa, 0x0},
+ {0x900fb, 0x0},
+ {0x900fc, 0x0},
+ {0x900fd, 0x0},
+ {0x900fe, 0x0},
+ {0x900ff, 0x0},
+ {0x90100, 0x0},
+ {0x90101, 0x0},
+ {0x90102, 0x0},
+ {0x90103, 0x0},
+ {0x90104, 0x0},
+ {0x90105, 0x0},
+ {0x90106, 0x0},
+ {0x90107, 0x0},
+ {0x90108, 0x0},
+ {0x90109, 0x0},
+ {0x9010a, 0x0},
+ {0x9010b, 0x0},
+ {0x9010c, 0x0},
+ {0x9010d, 0x0},
+ {0x9010e, 0x0},
+ {0x9010f, 0x0},
+ {0x90110, 0x0},
+ {0x90111, 0x0},
+ {0x90112, 0x0},
+ {0x90113, 0x0},
+ {0x90114, 0x0},
+ {0x90115, 0x0},
+ {0x90116, 0x0},
+ {0x90117, 0x0},
+ {0x90118, 0x0},
+ {0x90119, 0x0},
+ {0x9011a, 0x0},
+ {0x9011b, 0x0},
+ {0x9011c, 0x0},
+ {0x9011d, 0x0},
+ {0x9011e, 0x0},
+ {0x9011f, 0x0},
+ {0x90120, 0x0},
+ {0x90121, 0x0},
+ {0x90122, 0x0},
+ {0x90123, 0x0},
+ {0x90124, 0x0},
+ {0x90125, 0x0},
+ {0x90126, 0x0},
+ {0x90127, 0x0},
+ {0x90128, 0x0},
+ {0x90129, 0x0},
+ {0x9012a, 0x0},
+ {0x9012b, 0x0},
+ {0x9012c, 0x0},
+ {0x9012d, 0x0},
+ {0x9012e, 0x0},
+ {0x9012f, 0x0},
+ {0x90130, 0x0},
+ {0x90131, 0x0},
+ {0x90132, 0x0},
+ {0x90133, 0x0},
+ {0x90134, 0x0},
+ {0x90135, 0x0},
+ {0x90136, 0x0},
+ {0x90137, 0x0},
+ {0x90138, 0x0},
+ {0x90139, 0x0},
+ {0x9013a, 0x0},
+ {0x9013b, 0x0},
+ {0x9013c, 0x0},
+ {0x9013d, 0x0},
+ {0x9013e, 0x0},
+ {0x9013f, 0x0},
+ {0x90140, 0x0},
+ {0x90141, 0x0},
+ {0x90142, 0x0},
+ {0x90143, 0x0},
+ {0x90144, 0x0},
+ {0x90145, 0x0},
+ {0x90146, 0x0},
+ {0x90147, 0x0},
+ {0x90148, 0x0},
+ {0x90149, 0x0},
+ {0x9014a, 0x0},
+ {0x9014b, 0x0},
+ {0x9014c, 0x0},
+ {0x9014d, 0x0},
+ {0x9014e, 0x0},
+ {0x9014f, 0x0},
+ {0x90150, 0x0},
+ {0x90151, 0x0},
+ {0x90152, 0x0},
+ {0x90153, 0x0},
+ {0x90154, 0x0},
+ {0x90155, 0x0},
+ {0x90156, 0x0},
+ {0x90157, 0x0},
+ {0x90158, 0x0},
+ {0x90159, 0x0},
+ {0x9015a, 0x0},
+ {0x9015b, 0x0},
+ {0x9015c, 0x0},
+ {0x9015d, 0x0},
+ {0x9015e, 0x0},
+ {0x9015f, 0x0},
+ {0x90160, 0x0},
+ {0x90161, 0x0},
+ {0x90162, 0x0},
+ {0x90163, 0x0},
+ {0x90164, 0x0},
+ {0x90165, 0x0},
+ {0x90166, 0x0},
+ {0x90167, 0x0},
+ {0x90168, 0x0},
+ {0x90169, 0x0},
+ {0x9016a, 0x0},
+ {0x9016b, 0x0},
+ {0x9016c, 0x0},
+ {0x9016d, 0x0},
+ {0x9016e, 0x0},
+ {0x9016f, 0x0},
+ {0x90170, 0x0},
+ {0x90171, 0x0},
+ {0x90172, 0x0},
+ {0x90173, 0x0},
+ {0x90174, 0x0},
+ {0x90175, 0x0},
+ {0x90176, 0x0},
+ {0x90177, 0x0},
+ {0x90178, 0x0},
+ {0x90179, 0x0},
+ {0x9017a, 0x0},
+ {0x9017b, 0x0},
+ {0x9017c, 0x0},
+ {0x9017d, 0x0},
+ {0x9017e, 0x0},
+ {0x9017f, 0x0},
+ {0x90180, 0x0},
+ {0x90181, 0x0},
+ {0x90182, 0x0},
+ {0x90183, 0x0},
+ {0x90184, 0x0},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x0},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x0},
+ {0x90017, 0x0},
+ {0x9001f, 0x0},
+ {0x90026, 0x0},
+ {0x400d0, 0x0},
+ {0x400d1, 0x0},
+ {0x400d2, 0x0},
+ {0x400d3, 0x0},
+ {0x400d4, 0x0},
+ {0x400d5, 0x0},
+ {0x400d6, 0x0},
+ {0x400d7, 0x0},
+ {0x200be, 0x0},
+ {0x2000b, 0x0},
+ {0x2000c, 0x0},
+ {0x2000d, 0x0},
+ {0x2000e, 0x0},
+ {0x12000b, 0x0},
+ {0x12000c, 0x0},
+ {0x12000d, 0x0},
+ {0x12000e, 0x0},
+ {0x22000b, 0x0},
+ {0x22000c, 0x0},
+ {0x22000d, 0x0},
+ {0x22000e, 0x0},
+ {0x9000c, 0x0},
+ {0x9000d, 0x0},
+ {0x9000e, 0x0},
+ {0x9000f, 0x0},
+ {0x90010, 0x0},
+ {0x90011, 0x0},
+ {0x90012, 0x0},
+ {0x90013, 0x0},
+ {0x20010, 0x0},
+ {0x20011, 0x0},
+ {0x120010, 0x0},
+ {0x120011, 0x0},
+ {0x40080, 0x0},
+ {0x40081, 0x0},
+ {0x40082, 0x0},
+ {0x40083, 0x0},
+ {0x40084, 0x0},
+ {0x40085, 0x0},
+ {0x140080, 0x0},
+ {0x140081, 0x0},
+ {0x140082, 0x0},
+ {0x140083, 0x0},
+ {0x140084, 0x0},
+ {0x140085, 0x0},
+ {0x240080, 0x0},
+ {0x240081, 0x0},
+ {0x240082, 0x0},
+ {0x240083, 0x0},
+ {0x240084, 0x0},
+ {0x240085, 0x0},
+ {0x400fd, 0x0},
+ {0x400f1, 0x0},
+ {0x10011, 0x0},
+ {0x10012, 0x0},
+ {0x10013, 0x0},
+ {0x10018, 0x0},
+ {0x10002, 0x0},
+ {0x100b2, 0x0},
+ {0x101b4, 0x0},
+ {0x102b4, 0x0},
+ {0x103b4, 0x0},
+ {0x104b4, 0x0},
+ {0x105b4, 0x0},
+ {0x106b4, 0x0},
+ {0x107b4, 0x0},
+ {0x108b4, 0x0},
+ {0x11011, 0x0},
+ {0x11012, 0x0},
+ {0x11013, 0x0},
+ {0x11018, 0x0},
+ {0x11002, 0x0},
+ {0x110b2, 0x0},
+ {0x111b4, 0x0},
+ {0x112b4, 0x0},
+ {0x113b4, 0x0},
+ {0x114b4, 0x0},
+ {0x115b4, 0x0},
+ {0x116b4, 0x0},
+ {0x117b4, 0x0},
+ {0x118b4, 0x0},
+ {0x20089, 0x0},
+ {0xc0080, 0x0},
+ {0x200cb, 0x0},
+ {0x10068, 0x0},
+ {0x10069, 0x0},
+ {0x10168, 0x0},
+ {0x10169, 0x0},
+ {0x10268, 0x0},
+ {0x10269, 0x0},
+ {0x10368, 0x0},
+ {0x10369, 0x0},
+ {0x10468, 0x0},
+ {0x10469, 0x0},
+ {0x10568, 0x0},
+ {0x10569, 0x0},
+ {0x10668, 0x0},
+ {0x10669, 0x0},
+ {0x10768, 0x0},
+ {0x10769, 0x0},
+ {0x10868, 0x0},
+ {0x10869, 0x0},
+ {0x100aa, 0x0},
+ {0x10062, 0x0},
+ {0x10001, 0x0},
+ {0x100a0, 0x0},
+ {0x100a1, 0x0},
+ {0x100a2, 0x0},
+ {0x100a3, 0x0},
+ {0x100a4, 0x0},
+ {0x100a5, 0x0},
+ {0x100a6, 0x0},
+ {0x100a7, 0x0},
+ {0x11068, 0x0},
+ {0x11069, 0x0},
+ {0x11168, 0x0},
+ {0x11169, 0x0},
+ {0x11268, 0x0},
+ {0x11269, 0x0},
+ {0x11368, 0x0},
+ {0x11369, 0x0},
+ {0x11468, 0x0},
+ {0x11469, 0x0},
+ {0x11568, 0x0},
+ {0x11569, 0x0},
+ {0x11668, 0x0},
+ {0x11669, 0x0},
+ {0x11768, 0x0},
+ {0x11769, 0x0},
+ {0x11868, 0x0},
+ {0x11869, 0x0},
+ {0x110aa, 0x0},
+ {0x11062, 0x0},
+ {0x11001, 0x0},
+ {0x110a0, 0x0},
+ {0x110a1, 0x0},
+ {0x110a2, 0x0},
+ {0x110a3, 0x0},
+ {0x110a4, 0x0},
+ {0x110a5, 0x0},
+ {0x110a6, 0x0},
+ {0x110a7, 0x0},
+ {0x80, 0x0},
+ {0x1080, 0x0},
+ {0x2080, 0x0},
+ {0x10020, 0x0},
+ {0x10080, 0x0},
+ {0x10081, 0x0},
+ {0x100d0, 0x0},
+ {0x100d1, 0x0},
+ {0x1008c, 0x0},
+ {0x1008d, 0x0},
+ {0x10180, 0x0},
+ {0x10181, 0x0},
+ {0x101d0, 0x0},
+ {0x101d1, 0x0},
+ {0x1018c, 0x0},
+ {0x1018d, 0x0},
+ {0x100c0, 0x0},
+ {0x100c1, 0x0},
+ {0x101c0, 0x0},
+ {0x101c1, 0x0},
+ {0x102c0, 0x0},
+ {0x102c1, 0x0},
+ {0x103c0, 0x0},
+ {0x103c1, 0x0},
+ {0x104c0, 0x0},
+ {0x104c1, 0x0},
+ {0x105c0, 0x0},
+ {0x105c1, 0x0},
+ {0x106c0, 0x0},
+ {0x106c1, 0x0},
+ {0x107c0, 0x0},
+ {0x107c1, 0x0},
+ {0x108c0, 0x0},
+ {0x108c1, 0x0},
+ {0x100ae, 0x0},
+ {0x100af, 0x0},
+ {0x11020, 0x0},
+ {0x11080, 0x0},
+ {0x11081, 0x0},
+ {0x110d0, 0x0},
+ {0x110d1, 0x0},
+ {0x1108c, 0x0},
+ {0x1108d, 0x0},
+ {0x11180, 0x0},
+ {0x11181, 0x0},
+ {0x111d0, 0x0},
+ {0x111d1, 0x0},
+ {0x1118c, 0x0},
+ {0x1118d, 0x0},
+ {0x110c0, 0x0},
+ {0x110c1, 0x0},
+ {0x111c0, 0x0},
+ {0x111c1, 0x0},
+ {0x112c0, 0x0},
+ {0x112c1, 0x0},
+ {0x113c0, 0x0},
+ {0x113c1, 0x0},
+ {0x114c0, 0x0},
+ {0x114c1, 0x0},
+ {0x115c0, 0x0},
+ {0x115c1, 0x0},
+ {0x116c0, 0x0},
+ {0x116c1, 0x0},
+ {0x117c0, 0x0},
+ {0x117c1, 0x0},
+ {0x118c0, 0x0},
+ {0x118c1, 0x0},
+ {0x110ae, 0x0},
+ {0x110af, 0x0},
+ {0x90201, 0x0},
+ {0x90202, 0x0},
+ {0x90203, 0x0},
+ {0x90205, 0x0},
+ {0x90206, 0x0},
+ {0x90207, 0x0},
+ {0x90208, 0x0},
+ {0x20020, 0x0},
+ {0x100080, 0x0},
+ {0x101080, 0x0},
+ {0x102080, 0x0},
+ {0x110020, 0x0},
+ {0x110080, 0x0},
+ {0x110081, 0x0},
+ {0x1100d0, 0x0},
+ {0x1100d1, 0x0},
+ {0x11008c, 0x0},
+ {0x11008d, 0x0},
+ {0x110180, 0x0},
+ {0x110181, 0x0},
+ {0x1101d0, 0x0},
+ {0x1101d1, 0x0},
+ {0x11018c, 0x0},
+ {0x11018d, 0x0},
+ {0x1100c0, 0x0},
+ {0x1100c1, 0x0},
+ {0x1101c0, 0x0},
+ {0x1101c1, 0x0},
+ {0x1102c0, 0x0},
+ {0x1102c1, 0x0},
+ {0x1103c0, 0x0},
+ {0x1103c1, 0x0},
+ {0x1104c0, 0x0},
+ {0x1104c1, 0x0},
+ {0x1105c0, 0x0},
+ {0x1105c1, 0x0},
+ {0x1106c0, 0x0},
+ {0x1106c1, 0x0},
+ {0x1107c0, 0x0},
+ {0x1107c1, 0x0},
+ {0x1108c0, 0x0},
+ {0x1108c1, 0x0},
+ {0x1100ae, 0x0},
+ {0x1100af, 0x0},
+ {0x111020, 0x0},
+ {0x111080, 0x0},
+ {0x111081, 0x0},
+ {0x1110d0, 0x0},
+ {0x1110d1, 0x0},
+ {0x11108c, 0x0},
+ {0x11108d, 0x0},
+ {0x111180, 0x0},
+ {0x111181, 0x0},
+ {0x1111d0, 0x0},
+ {0x1111d1, 0x0},
+ {0x11118c, 0x0},
+ {0x11118d, 0x0},
+ {0x1110c0, 0x0},
+ {0x1110c1, 0x0},
+ {0x1111c0, 0x0},
+ {0x1111c1, 0x0},
+ {0x1112c0, 0x0},
+ {0x1112c1, 0x0},
+ {0x1113c0, 0x0},
+ {0x1113c1, 0x0},
+ {0x1114c0, 0x0},
+ {0x1114c1, 0x0},
+ {0x1115c0, 0x0},
+ {0x1115c1, 0x0},
+ {0x1116c0, 0x0},
+ {0x1116c1, 0x0},
+ {0x1117c0, 0x0},
+ {0x1117c1, 0x0},
+ {0x1118c0, 0x0},
+ {0x1118c1, 0x0},
+ {0x1110ae, 0x0},
+ {0x1110af, 0x0},
+ {0x190201, 0x0},
+ {0x190202, 0x0},
+ {0x190203, 0x0},
+ {0x190205, 0x0},
+ {0x190206, 0x0},
+ {0x190207, 0x0},
+ {0x190208, 0x0},
+ {0x120020, 0x0},
+ {0x200080, 0x0},
+ {0x201080, 0x0},
+ {0x202080, 0x0},
+ {0x210020, 0x0},
+ {0x210080, 0x0},
+ {0x210081, 0x0},
+ {0x2100d0, 0x0},
+ {0x2100d1, 0x0},
+ {0x21008c, 0x0},
+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
+ {0x20077, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
+ {0x400c0, 0x0},
+ {0x10040, 0x0},
+ {0x10140, 0x0},
+ {0x10240, 0x0},
+ {0x10340, 0x0},
+ {0x10440, 0x0},
+ {0x10540, 0x0},
+ {0x10640, 0x0},
+ {0x10740, 0x0},
+ {0x10840, 0x0},
+ {0x11040, 0x0},
+ {0x11140, 0x0},
+ {0x11240, 0x0},
+ {0x11340, 0x0},
+ {0x11440, 0x0},
+ {0x11540, 0x0},
+ {0x11640, 0x0},
+ {0x11740, 0x0},
+ {0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x960},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x24c4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x24c4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xc400},
+ {0x54033, 0x3324},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xc400},
+ {0x54039, 0x3324},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x4b0},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x52a4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x52a4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xa400},
+ {0x54033, 0x3352},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xa400},
+ {0x54039, 0x3352},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4800},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4800},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3309},
+ {0x54034, 0x4600},
+ {0x54035, 0x11},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3309},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x11},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x960},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54010, 0x2080},
+ {0x54012, 0x110},
+ {0x54019, 0x24c4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x24c4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xc400},
+ {0x54033, 0x3324},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xc400},
+ {0x54039, 0x3324},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x30},
+ {0x90051, 0x65a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x45a},
+ {0x90055, 0x9},
+ {0x90056, 0x0},
+ {0x90057, 0x448},
+ {0x90058, 0x109},
+ {0x90059, 0x40},
+ {0x9005a, 0x633},
+ {0x9005b, 0x179},
+ {0x9005c, 0x1},
+ {0x9005d, 0x618},
+ {0x9005e, 0x109},
+ {0x9005f, 0x40c0},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x8},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x4040},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x0},
+ {0x90069, 0x4},
+ {0x9006a, 0x48},
+ {0x9006b, 0x40},
+ {0x9006c, 0x633},
+ {0x9006d, 0x149},
+ {0x9006e, 0x0},
+ {0x9006f, 0x658},
+ {0x90070, 0x109},
+ {0x90071, 0x10},
+ {0x90072, 0x4},
+ {0x90073, 0x18},
+ {0x90074, 0x0},
+ {0x90075, 0x4},
+ {0x90076, 0x78},
+ {0x90077, 0x549},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0xd49},
+ {0x9007b, 0x633},
+ {0x9007c, 0x159},
+ {0x9007d, 0x94a},
+ {0x9007e, 0x633},
+ {0x9007f, 0x159},
+ {0x90080, 0x441},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x42},
+ {0x90084, 0x633},
+ {0x90085, 0x149},
+ {0x90086, 0x1},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x0},
+ {0x9008a, 0xe0},
+ {0x9008b, 0x109},
+ {0x9008c, 0xa},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x9},
+ {0x90090, 0x3c0},
+ {0x90091, 0x149},
+ {0x90092, 0x9},
+ {0x90093, 0x3c0},
+ {0x90094, 0x159},
+ {0x90095, 0x18},
+ {0x90096, 0x10},
+ {0x90097, 0x109},
+ {0x90098, 0x0},
+ {0x90099, 0x3c0},
+ {0x9009a, 0x109},
+ {0x9009b, 0x18},
+ {0x9009c, 0x4},
+ {0x9009d, 0x48},
+ {0x9009e, 0x18},
+ {0x9009f, 0x4},
+ {0x900a0, 0x58},
+ {0x900a1, 0xb},
+ {0x900a2, 0x10},
+ {0x900a3, 0x109},
+ {0x900a4, 0x1},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x5},
+ {0x900a8, 0x7c0},
+ {0x900a9, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x790},
+ {0x900ac, 0x11a},
+ {0x900ad, 0x8},
+ {0x900ae, 0x7aa},
+ {0x900af, 0x2a},
+ {0x900b0, 0x10},
+ {0x900b1, 0x7b2},
+ {0x900b2, 0x2a},
+ {0x900b3, 0x0},
+ {0x900b4, 0x7c8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x10},
+ {0x900b7, 0x10},
+ {0x900b8, 0x109},
+ {0x900b9, 0x10},
+ {0x900ba, 0x2a8},
+ {0x900bb, 0x129},
+ {0x900bc, 0x8},
+ {0x900bd, 0x370},
+ {0x900be, 0x129},
+ {0x900bf, 0xa},
+ {0x900c0, 0x3c8},
+ {0x900c1, 0x1a9},
+ {0x900c2, 0xc},
+ {0x900c3, 0x408},
+ {0x900c4, 0x199},
+ {0x900c5, 0x14},
+ {0x900c6, 0x790},
+ {0x900c7, 0x11a},
+ {0x900c8, 0x8},
+ {0x900c9, 0x4},
+ {0x900ca, 0x18},
+ {0x900cb, 0xe},
+ {0x900cc, 0x408},
+ {0x900cd, 0x199},
+ {0x900ce, 0x8},
+ {0x900cf, 0x8568},
+ {0x900d0, 0x108},
+ {0x900d1, 0x18},
+ {0x900d2, 0x790},
+ {0x900d3, 0x16a},
+ {0x900d4, 0x8},
+ {0x900d5, 0x1d8},
+ {0x900d6, 0x169},
+ {0x900d7, 0x10},
+ {0x900d8, 0x8558},
+ {0x900d9, 0x168},
+ {0x900da, 0x1ff8},
+ {0x900db, 0x85a8},
+ {0x900dc, 0x1e8},
+ {0x900dd, 0x50},
+ {0x900de, 0x798},
+ {0x900df, 0x16a},
+ {0x900e0, 0x60},
+ {0x900e1, 0x7a0},
+ {0x900e2, 0x16a},
+ {0x900e3, 0x8},
+ {0x900e4, 0x8310},
+ {0x900e5, 0x168},
+ {0x900e6, 0x8},
+ {0x900e7, 0xa310},
+ {0x900e8, 0x168},
+ {0x900e9, 0xa},
+ {0x900ea, 0x408},
+ {0x900eb, 0x169},
+ {0x900ec, 0x6e},
+ {0x900ed, 0x0},
+ {0x900ee, 0x68},
+ {0x900ef, 0x0},
+ {0x900f0, 0x408},
+ {0x900f1, 0x169},
+ {0x900f2, 0x0},
+ {0x900f3, 0x8310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x0},
+ {0x900f6, 0xa310},
+ {0x900f7, 0x168},
+ {0x900f8, 0x1ff8},
+ {0x900f9, 0x85a8},
+ {0x900fa, 0x1e8},
+ {0x900fb, 0x68},
+ {0x900fc, 0x798},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x78},
+ {0x900ff, 0x7a0},
+ {0x90100, 0x16a},
+ {0x90101, 0x68},
+ {0x90102, 0x790},
+ {0x90103, 0x16a},
+ {0x90104, 0x8},
+ {0x90105, 0x8b10},
+ {0x90106, 0x168},
+ {0x90107, 0x8},
+ {0x90108, 0xab10},
+ {0x90109, 0x168},
+ {0x9010a, 0xa},
+ {0x9010b, 0x408},
+ {0x9010c, 0x169},
+ {0x9010d, 0x58},
+ {0x9010e, 0x0},
+ {0x9010f, 0x68},
+ {0x90110, 0x0},
+ {0x90111, 0x408},
+ {0x90112, 0x169},
+ {0x90113, 0x0},
+ {0x90114, 0x8b10},
+ {0x90115, 0x168},
+ {0x90116, 0x1},
+ {0x90117, 0xab10},
+ {0x90118, 0x168},
+ {0x90119, 0x0},
+ {0x9011a, 0x1d8},
+ {0x9011b, 0x169},
+ {0x9011c, 0x80},
+ {0x9011d, 0x790},
+ {0x9011e, 0x16a},
+ {0x9011f, 0x18},
+ {0x90120, 0x7aa},
+ {0x90121, 0x6a},
+ {0x90122, 0xa},
+ {0x90123, 0x0},
+ {0x90124, 0x1e9},
+ {0x90125, 0x8},
+ {0x90126, 0x8080},
+ {0x90127, 0x108},
+ {0x90128, 0xf},
+ {0x90129, 0x408},
+ {0x9012a, 0x169},
+ {0x9012b, 0xc},
+ {0x9012c, 0x0},
+ {0x9012d, 0x68},
+ {0x9012e, 0x9},
+ {0x9012f, 0x0},
+ {0x90130, 0x1a9},
+ {0x90131, 0x0},
+ {0x90132, 0x408},
+ {0x90133, 0x169},
+ {0x90134, 0x0},
+ {0x90135, 0x8080},
+ {0x90136, 0x108},
+ {0x90137, 0x8},
+ {0x90138, 0x7aa},
+ {0x90139, 0x6a},
+ {0x9013a, 0x0},
+ {0x9013b, 0x8568},
+ {0x9013c, 0x108},
+ {0x9013d, 0xb7},
+ {0x9013e, 0x790},
+ {0x9013f, 0x16a},
+ {0x90140, 0x1f},
+ {0x90141, 0x0},
+ {0x90142, 0x68},
+ {0x90143, 0x8},
+ {0x90144, 0x8558},
+ {0x90145, 0x168},
+ {0x90146, 0xf},
+ {0x90147, 0x408},
+ {0x90148, 0x169},
+ {0x90149, 0xd},
+ {0x9014a, 0x0},
+ {0x9014b, 0x68},
+ {0x9014c, 0x0},
+ {0x9014d, 0x408},
+ {0x9014e, 0x169},
+ {0x9014f, 0x0},
+ {0x90150, 0x8558},
+ {0x90151, 0x168},
+ {0x90152, 0x8},
+ {0x90153, 0x3c8},
+ {0x90154, 0x1a9},
+ {0x90155, 0x3},
+ {0x90156, 0x370},
+ {0x90157, 0x129},
+ {0x90158, 0x20},
+ {0x90159, 0x2aa},
+ {0x9015a, 0x9},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x104},
+ {0x90164, 0x8},
+ {0x90165, 0x448},
+ {0x90166, 0x109},
+ {0x90167, 0xf},
+ {0x90168, 0x7c0},
+ {0x90169, 0x109},
+ {0x9016a, 0x0},
+ {0x9016b, 0xe8},
+ {0x9016c, 0x109},
+ {0x9016d, 0x47},
+ {0x9016e, 0x630},
+ {0x9016f, 0x109},
+ {0x90170, 0x8},
+ {0x90171, 0x618},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0xe0},
+ {0x90175, 0x109},
+ {0x90176, 0x0},
+ {0x90177, 0x7c8},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0x8140},
+ {0x9017b, 0x10c},
+ {0x9017c, 0x0},
+ {0x9017d, 0x478},
+ {0x9017e, 0x109},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x0},
+ {0x90006, 0x8},
+ {0x90007, 0x7c8},
+ {0x90008, 0x109},
+ {0x90009, 0x0},
+ {0x9000a, 0x400},
+ {0x9000b, 0x106},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2b},
+ {0x90026, 0x69},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x200be, 0x3},
+ {0x2000b, 0x2a3},
+ {0x2000c, 0x96},
+ {0x2000d, 0x5dc},
+ {0x2000e, 0x2c},
+ {0x12000b, 0x152},
+ {0x12000c, 0x4b},
+ {0x12000d, 0x2ee},
+ {0x12000e, 0x2c},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x400f1, 0xe},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1200mts 1D */
+ .drate = 1200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 2400, 1200, 625, },
+ .fsp_cfg = ddr_dram_fsp_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c b/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c
new file mode 100644
index 0000000..8116871
--- /dev/null
+++ b/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x44100001},
+ {0x4e300000, 0x8000ef},
+ {0x4e300008, 0x0},
+ {0x4e300080, 0x80000512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1012},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30d00},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0xc0000000},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x135C2110},
+ {0x4e300104, 0xF8990011},
+ {0x4e300108, 0x636E08CC},
+ {0x4e30010C, 0x0061E070},
+ {0x4e300124, 0x124E0000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x31D00000},
+ {0x4e300170, 0x8B0B0608},
+ {0x4e300250, 0x0000001A},
+ {0x4e300254, 0x00DC00DC},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ {0x4e300300, 0x1633160D},
+ {0x4e300304, 0x00DC180C},
+ {0x4e300308, 0x0C3C0927},
+ },
+ {
+ {0x01, 0xC4},
+ {0x02, 0x24},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x010D1100},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0xBABAC068},
+ {0x4e30010C, 0x00610158},
+ {0x4e300124, 0x09270000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30400000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x0000000D},
+ {0x4e300254, 0x006A006A},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0xA4},
+ {0x02, 0x52},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x33},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x48},
+ {0x16, 0x04},
+ },
+ 1,
+ },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x4},
+ {0x100a1, 0x5},
+ {0x100a2, 0x6},
+ {0x100a3, 0x7},
+ {0x100a4, 0x0},
+ {0x100a5, 0x1},
+ {0x100a6, 0x2},
+ {0x100a7, 0x3},
+ {0x110a0, 0x3},
+ {0x110a1, 0x2},
+ {0x110a2, 0x0},
+ {0x110a3, 0x1},
+ {0x110a4, 0x7},
+ {0x110a5, 0x6},
+ {0x110a6, 0x4},
+ {0x110a7, 0x5},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x200c5, 0xa},
+ {0x1200c5, 0x2},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x1},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x2007d, 0x212},
+ {0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0x600},
+ {0x1014d, 0x600},
+ {0x1104d, 0x600},
+ {0x1114d, 0x600},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0xe3f},
+ {0x10149, 0xe3f},
+ {0x11049, 0xe3f},
+ {0x11149, 0xe3f},
+ {0x110049, 0xe3f},
+ {0x110149, 0xe3f},
+ {0x111049, 0xe3f},
+ {0x111149, 0xe3f},
+ {0x210049, 0xe3f},
+ {0x210149, 0xe3f},
+ {0x211049, 0xe3f},
+ {0x211149, 0xe3f},
+ {0x43, 0x7f},
+ {0x1043, 0x7f},
+ {0x2043, 0x7f},
+ {0x20018, 0x1},
+ {0x20075, 0x4},
+ {0x20050, 0x11},
+ {0x2009b, 0x2},
+ {0x20008, 0x258},
+ {0x120008, 0x12c},
+ {0x220008, 0x9c},
+ {0x20088, 0x9},
+ {0x200b2, 0x10c},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x1200b2, 0x10c},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x10c},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x600},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5655},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0x20021, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x41},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x2007d, 0x0},
+ {0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
+ {0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x2009b, 0x0},
+ {0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
+ {0x20088, 0x0},
+ {0x200b2, 0x0},
+ {0x10043, 0x0},
+ {0x10143, 0x0},
+ {0x11043, 0x0},
+ {0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
+ {0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
+ {0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
+ {0x90047, 0x0},
+ {0x90048, 0x0},
+ {0x90049, 0x0},
+ {0x9004a, 0x0},
+ {0x9004b, 0x0},
+ {0x9004c, 0x0},
+ {0x9004d, 0x0},
+ {0x9004e, 0x0},
+ {0x9004f, 0x0},
+ {0x90050, 0x0},
+ {0x90051, 0x0},
+ {0x90052, 0x0},
+ {0x90053, 0x0},
+ {0x90054, 0x0},
+ {0x90055, 0x0},
+ {0x90056, 0x0},
+ {0x90057, 0x0},
+ {0x90058, 0x0},
+ {0x90059, 0x0},
+ {0x9005a, 0x0},
+ {0x9005b, 0x0},
+ {0x9005c, 0x0},
+ {0x9005d, 0x0},
+ {0x9005e, 0x0},
+ {0x9005f, 0x0},
+ {0x90060, 0x0},
+ {0x90061, 0x0},
+ {0x90062, 0x0},
+ {0x90063, 0x0},
+ {0x90064, 0x0},
+ {0x90065, 0x0},
+ {0x90066, 0x0},
+ {0x90067, 0x0},
+ {0x90068, 0x0},
+ {0x90069, 0x0},
+ {0x9006a, 0x0},
+ {0x9006b, 0x0},
+ {0x9006c, 0x0},
+ {0x9006d, 0x0},
+ {0x9006e, 0x0},
+ {0x9006f, 0x0},
+ {0x90070, 0x0},
+ {0x90071, 0x0},
+ {0x90072, 0x0},
+ {0x90073, 0x0},
+ {0x90074, 0x0},
+ {0x90075, 0x0},
+ {0x90076, 0x0},
+ {0x90077, 0x0},
+ {0x90078, 0x0},
+ {0x90079, 0x0},
+ {0x9007a, 0x0},
+ {0x9007b, 0x0},
+ {0x9007c, 0x0},
+ {0x9007d, 0x0},
+ {0x9007e, 0x0},
+ {0x9007f, 0x0},
+ {0x90080, 0x0},
+ {0x90081, 0x0},
+ {0x90082, 0x0},
+ {0x90083, 0x0},
+ {0x90084, 0x0},
+ {0x90085, 0x0},
+ {0x90086, 0x0},
+ {0x90087, 0x0},
+ {0x90088, 0x0},
+ {0x90089, 0x0},
+ {0x9008a, 0x0},
+ {0x9008b, 0x0},
+ {0x9008c, 0x0},
+ {0x9008d, 0x0},
+ {0x9008e, 0x0},
+ {0x9008f, 0x0},
+ {0x90090, 0x0},
+ {0x90091, 0x0},
+ {0x90092, 0x0},
+ {0x90093, 0x0},
+ {0x90094, 0x0},
+ {0x90095, 0x0},
+ {0x90096, 0x0},
+ {0x90097, 0x0},
+ {0x90098, 0x0},
+ {0x90099, 0x0},
+ {0x9009a, 0x0},
+ {0x9009b, 0x0},
+ {0x9009c, 0x0},
+ {0x9009d, 0x0},
+ {0x9009e, 0x0},
+ {0x9009f, 0x0},
+ {0x900a0, 0x0},
+ {0x900a1, 0x0},
+ {0x900a2, 0x0},
+ {0x900a3, 0x0},
+ {0x900a4, 0x0},
+ {0x900a5, 0x0},
+ {0x900a6, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x0},
+ {0x900a9, 0x0},
+ {0x40000, 0x0},
+ {0x40020, 0x0},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x0},
+ {0x40021, 0x0},
+ {0x40041, 0x0},
+ {0x40061, 0x0},
+ {0x40002, 0x0},
+ {0x40022, 0x0},
+ {0x40042, 0x0},
+ {0x40062, 0x0},
+ {0x40003, 0x0},
+ {0x40023, 0x0},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x0},
+ {0x40024, 0x0},
+ {0x40044, 0x0},
+ {0x40064, 0x0},
+ {0x40005, 0x0},
+ {0x40025, 0x0},
+ {0x40045, 0x0},
+ {0x40065, 0x0},
+ {0x40006, 0x0},
+ {0x40026, 0x0},
+ {0x40046, 0x0},
+ {0x40066, 0x0},
+ {0x40007, 0x0},
+ {0x40027, 0x0},
+ {0x40047, 0x0},
+ {0x40067, 0x0},
+ {0x40008, 0x0},
+ {0x40028, 0x0},
+ {0x40048, 0x0},
+ {0x40068, 0x0},
+ {0x40009, 0x0},
+ {0x40029, 0x0},
+ {0x40049, 0x0},
+ {0x40069, 0x0},
+ {0x4000a, 0x0},
+ {0x4002a, 0x0},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x0},
+ {0x4002b, 0x0},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x0},
+ {0x4002c, 0x0},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0x0},
+ {0x4002d, 0x0},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x0},
+ {0x4002e, 0x0},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x0},
+ {0x4002f, 0x0},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x0},
+ {0x40030, 0x0},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x0},
+ {0x40031, 0x0},
+ {0x40051, 0x0},
+ {0x40071, 0x0},
+ {0x40012, 0x0},
+ {0x40032, 0x0},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x0},
+ {0x40033, 0x0},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x0},
+ {0x40034, 0x0},
+ {0x40054, 0x0},
+ {0x40074, 0x0},
+ {0x40015, 0x0},
+ {0x40035, 0x0},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x0},
+ {0x40036, 0x0},
+ {0x40056, 0x0},
+ {0x40076, 0x0},
+ {0x40017, 0x0},
+ {0x40037, 0x0},
+ {0x40057, 0x0},
+ {0x40077, 0x0},
+ {0x40018, 0x0},
+ {0x40038, 0x0},
+ {0x40058, 0x0},
+ {0x40078, 0x0},
+ {0x40019, 0x0},
+ {0x40039, 0x0},
+ {0x40059, 0x0},
+ {0x40079, 0x0},
+ {0x4001a, 0x0},
+ {0x4003a, 0x0},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x0},
+ {0x900ac, 0x0},
+ {0x900ad, 0x0},
+ {0x900ae, 0x0},
+ {0x900af, 0x0},
+ {0x900b0, 0x0},
+ {0x900b1, 0x0},
+ {0x900b2, 0x0},
+ {0x900b3, 0x0},
+ {0x900b4, 0x0},
+ {0x900b5, 0x0},
+ {0x900b6, 0x0},
+ {0x900b7, 0x0},
+ {0x900b8, 0x0},
+ {0x900b9, 0x0},
+ {0x900ba, 0x0},
+ {0x900bb, 0x0},
+ {0x900bc, 0x0},
+ {0x900bd, 0x0},
+ {0x900be, 0x0},
+ {0x900bf, 0x0},
+ {0x900c0, 0x0},
+ {0x900c1, 0x0},
+ {0x900c2, 0x0},
+ {0x900c3, 0x0},
+ {0x900c4, 0x0},
+ {0x900c5, 0x0},
+ {0x900c6, 0x0},
+ {0x900c7, 0x0},
+ {0x900c8, 0x0},
+ {0x900c9, 0x0},
+ {0x900ca, 0x0},
+ {0x900cb, 0x0},
+ {0x900cc, 0x0},
+ {0x900cd, 0x0},
+ {0x900ce, 0x0},
+ {0x900cf, 0x0},
+ {0x900d0, 0x0},
+ {0x900d1, 0x0},
+ {0x900d2, 0x0},
+ {0x900d3, 0x0},
+ {0x900d4, 0x0},
+ {0x900d5, 0x0},
+ {0x900d6, 0x0},
+ {0x900d7, 0x0},
+ {0x900d8, 0x0},
+ {0x900d9, 0x0},
+ {0x900da, 0x0},
+ {0x900db, 0x0},
+ {0x900dc, 0x0},
+ {0x900dd, 0x0},
+ {0x900de, 0x0},
+ {0x900df, 0x0},
+ {0x900e0, 0x0},
+ {0x900e1, 0x0},
+ {0x900e2, 0x0},
+ {0x900e3, 0x0},
+ {0x900e4, 0x0},
+ {0x900e5, 0x0},
+ {0x900e6, 0x0},
+ {0x900e7, 0x0},
+ {0x900e8, 0x0},
+ {0x900e9, 0x0},
+ {0x900ea, 0x0},
+ {0x900eb, 0x0},
+ {0x900ec, 0x0},
+ {0x900ed, 0x0},
+ {0x900ee, 0x0},
+ {0x900ef, 0x0},
+ {0x900f0, 0x0},
+ {0x900f1, 0x0},
+ {0x900f2, 0x0},
+ {0x900f3, 0x0},
+ {0x900f4, 0x0},
+ {0x900f5, 0x0},
+ {0x900f6, 0x0},
+ {0x900f7, 0x0},
+ {0x900f8, 0x0},
+ {0x900f9, 0x0},
+ {0x900fa, 0x0},
+ {0x900fb, 0x0},
+ {0x900fc, 0x0},
+ {0x900fd, 0x0},
+ {0x900fe, 0x0},
+ {0x900ff, 0x0},
+ {0x90100, 0x0},
+ {0x90101, 0x0},
+ {0x90102, 0x0},
+ {0x90103, 0x0},
+ {0x90104, 0x0},
+ {0x90105, 0x0},
+ {0x90106, 0x0},
+ {0x90107, 0x0},
+ {0x90108, 0x0},
+ {0x90109, 0x0},
+ {0x9010a, 0x0},
+ {0x9010b, 0x0},
+ {0x9010c, 0x0},
+ {0x9010d, 0x0},
+ {0x9010e, 0x0},
+ {0x9010f, 0x0},
+ {0x90110, 0x0},
+ {0x90111, 0x0},
+ {0x90112, 0x0},
+ {0x90113, 0x0},
+ {0x90114, 0x0},
+ {0x90115, 0x0},
+ {0x90116, 0x0},
+ {0x90117, 0x0},
+ {0x90118, 0x0},
+ {0x90119, 0x0},
+ {0x9011a, 0x0},
+ {0x9011b, 0x0},
+ {0x9011c, 0x0},
+ {0x9011d, 0x0},
+ {0x9011e, 0x0},
+ {0x9011f, 0x0},
+ {0x90120, 0x0},
+ {0x90121, 0x0},
+ {0x90122, 0x0},
+ {0x90123, 0x0},
+ {0x90124, 0x0},
+ {0x90125, 0x0},
+ {0x90126, 0x0},
+ {0x90127, 0x0},
+ {0x90128, 0x0},
+ {0x90129, 0x0},
+ {0x9012a, 0x0},
+ {0x9012b, 0x0},
+ {0x9012c, 0x0},
+ {0x9012d, 0x0},
+ {0x9012e, 0x0},
+ {0x9012f, 0x0},
+ {0x90130, 0x0},
+ {0x90131, 0x0},
+ {0x90132, 0x0},
+ {0x90133, 0x0},
+ {0x90134, 0x0},
+ {0x90135, 0x0},
+ {0x90136, 0x0},
+ {0x90137, 0x0},
+ {0x90138, 0x0},
+ {0x90139, 0x0},
+ {0x9013a, 0x0},
+ {0x9013b, 0x0},
+ {0x9013c, 0x0},
+ {0x9013d, 0x0},
+ {0x9013e, 0x0},
+ {0x9013f, 0x0},
+ {0x90140, 0x0},
+ {0x90141, 0x0},
+ {0x90142, 0x0},
+ {0x90143, 0x0},
+ {0x90144, 0x0},
+ {0x90145, 0x0},
+ {0x90146, 0x0},
+ {0x90147, 0x0},
+ {0x90148, 0x0},
+ {0x90149, 0x0},
+ {0x9014a, 0x0},
+ {0x9014b, 0x0},
+ {0x9014c, 0x0},
+ {0x9014d, 0x0},
+ {0x9014e, 0x0},
+ {0x9014f, 0x0},
+ {0x90150, 0x0},
+ {0x90151, 0x0},
+ {0x90152, 0x0},
+ {0x90153, 0x0},
+ {0x90154, 0x0},
+ {0x90155, 0x0},
+ {0x90156, 0x0},
+ {0x90157, 0x0},
+ {0x90158, 0x0},
+ {0x90159, 0x0},
+ {0x9015a, 0x0},
+ {0x9015b, 0x0},
+ {0x9015c, 0x0},
+ {0x9015d, 0x0},
+ {0x9015e, 0x0},
+ {0x9015f, 0x0},
+ {0x90160, 0x0},
+ {0x90161, 0x0},
+ {0x90162, 0x0},
+ {0x90163, 0x0},
+ {0x90164, 0x0},
+ {0x90165, 0x0},
+ {0x90166, 0x0},
+ {0x90167, 0x0},
+ {0x90168, 0x0},
+ {0x90169, 0x0},
+ {0x9016a, 0x0},
+ {0x9016b, 0x0},
+ {0x9016c, 0x0},
+ {0x9016d, 0x0},
+ {0x9016e, 0x0},
+ {0x9016f, 0x0},
+ {0x90170, 0x0},
+ {0x90171, 0x0},
+ {0x90172, 0x0},
+ {0x90173, 0x0},
+ {0x90174, 0x0},
+ {0x90175, 0x0},
+ {0x90176, 0x0},
+ {0x90177, 0x0},
+ {0x90178, 0x0},
+ {0x90179, 0x0},
+ {0x9017a, 0x0},
+ {0x9017b, 0x0},
+ {0x9017c, 0x0},
+ {0x9017d, 0x0},
+ {0x9017e, 0x0},
+ {0x9017f, 0x0},
+ {0x90180, 0x0},
+ {0x90181, 0x0},
+ {0x90182, 0x0},
+ {0x90183, 0x0},
+ {0x90184, 0x0},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x0},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x0},
+ {0x90017, 0x0},
+ {0x9001f, 0x0},
+ {0x90026, 0x0},
+ {0x400d0, 0x0},
+ {0x400d1, 0x0},
+ {0x400d2, 0x0},
+ {0x400d3, 0x0},
+ {0x400d4, 0x0},
+ {0x400d5, 0x0},
+ {0x400d6, 0x0},
+ {0x400d7, 0x0},
+ {0x200be, 0x0},
+ {0x2000b, 0x0},
+ {0x2000c, 0x0},
+ {0x2000d, 0x0},
+ {0x2000e, 0x0},
+ {0x12000b, 0x0},
+ {0x12000c, 0x0},
+ {0x12000d, 0x0},
+ {0x12000e, 0x0},
+ {0x22000b, 0x0},
+ {0x22000c, 0x0},
+ {0x22000d, 0x0},
+ {0x22000e, 0x0},
+ {0x9000c, 0x0},
+ {0x9000d, 0x0},
+ {0x9000e, 0x0},
+ {0x9000f, 0x0},
+ {0x90010, 0x0},
+ {0x90011, 0x0},
+ {0x90012, 0x0},
+ {0x90013, 0x0},
+ {0x20010, 0x0},
+ {0x20011, 0x0},
+ {0x120010, 0x0},
+ {0x120011, 0x0},
+ {0x40080, 0x0},
+ {0x40081, 0x0},
+ {0x40082, 0x0},
+ {0x40083, 0x0},
+ {0x40084, 0x0},
+ {0x40085, 0x0},
+ {0x140080, 0x0},
+ {0x140081, 0x0},
+ {0x140082, 0x0},
+ {0x140083, 0x0},
+ {0x140084, 0x0},
+ {0x140085, 0x0},
+ {0x240080, 0x0},
+ {0x240081, 0x0},
+ {0x240082, 0x0},
+ {0x240083, 0x0},
+ {0x240084, 0x0},
+ {0x240085, 0x0},
+ {0x400fd, 0x0},
+ {0x400f1, 0x0},
+ {0x10011, 0x0},
+ {0x10012, 0x0},
+ {0x10013, 0x0},
+ {0x10018, 0x0},
+ {0x10002, 0x0},
+ {0x100b2, 0x0},
+ {0x101b4, 0x0},
+ {0x102b4, 0x0},
+ {0x103b4, 0x0},
+ {0x104b4, 0x0},
+ {0x105b4, 0x0},
+ {0x106b4, 0x0},
+ {0x107b4, 0x0},
+ {0x108b4, 0x0},
+ {0x11011, 0x0},
+ {0x11012, 0x0},
+ {0x11013, 0x0},
+ {0x11018, 0x0},
+ {0x11002, 0x0},
+ {0x110b2, 0x0},
+ {0x111b4, 0x0},
+ {0x112b4, 0x0},
+ {0x113b4, 0x0},
+ {0x114b4, 0x0},
+ {0x115b4, 0x0},
+ {0x116b4, 0x0},
+ {0x117b4, 0x0},
+ {0x118b4, 0x0},
+ {0x20089, 0x0},
+ {0xc0080, 0x0},
+ {0x200cb, 0x0},
+ {0x10068, 0x0},
+ {0x10069, 0x0},
+ {0x10168, 0x0},
+ {0x10169, 0x0},
+ {0x10268, 0x0},
+ {0x10269, 0x0},
+ {0x10368, 0x0},
+ {0x10369, 0x0},
+ {0x10468, 0x0},
+ {0x10469, 0x0},
+ {0x10568, 0x0},
+ {0x10569, 0x0},
+ {0x10668, 0x0},
+ {0x10669, 0x0},
+ {0x10768, 0x0},
+ {0x10769, 0x0},
+ {0x10868, 0x0},
+ {0x10869, 0x0},
+ {0x100aa, 0x0},
+ {0x10062, 0x0},
+ {0x10001, 0x0},
+ {0x100a0, 0x0},
+ {0x100a1, 0x0},
+ {0x100a2, 0x0},
+ {0x100a3, 0x0},
+ {0x100a4, 0x0},
+ {0x100a5, 0x0},
+ {0x100a6, 0x0},
+ {0x100a7, 0x0},
+ {0x11068, 0x0},
+ {0x11069, 0x0},
+ {0x11168, 0x0},
+ {0x11169, 0x0},
+ {0x11268, 0x0},
+ {0x11269, 0x0},
+ {0x11368, 0x0},
+ {0x11369, 0x0},
+ {0x11468, 0x0},
+ {0x11469, 0x0},
+ {0x11568, 0x0},
+ {0x11569, 0x0},
+ {0x11668, 0x0},
+ {0x11669, 0x0},
+ {0x11768, 0x0},
+ {0x11769, 0x0},
+ {0x11868, 0x0},
+ {0x11869, 0x0},
+ {0x110aa, 0x0},
+ {0x11062, 0x0},
+ {0x11001, 0x0},
+ {0x110a0, 0x0},
+ {0x110a1, 0x0},
+ {0x110a2, 0x0},
+ {0x110a3, 0x0},
+ {0x110a4, 0x0},
+ {0x110a5, 0x0},
+ {0x110a6, 0x0},
+ {0x110a7, 0x0},
+ {0x80, 0x0},
+ {0x1080, 0x0},
+ {0x2080, 0x0},
+ {0x10020, 0x0},
+ {0x10080, 0x0},
+ {0x10081, 0x0},
+ {0x100d0, 0x0},
+ {0x100d1, 0x0},
+ {0x1008c, 0x0},
+ {0x1008d, 0x0},
+ {0x10180, 0x0},
+ {0x10181, 0x0},
+ {0x101d0, 0x0},
+ {0x101d1, 0x0},
+ {0x1018c, 0x0},
+ {0x1018d, 0x0},
+ {0x100c0, 0x0},
+ {0x100c1, 0x0},
+ {0x101c0, 0x0},
+ {0x101c1, 0x0},
+ {0x102c0, 0x0},
+ {0x102c1, 0x0},
+ {0x103c0, 0x0},
+ {0x103c1, 0x0},
+ {0x104c0, 0x0},
+ {0x104c1, 0x0},
+ {0x105c0, 0x0},
+ {0x105c1, 0x0},
+ {0x106c0, 0x0},
+ {0x106c1, 0x0},
+ {0x107c0, 0x0},
+ {0x107c1, 0x0},
+ {0x108c0, 0x0},
+ {0x108c1, 0x0},
+ {0x100ae, 0x0},
+ {0x100af, 0x0},
+ {0x11020, 0x0},
+ {0x11080, 0x0},
+ {0x11081, 0x0},
+ {0x110d0, 0x0},
+ {0x110d1, 0x0},
+ {0x1108c, 0x0},
+ {0x1108d, 0x0},
+ {0x11180, 0x0},
+ {0x11181, 0x0},
+ {0x111d0, 0x0},
+ {0x111d1, 0x0},
+ {0x1118c, 0x0},
+ {0x1118d, 0x0},
+ {0x110c0, 0x0},
+ {0x110c1, 0x0},
+ {0x111c0, 0x0},
+ {0x111c1, 0x0},
+ {0x112c0, 0x0},
+ {0x112c1, 0x0},
+ {0x113c0, 0x0},
+ {0x113c1, 0x0},
+ {0x114c0, 0x0},
+ {0x114c1, 0x0},
+ {0x115c0, 0x0},
+ {0x115c1, 0x0},
+ {0x116c0, 0x0},
+ {0x116c1, 0x0},
+ {0x117c0, 0x0},
+ {0x117c1, 0x0},
+ {0x118c0, 0x0},
+ {0x118c1, 0x0},
+ {0x110ae, 0x0},
+ {0x110af, 0x0},
+ {0x90201, 0x0},
+ {0x90202, 0x0},
+ {0x90203, 0x0},
+ {0x90205, 0x0},
+ {0x90206, 0x0},
+ {0x90207, 0x0},
+ {0x90208, 0x0},
+ {0x20020, 0x0},
+ {0x100080, 0x0},
+ {0x101080, 0x0},
+ {0x102080, 0x0},
+ {0x110020, 0x0},
+ {0x110080, 0x0},
+ {0x110081, 0x0},
+ {0x1100d0, 0x0},
+ {0x1100d1, 0x0},
+ {0x11008c, 0x0},
+ {0x11008d, 0x0},
+ {0x110180, 0x0},
+ {0x110181, 0x0},
+ {0x1101d0, 0x0},
+ {0x1101d1, 0x0},
+ {0x11018c, 0x0},
+ {0x11018d, 0x0},
+ {0x1100c0, 0x0},
+ {0x1100c1, 0x0},
+ {0x1101c0, 0x0},
+ {0x1101c1, 0x0},
+ {0x1102c0, 0x0},
+ {0x1102c1, 0x0},
+ {0x1103c0, 0x0},
+ {0x1103c1, 0x0},
+ {0x1104c0, 0x0},
+ {0x1104c1, 0x0},
+ {0x1105c0, 0x0},
+ {0x1105c1, 0x0},
+ {0x1106c0, 0x0},
+ {0x1106c1, 0x0},
+ {0x1107c0, 0x0},
+ {0x1107c1, 0x0},
+ {0x1108c0, 0x0},
+ {0x1108c1, 0x0},
+ {0x1100ae, 0x0},
+ {0x1100af, 0x0},
+ {0x111020, 0x0},
+ {0x111080, 0x0},
+ {0x111081, 0x0},
+ {0x1110d0, 0x0},
+ {0x1110d1, 0x0},
+ {0x11108c, 0x0},
+ {0x11108d, 0x0},
+ {0x111180, 0x0},
+ {0x111181, 0x0},
+ {0x1111d0, 0x0},
+ {0x1111d1, 0x0},
+ {0x11118c, 0x0},
+ {0x11118d, 0x0},
+ {0x1110c0, 0x0},
+ {0x1110c1, 0x0},
+ {0x1111c0, 0x0},
+ {0x1111c1, 0x0},
+ {0x1112c0, 0x0},
+ {0x1112c1, 0x0},
+ {0x1113c0, 0x0},
+ {0x1113c1, 0x0},
+ {0x1114c0, 0x0},
+ {0x1114c1, 0x0},
+ {0x1115c0, 0x0},
+ {0x1115c1, 0x0},
+ {0x1116c0, 0x0},
+ {0x1116c1, 0x0},
+ {0x1117c0, 0x0},
+ {0x1117c1, 0x0},
+ {0x1118c0, 0x0},
+ {0x1118c1, 0x0},
+ {0x1110ae, 0x0},
+ {0x1110af, 0x0},
+ {0x190201, 0x0},
+ {0x190202, 0x0},
+ {0x190203, 0x0},
+ {0x190205, 0x0},
+ {0x190206, 0x0},
+ {0x190207, 0x0},
+ {0x190208, 0x0},
+ {0x120020, 0x0},
+ {0x200080, 0x0},
+ {0x201080, 0x0},
+ {0x202080, 0x0},
+ {0x210020, 0x0},
+ {0x210080, 0x0},
+ {0x210081, 0x0},
+ {0x2100d0, 0x0},
+ {0x2100d1, 0x0},
+ {0x21008c, 0x0},
+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
+ {0x20077, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
+ {0x400c0, 0x0},
+ {0x10040, 0x0},
+ {0x10140, 0x0},
+ {0x10240, 0x0},
+ {0x10340, 0x0},
+ {0x10440, 0x0},
+ {0x10540, 0x0},
+ {0x10640, 0x0},
+ {0x10740, 0x0},
+ {0x10840, 0x0},
+ {0x11040, 0x0},
+ {0x11140, 0x0},
+ {0x11240, 0x0},
+ {0x11340, 0x0},
+ {0x11440, 0x0},
+ {0x11540, 0x0},
+ {0x11640, 0x0},
+ {0x11740, 0x0},
+ {0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x960},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x24c4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x24c4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xc400},
+ {0x54033, 0x3324},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xc400},
+ {0x54039, 0x3324},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x4b0},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x52a4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x52a4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xa400},
+ {0x54033, 0x3352},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xa400},
+ {0x54039, 0x3352},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4800},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4800},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3309},
+ {0x54034, 0x4600},
+ {0x54035, 0x11},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3309},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x11},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x960},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54010, 0x2080},
+ {0x54012, 0x110},
+ {0x54019, 0x24c4},
+ {0x5401a, 0x33},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x4808},
+ {0x5401e, 0x4},
+ {0x5401f, 0x24c4},
+ {0x54020, 0x33},
+ {0x54021, 0x1146},
+ {0x54022, 0x4808},
+ {0x54024, 0x4},
+ {0x54032, 0xc400},
+ {0x54033, 0x3324},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x48},
+ {0x54037, 0x400},
+ {0x54038, 0xc400},
+ {0x54039, 0x3324},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x48},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x30},
+ {0x90051, 0x65a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x45a},
+ {0x90055, 0x9},
+ {0x90056, 0x0},
+ {0x90057, 0x448},
+ {0x90058, 0x109},
+ {0x90059, 0x40},
+ {0x9005a, 0x633},
+ {0x9005b, 0x179},
+ {0x9005c, 0x1},
+ {0x9005d, 0x618},
+ {0x9005e, 0x109},
+ {0x9005f, 0x40c0},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x8},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x4040},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x0},
+ {0x90069, 0x4},
+ {0x9006a, 0x48},
+ {0x9006b, 0x40},
+ {0x9006c, 0x633},
+ {0x9006d, 0x149},
+ {0x9006e, 0x0},
+ {0x9006f, 0x658},
+ {0x90070, 0x109},
+ {0x90071, 0x10},
+ {0x90072, 0x4},
+ {0x90073, 0x18},
+ {0x90074, 0x0},
+ {0x90075, 0x4},
+ {0x90076, 0x78},
+ {0x90077, 0x549},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0xd49},
+ {0x9007b, 0x633},
+ {0x9007c, 0x159},
+ {0x9007d, 0x94a},
+ {0x9007e, 0x633},
+ {0x9007f, 0x159},
+ {0x90080, 0x441},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x42},
+ {0x90084, 0x633},
+ {0x90085, 0x149},
+ {0x90086, 0x1},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x0},
+ {0x9008a, 0xe0},
+ {0x9008b, 0x109},
+ {0x9008c, 0xa},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x9},
+ {0x90090, 0x3c0},
+ {0x90091, 0x149},
+ {0x90092, 0x9},
+ {0x90093, 0x3c0},
+ {0x90094, 0x159},
+ {0x90095, 0x18},
+ {0x90096, 0x10},
+ {0x90097, 0x109},
+ {0x90098, 0x0},
+ {0x90099, 0x3c0},
+ {0x9009a, 0x109},
+ {0x9009b, 0x18},
+ {0x9009c, 0x4},
+ {0x9009d, 0x48},
+ {0x9009e, 0x18},
+ {0x9009f, 0x4},
+ {0x900a0, 0x58},
+ {0x900a1, 0xb},
+ {0x900a2, 0x10},
+ {0x900a3, 0x109},
+ {0x900a4, 0x1},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x5},
+ {0x900a8, 0x7c0},
+ {0x900a9, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x790},
+ {0x900ac, 0x11a},
+ {0x900ad, 0x8},
+ {0x900ae, 0x7aa},
+ {0x900af, 0x2a},
+ {0x900b0, 0x10},
+ {0x900b1, 0x7b2},
+ {0x900b2, 0x2a},
+ {0x900b3, 0x0},
+ {0x900b4, 0x7c8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x10},
+ {0x900b7, 0x10},
+ {0x900b8, 0x109},
+ {0x900b9, 0x10},
+ {0x900ba, 0x2a8},
+ {0x900bb, 0x129},
+ {0x900bc, 0x8},
+ {0x900bd, 0x370},
+ {0x900be, 0x129},
+ {0x900bf, 0xa},
+ {0x900c0, 0x3c8},
+ {0x900c1, 0x1a9},
+ {0x900c2, 0xc},
+ {0x900c3, 0x408},
+ {0x900c4, 0x199},
+ {0x900c5, 0x14},
+ {0x900c6, 0x790},
+ {0x900c7, 0x11a},
+ {0x900c8, 0x8},
+ {0x900c9, 0x4},
+ {0x900ca, 0x18},
+ {0x900cb, 0xe},
+ {0x900cc, 0x408},
+ {0x900cd, 0x199},
+ {0x900ce, 0x8},
+ {0x900cf, 0x8568},
+ {0x900d0, 0x108},
+ {0x900d1, 0x18},
+ {0x900d2, 0x790},
+ {0x900d3, 0x16a},
+ {0x900d4, 0x8},
+ {0x900d5, 0x1d8},
+ {0x900d6, 0x169},
+ {0x900d7, 0x10},
+ {0x900d8, 0x8558},
+ {0x900d9, 0x168},
+ {0x900da, 0x1ff8},
+ {0x900db, 0x85a8},
+ {0x900dc, 0x1e8},
+ {0x900dd, 0x50},
+ {0x900de, 0x798},
+ {0x900df, 0x16a},
+ {0x900e0, 0x60},
+ {0x900e1, 0x7a0},
+ {0x900e2, 0x16a},
+ {0x900e3, 0x8},
+ {0x900e4, 0x8310},
+ {0x900e5, 0x168},
+ {0x900e6, 0x8},
+ {0x900e7, 0xa310},
+ {0x900e8, 0x168},
+ {0x900e9, 0xa},
+ {0x900ea, 0x408},
+ {0x900eb, 0x169},
+ {0x900ec, 0x6e},
+ {0x900ed, 0x0},
+ {0x900ee, 0x68},
+ {0x900ef, 0x0},
+ {0x900f0, 0x408},
+ {0x900f1, 0x169},
+ {0x900f2, 0x0},
+ {0x900f3, 0x8310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x0},
+ {0x900f6, 0xa310},
+ {0x900f7, 0x168},
+ {0x900f8, 0x1ff8},
+ {0x900f9, 0x85a8},
+ {0x900fa, 0x1e8},
+ {0x900fb, 0x68},
+ {0x900fc, 0x798},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x78},
+ {0x900ff, 0x7a0},
+ {0x90100, 0x16a},
+ {0x90101, 0x68},
+ {0x90102, 0x790},
+ {0x90103, 0x16a},
+ {0x90104, 0x8},
+ {0x90105, 0x8b10},
+ {0x90106, 0x168},
+ {0x90107, 0x8},
+ {0x90108, 0xab10},
+ {0x90109, 0x168},
+ {0x9010a, 0xa},
+ {0x9010b, 0x408},
+ {0x9010c, 0x169},
+ {0x9010d, 0x58},
+ {0x9010e, 0x0},
+ {0x9010f, 0x68},
+ {0x90110, 0x0},
+ {0x90111, 0x408},
+ {0x90112, 0x169},
+ {0x90113, 0x0},
+ {0x90114, 0x8b10},
+ {0x90115, 0x168},
+ {0x90116, 0x1},
+ {0x90117, 0xab10},
+ {0x90118, 0x168},
+ {0x90119, 0x0},
+ {0x9011a, 0x1d8},
+ {0x9011b, 0x169},
+ {0x9011c, 0x80},
+ {0x9011d, 0x790},
+ {0x9011e, 0x16a},
+ {0x9011f, 0x18},
+ {0x90120, 0x7aa},
+ {0x90121, 0x6a},
+ {0x90122, 0xa},
+ {0x90123, 0x0},
+ {0x90124, 0x1e9},
+ {0x90125, 0x8},
+ {0x90126, 0x8080},
+ {0x90127, 0x108},
+ {0x90128, 0xf},
+ {0x90129, 0x408},
+ {0x9012a, 0x169},
+ {0x9012b, 0xc},
+ {0x9012c, 0x0},
+ {0x9012d, 0x68},
+ {0x9012e, 0x9},
+ {0x9012f, 0x0},
+ {0x90130, 0x1a9},
+ {0x90131, 0x0},
+ {0x90132, 0x408},
+ {0x90133, 0x169},
+ {0x90134, 0x0},
+ {0x90135, 0x8080},
+ {0x90136, 0x108},
+ {0x90137, 0x8},
+ {0x90138, 0x7aa},
+ {0x90139, 0x6a},
+ {0x9013a, 0x0},
+ {0x9013b, 0x8568},
+ {0x9013c, 0x108},
+ {0x9013d, 0xb7},
+ {0x9013e, 0x790},
+ {0x9013f, 0x16a},
+ {0x90140, 0x1f},
+ {0x90141, 0x0},
+ {0x90142, 0x68},
+ {0x90143, 0x8},
+ {0x90144, 0x8558},
+ {0x90145, 0x168},
+ {0x90146, 0xf},
+ {0x90147, 0x408},
+ {0x90148, 0x169},
+ {0x90149, 0xd},
+ {0x9014a, 0x0},
+ {0x9014b, 0x68},
+ {0x9014c, 0x0},
+ {0x9014d, 0x408},
+ {0x9014e, 0x169},
+ {0x9014f, 0x0},
+ {0x90150, 0x8558},
+ {0x90151, 0x168},
+ {0x90152, 0x8},
+ {0x90153, 0x3c8},
+ {0x90154, 0x1a9},
+ {0x90155, 0x3},
+ {0x90156, 0x370},
+ {0x90157, 0x129},
+ {0x90158, 0x20},
+ {0x90159, 0x2aa},
+ {0x9015a, 0x9},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x104},
+ {0x90164, 0x8},
+ {0x90165, 0x448},
+ {0x90166, 0x109},
+ {0x90167, 0xf},
+ {0x90168, 0x7c0},
+ {0x90169, 0x109},
+ {0x9016a, 0x0},
+ {0x9016b, 0xe8},
+ {0x9016c, 0x109},
+ {0x9016d, 0x47},
+ {0x9016e, 0x630},
+ {0x9016f, 0x109},
+ {0x90170, 0x8},
+ {0x90171, 0x618},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0xe0},
+ {0x90175, 0x109},
+ {0x90176, 0x0},
+ {0x90177, 0x7c8},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0x8140},
+ {0x9017b, 0x10c},
+ {0x9017c, 0x0},
+ {0x9017d, 0x478},
+ {0x9017e, 0x109},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x0},
+ {0x90006, 0x8},
+ {0x90007, 0x7c8},
+ {0x90008, 0x109},
+ {0x90009, 0x0},
+ {0x9000a, 0x400},
+ {0x9000b, 0x106},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2b},
+ {0x90026, 0x69},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x200be, 0x3},
+ {0x2000b, 0x2a3},
+ {0x2000c, 0x96},
+ {0x2000d, 0x5dc},
+ {0x2000e, 0x2c},
+ {0x12000b, 0x152},
+ {0x12000c, 0x4b},
+ {0x12000d, 0x2ee},
+ {0x12000e, 0x2c},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x400f1, 0xe},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1200mts 1D */
+ .drate = 1200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 2400, 1200, 625, },
+ .fsp_cfg = ddr_dram_fsp_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx91_evk/spl.c b/board/freescale/imx91_evk/spl.c
new file mode 100644
index 0000000..46bde93
--- /dev/null
+++ b/board/freescale/imx91_evk/spl.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/mu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch-mx7ulp/gpio.h>
+#include <asm/mach-imx/ele_api.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <linux/delay.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <asm/arch/trdc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_board_init(void)
+{
+ int ret;
+
+ ret = ele_start_rng();
+ if (ret)
+ printf("Fail to start RNG: %d\n", ret);
+
+ puts("Normal Boot\n");
+}
+
+extern struct dram_timing_info dram_timing_1600mts;
+void spl_dram_init(void)
+{
+ struct dram_timing_info *ptiming = &dram_timing;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
+ ptiming = &dram_timing_1600mts;
+
+ printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate);
+ ddr_init(ptiming);
+}
+
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+ unsigned int val = 0, buck_val;
+
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("ERROR: Get PMIC PCA9451A failed!\n");
+ return ret;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* enable DVS control through PMIC_STBY_REQ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
+ if (ret < 0)
+ return ret;
+
+ val = ret;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ buck_val = 0x0c; /* 0.8V for Low drive mode */
+ printf("PMIC: Low Drive Voltage Mode\n");
+ } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
+ buck_val = 0x10; /* 0.85V for Nominal drive mode */
+ printf("PMIC: Nominal Voltage Mode\n");
+ } else {
+ buck_val = 0x14; /* 0.9V for Over drive mode */
+ printf("PMIC: Over Drive Voltage Mode\n");
+ }
+
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
+ } else {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
+ }
+
+ /* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
+
+ /* set standby voltage to 0.65V */
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+
+ /* I2C_LT_EN*/
+ pmic_reg_write(dev, 0xa, 0x3);
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ timer_init();
+
+ arch_cpu_init();
+
+ spl_early_init();
+
+ preloader_console_init();
+
+ ret = imx9_probe_mu();
+ if (ret) {
+ printf("Fail to init ELE API\n");
+ } else {
+ debug("SOC: 0x%x\n", gd->arch.soc_rev);
+ debug("LC: 0x%x\n", gd->arch.lifecycle);
+ }
+
+ clock_init_late();
+
+ power_init_board();
+
+ if (!is_voltage_mode(VOLT_LOW_DRIVE))
+ set_arm_clk(get_cpu_speed_grade_hz());
+
+ /* Init power of mix */
+ soc_power_init();
+
+ /* Setup TRDC for DDR access */
+ trdc_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
old mode 100755
new mode 100644
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 3443dc9..db96534 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -151,8 +151,8 @@
return -ENOSYS;
switch (id) {
- case SYSINFO_ID_SMBIOS_SYSTEM_VERSION:
- case SYSINFO_ID_SMBIOS_BASEBOARD_VERSION: {
+ case SYSID_SM_SYSTEM_VERSION:
+ case SYSID_SM_BASEBOARD_VERSION: {
ret = get_skuconfig(dev);
if (ret < 0)
@@ -162,7 +162,7 @@
sprintf(val, "rev%d", ret);
break;
}
- case SYSINFO_ID_BOARD_MODEL: {
+ case SYSID_BOARD_MODEL: {
int mem_config, sku_config;
const char *model;
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index f394ace..bc55117 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -19,6 +19,14 @@
Support of I2C EEPROM based SoM detection. Supported
for PHYTEC i.MX8MM/i.MX8MP boards
+config PHYTEC_IMX93_SOM_DETECTION
+ bool "Support SoM detection for i.MX93 PHYTEC platforms"
+ depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION
+ default y
+ help
+ Support of I2C EEPROM based SoM detection. Supported
+ for PHYTEC i.MX93 based boards
+
config PHYTEC_AM62_SOM_DETECTION
bool "Support SoM detection for AM62x PHYTEC platforms"
depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
index cd78f76..8126f73 100644
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -10,3 +10,4 @@
obj-y += phytec_som_detection.o phytec_som_detection_blocks.o
obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/
obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
+obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o
diff --git a/board/phytec/common/imx93_som_detection.c b/board/phytec/common/imx93_som_detection.c
new file mode 100644
index 0000000..eb9574d
--- /dev/null
+++ b/board/phytec/common/imx93_som_detection.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ */
+
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <i2c.h>
+#include <u-boot/crc.h>
+
+#include "imx93_som_detection.h"
+
+extern struct phytec_eeprom_data eeprom_data;
+
+#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION)
+
+/* Check if the SoM is actually one of the following products:
+ * - i.MX93
+ *
+ * Returns 0 in case it's a known SoM. Otherwise, returns 1.
+ */
+u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+{
+ u8 som;
+
+ if (!data)
+ data = &eeprom_data;
+
+ /* Early API revisions are not supported */
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+ return 1;
+
+ som = data->payload.data.data_api2.som_no;
+ debug("%s: som id: %u\n", __func__, som);
+
+ if (som == PHYTEC_IMX93_SOM && is_imx93())
+ return 0;
+
+ pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__);
+ return 1;
+}
+
+/*
+ * Filter PHYTEC i.MX93 SoM options by option index
+ *
+ * Returns:
+ * - option value
+ * - PHYTEC_EEPROM_INVAL when the data is invalid
+ *
+ */
+u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+ enum phytec_imx93_option_index idx)
+{
+ char *opt;
+ u8 opt_id;
+
+ if (!data)
+ data = &eeprom_data;
+
+ if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+ return PHYTEC_EEPROM_INVAL;
+
+ opt = phytec_get_opt(data);
+ if (opt)
+ opt_id = PHYTEC_GET_OPTION(opt[idx]);
+ else
+ opt_id = PHYTEC_EEPROM_INVAL;
+
+ debug("%s: opt[%d] id: %u\n", __func__, idx, opt_id);
+ return opt_id;
+}
+
+/*
+ * Filter PHYTEC i.MX93 SoM voltage
+ *
+ * Returns:
+ * - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3
+ * - PHYTEC_EEPROM_INVAL when the data is invalid
+ *
+ */
+enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data)
+{
+ u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT);
+
+ if (option == PHYTEC_EEPROM_INVAL)
+ return PHYTEC_IMX93_VOLTAGE_INVALID;
+ return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3;
+}
+
+#else
+
+inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+{
+ return 1;
+}
+
+inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+ enum phytec_imx93_option_index idx)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
+ (struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */
diff --git a/board/phytec/common/imx93_som_detection.h b/board/phytec/common/imx93_som_detection.h
new file mode 100644
index 0000000..a0803b4
--- /dev/null
+++ b/board/phytec/common/imx93_som_detection.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ */
+
+#ifndef _PHYTEC_IMX93_SOM_DETECTION_H
+#define _PHYTEC_IMX93_SOM_DETECTION_H
+
+#include "phytec_som_detection.h"
+
+#define PHYTEC_IMX93_SOM 77
+
+enum phytec_imx93_option_index {
+ PHYTEC_IMX93_OPT_DDR = 0,
+ PHYTEC_IMX93_OPT_EMMC = 1,
+ PHYTEC_IMX93_OPT_CPU = 2,
+ PHYTEC_IMX93_OPT_FREQ = 3,
+ PHYTEC_IMX93_OPT_NPU = 4,
+ PHYTEC_IMX93_OPT_DISP = 5,
+ PHYTEC_IMX93_OPT_ETH = 6,
+ PHYTEC_IMX93_OPT_FEAT = 7,
+ PHYTEC_IMX93_OPT_TEMP = 8,
+ PHYTEC_IMX93_OPT_BOOT = 9,
+ PHYTEC_IMX93_OPT_LED = 10,
+ PHYTEC_IMX93_OPT_EEPROM = 11,
+};
+
+enum phytec_imx93_voltage {
+ PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL,
+ PHYTEC_IMX93_VOLTAGE_3V3 = 0,
+ PHYTEC_IMX93_VOLTAGE_1V8 = 1,
+};
+
+enum phytec_imx93_ddr_eeprom_code {
+ PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL,
+ PHYTEC_IMX93_LPDDR4X_512MB = 0,
+ PHYTEC_IMX93_LPDDR4X_1GB = 1,
+ PHYTEC_IMX93_LPDDR4X_2GB = 2,
+ PHYTEC_IMX93_LPDDR4_512MB = 3,
+ PHYTEC_IMX93_LPDDR4_1GB = 4,
+ PHYTEC_IMX93_LPDDR4_2GB = 5,
+};
+
+u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+ enum phytec_imx93_option_index idx);
+enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
+ (struct phytec_eeprom_data *data);
+
+#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */
diff --git a/board/phytec/common/k3/Kconfig b/board/phytec/common/k3/Kconfig
new file mode 100644
index 0000000..282f4b7
--- /dev/null
+++ b/board/phytec/common/k3/Kconfig
@@ -0,0 +1,5 @@
+config PHYTEC_K3_DDR_PATCH
+ bool "Patch DDR timings on PHYTEC K3 SoMs"
+ help
+ Allow to override default DDR timings prior to
+ DDRSS driver probing.
diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile
index 40e91a4..6861c70 100644
--- a/board/phytec/common/k3/Makefile
+++ b/board/phytec/common/k3/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += board.o
-obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o
+obj-$(CONFIG_PHYTEC_K3_DDR_PATCH) += k3_ddrss_patch.o
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index 346b2b6..9ff861c 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -4,15 +4,92 @@
* Author: Wadim Egorov <w.egorov@phytec.de>
*/
+#include <efi_loader.h>
#include <env_internal.h>
#include <fdt_support.h>
#include <dm/ofnode.h>
+#include <mtd.h>
#include <spl.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
#include "../am6_som_detection.h"
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_image fw_images[] = {
+ {
+ .fw_name = PHYCORE_AM6XX_FW_NAME_TIBOOT3,
+ .image_index = 1,
+ },
+ {
+ .fw_name = PHYCORE_AM6XX_FW_NAME_SPL,
+ .image_index = 2,
+ },
+ {
+ .fw_name = PHYCORE_AM6XX_FW_NAME_UBOOT,
+ .image_index = 3,
+ }
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = NULL,
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
+/**
+ * configure_capsule_updates() - Set up the DFU string for capsule updates
+ *
+ * Configures all three bootloader binaries for updates on the current
+ * booted flash device, which may be eMMC, OSPI NOR, or a uSD card. If
+ * booting from USB or Serial, capsule updates will be performed on the
+ * eMMC device.
+ *
+ * Note: Currently, eMMC hardware partitions are not differentiated; Updates
+ * are always applied to the first boot partition.
+ */
+void configure_capsule_updates(void)
+{
+ static char dfu_string[128] = { 0 };
+ const char *dfu_raw = "tiboot3.bin raw 0x0 0x400 mmcpart 1;"
+ "tispl.bin raw 0x400 0x1000 mmcpart 1;"
+ "u-boot.img.raw raw 0x1400 0x2000 mmcpart 1";
+ const char *dfu_fat = "tiboot3.bin fat 1 1;"
+ "tispl.bin fat 1 1;"
+ "u-boot.img fat 1 1";
+ const char *dfu_spi = "tiboot3.bin part 1;"
+ "tispl.bin part 2;"
+ "u-boot.img part 3";
+ u32 boot_device = get_boot_device();
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ snprintf(dfu_string, 128, "mmc 0=%s", dfu_raw);
+ break;
+ case BOOT_DEVICE_MMC2:
+ snprintf(dfu_string, 128, "mmc 1=%s", dfu_fat);
+ break;
+ case BOOT_DEVICE_SPI:
+ mtd_probe_devices();
+ snprintf(dfu_string, 128, "mtd nor0=%s", dfu_spi);
+ break;
+ default:
+ snprintf(dfu_string, 128, "mmc 0=%s", dfu_raw);
+ break;
+ };
+
+ update_info.dfu_string = dfu_string;
+}
+#endif
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
int mmc_get_env_dev(void)
{
@@ -94,6 +171,10 @@
}
}
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+ configure_capsule_updates();
+#endif
+
return 0;
}
#endif
diff --git a/board/phytec/phycore_am62ax/Kconfig b/board/phytec/phycore_am62ax/Kconfig
new file mode 100644
index 0000000..516dc8e
--- /dev/null
+++ b/board/phytec/phycore_am62ax/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+#
+# Copyright (C) 2024 PHYTEC America LLC
+# Author: Garrett Giordano <ggiordano@phytec.com>
+
+if TARGET_PHYCORE_AM62AX_A53
+
+config SYS_BOARD
+ default "phycore_am62ax"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_CONFIG_NAME
+ default "phycore_am62ax"
+
+source "board/phytec/common/Kconfig"
+
+endif
+
+if TARGET_PHYCORE_AM62AX_R5
+
+config SYS_BOARD
+ default "phycore_am62ax"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_CONFIG_NAME
+ default "phycore_am62ax"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/phytec/common/Kconfig"
+
+endif
diff --git a/board/phytec/phycore_am62ax/MAINTAINERS b/board/phytec/phycore_am62ax/MAINTAINERS
new file mode 100644
index 0000000..3e4e2fe
--- /dev/null
+++ b/board/phytec/phycore_am62ax/MAINTAINERS
@@ -0,0 +1,14 @@
+phyCORE-AM62ax
+M: Garrett Giordano <ggiordano@phytec.com>
+M: Wadim Egorov <w.egorov@phytec.de>
+W: https://www.phytec.com/product/phycore-am62a
+S: Maintained
+F: arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
+F: arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsit.dtsi
+F: arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
+F: arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
+F: board/phytec/phycore_am62ax/
+F: configs/phycore_am62ax_a53_defconfig
+F: configs/phycore_am62ax_r5_defconfig
+F: include/configs/phycore_am62ax.h
+F: doc/board/phytec/phycore-am62ax.rst
diff --git a/board/phytec/phycore_am62ax/Makefile b/board/phytec/phycore_am62ax/Makefile
new file mode 100644
index 0000000..61e7c92
--- /dev/null
+++ b/board/phytec/phycore_am62ax/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+#
+# Copyright (C) 2024 PHYTEC America LLC
+# Author: Garrett Giordano <ggiordano@phytec.com>
+
+obj-y += phycore-am62ax.o
diff --git a/board/phytec/phycore_am62ax/board-cfg.yaml b/board/phytec/phycore_am62ax/board-cfg.yaml
new file mode 100644
index 0000000..a0930d6
--- /dev/null
+++ b/board/phytec/phycore_am62ax/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62ax
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable: 0x5A
+ main_isolation_hostid: 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor: 0x1
+ scaling_profile: 0x1
+ disable_main_nav_secure_proxy: 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size: 0x10
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables: 0x00
+ trace_src_enables: 0x00
diff --git a/board/phytec/phycore_am62ax/phycore-am62ax.c b/board/phytec/phycore_am62ax/phycore-am62ax.c
new file mode 100644
index 0000000..14b8959
--- /dev/null
+++ b/board/phytec/phycore_am62ax/phycore-am62ax.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <fdt_support.h>
+
+#include "../common/am6_som_detection.h"
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#define CTRLMMR_USB0_PHY_CTRL 0x43004008
+#define CTRLMMR_USB1_PHY_CTRL 0x43004018
+#define CORE_VOLTAGE 0x80000000
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+ u32 val;
+
+ /* Set USB0 PHY core voltage to 0.85V */
+ val = readl(CTRLMMR_USB0_PHY_CTRL);
+ val &= ~(CORE_VOLTAGE);
+ writel(val, CTRLMMR_USB0_PHY_CTRL);
+
+ /* Set USB1 PHY core voltage to 0.85V */
+ val = readl(CTRLMMR_USB1_PHY_CTRL);
+ val &= ~(CORE_VOLTAGE);
+ writel(val, CTRLMMR_USB1_PHY_CTRL);
+
+ if (IS_ENABLED(CONFIG_SPL_ETH))
+ /* Init DRAM size for R5/A53 SPL */
+ dram_init_banksize();
+
+ /* We have 32k crystal, so lets enable it */
+ val = readl(MCU_CTRL_LFXOSC_CTRL);
+ val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL);
+ writel(val, MCU_CTRL_LFXOSC_CTRL);
+ /* Add any TRIM needed for the crystal here.. */
+ /* Make sure to mux up to take the SoC 32k from the crystal */
+ writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
+ MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
+
+ /* Init DRAM size for R5/A53 SPL */
+ dram_init_banksize();
+}
+#endif
diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env
new file mode 100644
index 0000000..77c5ea8
--- /dev/null
+++ b/board/phytec/phycore_am62ax/phycore_am62ax.env
@@ -0,0 +1,14 @@
+fdtaddr=0x88000000
+loadaddr=0x82000000
+scriptaddr=0x80000000
+fdt_addr_r=0x88000000
+kernel_addr_r=0x82000000
+ramdisk_addr_r=0x88080000
+fdtoverlay_addr_r=0x89000000
+
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+mmcdev=1
+mmcroot=2
+mmcpart=1
+console=ttyS2,115200n8
+earlycon=ns16550a,mmio32,0x02800000
diff --git a/board/phytec/phycore_am62ax/pm-cfg.yaml b/board/phytec/phycore_am62ax/pm-cfg.yaml
new file mode 100644
index 0000000..4031af2
--- /dev/null
+++ b/board/phytec/phycore_am62ax/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62ax
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
diff --git a/board/phytec/phycore_am62ax/rm-cfg.yaml b/board/phytec/phycore_am62ax/rm-cfg.yaml
new file mode 100644
index 0000000..cbd087d
--- /dev/null
+++ b/board/phytec/phycore_am62ax/rm-cfg.yaml
@@ -0,0 +1,1047 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62A
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ - # 1
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 2
+ host_id: 20
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 3
+ host_id: 30
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 4
+ host_id: 36
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 5
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 6
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 7
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 8
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 9
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 10
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 11
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 12
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 13
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 14
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 15
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 16
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 17
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 18
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 19
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 20
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 21
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 22
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 23
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 24
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 25
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 26
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 27
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 28
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 29
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 30
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 31
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 32
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 1064
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 64
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 22
+ type: 64
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 192
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 34
+ num_resource: 2
+ type: 192
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 320
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 320
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 320
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 320
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 26
+ type: 384
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 50176
+ num_resource: 164
+ type: 1666
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1667
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1677
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1677
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1677
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1677
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 6
+ type: 1677
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 18
+ type: 1678
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 72
+ num_resource: 6
+ type: 1678
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 72
+ num_resource: 6
+ type: 1678
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 78
+ num_resource: 2
+ type: 1678
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 2
+ type: 1678
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 12
+ type: 1679
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 50
+ num_resource: 2
+ type: 1679
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 2
+ type: 1679
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1696
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1696
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1696
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1696
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 6
+ type: 1696
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1697
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1697
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1697
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1697
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 2
+ type: 1697
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 12
+ type: 1698
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 2
+ type: 1698
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 2
+ type: 1698
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 6
+ num_resource: 26
+ type: 1802
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 8
+ type: 1802
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 35
+ type: 1802
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 35
+ type: 1802
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 168
+ num_resource: 8
+ type: 1802
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 512
+ type: 1805
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 526
+ num_resource: 256
+ type: 1805
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 526
+ num_resource: 256
+ type: 1805
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 782
+ num_resource: 128
+ type: 1805
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 910
+ num_resource: 128
+ type: 1805
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 1038
+ num_resource: 497
+ type: 1805
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1024
+ type: 1807
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 29
+ type: 1808
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4608
+ num_resource: 99
+ type: 1809
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5120
+ num_resource: 24
+ type: 1810
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5632
+ num_resource: 51
+ type: 1811
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 6144
+ num_resource: 51
+ type: 1812
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 6656
+ num_resource: 51
+ type: 1813
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8192
+ num_resource: 32
+ type: 1814
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8704
+ num_resource: 32
+ type: 1815
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9216
+ num_resource: 32
+ type: 1816
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9728
+ num_resource: 22
+ type: 1817
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10240
+ num_resource: 22
+ type: 1818
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10752
+ num_resource: 22
+ type: 1819
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11264
+ num_resource: 28
+ type: 1820
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11776
+ num_resource: 28
+ type: 1821
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 12288
+ num_resource: 28
+ type: 1822
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1923
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1936
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1936
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1936
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 8
+ type: 1938
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 91
+ num_resource: 8
+ type: 1939
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 99
+ num_resource: 10
+ type: 1942
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 112
+ num_resource: 3
+ type: 1942
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 3
+ type: 1942
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1944
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1945
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1946
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1947
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1955
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1955
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1955
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 1
+ type: 1957
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 1958
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1961
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1961
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1961
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1962
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1962
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1962
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 1965
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1966
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 1
+ type: 1967
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1968
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 1
+ type: 1969
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1970
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 1
+ type: 1971
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1972
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 2112
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 2122
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 51200
+ num_resource: 12
+ type: 12738
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 12739
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 6
+ type: 12750
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 6
+ type: 12769
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12810
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 12288
+ num_resource: 128
+ type: 12813
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3072
+ num_resource: 6
+ type: 12828
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3584
+ num_resource: 6
+ type: 12829
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 6
+ type: 12830
+ host_id: 128
+ reserved: 0
diff --git a/board/phytec/phycore_am62ax/sec-cfg.yaml b/board/phytec/phycore_am62ax/sec-cfg.yaml
new file mode 100644
index 0000000..ae6939e
--- /dev/null
+++ b/board/phytec/phycore_am62ax/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security configuration for AM62ax
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ - # 1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - # 1
+ host_id: 0
+ supervisor_host_id: 0
+ - # 2
+ host_id: 0
+ supervisor_host_id: 0
+ - # 3
+ host_id: 0
+ supervisor_host_id: 0
+ - # 4
+ host_id: 0
+ supervisor_host_id: 0
+ - # 5
+ host_id: 0
+ supervisor_host_id: 0
+ - # 6
+ host_id: 0
+ supervisor_host_id: 0
+ - # 7
+ host_id: 0
+ supervisor_host_id: 0
+ - # 8
+ host_id: 0
+ supervisor_host_id: 0
+ - # 9
+ host_id: 0
+ supervisor_host_id: 0
+ - # 10
+ host_id: 0
+ supervisor_host_id: 0
+ - # 11
+ host_id: 0
+ supervisor_host_id: 0
+ - # 12
+ host_id: 0
+ supervisor_host_id: 0
+ - # 13
+ host_id: 0
+ supervisor_host_id: 0
+ - # 14
+ host_id: 0
+ supervisor_host_id: 0
+ - # 15
+ host_id: 0
+ supervisor_host_id: 0
+ - # 16
+ host_id: 0
+ supervisor_host_id: 0
+ - # 17
+ host_id: 0
+ supervisor_host_id: 0
+ - # 18
+ host_id: 0
+ supervisor_host_id: 0
+ - # 19
+ host_id: 0
+ supervisor_host_id: 0
+ - # 20
+ host_id: 0
+ supervisor_host_id: 0
+ - # 21
+ host_id: 0
+ supervisor_host_id: 0
+ - # 22
+ host_id: 0
+ supervisor_host_id: 0
+ - # 23
+ host_id: 0
+ supervisor_host_id: 0
+ - # 24
+ host_id: 0
+ supervisor_host_id: 0
+ - # 25
+ host_id: 0
+ supervisor_host_id: 0
+ - # 26
+ host_id: 0
+ supervisor_host_id: 0
+ - # 27
+ host_id: 0
+ supervisor_host_id: 0
+ - # 28
+ host_id: 0
+ supervisor_host_id: 0
+ - # 29
+ host_id: 0
+ supervisor_host_id: 0
+ - # 30
+ host_id: 0
+ supervisor_host_id: 0
+ - # 31
+ host_id: 0
+ supervisor_host_id: 0
+ - # 32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ write_host_id: 0
+ otp_entry:
+ - # 1
+ host_id: 0
+ host_perms: 0
+ - # 2
+ host_id: 0
+ host_perms: 0
+ - # 3
+ host_id: 0
+ host_perms: 0
+ - # 4
+ host_id: 0
+ host_perms: 0
+ - # 5
+ host_id: 0
+ host_perms: 0
+ - # 6
+ host_id: 0
+ host_perms: 0
+ - # 7
+ host_id: 0
+ host_perms: 0
+ - # 8
+ host_id: 0
+ host_perms: 0
+ - # 9
+ host_id: 0
+ host_perms: 0
+ - # 10
+ host_id: 0
+ host_perms: 0
+ - # 11
+ host_id: 0
+ host_perms: 0
+ - # 12
+ host_id: 0
+ host_perms: 0
+ - # 13
+ host_id: 0
+ host_perms: 0
+ - # 14
+ host_id: 0
+ host_perms: 0
+ - # 15
+ host_id: 0
+ host_perms: 0
+ - # 16
+ host_id: 0
+ host_perms: 0
+ - # 17
+ host_id: 0
+ host_perms: 0
+ - # 18
+ host_id: 0
+ host_perms: 0
+ - # 19
+ host_id: 0
+ host_perms: 0
+ - # 20
+ host_id: 0
+ host_perms: 0
+ - # 21
+ host_id: 0
+ host_perms: 0
+ - # 22
+ host_id: 0
+ host_perms: 0
+ - # 23
+ host_id: 0
+ host_perms: 0
+ - # 24
+ host_id: 0
+ host_perms: 0
+ - # 25
+ host_id: 0
+ host_perms: 0
+ - # 26
+ host_id: 0
+ host_perms: 0
+ - # 27
+ host_id: 0
+ host_perms: 0
+ - # 28
+ host_id: 0
+ host_perms: 0
+ - # 29
+ host_id: 0
+ host_perms: 0
+ - # 30
+ host_id: 0
+ host_perms: 0
+ - # 31
+ host_id: 0
+ host_perms: 0
+ - # 32
+ host_id: 0
+ host_perms: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci: 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size: 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0x5A
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock: 0x5A
+ allow_wildcard_unlock: 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev: 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender: 0
+ handover_to_host_id: 0
+ rsvd: [0, 0, 0, 0]
diff --git a/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
new file mode 100644
index 0000000..151cd59
--- /dev/null
+++ b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
@@ -0,0 +1,903 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62AX
+#
+
+---
+
+tifs-rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ - # 1
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 2
+ host_id: 30
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 3
+ host_id: 36
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 4
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 5
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 6
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 7
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 8
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 9
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 10
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 11
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 12
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 13
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 14
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 15
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 16
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 17
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 18
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 19
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 20
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 21
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 22
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 23
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 24
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 25
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 26
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 27
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 28
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 29
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 30
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 31
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 32
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 872
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1677
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1677
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1677
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1677
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 6
+ type: 1677
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 18
+ type: 1678
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 72
+ num_resource: 6
+ type: 1678
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 72
+ num_resource: 6
+ type: 1678
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 78
+ num_resource: 2
+ type: 1678
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 2
+ type: 1678
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 12
+ type: 1679
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 50
+ num_resource: 2
+ type: 1679
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 2
+ type: 1679
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1696
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1696
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1696
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1696
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 6
+ type: 1696
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1697
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1697
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1697
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1697
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 2
+ type: 1697
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 12
+ type: 1698
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 2
+ type: 1698
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 2
+ type: 1698
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 6
+ num_resource: 34
+ type: 1802
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 168
+ num_resource: 8
+ type: 1802
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1024
+ type: 1807
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 29
+ type: 1808
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4608
+ num_resource: 99
+ type: 1809
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5120
+ num_resource: 24
+ type: 1810
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5632
+ num_resource: 51
+ type: 1811
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 6144
+ num_resource: 51
+ type: 1812
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 6656
+ num_resource: 51
+ type: 1813
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8192
+ num_resource: 32
+ type: 1814
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8704
+ num_resource: 32
+ type: 1815
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9216
+ num_resource: 32
+ type: 1816
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9728
+ num_resource: 22
+ type: 1817
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10240
+ num_resource: 22
+ type: 1818
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10752
+ num_resource: 22
+ type: 1819
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11264
+ num_resource: 28
+ type: 1820
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11776
+ num_resource: 28
+ type: 1821
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 12288
+ num_resource: 28
+ type: 1822
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1936
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1936
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1936
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 8
+ type: 1938
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 91
+ num_resource: 8
+ type: 1939
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 99
+ num_resource: 10
+ type: 1942
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 112
+ num_resource: 3
+ type: 1942
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 3
+ type: 1942
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1944
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1945
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1946
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1947
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1955
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1955
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1955
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 1
+ type: 1957
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 1958
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1961
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1961
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1961
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1962
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1962
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1962
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 1965
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1966
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 1
+ type: 1967
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1968
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 1
+ type: 1969
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1970
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 1
+ type: 1971
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1972
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 2112
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 2122
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 6
+ type: 12750
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 6
+ type: 12769
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12810
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3072
+ num_resource: 6
+ type: 12828
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3584
+ num_resource: 6
+ type: 12829
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 6
+ type: 12830
+ host_id: 128
+ reserved: 0
diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig
index 7c179ef..ecee587 100644
--- a/board/phytec/phycore_am62x/Kconfig
+++ b/board/phytec/phycore_am62x/Kconfig
@@ -33,6 +33,7 @@
default "arch/arm/mach-omap2/u-boot-spl.lds"
source "board/phytec/common/Kconfig"
+source "board/phytec/common/k3/Kconfig"
endif
diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig
index 25e4bf2..0644912 100644
--- a/board/phytec/phycore_imx8mm/Kconfig
+++ b/board/phytec/phycore_imx8mm/Kconfig
@@ -12,4 +12,5 @@
config IMX_CONFIG
default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg"
+source "board/phytec/common/Kconfig"
endif
diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env
new file mode 100644
index 0000000..a7d14e7
--- /dev/null
+++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env
@@ -0,0 +1,65 @@
+#include <env/phytec/rauc.env>
+
+bootcmd=
+ mmc dev ${mmcdev};
+ if mmc rescan; then
+ if test ${doraucboot} = 1; then
+ run raucinit;
+ fi;
+ if run loadimage; then
+ run mmcboot;
+ else
+ run netboot;
+ fi;
+ fi;
+console=ttymxc2,115200
+emmc_dev=2
+fdt_addr_r=0x48000000
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+image=Image
+ip_dyn=yes
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+mmcargs=
+ setenv bootargs console=${console}
+ root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
+mmcautodetect=yes
+mmcboot=
+ echo Booting from mmc ...;
+ run mmcargs;
+ if run loadfdt; then
+ if test ${dofitboot} = 1; then
+ booti ${loadaddr} - ${fdt_addr_r}
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+mmcdev=CONFIG_SYS_MMC_ENV_DEV
+mmcpart=1
+mmcroot=2
+netargs=
+ setenv bootargs console=${console} root=/dev/nfs ip=dhcp
+ nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=
+ echo Booting from net ...;
+ if test ${ip_dyn} = yes; then
+ setenv get_cmd dhcp;
+ else
+ setenv get_cmd tftp;
+ fi;
+ ${get_cmd} ${loadaddr} ${image};
+ run netargs;
+ if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+ booti ${loadaddr} - ${fdt_addr_r};
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+nfsroot=/srv/nfs
+update_bootimg=
+ mmc dev ${mmcdev};
+ if dhcp ${loadaddr} ${update_filepath}/${update_filename}; then
+ setexpr fw_sz ${filesize} / 0x200;
+ mmc write ${loadaddr} ${update_offset} ${fw_sz};
+ fi;
+update_filename=flash.bin
+update_offset=0x42
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c
index 8d85859..faff064 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -17,8 +17,13 @@
#include <log.h>
#include <spl.h>
+#include "../common/imx8m_som_detection.h"
+
DECLARE_GLOBAL_DATA_PTR;
+#define EEPROM_ADDR 0x51
+#define EEPROM_ADDR_FALLBACK 0x59
+
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
@@ -39,6 +44,18 @@
static void spl_dram_init(void)
{
+ int ret;
+
+ ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
+ EEPROM_ADDR_FALLBACK);
+ if (ret)
+ goto out;
+
+ ret = phytec_imx8m_detect(NULL);
+ if (!ret)
+ phytec_print_som_info(NULL);
+
+out:
ddr_init(&dram_timing);
}
diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig
index a70104c..09f26e8 100644
--- a/board/phytec/phycore_imx93/Kconfig
+++ b/board/phytec/phycore_imx93/Kconfig
@@ -10,4 +10,32 @@
config SYS_CONFIG_NAME
default "phycore_imx93"
+config PHYCORE_IMX93_RAM_TYPE_FIX
+ bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting"
+ default false
+ help
+ RAM type and size is being automatically detected with the help
+ of the PHYTEC EEPROM introspection data.
+ Set RAM type to a fix value instead.
+
+choice
+ prompt "phyCORE-i.MX93 RAM type"
+ depends on PHYCORE_IMX93_RAM_TYPE_FIX
+ default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
+
+config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
+ bool "LPDDR4X 1GB RAM"
+ help
+ Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB
+ for phyCORE-i.MX93.
+
+config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB
+ bool "LPDDR4X 2GB RAM"
+ help
+ Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB
+ for phyCORE-i.MX93.
+
+endchoice
+
+source "board/phytec/common/Kconfig"
endif
diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS
index 9e91a29..718f89a 100644
--- a/board/phytec/phycore_imx93/MAINTAINERS
+++ b/board/phytec/phycore_imx93/MAINTAINERS
@@ -1,10 +1,13 @@
phyCORE-i.MX93
-M: Mathieu Othacehe <m.othacehe@gmail.com>
+M: Mathieu Othacehe <m.othacehe@gmail.com>
+R: Christoph Stoidner <c.stoidner@phytec.de>
W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
S: Maintained
F: arch/arm/dts/imx93-phyboard-segin.dts
F: arch/arm/dts/imx93-phycore-som.dtsi
F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
F: board/phytec/phycore_imx93/
-F: configs/imx93-phyboard-segin_defconfig
+F: board/phytec/common/imx93_som_detection.c
+F: board/phytec/common/imx93_som_detection.h
+F: configs/imx93-phycore_defconfig
F: include/configs/phycore_imx93.h
diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx93/lpddr4_timing.c
index 2111972..f1261f6 100644
--- a/board/phytec/phycore_imx93/lpddr4_timing.c
+++ b/board/phytec/phycore_imx93/lpddr4_timing.c
@@ -1,24 +1,24 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2023 NXP
- * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Copyright 2024 NXP
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
* Christoph Stoidner <c.stoidner@phytec.de>
*
- * Code generated with DDR Tool v1.0.0.
+ * Code generated with DDR Tool v3.1.0_7.4.
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
+/* Initialize DDRC registers */
static struct dram_cfg_param ddr_ddrc_cfg[] = {
- /** Initialize DDRC registers **/
{0x4e300110, 0x44100001},
{0x4e300000, 0x8000bf},
{0x4e300008, 0x0},
{0x4e300080, 0x80000412},
{0x4e300084, 0x0},
{0x4e300114, 0x1002},
- {0x4e300260, 0x4080},
+ {0x4e300260, 0x80},
{0x4e300f04, 0x80},
{0x4e300800, 0x43b30002},
{0x4e300804, 0x1f1f1f1f},
@@ -31,18 +31,17 @@
{0x4e301254, 0x0},
{0x4e301258, 0x0},
{0x4e30125c, 0x0},
-
};
/* dram fsp cfg */
static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{
{
- {0x4e300100, 0x24A0421B},
+ {0x4e300100, 0x24A0321B},
{0x4e300104, 0xF8EE001B},
- {0x4e300108, 0x2F263233},
- {0x4e30010C, 0x0005E18B},
- {0x4e300124, 0x1C770000},
+ {0x4e300108, 0x2F2E3233},
+ {0x4e30010C, 0x0005C18B},
+ {0x4e300124, 0x1C790000},
{0x4e300160, 0x00009102},
{0x4e30016C, 0x35F00000},
{0x4e300170, 0x8B0B0608},
@@ -50,21 +49,73 @@
{0x4e300254, 0x00FE00FE},
{0x4e300258, 0x00000008},
{0x4e30025C, 0x00000400},
- {0x4e300300, 0x224F2215},
+ {0x4e300300, 0x224F2213},
{0x4e300304, 0x00FE2213},
- {0x4e300308, 0x0A3C0E3C},
+ {0x4e300308, 0x0A380E3D},
},
{
{0x01, 0xE4},
{0x02, 0x36},
- {0x03, 0xF2},
- {0x0b, 0x46},
- {0x0c, 0x11},
- {0x0e, 0x11},
+ {0x03, 0x22},
+ {0x0b, 0x44},
+ {0x0c, 0x1E},
+ {0x0e, 0x12},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x124F2100},
+ {0x4e300104, 0xF877000E},
+ {0x4e300108, 0x1816E4AA},
+ {0x4e30010C, 0x005101E6},
+ {0x4e300124, 0x0E3C0000},
+ {0x4e300160, 0x00009101},
+ {0x4e30016C, 0x30900000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x00000014},
+ {0x4e300254, 0x007B007B},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0xB4},
+ {0x02, 0x1B},
+ {0x03, 0x22},
+ {0x0b, 0x44},
+ {0x0c, 0x1E},
+ {0x0e, 0x12},
{0x16, 0x04},
},
0,
},
+ {
+ {
+ {0x4e300100, 0x00051000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E620A48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009100},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00240024},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x22},
+ {0x0b, 0x44},
+ {0x0c, 0x1E},
+ {0x0e, 0x12},
+ {0x16, 0x04},
+ },
+ 1,
+ },
};
@@ -90,25 +141,65 @@
{0x1015f, 0x5ff},
{0x1105f, 0x5ff},
{0x1115f, 0x5ff},
+ {0x11005f, 0x5ff},
+ {0x11015f, 0x5ff},
+ {0x11105f, 0x5ff},
+ {0x11115f, 0x5ff},
+ {0x21005f, 0x5ff},
+ {0x21015f, 0x5ff},
+ {0x21105f, 0x5ff},
+ {0x21115f, 0x5ff},
{0x55, 0x1ff},
{0x1055, 0x1ff},
{0x2055, 0x1ff},
{0x200c5, 0x19},
+ {0x1200c5, 0xb},
+ {0x2200c5, 0x7},
{0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
{0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
{0x20024, 0x1e3},
{0x2003a, 0x2},
{0x2007d, 0x212},
{0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
{0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
{0x1004d, 0x600},
{0x1014d, 0x600},
{0x1104d, 0x600},
{0x1114d, 0x600},
- {0x10049, 0xe00},
- {0x10149, 0xe00},
- {0x11049, 0xe00},
- {0x11149, 0xe00},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0x604},
+ {0x10149, 0x604},
+ {0x11049, 0x604},
+ {0x11149, 0x604},
+ {0x110049, 0x604},
+ {0x110149, 0x604},
+ {0x111049, 0x604},
+ {0x111149, 0x604},
+ {0x210049, 0x604},
+ {0x210149, 0x604},
+ {0x211049, 0x604},
+ {0x211149, 0x604},
{0x43, 0x60},
{0x1043, 0x60},
{0x2043, 0x60},
@@ -117,14 +208,30 @@
{0x20050, 0x0},
{0x2009b, 0x2},
{0x20008, 0x3a5},
+ {0x120008, 0x1d3},
+ {0x220008, 0x9c},
{0x20088, 0x9},
- {0x200b2, 0x10c},
+ {0x200b2, 0x104},
{0x10043, 0x5a1},
{0x10143, 0x5a1},
{0x11043, 0x5a1},
{0x11143, 0x5a1},
+ {0x1200b2, 0x104},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x104},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
{0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
{0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
{0x200f0, 0x600},
{0x200f1, 0x0},
{0x200f2, 0x4444},
@@ -133,42 +240,83 @@
{0x200f5, 0x0},
{0x200f6, 0x0},
{0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
{0x20025, 0x0},
- {0x2002d, 0x1},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
{0x2002c, 0x0},
{0x20021, 0x0},
{0x200c7, 0x21},
{0x1200c7, 0x21},
{0x200ca, 0x24},
{0x1200ca, 0x24},
-
};
-/* ddr phy trained csr */
+/* PHY trained csr */
static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x1005f, 0x0},
{0x1015f, 0x0},
{0x1105f, 0x0},
{0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
{0x55, 0x0},
{0x1055, 0x0},
{0x2055, 0x0},
{0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
{0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
{0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
{0x20024, 0x0},
{0x2003a, 0x0},
{0x2007d, 0x0},
{0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
{0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
{0x1004d, 0x0},
{0x1014d, 0x0},
{0x1104d, 0x0},
{0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
{0x10049, 0x0},
{0x10149, 0x0},
{0x11049, 0x0},
{0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
{0x43, 0x0},
{0x1043, 0x0},
{0x2043, 0x0},
@@ -177,14 +325,30 @@
{0x20050, 0x0},
{0x2009b, 0x0},
{0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
{0x20088, 0x0},
{0x200b2, 0x0},
{0x10043, 0x0},
{0x10143, 0x0},
{0x11043, 0x0},
{0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
{0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
{0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
{0x200f0, 0x0},
{0x200f1, 0x0},
{0x200f2, 0x0},
@@ -193,8 +357,12 @@
{0x200f5, 0x0},
{0x200f6, 0x0},
{0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
{0x20025, 0x0},
{0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
{0x2002c, 0x0},
{0xd0000, 0x0},
{0x90000, 0x0},
@@ -682,6 +850,14 @@
{0x2000c, 0x0},
{0x2000d, 0x0},
{0x2000e, 0x0},
+ {0x12000b, 0x0},
+ {0x12000c, 0x0},
+ {0x12000d, 0x0},
+ {0x12000e, 0x0},
+ {0x22000b, 0x0},
+ {0x22000c, 0x0},
+ {0x22000d, 0x0},
+ {0x22000e, 0x0},
{0x9000c, 0x0},
{0x9000d, 0x0},
{0x9000e, 0x0},
@@ -692,12 +868,26 @@
{0x90013, 0x0},
{0x20010, 0x0},
{0x20011, 0x0},
+ {0x120010, 0x0},
+ {0x120011, 0x0},
{0x40080, 0x0},
{0x40081, 0x0},
{0x40082, 0x0},
{0x40083, 0x0},
{0x40084, 0x0},
{0x40085, 0x0},
+ {0x140080, 0x0},
+ {0x140081, 0x0},
+ {0x140082, 0x0},
+ {0x140083, 0x0},
+ {0x140084, 0x0},
+ {0x140085, 0x0},
+ {0x240080, 0x0},
+ {0x240081, 0x0},
+ {0x240082, 0x0},
+ {0x240083, 0x0},
+ {0x240084, 0x0},
+ {0x240085, 0x0},
{0x400fd, 0x0},
{0x400f1, 0x0},
{0x10011, 0x0},
@@ -866,6 +1056,160 @@
{0x90207, 0x0},
{0x90208, 0x0},
{0x20020, 0x0},
+ {0x100080, 0x0},
+ {0x101080, 0x0},
+ {0x102080, 0x0},
+ {0x110020, 0x0},
+ {0x110080, 0x0},
+ {0x110081, 0x0},
+ {0x1100d0, 0x0},
+ {0x1100d1, 0x0},
+ {0x11008c, 0x0},
+ {0x11008d, 0x0},
+ {0x110180, 0x0},
+ {0x110181, 0x0},
+ {0x1101d0, 0x0},
+ {0x1101d1, 0x0},
+ {0x11018c, 0x0},
+ {0x11018d, 0x0},
+ {0x1100c0, 0x0},
+ {0x1100c1, 0x0},
+ {0x1101c0, 0x0},
+ {0x1101c1, 0x0},
+ {0x1102c0, 0x0},
+ {0x1102c1, 0x0},
+ {0x1103c0, 0x0},
+ {0x1103c1, 0x0},
+ {0x1104c0, 0x0},
+ {0x1104c1, 0x0},
+ {0x1105c0, 0x0},
+ {0x1105c1, 0x0},
+ {0x1106c0, 0x0},
+ {0x1106c1, 0x0},
+ {0x1107c0, 0x0},
+ {0x1107c1, 0x0},
+ {0x1108c0, 0x0},
+ {0x1108c1, 0x0},
+ {0x1100ae, 0x0},
+ {0x1100af, 0x0},
+ {0x111020, 0x0},
+ {0x111080, 0x0},
+ {0x111081, 0x0},
+ {0x1110d0, 0x0},
+ {0x1110d1, 0x0},
+ {0x11108c, 0x0},
+ {0x11108d, 0x0},
+ {0x111180, 0x0},
+ {0x111181, 0x0},
+ {0x1111d0, 0x0},
+ {0x1111d1, 0x0},
+ {0x11118c, 0x0},
+ {0x11118d, 0x0},
+ {0x1110c0, 0x0},
+ {0x1110c1, 0x0},
+ {0x1111c0, 0x0},
+ {0x1111c1, 0x0},
+ {0x1112c0, 0x0},
+ {0x1112c1, 0x0},
+ {0x1113c0, 0x0},
+ {0x1113c1, 0x0},
+ {0x1114c0, 0x0},
+ {0x1114c1, 0x0},
+ {0x1115c0, 0x0},
+ {0x1115c1, 0x0},
+ {0x1116c0, 0x0},
+ {0x1116c1, 0x0},
+ {0x1117c0, 0x0},
+ {0x1117c1, 0x0},
+ {0x1118c0, 0x0},
+ {0x1118c1, 0x0},
+ {0x1110ae, 0x0},
+ {0x1110af, 0x0},
+ {0x190201, 0x0},
+ {0x190202, 0x0},
+ {0x190203, 0x0},
+ {0x190205, 0x0},
+ {0x190206, 0x0},
+ {0x190207, 0x0},
+ {0x190208, 0x0},
+ {0x120020, 0x0},
+ {0x200080, 0x0},
+ {0x201080, 0x0},
+ {0x202080, 0x0},
+ {0x210020, 0x0},
+ {0x210080, 0x0},
+ {0x210081, 0x0},
+ {0x2100d0, 0x0},
+ {0x2100d1, 0x0},
+ {0x21008c, 0x0},
+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
{0x20077, 0x0},
{0x20072, 0x0},
{0x20073, 0x0},
@@ -888,7 +1232,6 @@
{0x11640, 0x0},
{0x11740, 0x0},
{0x11840, 0x0},
-
};
/* P0 message block parameter for training firmware */
@@ -896,7 +1239,7 @@
{0xd0000, 0x0},
{0x54003, 0xe94},
{0x54004, 0x4},
- {0x54006, 0x15},
+ {0x54006, 0x14},
{0x54008, 0x131f},
{0x54009, 0xc8},
{0x5400b, 0x4},
@@ -904,36 +1247,112 @@
{0x5400f, 0x100},
{0x54012, 0x110},
{0x54019, 0x36e4},
- {0x5401a, 0xf2},
- {0x5401b, 0x1146},
- {0x5401c, 0x1108},
+ {0x5401a, 0x22},
+ {0x5401b, 0x1e44},
+ {0x5401c, 0x1208},
{0x5401e, 0x4},
{0x5401f, 0x36e4},
- {0x54020, 0xf2},
- {0x54021, 0x1146},
- {0x54022, 0x1108},
+ {0x54020, 0x22},
+ {0x54021, 0x1e44},
+ {0x54022, 0x1208},
{0x54024, 0x4},
{0x54032, 0xe400},
- {0x54033, 0xf236},
- {0x54034, 0x4600},
- {0x54035, 0x811},
- {0x54036, 0x11},
+ {0x54033, 0x2236},
+ {0x54034, 0x4400},
+ {0x54035, 0x81e},
+ {0x54036, 0x12},
{0x54037, 0x400},
{0x54038, 0xe400},
- {0x54039, 0xf236},
- {0x5403a, 0x4600},
- {0x5403b, 0x811},
- {0x5403c, 0x11},
+ {0x54039, 0x2236},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x81e},
+ {0x5403c, 0x12},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x74a},
+ {0x54004, 0x4},
+ {0x54006, 0x14},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x1bb4},
+ {0x5401a, 0x22},
+ {0x5401b, 0x1e44},
+ {0x5401c, 0x1208},
+ {0x5401e, 0x4},
+ {0x5401f, 0x1bb4},
+ {0x54020, 0x22},
+ {0x54021, 0x1e44},
+ {0x54022, 0x1208},
+ {0x54024, 0x4},
+ {0x54032, 0xb400},
+ {0x54033, 0x221b},
+ {0x54034, 0x4400},
+ {0x54035, 0x81e},
+ {0x54036, 0x12},
+ {0x54037, 0x400},
+ {0x54038, 0xb400},
+ {0x54039, 0x221b},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x81e},
+ {0x5403c, 0x12},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x14},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x22},
+ {0x5401b, 0x1e44},
+ {0x5401c, 0x1200},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x22},
+ {0x54021, 0x1e44},
+ {0x54022, 0x1200},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x2209},
+ {0x54034, 0x4400},
+ {0x54035, 0x1e},
+ {0x54036, 0x12},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x2209},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x1e},
+ {0x5403c, 0x12},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
/* P0 2D message block parameter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0xd0000, 0x0},
{0x54003, 0xe94},
{0x54004, 0x4},
- {0x54006, 0x15},
+ {0x54006, 0x14},
{0x54008, 0x61},
{0x54009, 0xc8},
{0x5400b, 0x4},
@@ -942,26 +1361,26 @@
{0x54010, 0x2080},
{0x54012, 0x110},
{0x54019, 0x36e4},
- {0x5401a, 0xf2},
- {0x5401b, 0x1146},
- {0x5401c, 0x1108},
+ {0x5401a, 0x22},
+ {0x5401b, 0x1e44},
+ {0x5401c, 0x1208},
{0x5401e, 0x4},
{0x5401f, 0x36e4},
- {0x54020, 0xf2},
- {0x54021, 0x1146},
- {0x54022, 0x1108},
+ {0x54020, 0x22},
+ {0x54021, 0x1e44},
+ {0x54022, 0x1208},
{0x54024, 0x4},
{0x54032, 0xe400},
- {0x54033, 0xf236},
- {0x54034, 0x4600},
- {0x54035, 0x811},
- {0x54036, 0x11},
+ {0x54033, 0x2236},
+ {0x54034, 0x4400},
+ {0x54035, 0x81e},
+ {0x54036, 0x12},
{0x54037, 0x400},
{0x54038, 0xe400},
- {0x54039, 0xf236},
- {0x5403a, 0x4600},
- {0x5403b, 0x811},
- {0x5403c, 0x11},
+ {0x54039, 0x2236},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x81e},
+ {0x5403c, 0x12},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
@@ -1451,10 +1870,18 @@
{0x400d7, 0x20b},
{0x2003a, 0x2},
{0x200be, 0x3},
- {0x2000b, 0x75},
+ {0x2000b, 0x41a},
{0x2000c, 0xe9},
{0x2000d, 0x91c},
{0x2000e, 0x2c},
+ {0x12000b, 0x20d},
+ {0x12000c, 0x74},
+ {0x12000d, 0x48e},
+ {0x12000e, 0x2c},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
{0x9000c, 0x0},
{0x9000d, 0x173},
{0x9000e, 0x60},
@@ -1465,12 +1892,26 @@
{0x90013, 0x6152},
{0x20010, 0x5a},
{0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
{0x40080, 0xe0},
{0x40081, 0x12},
{0x40082, 0xe0},
{0x40083, 0x12},
{0x40084, 0xe0},
{0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
{0x400fd, 0xf},
{0x400f1, 0xe},
{0x10011, 0x1},
@@ -1505,7 +1946,6 @@
{0x20088, 0x19},
{0xc0080, 0x0},
{0xd0000, 0x1},
-
};
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
@@ -1515,9 +1955,21 @@
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
-
},
-
+ {
+ /* P1 1866mts 1D */
+ .drate = 1866,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
{
/* P0 3733mts 2D */
.drate = 3733,
@@ -1525,7 +1977,6 @@
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
},
-
};
/* ddr timing config params */
@@ -1540,7 +1991,227 @@
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, },
+ .fsp_table = { 3733, 1866, 625, },
.fsp_cfg = ddr_dram_fsp_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
};
+
+void set_dram_timings_2gb_lpddr4x(void)
+{
+ /* Initialize DDRC registers */
+ dram_timing.ddrc_cfg[1].val = 0x8000ff;
+ dram_timing.ddrc_cfg[3].val = 0x80000512;
+
+ /* dram fsp cfg */
+ dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x24AB321B;
+ dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x2F2EE233;
+ dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x015B015B;
+ dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x015B2213;
+ dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x13;
+
+ dram_timing.fsp_cfg[1].ddrc_cfg[0].val = 0x12552100;
+ dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x1816B4AA;
+ dram_timing.fsp_cfg[1].ddrc_cfg[9].val = 0x00AA00AA;
+ dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x13;
+
+ dram_timing.fsp_cfg[2].ddrc_cfg[0].val = 0x00061000;
+ dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E62FA48;
+ dram_timing.fsp_cfg[2].ddrc_cfg[9].val = 0x00340034;
+ dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x13;
+
+ /* P0 message block parameter for training firmware */
+ dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
+ dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1308;
+ dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
+ dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1308;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
+ dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x13;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
+ dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x13;
+
+ /* P1 message block parameter for training firmware */
+ dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1308;
+ dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1308;
+ dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
+ dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x13;
+ dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
+ dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x13;
+
+ /* P2 message block parameter for training firmware */
+ dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1300;
+ dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1300;
+ dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
+ dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x13;
+ dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
+ dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x13;
+
+ /* P0 2D message block parameter for training firmware */
+ dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1308;
+ dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1308;
+ dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
+ dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x13;
+ dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
+ dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x13;
+}
+
+/* Generated with DDR Tool v3.3.0_7.8-d1cdb7d3 */
+void set_dram_timings_1gb_lpddr4x_900mhz(void)
+{
+ /* Initialize DDRC registers */
+ dram_timing.ddrc_cfg[6].val = 0x4080;
+
+ /* dram fsp cfg */
+ dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x124F2100;
+ dram_timing.fsp_cfg[0].ddrc_cfg[1].val = 0xF877000E;
+ dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x181AE4AA;
+ dram_timing.fsp_cfg[0].ddrc_cfg[3].val = 0x005101E6;
+ dram_timing.fsp_cfg[0].ddrc_cfg[4].val = 0x0E3C0000;
+ dram_timing.fsp_cfg[0].ddrc_cfg[5].val = 0x00009101;
+ dram_timing.fsp_cfg[0].ddrc_cfg[6].val = 0x30900000;
+ dram_timing.fsp_cfg[0].ddrc_cfg[7].val = 0x8A0A0508;
+ dram_timing.fsp_cfg[0].ddrc_cfg[8].val = 0x00000014;
+ dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x007B007B;
+ dram_timing.fsp_cfg[0].ddrc_cfg[12].val = 0x1128110B;
+ dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x007B140A;
+ dram_timing.fsp_cfg[0].ddrc_cfg[14].val = 0x0620071E;
+ dram_timing.fsp_cfg[0].mr_cfg[0].val = 0xB4;
+ dram_timing.fsp_cfg[0].mr_cfg[1].val = 0x1B;
+ dram_timing.fsp_cfg[0].mr_cfg[2].val = 0xE2;
+ dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x15;
+
+ dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x181AE4AA;
+ dram_timing.fsp_cfg[1].mr_cfg[2].val = 0xE2;
+ dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x15;
+
+ dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E660A48;
+ dram_timing.fsp_cfg[2].mr_cfg[2].val = 0xE2;
+ dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
+ dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x15;
+
+ /* PHY Initialize Configuration */
+ dram_timing.ddrphy_cfg[31].val = 0xb;
+ dram_timing.ddrphy_cfg[86].val = 0x1d3;
+ dram_timing.ddrphy_cfg[90].val = 0x10c;
+ dram_timing.ddrphy_cfg[95].val = 0x10c;
+ dram_timing.ddrphy_cfg[100].val = 0x10c;
+ dram_timing.ddrphy_cfg[122].val = 0x1;
+ /**
+ * NOTE:
+ * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 119
+ * (reg=0x1004a, val=0x500) and 120 (reg=0x1104a, val=0x500) are not
+ * present in the ddr_ddrphy_cfg array. However they were present in array
+ * generated with previous DDR Tool v3.1.0_7.4. We simply set both values
+ * to default value of 0x400 (read with dwc_ddrphy_apb_rd()) here to avoid
+ * any negative side-effects.
+ */
+ dram_timing.ddrphy_cfg[119].val = 0x400;
+ dram_timing.ddrphy_cfg[120].val = 0x400;
+
+ /**
+ * NOTE:
+ * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 101
+ * (reg=0x1004a, val=0x0) and 120 (reg=0x1104a, val=0x0) are not present
+ * in the ddr_ddrphy_trained_csr array. However they were present in array
+ * generated with previous DDR Tool v3.1.0_7.4. We simply set both values
+ * to default 0x0 (like all other ddrphy_trained_csr values) here to avoid
+ * any negative side-effects.
+ */
+ /* PHY trained csr */
+ dram_timing.ddrphy_trained_csr[101].val = 0x0;
+ dram_timing.ddrphy_trained_csr[102].val = 0x0;
+
+ /* P0 message block parameter for training firmware */
+ dram_timing.fsp_msg[0].fsp_cfg[1].val = 0x74a;
+ dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x15;
+ dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x1bb4;
+ dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xe2;
+ dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
+ dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1508;
+ dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x1bb4;
+ dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xe2;
+ dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
+ dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1508;
+ dram_timing.fsp_msg[0].fsp_cfg[20].val = 0xb400;
+ dram_timing.fsp_msg[0].fsp_cfg[21].val = 0xe21b;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
+ dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x15;
+ dram_timing.fsp_msg[0].fsp_cfg[26].val = 0xb400;
+ dram_timing.fsp_msg[0].fsp_cfg[27].val = 0xe21b;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
+ dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x15;
+
+ /* P1 message block parameter for training firmware */
+ dram_timing.fsp_msg[1].fsp_cfg[4].val = 0x15;
+ dram_timing.fsp_msg[1].fsp_cfg[12].val = 0xe2;
+ dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1508;
+ dram_timing.fsp_msg[1].fsp_cfg[17].val = 0xe2;
+ dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1508;
+ dram_timing.fsp_msg[1].fsp_cfg[22].val = 0xe21b;
+ dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
+ dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x15;
+ dram_timing.fsp_msg[1].fsp_cfg[28].val = 0xe21b;
+ dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
+ dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x15;
+
+ /* P2 message block parameter for training firmware */
+ dram_timing.fsp_msg[2].fsp_cfg[4].val = 0x15;
+ dram_timing.fsp_msg[2].fsp_cfg[12].val = 0xe2;
+ dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1500;
+ dram_timing.fsp_msg[2].fsp_cfg[17].val = 0xe2;
+ dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1500;
+ dram_timing.fsp_msg[2].fsp_cfg[22].val = 0xe209;
+ dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
+ dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x15;
+ dram_timing.fsp_msg[2].fsp_cfg[28].val = 0xe209;
+ dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
+ dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x15;
+
+ /* P0 2D message block parameter for training firmware */
+ dram_timing.fsp_msg[3].fsp_cfg[1].val = 0x74a;
+ dram_timing.fsp_msg[3].fsp_cfg[3].val = 0x15;
+ dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x1bb4;
+ dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xe2;
+ dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
+ dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1508;
+ dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x1bb4;
+ dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xe2;
+ dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
+ dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1508;
+ dram_timing.fsp_msg[3].fsp_cfg[21].val = 0xb400;
+ dram_timing.fsp_msg[3].fsp_cfg[22].val = 0xe21b;
+ dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
+ dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x15;
+ dram_timing.fsp_msg[3].fsp_cfg[27].val = 0xb400;
+ dram_timing.fsp_msg[3].fsp_cfg[28].val = 0xe21b;
+ dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
+ dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x15;
+
+ /* DRAM PHY init engine image */
+ dram_timing.ddrphy_pie[483].val = 0x20d;
+ dram_timing.ddrphy_pie[484].val = 0x74;
+ dram_timing.ddrphy_pie[485].val = 0x48e;
+
+ /* P0 3733mts 1D */
+ dram_timing.fsp_msg[0].drate = 1866;
+
+ /* P0 1866mts 2D */
+ dram_timing.fsp_msg[3].drate = 1866;
+
+ /* ddr timing config params */
+ dram_timing.fsp_table[0] = 1866;
+}
diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c
index 085c8e1..a55795e 100644
--- a/board/phytec/phycore_imx93/phycore-imx93.c
+++ b/board/phytec/phycore_imx93/phycore-imx93.c
@@ -3,6 +3,7 @@
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
*/
#include <asm/arch-imx9/ccm_regs.h>
@@ -12,11 +13,21 @@
#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
+#include <fdt_support.h>
+
+#include "../common/imx93_som_detection.h"
DECLARE_GLOBAL_DATA_PTR;
+#define EEPROM_ADDR 0x50
+
int board_init(void)
{
+ int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
+
+ if (ret)
+ printf("%s: EEPROM data init failed\n", __func__);
+
return 0;
}
@@ -38,5 +49,45 @@
break;
}
+ return 0;
+}
+
+static void emmc_fixup(void *blob, struct phytec_eeprom_data *data)
+{
+ enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data);
+ int offset;
+
+ if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID)
+ goto err;
+
+ if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) {
+ offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc",
+ 0x42850000);
+ if (offset)
+ fdt_delprop(blob, offset, "no-1-8-v");
+ else
+ goto err;
+ }
+
+ return;
+err:
+ printf("Could not detect eMMC VDD-IO. Fall back to default.\n");
+}
+
+int board_fix_fdt(void *blob)
+{
+ struct phytec_eeprom_data data;
+
+ phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR);
+
+ emmc_fixup(blob, &data);
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ emmc_fixup(blob, NULL);
+
return 0;
}
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 17a8736..a4d2aaa 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -3,6 +3,7 @@
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
* Author: Christoph Stoidner <c.stoidner@phytec.de>
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
*/
#include <asm/arch/clock.h>
@@ -20,6 +21,8 @@
#include <power/pca9450.h>
#include <spl.h>
+#include "../common/imx93_som_detection.h"
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -27,6 +30,13 @@
* when pca9451a support is added.
*/
#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5)
+#define EEPROM_ADDR 0x50
+
+/*
+ * Prototypes of automatically generated ram config file
+ */
+void set_dram_timings_2gb_lpddr4x(void);
+void set_dram_timings_1gb_lpddr4x_900mhz(void);
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
@@ -46,6 +56,44 @@
void spl_dram_init(void)
{
+ int ret;
+ enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
+
+ /* NOTE: In SPL lpi2c3 is mapped to bus 0 */
+ ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
+ if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
+ goto out;
+
+ ret = phytec_imx93_detect(NULL);
+ if (!ret)
+ phytec_print_som_info(NULL);
+
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB))
+ ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB))
+ ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB;
+ } else {
+ ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR);
+ }
+
+ switch (ddr_opt) {
+ case PHYTEC_IMX93_LPDDR4X_1GB:
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
+ set_dram_timings_1gb_lpddr4x_900mhz();
+ break;
+ case PHYTEC_IMX93_LPDDR4X_2GB:
+ set_dram_timings_2gb_lpddr4x();
+ break;
+ default:
+ goto out;
+ }
+ ddr_init(&dram_timing);
+ return;
+out:
+ puts("Could not detect correct RAM type and size. Fall back to default.\n");
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
+ set_dram_timings_1gb_lpddr4x_900mhz();
ddr_init(&dram_timing);
}
diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig
index c5a28ff..fe23097 100644
--- a/board/siemens/capricorn/Kconfig
+++ b/board/siemens/capricorn/Kconfig
@@ -1,4 +1,5 @@
-if TARGET_GIEDI
+if TARGET_CAPRICORN
+
config SYS_BOARD
default "capricorn"
@@ -7,24 +8,18 @@
default "siemens"
config SYS_CONFIG_NAME
- default "giedi"
+ default "capricorn-common"
config IMX_CONFIG
default "board/siemens/capricorn/imximage.cfg"
-endif
-if TARGET_DENEB
-
-config SYS_BOARD
- default "capricorn"
-
-config SYS_VENDOR
- default "siemens"
+endif
-config SYS_CONFIG_NAME
- default "deneb"
-config IMX_CONFIG
- default "board/siemens/capricorn/imximage.cfg"
+config SPL_CMT
+ bool "Enable Siemens SPL RAM test"
+ depends on SPL
+ help
+ Enable SIemens SPL RAM test.
-endif
+source "board/siemens/common/Kconfig"
diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS
index b4c5203..5f467aa 100644
--- a/board/siemens/capricorn/MAINTAINERS
+++ b/board/siemens/capricorn/MAINTAINERS
@@ -1,10 +1,12 @@
CAPRICORN BOARD
+M: Alexander Sverdlin <alexander.sverdlin@siemens.com>
M: Anatolij Gustschin <agust@denx.de>
+M: Heiko Schocher <hs@denx.de>
+M: Walter Schweizer <walter.schweizer@siemens.com>
S: Maintained
+F: arch/arm/dts/imx8-capricorn-cxg3.dts
+F: arch/arm/dts/imx8-capricorn-u-boot.dtsi
+F: arch/arm/dts/imx8-capricorn.dtsi
F: board/siemens/capricorn/
+F: configs/capricorn_cxg3_defconfig
F: include/configs/capricorn-common.h
-F: include/configs/deneb.h
-F: include/configs/giedi.h
-F: include/configs/siemens-env-common.h
-F: configs/deneb_defconfig
-F: configs/giedi_defconfig
diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile
index e8a24c4..a03d54e 100644
--- a/board/siemens/capricorn/Makefile
+++ b/board/siemens/capricorn/Makefile
@@ -8,6 +8,8 @@
ifdef CONFIG_XPL_BUILD
obj-y += spl.o
+obj-$(CONFIG_SPL_CMT) += spl_memory_test.o
else
obj-y += ../common/factoryset.o
+obj-$(CONFIG_DDR_SI_TEST) += ../common/ddr_si_test.o
endif
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c
index ad474d9..390a7b0 100644
--- a/board/siemens/capricorn/board.c
+++ b/board/siemens/capricorn/board.c
@@ -26,6 +26,7 @@
#include <asm/arch-imx8/clock.h>
#endif
#include <linux/delay.h>
+#include "../common/board.h"
#include "../common/eeprom.h"
#include "../common/factoryset.h"
@@ -63,8 +64,7 @@
sc_pm_clock_rate_t rate = SC_80MHZ;
int ret;
- ret = sc_pm_setup_uart(SC_R_UART_0, rate);
- ret |= sc_pm_setup_uart(SC_R_UART_2, rate);
+ ret = sc_pm_setup_uart(SC_R_UART_2, rate);
if (ret)
return ret;
@@ -73,6 +73,40 @@
return 0;
}
+#ifndef CONFIG_XPL_BUILD
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+ u64 *phys_sdram_1_size,
+ u64 *phys_sdram_2_start,
+ u64 *phys_sdram_2_size)
+{
+ sc_faddr_t addr_start, addr_end;
+ sc_faddr_t sdram_1_size, sdram_2_size;
+ sc_err_t sc_err;
+
+ sc_err = sc_rm_get_memreg_info(-1, 6, &addr_start, &addr_end);
+ if (sc_err == SC_ERR_NONE) {
+ if (addr_end < 0x100000000) {
+ /* only lower RAM available */
+ sdram_1_size = (addr_end + 1) - PHYS_SDRAM_1;
+ sdram_2_size = 0;
+ } else {
+ /* lower RAM (2 GB) und upper RAM available */
+ sdram_1_size = SZ_2G;
+ sdram_2_size = (addr_end + 1) - PHYS_SDRAM_2;
+ }
+ } else {
+ /* Get default in case it would fail */
+ sdram_1_size = PHYS_SDRAM_1_SIZE;
+ sdram_2_size = PHYS_SDRAM_2_SIZE;
+ }
+
+ *phys_sdram_1_start = PHYS_SDRAM_1;
+ *phys_sdram_1_size = sdram_1_size;
+ *phys_sdram_2_start = PHYS_SDRAM_2;
+ *phys_sdram_2_size = sdram_2_size;
+}
+#endif /* ! CONFIG_XPL_BUILD */
+
#define ENET_PHY_RESET IMX_GPIO_NR(0, 3)
#define ENET_TEST_1 IMX_GPIO_NR(0, 8)
#define ENET_TEST_2 IMX_GPIO_NR(0, 9)
@@ -271,11 +305,7 @@
{
puts("Board: Capricorn\n");
- /*
- * Running build_info() doesn't work with current SCFW blob.
- * Uncomment below call when new blob is available.
- */
- /*build_info();*/
+ build_info();
print_bootinfo();
return 0;
@@ -283,6 +313,32 @@
int board_init(void)
{
+ struct chip_data eeprom_data = {};
+ char module_name[16];
+ int ret;
+
+ ret = siemens_ee_setup();
+ if (ret) {
+ printf("'siemens_ee_setup' failed, ret: %d\n", ret);
+ goto skip;
+ }
+
+ /* Get module name from EEPROM */
+ siemens_ee_read_data(SIEMENS_EE_ADDR_DDR3, module_name,
+ sizeof(module_name));
+ printf("CPU module: %s\n", module_name);
+
+ ret = siemens_ee_read_data(SIEMENS_EE_ADDR_CHIP,
+ (uchar *)&eeprom_data,
+ sizeof(eeprom_data));
+ if (ret) {
+ printf("'siemens_ee_read_data' failed, ret: %d\n", ret);
+ goto skip;
+ }
+
+ printf("HW Version: %s\n", eeprom_data.shwver);
+skip:
+
setup_fec();
return 0;
}
diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg
index 4350e29..7fd3fb8 100644
--- a/board/siemens/capricorn/imximage.cfg
+++ b/board/siemens/capricorn/imximage.cfg
@@ -9,13 +9,24 @@
/* Boot from SD, sector size 0x400 */
BOOT_FROM sd
+
+/* skip DCD data, as firmware initializes the RAM */
+DCD_SKIP true
+
/* SoC type IMX8QX */
SOC_TYPE IMX8QX
-/* Append seco container image */
-APPEND ahab-container.img
+/*
+ * Append seco container image,
+ * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi
+ */
+APPEND mx8qxc0-ahab-container.img
/* Create the 2nd container */
CONTAINER
-/* Add scfw image with exec attribute */
-IMAGE SCU capricorn-scfw-tcm.bin
-/* Add ATF image with exec attribute */
+/*
+ * Add scfw image with exec attribute
+ * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi
+ */
+IMAGE SCU mx8qx-mek-scfw-tcm.bin
+
+/* Add SPL image with exec attribute */
IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c
index 696b5eb..5865cde 100644
--- a/board/siemens/capricorn/spl.c
+++ b/board/siemens/capricorn/spl.c
@@ -15,12 +15,31 @@
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
+#include <firmware/imx/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include "spl_memory_test.h"
+
DECLARE_GLOBAL_DATA_PTR;
+#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19)
+static iomux_cfg_t usdhc2_sd_pwr[] = {
+ SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
void spl_board_init(void)
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
@@ -34,8 +53,32 @@
timer_init();
+ imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr));
+ gpio_direction_output(USDHC2_SD_PWR, 0);
+
preloader_console_init();
+
+ puts("Normal Boot\n");
+
+#if IS_ENABLED(CONFIG_SPL_CMT)
+ spl_siemens_memory_full_test();
+#endif
+}
+
+void spl_board_prepare_for_boot(void)
+{
+ imx8_power_off_pd_devices(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
}
+#endif
void board_init_f(ulong dummy)
{
diff --git a/board/siemens/capricorn/spl_memory_test.c b/board/siemens/capricorn/spl_memory_test.c
new file mode 100644
index 0000000..84c97e7
--- /dev/null
+++ b/board/siemens/capricorn/spl_memory_test.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright Siemens AG 2020
+ *
+ * SPL Full Memory Test
+ * - memory test through the full DDR area
+ * - refresh over temperature torture (write all, read all)
+ *
+ * Remark:
+ * This test has ran properly with the definition of the RAM sizes in board
+ * headers. Since these headers are removed it's necessary to set the correct
+ * values to PHYS_SDRAM_1_SIZE & PHYS_SDRAM_2_SIZE before to recompile.
+ *
+ * An alternative is to refactor the code to get the size info from system
+ * controller
+ */
+
+#include <init.h>
+#include <log.h>
+
+/* ----- Defines ----- */
+#define CHECK_LOWER_UPPER
+
+#define LEVEL2_PRINT 0x0FFFFFFF
+
+/* use 0x7FFF0000 for shorter loop test */
+#define BASE_OFFSET 0x00000000
+
+/* ----- Types ----- */
+struct ct_t {
+ unsigned long *start;
+ unsigned long *end;
+};
+
+/* ----- Variables ----- */
+static struct ct_t ct;
+static unsigned long error_counter;
+
+static void print_parameters(void)
+{
+ printf("\nstart addr: %p\n", ct.start);
+ printf("end addr : %p\n", ct.end);
+}
+
+static void run_test(void)
+{
+ /* moved full test in one void */
+ unsigned long *address; /* 512 */
+ unsigned long ebyte1;
+ unsigned long ebyte2;
+ unsigned int i;
+ unsigned long rpattern;
+
+ for (i = 0; i <= 255; i++) {
+ memset(&ebyte1, i, sizeof(ebyte1));
+ ebyte2 = ~ebyte1;
+ printf("LWord: %016lx #LWord: %016lx\n", ebyte1, ebyte2);
+
+ /* write all bytes -> duration ~ 150 s */
+ for (address = ct.start; address <= ct.end; address++) {
+#ifdef LEVEL2_PRINT
+ if (((unsigned long)address & LEVEL2_PRINT) == 0)
+ printf("write to %p - %p\n", address,
+ (void *)((unsigned long)address +
+ LEVEL2_PRINT));
+#endif
+ *address = ebyte1;
+ address++;
+ *address = ebyte2;
+ }
+
+ /* check all bytes */
+ for (address = ct.start; address <= ct.end; address++) {
+#ifdef LEVEL2_PRINT
+ if (((unsigned long)address & LEVEL2_PRINT) == 0)
+ printf("check from %p - %p\n", address,
+ (void *)((unsigned long)address +
+ LEVEL2_PRINT));
+#endif
+
+ rpattern = *address;
+ if (rpattern != ebyte1) {
+ error_counter++;
+ printf("Error! Read: %016lX Wrote: %016lX Address: %p\n",
+ rpattern, ebyte1, address);
+ }
+
+ address++;
+ rpattern = *address;
+ if (rpattern != ebyte2) {
+ error_counter++;
+ printf("Error! Read: %016lX Wrote: %016lX Address: %p\n",
+ rpattern, ebyte2, address);
+ }
+ }
+ }
+}
+
+#ifdef CHECK_LOWER_UPPER
+void test_lower_upper(void)
+{
+ /*
+ * write different values at the same address of both memory areas
+ * and check them
+ */
+#define TEST_ADDRESS 0x12345670UL
+#define LOWER_ADDRESS (PHYS_SDRAM_1 + TEST_ADDRESS)
+#define UPPER_ADDRESS (PHYS_SDRAM_2 + TEST_ADDRESS)
+#define LOWER_VALUE 0x0011223344556677
+#define UPPER_VALUE 0x89ab89abffeeddcc
+
+ *(unsigned long *)LOWER_ADDRESS = LOWER_VALUE;
+ *(unsigned long *)UPPER_ADDRESS = UPPER_VALUE;
+
+ puts("\nlower-upper memory area test\n");
+ printf("write %016lx to lower address %010lx\n", LOWER_VALUE,
+ LOWER_ADDRESS);
+ printf("write %016lx to upper address %010lx\n", UPPER_VALUE,
+ UPPER_ADDRESS);
+ printf("read %016lx from lower address %010lx\n",
+ *(unsigned long *)LOWER_ADDRESS, LOWER_ADDRESS);
+ printf("read %016lx from upper address %010lx\n",
+ *(unsigned long *)UPPER_ADDRESS, UPPER_ADDRESS);
+}
+#endif
+
+void spl_siemens_memory_full_test(void)
+{
+ unsigned long loopc = 0;
+
+ puts("\nSPL: memory cell test\n");
+
+#ifdef CHECK_LOWER_UPPER
+ if (PHYS_SDRAM_2_SIZE != 0)
+ test_lower_upper();
+#endif
+
+ while (true) {
+ /* imx8x has 2 memory areas up to 2 GB */
+
+ /* 1st memory area @ 0x80000000 */
+ ct.start = (unsigned long *)(PHYS_SDRAM_1 + BASE_OFFSET);
+ ct.end = (unsigned long *)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - 1);
+ print_parameters();
+ run_test();
+
+ /* 2nd memory area @ 0x880000000 */
+ if (PHYS_SDRAM_2_SIZE != 0) {
+ ct.start = (unsigned long *)(PHYS_SDRAM_2 + BASE_OFFSET);
+ ct.end = (unsigned long *)(PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE - 1);
+ print_parameters();
+ run_test();
+ }
+
+ loopc++;
+ printf("loop: %ld, errors: %ld\n\n", loopc, error_counter);
+ };
+}
diff --git a/board/siemens/capricorn/spl_memory_test.h b/board/siemens/capricorn/spl_memory_test.h
new file mode 100644
index 0000000..28df284
--- /dev/null
+++ b/board/siemens/capricorn/spl_memory_test.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright Siemens AG 2020
+ *
+ */
+
+void spl_siemens_memory_full_test(void);
diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig
index 131439f..4ae12b1 100644
--- a/board/siemens/common/Kconfig
+++ b/board/siemens/common/Kconfig
@@ -1,2 +1,6 @@
config FACTORYSET
bool
+
+config DDR_SI_TEST
+ bool "DDR signal integrity test implementations"
+ default y
diff --git a/board/siemens/common/board.h b/board/siemens/common/board.h
new file mode 100644
index 0000000..db34bc7
--- /dev/null
+++ b/board/siemens/common/board.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common board functions for siemens based boards
+ * (C) Copyright 2022 Siemens Schweiz AG
+ */
+
+#ifndef __COMMON_BOARD_H
+#define __COMMON_BOARD_H
+
+/*
+ * Chip data
+ * Offset in EEPROM: 0x120 - 0x14F
+ *
+ * -----------------------------------------------------------------------------------
+ * | Address range | Content |
+ * -----------------------------------------------------------------------------------
+ * | 0x120 - 0x123 | Magic Number - 0x43484950 (4 byte) |
+ * -----------------------------------------------------------------------------------
+ * | 0x124 - 0x133 | Device Nomenclature (15 + 1 byte) |
+ * -----------------------------------------------------------------------------------
+ * | 0x134 - 0x13A | HW Version of the form "v00.00" (6 + 1 byte) |
+ * | | - First 2 digits: Layout revision (starting from 1) |
+ * | | - Last 2 digits: Assembly variant revision (starting from 1) |
+ * -----------------------------------------------------------------------------------
+ * | 0x13B - 0x13F | Flash Size in Gibit (4 + 1 byte) |
+ * -----------------------------------------------------------------------------------
+ * | 0x140 - 0x144 | Ram Size in Gibit (4 + 1 byte) |
+ * -----------------------------------------------------------------------------------
+ * | 0x145 - 0x14F | Sequence number, equals DMC-code (10 + 1 byte) [OBSOLETE] |
+ * -----------------------------------------------------------------------------------
+ */
+
+#define MAGIC_CHIP 0x50494843
+#define EEPROM_CHIP_OFFSET 0x120
+
+struct chip_data {
+ unsigned int magic;
+ char sdevname[16];
+ char shwver[7];
+ char flash_size[5];
+ char ram_size[5];
+};
+
+#endif /* __COMMON_BOARD_H */
diff --git a/board/siemens/common/ddr_si_test.c b/board/siemens/common/ddr_si_test.c
new file mode 100644
index 0000000..c1f523e
--- /dev/null
+++ b/board/siemens/common/ddr_si_test.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright Siemens AG 2023
+ *
+ * DDR signal integrity test
+ * Check signals on DDR lines
+ * - signals must be as fast as possible and generate long burst
+ * - signals must be unidirectional (to DDR or from DDR only)
+ *
+ * Set pattern: define 2^n 32-bit patterns (up to 4)
+ * Addresses: must be multiple of 16 to avoid checks in loops
+ * Test functions
+ * - write: write pattern to memory area for iteration times
+ * - read: write pattern once to memory area, read for iteration times
+ */
+
+#include <command.h>
+#include <exports.h>
+#include <time.h>
+#if CONFIG_IS_ENABLED(AM33XX)
+#include <asm/arch-am33xx/hardware_am33xx.h>
+#include <asm/arch-am33xx/cpu.h>
+#include <asm/io.h>
+#endif
+
+/* enable some print for debugging */
+#ifdef PR_DEBUG
+ #define PDEBUG(fmt, args...) printf(fmt, ## args)
+#else
+ #define PDEBUG(fmt, args...)
+#endif
+
+/* define 4 32-bit patterns */
+#define MAX_PTN_SIZE (128)
+#define PTN_ARRAY_SIZE (MAX_PTN_SIZE / (8 * sizeof(u32)))
+
+/* define test direction */
+#define DIR_READ 0
+#define DIR_WRITE 1
+
+static union {
+ u64 l[2];
+ u32 s[4];
+ } test_pattern;
+static int num_ptn32;
+
+#if CONFIG_IS_ENABLED(AM33XX)
+static inline void wdt_disable(void)
+{
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ writel(0xAAAA, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+}
+
+static inline void wdt_enable(void)
+{
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ writel(0xBBBB, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ writel(0x4444, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+}
+#else /* ! */
+static inline void wdt_disable(void) {}
+
+static inline void wdt_enable(void) {}
+#endif /* CONFIG_IS_ENABLED(AM33XX) */
+
+static int do_ddr_set_ptn(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int i, n;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+
+ /* number of patterns: 2 exponent */
+ n = argc - 1;
+ if (n > PTN_ARRAY_SIZE || (n & (n - 1)))
+ return CMD_RET_USAGE;
+ num_ptn32 = n;
+
+ /* get patterns */
+ for (i = 0; i < n; i++)
+ test_pattern.s[i] = simple_strtoul(argv[i + 1], NULL, 0);
+
+ printf("Test pattern set\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_ddr_show_ptn(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (!num_ptn32) {
+ printf("No pattern available\n");
+ } else {
+ u32 *buf = test_pattern.s;
+ int len = num_ptn32;
+ int i;
+
+ printf("Pattern: ");
+ for (i = 0 ; i < len; i++)
+ printf("0x%08X ", *buf++);
+
+ printf("\n");
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static void ddr_read32(u64 start_addr, u64 n_word, unsigned long iter)
+{
+ while (iter--) {
+ register volatile u32 *addr = (u32 *)start_addr;
+ register u64 count = n_word;
+
+ while (count) {
+ (void)*addr++;
+ PDEBUG("Read 0x%08X from 0x%p\n", val, addr - 1);
+ count--;
+ }
+ }
+}
+
+static void ddr_read64(u64 start_addr, u64 n_word, unsigned long iter)
+{
+ while (iter--) {
+ register volatile u64 *addr = (u64 *)start_addr;
+ register u64 count = n_word;
+
+ if (num_ptn32 == 4)
+ count *= 2;
+
+ /*
+ * 64 & 128 bit pattern. Increase the nummber of read
+ * commands in the loop to generate longer burst signal
+ */
+ while (count) {
+ (void)*addr++;
+ PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+ (void)*addr++;
+ PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+ (void)*addr++;
+ PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+ (void)*addr++;
+ PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+ (void)*addr++;
+ PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+ (void)*addr++;
+ PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+ (void)*addr++;
+ PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+ (void)*addr++;
+ PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+ /*
+ * underflow cannot happen since n_word = end -
+ * start, end & start addresses are checked to be
+ * multiple of 16
+ */
+ count -= 8;
+ }
+ }
+}
+
+static void ddr_write32(u64 start_addr, u64 n_word, unsigned long iter)
+{
+ while (iter--) {
+ register u32 *addr = (u32 *)start_addr;
+ register u32 ptn = *test_pattern.s;
+ register u64 count = n_word;
+
+ while (count) {
+ PDEBUG("Write 0x%08X to 0x%p\n", ptn, addr);
+ *addr++ = ptn;
+ count--;
+ }
+ }
+}
+
+static void ddr_write64(u64 start_addr, u64 n_word, unsigned long iter)
+{
+ while (iter--) {
+ register u64 *addr = (u64 *)start_addr;
+ register u64 ptnA = test_pattern.l[0];
+ register u64 ptnB = test_pattern.l[1];
+ register u64 count = n_word;
+
+ if (num_ptn32 == 2)
+ ptnB = ptnA;
+ else
+ count *= 2;
+
+ /*
+ * 64 & 128 bit pattern. Increase the nummber of write
+ * commands in the loop to generate longer burst signal
+ */
+ while (count) {
+ PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+ *addr++ = ptnA;
+ PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+ *addr++ = ptnB;
+ PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+ *addr++ = ptnA;
+ PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+ *addr++ = ptnB;
+ PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+ *addr++ = ptnA;
+ PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+ *addr++ = ptnB;
+ PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+ *addr++ = ptnA;
+ PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+ *addr++ = ptnB;
+ /*
+ * underflow cannot happen since n_word = end -
+ * start, end & start addresses are checked to be
+ * multiple of 16
+ */
+ count -= 8;
+ }
+ }
+}
+
+static int do_ddr_si_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ u64 start_addr, end_addr, n_word;
+ u64 ts_start, ts_end;
+ unsigned long iteration, wr_iter;
+ int direction, i;
+
+ if (argc < 3 || argc > 4)
+ return CMD_RET_USAGE;
+
+ /* get arguments */
+ direction = strcmp(argv[0], "read") ? DIR_WRITE : DIR_READ;
+ start_addr = simple_strtoul(argv[1], NULL, 0);
+ end_addr = simple_strtoul(argv[2], NULL, 0);
+ iteration = simple_strtoul(argv[3], NULL, 10);
+
+ n_word = (end_addr - start_addr) / (num_ptn32 * 4);
+ printf("\nDDR signal integrity %s test: start\n", argv[0]);
+ /* checks */
+ if (start_addr & 0xF) {
+ printf("ERROR: start_address should be 16 bytes aligned\n\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (end_addr & 0xF) {
+ printf("ERROR: end_address should be 16 bytes aligned\n\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (start_addr >= end_addr) {
+ printf("ERROR: end_address is not bigger than start_address\n\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (!iteration) {
+ printf("ERROR: no iteration specified\n\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (!num_ptn32) {
+ printf("ERROR: no test pattern specified\n\n");
+ return CMD_RET_USAGE;
+ }
+
+ /* print parameters */
+ printf("start_address = 0x%016llX\n", start_addr);
+ printf("end_address = 0x%016llX\n", end_addr);
+ printf("iterations = %lu\n", iteration);
+
+ /* print pattern */
+ printf("test pattern 0x");
+ for (i = 0; i < num_ptn32; i++)
+ printf("%08X", test_pattern.s[i]);
+
+ printf("\n");
+
+ wdt_disable();
+
+ /* writing */
+ printf("Writing..\n");
+ ts_start = get_timer_us(0);
+
+ if (direction == DIR_READ)
+ wr_iter = 1;
+ else
+ wr_iter = iteration;
+
+ if (num_ptn32 == 1)
+ ddr_write32(start_addr, n_word, wr_iter);
+ else
+ ddr_write64(start_addr, n_word, wr_iter);
+
+ ts_end = get_timer_us(0);
+
+ /* reading */
+ if (direction == DIR_READ) {
+ printf("Reading..\n");
+ /* we need read time, just overwrite */
+ ts_start = get_timer_us(0);
+
+ if (num_ptn32 == 1)
+ ddr_read32(start_addr, n_word, iteration);
+ else
+ ddr_read64(start_addr, n_word, iteration);
+
+ ts_end = get_timer_us(0);
+ }
+
+ wdt_enable();
+
+ /* print stats */
+ printf("DONE.");
+ printf(" Bytes=%llu ", n_word * num_ptn32 * 4 * iteration);
+ printf(" Time=%llu us ", ts_end - ts_start);
+ printf("\nDDR signal integrity %s test: end\n", argv[0]);
+
+ return CMD_RET_SUCCESS;
+}
+
+static char ddr_si_help_text[] =
+ "- DDR signal integrity test\n\n"
+ "ddr_si setptn <pattern> [<pattern>] : set [1,2,4] 32-bit patterns\n"
+ "ddr_si showptn : show patterns\n"
+ "ddr_si read <start> <end> <iterations> : run test for reading\n"
+ "ddr_si write <start> <end> <iterations> : run test for writing\n"
+ "\nWith\n"
+ "\t<pattern>: 32-bit pattern in hex format\n"
+ "\t<start>: test start address in hex format\n"
+ "\t<end>: test end address in hex format\n"
+ "\t<iterations>: number of iterations\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(ddr_si, "DDR si test", ddr_si_help_text,
+ U_BOOT_SUBCMD_MKENT(setptn, 5, 0, do_ddr_set_ptn),
+ U_BOOT_SUBCMD_MKENT(showptn, 1, 0, do_ddr_show_ptn),
+ U_BOOT_SUBCMD_MKENT(read, 4, 0, do_ddr_si_test),
+ U_BOOT_SUBCMD_MKENT(write, 4, 0, do_ddr_si_test));
diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h
index 935f340..77f35a6 100644
--- a/board/siemens/draco/board.h
+++ b/board/siemens/draco/board.h
@@ -11,6 +11,8 @@
#ifndef _BOARD_DRACO_H_
#define _BOARD_DRACO_H_
+#include "../common/board.h"
+
#define PARGS(x) #x , /* Parameter Name */ \
settings.ddr3.x, /* EEPROM Value */ \
ddr3_default.x, /* Default Value */ \
@@ -18,8 +20,6 @@
#define PRINTARGS(y) printf("%-20s, %8x, %8x, %4d\n", PARGS(y))
-#define MAGIC_CHIP 0x50494843
-
/* Automatic generated definition */
/* Wed, 16 Apr 2014 16:50:41 +0200 */
/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
@@ -43,12 +43,6 @@
char manu_marking[32]; /* "default \0" */
};
-struct chip_data {
- unsigned int magic;
- char sdevname[16];
- char shwver[7];
-};
-
struct draco_baseboard_id {
struct ddr3_data ddr3;
struct chip_data chip;
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index e9269ef..b543bf8 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -385,7 +385,7 @@
int phy_addr = -ENOENT;
#ifdef CONFIG_FEC_MXC
- bus = fec_get_miibus(ENET_BASE_ADDR, -1);
+ bus = fec_get_miibus(NULL, ENET_BASE_ADDR, -1);
if (!bus)
return -ENOENT;
diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env
index 97122fb..96d9e1e 100644
--- a/board/ti/am62ax/am62ax.env
+++ b/board/ti/am62ax/am62ax.env
@@ -1,5 +1,6 @@
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC
#include <env/ti/k3_rproc.env>
#endif
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index de44e4d..821f02b 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -41,6 +41,7 @@
imply CMD_I2C
imply CMD_MII
imply CMD_MMC
+ imply CMD_NFS
imply CMD_PART
imply CMD_PING
imply CMD_PMIC if DM_PMIC
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 2cfeb3b..9bcf67b 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -326,4 +326,27 @@
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ESM_K3)) {
+ const char * const esms[] = {"esm@700000", "esm@40800000", "esm@42080000"};
+
+ for (int i = 0; i < ARRAY_SIZE(esms); ++i) {
+ ret = uclass_get_device_by_name(UCLASS_MISC, esms[i],
+ &dev);
+ if (ret) {
+ printf("MISC init for %s failed: %d\n", esms[i], ret);
+ break;
+ }
+ }
+ }
+
+ if (IS_ENABLED(CONFIG_ESM_PMIC) && ret == 0) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(pmic_esm),
+ &dev);
+ if (ret)
+ printf("ESM PMIC init failed: %d\n", ret);
+ }
}
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index a6e3c6a..0fb49fc 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -70,97 +70,95 @@
#define TARGET_IS_ENABLED(x) IS_ENABLED(CONFIG_TARGET_ ## x)
const struct toradex_som toradex_modules[] = {
- [0] = { "UNKNOWN MODULE", 0 },
- [1] = { "Colibri PXA270 312MHz", 0 },
- [2] = { "Colibri PXA270 520MHz", 0 },
- [3] = { "Colibri PXA320 806MHz", 0 },
- [4] = { "Colibri PXA300 208MHz", 0 },
- [5] = { "Colibri PXA310 624MHz", 0 },
- [6] = { "Colibri PXA320IT 806MHz", 0 },
- [7] = { "Colibri PXA300 208MHz XT", 0 },
- [8] = { "Colibri PXA270 312MHz", 0 },
- [9] = { "Colibri PXA270 520MHz", 0 },
- [10] = { "Colibri VF50 128MB", TARGET_IS_ENABLED(COLIBRI_VF) },
- [11] = { "Colibri VF61 256MB", TARGET_IS_ENABLED(COLIBRI_VF) },
- [12] = { "Colibri VF61 256MB IT", TARGET_IS_ENABLED(COLIBRI_VF) },
- [13] = { "Colibri VF50 128MB IT", TARGET_IS_ENABLED(COLIBRI_VF) },
- [14] = { "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) },
- [15] = { "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) },
- [16] = { "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) },
- [17] = { "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) },
- [18] = { "UNKNOWN MODULE", 0 },
- [19] = { "UNKNOWN MODULE", 0 },
- [20] = { "Colibri T20 256MB", TARGET_IS_ENABLED(COLIBRI_T20) },
- [21] = { "Colibri T20 512MB", TARGET_IS_ENABLED(COLIBRI_T20) },
- [22] = { "Colibri T20 512MB IT", TARGET_IS_ENABLED(COLIBRI_T20) },
- [23] = { "Colibri T30 1GB", TARGET_IS_ENABLED(COLIBRI_T30) },
- [24] = { "Colibri T20 256MB IT", TARGET_IS_ENABLED(COLIBRI_T20) },
- [25] = { "Apalis T30 2GB", TARGET_IS_ENABLED(APALIS_T30) },
- [26] = { "Apalis T30 1GB", TARGET_IS_ENABLED(APALIS_T30) },
- [27] = { "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) },
- [28] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
- [29] = { "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) },
- [30] = { "Colibri T30 1GB IT", TARGET_IS_ENABLED(COLIBRI_T30) },
- [31] = { "Apalis T30 1GB IT", TARGET_IS_ENABLED(APALIS_T30) },
- [32] = { "Colibri iMX7S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX7) },
- [33] = { "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) },
- [34] = { "Apalis TK1 2GB", TARGET_IS_ENABLED(APALIS_TK1) },
- [35] = { "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
- [36] = { "Colibri iMX6ULL 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
- [37] = { "Apalis iMX8QM 4GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
- [38] = { "Colibri iMX8QXP 2GB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) },
- [39] = { "Colibri iMX7D 1GB", TARGET_IS_ENABLED(COLIBRI_IMX7) },
- [40] = { "Colibri iMX6ULL 512MB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
- [41] = { "Colibri iMX7D 512MB EPDC", TARGET_IS_ENABLED(COLIBRI_IMX7) },
- [42] = { "Apalis TK1 4GB", TARGET_IS_ENABLED(APALIS_TK1) },
- [43] = { "Colibri T20 512MB IT SETEK", TARGET_IS_ENABLED(COLIBRI_T20) },
- [44] = { "Colibri iMX6ULL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
- [45] = { "Colibri iMX6ULL 512MB WB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
- [46] = { "Apalis iMX8QXP 2GB WB IT", 0 },
- [47] = { "Apalis iMX8QM 4GB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
- [48] = { "Apalis iMX8QP 2GB WB", TARGET_IS_ENABLED(APALIS_IMX8) },
- [49] = { "Apalis iMX8QP 2GB", TARGET_IS_ENABLED(APALIS_IMX8) },
- [50] = { "Colibri iMX8QXP 2GB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) },
- [51] = { "Colibri iMX8DX 1GB WB", TARGET_IS_ENABLED(COLIBRI_IMX8X) },
- [52] = { "Colibri iMX8DX 1GB", TARGET_IS_ENABLED(COLIBRI_IMX8X) },
- [53] = { "Apalis iMX8QXP 2GB ECC IT", 0 },
- [54] = { "Apalis iMX8DXP 1GB", TARGET_IS_ENABLED(APALIS_IMX8) },
- [55] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
- [56] = { "Verdin iMX8M Nano Quad 1GB WB", 0 },
- [57] = { "Verdin iMX8M Mini DualLite 1GB", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
- [58] = { "Verdin iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
- [59] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
- [60] = { "Verdin iMX8M Mini DualLite 1GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
- [61] = { "Verdin iMX8M Plus Quad 2GB", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
- [62] = { "Colibri iMX6ULL 1GB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
- [63] = { "Verdin iMX8M Plus Quad 4GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
- [64] = { "Verdin iMX8M Plus Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
- [65] = { "Verdin iMX8M Plus QuadLite 1GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
- [66] = { "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
- [67] = { "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
- [68] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
- [69] = { "Verdin AM62 Quad 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
- [70] = { "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
- [71] = { "Verdin AM62 Solo 512MB", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
- [72] = { "Verdin AM62 Solo 512MB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
- [73] = { "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
- [74] = { "Verdin AM62 Dual 1GB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
- [75] = { "Verdin AM62 Dual 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
- [76] = { "Verdin AM62 Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
- [77] = { "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) },
- [78] = { "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) },
- [79] = { "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) },
- [80] = { "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) },
- [81] = { "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) },
- [82] = { "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) },
- [83] = { "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) },
- [84] = { "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
- [85] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
- [86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
- [87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
- [88] = { "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
- [89] = { "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) },
- [90] = { "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ { 0, "UNKNOWN MODULE", 0 },
+ { COLIBRI_PXA270_V1_312MHZ, "Colibri PXA270 312MHz", 0 },
+ { COLIBRI_PXA270_V1_520MHZ, "Colibri PXA270 520MHz", 0 },
+ { COLIBRI_PXA320, "Colibri PXA320 806MHz", 0 },
+ { COLIBRI_PXA300, "Colibri PXA300 208MHz", 0 },
+ { COLIBRI_PXA310, "Colibri PXA310 624MHz", 0 },
+ { COLIBRI_PXA320_IT, "Colibri PXA320IT 806MHz", 0 },
+ { COLIBRI_PXA300_XT, "Colibri PXA300 208MHz XT", 0 },
+ { COLIBRI_PXA270_312MHZ, "Colibri PXA270 312MHz", 0 },
+ { COLIBRI_PXA270_520MHZ, "Colibri PXA270 520MHz", 0 },
+ { COLIBRI_VF50, "Colibri VF50 128MB", TARGET_IS_ENABLED(COLIBRI_VF) },
+ { COLIBRI_VF61, "Colibri VF61 256MB", TARGET_IS_ENABLED(COLIBRI_VF) },
+ { COLIBRI_VF61_IT, "Colibri VF61 256MB IT", TARGET_IS_ENABLED(COLIBRI_VF) },
+ { COLIBRI_VF50_IT, "Colibri VF50 128MB IT", TARGET_IS_ENABLED(COLIBRI_VF) },
+ { COLIBRI_IMX6S, "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) },
+ { COLIBRI_IMX6DL, "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) },
+ { COLIBRI_IMX6S_IT, "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) },
+ { COLIBRI_IMX6DL_IT, "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) },
+ { COLIBRI_T20_256MB, "Colibri T20 256MB", TARGET_IS_ENABLED(COLIBRI_T20) },
+ { COLIBRI_T20_512MB, "Colibri T20 512MB", TARGET_IS_ENABLED(COLIBRI_T20) },
+ { COLIBRI_T20_512MB_IT, "Colibri T20 512MB IT", TARGET_IS_ENABLED(COLIBRI_T20) },
+ { COLIBRI_T30, "Colibri T30 1GB", TARGET_IS_ENABLED(COLIBRI_T30) },
+ { COLIBRI_T20_256MB_IT, "Colibri T20 256MB IT", TARGET_IS_ENABLED(COLIBRI_T20) },
+ { APALIS_T30_2GB, "Apalis T30 2GB", TARGET_IS_ENABLED(APALIS_T30) },
+ { APALIS_T30_1GB, "Apalis T30 1GB", TARGET_IS_ENABLED(APALIS_T30) },
+ { APALIS_IMX6Q, "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) },
+ { APALIS_IMX6Q_IT, "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
+ { APALIS_IMX6D, "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) },
+ { COLIBRI_T30_IT, "Colibri T30 1GB IT", TARGET_IS_ENABLED(COLIBRI_T30) },
+ { APALIS_T30_IT, "Apalis T30 1GB IT", TARGET_IS_ENABLED(APALIS_T30) },
+ { COLIBRI_IMX7S, "Colibri iMX7S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX7) },
+ { COLIBRI_IMX7D, "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) },
+ { APALIS_TK1_2GB, "Apalis TK1 2GB", TARGET_IS_ENABLED(APALIS_TK1) },
+ { APALIS_IMX6D_IT, "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
+ { COLIBRI_IMX6ULL, "Colibri iMX6ULL 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+ { APALIS_IMX8QM_WIFI_BT_IT, "Apalis iMX8QM 4GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
+ { COLIBRI_IMX8QXP_WIFI_BT_IT, "Colibri iMX8QXP 2GB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) },
+ { COLIBRI_IMX7D_EMMC, "Colibri iMX7D 1GB", TARGET_IS_ENABLED(COLIBRI_IMX7) },
+ { COLIBRI_IMX6ULL_WIFI_BT_IT, "Colibri iMX6ULL 512MB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+ { COLIBRI_IMX7D_EPDC, "Colibri iMX7D 512MB EPDC", TARGET_IS_ENABLED(COLIBRI_IMX7) },
+ { APALIS_TK1_4GB, "Apalis TK1 4GB", TARGET_IS_ENABLED(APALIS_TK1) },
+ { COLIBRI_T20_512MB_IT_SETEK, "Colibri T20 512MB IT SETEK", TARGET_IS_ENABLED(COLIBRI_T20) },
+ { COLIBRI_IMX6ULL_IT, "Colibri iMX6ULL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+ { COLIBRI_IMX6ULL_WIFI_BT, "Colibri iMX6ULL 512MB WB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+ { APALIS_IMX8QXP_WIFI_BT_IT, "Apalis iMX8QXP 2GB WB IT", 0 },
+ { APALIS_IMX8QM_IT, "Apalis iMX8QM 4GB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
+ { APALIS_IMX8QP_WIFI_BT, "Apalis iMX8QP 2GB WB", TARGET_IS_ENABLED(APALIS_IMX8) },
+ { APALIS_IMX8QP, "Apalis iMX8QP 2GB", TARGET_IS_ENABLED(APALIS_IMX8) },
+ { COLIBRI_IMX8QXP_IT, "Colibri iMX8QXP 2GB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) },
+ { COLIBRI_IMX8DX_WIFI_BT, "Colibri iMX8DX 1GB WB", TARGET_IS_ENABLED(COLIBRI_IMX8X) },
+ { COLIBRI_IMX8DX, "Colibri iMX8DX 1GB", TARGET_IS_ENABLED(COLIBRI_IMX8X) },
+ { APALIS_IMX8QXP, "Apalis iMX8QXP 2GB ECC IT", 0 },
+ { APALIS_IMX8DXP, "Apalis iMX8DXP 1GB", TARGET_IS_ENABLED(APALIS_IMX8) },
+ { VERDIN_IMX8MMQ_WIFI_BT_IT, "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ { VERDIN_IMX8MNQ_WIFI_BT, "Verdin iMX8M Nano Quad 1GB WB", 0 },
+ { VERDIN_IMX8MMDL, "Verdin iMX8M Mini DualLite 1GB", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ { VERDIN_IMX8MPQ_WIFI_BT_IT, "Verdin iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
+ { VERDIN_IMX8MMQ_IT, "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ { VERDIN_IMX8MMDL_WIFI_BT_IT, "Verdin iMX8M Mini DualLite 1GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ { VERDIN_IMX8MPQ, "Verdin iMX8M Plus Quad 2GB", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
+ { COLIBRI_IMX6ULL_IT_EMMC, "Colibri iMX6ULL 1GB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+ { VERDIN_IMX8MPQ_IT, "Verdin iMX8M Plus Quad 4GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
+ { VERDIN_IMX8MPQ_2GB_WIFI_BT_IT, "Verdin iMX8M Plus Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
+ { VERDIN_IMX8MPQL_IT, "Verdin iMX8M Plus QuadLite 1GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
+ { VERDIN_IMX8MPQ_8GB_WIFI_BT, "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
+ { APALIS_IMX8QM_8GB_WIFI_BT_IT, "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
+ { VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN, "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ { VERDIN_AM62Q_WIFI_BT_IT, "Verdin AM62 Quad 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ { VERDIN_IMX8MPQ_8GB_WIFI_BT_IT, "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
+ { VERDIN_AM62S_512MB, "Verdin AM62 Solo 512MB", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ { VERDIN_AM62S_512MB_WIFI_BT_IT, "Verdin AM62 Solo 512MB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ { VERDIN_AM62D_1G_ET, "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ { VERDIN_AM62D_1G_IT, "Verdin AM62 Dual 1GB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ { VERDIN_AM62D_1G_WIFI_BT_IT, "Verdin AM62 Dual 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ { VERDIN_AM62Q_2G_WIFI_BT_IT, "Verdin AM62 Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+ { COLIBRI_IMX6S_NOWINCE, "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) },
+ { COLIBRI_IMX6S_IT_NOWINCE, "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) },
+ { COLIBRI_IMX6DL_NOWINCE, "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) },
+ { COLIBRI_IMX6DL_IT_NOWINCE, "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) },
+ { COLIBRI_IMX7D_NOWINCE, "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) },
+ { APALIS_IMX6D_NOWINCE, "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) },
+ { APALIS_IMX6Q_NOWINCE, "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) },
+ { APALIS_IMX6D_IT_NOWINCE, "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
+ { APALIS_IMX6Q_IT_NOWINCE, "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) },
+ { VERDIN_IMX8MMDL_2G_IT, "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ { VERDIN_IMX8MMQ_2G_IT_NO_CAN, "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
+ { AQUILA_AM69O_32G_WIFI_BT_IT, "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
+ { VERDIN_IMX95H_16G_WIFI_BT_IT, "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) },
+ { VERDIN_IMX8MMQ_4G_WIFI_BT_ET, "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
};
struct pid4list {
@@ -188,6 +186,20 @@
[1] = 0x8c06cbUL,
};
+int get_toradex_modules_idx(int pid4)
+{
+ int i, index = 0;
+
+ for (i = 1; i < ARRAY_SIZE(toradex_modules); i++) {
+ if (pid4 == toradex_modules[i].pid4) {
+ index = i;
+ break;
+ }
+ }
+
+ return index;
+}
+
const char * const get_toradex_carrier_boards(int pid4)
{
int i, index = 0;
@@ -361,7 +373,7 @@
int read_tdx_cfg_block(void)
{
- int ret = 0;
+ int idx, ret = 0;
u8 *config_block = NULL;
struct toradex_tag *tag;
size_t size = TDX_CFG_BLOCK_MAX_SIZE;
@@ -430,7 +442,8 @@
}
/* Cap product id to avoid issues with a yet unknown one */
- if (tdx_hw_tag.prodid >= ARRAY_SIZE(toradex_modules))
+ idx = get_toradex_modules_idx(tdx_hw_tag.prodid);
+ if (!toradex_modules[idx].pid4)
tdx_hw_tag.prodid = 0;
out:
@@ -456,19 +469,21 @@
int len = 0;
int ret = 0;
unsigned int prodid;
- int i;
+ int i, idx;
printf("Enabled modules:\n");
for (i = 0; i < ARRAY_SIZE(toradex_modules); i++) {
if (toradex_modules[i].is_enabled)
- printf(" %04d %s\n", i, toradex_modules[i].name);
+ printf(" %04d %s\n", toradex_modules[i].pid4,
+ toradex_modules[i].name);
}
sprintf(message, "Enter the module ID: ");
len = cli_readline(message);
prodid = dectoul(console_buffer, NULL);
- if (prodid >= ARRAY_SIZE(toradex_modules) || !toradex_modules[prodid].is_enabled) {
+ idx = get_toradex_modules_idx(prodid);
+ if (!toradex_modules[idx].pid4 || !toradex_modules[idx].is_enabled) {
printf("Parsing module id failed\n");
return -1;
}
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 0d6dd1c..937e84c 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -21,6 +21,7 @@
} __attribute__((__packed__));
struct toradex_som {
+ int pid4;
const char *name;
int is_enabled;
};
@@ -139,6 +140,7 @@
int read_tdx_cfg_block(void);
int read_tdx_cfg_block_carrier(void);
+int get_toradex_modules_idx(int pid4);
const char * const get_toradex_carrier_boards(int pid4);
const char * const get_toradex_display_adapters(int pid4);
int try_migrate_tdx_cfg_block_carrier(void);
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index a6b45cd..f01fb36 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -191,13 +191,16 @@
static int tdx_get_str(struct udevice *dev, int id, size_t size, char *val)
{
int ret = -ENOTSUPP;
+ int idx;
switch (id) {
- case SYSINFO_ID_BOARD_MODEL:
+ case SYSID_BOARD_MODEL:
+ idx = get_toradex_modules_idx(tdx_hw_tag.prodid);
+
snprintf(val, size,
"Toradex %04d %s %s",
tdx_hw_tag.prodid,
- toradex_modules[tdx_hw_tag.prodid].name,
+ toradex_modules[idx].name,
tdx_board_rev_str);
ret = 0;
diff --git a/boot/Kconfig b/boot/Kconfig
index 7dd30a0..99dcedc 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -283,21 +283,6 @@
injected into the FIT creation (i.e. the blobs would have been pre-
processed before being added to the FIT image).
-config USE_SPL_FIT_GENERATOR
- bool "Use a script to generate the .its script"
- depends on SPL_FIT
- default y if SPL_FIT && ARCH_ZYNQMP
-
-config SPL_FIT_GENERATOR
- string ".its file generator script for U-Boot FIT image"
- depends on USE_SPL_FIT_GENERATOR
- default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP
- help
- Specifies a (platform specific) script file to generate the FIT
- source file used to build the U-Boot FIT image file. This gets
- passed a list of supported device tree file stub names to
- include in the generated image.
-
if VPL
config VPL_FIT
@@ -500,7 +485,6 @@
bool "Bootdev support for Android"
depends on X86 || ARM || SANDBOX
depends on CMDLINE
- select ANDROID_AB
select ANDROID_BOOT_IMAGE
select CMD_BCB
imply CMD_FASTBOOT
diff --git a/boot/bootmeth_android.c b/boot/bootmeth_android.c
index 19b1f2c..3a5144a 100644
--- a/boot/bootmeth_android.c
+++ b/boot/bootmeth_android.c
@@ -29,6 +29,7 @@
#define BCB_PART_NAME "misc"
#define BOOT_PART_NAME "boot"
#define VENDOR_BOOT_PART_NAME "vendor_boot"
+#define SLOT_LEN 2
/**
* struct android_priv - Private data
@@ -42,8 +43,10 @@
*/
struct android_priv {
enum android_boot_mode boot_mode;
- char slot[2];
+ char *slot;
u32 header_version;
+ u32 boot_img_size;
+ u32 vendor_boot_img_size;
};
static int android_check(struct udevice *dev, struct bootflow_iter *iter)
@@ -71,7 +74,11 @@
char *buf;
int ret;
- sprintf(partname, BOOT_PART_NAME "_%s", priv->slot);
+ if (priv->slot)
+ sprintf(partname, BOOT_PART_NAME "_%s", priv->slot);
+ else
+ sprintf(partname, BOOT_PART_NAME);
+
ret = part_get_info_by_name(desc, partname, &partition);
if (ret < 0)
return log_msg_ret("part info", ret);
@@ -93,7 +100,13 @@
return log_msg_ret("header", -ENOENT);
}
+ if (!android_image_get_bootimg_size(buf, &priv->boot_img_size)) {
+ free(buf);
+ return log_msg_ret("get bootimg size", -EINVAL);
+ }
+
priv->header_version = ((struct andr_boot_img_hdr_v0 *)buf)->header_version;
+
free(buf);
return 0;
@@ -108,7 +121,11 @@
char *buf;
int ret;
+ if (priv->slot)
+ sprintf(partname, VENDOR_BOOT_PART_NAME "_%s", priv->slot);
+ else
+ sprintf(partname, VENDOR_BOOT_PART_NAME);
+
- sprintf(partname, VENDOR_BOOT_PART_NAME "_%s", priv->slot);
ret = part_get_info_by_name(desc, partname, &partition);
if (ret < 0)
return log_msg_ret("part info", ret);
@@ -129,6 +146,12 @@
free(buf);
return log_msg_ret("header", -ENOENT);
}
+
+ if (!android_image_get_vendor_bootimg_size(buf, &priv->vendor_boot_img_size)) {
+ free(buf);
+ return log_msg_ret("get vendor bootimg size", -EINVAL);
+ }
+
free(buf);
return 0;
@@ -142,6 +165,11 @@
char slot_suffix[3];
int ret;
+ if (!CONFIG_IS_ENABLED(ANDROID_AB)) {
+ priv->slot = NULL;
+ return 0;
+ }
+
ret = part_get_info_by_name(desc, BCB_PART_NAME, &misc);
if (ret < 0)
return log_msg_ret("part", ret);
@@ -150,6 +178,7 @@
if (ret < 0)
return log_msg_ret("slot", ret);
+ priv->slot = malloc(SLOT_LEN);
priv->slot[0] = BOOT_SLOT_NAME(ret);
priv->slot[1] = '\0';
@@ -259,16 +288,12 @@
goto free_priv;
}
- if (priv->header_version != 4) {
- log_debug("only boot.img v4 is supported %u\n", priv->header_version);
- ret = -EINVAL;
- goto free_priv;
- }
-
- ret = scan_vendor_boot_part(bflow->blk, priv);
- if (ret < 0) {
- log_debug("scan vendor_boot failed: err=%d\n", ret);
- goto free_priv;
+ if (priv->header_version >= 3) {
+ ret = scan_vendor_boot_part(bflow->blk, priv);
+ if (ret < 0) {
+ log_debug("scan vendor_boot failed: err=%d\n", ret);
+ goto free_priv;
+ }
}
/*
@@ -278,7 +303,7 @@
configure_serialno(bflow);
configure_bootloader_version(bflow);
- if (priv->boot_mode == ANDROID_BOOT_MODE_NORMAL) {
+ if (priv->boot_mode == ANDROID_BOOT_MODE_NORMAL && priv->slot) {
ret = bootflow_cmdline_set_arg(bflow, "androidboot.force_normal_boot",
"1", false);
if (ret < 0) {
@@ -319,28 +344,44 @@
* @blk: Block device to read
* @name: Partition name to read
* @slot: Nul-terminated slot suffixed to partition name ("a\0" or "b\0")
+ * @image_size: Image size in bytes used when reading the partition
* @addr: Address where the partition content is loaded into
* Return: 0 if OK, negative errno on failure.
*/
static int read_slotted_partition(struct blk_desc *desc, const char *const name,
- const char slot[2], ulong addr)
+ const char slot[2], ulong image_size, ulong addr)
{
struct disk_partition partition;
char partname[PART_NAME_LEN];
+ size_t partname_len;
+ ulong num_blks = DIV_ROUND_UP(image_size, desc->blksz);
int ret;
u32 n;
+ /*
+ * Ensure name fits in partname.
+ * For A/B, it should be <name>_<slot>\0
+ * For non A/B, it should be <name>\0
+ */
+ if (CONFIG_IS_ENABLED(ANDROID_AB))
+ partname_len = PART_NAME_LEN - 2 - 1;
+ else
+ partname_len = PART_NAME_LEN - 1;
+
- /* Ensure name fits in partname it should be: <name>_<slot>\0 */
- if (strlen(name) > (PART_NAME_LEN - 2 - 1))
+ if (strlen(name) > partname_len)
return log_msg_ret("name too long", -EINVAL);
- sprintf(partname, "%s_%s", name, slot);
+ if (slot)
+ sprintf(partname, "%s_%s", name, slot);
+ else
+ sprintf(partname, "%s", name);
+
ret = part_get_info_by_name(desc, partname, &partition);
if (ret < 0)
return log_msg_ret("part", ret);
- n = blk_dread(desc, partition.start, partition.size, map_sysmem(addr, 0));
- if (n < partition.size)
+ n = blk_dread(desc, partition.start, num_blks, map_sysmem(addr, 0));
+ if (n < num_blks)
return log_msg_ret("part read", -EIO);
return 0;
@@ -386,7 +427,7 @@
AvbSlotVerifyData *out_data;
enum avb_boot_state boot_state;
char *extra_args;
- char slot_suffix[3];
+ char slot_suffix[3] = "";
bool unlocked = false;
int ret;
@@ -394,7 +435,8 @@
if (!avb_ops)
return log_msg_ret("avb ops", -ENOMEM);
- sprintf(slot_suffix, "_%s", priv->slot);
+ if (priv->slot)
+ sprintf(slot_suffix, "_%s", priv->slot);
ret = avb_ops->read_is_device_unlocked(avb_ops, &unlocked);
if (ret != AVB_IO_RESULT_OK)
@@ -472,16 +514,22 @@
if (ret < 0)
return log_msg_ret("read slot", ret);
- ret = read_slotted_partition(desc, "boot", priv->slot, loadaddr);
+ ret = read_slotted_partition(desc, "boot", priv->slot, priv->boot_img_size,
+ loadaddr);
if (ret < 0)
return log_msg_ret("read boot", ret);
- ret = read_slotted_partition(desc, "vendor_boot", priv->slot, vloadaddr);
- if (ret < 0)
- return log_msg_ret("read vendor_boot", ret);
-
+ if (priv->header_version >= 3) {
+ ret = read_slotted_partition(desc, "vendor_boot", priv->slot,
+ priv->vendor_boot_img_size, vloadaddr);
+ if (ret < 0)
+ return log_msg_ret("read vendor_boot", ret);
+ set_avendor_bootimg_addr(vloadaddr);
+ }
set_abootimg_addr(loadaddr);
- set_avendor_bootimg_addr(vloadaddr);
+
+ if (priv->slot)
+ free(priv->slot);
ret = bootm_boot_start(loadaddr, bflow->cmdline);
diff --git a/boot/image-android.c b/boot/image-android.c
index cd01278..93b54bf 100644
--- a/boot/image-android.c
+++ b/boot/image-android.c
@@ -178,6 +178,51 @@
data->boot_img_total_size = end - (ulong)hdr;
}
+bool android_image_get_bootimg_size(const void *hdr, u32 *boot_img_size)
+{
+ struct andr_image_data data;
+
+ if (!hdr || !boot_img_size) {
+ printf("hdr or boot_img_size can't be NULL\n");
+ return false;
+ }
+
+ if (!is_android_boot_image_header(hdr)) {
+ printf("Incorrect boot image header\n");
+ return false;
+ }
+
+ if (((struct andr_boot_img_hdr_v0 *)hdr)->header_version <= 2)
+ android_boot_image_v0_v1_v2_parse_hdr(hdr, &data);
+ else
+ android_boot_image_v3_v4_parse_hdr(hdr, &data);
+
+ *boot_img_size = data.boot_img_total_size;
+
+ return true;
+}
+
+bool android_image_get_vendor_bootimg_size(const void *hdr, u32 *vendor_boot_img_size)
+{
+ struct andr_image_data data;
+
+ if (!hdr || !vendor_boot_img_size) {
+ printf("hdr or vendor_boot_img_size can't be NULL\n");
+ return false;
+ }
+
+ if (!is_android_vendor_boot_image_header(hdr)) {
+ printf("Incorrect vendor boot image header\n");
+ return false;
+ }
+
+ android_vendor_boot_image_v3_v4_parse_hdr(hdr, &data);
+
+ *vendor_boot_img_size = data.vendor_boot_img_total_size;
+
+ return true;
+}
+
bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr,
struct andr_image_data *data)
{
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 1d7ddb4..4936a70 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -176,6 +176,13 @@
internal name) and clock frequency. Other information may be
available depending on the CPU driver.
+config CMD_UFETCH
+ bool "U-Boot fetch"
+ depends on BLK
+ help
+ Fetch utility for U-Boot (akin to neofetch). Prints information
+ about U-Boot and the board it is running on in a pleasing format.
+
config CMD_FWU_METADATA
bool "fwu metadata read"
depends on FWU_MULTI_BANK_UPDATE
@@ -2117,11 +2124,8 @@
config CMD_WGET
bool "wget"
- depends on CMD_NET
default y if SANDBOX
- select PROT_TCP if NET
- select PROT_TCP_LWIP if NET_LWIP
- select PROT_DNS_LWIP if NET_LWIP
+ select WGET
help
wget is a simple command to download kernel, or other files,
from a http server over TCP.
diff --git a/cmd/Makefile b/cmd/Makefile
index d1f369d..1e6d312 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -53,6 +53,7 @@
obj-$(CONFIG_CMD_DATE) += date.o
obj-$(CONFIG_CMD_DEMO) += demo.o
obj-$(CONFIG_CMD_DM) += dm.o
+obj-$(CONFIG_CMD_UFETCH) += ufetch.o
obj-$(CONFIG_CMD_SOUND) += sound.o
ifdef CONFIG_POST
obj-$(CONFIG_CMD_DIAG) += diag.o
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 4c0e2ad..ae9e192 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -140,10 +140,6 @@
#endif
bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params);
print_bi_dram(bd);
- if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
- bdinfo_print_num_l("sramstart", (ulong)bd->bi_sramstart);
- bdinfo_print_num_l("sramsize", (ulong)bd->bi_sramsize);
- }
bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart);
bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize);
bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset);
diff --git a/cmd/net.c b/cmd/net.c
index c90578e..79525f7 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -196,6 +196,8 @@
#if defined(CONFIG_CMD_WGET)
static int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
{
+ wget_info = &default_wget_info;
+
return netboot_common(WGET, cmdtp, argc, argv);
}
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 392f90f..1f25980 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -523,6 +523,9 @@
case 'f': /* force */
env_flag |= H_FORCE;
break;
+ case 'k':
+ env_flag |= H_NOCLEAR;
+ break;
default:
return cmd_usage(cmdtp);
}
@@ -1133,8 +1136,9 @@
#if defined(CONFIG_CMD_ENV_CALLBACK)
"callbacks - print callbacks and their associated variables\nenv "
#endif
- "default [-f] -a - [forcibly] reset default environment\n"
- "env default [-f] var [...] - [forcibly] reset variable(s) to their default values\n"
+ "default [-k] [-f] -a - [forcibly] reset default environment\n"
+ "env default [-k] [-f] var [...] - [forcibly] reset variable(s) to their default values\n"
+ " \"-k\": keep variables not defined in default environment\n"
"env delete [-f] var [...] - [forcibly] delete variable(s)\n"
#if defined(CONFIG_CMD_EDITENV)
"env edit name - edit environment variable\n"
diff --git a/cmd/sb.c b/cmd/sb.c
index 9245052..79f3fb0 100644
--- a/cmd/sb.c
+++ b/cmd/sb.c
@@ -15,10 +15,8 @@
char *const argv[])
{
#if CONFIG_IS_ENABLED(HANDOFF)
- struct spl_handoff *handoff = handoff_get();
-
- if (handoff)
- printf("SPL handoff magic %lx\n", handoff->arch.magic);
+ if (gd->spl_handoff)
+ printf("SPL handoff magic %lx\n", gd->spl_handoff->arch.magic);
else
printf("SPL handoff info not received\n");
diff --git a/cmd/ufetch.c b/cmd/ufetch.c
new file mode 100644
index 0000000..0b825d7
--- /dev/null
+++ b/cmd/ufetch.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Small "fetch" utility for U-Boot */
+
+#ifdef CONFIG_ARM64
+#include <asm/system.h>
+#endif
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <display_options.h>
+#include <mmc.h>
+#include <time.h>
+#include <asm/global_data.h>
+#include <cli.h>
+#include <command.h>
+#include <dm/ofnode.h>
+#include <env.h>
+#include <rand.h>
+#include <vsprintf.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LINE_WIDTH 40
+#define BLUE "\033[38;5;4m"
+#define YELLOW "\033[38;5;11m"
+#define BOLD "\033[1m"
+#define RESET "\033[0m"
+static const char * const logo_lines[] = {
+ BLUE BOLD " ......::...... ",
+ BLUE BOLD " ...::::::::::::::::::... ",
+ BLUE BOLD " ..::::::::::::::::::::::::::.. ",
+ BLUE BOLD " .::::.:::::::::::::::...::::.::::. ",
+ BLUE BOLD " .::::::::::::::::::::..::::::::::::::. ",
+ BLUE BOLD " .::.:::::::::::::::::::" YELLOW "=*%#*" BLUE "::::::::::.::. ",
+ BLUE BOLD " .:::::::::::::::::....." YELLOW "*%%*-" BLUE ":....::::::::::. ",
+ BLUE BOLD " .:.:::...:::::::::.:-" YELLOW "===##*---==-" BLUE "::::::::::.:. ",
+ BLUE BOLD " .::::..::::........" YELLOW "-***#****###****-" BLUE "...::::::.:. ",
+ BLUE BOLD " ::.:.-" YELLOW "+***+=" BLUE "::-" YELLOW "=+**#%%%%%%%%%%%%###*= " BLUE "-::...::::. ",
+ BLUE BOLD ".:.::-" YELLOW "*****###%%%%%%%%%%%%%%%%%%%%%%%%%%#*=" BLUE ":..:::: ",
+ BLUE BOLD ".::" YELLOW "##" BLUE ":" YELLOW "***#%%%%%%#####%%%%%%%####%%%%%####%%%*" BLUE "-.::. ",
+ BLUE BOLD ":.:" YELLOW "#%" BLUE "::" YELLOW "*%%%%%%%#*****##%%%#*****##%%##*****#%%+" BLUE ".::.",
+ BLUE BOLD ".::" YELLOW "**==#%%%%%%%##****#%%%%##****#%%%%#****###%%" BLUE ":.. ",
+ BLUE BOLD "..:" YELLOW "#%" BLUE "::" YELLOW "*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%#%%%%%+ " BLUE ".:.",
+ BLUE BOLD " ::" YELLOW "##" BLUE ":" YELLOW "+**#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%* " BLUE "-.:: ",
+ BLUE BOLD " ..::-" YELLOW "#****#%#%%%%%%%%%%%%%%%%%%%%%%%%%%#*=" BLUE "-..::. ",
+ BLUE BOLD " ...:=" YELLOW "*****=" BLUE "::-" YELLOW "=+**###%%%%%%%%###**+= " BLUE "--:...::: ",
+ BLUE BOLD " .::.::--:........::::::--::::::......::::::. ",
+ BLUE BOLD " .::.....::::::::::...........:::::::::.::. ",
+ BLUE BOLD " .::::::::::::::::::::::::::::::::::::. ",
+ BLUE BOLD " .::::.::::::::::::::::::::::.::::. ",
+ BLUE BOLD " ..::::::::::::::::::::::::::.. ",
+ BLUE BOLD " ...::::::::::::::::::... ",
+ BLUE BOLD " ......::...... ",
+};
+
+enum output_lines {
+ FIRST,
+ SECOND,
+ KERNEL,
+ SYSINFO,
+ HOST,
+ UPTIME,
+ IP,
+ CMDS,
+ CONSOLES,
+ FEATURES,
+ RELOCATION,
+ CORES,
+ MEMORY,
+ STORAGE,
+
+ /* Up to 10 storage devices... Should be enough for anyone right? */
+ _LAST_LINE = (STORAGE + 10),
+#define LAST_LINE (_LAST_LINE - 1UL)
+};
+
+/*
+ * TODO/ideas:
+ * - Refactor to not use a for loop
+ * - Handle multiple network interfaces
+ * - Include stats about number of bound/probed devices
+ * - Show U-Boot's size and malloc usage, fdt size, etc.
+ */
+
+
+static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int num_lines = max(LAST_LINE + 1, ARRAY_SIZE(logo_lines));
+ const char *model, *compatible;
+ char *ipaddr;
+ int n_cmds, n_cpus = 0, ret, compatlen;
+ size_t size;
+ ofnode np;
+ struct udevice *dev;
+ struct blk_desc *desc;
+ bool skip_ascii = false;
+
+ if (argc > 1 && strcmp(argv[1], "-n") == 0) {
+ skip_ascii = true;
+ num_lines = LAST_LINE;
+ }
+
+ for (int line = 0; line < num_lines; line++) {
+ if (!skip_ascii) {
+ if (line < ARRAY_SIZE(logo_lines))
+ printf("%s ", logo_lines[line]);
+ else
+ printf("%*c ", LINE_WIDTH, ' ');
+ }
+ switch (line) {
+ case FIRST:
+ compatible = ofnode_read_string(ofnode_root(), "compatible");
+ if (!compatible)
+ compatible = "unknown";
+ printf(RESET "%s\n", compatible);
+ compatlen = strlen(compatible);
+ break;
+ case SECOND:
+ for (int j = 0; j < compatlen; j++)
+ putc('-');
+ putc('\n');
+ break;
+ case KERNEL:
+ printf("Kernel:" RESET " %s\n", U_BOOT_VERSION);
+ break;
+ case SYSINFO:
+ printf("Config:" RESET " %s_defconfig\n", CONFIG_SYS_CONFIG_NAME);
+ break;
+ case HOST:
+ model = ofnode_read_string(ofnode_root(), "model");
+ if (model)
+ printf("Host:" RESET " %s\n", model);
+ break;
+ case UPTIME:
+ printf("Uptime:" RESET " %ld seconds\n", get_timer(0) / 1000);
+ break;
+ case IP:
+ ipaddr = env_get("ipaddr");
+ if (!ipaddr)
+ ipaddr = "none";
+ printf("IP Address:" RESET " %s", ipaddr);
+ ipaddr = env_get("ipv6addr");
+ if (ipaddr)
+ printf(", %s\n", ipaddr);
+ else
+ putc('\n');
+ break;
+ case CMDS:
+ n_cmds = ll_entry_count(struct cmd_tbl, cmd);
+ printf("Commands:" RESET " %d (help)\n", n_cmds);
+ break;
+ case CONSOLES:
+ printf("Consoles:" RESET " %s", env_get("stdout"));
+ if (gd->baudrate)
+ printf(" (%d baud)", gd->baudrate);
+ putc('\n');
+ break;
+ case FEATURES:
+ printf("Features:" RESET " ");
+ if (IS_ENABLED(CONFIG_NET))
+ printf("Net");
+ if (IS_ENABLED(CONFIG_EFI_LOADER))
+ printf(", EFI");
+ if (IS_ENABLED(CONFIG_CMD_CAT))
+ printf(", cat :3");
+#ifdef CONFIG_ARM64
+ switch (current_el()) {
+ case 2:
+ printf(", VMs");
+ break;
+ case 3:
+ printf(", full control!");
+ break;
+ }
+#endif
+ printf("\n");
+ break;
+ case RELOCATION:
+ if (gd->flags & GD_FLG_SKIP_RELOC)
+ printf("Relocated:" RESET " no\n");
+ else
+ printf("Relocated:" RESET " to %#011lx\n", gd->relocaddr);
+ break;
+ case CORES:
+ ofnode_for_each_subnode(np, ofnode_path("/cpus")) {
+ if (ofnode_name_eq(np, "cpu"))
+ n_cpus++;
+ }
+ printf("CPU:" RESET " %d (1 in use)\n", n_cpus);
+ break;
+ case MEMORY:
+ for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->bd->bi_dram[j].size; j++)
+ size += gd->bd->bi_dram[j].size;
+ printf("Memory:" RESET " ");
+ print_size(size, "\n");
+ break;
+ case STORAGE:
+ default:
+ ret = uclass_find_device_by_seq(UCLASS_BLK, line - STORAGE, &dev);
+ if (!ret && dev) {
+ desc = dev_get_uclass_plat(dev);
+ size = desc->lba * desc->blksz;
+ printf("%4s %d: " RESET, blk_get_uclass_name(desc->uclass_id),
+ desc->lun);
+ if (size)
+ print_size(size, "");
+ else
+ printf("No media");
+ } else if (ret == -ENODEV && (skip_ascii || line > ARRAY_SIZE(logo_lines))) {
+ break;
+ }
+ printf("\n");
+ }
+ }
+
+ printf(RESET "\n\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(ufetch, 2, 1, do_ufetch,
+ "U-Boot fetch utility",
+ "Print information about your device.\n"
+ " -n Don't print the ASCII logo"
+);
diff --git a/common/board_f.c b/common/board_f.c
index 98dc259..54c48d4 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -305,6 +305,17 @@
return 0;
}
+static int setup_spl_handoff(void)
+{
+#if CONFIG_IS_ENABLED(HANDOFF)
+ gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
+ sizeof(struct spl_handoff));
+ debug("Found SPL hand-off info %p\n", gd->spl_handoff);
+#endif
+
+ return 0;
+}
+
__weak int arch_cpu_init(void)
{
return 0;
@@ -637,13 +648,6 @@
int setup_bdinfo(void)
{
- struct bd_info *bd = gd->bd;
-
- if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
- bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
- bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
- }
-
return arch_setup_bdinfo();
}
@@ -880,6 +884,7 @@
initf_bootstage, /* uses its own timer, so does not need DM */
event_init,
bloblist_maybe_init,
+ setup_spl_handoff,
#if defined(CONFIG_CONSOLE_RECORD_INIT_F)
console_record_init,
#endif
diff --git a/common/board_info.c b/common/board_info.c
index 33c260b..dc26e1a 100644
--- a/common/board_info.c
+++ b/common/board_info.c
@@ -18,9 +18,9 @@
const char *name;
enum sysinfo_id id;
} to_show[] = {
- { "Manufacturer", SYSINFO_ID_BOARD_MANUFACTURER},
- { "Prior-stage version", SYSINFO_ID_PRIOR_STAGE_VERSION },
- { "Prior-stage date", SYSINFO_ID_PRIOR_STAGE_DATE },
+ { "Manufacturer", SYSID_BOARD_MANUFACTURER},
+ { "Prior-stage version", SYSID_PRIOR_STAGE_VERSION },
+ { "Prior-stage date", SYSID_PRIOR_STAGE_DATE },
{ /* sentinel */ }
};
@@ -39,7 +39,7 @@
if (ret)
return ret;
- ret = sysinfo_get_str(dev, SYSINFO_ID_BOARD_MODEL, sizeof(str), str);
+ ret = sysinfo_get_str(dev, SYSID_BOARD_MODEL, sizeof(str), str);
if (ret)
return ret;
printf("Model: %s\n", str);
diff --git a/common/board_r.c b/common/board_r.c
index 62228a7..23ebc41 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -152,6 +152,15 @@
*/
gd->env_addr += gd->reloc_off;
#endif
+
+ /*
+ * For CONFIG_OF_EMBED case the FDT is embedded into ELF, available by
+ * __dtb_dt_begin. After U-boot ELF self-relocation to RAM top address
+ * it is worth to update fdt_blob in global_data
+ */
+ if (IS_ENABLED(CONFIG_OF_EMBED))
+ gd->fdt_blob = dtb_dt_embedded();
+
#ifdef CONFIG_EFI_LOADER
/*
* On the ARM architecture gd is mapped to a fixed register (r9 or x18).
@@ -287,13 +296,10 @@
return 0;
}
-static int initr_binman(void)
+static int __maybe_unused initr_binman(void)
{
int ret;
- if (!CONFIG_IS_ENABLED(BINMAN_FDT))
- return 0;
-
ret = binman_init();
if (ret)
printf("binman_init failed:%d\n", ret);
@@ -635,7 +641,9 @@
#ifdef CONFIG_EFI_LOADER
efi_memory_init,
#endif
+#ifdef CONFIG_BINMAN_FDT
initr_binman,
+#endif
#ifdef CONFIG_FSP_VERSION2
arch_fsp_init_r,
#endif
diff --git a/common/console.c b/common/console.c
index 2222470..863ac6a 100644
--- a/common/console.c
+++ b/common/console.c
@@ -745,11 +745,7 @@
}
if (IS_ENABLED(CONFIG_DEBUG_UART) && !(gd->flags & GD_FLG_SERIAL_READY)) {
- while (*s) {
- int ch = *s++;
-
- printch(ch);
- }
+ printascii(s);
return;
}
diff --git a/common/init/handoff.c b/common/init/handoff.c
index 86c020e..a7cd065 100644
--- a/common/init/handoff.c
+++ b/common/init/handoff.c
@@ -5,7 +5,6 @@
* Copyright 2018 Google, Inc
*/
-#include <bloblist.h>
#include <handoff.h>
#include <asm/global_data.h>
@@ -39,14 +38,3 @@
bd->bi_dram[i].size = ho->ram_bank[i].size;
}
}
-
-struct spl_handoff *handoff_get(void)
-{
- struct spl_handoff *handoff;
-
- handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
- sizeof(struct spl_handoff));
- debug("Found SPL hand-off info %p\n", handoff);
-
- return handoff;
-}
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index a93c33c..a0eaa12 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -89,6 +89,7 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
+CONFIG_K3_QOS=y
CONFIG_K3_SEC_PROXY=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/am62x_a53_android.config b/configs/am62x_a53_android.config
index adbe2b8..2aca51e 100644
--- a/configs/am62x_a53_android.config
+++ b/configs/am62x_a53_android.config
@@ -11,6 +11,7 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
# Enable Android boot flow
CONFIG_BOOTMETH_ANDROID=y
+CONFIG_ANDROID_AB=y
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_MALLOC_LEN=0x08000000
CONFIG_AVB_VERIFY=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index cf7a211..b6df8b4 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -14,7 +14,7 @@
CONFIG_ENV_OFFSET=0x680000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am654-base-board"
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -76,6 +76,7 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_OVERLAY_LIST="ti/k3-am654-icssg2"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
diff --git a/configs/am68_sk_r5_defconfig b/configs/am68_sk_r5_defconfig
index f4800ef..097bed6 100644
--- a/configs/am68_sk_r5_defconfig
+++ b/configs/am68_sk_r5_defconfig
@@ -5,10 +5,14 @@
CONFIG_SOC_K3_J721S2=y
CONFIG_TARGET_J721S2_R5_EVM=y
+CONFIG_ESM_K3=n
CONFIG_K3_AVS0=n
+CONFIG_ESM_PMIC=n
CONFIG_DM_REGULATOR_TPS65941=n
CONFIG_PMIC_TPS65941=n
+CONFIG_SPL_DM_REGULATOR_TPS6287X=y
+
CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board"
CONFIG_SPL_OF_LIST="k3-am68-sk-r5-base-board"
CONFIG_OF_LIST="k3-am68-sk-r5-base-board"
diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig
index 08e6077..b4aebf3 100644
--- a/configs/amd_versal2_virt_defconfig
+++ b/configs/amd_versal2_virt_defconfig
@@ -130,6 +130,8 @@
CONFIG_CADENCE_OSPI_VERSAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
CONFIG_TPM2_TIS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
@@ -151,3 +153,4 @@
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
CONFIG_TPM=y
+# CONFIG_OPTEE_LIB is not set
diff --git a/configs/bcm947622_defconfig b/configs/bcm947622_defconfig
index cf0651c..566f9f2 100644
--- a/configs/bcm947622_defconfig
+++ b/configs/bcm947622_defconfig
@@ -18,10 +18,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm94912_defconfig b/configs/bcm94912_defconfig
index bce823b..46bbfb6 100644
--- a/configs/bcm94912_defconfig
+++ b/configs/bcm94912_defconfig
@@ -18,10 +18,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm963146_defconfig b/configs/bcm963146_defconfig
index 691d055..239a8a1 100644
--- a/configs/bcm963146_defconfig
+++ b/configs/bcm963146_defconfig
@@ -18,10 +18,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm963158_defconfig b/configs/bcm963158_defconfig
index 6e4a85e..a6cfea6 100644
--- a/configs/bcm963158_defconfig
+++ b/configs/bcm963158_defconfig
@@ -18,10 +18,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm963178_defconfig b/configs/bcm963178_defconfig
index 60a1987..95c9c8e 100644
--- a/configs/bcm963178_defconfig
+++ b/configs/bcm963178_defconfig
@@ -19,10 +19,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm96756_defconfig b/configs/bcm96756_defconfig
index 4b1fa99..bfd309c 100644
--- a/configs/bcm96756_defconfig
+++ b/configs/bcm96756_defconfig
@@ -19,10 +19,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm96813_defconfig b/configs/bcm96813_defconfig
index 553bdc1..7f16523 100644
--- a/configs/bcm96813_defconfig
+++ b/configs/bcm96813_defconfig
@@ -18,10 +18,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig
index ff6dff0..342be0a 100644
--- a/configs/bcm96855_defconfig
+++ b/configs/bcm96855_defconfig
@@ -19,10 +19,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm96856_defconfig b/configs/bcm96856_defconfig
index 7c6fba2..5f22186 100644
--- a/configs/bcm96856_defconfig
+++ b/configs/bcm96856_defconfig
@@ -18,10 +18,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm96858_defconfig b/configs/bcm96858_defconfig
index 3e11b40..682cb14 100644
--- a/configs/bcm96858_defconfig
+++ b/configs/bcm96858_defconfig
@@ -18,10 +18,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/bcm96878_defconfig b/configs/bcm96878_defconfig
index 52c869a..ad65187 100644
--- a/configs/bcm96878_defconfig
+++ b/configs/bcm96878_defconfig
@@ -19,10 +19,7 @@
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_UPSTREAM=y
CONFIG_OF_EMBED=y
-CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/deneb_defconfig b/configs/capricorn_cxg3_defconfig
similarity index 88%
rename from configs/deneb_defconfig
rename to configs/capricorn_cxg3_defconfig
index 98841bb..2764455 100644
--- a/configs/deneb_defconfig
+++ b/configs/capricorn_cxg3_defconfig
@@ -10,10 +10,11 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
+CONFIG_ENV_OFFSET=0x200000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb"
-CONFIG_TARGET_DENEB=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8-capricorn-cxg3"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_CAPRICORN=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
@@ -25,7 +26,7 @@
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x2000
+CONFIG_ENV_OFFSET_REDUND=0x202000
CONFIG_IDENT_STRING=" ##v01.06"
CONFIG_REMAKE_ELF=y
# CONFIG_EFI_LOADER is not set
@@ -55,9 +56,10 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x4000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
@@ -112,10 +114,13 @@
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=5
CONFIG_MV88E61XX_PHY_PORTS=0x7
+CONFIG_DM_ETH_PHY=y
CONFIG_FEC_MXC_SHARE_MDIO=y
CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_NOP_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8=y
@@ -129,5 +134,7 @@
CONFIG_FSL_LPUART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_SCU_THERMAL=y
-# CONFIG_SPL_WDT is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_WDT=y
+CONFIG_WDT_SIEMENS_PMIC=y
CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/dhsom.config b/configs/dhsom.config
index fc76632..380beda 100644
--- a/configs/dhsom.config
+++ b/configs/dhsom.config
@@ -49,6 +49,7 @@
CONFIG_CMD_WGET=y
CONFIG_CMD_XXD=y
CONFIG_CRC32_VERIFY=y
+CONFIG_ENV_CALLBACK_LIST_STATIC="dh_som_serial_number:dh_som_serial_number,SN:SN,"
CONFIG_HASH_VERIFY=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_SHA1SUM_VERIFY=y
diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig
index 5797c6c..c36196c 100644
--- a/configs/e850-96_defconfig
+++ b/configs/e850-96_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARM_SMCCC=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TEXT_BASE=0xf8800000
CONFIG_SYS_MALLOC_LEN=0x81f000
@@ -9,6 +10,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000
CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96"
CONFIG_SYS_LOAD_ADDR=0x80000000
+# CONFIG_PSCI_RESET is not set
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig
deleted file mode 100644
index af9c7a4..0000000
--- a/configs/giedi_defconfig
+++ /dev/null
@@ -1,133 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_IMX8=y
-CONFIG_TEXT_BASE=0x80020000
-CONFIG_SYS_MALLOC_LEN=0x2800000
-CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x0
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi"
-CONFIG_TARGET_GIEDI=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x13e000
-CONFIG_SPL_TEXT_BASE=0x100000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x128000
-CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_BOOTM_LEN=0x800000
-CONFIG_SYS_LOAD_ADDR=0x80280000
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x2000
-CONFIG_IDENT_STRING=" ##v01.07"
-CONFIG_REMAKE_ELF=y
-# CONFIG_EFI_LOADER is not set
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_BOOTDELAY=3
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
-CONFIG_AUTOBOOT_KEYED_CTRLC=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2073
-CONFIG_LOG=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_MAX_SIZE=0x1f000
-CONFIG_SPL_BOARD_INIT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
-CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_CMD_CPU=y
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eth1"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_ENV=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_IMX8=y
-CONFIG_CPU=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_PHYLIB=y
-CONFIG_MV88E61XX_SWITCH=y
-CONFIG_MV88E61XX_CPU_PORT=5
-CONFIG_MV88E61XX_PHY_PORTS=0x7
-CONFIG_FEC_MXC_SHARE_MDIO=y
-CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
-CONFIG_DM_SERIAL=y
-CONFIG_FSL_LPUART=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_SCU_THERMAL=y
-# CONFIG_SPL_WDT is not set
-CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config
new file mode 100644
index 0000000..2164c75
--- /dev/null
+++ b/configs/imx8m_data_modul.config
@@ -0,0 +1,221 @@
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_INPUT is not set
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+# CONFIG_SPL_DM_USB is not set
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_ARCH_IMX8M=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_ARM=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_BKOPS_ENABLE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_WGET=y
+CONFIG_CMD_XXD=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x30880000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MTD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_THERMAL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_OFFSET=0xFFFC0000
+CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FEC_MXC=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_USDHC=y
+CONFIG_GPIO_HOG=y
+CONFIG_HASH_VERIFY=y
+CONFIG_HUSH_PARSER=y
+CONFIG_I2C_EEPROM=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_IMX_TMU=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_IPV6=y
+CONFIG_IP_DEFRAG=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_MII=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MTD=y
+CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
+CONFIG_MXC_GPIO=y
+CONFIG_MXC_SPI=y
+CONFIG_MXC_UART=y
+CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_REGMAP=y
+CONFIG_RGMII=y
+CONFIG_RTC_M41T62=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPL=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SYSCON=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
+CONFIG_SYS_EEPROM_SIZE=16384
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_SYS_PBSIZE=2081
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_TFTP_TSIZE=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_HUB_USB251XB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_USE_PREBOOT=y
+CONFIG_VERSION_VARIABLE=y
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 105fbfb..66cb133 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -1,242 +1,39 @@
+#include <configs/imx8m_data_modul.config>
+
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
-CONFIG_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0xFFFC0000
-CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc"
CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_DM_RESET=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
-CONFIG_SPL_STACK=0x920000
-CONFIG_SPL_TEXT_BASE=0x7E1000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x910000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
-CONFIG_SYS_BOOTM_LEN=0x8000000
-CONFIG_SYS_LOAD_ADDR=0x60000000
-CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
-CONFIG_IMX_BOOTAUX=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
-CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="run dmo_preboot"
-CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_LATE_INIT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
-CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_SPL_I2C=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="u-boot=> "
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_ERASEENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=16384
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
-CONFIG_CMD_MD5SUM=y
-CONFIG_MD5SUM_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_GPT_RENAME=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_MMC_SPEED_MODE_SET=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CAT=y
-CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_PXE=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_GETTIME=y
-CONFIG_CMD_KASLRSEED=y
-CONFIG_CMD_SYSBOOT=y
-CONFIG_CMD_UUID=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_SMC=y
-CONFIG_HASH_VERIFY=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
-CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_PART=1
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NETCONSOLE=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CI_UDC=y
CONFIG_CLK_IMX8MM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_TIMEOUT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_I2C=y
-# CONFIG_INPUT is not set
-CONFIG_USB_HUB_USB251XB=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_ES_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
-CONFIG_MII=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8M=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8M_POWER_DOMAIN=y
-CONFIG_DM_PMIC=y
+CONFIG_CMD_PCI=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb"
CONFIG_DM_PMIC_BD71837=y
-CONFIG_SPL_DM_PMIC_BD71837=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_IMX=y
+CONFIG_PHY=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_IMX8M_PCIE=y
+CONFIG_PREBOOT="run dmo_preboot"
+CONFIG_SDP_LOADADDR=0x60000000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BSS_START_ADDR=0x910000
+CONFIG_SPL_MAX_SIZE=0x30000
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_SPL_DM_REGULATOR_BD71837=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RNG=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_M41T62=y
-CONFIG_DM_SERIAL=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_FUNCTION_ACM=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_STACK=0x920000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SYS_LOAD_ADDR=0x60000000
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index f809d23..ea8109b 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -1,271 +1,54 @@
+#include <configs/imx8m_data_modul.config>
+
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
-CONFIG_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SYS_MALLOC_F_LEN=0x18000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0xFFFC0000
-CONFIG_DM_GPIO=y
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc"
CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_DM_RESET=y
-CONFIG_SYS_MONITOR_LEN=1048576
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
-CONFIG_SPL_STACK=0x96fc00
-CONFIG_SPL_TEXT_BASE=0x920000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x96fc00
-CONFIG_SPL_BSS_MAX_SIZE=0x400
-CONFIG_SYS_BOOTM_LEN=0x8000000
-CONFIG_SYS_LOAD_ADDR=0x50000000
-CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_DEBUG_UART_BASE=0x30880000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_IMX_BOOTAUX=y
-CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_DEBUG_UART=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x3000
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
-CONFIG_USE_PREBOOT=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc"
CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2081
-CONFIG_CONSOLE_MUX=y
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_BOOTROM_SUPPORT=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="u-boot=> "
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_EXPORTENV is not set
-CONFIG_CMD_ERASEENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=16384
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
-CONFIG_CMD_MD5SUM=y
-CONFIG_MD5SUM_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_SHA1SUM_VERIFY=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_GPT_RENAME=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_LSBLK=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_BKOPS_ENABLE=y
-CONFIG_MMC_SPEED_MODE_SET=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_READ=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_CAT=y
-CONFIG_CMD_XXD=y
-CONFIG_CMD_DHCP6=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_WGET=y
-CONFIG_CMD_PXE=y
-CONFIG_CMD_BOOTCOUNT=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_GETTIME=y
-CONFIG_CMD_KASLRSEED=y
-CONFIG_CMD_SYSBOOT=y
-CONFIG_CMD_UUID=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_SMC=y
-CONFIG_HASH_VERIFY=y
-CONFIG_CMD_BTRFS=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
-CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_PART=1
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_NETCONSOLE=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_PROT_TCP_SACK=y
-CONFIG_IPV6=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
-CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MP=y
-CONFIG_CLK_IMX8MP=y
-CONFIG_FSL_CAAM=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
CONFIG_IMX8M_DRAM_INLINE_ECC=y
-CONFIG_DFU_TFTP=y
-CONFIG_DFU_TIMEOUT=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x42800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
-CONFIG_SPL_GPIO_HOG=y
-CONFIG_MXC_GPIO=y
-CONFIG_DM_I2C=y
-# CONFIG_INPUT is not set
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_USB_HUB_USB251XB=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_SPL_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_ES_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_DWC_ETH_QOS=y
-CONFIG_DWC_ETH_QOS_IMX=y
-CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
-CONFIG_MII=y
-CONFIG_PHY_IMX8MQ_USB=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX8M=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_IMX8M_POWER_DOMAIN=y
-CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL_BSS_START_ADDR=0x96fc00
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
CONFIG_SPL_DM_PMIC_PCA9450=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_SPL_DM_REGULATOR_PCA9450=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RNG=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_M41T62=y
-CONFIG_DM_SERIAL=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_DM_USB_GADGET=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_GPIO_HOG=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_STACK=0x96fc00
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETH_CDC=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx91_11x11_evk_defconfig
similarity index 63%
copy from configs/imx93-phyboard-segin_defconfig
copy to configs/imx91_11x11_evk_defconfig
index 309262c..6ee0b44 100644
--- a/configs/imx93-phyboard-segin_defconfig
+++ b/configs/imx91_11x11_evk_defconfig
@@ -2,30 +2,30 @@
CONFIG_ARCH_IMX9=y
CONFIG_TEXT_BASE=0x80200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SOURCE_FILE="phycore_imx93"
-CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SOURCE_FILE="imx91_evk"
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx93-phyboard-segin"
-CONFIG_AHAB_BOOT=y
-CONFIG_TARGET_PHYCORE_IMX93=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-11x11-evk"
+CONFIG_TARGET_IMX91_11X11_EVK=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x20519dd0
-CONFIG_SPL_TEXT_BASE=0x2049A000
+CONFIG_SPL_STACK=0x204E0000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_TEXT_BASE=0x204A0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2051a000
+CONFIG_SPL_BSS_START_ADDR=0x20498000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SYS_LOAD_ADDR=0x80400000
CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x720000
CONFIG_CMD_DEKBLOB=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
CONFIG_SYS_MEMTEST_START=0x80000000
@@ -33,10 +33,10 @@
CONFIG_REMAKE_ELF=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
-CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_BOARD_INIT=y
@@ -44,30 +44,27 @@
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_CPU=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_BUS=2
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=4096
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_USB=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
@@ -83,40 +80,42 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
-CONFIG_SPL_CLK_IMX93=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_ADC=y
+CONFIG_ADC_IMX93=y
CONFIG_CLK_IMX93=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_UUU_SUPPORT=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
+CONFIG_CPU=y
+CONFIG_CPU_IMX=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000
CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_ADP5585_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
-CONFIG_PHY_TI_GENERIC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
-CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
@@ -130,22 +129,17 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
-CONFIG_CI_UDC=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYSRESET_PSCI=y
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_SHA384=y
CONFIG_LZO=y
CONFIG_BZIP2=y
diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx91_11x11_evk_inline_ecc_defconfig
similarity index 63%
copy from configs/imx93-phyboard-segin_defconfig
copy to configs/imx91_11x11_evk_inline_ecc_defconfig
index 309262c..761a666 100644
--- a/configs/imx93-phyboard-segin_defconfig
+++ b/configs/imx91_11x11_evk_inline_ecc_defconfig
@@ -2,30 +2,30 @@
CONFIG_ARCH_IMX9=y
CONFIG_TEXT_BASE=0x80200000
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SOURCE_FILE="phycore_imx93"
-CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SOURCE_FILE="imx91_evk"
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx93-phyboard-segin"
-CONFIG_AHAB_BOOT=y
-CONFIG_TARGET_PHYCORE_IMX93=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-11x11-evk"
+CONFIG_TARGET_IMX91_11X11_EVK=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x20519dd0
-CONFIG_SPL_TEXT_BASE=0x2049A000
+CONFIG_SPL_STACK=0x204E0000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_TEXT_BASE=0x204A0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2051a000
+CONFIG_SPL_BSS_START_ADDR=0x20498000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SYS_LOAD_ADDR=0x80400000
CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x720000
CONFIG_CMD_DEKBLOB=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
CONFIG_SYS_MEMTEST_START=0x80000000
@@ -33,10 +33,10 @@
CONFIG_REMAKE_ELF=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
-CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_BOARD_INIT=y
@@ -44,30 +44,27 @@
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_CPU=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_BUS=2
-CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_SYS_EEPROM_SIZE=4096
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_USB=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
@@ -83,40 +80,43 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
-CONFIG_SPL_CLK_IMX93=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_ADC=y
+CONFIG_ADC_IMX93=y
CONFIG_CLK_IMX93=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82800000
-CONFIG_FASTBOOT_BUF_SIZE=0x20000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_UUU_SUPPORT=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_GPIO_HOG=y
+CONFIG_CPU=y
+CONFIG_CPU_IMX=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000
+CONFIG_IMX9_DRAM_INLINE_ECC=y
CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_ADP5585_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
-CONFIG_PHY_TI_GENERIC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
-CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
@@ -130,22 +130,17 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
-CONFIG_CI_UDC=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYSRESET_PSCI=y
CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_SHA384=y
CONFIG_LZO=y
CONFIG_BZIP2=y
diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phycore_defconfig
similarity index 97%
rename from configs/imx93-phyboard-segin_defconfig
rename to configs/imx93-phycore_defconfig
index 309262c..cf98001 100644
--- a/configs/imx93-phyboard-segin_defconfig
+++ b/configs/imx93-phycore_defconfig
@@ -6,6 +6,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
+CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_ENV_SOURCE_FILE="phycore_imx93"
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x700000
@@ -31,6 +32,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_REMAKE_ELF=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index d6b4496..6e6105f 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -64,21 +64,14 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x300000
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
CONFIG_CMD_UBI=y
@@ -209,3 +202,4 @@
CONFIG_UFS=y
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 57a8ffc..02d446a 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -102,6 +102,7 @@
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_K3_AVS0=y
+# CONFIG_K3_OPP_LOW is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index d742ae6..bb031db 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -65,22 +65,15 @@
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
-CONFIG_CMD_ASKENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EFIDEBUG=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),1m(ospi.sysfw),256k(ospi.env.backup),57344k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
CONFIG_CMD_UBI=y
@@ -215,5 +208,6 @@
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
CONFIG_EFI_SET_TIME=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
#include <configs/k3_efi_capsule.config>
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 2a0ccfb..a2c39ae 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -62,20 +62,13 @@
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
CONFIG_CMD_UBI=y
@@ -204,3 +197,4 @@
CONFIG_UFS=y
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index f4441d6..23ae991 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -111,7 +111,9 @@
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
+CONFIG_ESM_K3=y
CONFIG_K3_AVS0=y
+CONFIG_ESM_PMIC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
index 35329fb..81eb934 100644
--- a/configs/j722s_evm_a53_defconfig
+++ b/configs/j722s_evm_a53_defconfig
@@ -55,16 +55,9 @@
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
@@ -170,3 +163,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_TI_COMMON_CMD_OPTIONS=y
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index a3c13fe..0f7cd4b 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -89,6 +89,7 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
+CONFIG_K3_QOS=y
CONFIG_K3_SEC_PROXY=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index c7fc6be..49775dc 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -61,15 +61,10 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_NVEDIT_EFI=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
CONFIG_CMD_EFIDEBUG=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_UPSTREAM=y
@@ -164,5 +159,6 @@
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
CONFIG_EFI_SET_TIME=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
#include <configs/k3_efi_capsule.config>
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index 3f1f66d..61a44bf 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -145,3 +145,7 @@
CONFIG_PANIC_HANG=y
CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_K3_AVS0=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_TPS6287X=y
diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig
index de5357c..a078c5d 100644
--- a/configs/khadas-vim3_android_ab_defconfig
+++ b/configs/khadas-vim3_android_ab_defconfig
@@ -24,6 +24,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTMETH_ANDROID=y
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_EXTLINUX_PXE is not set
+# CONFIG_BOOTMETH_EFILOADER is not set
+# CONFIG_BOOTMETH_EFI_BOOTMGR is not set
+# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -35,7 +41,6 @@
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
# CONFIG_CMD_IMI is not set
-CONFIG_CMD_BCB=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig
index a0d9c42..b77a44c 100644
--- a/configs/khadas-vim3_android_defconfig
+++ b/configs/khadas-vim3_android_defconfig
@@ -24,6 +24,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTMETH_ANDROID=y
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_EXTLINUX_PXE is not set
+# CONFIG_BOOTMETH_EFILOADER is not set
+# CONFIG_BOOTMETH_EFI_BOOTMGR is not set
+# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -34,7 +40,6 @@
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
# CONFIG_CMD_IMI is not set
-CONFIG_CMD_BCB=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig
index 4d7b90f..43db610 100644
--- a/configs/khadas-vim3l_android_ab_defconfig
+++ b/configs/khadas-vim3l_android_ab_defconfig
@@ -24,6 +24,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTMETH_ANDROID=y
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_EXTLINUX_PXE is not set
+# CONFIG_BOOTMETH_EFILOADER is not set
+# CONFIG_BOOTMETH_EFI_BOOTMGR is not set
+# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -35,7 +41,6 @@
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
# CONFIG_CMD_IMI is not set
-CONFIG_CMD_BCB=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig
index 4ec2726..32d57a5 100644
--- a/configs/khadas-vim3l_android_defconfig
+++ b/configs/khadas-vim3l_android_defconfig
@@ -24,6 +24,12 @@
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTMETH_ANDROID=y
+# CONFIG_BOOTMETH_EXTLINUX is not set
+# CONFIG_BOOTMETH_EXTLINUX_PXE is not set
+# CONFIG_BOOTMETH_EFILOADER is not set
+# CONFIG_BOOTMETH_EFI_BOOTMGR is not set
+# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -34,7 +40,6 @@
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
# CONFIG_CMD_IMI is not set
-CONFIG_CMD_BCB=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 5e59efe..3f43368 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -11,6 +11,7 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk"
CONFIG_TARGET_PHYCORE_IMX8MM=y
+CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
@@ -30,8 +31,6 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig
new file mode 100644
index 0000000..8148fd4
--- /dev/null
+++ b/configs/phycore_am62ax_a53_defconfig
@@ -0,0 +1,181 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM62A7=y
+CONFIG_PHYTEC_SOM_DETECTION=y
+CONFIG_PHYTEC_SOM_DETECTION_BLOCKS=y
+CONFIG_TARGET_PHYCORE_AM62AX_A53=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62a7-phyboard-lyra-rdk"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a00000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_ENV_OFFSET_REDUND=0x6c0000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb"
+CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62AX U-Boot A53 SPL"
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_SMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RV3028=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_DWC3_AM62=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_SPL_DFU=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig
new file mode 100644
index 0000000..a71ebf0
--- /dev/null
+++ b/configs/phycore_am62ax_r5_defconfig
@@ -0,0 +1,129 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_AM62A7=y
+CONFIG_TARGET_PHYCORE_AM62AX_R5=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-phycore-som-2gb"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145
+CONFIG_SPL_TEXT_BASE=0x43c00000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x43c3b000
+CONFIG_SPL_BSS_MAX_SIZE=0x3000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SIZE_LIMIT=0x3A7F0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0x3B000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+# CONFIG_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_ESM_K3=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index 43b0dac..551fd44 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -36,6 +36,9 @@
CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
@@ -61,12 +64,16 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_CMD_BOOTEFI_HELLO is not set
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_SMC=y
CONFIG_OF_CONTROL=y
@@ -91,6 +98,7 @@
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
@@ -107,6 +115,7 @@
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
@@ -157,3 +166,4 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+# CONFIG_HEXDUMP is not set
diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig
index ac9731d..bc45000 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -35,6 +35,8 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
@@ -65,7 +67,10 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_CMD_BOOTEFI_HELLO is not set
+CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@@ -73,6 +78,7 @@
CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SMC=y
@@ -98,6 +104,7 @@
CONFIG_CLK_CCF=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
@@ -121,6 +128,7 @@
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 718e4a8..af56571 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -50,7 +50,9 @@
CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_STACKPROTECTOR=y
+CONFIG_ANDROID_AB=y
CONFIG_CMD_CPU=y
+CONFIG_CMD_UFETCH=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_SMBIOS=y
CONFIG_CMD_BOOTM_PRE_LOAD=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 6f51179..4fed7ed 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -36,7 +36,6 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ID_EEPROM=y
CONFIG_PCI_INIT_R=y
-CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_SPL_MAX_SIZE=0x100000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
@@ -60,6 +59,7 @@
CONFIG_SPI_FLASH_ISSI=y
CONFIG_E1000=y
CONFIG_NVME_PCI=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCIE_DW_SIFIVE=y
CONFIG_SCSI=y
CONFIG_USB=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 319e1d3..20f89ae 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -56,9 +56,6 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
-CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index e5ffc70..8fb66f7 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -47,6 +47,7 @@
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_BINMAN_SYMBOLS is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_FS_LOAD_KERNEL_NAME=""
CONFIG_SPL_FS_LOAD_ARGS_NAME=""
@@ -207,6 +208,7 @@
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
+CONFIG_USB_ONBOARD_HUB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
@@ -223,6 +225,8 @@
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-som.dtb"
CONFIG_PANIC_HANG=y
CONFIG_TPM=y
CONFIG_SPL_GZIP=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index b58cf8a..396c876 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -60,6 +60,8 @@
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
CONFIG_ARM_DCC=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb"
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index f47880b..c19f79f 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -29,6 +29,7 @@
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_BINMAN_SYMBOLS is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
@@ -74,6 +75,8 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ARM_DCC=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb"
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index fc0070a..459e029 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -29,6 +29,7 @@
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_BINMAN_SYMBOLS is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
@@ -74,6 +75,8 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ARM_DCC=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb"
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index 6a7541f..0a5cfd8 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -60,6 +60,8 @@
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_MAX_CHIPS=2
CONFIG_ARM_DCC=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb"
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index 3643cae..4c399fd 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -59,6 +59,8 @@
CONFIG_NAND_ARASAN=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_ARM_DCC=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb"
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index a60403d..9d78541 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -32,6 +32,7 @@
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_BINMAN_SYMBOLS is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
@@ -92,6 +93,8 @@
CONFIG_ARM_DCC=y
CONFIG_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb"
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 310efdf..09f487a 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -41,6 +41,7 @@
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_CLOCKS=y
CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_BINMAN_SYMBOLS is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
@@ -241,6 +242,8 @@
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_BLK=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman.dtb"
CONFIG_PANIC_HANG=y
CONFIG_TPM=y
CONFIG_SPL_GZIP=y
diff --git a/doc/board/nxp/imx91_11x11_evk.rst b/doc/board/nxp/imx91_11x11_evk.rst
new file mode 100644
index 0000000..3ec3d28
--- /dev/null
+++ b/doc/board/nxp/imx91_11x11_evk.rst
@@ -0,0 +1,70 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx91_11x11_EVK
+=======================
+
+U-Boot for the NXP i.MX91 11x11 EVK
+
+Quick Start
+-----------
+
+- Get and Build the ARM Trusted firmware
+- Get the DDR firmware
+- Get ahab-container.img
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/nxp-imx/imx-atf/
+branch: lf_v2.10
+
+.. code-block:: bash
+
+ $ unset LDFLAGS
+ $ make PLAT=imx91 bl31
+ $ cp build/imx91/release/bl31.bin $(srctree)
+
+Get the DDR firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
+ $ chmod +x firmware-imx-8.21.bin
+ $ ./firmware-imx-8.21.bin
+ $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Get ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin
+ $ chmod +x firmware-ele-imx-1.3.0-17945fc.bin
+ $ ./firmware-ele-imx-1.3.0-17945fc.bin
+ $ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx91_11x11_evk_defconfig or imx91_11x11_evk_inline_ecc_defconfig
+ $ make
+
+- Inline ECC is to enable DDR ECC feature with imx91_11x11_evk_inline_ecc_defconfig
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+
+Set Boot switch to SD boot
diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst
index 734bab6..8ca4b56 100644
--- a/doc/board/nxp/index.rst
+++ b/doc/board/nxp/index.rst
@@ -12,6 +12,7 @@
imx8mq_evk
imx8qxp_mek
imx8ulp_evk
+ imx91_11x11_evk
imx93_9x9_qsb
imx93_11x11_evk
imxrt1020-evk
diff --git a/doc/board/phytec/imx93-phyboard-segin.rst b/doc/board/phytec/imx93-phycore.rst
similarity index 90%
rename from doc/board/phytec/imx93-phyboard-segin.rst
rename to doc/board/phytec/imx93-phycore.rst
index ce17fbe..bd110a3 100644
--- a/doc/board/phytec/imx93-phyboard-segin.rst
+++ b/doc/board/phytec/imx93-phycore.rst
@@ -1,9 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0+
-phyBOARD-Segin-i.MX93
-=====================
+phyCORE-i.MX 93
+===============
-U-Boot for the phyBOARD-Segin-i.MX93.
+U-Boot for the phyCORE-i.MX 93.
Quick Start
-----------
@@ -51,7 +51,7 @@
.. code-block:: bash
- $ make imx93-phyboard-segin_defconfig
+ $ make imx93-phycore_defconfig
$ make
Burn the flash.bin to MicroSD card offset 32KB:
diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst
index 99848a9..1ae30c2 100644
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -7,8 +7,9 @@
:maxdepth: 2
imx8mm-phygate-tauri-l
- imx93-phyboard-segin
+ imx93-phycore
phycore-am62x
+ phycore-am62ax
phycore-am64x
phycore-imx8mm
phycore-imx8mp
diff --git a/doc/board/phytec/phycore-am62ax.rst b/doc/board/phytec/phycore-am62ax.rst
new file mode 100644
index 0000000..0c5b481
--- /dev/null
+++ b/doc/board/phytec/phycore-am62ax.rst
@@ -0,0 +1,183 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Garrett Giordano <ggiordano@phytec.com>
+
+phyCORE-AM62Ax
+==============
+
+The `phyCORE-AM62Ax <https://www.phytec.com/product/phycore-am62a>`_ is a
+SoM (System on Module) featuring TI's AM62Ax SoC. It can be used in combination
+with different carrier boards. This module can come with different sizes and
+models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62Ax family.
+
+A development Kit, called `phyBOARD-Lyra <https://www.phytec.com/product/phyboard-am62x>`_
+is used as a carrier board reference design around the AM62Ax SoM.
+
+Quickstart
+----------
+
+* Download sources and TI firmware blobs
+* Build Trusted Firmware-A
+* Build OP-TEE
+* Build U-Boot for the R5
+* Build U-Boot for the A53
+* Create bootable uSD Card
+* Boot
+
+Sources
+-------
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_firmwares
+ :end-before: .. k3_rst_include_end_tifsstub
+
+Build procedure
+---------------
+
+Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=phycore_am62ax_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=phycore_am62ax_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62ax
+ $ # we dont use any extra OPTEE parameters
+ $ unset OPTEE_EXTRA_ARGS
+
+1. Trusted Firmware-A:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_tfa
+ :end-before: .. k3_rst_include_end_build_steps_tfa
+
+2. OP-TEE:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_optee
+ :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 3.1 R5:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 3.2 A53:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+
+uSD Card creation
+-----------------
+
+Use fdisk to partition the uSD card. The layout should look similar to:
+
+.. code-block:: bash
+
+ $ sudo fdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 15 GB, 15913189376 bytes, 31080448 sectors
+ 242816 cylinders, 4 heads, 32 sectors/track
+ Units: sectors of 1 * 512 = 512 bytes
+
+ Device Boot StartCHS EndCHS StartLBA EndLBA Sectors Size Id Type
+ /dev/mmcblk0p1 * 128,0,1 1023,3,32 16384 278527 262144 128M c Win95 FAT32 (LBA)
+ /dev/mmcblk0p2 1023,3,32 1023,3,32 278528 1693883 1415356 691M 83 Linux
+
+
+Once partitioned, the boot partition has to be formatted with a FAT filesystem.
+Assuming the uSD card is `/dev/mmcblk0`:
+
+.. code-block:: bash
+
+ $ mkfs.vfat /dev/mmcblk0p1
+
+To boot from a micro SD card on a HSFS device simply copy the following
+artifacts to the FAT partition:
+
+* tiboot3.bin from R5 build
+* tispl.bin from Cortex-A build
+* u-boot.img from Cortex-A build
+
+Boot
+----
+
+Put the uSD card in the slot on the board and apply power. Check the serial
+console for output.
+
+UART based boot
+---------------
+
+To boot the board via UART, set the switches to UART mode and connect to the
+micro USB port labeled as "Debug UART". After power-on the build artifacts
+needs to be uploaded one by one with a tool like sz.
+
+Example bash script sequence for running on a Linux host PC feeding all boot
+artifacts needed to the device. Assuming the host uses /dev/ttyUSB0 as
+the main domain serial port:
+
+.. prompt:: bash $
+
+ stty -F /dev/ttyUSB0 115200
+ sb --xmodem tiboot3.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem tispl.bin > /dev/ttyUSB0 < /dev/ttyUSB0
+ sb --ymodem u-boot.img > /dev/ttyUSB0 < /dev/ttyUSB0
+
+Boot Modes
+----------
+
+The phyCORE-AM62x development kit supports booting from many different
+interfaces. By default, the development kit is set to boot from the micro-SD
+card. To change the boot device, DIP switches S5 and S6 can be used.
+Boot switches should be changed with power off.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW5: 12345678
+ - SW6: 12345678
+
+ * - uSD
+ - 11000010
+ - 01000000
+
+ * - eMMC
+ - 11010010
+ - 00000000
+
+ * - OSPI
+ - 11010000
+ - 10000000
+
+ * - UART
+ - 11011100
+ - 00000000
+
+Further Information
+-------------------
+
+Please see :doc:`../ti/am62ax_sk` chapter for further AM62Ax SoC related documentation
+and https://docs.phytec.com/projects/yocto-phycore-am62ax/en/latest/ for vendor documentation.
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index 5d01f48..0deb4d7 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -46,6 +46,7 @@
* :doc:`../beagle/am62x_beagleplay`
* :doc:`../beagle/j721e_beagleboneai64`
* :doc:`../phytec/phycore-am62x`
+* :doc:`../phytec/phycore-am62ax`
* :doc:`../toradex/verdin-am62`
Boot Flow Overview
diff --git a/doc/build/docker.rst b/doc/build/docker.rst
index 45659b3..5896dd5 100644
--- a/doc/build/docker.rst
+++ b/doc/build/docker.rst
@@ -1,11 +1,30 @@
GitLab CI / U-Boot runner container
===================================
-In order to have a reproducible and portable build environment for CI we use a container for building in. This means that developers can also reproduce the CI environment, to a large degree at least, locally. This file is located in the tools/docker directory. To build the image yourself
+In order to have a reproducible and portable build environment for CI we use a container for building in. This means that developers can also reproduce the CI environment, to a large degree at least, locally. This file is located in the tools/docker directory.
+
+The docker image supports both amd64 and arm64. Ensure that the
+'docker-buildx' Debian package is installed (or the equivalent on another
+distribution).
+
+You will need a multi-platform container, otherwise this error is shown::
+
+ ERROR: Multi-platform build is not supported for the docker driver.
+ Switch to a different driver, or turn on the containerd image store, and try again.
+
+You can add one with::
+
+ sudo docker buildx create --name multiarch --driver docker-container --use
+
+Building is supported on both amd64 (i.e. 64-bit x86) and arm64 machines. While
+both amd64 and arm64 happen in parallel, the non-native part will take
+considerably longer as it must use QEMU to emulate the foreign code.
+
+To build the image yourself::
.. code-block:: bash
- sudo docker build -t your-namespace:your-tag .
+ sudo docker buildx build --platform linux/arm64/v8,linux/amd64 -t your-namespace:your-tag .
Or to use an existing container
diff --git a/doc/develop/environment.rst b/doc/develop/environment.rst
index e178346..e46cd39 100644
--- a/doc/develop/environment.rst
+++ b/doc/develop/environment.rst
@@ -18,8 +18,8 @@
U_BOOT_ENV_CALLBACK macro in your board or driver code.
These callbacks are associated with variables in one of two ways. The
-static list can be added to by defining CFG_ENV_CALLBACK_LIST_STATIC
-in the board configuration to a string that defines a list of
+static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
+in the board defconfig via menuconfig to a string that defines a list of
associations. The list must be in the following format::
entry = variable_name[:callback_name]
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index c742c2f..9f9252b 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -73,7 +73,7 @@
* U-Boot v2025.01-rc3 was released on Mon 25 November 2024.
-.. * U-Boot v2025.01-rc4 was released on Mon 09 December 2024.
+* U-Boot v2025.01-rc4 was released on Mon 09 December 2024.
.. * U-Boot v2025.01-rc5 was released on Mon 23 December 2024.
diff --git a/doc/usage/fit/howto.rst b/doc/usage/fit/howto.rst
index 280eff7..675c9aa 100644
--- a/doc/usage/fit/howto.rst
+++ b/doc/usage/fit/howto.rst
@@ -57,10 +57,6 @@
multiple /configurations subnodes. The required images must be enumerated in
the "loadables" property as a list of strings.
-CONFIG_SPL_FIT_GENERATOR can point to a script which generates this image source
-file during the build process. It gets passed a list of device tree files (taken
-from the CONFIG_OF_LIST symbol).
-
The SPL also records to a DT all additional images (called loadables) which are
loaded. The information about loadables locations is passed via the DT node with
fit-images name.
diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h
index 954cd88..739a17c 100644
--- a/drivers/bios_emulator/biosemui.h
+++ b/drivers/bios_emulator/biosemui.h
@@ -128,6 +128,7 @@
u32 finalVal;
} BE_portInfo;
+#if defined(X86EMU_RAW_IO)
#define PM_inpb(port) inb(port)
#define PM_inpw(port) inw(port)
#define PM_inpd(port) inl(port)
@@ -135,6 +136,46 @@
#define PM_outpw(port, val) outw(val, port)
#define PM_outpd(port, val) outl(val, port)
+#else
+
+/*
+ * Until the emulator code is fixed, at least print warnings.
+ */
+
+static inline u8 PM_inpb(u16 port)
+{
+ printf("x86 port 0x%x read attempt, returning 0\n", port);
+ return 0;
+}
+
+static inline u16 PM_inpw(u16 port)
+{
+ printf("x86 port 0x%x read attempt, returning 0\n", port);
+ return 0;
+}
+
+static inline u32 PM_inpd(u16 port)
+{
+ printf("x86 port 0x%x read attempt, returning 0\n", port);
+ return 0;
+}
+
+static inline void PM_outpb(u16 port, u8 val)
+{
+ printf("x86 port 0x%x write attempt, ignoring\n", port);
+}
+
+static inline void PM_outpw(u16 port, u16 val)
+{
+ printf("x86 port 0x%x write attempt, ignoring\n", port);
+}
+
+static inline void PM_outpd(u16 port, u32 val)
+{
+ printf("x86 port 0x%x write attempt, ignoring\n", port);
+}
+#endif
+
#define LOG_inpb(port) PM_inpb(port)
#define LOG_inpw(port) PM_inpw(port)
#define LOG_inpd(port) PM_inpd(port)
diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c
index b426dc3..c63cf3d 100644
--- a/drivers/bios_emulator/x86emu/debug.c
+++ b/drivers/bios_emulator/x86emu/debug.c
@@ -38,6 +38,8 @@
****************************************************************************/
#include <stdarg.h>
+#include <string.h>
+#include <vsprintf.h>
#include <linux/ctype.h>
#include <linux/printk.h>
#include "x86emu/x86emui.h"
diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig
index 3918b05..6cae16f 100644
--- a/drivers/button/Kconfig
+++ b/drivers/button/Kconfig
@@ -9,6 +9,17 @@
can provide access to board-specific buttons. Use of the device tree
for configuration is encouraged.
+config BUTTON_REMAP_PHONE_KEYS
+ bool "Remap phone keys for navigation"
+ depends on BUTTON
+ help
+ Enable remapping of phone keys to navigation keys. This is useful for
+ devices with phone keys that are not used in U-Boot. The phone keys
+ are remapped to the following navigation keys:
+ - Volume up: Up
+ - Volume down: Down
+ - Power: Enter
+
config BUTTON_ADC
bool "Button adc"
depends on BUTTON
diff --git a/drivers/button/button-gpio.c b/drivers/button/button-gpio.c
index 43b82d9..31b85c8 100644
--- a/drivers/button/button-gpio.c
+++ b/drivers/button/button-gpio.c
@@ -20,6 +20,9 @@
struct button_gpio_priv *priv = dev_get_priv(dev);
int ret;
+ if (!priv)
+ return -ENODATA;
+
if (!dm_gpio_is_valid(&priv->gpio))
return -EREMOTEIO;
ret = dm_gpio_get_value(&priv->gpio);
@@ -32,6 +35,8 @@
static int button_gpio_get_code(struct udevice *dev)
{
struct button_gpio_priv *priv = dev_get_priv(dev);
+ if (!priv)
+ return -ENODATA;
int code = priv->linux_code;
if (!code)
@@ -51,7 +56,7 @@
return 0;
ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_IN);
- if (ret)
+ if (ret || !dm_gpio_is_valid(&priv->gpio))
return ret;
ret = dev_read_u32(dev, "linux,code", &priv->linux_code);
@@ -98,6 +103,8 @@
return ret;
uc_plat = dev_get_uclass_plat(dev);
uc_plat->label = label;
+ debug("Button '%s' bound to driver '%s'\n", label,
+ dev->driver->name);
}
return 0;
diff --git a/drivers/button/button-uclass.c b/drivers/button/button-uclass.c
index cda2433..729983d 100644
--- a/drivers/button/button-uclass.c
+++ b/drivers/button/button-uclass.c
@@ -10,6 +10,7 @@
#include <button.h>
#include <dm.h>
#include <dm/uclass-internal.h>
+#include <dt-bindings/input/linux-event-codes.h>
int button_get_by_label(const char *label, struct udevice **devp)
{
@@ -37,14 +38,33 @@
return ops->get_state(dev);
}
+static int button_remap_phone_keys(int code)
+{
+ switch (code) {
+ case KEY_VOLUMEUP:
+ return KEY_UP;
+ case KEY_VOLUMEDOWN:
+ return KEY_DOWN;
+ case KEY_POWER:
+ return KEY_ENTER;
+ default:
+ return code;
+ }
+}
+
int button_get_code(struct udevice *dev)
{
struct button_ops *ops = button_get_ops(dev);
+ int code;
if (!ops->get_code)
return -ENOSYS;
- return ops->get_code(dev);
+ code = ops->get_code(dev);
+ if (CONFIG_IS_ENABLED(BUTTON_REMAP_PHONE_KEYS))
+ return button_remap_phone_keys(code);
+ else
+ return code;
}
UCLASS_DRIVER(button) = {
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index a9937c2..353ae47 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -569,8 +569,20 @@
return 0;
ops = clk_dev_ops(clk->dev);
- if (!ops->set_rate)
- return -ENOSYS;
+ /* Try to find parents which can set rate */
+ while (!ops->set_rate) {
+ struct clk *parent;
+
+ if (!(clk->flags & CLK_SET_RATE_PARENT))
+ return -ENOSYS;
+
+ parent = clk_get_parent(clk);
+ if (IS_ERR_OR_NULL(parent) || !clk_valid(parent))
+ return -ENODEV;
+
+ clk = parent;
+ ops = clk_dev_ops(clk->dev);
+ }
/* get private clock struct used for cache */
clk_get_priv(clk, &clkp);
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 8f42a5c..81e19d3 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -86,6 +86,7 @@
*/
static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
+ PLL_FRACN_GP(600000000U, 200, 0, 1, 0, 8),
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
@@ -93,7 +94,8 @@
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
- PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
+ PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
+ PLL_FRACN_GP(200000000U, 200, 0, 1, 0, 24)
};
struct imx_fracn_gppll_clk imx_fracn_gppll = {
@@ -111,6 +113,7 @@
PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
+ PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6),
};
struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index ede36c4..b31e57a 100644
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -13,6 +13,11 @@
#include "clk.h"
+#define IMX93_CLK_END 207
+
+#define PLAT_IMX93 BIT(0)
+#define PLAT_IMX91 BIT(1)
+
enum clk_sel {
LOW_SPEED_IO_SEL,
NON_IO_SEL,
@@ -50,6 +55,7 @@
u32 off;
enum clk_sel sel;
unsigned long flags;
+ unsigned long plat;
} root_array[] = {
/* a55/m33/bus critical clk for system run */
{ IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
@@ -60,7 +66,7 @@
{ IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
{ IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
{ IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
- { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, },
@@ -117,15 +123,15 @@
{ IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, },
{ IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, },
- { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, },
- { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, },
+ { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+ { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, },
{ IMX93_CLK_MEDIA_APB, "media_apb_root", 0x2300, LOW_SPEED_IO_SEL, },
- { IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, },
+ { IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", 0x2400, VIDEO_SEL, },
{ IMX93_CLK_CAM_PIX, "cam_pix_root", 0x2480, VIDEO_SEL, },
- { IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, },
- { IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, },
+ { IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, 0, PLAT_IMX93, },
+ { IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ADC, "adc_root", 0x2700, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_PDM, "pdm_root", 0x2780, AUDIO_SEL, },
{ IMX93_CLK_TSTMR1, "tstmr1_root", 0x2800, LOW_SPEED_IO_SEL, },
@@ -134,13 +140,16 @@
{ IMX93_CLK_MQS2, "mqs2_root", 0x2980, AUDIO_SEL, },
{ IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", 0x2a00, NON_IO_SEL, },
{ IMX93_CLK_SPDIF, "spdif_root", 0x2a80, AUDIO_SEL, },
- { IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, },
- { IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, },
- { IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, },
- { IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, },
- { IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, },
- { IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, },
- { IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, },
+ { IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, 0, PLAT_IMX93, },
+ { IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+ { IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+ { IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, 0, PLAT_IMX93, },
+ { IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+ { IMX91_CLK_ENET1_QOS_TSN, "enet1_qos_tsn_root", 0x2b00, NON_IO_SEL, 0, PLAT_IMX91, },
+ { IMX91_CLK_ENET_TIMER, "enet_timer_root", 0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX91, },
+ { IMX91_CLK_ENET2_REGULAR, "enet2_regular_root", 0x2c80, NON_IO_SEL, 0, PLAT_IMX91, },
+ { IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
+ { IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", 0x2e80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", 0x2f00, MISC_SEL, }
};
@@ -152,6 +161,7 @@
u32 off;
unsigned long flags;
u32 *shared_count;
+ unsigned long plat;
} ccgr_array[] = {
{ IMX93_CLK_A55_GATE, "a55_alt", "a55_alt_root", 0x8000, },
/* M33 critical clk for system run */
@@ -226,7 +236,7 @@
{ IMX93_CLK_SAI3_IPG, "sai3_ipg_clk", "bus_wakeup_root", 0x94c0, 0, &share_count_sai3},
{ IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, },
{ IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, },
- { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, },
+ { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, 0, NULL, PLAT_IMX93, },
{ IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, },
{ IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, },
{ IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, },
@@ -240,8 +250,10 @@
{ IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
{ IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, },
{ IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "clock-osc-24m", 0x9dc0, },
- { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, },
- { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, },
+ { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX93, },
+ { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX93, },
+ { IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX91, },
+ { IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX91, },
/* Critical because clk accessed during CPU idle */
{ IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "clock-osc-24m", 0x9e80, CLK_IS_CRITICAL},
{ IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, },
@@ -257,6 +269,7 @@
struct clk osc_24m_clk, osc_32k_clk, ext1_clk;
void __iomem *base, *anatop_base;
int i, ret;
+ const unsigned long plat = (unsigned long)dev_get_driver_data(dev);
clk_dm(IMX93_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0UL));
@@ -307,6 +320,8 @@
for (i = 0; i < ARRAY_SIZE(root_array); i++) {
root = &root_array[i];
+ if (root->plat && !(root->plat & plat))
+ continue;
clk_dm(root->clk, imx93_clk_composite_flags(root->name,
parent_names[root->sel],
4, base + root->off, 3,
@@ -315,6 +330,8 @@
for (i = 0; i < ARRAY_SIZE(ccgr_array); i++) {
ccgr = &ccgr_array[i];
+ if (ccgr->plat && !(ccgr->plat & plat))
+ continue;
clk_dm(ccgr->clk, imx93_clk_gate(NULL, ccgr->name, ccgr->parent_name,
ccgr->flags, base + ccgr->off, 0, 1, 1, 3,
ccgr->shared_count));
@@ -328,7 +345,8 @@
}
static const struct udevice_id imx93_clk_ids[] = {
- { .compatible = "fsl,imx93-ccm" },
+ { .compatible = "fsl,imx93-ccm", .data = (unsigned long)PLAT_IMX93 },
+ { .compatible = "fsl,imx91-ccm", .data = (unsigned long)PLAT_IMX91 },
{ /* Sentinel */ },
};
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index c8735d8..3c5340d 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -69,7 +69,15 @@
dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable",
is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id);
+
if (!is_mod_clk(clk->id)) {
+ /*
+ * Non-module clocks are always on. Ignore attempts to enable
+ * them and reject attempts to disable them.
+ */
+ if (enable)
+ return 0;
+
dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id);
return -EINVAL;
}
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 155ea8d..6e87db1 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -8,7 +8,6 @@
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
-#include <handoff.h>
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
@@ -1468,7 +1467,7 @@
init_clocks = true;
#elif CONFIG_IS_ENABLED(HANDOFF)
if (!(gd->flags & GD_FLG_RELOC)) {
- if (!handoff_get())
+ if (!(gd->spl_handoff))
init_clocks = true;
}
#endif
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
index b3a1b4c..b775bd5 100644
--- a/drivers/clk/ti/clk-k3-pll.c
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -14,6 +14,7 @@
#include <linux/clk-provider.h>
#include "k3-clk.h"
#include <linux/rational.h>
+#include <linux/delay.h>
/* 16FFT register offsets */
#define PLL_16FFT_CFG 0x08
@@ -29,10 +30,12 @@
/* CAL STAT register bits */
#define PLL_16FFT_CAL_STAT_CAL_LOCK BIT(31)
+#define PLL_16FFT_CAL_STAT_CAL_LOCK_TIMEOUT (4350U * 100U)
/* CFG register bits */
#define PLL_16FFT_CFG_PLL_TYPE_SHIFT (0)
#define PLL_16FFT_CFG_PLL_TYPE_MASK (0x3 << 0)
+#define PLL_16FFT_CFG_PLL_TYPE_FRAC2 0
#define PLL_16FFT_CFG_PLL_TYPE_FRACF 1
/* CAL CTRL register bits */
@@ -41,14 +44,21 @@
#define PLL_16FFT_CAL_CTRL_CAL_BYP BIT(15)
#define PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT 16
#define PLL_16FFT_CAL_CTRL_CAL_CNT_MASK (0x7 << 16)
+#define PLL_16FFT_CAL_CTRL_CAL_IN_MASK (0xFFFU)
/* CTRL register bits */
#define PLL_16FFT_CTRL_BYPASS_EN BIT(31)
+#define PLL_16FFT_CTRL_BYP_ON_LOCKLOSS BIT(16)
#define PLL_16FFT_CTRL_PLL_EN BIT(15)
+#define PLL_16FFT_CTRL_INTL_BYP_EN BIT(8)
+#define PLL_16FFT_CTRL_CLK_4PH_EN BIT(5)
+#define PLL_16FFT_CTRL_CLK_POSTDIV_EN BIT(4)
#define PLL_16FFT_CTRL_DSM_EN BIT(1)
+#define PLL_16FFT_CTRL_DAC_EN BIT(0)
/* STAT register bits */
#define PLL_16FFT_STAT_LOCK BIT(0)
+#define PLL_16FFT_STAT_LOCK_TIMEOUT (150U * 100U)
/* FREQ_CTRL0 bits */
#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK 0xfff
@@ -62,7 +72,6 @@
/* FREQ_CTRL1 bits */
#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK 0xffffff
-#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT 0
/* KICK register magic values */
#define PLL_KICK0_VALUE 0x68ef3490
@@ -75,68 +84,199 @@
*/
struct ti_pll_clk {
struct clk clk;
- void __iomem *reg;
+ void __iomem *base;
};
#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
-static int ti_pll_wait_for_lock(struct clk *clk)
+static int ti_pll_clk_disable(struct clk *clk)
{
struct ti_pll_clk *pll = to_clk_pll(clk);
+ u32 ctrl;
+
+ ctrl = readl(pll->base + PLL_16FFT_CTRL);
+
+ if ((ctrl & PLL_16FFT_CTRL_PLL_EN)) {
+ ctrl &= ~PLL_16FFT_CTRL_PLL_EN;
+ writel(ctrl, pll->base + PLL_16FFT_CTRL);
+
+ /* wait 1us */
+ udelay(1);
+ }
+
+ return 0;
+}
+
+static int ti_pll_clk_enable(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u32 ctrl;
+
+ ctrl = readl(pll->base + PLL_16FFT_CTRL);
+ ctrl |= PLL_16FFT_CTRL_PLL_EN;
+ writel(ctrl, pll->base + PLL_16FFT_CTRL);
+
+ /* Wait 1us */
+ udelay(1);
+
+ return 0;
+}
+
+static bool clk_pll_16fft_check_lock(const struct ti_pll_clk *pll)
+{
u32 stat;
+
+ stat = readl(pll->base + PLL_16FFT_STAT);
+ return (stat & PLL_16FFT_STAT_LOCK);
+}
+
+static bool clk_pll_16fft_check_cal_lock(const struct ti_pll_clk *pll)
+{
+ u32 stat;
+
+ stat = readl(pll->base + PLL_16FFT_CAL_STAT);
+ return (stat & PLL_16FFT_CAL_STAT_CAL_LOCK);
+}
+
+static void clk_pll_16fft_cal_int(const struct ti_pll_clk *pll)
+{
+ u32 cal;
+
+ cal = readl(pll->base + PLL_16FFT_CAL_CTRL);
+
+ /* Enable fast cal mode */
+ cal |= PLL_16FFT_CAL_CTRL_FAST_CAL;
+
+ /* Disable calibration bypass */
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP;
+
+ /* Set CALCNT to 2 */
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK;
+ cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT;
+
+ /* Set CAL_IN to 0 */
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_IN_MASK;
+
+ /* Note this register does not readback the written value. */
+ writel(cal, pll->base + PLL_16FFT_CAL_CTRL);
+
+ /* Wait 1us before enabling the CAL_EN field */
+ udelay(1);
+
+ cal = readl(pll->base + PLL_16FFT_CAL_CTRL);
+
+ /* Enable calibration for FRACF */
+ cal |= PLL_16FFT_CAL_CTRL_CAL_EN;
+
+ /* Note this register does not readback the written value. */
+ writel(cal, pll->base + PLL_16FFT_CAL_CTRL);
+}
+
+static void clk_pll_16fft_disable_cal(const struct ti_pll_clk *pll)
+{
+ u32 cal, stat;
+
+ cal = readl(pll->base + PLL_16FFT_CAL_CTRL);
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_EN;
+ /* Note this register does not readback the written value. */
+ writel(cal, pll->base + PLL_16FFT_CAL_CTRL);
+ do {
+ stat = readl(pll->base + PLL_16FFT_CAL_STAT);
+ } while (stat & PLL_16FFT_CAL_STAT_CAL_LOCK);
+}
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
u32 cfg;
u32 cal;
u32 freq_ctrl1;
- int i;
+ unsigned int i;
u32 pllfm;
u32 pll_type;
- int success;
+ u32 cal_en = 0;
+ bool success;
- for (i = 0; i < 100000; i++) {
- stat = readl(pll->reg + PLL_16FFT_STAT);
- if (stat & PLL_16FFT_STAT_LOCK) {
- success = 1;
+ /*
+ * Minimum VCO input freq is 5MHz, and the longest a lock should
+ * be consider to be timed out after 750 cycles. Be conservative
+ * and assume each loop takes 10 cycles and we run at a
+ * max of 1GHz. That gives 15000 loop cycles. We may end up waiting
+ * longer than necessary for timeout, but that should be ok.
+ */
+ success = false;
+ for (i = 0; i < PLL_16FFT_STAT_LOCK_TIMEOUT; i++) {
+ if (clk_pll_16fft_check_lock(pll)) {
+ success = true;
break;
}
}
- /* Enable calibration if not in fractional mode of the FRACF PLL */
- freq_ctrl1 = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+ /* Disable calibration in the fractional mode of the FRACF PLL based on data
+ * from silicon and simulation data.
+ */
+ freq_ctrl1 = readl(pll->base + PLL_16FFT_FREQ_CTRL1);
pllfm = freq_ctrl1 & PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK;
- pllfm >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT;
- cfg = readl(pll->reg + PLL_16FFT_CFG);
+
+ cfg = readl(pll->base + PLL_16FFT_CFG);
pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT;
- if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && pllfm == 0) {
- cal = readl(pll->reg + PLL_16FFT_CAL_CTRL);
+ if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF) {
+ cal = readl(pll->base + PLL_16FFT_CAL_CTRL);
+ cal_en = (cal & PLL_16FFT_CAL_CTRL_CAL_EN);
+ }
- /* Enable calibration for FRACF */
- cal |= PLL_16FFT_CAL_CTRL_CAL_EN;
+ if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF &&
+ pllfm == 0 && cal_en == 1) {
+ /*
+ * Wait for calibration lock.
+ *
+ * Lock should occur within:
+ *
+ * 170 * 2^(5+CALCNT) / PFD
+ * 21760 / PFD
+ *
+ * CALCNT = 2, PFD = 5-50MHz. This gives a range of 0.435mS to
+ * 4.35mS depending on PFD frequency.
+ *
+ * Be conservative and assume each loop takes 10 cycles and we run at a
+ * max of 1GHz. That gives 435000 loop cycles. We may end up waiting
+ * longer than necessary for timeout, but that should be ok.
+ *
+ * The recommend timeout for CALLOCK to go high is 4.35 ms
+ */
+ success = false;
+ for (i = 0; i < PLL_16FFT_CAL_STAT_CAL_LOCK_TIMEOUT; i++) {
+ if (clk_pll_16fft_check_cal_lock(pll)) {
+ success = true;
+ break;
+ }
+ }
- /* Enable fast cal mode */
- cal |= PLL_16FFT_CAL_CTRL_FAST_CAL;
+ /* In case of cal lock failure, operate without calibration */
+ if (!success) {
+ debug("Failure for calibration, falling back without calibration\n");
- /* Disable calibration bypass */
- cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP;
+ /* Disable PLL */
+ ti_pll_clk_disable(clk);
- /* Set CALCNT to 2 */
- cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK;
- cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT;
+ /* Disable Calibration */
+ clk_pll_16fft_disable_cal(pll);
- /* Note this register does not readback the written value. */
- writel(cal, pll->reg + PLL_16FFT_CAL_CTRL);
+ /* Enable PLL */
+ ti_pll_clk_enable(clk);
- success = 0;
- for (i = 0; i < 100000; i++) {
- stat = readl(pll->reg + PLL_16FFT_CAL_STAT);
- if (stat & PLL_16FFT_CAL_STAT_CAL_LOCK) {
- success = 1;
- break;
+ /* Wait for PLL Lock */
+ for (i = 0; i < PLL_16FFT_STAT_LOCK_TIMEOUT; i++) {
+ if (clk_pll_16fft_check_lock(pll)) {
+ success = true;
+ break;
+ }
}
}
}
- if (success == 0) {
+ if (!success) {
printf("%s: pll (%s) failed to lock\n", __func__,
clk->dev->name);
return -EBUSY;
@@ -156,14 +296,14 @@
u32 ctrl;
/* Check if we are in bypass */
- ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl = readl(pll->base + PLL_16FFT_CTRL);
if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
return parent_freq;
- pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
- pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+ pllm = readl(pll->base + PLL_16FFT_FREQ_CTRL0);
+ pllfm = readl(pll->base + PLL_16FFT_FREQ_CTRL1);
- plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+ plld = readl(pll->base + PLL_16FFT_DIV_CTRL) &
PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
current_freq = parent_freq * pllm / plld;
@@ -180,6 +320,30 @@
return current_freq;
}
+static bool ti_pll_clk_is_bypass(struct ti_pll_clk *pll)
+{
+ u32 ctrl;
+ bool ret;
+
+ ctrl = readl(pll->base + PLL_16FFT_CTRL);
+ ret = (ctrl & PLL_16FFT_CTRL_BYPASS_EN) != 0;
+
+ return ret;
+}
+
+static void ti_pll_clk_bypass(struct ti_pll_clk *pll, bool bypass)
+{
+ u32 ctrl;
+
+ ctrl = readl(pll->base + PLL_16FFT_CTRL);
+ if (bypass)
+ ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+ else
+ ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+
+ writel(ctrl, pll->base + PLL_16FFT_CTRL);
+}
+
static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
{
struct ti_pll_clk *pll = to_clk_pll(clk);
@@ -187,9 +351,13 @@
u64 parent_freq = clk_get_parent_rate(clk);
int ret;
u32 ctrl;
+ u32 cfg;
+ u32 pll_type;
unsigned long pllm;
u32 pllfm = 0;
unsigned long plld;
+ u32 freq_ctrl0;
+ u32 freq_ctrl1;
u32 div_ctrl;
u32 rem;
int shift;
@@ -212,16 +380,22 @@
break;
}
- /* Put PLL to bypass mode */
- ctrl = readl(pll->reg + PLL_16FFT_CTRL);
- ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
- writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+ if (!ti_pll_clk_is_bypass(pll)) {
+ /* Put the PLL into bypass */
+ ti_pll_clk_bypass(pll, true);
+ }
+
+ /* Disable the PLL */
+ ti_pll_clk_disable(clk);
if (rate == parent_freq) {
debug("%s: put %s to bypass\n", __func__, clk->dev->name);
return rate;
}
+ cfg = readl(pll->base + PLL_16FFT_CFG);
+ pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT;
+
debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n",
__func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm);
@@ -237,31 +411,75 @@
plld = 1;
}
- if (pllfm)
- ctrl |= PLL_16FFT_CTRL_DSM_EN;
- else
- ctrl &= ~PLL_16FFT_CTRL_DSM_EN;
+ /* Program the new rate */
+ freq_ctrl0 = readl(pll->base + PLL_16FFT_FREQ_CTRL0);
+ freq_ctrl1 = readl(pll->base + PLL_16FFT_FREQ_CTRL1);
+ div_ctrl = readl(pll->base + PLL_16FFT_DIV_CTRL);
- writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
- writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
+ freq_ctrl0 &= ~PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK;
+ freq_ctrl0 |= pllm;
+
+ freq_ctrl1 &= ~PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK;
+ freq_ctrl1 |= pllfm;
/*
* div_ctrl register contains other divider values, so rmw
* only plld and leave existing values alone
*/
- div_ctrl = readl(pll->reg + PLL_16FFT_DIV_CTRL);
div_ctrl &= ~PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
div_ctrl |= plld;
- writel(div_ctrl, pll->reg + PLL_16FFT_DIV_CTRL);
- ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
- ctrl |= PLL_16FFT_CTRL_PLL_EN;
- writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+ /* Make sure we have fractional support if required */
+ ctrl = readl(pll->base + PLL_16FFT_CTRL);
+
+ /* Don't use internal bypass,it is not glitch free. Always prefer glitchless bypass */
+ ctrl &= ~(PLL_16FFT_CTRL_INTL_BYP_EN | PLL_16FFT_CTRL_CLK_4PH_EN);
+
+ /* Always enable output if PLL, Always bypass if we lose lock */
+ ctrl |= (PLL_16FFT_CTRL_CLK_POSTDIV_EN | PLL_16FFT_CTRL_BYP_ON_LOCKLOSS);
+
+ /* Enable fractional support if required */
+ if (pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF) {
+ if (pllfm != 0)
+ ctrl |= (PLL_16FFT_CTRL_DSM_EN | PLL_16FFT_CTRL_DAC_EN);
+ else
+ ctrl &= ~(PLL_16FFT_CTRL_DSM_EN | PLL_16FFT_CTRL_DAC_EN);
+ }
+
+ /* Enable Fractional by default for PLL_16FFT_CFG_PLL_TYPE_FRAC2 */
+ if (pll_type == PLL_16FFT_CFG_PLL_TYPE_FRAC2)
+ ctrl |= (PLL_16FFT_CTRL_DSM_EN | PLL_16FFT_CTRL_DAC_EN);
+
+ writel(freq_ctrl0, pll->base + PLL_16FFT_FREQ_CTRL0);
+ writel(freq_ctrl1, pll->base + PLL_16FFT_FREQ_CTRL1);
+ writel(div_ctrl, pll->base + PLL_16FFT_DIV_CTRL);
+ writel(ctrl, pll->base + PLL_16FFT_CTRL);
+
+ /* Configure PLL calibration*/
+ if (pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF) {
+ if (pllfm != 0) {
+ /* Disable Calibration in Fractional mode */
+ clk_pll_16fft_disable_cal(pll);
+ } else {
+ /* Enable Calibration in Integer mode */
+ clk_pll_16fft_cal_int(pll);
+ }
+ }
+
+ /*
+ * Wait at least 1 ref cycle before enabling PLL.
+ * Minimum VCO input frequency is 5MHz, therefore maximum
+ * wait time for 1 ref clock is 0.2us.
+ */
+ udelay(1);
+ ti_pll_clk_enable(clk);
ret = ti_pll_wait_for_lock(clk);
if (ret)
return ret;
+ ti_pll_clk_bypass(pll, false);
+
debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n",
__func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq);
@@ -279,30 +497,7 @@
return current_freq;
}
-static int ti_pll_clk_enable(struct clk *clk)
-{
- struct ti_pll_clk *pll = to_clk_pll(clk);
- u32 ctrl;
-
- ctrl = readl(pll->reg + PLL_16FFT_CTRL);
- ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
- ctrl |= PLL_16FFT_CTRL_PLL_EN;
- writel(ctrl, pll->reg + PLL_16FFT_CTRL);
-
- return ti_pll_wait_for_lock(clk);
-}
-
-static int ti_pll_clk_disable(struct clk *clk)
-{
- struct ti_pll_clk *pll = to_clk_pll(clk);
- u32 ctrl;
- ctrl = readl(pll->reg + PLL_16FFT_CTRL);
- ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
- writel(ctrl, pll->reg + PLL_16FFT_CTRL);
-
- return 0;
-}
static const struct clk_ops ti_pll_clk_ops = {
.get_rate = ti_pll_clk_get_rate,
@@ -323,7 +518,7 @@
if (!pll)
return ERR_PTR(-ENOMEM);
- pll->reg = reg;
+ pll->base = reg;
ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name);
if (ret) {
@@ -333,19 +528,19 @@
}
/* Unlock the PLL registers */
- writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0);
- writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1);
+ writel(PLL_KICK0_VALUE, pll->base + PLL_KICK0);
+ writel(PLL_KICK1_VALUE, pll->base + PLL_KICK1);
/* Enable all HSDIV outputs */
- cfg = readl(pll->reg + PLL_16FFT_CFG);
+ cfg = readl(pll->base + PLL_16FFT_CFG);
for (i = 0; i < 16; i++) {
hsdiv_presence_bit = BIT(16 + i);
hsdiv_ctrl_offs = 0x80 + (i * 4);
/* Enable HSDIV output if present */
if ((hsdiv_presence_bit & cfg) != 0UL) {
- ctrl = readl(pll->reg + hsdiv_ctrl_offs);
+ ctrl = readl(pll->base + hsdiv_ctrl_offs);
ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN;
- writel(ctrl, pll->reg + hsdiv_ctrl_offs);
+ writel(ctrl, pll->base + hsdiv_ctrl_offs);
}
}
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 77acd76..b11e362 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -666,11 +666,12 @@
return i <= 0 ? -ENODATA : i;
}
-static int __of_parse_phandle_with_args(const struct device_node *np,
- const char *list_name,
- const char *cells_name,
- int cell_count, int index,
- struct of_phandle_args *out_args)
+static int __of_root_parse_phandle_with_args(struct device_node *root,
+ const struct device_node *np,
+ const char *list_name,
+ const char *cells_name,
+ int cell_count, int index,
+ struct of_phandle_args *out_args)
{
const __be32 *list, *list_end;
int rc = 0, cur_index = 0;
@@ -706,7 +707,7 @@
* below.
*/
if (cells_name || cur_index == index) {
- node = of_find_node_by_phandle(NULL, phandle);
+ node = of_find_node_by_phandle(root, phandle);
if (!node) {
dm_warn("%s: could not find phandle\n",
np->full_name);
@@ -783,39 +784,65 @@
return rc;
}
-struct device_node *of_parse_phandle(const struct device_node *np,
- const char *phandle_name, int index)
+struct device_node *of_root_parse_phandle(struct device_node *root,
+ const struct device_node *np,
+ const char *phandle_name, int index)
{
struct of_phandle_args args;
if (index < 0)
return NULL;
- if (__of_parse_phandle_with_args(np, phandle_name, NULL, 0, index,
- &args))
+ if (__of_root_parse_phandle_with_args(root, np, phandle_name, NULL, 0,
+ index, &args))
return NULL;
return args.np;
}
+int of_root_parse_phandle_with_args(struct device_node *root,
+ const struct device_node *np,
+ const char *list_name, const char *cells_name,
+ int cell_count, int index,
+ struct of_phandle_args *out_args)
+{
+ if (index < 0)
+ return -EINVAL;
+
+ return __of_root_parse_phandle_with_args(root, np, list_name, cells_name,
+ cell_count, index, out_args);
+}
+
+int of_root_count_phandle_with_args(struct device_node *root,
+ const struct device_node *np,
+ const char *list_name, const char *cells_name,
+ int cell_count)
+{
+ return __of_root_parse_phandle_with_args(root, np, list_name, cells_name,
+ cell_count, -1, NULL);
+}
+
+struct device_node *of_parse_phandle(const struct device_node *np,
+ const char *phandle_name, int index)
+{
+ return of_root_parse_phandle(NULL, np, phandle_name, index);
+}
+
int of_parse_phandle_with_args(const struct device_node *np,
const char *list_name, const char *cells_name,
int cell_count, int index,
struct of_phandle_args *out_args)
{
- if (index < 0)
- return -EINVAL;
-
- return __of_parse_phandle_with_args(np, list_name, cells_name,
- cell_count, index, out_args);
+ return of_root_parse_phandle_with_args(NULL, np, list_name, cells_name,
+ cell_count, index, out_args);
}
int of_count_phandle_with_args(const struct device_node *np,
const char *list_name, const char *cells_name,
int cell_count)
{
- return __of_parse_phandle_with_args(np, list_name, cells_name,
- cell_count, -1, NULL);
+ return of_root_count_phandle_with_args(NULL, np, list_name, cells_name,
+ cell_count);
}
static void of_alias_add(struct alias_prop *ap, struct device_node *np,
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 950895e..c816182 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -879,11 +879,69 @@
return count;
}
-static void ofnode_from_fdtdec_phandle_args(struct fdtdec_phandle_args *in,
+ofnode ofnode_parse_phandle(ofnode node, const char *phandle_name,
+ int index)
+{
+ ofnode phandle;
+
+ if (ofnode_is_np(node)) {
+ struct device_node *np;
+
+ np = of_parse_phandle(ofnode_to_np(node), phandle_name,
+ index);
+ if (!np)
+ return ofnode_null();
+
+ phandle = np_to_ofnode(np);
+ } else {
+ struct fdtdec_phandle_args args;
+
+ if (fdtdec_parse_phandle_with_args(ofnode_to_fdt(node),
+ ofnode_to_offset(node),
+ phandle_name, NULL,
+ 0, index, &args))
+ return ofnode_null();
+
+ phandle = offset_to_ofnode(args.node);
+ }
+
+ return phandle;
+}
+
+ofnode oftree_parse_phandle(oftree tree, ofnode node, const char *phandle_name,
+ int index)
+{
+ ofnode phandle;
+
+ if (ofnode_is_np(node)) {
+ struct device_node *np;
+
+ np = of_root_parse_phandle(tree.np, ofnode_to_np(node),
+ phandle_name, index);
+ if (!np)
+ return ofnode_null();
+
+ phandle = np_to_ofnode(np);
+ } else {
+ struct fdtdec_phandle_args args;
+
+ if (fdtdec_parse_phandle_with_args(tree.fdt,
+ ofnode_to_offset(node),
+ phandle_name, NULL,
+ 0, index, &args))
+ return ofnode_null();
+
+ phandle = noffset_to_ofnode(node, args.node);
+ }
+
+ return phandle;
+}
+
+static void ofnode_from_fdtdec_phandle_args(ofnode node, struct fdtdec_phandle_args *in,
struct ofnode_phandle_args *out)
{
assert(OF_MAX_PHANDLE_ARGS == MAX_PHANDLE_ARGS);
- out->node = offset_to_ofnode(in->node);
+ out->node = noffset_to_ofnode(node, in->node);
out->args_count = in->args_count;
memcpy(out->args, in->args, sizeof(out->args));
}
@@ -923,7 +981,40 @@
cell_count, index, &args);
if (ret)
return ret;
+ ofnode_from_fdtdec_phandle_args(node, &args, out_args);
+ }
+
+ return 0;
+}
+
+int oftree_parse_phandle_with_args(oftree tree, ofnode node, const char *list_name,
+ const char *cells_name, int cell_count,
+ int index,
+ struct ofnode_phandle_args *out_args)
+{
+ if (ofnode_is_np(node)) {
+ struct of_phandle_args args;
+ int ret;
+
+ ret = of_root_parse_phandle_with_args(tree.np,
+ ofnode_to_np(node),
+ list_name, cells_name,
+ cell_count, index,
+ &args);
+ if (ret)
+ return ret;
+ ofnode_from_of_phandle_args(&args, out_args);
+ } else {
+ struct fdtdec_phandle_args args;
+ int ret;
+
+ ret = fdtdec_parse_phandle_with_args(tree.fdt,
+ ofnode_to_offset(node),
+ list_name, cells_name,
+ cell_count, index, &args);
+ if (ret)
+ return ret;
- ofnode_from_fdtdec_phandle_args(&args, out_args);
+ ofnode_from_fdtdec_phandle_args(node, &args, out_args);
}
return 0;
@@ -941,6 +1032,18 @@
cell_count, -1, NULL);
}
+int oftree_count_phandle_with_args(oftree tree, ofnode node, const char *list_name,
+ const char *cells_name, int cell_count)
+{
+ if (ofnode_is_np(node))
+ return of_root_count_phandle_with_args(tree.np, ofnode_to_np(node),
+ list_name, cells_name, cell_count);
+ else
+ return fdtdec_parse_phandle_with_args(tree.fdt,
+ ofnode_to_offset(node), list_name, cells_name,
+ cell_count, -1, NULL);
+}
+
ofnode ofnode_path(const char *path)
{
if (of_live_active())
@@ -1768,6 +1871,21 @@
return ofnode_read_string(uboot, prop_name);
}
+int ofnode_options_get_by_phandle(const char *prop_name, ofnode *nodep)
+{
+ ofnode uboot;
+
+ uboot = ofnode_path("/options/u-boot");
+ if (!ofnode_valid(uboot))
+ return -EINVAL;
+
+ *nodep = ofnode_parse_phandle(uboot, prop_name, 0);
+ if (!ofnode_valid(*nodep))
+ return -EINVAL;
+
+ return 0;
+}
+
int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset)
{
int ret;
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 51262be..53d31b3 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -65,6 +65,14 @@
return "93(02)";/* iMX93 900Mhz Low performance Dual core without NPU */
case MXC_CPU_IMX9301:
return "93(01)";/* iMX93 900Mhz Low performance Single core without NPU */
+ case MXC_CPU_IMX91:
+ return "91(31)";/* iMX91 11x11 Full feature */
+ case MXC_CPU_IMX9121:
+ return "91(21)";/* iMX91 11x11 Low drive mode */
+ case MXC_CPU_IMX9111:
+ return "91(11)";/* iMX91 9x9 Reduced feature */
+ case MXC_CPU_IMX9101:
+ return "91(01)";/* iMX91 9x9 Specific feature */
default:
return "??";
}
@@ -127,6 +135,8 @@
if (IS_ENABLED(CONFIG_IMX8)) {
if (plat->cpu_rsrc == SC_R_A72)
idx = 2; /* use "cpu-thermal1" device */
+ } else if (IS_ENABLED(CONFIG_IMX91)) {
+ idx = 0;
} else {
idx = 1;
}
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index 14278f5..8e350de 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -144,6 +144,10 @@
dram_pll_init(MHZ(400));
dram_disable_bypass();
break;
+ case 1200:
+ dram_pll_init(MHZ(300));
+ dram_disable_bypass();
+ break;
case 1066:
dram_pll_init(MHZ(266));
dram_disable_bypass();
@@ -152,6 +156,10 @@
dram_pll_init(MHZ(233));
dram_disable_bypass();
break;
+ case 800:
+ dram_pll_init(MHZ(200));
+ dram_disable_bypass();
+ break;
case 667:
dram_pll_init(MHZ(167));
dram_disable_bypass();
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 50a6981..76fcd3f 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -219,6 +219,44 @@
val = readl(&at91_port->osr);
return val & mask;
}
+
+static bool at91_is_port_gpio(struct at91_port *at91_port, int offset)
+{
+ u32 mask, val;
+
+ mask = 1 << offset;
+ val = readl(&at91_port->psr);
+ return !!(val & mask);
+}
+
+static void at91_set_port_multi_drive(struct at91_port *at91_port, int offset, int is_on)
+{
+ u32 mask;
+
+ mask = 1 << offset;
+ if (is_on)
+ writel(mask, &at91_port->mder);
+ else
+ writel(mask, &at91_port->mddr);
+}
+
+static bool at91_get_port_multi_drive(struct at91_port *at91_port, int offset)
+{
+ u32 mask, val;
+
+ mask = 1 << offset;
+ val = readl(&at91_port->mdsr);
+ return !!(val & mask);
+}
+
+static bool at91_get_port_pullup(struct at91_port *at91_port, int offset)
+{
+ u32 mask, val;
+
+ mask = 1 << offset;
+ val = readl(&at91_port->pusr);
+ return !(val & mask);
+}
#endif
static void at91_set_port_input(struct at91_port *at91_port, int offset,
@@ -549,13 +587,68 @@
{
struct at91_port_priv *port = dev_get_priv(dev);
- /* GPIOF_FUNC is not implemented yet */
+ if (!at91_is_port_gpio(port->regs, offset))
+ return GPIOF_FUNC;
+
if (at91_get_port_output(port->regs, offset))
return GPIOF_OUTPUT;
else
return GPIOF_INPUT;
}
+static int at91_gpio_set_flags(struct udevice *dev, unsigned int offset,
+ ulong flags)
+{
+ struct at91_port_priv *port = dev_get_priv(dev);
+ ulong supported_mask;
+
+ supported_mask = GPIOD_OPEN_DRAIN | GPIOD_MASK_DIR | GPIOD_PULL_UP;
+ if (flags & ~supported_mask)
+ return -ENOTSUPP;
+
+ if (flags & GPIOD_IS_OUT) {
+ if (flags & GPIOD_OPEN_DRAIN)
+ at91_set_port_multi_drive(port->regs, offset, true);
+ else
+ at91_set_port_multi_drive(port->regs, offset, false);
+
+ at91_set_port_output(port->regs, offset, flags & GPIOD_IS_OUT_ACTIVE);
+
+ } else if (flags & GPIOD_IS_IN) {
+ at91_set_port_input(port->regs, offset, false);
+ }
+ if (flags & GPIOD_PULL_UP)
+ at91_set_port_pullup(port->regs, offset, true);
+
+ return 0;
+}
+
+static int at91_gpio_get_flags(struct udevice *dev, unsigned int offset,
+ ulong *flagsp)
+{
+ struct at91_port_priv *port = dev_get_priv(dev);
+ ulong dir_flags = 0;
+
+ if (at91_get_port_output(port->regs, offset)) {
+ dir_flags |= GPIOD_IS_OUT;
+
+ if (at91_get_port_multi_drive(port->regs, offset))
+ dir_flags |= GPIOD_OPEN_DRAIN;
+
+ if (at91_get_port_value(port->regs, offset))
+ dir_flags |= GPIOD_IS_OUT_ACTIVE;
+ } else {
+ dir_flags |= GPIOD_IS_IN;
+ }
+
+ if (at91_get_port_pullup(port->regs, offset))
+ dir_flags |= GPIOD_PULL_UP;
+
+ *flagsp = dir_flags;
+
+ return 0;
+}
+
static const char *at91_get_bank_name(uint32_t base_addr)
{
switch (base_addr) {
@@ -584,6 +677,8 @@
.get_value = at91_gpio_get_value,
.set_value = at91_gpio_set_value,
.get_function = at91_gpio_get_function,
+ .set_flags = at91_gpio_set_flags,
+ .get_flags = at91_gpio_get_flags,
};
static int at91_gpio_probe(struct udevice *dev)
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 0213271..da929c3 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -705,6 +705,9 @@
if (ops->set_flags) {
ret = ops->set_flags(dev, desc->offset, flags);
} else {
+ if (flags & GPIOD_MASK_PULL)
+ return -EINVAL;
+
if (flags & GPIOD_IS_OUT) {
bool value = flags & GPIOD_IS_OUT_ACTIVE;
diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c
index fc1d418..7cf178f 100644
--- a/drivers/gpio/imx_rgpio2p.c
+++ b/drivers/gpio/imx_rgpio2p.c
@@ -231,7 +231,7 @@
.have_dual_base = true,
};
-static struct imx_rgpio2p_soc_data imx8ulp_data = {
+static struct imx_rgpio2p_soc_data imx8ulp_data __section(".data") = {
.have_dual_base = false,
};
diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c
index 05e0990..7607505 100644
--- a/drivers/led/led-uclass.c
+++ b/drivers/led/led-uclass.c
@@ -232,16 +232,24 @@
#endif
#endif
+static const char *led_get_label(ofnode node)
+{
+ const char *label;
+
+ label = ofnode_read_string(node, "label");
+ if (!label && !ofnode_read_string(node, "compatible"))
+ label = ofnode_get_name(node);
+
+ return label;
+}
+
static int led_post_bind(struct udevice *dev)
{
struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
const char *default_state;
if (!uc_plat->label)
- uc_plat->label = dev_read_string(dev, "label");
-
- if (!uc_plat->label && !dev_read_string(dev, "compatible"))
- uc_plat->label = ofnode_get_name(dev_ofnode(dev));
+ uc_plat->label = led_get_label(dev_ofnode(dev));
uc_plat->default_state = LEDST_COUNT;
@@ -300,15 +308,21 @@
static int led_init(struct uclass *uc)
{
struct led_uc_priv *priv = uclass_get_priv(uc);
+ ofnode led_node;
+ int ret;
#ifdef CONFIG_LED_BOOT
- priv->boot_led_label = ofnode_options_read_str("boot-led");
- priv->boot_led_period = ofnode_options_read_int("boot-led-period", 250);
+ ret = ofnode_options_get_by_phandle("boot-led", &led_node);
+ if (!ret)
+ priv->boot_led_label = led_get_label(led_node);
+ priv->boot_led_period = ofnode_options_read_int("boot-led-period-ms", 250);
#endif
#ifdef CONFIG_LED_ACTIVITY
- priv->activity_led_label = ofnode_options_read_str("activity-led");
- priv->activity_led_period = ofnode_options_read_int("activity-led-period",
+ ret = ofnode_options_get_by_phandle("activity-led", &led_node);
+ if (!ret)
+ priv->activity_led_label = led_get_label(led_node);
+ priv->activity_led_period = ofnode_options_read_int("activity-led-period-ms",
250);
#endif
diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
index 10f0173..3cb38aa 100644
--- a/drivers/misc/i2c_eeprom.c
+++ b/drivers/misc/i2c_eeprom.c
@@ -264,6 +264,13 @@
.offset_len = 2,
};
+static const struct i2c_eeprom_drv_data st24256e_wlp_data = {
+ .size = 64,
+ .pagesize = 64,
+ .addr_offset_mask = 0,
+ .offset_len = 2,
+};
+
static const struct i2c_eeprom_drv_data atmel24c512_data = {
.size = 65536,
.pagesize = 64,
@@ -287,6 +294,7 @@
{ .compatible = "atmel,24c128", (ulong)&atmel24c128_data },
{ .compatible = "atmel,24c256", (ulong)&atmel24c256_data },
{ .compatible = "atmel,24c512", (ulong)&atmel24c512_data },
+ { .compatible = "st,24256e-wl", (ulong)&st24256e_wlp_data },
{ }
};
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index 591d71b..a40c8ba 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -951,6 +951,26 @@
return ret;
}
+int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ struct sc_rpc_msg_s msg;
+ int size = sizeof(struct sc_rpc_msg_s);
+ int ret;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (u8)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (u8)TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG;
+ RPC_U8(&msg, 0U) = (u8)cmd;
+ RPC_SIZE(&msg) = 2U;
+
+ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+ if (ret)
+ printf("%s: res:%d\n", __func__, RPC_R8(&msg));
+
+ return ret;
+}
+
int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
sc_faddr_t addr)
{
diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c
index 99a18a1..0774e0a 100644
--- a/drivers/misc/k3_avs.c
+++ b/drivers/misc/k3_avs.c
@@ -121,6 +121,11 @@
if (!vd->supply)
return -ENODEV;
+ if (!volt) {
+ dev_err(priv->dev, "No efuse found for opp_%d\n", opp_id);
+ return -EINVAL;
+ }
+
vd->opp = opp_id;
vd->flags |= VD_FLAG_INIT_DONE;
@@ -189,6 +194,33 @@
printf("No matching OPP found for freq %d.\n", freq);
+ return -EINVAL;
+}
+
+/**
+ * k3_check_opp: Check for presence of opp efuse
+ * @dev: AVS device
+ * @vdd_id: voltage domain ID
+ * @opp_id: opp id to check if voltage is present
+ *
+ * Checks to see if an opp has voltage. k3_avs probe will populate
+ * voltage data if efuse is present. Returns 0 if data is valid.
+ */
+int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id)
+{
+ struct k3_avs_privdata *priv = dev_get_priv(dev);
+ struct vd_data *vd;
+ int volt;
+
+ vd = get_vd(priv, vdd_id);
+ if (!vd)
+ return -EINVAL;
+
+ volt = vd->opps[opp_id].volt;
+ if (volt)
+ return 0;
+
+ printf("No efuse found for opp_%d\n", opp_id);
return -EINVAL;
}
@@ -501,6 +533,10 @@
.dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */
.clk_id = 2, /* ARM clock */
.opps = {
+ [AM6_OPP_LOW] = {
+ .volt = 0, /* voltage TBD after OPP fuse reading */
+ .freq = 1000000000,
+ },
[AM6_OPP_NOM] = {
.volt = 880000, /* TBD in DM */
.freq = 2000000000,
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 817fab4..25f187a 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -2205,7 +2205,6 @@
static int atmel_nand_controller_probe(struct udevice *dev)
{
const struct atmel_nand_controller_caps *caps;
- struct udevice *pmecc_dev;
caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev);
if (!caps) {
@@ -2213,12 +2212,6 @@
return -EINVAL;
}
- /* Probe pmecc driver */
- if (uclass_get_device(UCLASS_MTD, 1, &pmecc_dev)) {
- printf("%s: get device fail\n", __func__);
- return -EINVAL;
- }
-
return caps->ops->probe(dev, caps);
}
diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c b/drivers/mtd/nand/raw/atmel/pmecc.c
index 51f6bd2..e500a0f 100644
--- a/drivers/mtd/nand/raw/atmel/pmecc.c
+++ b/drivers/mtd/nand/raw/atmel/pmecc.c
@@ -913,6 +913,7 @@
ret = ofnode_parse_phandle_with_args(userdev->node_,
"ecc-engine",
NULL, 0, 0, &args);
+ /* Probe pmecc driver */
ret = uclass_get_device_by_ofnode(UCLASS_MTD, args.node, &pdev);
if (ret)
return NULL;
diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c
index 90a7c4c..9face5f 100644
--- a/drivers/mtd/ubispl/ubispl.c
+++ b/drivers/mtd/ubispl/ubispl.c
@@ -113,7 +113,7 @@
crc = crc32(UBI_CRC32_INIT, &vtbl[i], UBI_VTBL_RECORD_SIZE_CRC);
if (be32_to_cpu(vtbl[i].crc) != crc) {
- ubi_err("bad CRC at record %u: %#08x, not %#08x",
+ ubi_err("bad CRC at record %u: #%08x, not #%08x",
i, crc, be32_to_cpu(vtbl[i].crc));
ubi_dump_vtbl_record(&vtbl[i], i);
return 1;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index d6d5cb5..eca681b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -160,7 +160,7 @@
}
}
-static void fec_mii_setspeed(struct ethernet_regs *eth)
+static void fec_mii_setspeed(struct udevice *dev, struct ethernet_regs *eth)
{
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
@@ -182,7 +182,7 @@
u32 hold;
int ret;
- ret = fec_get_clk_rate(NULL, 0);
+ ret = fec_get_clk_rate(dev, 0);
if (ret < 0) {
printf("Can't find FEC0 clk rate: %d\n", ret);
return;
@@ -581,7 +581,7 @@
fec_reg_setup(fec);
if (fec->xcv_type != SEVENWIRE)
- fec_mii_setspeed(fec->bus->priv);
+ fec_mii_setspeed(dev, fec->bus->priv);
/* Set Opcode/Pause Duration Register */
writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
@@ -996,7 +996,7 @@
free(fec->tbd_base);
}
-struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
+struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id)
{
struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
struct mii_dev *bus;
@@ -1018,7 +1018,7 @@
free(bus);
return NULL;
}
- fec_mii_setspeed(eth);
+ fec_mii_setspeed(dev, eth);
return bus;
}
@@ -1354,10 +1354,10 @@
if (!bus) {
dm_mii_bus = false;
#ifdef CONFIG_FEC_MXC_MDIO_BASE
- bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
+ bus = fec_get_miibus(dev, (ulong)CONFIG_FEC_MXC_MDIO_BASE,
dev_seq(dev));
#else
- bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev));
+ bus = fec_get_miibus(dev, (ulong)priv->eth, dev_seq(dev));
#endif
}
if (!bus) {
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index f1401d2..231764e 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -649,7 +649,6 @@
int ravb_of_to_plat(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
- const fdt32_t *cell;
pdata->iobase = dev_read_addr(dev);
@@ -657,10 +656,7 @@
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
- pdata->max_speed = 1000;
- cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
- if (cell)
- pdata->max_speed = fdt32_to_cpu(*cell);
+ pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000);
sprintf(bb_miiphy_buses[0].name, dev->name);
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c
index b393127..b37282f 100644
--- a/drivers/pinctrl/exynos/pinctrl-exynos.c
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -114,8 +114,8 @@
int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
- unsigned int count, idx;
- unsigned int pinvals[PINCFG_TYPE_NUM];
+ int count;
+ unsigned int idx, pinvals[PINCFG_TYPE_NUM];
/*
* refer to the following document for the pinctrl bindings
diff --git a/drivers/pinctrl/nxp/pinctrl-imx93.c b/drivers/pinctrl/nxp/pinctrl-imx93.c
index 9a5b9de..8d8ffec 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx93.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx93.c
@@ -22,6 +22,7 @@
static const struct udevice_id imx93_pinctrl_match[] = {
{ .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
+ { .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c
index e88ec1c..3c751e9 100644
--- a/drivers/pinctrl/renesas/rzg2l-pfc.c
+++ b/drivers/pinctrl/renesas/rzg2l-pfc.c
@@ -180,7 +180,7 @@
RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
@@ -189,7 +189,7 @@
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -381,7 +381,7 @@
}
switch (param) {
- case PIN_CONFIG_INPUT_ENABLE: {
+ case PIN_CONFIG_INPUT_ENABLE:
if (!(cfg & PIN_CFG_IEN)) {
dev_err(dev, "pin does not support IEN\n");
return -EINVAL;
@@ -391,21 +391,12 @@
port_offset, pin, argument);
rzg2l_rmw_pin_config(data, IEN(port_offset), pin, IEN_MASK, !!argument);
break;
- }
case PIN_CONFIG_POWER_SOURCE: {
- u32 pwr_reg = 0x0;
+ bool support_2500 = false;
+ u32 pwr_reg;
+ u32 value;
- /* argument is in mV */
- if (argument != 1800 && argument != 3300) {
- dev_err(dev, "Invalid mV %u\n", argument);
- return -EINVAL;
- }
-
- /*
- * TODO: PIN_CFG_IO_VMC_ETH0 & PIN_CFG_IO_VMC_ETH1 will be
- * handled when the RZ/G2L Ethernet driver is added.
- */
if (cfg & PIN_CFG_IO_VMC_SD0) {
dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n",
port_offset, pin, argument);
@@ -418,13 +409,68 @@
dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n",
port_offset, pin, argument);
pwr_reg = QSPI;
+ } else if (cfg & PIN_CFG_IO_VMC_ETH0) {
+ dev_dbg(dev, "port off %u:%u set ETH0 PVDD=%u\n",
+ port_offset, pin, argument);
+ pwr_reg = ETH_POC(0);
+ support_2500 = true;
+ } else if (cfg & PIN_CFG_IO_VMC_ETH1) {
+ dev_dbg(dev, "port off %u:%u set ETH1 PVDD=%u\n",
+ port_offset, pin, argument);
+ pwr_reg = ETH_POC(1);
+ support_2500 = true;
} else {
- dev_dbg(dev, "pin power source is not selectable\n");
+ dev_dbg(dev, "port off %u:%u PVDD is not selectable\n",
+ port_offset, pin);
+ return -EINVAL;
+ }
+
+ /* argument is in mV */
+ switch (argument) {
+ case 1800:
+ value = PVDD_1800;
+ break;
+ case 3300:
+ value = PVDD_3300;
+ break;
+ case 2500:
+ if (support_2500) {
+ value = PVDD_2500;
+ break;
+ }
+ fallthrough;
+ default:
+ dev_err(dev, "Invalid mV %u\n", argument);
return -EINVAL;
}
+ writel(value, data->base + pwr_reg);
+ break;
+ }
+
+ case PIN_CONFIG_OUTPUT_ENABLE: {
+ u8 ch;
+
+ if (!(cfg & PIN_CFG_OEN)) {
+ dev_err(dev, "pin does not support OEN\n");
+ return -EINVAL;
+ }
+
+ /*
+ * We can determine which Ethernet interface we're dealing with from
+ * the caps.
+ */
+ if (cfg & PIN_CFG_IO_VMC_ETH0)
+ ch = 0;
+ else /* PIN_CFG_IO_VMC_ETH1 */
+ ch = 1;
+
+ dev_dbg(dev, "set ETH%u TXC OEN=%u\n", ch, argument);
+ if (argument)
+ clrbits_8(data->base + ETH_MODE, BIT(ch));
+ else
+ setbits_8(data->base + ETH_MODE, BIT(ch));
+
- writel((argument == 1800) ? PVDD_1800 : PVDD_3300,
- data->base + pwr_reg);
break;
}
@@ -521,6 +567,7 @@
static const struct pinconf_param rzg2l_pinconf_params[] = {
{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
+ { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
{ "power-source", PIN_CONFIG_POWER_SOURCE, 3300 /* mV */ },
};
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index decd080..09567eb 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -9,6 +9,7 @@
#include <errno.h>
#include <dm.h>
#include <log.h>
+#include <dm/device_compat.h>
#include <dm/uclass-internal.h>
#include <linux/delay.h>
#include <power/pmic.h>
@@ -43,8 +44,7 @@
{
int delay = DIV_ROUND_UP(abs(new_uV - old_uV), ramp_delay);
- debug("regulator %s: delay %u us (%d uV -> %d uV)\n", dev->name, delay,
- old_uV, new_uV);
+ dev_dbg(dev, "delay %u us (%d uV -> %d uV)\n", delay, old_uV, new_uV);
udelay(delay);
}
@@ -263,7 +263,7 @@
for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev;
ret = uclass_find_next_device(&dev)) {
if (ret) {
- debug("regulator %s, ret=%d\n", dev->name, ret);
+ dev_dbg(dev, "ret=%d\n", ret);
continue;
}
@@ -439,16 +439,15 @@
/* Regulator's mandatory constraint */
uc_pdata->name = dev_read_string(dev, property);
if (!uc_pdata->name) {
- debug("%s: dev '%s' has no property '%s'\n",
- __func__, dev->name, property);
+ dev_dbg(dev, "has no property '%s'\n", property);
uc_pdata->name = dev_read_name(dev);
if (!uc_pdata->name)
return -EINVAL;
}
if (!regulator_name_is_unique(dev, uc_pdata->name)) {
- debug("'%s' of dev: '%s', has nonunique value: '%s\n",
- property, dev->name, uc_pdata->name);
+ dev_err(dev, "'%s' has nonunique value: '%s\n",
+ property, uc_pdata->name);
return -EINVAL;
}
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 525b6d5..6e9202b 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -216,9 +216,6 @@
req_type = readl(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03;
- debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n",
- __func__, req_type, counter, ddrss->instance);
-
if (req_type == 1)
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
else if (req_type == 2)
@@ -245,8 +242,6 @@
{
struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
- debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
-
switch (ddrss->dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
break;
diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c
index ab1836b..0b3941b 100644
--- a/drivers/remoteproc/rproc-elf-loader.c
+++ b/drivers/remoteproc/rproc-elf-loader.c
@@ -6,6 +6,7 @@
#include <dm.h>
#include <elf.h>
#include <log.h>
+#include <mapmem.h>
#include <remoteproc.h>
#include <asm/cache.h>
#include <dm/device_compat.h>
@@ -180,6 +181,7 @@
for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
void *dst = (void *)(uintptr_t)phdr->p_paddr;
void *src = (void *)addr + phdr->p_offset;
+ ulong dst_addr;
if (phdr->p_type != PT_LOAD)
continue;
@@ -195,10 +197,11 @@
if (phdr->p_filesz != phdr->p_memsz)
memset(dst + phdr->p_filesz, 0x00,
phdr->p_memsz - phdr->p_filesz);
- flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN),
- roundup((unsigned long)dst + phdr->p_filesz,
+ dst_addr = map_to_sysmem(dst);
+ flush_cache(rounddown(dst_addr, ARCH_DMA_MINALIGN),
+ roundup(dst_addr + phdr->p_filesz,
ARCH_DMA_MINALIGN) -
- rounddown((unsigned long)dst, ARCH_DMA_MINALIGN));
+ rounddown(dst_addr, ARCH_DMA_MINALIGN));
}
return 0;
@@ -377,6 +380,7 @@
const struct dm_rproc_ops *ops;
Elf32_Shdr *shdr;
void *src, *dst;
+ ulong dst_addr;
shdr = rproc_elf32_find_rsc_table(dev, fw_addr, fw_size);
if (!shdr)
@@ -398,10 +402,10 @@
(ulong)dst, *rsc_size);
memcpy(dst, src, *rsc_size);
- flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN),
- roundup((unsigned long)dst + *rsc_size,
- ARCH_DMA_MINALIGN) -
- rounddown((unsigned long)dst, ARCH_DMA_MINALIGN));
+ dst_addr = map_to_sysmem(dst);
+ flush_cache(rounddown(dst_addr, ARCH_DMA_MINALIGN),
+ roundup(dst_addr + *rsc_size, ARCH_DMA_MINALIGN) -
+ rounddown(dst_addr, ARCH_DMA_MINALIGN));
return 0;
}
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 7fc53a6..9c2d139 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -203,6 +203,7 @@
config RTC_PL031
bool "Enable ARM AMBA PL031 RTC driver"
+ depends on DM_RTC
help
The ARM PrimeCell Real Time Clock (PL031) is an optional SoC
peripheral based on the Advanced Microcontroller Bus Architecture
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3f6860f..c3b884b 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -12,7 +12,6 @@
#include <log.h>
#include <ns16550.h>
#include <reset.h>
-#include <serial.h>
#include <spl.h>
#include <watchdog.h>
#include <asm/global_data.h>
@@ -158,7 +157,7 @@
#endif /* CONFIG_NS16550_DYNAMIC */
-static void ns16550_writeb(struct ns16550 *port, int offset, int value)
+void ns16550_writeb(struct ns16550 *port, int offset, int value)
{
struct ns16550_plat *plat = port->plat;
unsigned char *addr;
@@ -193,13 +192,6 @@
return plat->fcr;
}
-/* We can clean these up once everything is moved to driver model */
-#define serial_out(value, addr) \
- ns16550_writeb(com_port, \
- (unsigned char *)addr - (unsigned char *)com_port, value)
-#define serial_in(addr) \
- ns16550_readb(com_port, \
- (unsigned char *)addr - (unsigned char *)com_port)
#else
static u32 ns16550_getfcr(struct ns16550 *port)
{
@@ -214,7 +206,7 @@
return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
}
-static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor)
+void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor)
{
/* to keep serial format, read lcr before writing BKSE */
int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
@@ -380,7 +372,7 @@
#endif
#if CONFIG_IS_ENABLED(DM_SERIAL)
-static int ns16550_serial_putc(struct udevice *dev, const char ch)
+int ns16550_serial_putc(struct udevice *dev, const char ch)
{
struct ns16550 *const com_port = dev_get_priv(dev);
@@ -400,7 +392,7 @@
return 0;
}
-static int ns16550_serial_pending(struct udevice *dev, bool input)
+int ns16550_serial_pending(struct udevice *dev, bool input)
{
struct ns16550 *const com_port = dev_get_priv(dev);
@@ -410,7 +402,7 @@
return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1;
}
-static int ns16550_serial_getc(struct udevice *dev)
+int ns16550_serial_getc(struct udevice *dev)
{
struct ns16550 *const com_port = dev_get_priv(dev);
@@ -420,7 +412,7 @@
return serial_in(&com_port->rbr);
}
-static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
+int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
{
struct ns16550 *const com_port = dev_get_priv(dev);
struct ns16550_plat *plat = com_port->plat;
@@ -433,7 +425,7 @@
return 0;
}
-static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config)
+int ns16550_serial_setconfig(struct udevice *dev, uint serial_config)
{
struct ns16550 *const com_port = dev_get_priv(dev);
int lcr_val = UART_LCR_WLS_8;
@@ -466,8 +458,7 @@
return 0;
}
-static int ns16550_serial_getinfo(struct udevice *dev,
- struct serial_device_info *info)
+int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info)
{
struct ns16550 *const com_port = dev_get_priv(dev);
struct ns16550_plat *plat = com_port->plat;
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index 9467265..224d9cb 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -15,6 +15,12 @@
#include <clk.h>
#include <linux/err.h>
+/*
+ * These are the definitions for the MDR1 register
+ */
+#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
+#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */
+
#ifndef CFG_SYS_NS16550_CLK
#define CFG_SYS_NS16550_CLK 0
#endif
@@ -151,6 +157,54 @@
};
#endif /* OF_REAL */
+static int omap_serial_calc_divisor(struct ns16550 *com_port, int clock, int baudrate)
+{
+ unsigned int div_13, div_16;
+ unsigned int abs_d13, abs_d16;
+ /*
+ * The below logic sets the MDR1 register based on clock and baudrate.
+ */
+ div_13 = DIV_ROUND_CLOSEST(clock, 13 * baudrate);
+ div_16 = DIV_ROUND_CLOSEST(clock, 16 * baudrate);
+
+ if (!div_13)
+ div_13 = 1;
+ if (!div_16)
+ div_16 = 1;
+
+ abs_d13 = abs(baudrate - clock / 13 / div_13);
+ abs_d16 = abs(baudrate - clock / 16 / div_16);
+
+ if (abs_d13 >= abs_d16)
+ serial_out(UART_OMAP_MDR1_16X_MODE, &com_port->mdr1);
+ else
+ serial_out(UART_OMAP_MDR1_13X_MODE, &com_port->mdr1);
+
+ return abs_d13 >= abs_d16 ? div_16 : div_13;
+}
+
+static int omap_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct ns16550 *const com_port = dev_get_priv(dev);
+ struct ns16550_plat *plat = com_port->plat;
+ int clock_divisor;
+
+ clock_divisor = omap_serial_calc_divisor(com_port, plat->clock, baudrate);
+
+ ns16550_setbrg(com_port, clock_divisor);
+
+ return 0;
+}
+
+const struct dm_serial_ops omap_serial_ops = {
+ .putc = ns16550_serial_putc,
+ .pending = ns16550_serial_pending,
+ .getc = ns16550_serial_getc,
+ .setbrg = omap_serial_setbrg,
+ .setconfig = ns16550_serial_setconfig,
+ .getinfo = ns16550_serial_getinfo,
+};
+
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
U_BOOT_DRIVER(omap_serial) = {
.name = "omap_serial",
@@ -162,7 +216,7 @@
#endif
.priv_auto = sizeof(struct ns16550),
.probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
+ .ops = &omap_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
#endif
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 222f828..dcf28c7 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -125,49 +125,8 @@
return 0;
}
-#if defined(CONFIG_DM_GPIO)
-int cadence_qspi_versal_flash_reset(struct udevice *dev)
-{
- struct gpio_desc gpio;
- u32 reset_gpio;
- int ret;
-
- /* request gpio and set direction as output set to 1 */
- ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio,
- GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
- if (ret) {
- printf("%s: unable to reset ospi flash device", __func__);
- return ret;
- }
-
- reset_gpio = PMIO_NODE_ID_BASE + gpio.offset;
-
- /* Request for pin */
- xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL);
-
- /* Enable hysteresis in cmos receiver */
- xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio,
- PM_PINCTRL_CONFIG_SCHMITT_CMOS,
- PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL);
-
- /* Disable Tri-state */
- xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio,
- PM_PINCTRL_CONFIG_TRI_STATE,
- PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL);
- udelay(1);
-
- /* Set value 0 to pin */
- dm_gpio_set_value(&gpio, 0);
- udelay(1);
-
- /* Set value 1 to pin */
- dm_gpio_set_value(&gpio, 1);
- udelay(1);
-
- return 0;
-}
-#else
-int cadence_qspi_versal_flash_reset(struct udevice *dev)
+#if !CONFIG_IS_ENABLED(DM_GPIO)
+int cadence_qspi_flash_reset(struct udevice *dev)
{
/* CRP WPROT */
writel(0, WPROT_CRP);
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 331a46d..623904e 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -33,7 +33,7 @@
return 0;
}
-__weak int cadence_qspi_versal_flash_reset(struct udevice *dev)
+__weak int cadence_qspi_flash_reset(struct udevice *dev)
{
return 0;
}
@@ -252,7 +252,9 @@
priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
/* Reset ospi flash device */
- return cadence_qspi_versal_flash_reset(bus);
+ return cadence_qspi_flash_reset(bus);
+
+ return 0;
}
static int cadence_spi_remove(struct udevice *dev)
diff --git a/drivers/sysinfo/gazerbeam.h b/drivers/sysinfo/gazerbeam.h
index 6bf3c00..047f365 100644
--- a/drivers/sysinfo/gazerbeam.h
+++ b/drivers/sysinfo/gazerbeam.h
@@ -8,8 +8,8 @@
#include <sysinfo.h>
enum {
- BOARD_HWVERSION = SYSINFO_ID_BOARD_MODEL,
- BOARD_MULTICHANNEL = SYSINFO_ID_USER,
+ BOARD_HWVERSION = SYSID_BOARD_MODEL,
+ BOARD_MULTICHANNEL = SYSID_USER,
BOARD_VARIANT
};
diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c
index aaca318..66d2a91 100644
--- a/drivers/sysinfo/gpio.c
+++ b/drivers/sysinfo/gpio.c
@@ -38,7 +38,7 @@
struct sysinfo_gpio_priv *priv = dev_get_priv(dev);
switch (id) {
- case SYSINFO_ID_BOARD_MODEL:
+ case SYSID_BOARD_MODEL:
*val = priv->revision;
return 0;
default:
@@ -51,7 +51,7 @@
struct sysinfo_gpio_priv *priv = dev_get_priv(dev);
switch (id) {
- case SYSINFO_ID_BOARD_MODEL: {
+ case SYSID_BOARD_MODEL: {
const char *name = NULL;
int i, ret;
u32 revision;
diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c
index 37e2ccc..2994df9 100644
--- a/drivers/sysinfo/rcar3.c
+++ b/drivers/sysinfo/rcar3.c
@@ -46,7 +46,7 @@
struct sysinfo_rcar_priv *priv = dev_get_priv(dev);
switch (id) {
- case SYSINFO_ID_BOARD_MODEL:
+ case SYSID_BOARD_MODEL:
strncpy(val, priv->boardmodel, size);
val[size - 1] = '\0';
return 0;
diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h
index d9c5804..a7cbac0 100644
--- a/drivers/sysinfo/sandbox.h
+++ b/drivers/sysinfo/sandbox.h
@@ -5,7 +5,7 @@
*/
enum {
- BOOL_CALLED_DETECT = SYSINFO_ID_USER,
+ BOOL_CALLED_DETECT = SYSID_USER,
INT_TEST1,
INT_TEST2,
STR_VACATIONSPOT,
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 2ab41cb..55e62b3 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -51,7 +51,8 @@
};
static int dwc3_generic_probe(struct udevice *dev,
- struct dwc3_generic_priv *priv)
+ struct dwc3_generic_priv *priv,
+ enum usb_dr_mode mode)
{
int rc;
struct dwc3_generic_plat *plat = dev_get_plat(dev);
@@ -62,7 +63,7 @@
dwc3->dev = dev;
dwc3->maximum_speed = plat->maximum_speed;
- dwc3->dr_mode = plat->dr_mode;
+ dwc3->dr_mode = mode;
#if CONFIG_IS_ENABLED(OF_CONTROL)
dwc3_of_parse(dwc3);
@@ -197,7 +198,7 @@
{
struct dwc3_generic_priv *priv = dev_get_priv(dev);
- return dwc3_generic_probe(dev, priv);
+ return dwc3_generic_probe(dev, priv, USB_DR_MODE_PERIPHERAL);
}
static int dwc3_generic_peripheral_remove(struct udevice *dev)
@@ -241,7 +242,7 @@
struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
int rc;
- rc = dwc3_generic_probe(dev, &priv->gen_priv);
+ rc = dwc3_generic_probe(dev, &priv->gen_priv, USB_DR_MODE_HOST);
if (rc)
return rc;
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0e45f0a..b39b254 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -351,6 +351,13 @@
In the single stage mode, when the timeout is reached, your system
will be reset by WS1. The first signal (WS0) is ignored.
+config WDT_SIEMENS_PMIC
+ bool "Enable PMIC Watchdog Timer support for Siemens platforms"
+ depends on ARCH_IMX8 && WDT
+ help
+ Select this to enable the PMIC watchdog driver controlled via
+ IMX8 SCU API found on Siemens platforms.
+
config WDT_SL28CPLD
bool "sl28cpld watchdog timer support"
depends on WDT && SL28CPLD
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 0b107c0..9b6b1a8 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -45,6 +45,7 @@
obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
+obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o
obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o
diff --git a/drivers/watchdog/siemens_pmic_wdt.c b/drivers/watchdog/siemens_pmic_wdt.c
new file mode 100644
index 0000000..87e817b
--- /dev/null
+++ b/drivers/watchdog/siemens_pmic_wdt.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for a PMIC watchdog timer controlled via Siemens SCU firmware
+ * extensions. Only useful on some Siemens i.MX8-based platforms as
+ * special NXP SCFW is needed which provides the needed SCU API.
+ *
+ * Copyright (C) 2024 Siemens AG
+ */
+
+#include <dm.h>
+#include <wdt.h>
+#include <firmware/imx/sci/sci.h>
+
+/* watchdog commands */
+#define CMD_START_WDT 0x55
+#define CMD_STOP_WDT 0x45
+#define CMD_PING_WDT 0x35
+
+static int scu_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ /* start external watchdog via Timer API */
+ return sc_timer_control_siemens_pmic_wdog(-1, CMD_START_WDT);
+}
+
+static int scu_wdt_stop(struct udevice *dev)
+{
+ /* stop external watchdog via Timer API */
+ return sc_timer_control_siemens_pmic_wdog(-1, CMD_STOP_WDT);
+}
+
+static int scu_wdt_reset(struct udevice *dev)
+{
+ return sc_timer_control_siemens_pmic_wdog(-1, CMD_PING_WDT);
+}
+
+static int scu_wdt_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+ return 0;
+}
+
+static const struct wdt_ops scu_wdt_ops = {
+ .reset = scu_wdt_reset,
+ .start = scu_wdt_start,
+ .stop = scu_wdt_stop,
+};
+
+static const struct udevice_id scu_wdt_ids[] = {
+ { .compatible = "siemens,scu-wdt" },
+ { }
+};
+
+U_BOOT_DRIVER(scu_wdt) = {
+ .name = "scu_wdt",
+ .id = UCLASS_WDT,
+ .of_match = scu_wdt_ids,
+ .probe = scu_wdt_probe,
+ .ops = &scu_wdt_ops,
+};
diff --git a/dts/upstream/include/dt-bindings/clock/imx93-clock.h b/dts/upstream/include/dt-bindings/clock/imx93-clock.h
index 787c9e7..6c68506 100644
--- a/dts/upstream/include/dt-bindings/clock/imx93-clock.h
+++ b/dts/upstream/include/dt-bindings/clock/imx93-clock.h
@@ -204,6 +204,10 @@
#define IMX93_CLK_A55_SEL 199
#define IMX93_CLK_A55_CORE 200
#define IMX93_CLK_PDM_IPG 201
-#define IMX93_CLK_END 202
+#define IMX91_CLK_ENET1_QOS_TSN 202
+#define IMX91_CLK_ENET_TIMER 203
+#define IMX91_CLK_ENET2_REGULAR 204
+#define IMX91_CLK_ENET2_REGULAR_GATE 205
+#define IMX91_CLK_ENET1_QOS_TSN_GATE 206
#endif
diff --git a/dts/upstream/src/arm64/freescale/imx91-11x11-evk.dts b/dts/upstream/src/arm64/freescale/imx91-11x11-evk.dts
new file mode 100644
index 0000000..65571fc
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx91-11x11-evk.dts
@@ -0,0 +1,875 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx91.dtsi"
+
+/ {
+ compatible = "fsl,imx91-11x11-evk", "fsl,imx91";
+ model = "NXP i.MX91 11X11 EVK board";
+
+ aliases {
+ ethernet0 = &fec;
+ ethernet1 = &eqos;
+ rtc0 = &bbnsm_rtc;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vref_1v8";
+ };
+
+ reg_audio_pwr: regulator-audio-pwr {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "audio-pwr";
+ gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc3_vmmc: regulator-usdhc3 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "WLAN_EN";
+ gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * IW612 wifi chip needs more delay than other wifi chips to complete
+ * the host interface initialization after power up, otherwise the
+ * internal state of IW612 may be unstable, resulting in the failure of
+ * the SDIO3.0 switch voltage.
+ */
+ startup-delay-us = <20000>;
+ };
+
+ reg_vdd_12v: regulator-vdd-12v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <12000000>;
+ regulator-min-microvolt = <12000000>;
+ regulator-name = "reg_vdd_12v";
+ gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vrpi_3v3: regulator-vrpi-3v3 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VRPI_3V3";
+ vin-supply = <&buck4>;
+ gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vrpi_5v: regulator-vrpi-5v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "VRPI_5V";
+ gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x40000000>;
+ reusable;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&eqos {
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_eqos>;
+ pinctrl-1 = <&pinctrl_eqos_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ eee-broken-1000t;
+ };
+ };
+};
+
+&fec {
+ phy-handle = <ðphy2>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_fec>;
+ pinctrl-1 = <&pinctrl_fec_sleep>;
+ pinctrl-names = "default", "sleep";
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ eee-broken-1000t;
+ };
+ };
+};
+
+/*
+ * When add, delete or change any target device setting in &lpi2c1,
+ * please synchronize the changes to the &i3c1 bus in imx91-11x11-evk-i3c.dts.
+ */
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ codec: wm8962@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clk IMX93_CLK_SAI3_GATE>;
+ AVDD-supply = <®_audio_pwr>;
+ CPVDD-supply = <®_audio_pwr>;
+ DBVDD-supply = <®_audio_pwr>;
+ DCVDD-supply = <®_audio_pwr>;
+ MICVDD-supply = <®_audio_pwr>;
+ PLLVDD-supply = <®_audio_pwr>;
+ SPKVDD1-supply = <®_audio_pwr>;
+ SPKVDD2-supply = <®_audio_pwr>;
+ gpio-cfg = <
+ 0x0000 /* 0:Default */
+ 0x0000 /* 1:Default */
+ 0x0000 /* 2:FN_DMICCLK */
+ 0x0000 /* 3:Default */
+ 0x0000 /* 4:FN_DMICCDAT */
+ 0x0000 /* 5:Default */
+ >;
+ };
+
+ lsm6dsm@6a {
+ compatible = "st,lsm6dso";
+ reg = <0x6a>;
+ };
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio3>;
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ pinctrl-names = "default";
+ };
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&pcal6524>;
+
+ regulators {
+
+ buck1: BUCK1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2237500>;
+ regulator-min-microvolt = <650000>;
+ regulator-name = "BUCK1";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2187500>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK2";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK4";
+ };
+
+ buck5: BUCK5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK5";
+ };
+
+ buck6: BUCK6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK6";
+ };
+
+ ldo1: LDO1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1600000>;
+ regulator-name = "LDO1";
+ };
+
+ ldo4: LDO4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <800000>;
+ regulator-name = "LDO4";
+ };
+
+ ldo5: LDO5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "LDO5";
+ };
+ };
+ };
+
+ adp5585: io-expander@34 {
+ compatible = "adi,adp5585-00", "adi,adp5585";
+ reg = <0x34>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #pwm-cells = <3>;
+ gpio-reserved-ranges = <5 1>;
+
+ exp-sel-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+};
+
+&lpi2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio3>;
+ status = "okay";
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <15000000>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
+ ptn5110_2: tcpc@51 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x51>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio3>;
+ status = "okay";
+
+ typec2_con: connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <15000000>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec2_dr_sw: endpoint {
+ remote-endpoint = <&usb2_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
+ pcf2131: rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&pcal6524>;
+ status = "okay";
+ };
+};
+
+&lpuart1 {
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lpuart5 {
+ pinctrl-0 = <&pinctrl_uart5>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+
+ port {
+ usb2_drd_sw: endpoint {
+ remote-endpoint = <&typec2_dr_sw>;
+ };
+ };
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&wdog3 {
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
+ MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
+ MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
+ MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
+ MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_eqos_sleep: eqossleepgrp {
+ fsl,pins = <
+ MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
+ MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
+ MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
+ MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
+ MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
+ MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
+ MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
+ MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
+ MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
+ MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
+ MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
+ MX91_PAD_ENET1_TD3__GPIO4_IO3 0x31e
+ MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
+ MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e
+ MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e
+ MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
+ MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
+ MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
+ MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e
+ MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
+ MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
+ MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
+ MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
+ MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
+ MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
+ MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
+ MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_fec_sleep: fecsleepgrp {
+ fsl,pins = <
+ MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
+ MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
+ MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
+ MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
+ MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
+ MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e
+ MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
+ MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
+ MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
+ MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
+ MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
+ MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
+ MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
+ MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX91_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_flexcan2_sleep: flexcan2sleepgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e
+ MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e
+ >;
+ };
+
+ pinctrl_lcdif_gpio: lcdifgpiogrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO00__GPIO2_IO0 0x51e
+ MX91_PAD_GPIO_IO01__GPIO2_IO1 0x51e
+ MX91_PAD_GPIO_IO02__GPIO2_IO2 0x51e
+ MX91_PAD_GPIO_IO03__GPIO2_IO3 0x51e
+ >;
+ };
+
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e
+ MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e
+ MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e
+ MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e
+ MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e
+ MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e
+ MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e
+ MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e
+ MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e
+ MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e
+ MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e
+ MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e
+ MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e
+ MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e
+ MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e
+ MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e
+ MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e
+ MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e
+ MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e
+ MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e
+ MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e
+ MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e
+ MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
+ >;
+ };
+
+ pinctrl_pdm: pdmgrp {
+ fsl,pins = <
+ MX91_PAD_PDM_CLK__PDM_CLK 0x31e
+ MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e
+ MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e
+ >;
+ };
+
+ pinctrl_pdm_sleep: pdmsleepgrp {
+ fsl,pins = <
+ MX91_PAD_PDM_CLK__GPIO1_IO8 0x31e
+ MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x31e
+ MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
+ MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
+ MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e
+ MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e
+ >;
+ };
+
+ pinctrl_sai1_sleep: sai1sleepgrp {
+ fsl,pins = <
+ MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e
+ MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e
+ MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e
+ MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
+ MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
+ MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e
+ MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e
+ MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e
+ >;
+ };
+
+ pinctrl_sai3_sleep: sai3sleepgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e
+ MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e
+ MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e
+ MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e
+ MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e
+ MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e
+ >;
+ };
+
+ pinctrl_spdif_sleep: spdifsleepgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO22__GPIO2_IO22 0x31e
+ MX91_PAD_GPIO_IO23__GPIO2_IO23 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
+ MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
+ MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
+ MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2sleepgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
+ MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
+ MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
+ MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
+ MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
+ MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
+ MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
+ MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
+ MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
+ MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
+ MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
+ MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
+ MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
+ MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
+ MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
+ MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
+ MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
+ MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
+ MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
+ MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
+ MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
+ MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3sleepgrp {
+ fsl,pins = <
+ MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
+ MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
+ MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
+ MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
+ MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
+ MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
+ >;
+ };
+
+ pinctrl_usdhc3_wlan: usdhc3wlangrp {
+ fsl,pins = <
+ MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx91-pinfunc.h b/dts/upstream/src/arm64/freescale/imx91-pinfunc.h
new file mode 100644
index 0000000..b0066df
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx91-pinfunc.h
@@ -0,0 +1,770 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DTS_IMX91_PINFUNC_H
+#define __DTS_IMX91_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01b0 0x03d8 0x00 0x00
+#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01b0 0x0000 0x01 0x00
+#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01b0 0x0000 0x03 0x00
+#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01b0 0x0000 0x04 0x00
+#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01b0 0x0000 0x05 0x00
+#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01b0 0x0488 0x06 0x00
+
+#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01b4 0x03dc 0x00 0x00
+#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01b4 0x0000 0x04 0x00
+#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01b4 0x0000 0x05 0x00
+#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01b4 0x0000 0x06 0x00
+
+#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01b8 0x03d4 0x00 0x00
+#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01b8 0x0000 0x04 0x00
+#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01b8 0x0000 0x05 0x00
+#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01b8 0x0484 0x06 0x00
+
+#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x01bc 0x0000 0x00 0x00
+#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x01bc 0x0000 0x01 0x00
+#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x01bc 0x0364 0x03 0x00
+#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000c 0x01bc 0x0000 0x04 0x00
+#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000c 0x01bc 0x0000 0x05 0x00
+#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x01bc 0x048c 0x06 0x00
+
+#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01c0 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01c0 0x03f4 0x01 0x00
+#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01c0 0x04bc 0x02 0x00
+#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01c0 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01c0 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01c0 0x048c 0x05 0x01
+#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01c0 0x0404 0x06 0x00
+#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01c0 0x036c 0x07 0x00
+
+#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01c4 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01c4 0x03f0 0x01 0x00
+#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01c4 0x0490 0x02 0x00
+#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01c4 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01c4 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01c4 0x0488 0x05 0x01
+#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01c4 0x0400 0x06 0x00
+#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01c4 0x0370 0x07 0x00
+
+#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01c8 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01c8 0x03fc 0x01 0x00
+#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01c8 0x04c0 0x02 0x00
+#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01c8 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01c8 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01c8 0x0484 0x05 0x01
+#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01c8 0x040c 0x06 0x00
+#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01c8 0x0374 0x07 0x00
+
+#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x01cc 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001c 0x01cc 0x03f8 0x01 0x00
+#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001c 0x01cc 0x04b8 0x02 0x00
+#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001c 0x01cc 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x01cc 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x01cc 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x01cc 0x0408 0x06 0x00
+#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x01cc 0x0378 0x07 0x00
+
+#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01d0 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01d0 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01d0 0x0000 0x02 0x00
+#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01d0 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01d0 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01d0 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01d0 0x040c 0x06 0x01
+#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01d0 0x037c 0x07 0x00
+
+#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01d4 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01d4 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01d4 0x04c4 0x02 0x00
+#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01d4 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01d4 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01d4 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01d4 0x0408 0x06 0x01
+#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01d4 0x0380 0x07 0x00
+
+#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01d8 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01d8 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01d8 0x04c8 0x02 0x00
+#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01d8 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01d8 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01d8 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01d8 0x0414 0x06 0x00
+#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01d8 0x0384 0x07 0x00
+
+#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x01dc 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x01dc 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002c 0x01dc 0x0494 0x02 0x00
+#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002c 0x01dc 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x01dc 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x01dc 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x01dc 0x0410 0x06 0x00
+#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x01dc 0x0388 0x07 0x00
+
+#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01e0 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01e0 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01e0 0x0498 0x02 0x00
+#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01e0 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01e0 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01e0 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01e0 0x0414 0x06 0x01
+#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01e0 0x038c 0x07 0x00
+
+#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01e4 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01e4 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01e4 0x049c 0x02 0x00
+#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01e4 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01e4 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01e4 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01e4 0x0410 0x06 0x01
+#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01e4 0x0390 0x07 0x00
+
+#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01e8 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01e8 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01e8 0x04a0 0x02 0x00
+#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01e8 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01e8 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01e8 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01e8 0x041c 0x06 0x00
+#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01e8 0x0394 0x07 0x00
+
+#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x01ec 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x01ec 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003c 0x01ec 0x04a4 0x02 0x00
+#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003c 0x01ec 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x01ec 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x01ec 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x01ec 0x0418 0x06 0x00
+#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x01ec 0x0398 0x07 0x00
+
+#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01f0 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01f0 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01f0 0x04cc 0x02 0x00
+#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01f0 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01f0 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01f0 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01f0 0x041c 0x06 0x01
+#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01f0 0x04dc 0x07 0x00
+
+#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01f4 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01f4 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01f4 0x04d0 0x02 0x00
+#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01f4 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01f4 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01f4 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01f4 0x0418 0x06 0x01
+#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01f4 0x039c 0x07 0x00
+
+#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01f8 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01f8 0x0474 0x01 0x00
+#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01f8 0x04a8 0x02 0x00
+#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01f8 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01f8 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01f8 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01f8 0x0480 0x06 0x00
+#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01f8 0x03a0 0x07 0x00
+
+#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x01fc 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004c 0x01fc 0x0470 0x01 0x00
+#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004c 0x01fc 0x04ac 0x02 0x00
+#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004c 0x01fc 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x01fc 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x01fc 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x01fc 0x047c 0x06 0x00
+#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x01fc 0x03a4 0x07 0x00
+
+#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04cc 0x02 0x01
+#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046c 0x04 0x00
+#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00
+#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03a8 0x07 0x00
+
+#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04b0 0x02 0x00
+#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00
+#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03ac 0x07 0x00
+
+#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04d8 0x01 0x00
+#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04b4 0x02 0x00
+#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00
+#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03b0 0x07 0x00
+
+#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x020c 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005c 0x020c 0x04dc 0x01 0x01
+#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005c 0x020c 0x04d0 0x02 0x01
+#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005c 0x020c 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005c 0x020c 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005c 0x020c 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005c 0x020c 0x0000 0x06 0x00
+#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005c 0x020c 0x0000 0x07 0x00
+
+#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04c4 0x02 0x01
+#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00
+#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03b4 0x07 0x00
+
+#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00
+#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00
+#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00
+#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04d8 0x07 0x01
+
+#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04e8 0x01 0x00
+#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04e4 0x02 0x00
+#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01
+#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03b8 0x07 0x00
+
+#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x021c 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006c 0x021c 0x04ec 0x01 0x00
+#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006c 0x021c 0x0000 0x02 0x00
+#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006c 0x021c 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006c 0x021c 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006c 0x021c 0x0400 0x06 0x01
+#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006c 0x021c 0x03bc 0x07 0x00
+
+#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04f0 0x01 0x00
+#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00
+#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00
+#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03c0 0x07 0x00
+
+#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04f4 0x01 0x00
+#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00
+#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03d4 0x05 0x01
+#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00
+#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03c4 0x07 0x00
+
+#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04f8 0x01 0x00
+#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04c8 0x02 0x01
+#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03d8 0x05 0x01
+#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00
+#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04e0 0x07 0x00
+
+#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x022c 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007c 0x022c 0x04fc 0x01 0x00
+#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007c 0x022c 0x0364 0x02 0x01
+#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007c 0x022c 0x0000 0x03 0x00
+#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007c 0x022c 0x0000 0x04 0x00
+#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007c 0x022c 0x03dc 0x05 0x01
+#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007c 0x022c 0x0000 0x06 0x00
+#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007c 0x022c 0x03c8 0x07 0x00
+
+#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03f4 0x01 0x01
+#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00
+#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00
+
+#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00
+#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03f0 0x01 0x01
+#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00
+#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00
+
+#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00
+#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00
+#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00
+
+#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008c 0x023c 0x0000 0x05 0x00
+#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008c 0x023c 0x0000 0x00 0x00
+#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008c 0x023c 0x03c8 0x04 0x01
+
+#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00
+#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00
+#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00
+
+#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00
+#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00
+#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00
+
+#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00
+#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03cc 0x02 0x00
+#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00
+#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03e0 0x06 0x00
+
+#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009c 0x024c 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009c 0x024c 0x0000 0x01 0x00
+#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009c 0x024c 0x03d0 0x02 0x00
+#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009c 0x024c 0x0000 0x03 0x00
+#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009c 0x024c 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009c 0x024c 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009c 0x024c 0x03e4 0x06 0x00
+
+#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00a0 0x0250 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00
+#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00
+#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_TD3__GPIO4_IO3 0x00a0 0x0250 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00
+
+#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00a4 0x0254 0x0000 0x01 0x00
+#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00a4 0x0254 0x0364 0x02 0x02
+#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00a4 0x0254 0x0000 0x03 0x00
+#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00a4 0x0254 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00a4 0x0254 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00a4 0x0254 0x03ec 0x06 0x00
+
+#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00a8 0x0258 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00a8 0x0258 0x0000 0x01 0x00
+#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00a8 0x0258 0x0000 0x02 0x00
+#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00a8 0x0258 0x0000 0x03 0x00
+#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00a8 0x0258 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00a8 0x0258 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00a8 0x0258 0x0000 0x06 0x00
+
+#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00ac 0x025c 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00ac 0x025c 0x0474 0x01 0x01
+#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00ac 0x025c 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00ac 0x025c 0x0000 0x05 0x00
+
+#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00b0 0x0260 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00b0 0x0260 0x0000 0x01 0x00
+#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00b0 0x0260 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00b0 0x0260 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00b0 0x0260 0x043c 0x02 0x00
+
+#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00b4 0x0264 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00b4 0x0264 0x0000 0x01 0x00
+#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00b4 0x0264 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00b4 0x0264 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00b4 0x0264 0x0440 0x02 0x00
+
+#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00b8 0x0268 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00b8 0x0268 0x0000 0x01 0x00
+#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00b8 0x0268 0x0000 0x03 0x00
+#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00b8 0x0268 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00b8 0x0268 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00b8 0x0268 0x0434 0x02 0x00
+
+#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00bc 0x026c 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00bc 0x026c 0x0000 0x01 0x00
+#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00bc 0x026c 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00bc 0x026c 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00bc 0x026c 0x0444 0x02 0x00
+
+#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00c0 0x0270 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00c0 0x0270 0x0470 0x01 0x01
+#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00c0 0x0270 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00c0 0x0270 0x0000 0x05 0x00
+
+#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00c4 0x0274 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00c4 0x0274 0x046c 0x01 0x01
+#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00c4 0x0274 0x0448 0x03 0x00
+#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00c4 0x0274 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00c4 0x0274 0x0000 0x05 0x00
+
+#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00c8 0x0278 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00c8 0x0278 0x044c 0x03 0x00
+#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00c8 0x0278 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00c8 0x0278 0x0000 0x05 0x00
+
+#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00cc 0x027c 0x0000 0x00 0x00
+#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00cc 0x027c 0x0000 0x02 0x00
+#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00cc 0x027c 0x0450 0x03 0x00
+#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00cc 0x027c 0x0000 0x04 0x00
+#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00cc 0x027c 0x0000 0x05 0x00
+
+#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00d0 0x0280 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00d0 0x0280 0x0000 0x01 0x00
+#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00d0 0x0280 0x0000 0x02 0x00
+#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00d0 0x0280 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00d0 0x0280 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00d0 0x0280 0x04bc 0x06 0x01
+
+#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00d4 0x0284 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00d4 0x0284 0x0000 0x01 0x00
+#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00d4 0x0284 0x0000 0x02 0x00
+#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00d4 0x0284 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00d4 0x0284 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00d4 0x0284 0x0490 0x06 0x01
+
+#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00d8 0x0288 0x0000 0x02 0x00
+#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00d8 0x0288 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00d8 0x0288 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00d8 0x0288 0x04c0 0x06 0x01
+#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00d8 0x0288 0x0000 0x00 0x00
+
+#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00dc 0x028c 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00dc 0x028c 0x0000 0x01 0x00
+#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00dc 0x028c 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00dc 0x028c 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00dc 0x028c 0x04b8 0x06 0x01
+
+#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00e0 0x0290 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00e0 0x0290 0x0000 0x01 0x00
+#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00e0 0x0290 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00e0 0x0290 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00e0 0x0290 0x0494 0x06 0x01
+
+#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00e4 0x0294 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00e4 0x0294 0x0480 0x01 0x01
+#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00e4 0x0294 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00e4 0x0294 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00e4 0x0294 0x0498 0x06 0x01
+
+#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00e8 0x0298 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00e8 0x0298 0x0000 0x01 0x00
+#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00e8 0x0298 0x0000 0x02 0x00
+#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00e8 0x0298 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00e8 0x0298 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00e8 0x0298 0x049c 0x06 0x01
+
+#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00ec 0x029c 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00ec 0x029c 0x0000 0x01 0x00
+#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00ec 0x029c 0x0000 0x02 0x00
+#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00ec 0x029c 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00ec 0x029c 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00ec 0x029c 0x04a0 0x06 0x01
+
+#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00f0 0x02a0 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00f0 0x02a0 0x0000 0x01 0x00
+#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00f0 0x02a0 0x0000 0x02 0x00
+#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00f0 0x02a0 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00f0 0x02a0 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00f0 0x02a0 0x04a4 0x06 0x01
+
+#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00f4 0x02a4 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00f4 0x02a4 0x0000 0x01 0x00
+#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00f4 0x02a4 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00f4 0x02a4 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00f4 0x02a4 0x04a8 0x06 0x01
+
+#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00f8 0x02a8 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00f8 0x02a8 0x047c 0x01 0x01
+#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00f8 0x02a8 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00f8 0x02a8 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00f8 0x02a8 0x04ac 0x06 0x01
+
+#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00fc 0x02ac 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00fc 0x02ac 0x04e4 0x01 0x01
+#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00fc 0x02ac 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00fc 0x02ac 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00fc 0x02ac 0x04b0 0x06 0x01
+
+#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02b0 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02b0 0x0478 0x01 0x01
+#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02b0 0x0000 0x02 0x00
+#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02b0 0x0000 0x03 0x00
+#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02b0 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02b0 0x0000 0x05 0x00
+#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02b0 0x04b4 0x06 0x01
+
+#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02b4 0x0000 0x00 0x00
+#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02b4 0x0000 0x01 0x00
+#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02b4 0x04e4 0x02 0x02
+#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02b4 0x0000 0x03 0x00
+#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02b4 0x0000 0x04 0x00
+#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02b4 0x0000 0x05 0x00
+
+#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02b8 0x038c 0x04 0x01
+#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02b8 0x0000 0x05 0x00
+#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02b8 0x0000 0x00 0x00
+#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02b8 0x043c 0x03 0x01
+
+#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010c 0x02bc 0x0000 0x00 0x00
+#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010c 0x02bc 0x0390 0x04 0x01
+#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010c 0x02bc 0x0000 0x05 0x00
+#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010c 0x02bc 0x0440 0x03 0x01
+
+#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02c0 0x0000 0x00 0x00
+#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02c0 0x0394 0x04 0x01
+#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02c0 0x0000 0x05 0x00
+#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02c0 0x0434 0x03 0x01
+
+#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02c4 0x0000 0x00 0x00
+#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02c4 0x0398 0x04 0x01
+#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02c4 0x0000 0x05 0x00
+#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02c4 0x0000 0x06 0x00
+#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02c4 0x0444 0x03 0x01
+
+#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02c8 0x0000 0x00 0x00
+#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02c8 0x0000 0x04 0x00
+#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02c8 0x0000 0x05 0x00
+#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02c8 0x0000 0x06 0x00
+#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02c8 0x0438 0x03 0x00
+
+#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011c 0x02cc 0x0000 0x00 0x00
+#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011c 0x02cc 0x0000 0x01 0x00
+#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011c 0x02cc 0x039c 0x04 0x01
+#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011c 0x02cc 0x0000 0x05 0x00
+#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011c 0x02cc 0x0424 0x03 0x00
+
+#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02d0 0x0000 0x00 0x00
+#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02d0 0x0000 0x01 0x00
+#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02d0 0x03a0 0x04 0x01
+#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02d0 0x0000 0x05 0x00
+#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02d0 0x0420 0x03 0x00
+
+#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02d4 0x0000 0x00 0x00
+#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02d4 0x0000 0x01 0x00
+#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02d4 0x0000 0x02 0x00
+#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02d4 0x03a4 0x04 0x01
+#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02d4 0x0000 0x05 0x00
+#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02d4 0x042c 0x03 0x00
+
+#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02d8 0x0000 0x00 0x00
+#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02d8 0x0000 0x01 0x00
+#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02d8 0x0000 0x02 0x00
+#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02d8 0x03a8 0x04 0x01
+#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02d8 0x0000 0x05 0x00
+#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02d8 0x0428 0x03 0x00
+
+#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012c 0x02dc 0x0000 0x00 0x00
+#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012c 0x02dc 0x0000 0x01 0x00
+#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012c 0x02dc 0x0000 0x02 0x00
+#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012c 0x02dc 0x03ac 0x04 0x01
+#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012c 0x02dc 0x0000 0x05 0x00
+#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012c 0x02dc 0x0430 0x03 0x00
+
+#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02e0 0x0000 0x00 0x00
+#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02e0 0x0000 0x01 0x00
+#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02e0 0x03b0 0x04 0x01
+#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02e0 0x0000 0x05 0x00
+
+#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02e4 0x0000 0x00 0x00
+#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02e4 0x0000 0x01 0x00
+#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02e4 0x0450 0x02 0x01
+#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02e4 0x0000 0x04 0x00
+#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02e4 0x0000 0x05 0x00
+#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02e4 0x0368 0x06 0x00
+
+#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02e8 0x04e8 0x00 0x01
+#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02e8 0x0000 0x01 0x00
+#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02e8 0x0454 0x02 0x00
+#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02e8 0x03b4 0x04 0x01
+#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02e8 0x0000 0x05 0x00
+
+#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013c 0x02ec 0x04ec 0x00 0x01
+#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013c 0x02ec 0x0000 0x01 0x00
+#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013c 0x02ec 0x0000 0x02 0x00
+#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013c 0x02ec 0x0000 0x04 0x00
+#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013c 0x02ec 0x0000 0x05 0x00
+
+#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02f0 0x04f0 0x00 0x01
+#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02f0 0x0000 0x01 0x00
+#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02f0 0x0460 0x02 0x00
+#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02f0 0x03b8 0x04 0x01
+#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02f0 0x0000 0x05 0x00
+
+#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02f4 0x04f4 0x00 0x01
+#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02f4 0x0000 0x01 0x00
+#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02f4 0x0000 0x02 0x00
+#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02f4 0x03bc 0x04 0x01
+#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02f4 0x0000 0x05 0x00
+
+#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02f8 0x04f8 0x00 0x01
+#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02f8 0x03fc 0x02 0x01
+#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02f8 0x0000 0x01 0x00
+#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02f8 0x03c0 0x04 0x01
+#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02f8 0x0000 0x05 0x00
+
+#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014c 0x02fc 0x04fc 0x00 0x01
+#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014c 0x02fc 0x0000 0x01 0x00
+#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014c 0x02fc 0x03f8 0x02 0x01
+#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014c 0x02fc 0x03c4 0x04 0x01
+#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014c 0x02fc 0x0000 0x05 0x00
+
+#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00
+#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00
+#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03cc 0x02 0x01
+#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036c 0x04 0x01
+#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00
+#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03e0 0x03 0x01
+
+#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00
+#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00
+#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00
+#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03d0 0x02 0x01
+#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01
+#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00
+#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00
+#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03e4 0x03 0x01
+
+#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00
+#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00
+#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00
+#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00
+#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01
+#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00
+#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00
+
+#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015c 0x030c 0x0000 0x00 0x00
+#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015c 0x030c 0x0000 0x01 0x00
+#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015c 0x030c 0x0000 0x02 0x00
+#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015c 0x030c 0x0378 0x04 0x01
+#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015c 0x030c 0x0000 0x05 0x00
+#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015c 0x030c 0x045c 0x03 0x00
+#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015c 0x030c 0x0000 0x06 0x00
+
+#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00
+#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00
+#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03
+#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037c 0x04 0x01
+#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00
+#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00
+#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00
+
+#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00
+#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00
+#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00
+#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01
+#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00
+#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00
+#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00
+
+#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00
+#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01
+#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00
+#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01
+#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00
+#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00
+#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00
+
+#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016c 0x031c 0x0000 0x00 0x00
+#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016c 0x031c 0x044c 0x01 0x01
+#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016c 0x031c 0x0388 0x04 0x01
+#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016c 0x031c 0x0000 0x05 0x00
+#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016c 0x031c 0x0000 0x06 0x00
+
+#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03e0 0x00 0x02
+#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00
+#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00
+#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00
+#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00
+
+#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03e4 0x00 0x02
+#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00
+#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00
+#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00
+#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00
+
+#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03e8 0x00 0x01
+#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00
+#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00
+#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00
+#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00
+#define MX91_PAD_I2C2_SCL__GPIO1_IO3 0x0178 0x0328 0x0000 0x05 0x00
+#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00
+
+#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01
+#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017c 0x032c 0x0000 0x02 0x00
+#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017c 0x032c 0x0000 0x03 0x00
+#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017c 0x032c 0x0000 0x04 0x00
+#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017c 0x032c 0x0000 0x05 0x00
+
+#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01
+#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00
+#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02
+#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00
+#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00
+
+#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045c 0x00 0x01
+#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00
+#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02
+#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00
+#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00
+
+#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01
+#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01
+#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02
+#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00
+#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04d4 0x04 0x00
+#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00
+
+#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018c 0x033c 0x0468 0x00 0x01
+#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018c 0x033c 0x0000 0x01 0x00
+#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018c 0x033c 0x043c 0x02 0x02
+#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018c 0x033c 0x0000 0x03 0x00
+#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018c 0x033c 0x0000 0x05 0x00
+#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018c 0x033c 0x04e0 0x07 0x02
+
+#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00
+#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00
+#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00
+#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00
+#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00
+
+#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04c4 0x00 0x02
+#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00
+#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01
+#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00
+#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00
+#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00
+#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01
+
+#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04c8 0x00 0x02
+#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01
+#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00
+#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00
+#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00
+#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01
+
+#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019c 0x034c 0x0000 0x00 0x00
+#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019c 0x034c 0x0000 0x01 0x00
+#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019c 0x034c 0x0420 0x02 0x01
+#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019c 0x034c 0x0000 0x03 0x00
+#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019c 0x034c 0x0000 0x04 0x00
+#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019c 0x034c 0x0000 0x05 0x00
+
+#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01a0 0x0350 0x0000 0x00 0x00
+#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01a0 0x0350 0x0460 0x01 0x01
+#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01a0 0x0350 0x042c 0x02 0x01
+#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01a0 0x0350 0x0000 0x03 0x00
+#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01a0 0x0350 0x0360 0x04 0x02
+#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01a0 0x0350 0x0000 0x05 0x00
+
+#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01a4 0x0354 0x0000 0x00 0x00
+#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01a4 0x0354 0x0000 0x01 0x00
+#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01a4 0x0354 0x0428 0x02 0x01
+#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01a4 0x0354 0x0000 0x03 0x00
+#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01a4 0x0354 0x0000 0x04 0x00
+#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01a4 0x0354 0x0000 0x05 0x00
+#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01a4 0x0354 0x04d4 0x06 0x01
+
+#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01a8 0x0358 0x0000 0x00 0x00
+#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01a8 0x0358 0x04d4 0x01 0x02
+#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01a8 0x0358 0x0430 0x02 0x01
+#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01a8 0x0358 0x0000 0x03 0x00
+#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01a8 0x0358 0x0000 0x04 0x00
+#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01a8 0x0358 0x0000 0x05 0x00
+
+#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01ac 0x035c 0x0000 0x00 0x00
+#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01ac 0x035c 0x0000 0x05 0x00
+#endif /* __DTS_IMX91_PINFUNC_H */
diff --git a/dts/upstream/src/arm64/freescale/imx91.dtsi b/dts/upstream/src/arm64/freescale/imx91.dtsi
new file mode 100644
index 0000000..be923e5
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx91.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx91-pinfunc.h"
+#include "imx93.dtsi"
+
+/delete-node/ &A55_1;
+/delete-node/ &cm33;
+/delete-node/ &mlmix;
+/delete-node/ &mu1;
+/delete-node/ &mu2;
+
+&clk {
+ compatible = "fsl,imx91-ccm";
+};
+
+&eqos {
+ clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
+ <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
+ <&clk IMX91_CLK_ENET_TIMER>,
+ <&clk IMX91_CLK_ENET1_QOS_TSN>,
+ <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
+ assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
+ <&clk IMX91_CLK_ENET1_QOS_TSN>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
+};
+
+&fec {
+ clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
+ <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
+ <&clk IMX91_CLK_ENET_TIMER>,
+ <&clk IMX91_CLK_ENET2_REGULAR>,
+ <&clk IMX93_CLK_DUMMY>;
+ assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
+ <&clk IMX91_CLK_ENET2_REGULAR>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
+ assigned-clock-rates = <100000000>, <250000000>;
+};
+
+&i3c1 {
+ clocks = <&clk IMX93_CLK_BUS_AON>,
+ <&clk IMX93_CLK_I3C1_GATE>,
+ <&clk IMX93_CLK_DUMMY>;
+};
+
+&i3c2 {
+ clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+ <&clk IMX93_CLK_I3C2_GATE>,
+ <&clk IMX93_CLK_DUMMY>;
+};
+
+&iomuxc {
+ compatible = "fsl,imx91-iomuxc";
+};
+
+&tmu {
+ status = "disabled";
+};
+
+&{/soc@0/ddr-pmu@4e300dc0} {
+ compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu";
+};
+
+&{/thermal-zones/cpu-thermal/cooling-maps/map0} {
+ cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+};
diff --git a/env/Kconfig b/env/Kconfig
index 031cf58..aaf0b1f 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -21,6 +21,19 @@
environment is assumed to come from the ad-hoc
CFG_EXTRA_ENV_SETTINGS #define
+config ENV_CALLBACK_LIST_STATIC
+ string "Static callbacks list"
+ default ""
+ help
+ The environment callbacks are associated with variables in a
+ static list. Define this list in the following format:
+
+ entry = variable_name[:callback_name]
+ list = entry[,list]
+
+ If the callback name is not specified, then the callback is deleted.
+ Spaces are also allowed anywhere in the list.
+
config SAVEENV
def_bool y if CMD_SAVEENV
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 26277b9..789adf2 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -400,6 +400,12 @@
*/
struct bloblist_hdr *bloblist;
#endif
+#if CONFIG_IS_ENABLED(HANDOFF)
+ /**
+ * @spl_handoff: SPL hand-off information
+ */
+ struct spl_handoff *spl_handoff;
+#endif
#if defined(CONFIG_TRANSLATION_OFFSET)
/**
* @translation_offset: optional translation offset
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 70303ac..8c619c1 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -30,8 +30,6 @@
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
#ifdef CONFIG_ARM
unsigned long bi_arm_freq; /* arm frequency */
unsigned long bi_dsp_freq; /* dsp core frequency */
diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h
index 1f61b2b..4d95f3f 100644
--- a/include/configs/capricorn-common.h
+++ b/include/configs/capricorn-common.h
@@ -95,7 +95,9 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
-/* DDR3 board total DDR is 1 GB */
+/* Set default values to the smallest DDR we have in capricorn modules
+ * Use it in case the system controller would return an error
+ */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
diff --git a/include/configs/deneb.h b/include/configs/deneb.h
deleted file mode 100644
index f155bb8..0000000
--- a/include/configs/deneb.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2019 Siemens AG
- *
- */
-
-#ifndef __DENEB_H
-#define __DENEB_H
-
-#include "capricorn-common.h"
-
-/* DDR3 board total DDR is 2 GB */
-#undef PHYS_SDRAM_1_SIZE
-#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
-
-#endif /* __DENEB_H */
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index d323f84..57ecb5e 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h
@@ -34,7 +34,7 @@
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CFG_EXTRA_ENV_SETTINGS \
- "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
+ "altbootcmd=run bootcmd\0" \
"bootlimit=3\0" \
"devtype=mmc\0" \
"devpart=1\0" \
diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h
index f953847..de5bdd3 100644
--- a/include/configs/imx8mp_data_modul_edm_sbc.h
+++ b/include/configs/imx8mp_data_modul_edm_sbc.h
@@ -24,7 +24,7 @@
#define FEC_QUIRK_ENET_MAC
#define CFG_EXTRA_ENV_SETTINGS \
- "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
+ "altbootcmd=run bootcmd\0" \
"bootlimit=3\0" \
"devtype=mmc\0" \
"devpart=1\0" \
diff --git a/include/configs/imx91_evk.h b/include/configs/imx91_evk.h
new file mode 100644
index 0000000..9c5014f
--- /dev/null
+++ b/include/configs/imx91_evk.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __IMX91_EVK_H
+#define __IMX91_EVK_H
+
+#define CFG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+
+#define WDOG_BASE_ADDR WDG3_BASE_ADDR
+
+#endif
diff --git a/include/configs/khadas-vim3_android.h b/include/configs/khadas-vim3_android.h
index fc89efb..551ab51 100644
--- a/include/configs/khadas-vim3_android.h
+++ b/include/configs/khadas-vim3_android.h
@@ -24,7 +24,7 @@
"name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \
"name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \
"name=super,size=3072M,uuid=${uuid_gpt_super};" \
- "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \
+ "name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \
"name=rootfs,size=-,uuid=" ROOT_UUID
#else
#define PARTS_DEFAULT \
@@ -37,14 +37,31 @@
"name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \
"name=cache,size=256M,uuid=${uuid_gpt_cache};" \
"name=super,size=1792M,uuid=${uuid_gpt_super};" \
- "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \
+ "name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \
"name=rootfs,size=-,uuid=" ROOT_UUID
#endif
-#define EXTRA_ANDROID_ENV_SETTINGS \
- "board=vim3\0" \
- "board_name=vim3\0" \
+#define CFG_EXTRA_ENV_SETTINGS \
+ "board=vim3\0" \
+ "board_name=vim3\0" \
+ "bootmeths=android\0" \
+ "bootcmd=bootflow scan\0" \
+ "adtb_idx=3\0" \
+ "partitions=" PARTS_DEFAULT "\0" \
+ "mmcdev=2\0" \
+ "fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0" \
+ "fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0" \
+ "stdin=" STDIN_CFG "\0" \
+ "stdout=" STDOUT_CFG "\0" \
+ "stderr=" STDOUT_CFG "\0" \
+ "dtboaddr=0x08200000\0" \
+ "loadaddr=0x01080000\0" \
+ "fdt_addr_r=0x01000000\0" \
+ "scriptaddr=0x08000000\0" \
+ "kernel_addr_r=0x01080000\0" \
+ "pxefile_addr_r=0x01080000\0" \
+ "ramdisk_addr_r=0x13000000\0" \
-#include <configs/meson64_android.h>
+#include <configs/meson64.h>
#endif /* __CONFIG_H */
diff --git a/include/configs/khadas-vim3l_android.h b/include/configs/khadas-vim3l_android.h
index 5b2aed1..1869249 100644
--- a/include/configs/khadas-vim3l_android.h
+++ b/include/configs/khadas-vim3l_android.h
@@ -24,7 +24,7 @@
"name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \
"name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \
"name=super,size=3072M,uuid=${uuid_gpt_super};" \
- "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \
+ "name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \
"name=rootfs,size=-,uuid=" ROOT_UUID
#else
#define PARTS_DEFAULT \
@@ -37,14 +37,31 @@
"name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \
"name=cache,size=256M,uuid=${uuid_gpt_cache};" \
"name=super,size=1792M,uuid=${uuid_gpt_super};" \
- "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \
+ "name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \
"name=rootfs,size=-,uuid=" ROOT_UUID
#endif
-#define EXTRA_ANDROID_ENV_SETTINGS \
- "board=vim3l\0" \
- "board_name=vim3l\0" \
+#define CFG_EXTRA_ENV_SETTINGS \
+ "board=vim3l\0" \
+ "board_name=vim3l\0" \
+ "bootmeths=android\0" \
+ "bootcmd=bootflow scan\0" \
+ "adtb_idx=2\0" \
+ "partitions=" PARTS_DEFAULT "\0" \
+ "mmcdev=2\0" \
+ "fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0" \
+ "fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0" \
+ "stdin=" STDIN_CFG "\0" \
+ "stdout=" STDOUT_CFG "\0" \
+ "stderr=" STDOUT_CFG "\0" \
+ "dtboaddr=0x08200000\0" \
+ "loadaddr=0x01080000\0" \
+ "fdt_addr_r=0x01000000\0" \
+ "scriptaddr=0x08000000\0" \
+ "kernel_addr_r=0x01080000\0" \
+ "pxefile_addr_r=0x01080000\0" \
+ "ramdisk_addr_r=0x13000000\0" \
-#include <configs/meson64_android.h>
+#include <configs/meson64.h>
#endif /* __CONFIG_H */
diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h
index 77364bb..d6ef0a8 100644
--- a/include/configs/meson64_android.h
+++ b/include/configs/meson64_android.h
@@ -104,12 +104,6 @@
"elif test $board_name = sei610; then " \
"echo \" Reading DTB for sei610...\"; " \
"setenv dtb_index 1;" \
- "elif test $board_name = vim3l; then " \
- "echo \" Reading DTB for vim3l...\"; " \
- "setenv dtb_index 2;" \
- "elif test $board_name = vim3; then " \
- "echo \" Reading DTB for vim3...\"; " \
- "setenv dtb_index 3;" \
"else " \
"echo Error: Android boot is not supported for $board_name; " \
"exit; " \
diff --git a/include/configs/phycore_am62ax.h b/include/configs/phycore_am62ax.h
new file mode 100644
index 0000000..661ba8f
--- /dev/null
+++ b/include/configs/phycore_am62ax.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
+/*
+ * Configuration header file for PHYTEC phyCORE-AM62Ax
+ *
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ */
+
+#ifndef __PHYCORE_AM62AX_H
+#define __PHYCORE_AM62AX_H
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE 0x80000000
+
+#endif /* __PHYCORE_AM62AX_H */
diff --git a/include/configs/phycore_am62x.h b/include/configs/phycore_am62x.h
index 10b78b6..2bc6e7e 100644
--- a/include/configs/phycore_am62x.h
+++ b/include/configs/phycore_am62x.h
@@ -12,4 +12,8 @@
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000
+#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM62X_TIBOOT3"
+#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM62X_SPL"
+#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM62X_UBOOT"
+
#endif /* __PHYCORE_AM62X_H */
diff --git a/include/configs/phycore_am64x.h b/include/configs/phycore_am64x.h
index 9377db3..dd3dfa9 100644
--- a/include/configs/phycore_am64x.h
+++ b/include/configs/phycore_am64x.h
@@ -12,4 +12,8 @@
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000
+#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM64X_TIBOOT3"
+#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM64X_SPL"
+#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM64X_UBOOT"
+
#endif /* __PHYCORE_AM64X_H */
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index e74a3f1..20e2ab8 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -20,52 +20,6 @@
/* For RAW image gives a error info not panic */
#endif
-#define CFG_EXTRA_ENV_SETTINGS \
- "image=Image\0" \
- "console=ttymxc2,115200\0" \
- "fdt_addr=0x48000000\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "ip_dyn=yes\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=1\0" \
- "mmcroot=2\0" \
- "update_offset=0x42\0" \
- "update_filename=flash.bin\0" \
- "update_bootimg=" \
- "mmc dev ${mmcdev} ; " \
- "if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \
- "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
- "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \
- "fi\0" \
- "mmcautodetect=yes\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if run loadfdt; then " \
- "booti ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi;\0 " \
- "nfsroot=/nfs\0" \
- "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
- "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${loadaddr} ${image}; " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "booti ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi;\0" \
-
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 0ae4fc5..8de930e 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -19,8 +19,11 @@
*/
/* Initial RAM for temporary stack, global data */
#define CFG_SYS_INIT_RAM_SIZE 0x10000
+#define CFG_SYS_SRAM_BASE 0x80000000
+#define CFG_SYS_SRAM_SIZE 0x00080000
+
#define CFG_SYS_INIT_RAM_ADDR \
- (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE)
+ (CFG_SYS_SRAM_BASE + CFG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE)
/* SDRAM Configuration (for final code, data, stack, heap) */
#define CFG_SYS_SDRAM_BASE 0x88000000
diff --git a/include/dm/of_access.h b/include/dm/of_access.h
index de740d4..44143a5 100644
--- a/include/dm/of_access.h
+++ b/include/dm/of_access.h
@@ -454,6 +454,92 @@
}
/**
+ * of_root_parse_phandle - Resolve a phandle property to a device_node pointer
+ * from a root node
+ * @root: Pointer to root device tree node (default root node if NULL)
+ * @np: Pointer to device node holding phandle property
+ * @phandle_name: Name of property holding a phandle value
+ * @index: For properties holding a table of phandles, this is the index into
+ * the table
+ *
+ * Return:
+ * the device_node pointer with refcount incremented. Use
+ * of_node_put() on it when done.
+ */
+struct device_node *of_root_parse_phandle(struct device_node *root,
+ const struct device_node *np,
+ const char *phandle_name, int index);
+
+/**
+ * of_root_parse_phandle_with_args() - Find a node pointed by phandle in a list
+ * from a root node
+ *
+ * @root: pointer to root device tree node (default root node if NULL)
+ * @np: pointer to a device tree node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @cells_count: Cell count to use if @cells_name is NULL
+ * @index: index of a phandle to parse out
+ * @out_args: optional pointer to output arguments structure (will be filled)
+ * Return:
+ * 0 on success (with @out_args filled out if not NULL), -ENOENT if
+ * @list_name does not exist, -EINVAL if a phandle was not found,
+ * @cells_name could not be found, the arguments were truncated or there
+ * were too many arguments.
+ *
+ * This function is useful to parse lists of phandles and their arguments.
+ * Returns 0 on success and fills out_args, on error returns appropriate
+ * errno value.
+ *
+ * Caller is responsible to call of_node_put() on the returned out_args->np
+ * pointer.
+ *
+ * Example:
+ *
+ * .. code-block::
+ *
+ * phandle1: node1 {
+ * #list-cells = <2>;
+ * };
+ * phandle2: node2 {
+ * #list-cells = <1>;
+ * };
+ * node3 {
+ * list = <&phandle1 1 2 &phandle2 3>;
+ * };
+ *
+ * To get a device_node of the `node2' node you may call this:
+ * of_root_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args);
+ */
+int of_root_parse_phandle_with_args(struct device_node *root,
+ const struct device_node *np,
+ const char *list_name, const char *cells_name,
+ int cells_count, int index,
+ struct of_phandle_args *out_args);
+
+/**
+ * of_root_count_phandle_with_args() - Count the number of phandle in a list
+ * from a root node
+ *
+ * @root: pointer to root device tree node (default root node if NULL)
+ * @np: pointer to a device tree node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @cells_count: Cell count to use if @cells_name is NULL
+ * Return:
+ * number of phandle found, -ENOENT if @list_name does not exist,
+ * -EINVAL if a phandle was not found, @cells_name could not be found,
+ * the arguments were truncated or there were too many arguments.
+ *
+ * Returns number of phandle found on success, on error returns appropriate
+ * errno value.
+ */
+int of_root_count_phandle_with_args(struct device_node *root,
+ const struct device_node *np,
+ const char *list_name, const char *cells_name,
+ int cells_count);
+
+/**
* of_parse_phandle - Resolve a phandle property to a device_node pointer
* @np: Pointer to device node holding phandle property
* @phandle_name: Name of property holding a phandle value
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 0787758..890f0e6 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -848,6 +848,18 @@
const char ***listp);
/**
+ * ofnode_parse_phandle() - Resolve a phandle property to an ofnode
+ *
+ * @node: node to check
+ * @phandle_name: Name of property holding a phandle value
+ * @index: For properties holding a table of phandles, this is the index into
+ * the table
+ * Return: ofnode that the phandle points to or ofnode_null() on error.
+ */
+ofnode ofnode_parse_phandle(ofnode node, const char *phandle_name,
+ int index);
+
+/**
* ofnode_parse_phandle_with_args() - Find a node pointed by phandle in a list
*
* This function is useful to parse lists of phandles and their arguments.
@@ -910,6 +922,86 @@
const char *cells_name, int cell_count);
/**
+ * oftree_parse_phandle() - Resolve a phandle property to an ofnode
+ * from a root node
+ *
+ * @tree: device tree to use
+ * @node: node to check
+ * @phandle_name: Name of property holding a phandle value
+ * @index: For properties holding a table of phandles, this is the index into
+ * the table
+ * Return: ofnode that the phandle points to or ofnode_null() on error.
+ */
+ofnode oftree_parse_phandle(oftree tree, ofnode node, const char *phandle_name,
+ int index);
+
+/**
+ * oftree_parse_phandle_with_args() - Find a node pointed by phandle in a list
+ * from a root node
+ *
+ * This function is useful to parse lists of phandles and their arguments.
+ * Returns 0 on success and fills out_args, on error returns appropriate
+ * errno value.
+ *
+ * Caller is responsible to call of_node_put() on the returned out_args->np
+ * pointer.
+ *
+ * Example:
+ *
+ * .. code-block::
+ *
+ * phandle1: node1 {
+ * #list-cells = <2>;
+ * };
+ * phandle2: node2 {
+ * #list-cells = <1>;
+ * };
+ * node3 {
+ * list = <&phandle1 1 2 &phandle2 3>;
+ * };
+ *
+ * To get a device_node of the `node2' node you may call this:
+ * oftree_parse_phandle_with_args(node3, "list", "#list-cells", 0, 1, &args);
+ *
+ * @tree: device tree to use
+ * @node: device tree node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @cell_count: Cell count to use if @cells_name is NULL
+ * @index: index of a phandle to parse out
+ * @out_args: optional pointer to output arguments structure (will be filled)
+ * Return:
+ * 0 on success (with @out_args filled out if not NULL), -ENOENT if
+ * @list_name does not exist, -EINVAL if a phandle was not found,
+ * @cells_name could not be found, the arguments were truncated or there
+ * were too many arguments.
+ */
+int oftree_parse_phandle_with_args(oftree tree, ofnode node, const char *list_name,
+ const char *cells_name, int cell_count,
+ int index,
+ struct ofnode_phandle_args *out_args);
+
+/**
+ * oftree_count_phandle_with_args() - Count number of phandle in a list
+ * from a root node
+ *
+ * This function is useful to count phandles into a list.
+ * Returns number of phandle on success, on error returns appropriate
+ * errno value.
+ *
+ * @tree: device tree to use
+ * @node: device tree node containing a list
+ * @list_name: property name that contains a list
+ * @cells_name: property name that specifies phandles' arguments count
+ * @cell_count: Cell count to use if @cells_name is NULL
+ * Return:
+ * number of phandle on success, -ENOENT if @list_name does not exist,
+ * -EINVAL if a phandle was not found, @cells_name could not be found.
+ */
+int oftree_count_phandle_with_args(oftree tree, ofnode node, const char *list_name,
+ const char *cells_name, int cell_count);
+
+/**
* ofnode_path() - find a node by full path
*
* This uses the control FDT.
@@ -1629,6 +1721,21 @@
const char *ofnode_options_read_str(const char *prop_name);
/**
+ * ofnode_options_get_by_phandle() - Get a ofnode from phandle from the U-Boot options
+ *
+ * This reads a property from the /options/u-boot/ node of the devicetree.
+ *
+ * This only works with the control FDT.
+ *
+ * See dtschema/schemas/options/u-boot.yaml in dt-schema project for bindings
+ *
+ * @prop_name: property name to look up
+ * @nodep: pointer to ofnode where node is stored
+ * Return: 0, if found, or negative error if not
+ */
+int ofnode_options_get_by_phandle(const char *prop_name, ofnode *nodep);
+
+/**
* ofnode_read_bootscript_address() - Read bootscr-address or bootscr-ram-offset
*
* @bootscr_address: pointer to 64bit address where bootscr-address property value
diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
deleted file mode 100644
index 06f198e..0000000
--- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Jian Hu <jian.hu@amlogic.com>
- *
- * Copyright (c) 2023, SberDevices. All Rights Reserved.
- * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
- */
-
-#ifndef __A1_PERIPHERALS_CLKC_H
-#define __A1_PERIPHERALS_CLKC_H
-
-#define CLKID_XTAL_IN 0
-#define CLKID_FIXPLL_IN 1
-#define CLKID_USB_PHY_IN 2
-#define CLKID_USB_CTRL_IN 3
-#define CLKID_HIFIPLL_IN 4
-#define CLKID_SYSPLL_IN 5
-#define CLKID_DDS_IN 6
-#define CLKID_SYS 7
-#define CLKID_CLKTREE 8
-#define CLKID_RESET_CTRL 9
-#define CLKID_ANALOG_CTRL 10
-#define CLKID_PWR_CTRL 11
-#define CLKID_PAD_CTRL 12
-#define CLKID_SYS_CTRL 13
-#define CLKID_TEMP_SENSOR 14
-#define CLKID_AM2AXI_DIV 15
-#define CLKID_SPICC_B 16
-#define CLKID_SPICC_A 17
-#define CLKID_MSR 18
-#define CLKID_AUDIO 19
-#define CLKID_JTAG_CTRL 20
-#define CLKID_SARADC_EN 21
-#define CLKID_PWM_EF 22
-#define CLKID_PWM_CD 23
-#define CLKID_PWM_AB 24
-#define CLKID_CEC 25
-#define CLKID_I2C_S 26
-#define CLKID_IR_CTRL 27
-#define CLKID_I2C_M_D 28
-#define CLKID_I2C_M_C 29
-#define CLKID_I2C_M_B 30
-#define CLKID_I2C_M_A 31
-#define CLKID_ACODEC 32
-#define CLKID_OTP 33
-#define CLKID_SD_EMMC_A 34
-#define CLKID_USB_PHY 35
-#define CLKID_USB_CTRL 36
-#define CLKID_SYS_DSPB 37
-#define CLKID_SYS_DSPA 38
-#define CLKID_DMA 39
-#define CLKID_IRQ_CTRL 40
-#define CLKID_NIC 41
-#define CLKID_GIC 42
-#define CLKID_UART_C 43
-#define CLKID_UART_B 44
-#define CLKID_UART_A 45
-#define CLKID_SYS_PSRAM 46
-#define CLKID_RSA 47
-#define CLKID_CORESIGHT 48
-#define CLKID_AM2AXI_VAD 49
-#define CLKID_AUDIO_VAD 50
-#define CLKID_AXI_DMC 51
-#define CLKID_AXI_PSRAM 52
-#define CLKID_RAMB 53
-#define CLKID_RAMA 54
-#define CLKID_AXI_SPIFC 55
-#define CLKID_AXI_NIC 56
-#define CLKID_AXI_DMA 57
-#define CLKID_CPU_CTRL 58
-#define CLKID_ROM 59
-#define CLKID_PROC_I2C 60
-#define CLKID_DSPA_SEL 61
-#define CLKID_DSPB_SEL 62
-#define CLKID_DSPA_EN 63
-#define CLKID_DSPA_EN_NIC 64
-#define CLKID_DSPB_EN 65
-#define CLKID_DSPB_EN_NIC 66
-#define CLKID_RTC 67
-#define CLKID_CECA_32K 68
-#define CLKID_CECB_32K 69
-#define CLKID_24M 70
-#define CLKID_12M 71
-#define CLKID_FCLK_DIV2_DIVN 72
-#define CLKID_GEN 73
-#define CLKID_SARADC_SEL 74
-#define CLKID_SARADC 75
-#define CLKID_PWM_A 76
-#define CLKID_PWM_B 77
-#define CLKID_PWM_C 78
-#define CLKID_PWM_D 79
-#define CLKID_PWM_E 80
-#define CLKID_PWM_F 81
-#define CLKID_SPICC 82
-#define CLKID_TS 83
-#define CLKID_SPIFC 84
-#define CLKID_USB_BUS 85
-#define CLKID_SD_EMMC 86
-#define CLKID_PSRAM 87
-#define CLKID_DMC 88
-#define CLKID_SYS_A_SEL 89
-#define CLKID_SYS_A_DIV 90
-#define CLKID_SYS_A 91
-#define CLKID_SYS_B_SEL 92
-#define CLKID_SYS_B_DIV 93
-#define CLKID_SYS_B 94
-#define CLKID_DSPA_A_SEL 95
-#define CLKID_DSPA_A_DIV 96
-#define CLKID_DSPA_A 97
-#define CLKID_DSPA_B_SEL 98
-#define CLKID_DSPA_B_DIV 99
-#define CLKID_DSPA_B 100
-#define CLKID_DSPB_A_SEL 101
-#define CLKID_DSPB_A_DIV 102
-#define CLKID_DSPB_A 103
-#define CLKID_DSPB_B_SEL 104
-#define CLKID_DSPB_B_DIV 105
-#define CLKID_DSPB_B 106
-#define CLKID_RTC_32K_IN 107
-#define CLKID_RTC_32K_DIV 108
-#define CLKID_RTC_32K_XTAL 109
-#define CLKID_RTC_32K_SEL 110
-#define CLKID_CECB_32K_IN 111
-#define CLKID_CECB_32K_DIV 112
-#define CLKID_CECB_32K_SEL_PRE 113
-#define CLKID_CECB_32K_SEL 114
-#define CLKID_CECA_32K_IN 115
-#define CLKID_CECA_32K_DIV 116
-#define CLKID_CECA_32K_SEL_PRE 117
-#define CLKID_CECA_32K_SEL 118
-#define CLKID_DIV2_PRE 119
-#define CLKID_24M_DIV2 120
-#define CLKID_GEN_SEL 121
-#define CLKID_GEN_DIV 122
-#define CLKID_SARADC_DIV 123
-#define CLKID_PWM_A_SEL 124
-#define CLKID_PWM_A_DIV 125
-#define CLKID_PWM_B_SEL 126
-#define CLKID_PWM_B_DIV 127
-#define CLKID_PWM_C_SEL 128
-#define CLKID_PWM_C_DIV 129
-#define CLKID_PWM_D_SEL 130
-#define CLKID_PWM_D_DIV 131
-#define CLKID_PWM_E_SEL 132
-#define CLKID_PWM_E_DIV 133
-#define CLKID_PWM_F_SEL 134
-#define CLKID_PWM_F_DIV 135
-#define CLKID_SPICC_SEL 136
-#define CLKID_SPICC_DIV 137
-#define CLKID_SPICC_SEL2 138
-#define CLKID_TS_DIV 139
-#define CLKID_SPIFC_SEL 140
-#define CLKID_SPIFC_DIV 141
-#define CLKID_SPIFC_SEL2 142
-#define CLKID_USB_BUS_SEL 143
-#define CLKID_USB_BUS_DIV 144
-#define CLKID_SD_EMMC_SEL 145
-#define CLKID_SD_EMMC_DIV 146
-#define CLKID_SD_EMMC_SEL2 147
-#define CLKID_PSRAM_SEL 148
-#define CLKID_PSRAM_DIV 149
-#define CLKID_PSRAM_SEL2 150
-#define CLKID_DMC_SEL 151
-#define CLKID_DMC_DIV 152
-#define CLKID_DMC_SEL2 153
-
-#endif /* __A1_PERIPHERALS_CLKC_H */
diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
deleted file mode 100644
index 2b660c0..0000000
--- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Jian Hu <jian.hu@amlogic.com>
- *
- * Copyright (c) 2023, SberDevices. All Rights Reserved.
- * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
- */
-
-#ifndef __A1_PLL_CLKC_H
-#define __A1_PLL_CLKC_H
-
-#define CLKID_FIXED_PLL_DCO 0
-#define CLKID_FIXED_PLL 1
-#define CLKID_FCLK_DIV2_DIV 2
-#define CLKID_FCLK_DIV3_DIV 3
-#define CLKID_FCLK_DIV5_DIV 4
-#define CLKID_FCLK_DIV7_DIV 5
-#define CLKID_FCLK_DIV2 6
-#define CLKID_FCLK_DIV3 7
-#define CLKID_FCLK_DIV5 8
-#define CLKID_FCLK_DIV7 9
-#define CLKID_HIFI_PLL 10
-
-#endif /* __A1_PLL_CLKC_H */
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
deleted file mode 100644
index f561f5c..0000000
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (c) 2018 Baylibre SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
-#define __AXG_AUDIO_CLKC_BINDINGS_H
-
-#define AUD_CLKID_DDR_ARB 29
-#define AUD_CLKID_PDM 30
-#define AUD_CLKID_TDMIN_A 31
-#define AUD_CLKID_TDMIN_B 32
-#define AUD_CLKID_TDMIN_C 33
-#define AUD_CLKID_TDMIN_LB 34
-#define AUD_CLKID_TDMOUT_A 35
-#define AUD_CLKID_TDMOUT_B 36
-#define AUD_CLKID_TDMOUT_C 37
-#define AUD_CLKID_FRDDR_A 38
-#define AUD_CLKID_FRDDR_B 39
-#define AUD_CLKID_FRDDR_C 40
-#define AUD_CLKID_TODDR_A 41
-#define AUD_CLKID_TODDR_B 42
-#define AUD_CLKID_TODDR_C 43
-#define AUD_CLKID_LOOPBACK 44
-#define AUD_CLKID_SPDIFIN 45
-#define AUD_CLKID_SPDIFOUT 46
-#define AUD_CLKID_RESAMPLE 47
-#define AUD_CLKID_POWER_DETECT 48
-#define AUD_CLKID_MST_A_MCLK 49
-#define AUD_CLKID_MST_B_MCLK 50
-#define AUD_CLKID_MST_C_MCLK 51
-#define AUD_CLKID_MST_D_MCLK 52
-#define AUD_CLKID_MST_E_MCLK 53
-#define AUD_CLKID_MST_F_MCLK 54
-#define AUD_CLKID_SPDIFOUT_CLK 55
-#define AUD_CLKID_SPDIFIN_CLK 56
-#define AUD_CLKID_PDM_DCLK 57
-#define AUD_CLKID_PDM_SYSCLK 58
-#define AUD_CLKID_MST_A_SCLK 79
-#define AUD_CLKID_MST_B_SCLK 80
-#define AUD_CLKID_MST_C_SCLK 81
-#define AUD_CLKID_MST_D_SCLK 82
-#define AUD_CLKID_MST_E_SCLK 83
-#define AUD_CLKID_MST_F_SCLK 84
-#define AUD_CLKID_MST_A_LRCLK 86
-#define AUD_CLKID_MST_B_LRCLK 87
-#define AUD_CLKID_MST_C_LRCLK 88
-#define AUD_CLKID_MST_D_LRCLK 89
-#define AUD_CLKID_MST_E_LRCLK 90
-#define AUD_CLKID_MST_F_LRCLK 91
-#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
-#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
-#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
-#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
-#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
-#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
-#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
-#define AUD_CLKID_TDMIN_A_SCLK 123
-#define AUD_CLKID_TDMIN_B_SCLK 124
-#define AUD_CLKID_TDMIN_C_SCLK 125
-#define AUD_CLKID_TDMIN_LB_SCLK 126
-#define AUD_CLKID_TDMOUT_A_SCLK 127
-#define AUD_CLKID_TDMOUT_B_SCLK 128
-#define AUD_CLKID_TDMOUT_C_SCLK 129
-#define AUD_CLKID_TDMIN_A_LRCLK 130
-#define AUD_CLKID_TDMIN_B_LRCLK 131
-#define AUD_CLKID_TDMIN_C_LRCLK 132
-#define AUD_CLKID_TDMIN_LB_LRCLK 133
-#define AUD_CLKID_TDMOUT_A_LRCLK 134
-#define AUD_CLKID_TDMOUT_B_LRCLK 135
-#define AUD_CLKID_TDMOUT_C_LRCLK 136
-#define AUD_CLKID_SPDIFOUT_B 151
-#define AUD_CLKID_SPDIFOUT_B_CLK 152
-#define AUD_CLKID_TDM_MCLK_PAD0 155
-#define AUD_CLKID_TDM_MCLK_PAD1 156
-#define AUD_CLKID_TDM_LRCLK_PAD0 157
-#define AUD_CLKID_TDM_LRCLK_PAD1 158
-#define AUD_CLKID_TDM_LRCLK_PAD2 159
-#define AUD_CLKID_TDM_SCLK_PAD0 160
-#define AUD_CLKID_TDM_SCLK_PAD1 161
-#define AUD_CLKID_TDM_SCLK_PAD2 162
-#define AUD_CLKID_TOP 163
-#define AUD_CLKID_TORAM 164
-#define AUD_CLKID_EQDRC 165
-#define AUD_CLKID_RESAMPLE_B 166
-#define AUD_CLKID_TOVAD 167
-#define AUD_CLKID_LOCKER 168
-#define AUD_CLKID_SPDIFIN_LB 169
-#define AUD_CLKID_FRDDR_D 170
-#define AUD_CLKID_TODDR_D 171
-#define AUD_CLKID_LOOPBACK_B 172
-
-#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
deleted file mode 100644
index 93752ea..0000000
--- a/include/dt-bindings/clock/axg-clkc.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Meson-AXG clock tree IDs
- *
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- */
-
-#ifndef __AXG_CLKC_H
-#define __AXG_CLKC_H
-
-#define CLKID_SYS_PLL 0
-#define CLKID_FIXED_PLL 1
-#define CLKID_FCLK_DIV2 2
-#define CLKID_FCLK_DIV3 3
-#define CLKID_FCLK_DIV4 4
-#define CLKID_FCLK_DIV5 5
-#define CLKID_FCLK_DIV7 6
-#define CLKID_GP0_PLL 7
-#define CLKID_CLK81 10
-#define CLKID_MPLL0 11
-#define CLKID_MPLL1 12
-#define CLKID_MPLL2 13
-#define CLKID_MPLL3 14
-#define CLKID_DDR 15
-#define CLKID_AUDIO_LOCKER 16
-#define CLKID_MIPI_DSI_HOST 17
-#define CLKID_ISA 18
-#define CLKID_PL301 19
-#define CLKID_PERIPHS 20
-#define CLKID_SPICC0 21
-#define CLKID_I2C 22
-#define CLKID_RNG0 23
-#define CLKID_UART0 24
-#define CLKID_MIPI_DSI_PHY 25
-#define CLKID_SPICC1 26
-#define CLKID_PCIE_A 27
-#define CLKID_PCIE_B 28
-#define CLKID_HIU_IFACE 29
-#define CLKID_ASSIST_MISC 30
-#define CLKID_SD_EMMC_B 31
-#define CLKID_SD_EMMC_C 32
-#define CLKID_DMA 33
-#define CLKID_SPI 34
-#define CLKID_AUDIO 35
-#define CLKID_ETH 36
-#define CLKID_UART1 37
-#define CLKID_G2D 38
-#define CLKID_USB0 39
-#define CLKID_USB1 40
-#define CLKID_RESET 41
-#define CLKID_USB 42
-#define CLKID_AHB_ARB0 43
-#define CLKID_EFUSE 44
-#define CLKID_BOOT_ROM 45
-#define CLKID_AHB_DATA_BUS 46
-#define CLKID_AHB_CTRL_BUS 47
-#define CLKID_USB1_DDR_BRIDGE 48
-#define CLKID_USB0_DDR_BRIDGE 49
-#define CLKID_MMC_PCLK 50
-#define CLKID_VPU_INTR 51
-#define CLKID_SEC_AHB_AHB3_BRIDGE 52
-#define CLKID_GIC 53
-#define CLKID_AO_MEDIA_CPU 54
-#define CLKID_AO_AHB_SRAM 55
-#define CLKID_AO_AHB_BUS 56
-#define CLKID_AO_IFACE 57
-#define CLKID_AO_I2C 58
-#define CLKID_SD_EMMC_B_CLK0 59
-#define CLKID_SD_EMMC_C_CLK0 60
-#define CLKID_HIFI_PLL 69
-#define CLKID_PCIE_CML_EN0 79
-#define CLKID_PCIE_CML_EN1 80
-#define CLKID_GEN_CLK 84
-#define CLKID_VPU_0_SEL 92
-#define CLKID_VPU_0 93
-#define CLKID_VPU_1_SEL 95
-#define CLKID_VPU_1 96
-#define CLKID_VPU 97
-#define CLKID_VAPB_0_SEL 99
-#define CLKID_VAPB_0 100
-#define CLKID_VAPB_1_SEL 102
-#define CLKID_VAPB_1 103
-#define CLKID_VAPB_SEL 104
-#define CLKID_VAPB 105
-#define CLKID_VCLK 106
-#define CLKID_VCLK2 107
-#define CLKID_VCLK_DIV1 122
-#define CLKID_VCLK_DIV2 123
-#define CLKID_VCLK_DIV4 124
-#define CLKID_VCLK_DIV6 125
-#define CLKID_VCLK_DIV12 126
-#define CLKID_VCLK2_DIV1 127
-#define CLKID_VCLK2_DIV2 128
-#define CLKID_VCLK2_DIV4 129
-#define CLKID_VCLK2_DIV6 130
-#define CLKID_VCLK2_DIV12 131
-#define CLKID_CTS_ENCL 133
-#define CLKID_VDIN_MEAS 136
-
-#endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h
deleted file mode 100644
index 40e57a5..0000000
--- a/include/dt-bindings/gpio/meson-a1-gpio.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Qianggui Song <qianggui.song@amlogic.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_A1_GPIO_H
-#define _DT_BINDINGS_MESON_A1_GPIO_H
-
-#define GPIOP_0 0
-#define GPIOP_1 1
-#define GPIOP_2 2
-#define GPIOP_3 3
-#define GPIOP_4 4
-#define GPIOP_5 5
-#define GPIOP_6 6
-#define GPIOP_7 7
-#define GPIOP_8 8
-#define GPIOP_9 9
-#define GPIOP_10 10
-#define GPIOP_11 11
-#define GPIOP_12 12
-#define GPIOB_0 13
-#define GPIOB_1 14
-#define GPIOB_2 15
-#define GPIOB_3 16
-#define GPIOB_4 17
-#define GPIOB_5 18
-#define GPIOB_6 19
-#define GPIOX_0 20
-#define GPIOX_1 21
-#define GPIOX_2 22
-#define GPIOX_3 23
-#define GPIOX_4 24
-#define GPIOX_5 25
-#define GPIOX_6 26
-#define GPIOX_7 27
-#define GPIOX_8 28
-#define GPIOX_9 29
-#define GPIOX_10 30
-#define GPIOX_11 31
-#define GPIOX_12 32
-#define GPIOX_13 33
-#define GPIOX_14 34
-#define GPIOX_15 35
-#define GPIOX_16 36
-#define GPIOF_0 37
-#define GPIOF_1 38
-#define GPIOF_2 39
-#define GPIOF_3 40
-#define GPIOF_4 41
-#define GPIOF_5 42
-#define GPIOF_6 43
-#define GPIOF_7 44
-#define GPIOF_8 45
-#define GPIOF_9 46
-#define GPIOF_10 47
-#define GPIOF_11 48
-#define GPIOF_12 49
-#define GPIOA_0 50
-#define GPIOA_1 51
-#define GPIOA_2 52
-#define GPIOA_3 53
-#define GPIOA_4 54
-#define GPIOA_5 55
-#define GPIOA_6 56
-#define GPIOA_7 57
-#define GPIOA_8 58
-#define GPIOA_9 59
-#define GPIOA_10 60
-#define GPIOA_11 61
-
-#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
deleted file mode 100644
index 35b6f69..0000000
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/*
- * This header provides constants for the ARM GIC.
- */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/* interrupt specifier cell 0 */
-
-#define GIC_SPI 0
-#define GIC_PPI 1
-
-/*
- * Interrupt specifier cell 2.
- * The flags in irq.h are valid, plus those below.
- */
-#define GIC_CPU_MASK_RAW(x) ((x) << 8)
-#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
-
-#endif
diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h
deleted file mode 100644
index 8e39dfc..0000000
--- a/include/dt-bindings/power/meson-a1-power.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2023 SberDevices, Inc.
- * Author: Alexey Romanov <avromanov@sberdevices.ru>
- */
-
-#ifndef _DT_BINDINGS_MESON_A1_POWER_H
-#define _DT_BINDINGS_MESON_A1_POWER_H
-
-#define PWRC_DSPA_ID 8
-#define PWRC_DSPB_ID 9
-#define PWRC_UART_ID 10
-#define PWRC_DMC_ID 11
-#define PWRC_I2C_ID 12
-#define PWRC_PSRAM_ID 13
-#define PWRC_ACODEC_ID 14
-#define PWRC_AUDIO_ID 15
-#define PWRC_OTP_ID 16
-#define PWRC_DMA_ID 17
-#define PWRC_SD_EMMC_ID 18
-#define PWRC_RAMA_ID 19
-#define PWRC_RAMB_ID 20
-#define PWRC_IR_ID 21
-#define PWRC_SPICC_ID 22
-#define PWRC_SPIFC_ID 23
-#define PWRC_USB_ID 24
-#define PWRC_NIC_ID 25
-#define PWRC_PDMIN_ID 26
-#define PWRC_RSA_ID 27
-#define PWRC_MAX_ID 28
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h
deleted file mode 100644
index 2c749c6..0000000
--- a/include/dt-bindings/reset/amlogic,meson-a1-reset.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * Copyright (c) 2023, SberDevices, Inc.
- * Author: Alexey Romanov <avromanov@salutedevices.com>
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
-
-/* RESET0 */
-/* 0 */
-#define RESET_AM2AXI_VAD 1
-/* 2-3 */
-#define RESET_PSRAM 4
-#define RESET_PAD_CTRL 5
-/* 6 */
-#define RESET_TEMP_SENSOR 7
-#define RESET_AM2AXI_DEV 8
-/* 9 */
-#define RESET_SPICC_A 10
-#define RESET_MSR_CLK 11
-#define RESET_AUDIO 12
-#define RESET_ANALOG_CTRL 13
-#define RESET_SAR_ADC 14
-#define RESET_AUDIO_VAD 15
-#define RESET_CEC 16
-#define RESET_PWM_EF 17
-#define RESET_PWM_CD 18
-#define RESET_PWM_AB 19
-/* 20 */
-#define RESET_IR_CTRL 21
-#define RESET_I2C_S_A 22
-/* 23 */
-#define RESET_I2C_M_D 24
-#define RESET_I2C_M_C 25
-#define RESET_I2C_M_B 26
-#define RESET_I2C_M_A 27
-#define RESET_I2C_PROD_AHB 28
-#define RESET_I2C_PROD 29
-/* 30-31 */
-
-/* RESET1 */
-#define RESET_ACODEC 32
-#define RESET_DMA 33
-#define RESET_SD_EMMC_A 34
-/* 35 */
-#define RESET_USBCTRL 36
-/* 37 */
-#define RESET_USBPHY 38
-/* 39-41 */
-#define RESET_RSA 42
-#define RESET_DMC 43
-/* 44 */
-#define RESET_IRQ_CTRL 45
-/* 46 */
-#define RESET_NIC_VAD 47
-#define RESET_NIC_AXI 48
-#define RESET_RAMA 49
-#define RESET_RAMB 50
-/* 51-52 */
-#define RESET_ROM 53
-#define RESET_SPIFC 54
-#define RESET_GIC 55
-#define RESET_UART_C 56
-#define RESET_UART_B 57
-#define RESET_UART_A 58
-#define RESET_OSC_RING 59
-/* 60-63 */
-
-/* RESET2 */
-/* 64-95 */
-
-#endif
diff --git a/include/efi_api.h b/include/efi_api.h
index f07d074..61c4eda 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -616,6 +616,7 @@
# define DEVICE_PATH_SUB_TYPE_MSG_SCSI 0x02
# define DEVICE_PATH_SUB_TYPE_MSG_USB 0x05
# define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b
+# define DEVICE_PATH_SUB_TYPE_MSG_IPV4 0x0c
# define DEVICE_PATH_SUB_TYPE_MSG_UART 0x0e
# define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f
# define DEVICE_PATH_SUB_TYPE_MSG_USB_WWI 0x10
@@ -691,6 +692,22 @@
u8 uri[];
} __packed;
+struct efi_ipv4_address {
+ u8 ip_addr[4];
+};
+
+struct efi_device_path_ipv4 {
+ struct efi_device_path dp;
+ struct efi_ipv4_address local_ip_address;
+ struct efi_ipv4_address remote_ip_address;
+ u16 local_port;
+ u16 remote_port;
+ u16 protocol;
+ u8 static_ip_address;
+ struct efi_ipv4_address gateway_ip_address;
+ struct efi_ipv4_address subnet_mask;
+} __packed;
+
#define DEVICE_PATH_TYPE_MEDIA_DEVICE 0x04
# define DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH 0x01
# define DEVICE_PATH_SUB_TYPE_CDROM_PATH 0x02
@@ -1708,6 +1725,209 @@
struct efi_pxe_mode *mode;
};
+#define EFI_IP4_CONFIG2_PROTOCOL_GUID \
+ EFI_GUID(0x5b446ed1, 0xe30b, 0x4faa, \
+ 0x87, 0x1a, 0x36, 0x54, 0xec, 0xa3, 0x60, 0x80)
+
+enum efi_ip4_config2_data_type {
+ EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO,
+ EFI_IP4_CONFIG2_DATA_TYPE_POLICY,
+ EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS,
+ EFI_IP4_CONFIG2_DATA_TYPE_GATEWAY,
+ EFI_IP4_CONFIG2_DATA_TYPE_DNSSERVER,
+ EFI_IP4_CONFIG2_DATA_TYPE_MAXIMUM,
+};
+
+struct efi_ip4_config2_protocol {
+ efi_status_t (EFIAPI * set_data)(struct efi_ip4_config2_protocol *this,
+ enum efi_ip4_config2_data_type data_type,
+ efi_uintn_t data_size,
+ void *data);
+ efi_status_t (EFIAPI * get_data)(struct efi_ip4_config2_protocol *this,
+ enum efi_ip4_config2_data_type data_type,
+ efi_uintn_t *data_size,
+ void *data);
+ efi_status_t (EFIAPI * register_data_notify)(struct efi_ip4_config2_protocol *this,
+ enum efi_ip4_config2_data_type data_type,
+ struct efi_event *event);
+ efi_status_t (EFIAPI * unregister_data_notify)(struct efi_ip4_config2_protocol *this,
+ enum efi_ip4_config2_data_type data_type,
+ struct efi_event *event);
+};
+
+struct efi_ip4_route_table {
+ struct efi_ipv4_address subnet_address;
+ struct efi_ipv4_address subnet_mask;
+ struct efi_ipv4_address gateway_address;
+};
+
+#define EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE 32
+
+struct efi_ip4_config2_interface_info {
+ u16 name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE];
+ u8 if_type;
+ u32 hw_address_size;
+ struct efi_mac_address hw_address;
+ struct efi_ipv4_address station_address;
+ struct efi_ipv4_address subnet_mask;
+ u32 route_table_size;
+ struct efi_ip4_route_table *route_table;
+};
+
+enum efi_ip4_config2_policy {
+ EFI_IP4_CONFIG2_POLICY_STATIC,
+ EFI_IP4_CONFIG2_POLICY_DHCP,
+ EFI_IP4_CONFIG2_POLICY_MAX
+};
+
+struct efi_ip4_config2_manual_address {
+ struct efi_ipv4_address address;
+ struct efi_ipv4_address subnet_mask;
+};
+
+#define EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID \
+ EFI_GUID(0xbdc8e6af, 0xd9bc, 0x4379, \
+ 0xa7, 0x2a, 0xe0, 0xc4, 0xe7, 0x5d, 0xae, 0x1c)
+
+struct efi_service_binding_protocol {
+ efi_status_t (EFIAPI * create_child)(struct efi_service_binding_protocol *this,
+ efi_handle_t *child_handle);
+ efi_status_t (EFIAPI * destroy_child)(struct efi_service_binding_protocol *this,
+ efi_handle_t child_handle);
+};
+
+#define EFI_HTTP_PROTOCOL_GUID \
+ EFI_GUID(0x7A59B29B, 0x910B, 0x4171, \
+ 0x82, 0x42, 0xA8, 0x5A, 0x0D, 0xF2, 0x5B, 0x5B)
+
+enum efi_http_version {
+ HTTPVERSION10,
+ HTTPVERSION11,
+ HTTPVERSIONUNSUPPORTED
+};
+
+struct efi_httpv4_access_point {
+ bool use_default_address;
+ struct efi_ipv4_address local_address;
+ struct efi_ipv4_address local_subnet;
+ u16 local_port;
+};
+
+union efi_http_access_point {
+ struct efi_httpv4_access_point *ipv4_node;
+ struct efi_httpv6_access_point *ipv6_node;
+};
+
+struct efi_http_config_data {
+ enum efi_http_version http_version;
+ u32 timeout;
+ bool is_ipv6;
+ union efi_http_access_point access_point;
+};
+
+enum efi_http_method {
+ HTTP_METHOD_GET,
+ HTTP_METHOD_POST,
+ HTTP_METHOD_PATCH,
+ HTTP_METHOD_OPTIONS,
+ HTTP_METHOD_CONNECT,
+ HTTP_METHOD_HEAD,
+ HTTP_METHOD_PUT,
+ HTTP_METHOD_DELETE,
+ HTTP_METHOD_TRACE,
+ HTTP_METHOD_MAX
+};
+
+enum efi_http_status_code {
+ HTTP_STATUS_UNSUPPORTED_STATUS = 0,
+ HTTP_STATUS_100_CONTINUE,
+ HTTP_STATUS_101_SWITCHING_PROTOCOLS,
+ HTTP_STATUS_200_OK,
+ HTTP_STATUS_201_CREATED,
+ HTTP_STATUS_202_ACCEPTED,
+ HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION,
+ HTTP_STATUS_204_NO_CONTENT,
+ HTTP_STATUS_205_RESET_CONTENT,
+ HTTP_STATUS_206_PARTIAL_CONTENT,
+ HTTP_STATUS_300_MULTIPLE_CHOICES,
+ HTTP_STATUS_301_MOVED_PERMANENTLY,
+ HTTP_STATUS_302_FOUND,
+ HTTP_STATUS_303_SEE_OTHER,
+ HTTP_STATUS_304_NOT_MODIFIED,
+ HTTP_STATUS_305_USE_PROXY,
+ HTTP_STATUS_307_TEMPORARY_REDIRECT,
+ HTTP_STATUS_400_BAD_REQUEST,
+ HTTP_STATUS_401_UNAUTHORIZED,
+ HTTP_STATUS_402_PAYMENT_REQUIRED,
+ HTTP_STATUS_403_FORBIDDEN,
+ HTTP_STATUS_404_NOT_FOUND,
+ HTTP_STATUS_405_METHOD_NOT_ALLOWED,
+ HTTP_STATUS_406_NOT_ACCEPTABLE,
+ HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED,
+ HTTP_STATUS_408_REQUEST_TIME_OUT,
+ HTTP_STATUS_409_CONFLICT,
+ HTTP_STATUS_410_GONE,
+ HTTP_STATUS_411_LENGTH_REQUIRED,
+ HTTP_STATUS_412_PRECONDITION_FAILED,
+ HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE,
+ HTTP_STATUS_414_REQUEST_URI_TOO_LARGE,
+ HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE,
+ HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED,
+ HTTP_STATUS_417_EXPECTATION_FAILED,
+ HTTP_STATUS_500_INTERNAL_SERVER_ERROR,
+ HTTP_STATUS_501_NOT_IMPLEMENTED,
+ HTTP_STATUS_502_BAD_GATEWAY,
+ HTTP_STATUS_503_SERVICE_UNAVAILABLE,
+ HTTP_STATUS_504_GATEWAY_TIME_OUT,
+ HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED,
+ HTTP_STATUS_308_PERMANENT_REDIRECT
+};
+
+struct efi_http_request_data {
+ enum efi_http_method method;
+ u16 *url;
+};
+
+struct efi_http_response_data {
+ enum efi_http_status_code status_code;
+};
+
+struct efi_http_header {
+ char *field_name;
+ char *field_value;
+};
+
+struct efi_http_message {
+ union {
+ struct efi_http_request_data *request;
+ struct efi_http_response_data *response;
+ } data;
+ efi_uintn_t header_count;
+ struct efi_http_header *headers;
+ efi_uintn_t body_length;
+ void *body;
+};
+
+struct efi_http_token {
+ struct efi_event *event;
+ efi_status_t status;
+ struct efi_http_message *message;
+};
+
+struct efi_http_protocol {
+ efi_status_t (EFIAPI * get_mode_data)(struct efi_http_protocol *this,
+ struct efi_http_config_data *data);
+ efi_status_t (EFIAPI * configure)(struct efi_http_protocol *this,
+ struct efi_http_config_data *data);
+ efi_status_t (EFIAPI * request)(struct efi_http_protocol *this,
+ struct efi_http_token *token);
+ efi_status_t (EFIAPI * cancel)(struct efi_http_protocol *this,
+ struct efi_http_token *token);
+ efi_status_t (EFIAPI * response)(struct efi_http_protocol *this,
+ struct efi_http_token *token);
+ efi_status_t (EFIAPI * poll)(struct efi_http_protocol *this);
+};
+
#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID \
EFI_GUID(0x964e5b22, 0x6459, 0x11d2, \
0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 39809ea..9afbec3 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -16,6 +16,7 @@
#include <image.h>
#include <pe.h>
#include <linux/list.h>
+#include <linux/sizes.h>
#include <linux/oid_registry.h>
struct blk_desc;
@@ -125,6 +126,39 @@
size_t buffer_size) { }
#endif
+#if CONFIG_IS_ENABLED(NETDEVICES) && CONFIG_IS_ENABLED(EFI_LOADER)
+/* Call this to update the current device path of the efi net device */
+efi_status_t efi_net_set_dp(const char *dev, const char *server);
+/* Call this to get the current device path of the efi net device */
+void efi_net_get_dp(struct efi_device_path **dp);
+void efi_net_get_addr(struct efi_ipv4_address *ip,
+ struct efi_ipv4_address *mask,
+ struct efi_ipv4_address *gw);
+void efi_net_set_addr(struct efi_ipv4_address *ip,
+ struct efi_ipv4_address *mask,
+ struct efi_ipv4_address *gw);
+efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer,
+ u32 *status_code, ulong *file_size, char *headers_buffer);
+#define MAX_HTTP_HEADERS_SIZE SZ_64K
+#define MAX_HTTP_HEADERS 100
+#define MAX_HTTP_HEADER_NAME 128
+#define MAX_HTTP_HEADER_VALUE 512
+struct http_header {
+ uchar name[MAX_HTTP_HEADER_NAME];
+ uchar value[MAX_HTTP_HEADER_VALUE];
+};
+
+void efi_net_parse_headers(ulong *num_headers, struct http_header *headers);
+#else
+static inline void efi_net_get_dp(struct efi_device_path **dp) { }
+static inline void efi_net_get_addr(struct efi_ipv4_address *ip,
+ struct efi_ipv4_address *mask,
+ struct efi_ipv4_address *gw) { }
+static inline void efi_net_set_addr(struct efi_ipv4_address *ip,
+ struct efi_ipv4_address *mask,
+ struct efi_ipv4_address *gw) { }
+#endif
+
/* Maximum number of configuration tables */
#define EFI_MAX_CONFIGURATION_TABLES 16
@@ -592,6 +626,12 @@
efi_status_t efi_gop_register(void);
/* Called by bootefi to make the network interface available */
efi_status_t efi_net_register(void);
+/* Called by efi_net_register to make the ip4 config2 protocol available */
+efi_status_t efi_ipconfig_register(const efi_handle_t handle,
+ struct efi_ip4_config2_protocol *ip4config);
+/* Called by efi_net_register to make the http protocol available */
+efi_status_t efi_http_register(const efi_handle_t handle,
+ struct efi_service_binding_protocol *http_service_binding);
/* Called by bootefi to make the watchdog available */
efi_status_t efi_watchdog_register(void);
efi_status_t efi_initrd_register(void);
@@ -856,6 +896,7 @@
struct efi_device_path *efi_dp_from_file(const struct efi_device_path *dp,
const char *path);
struct efi_device_path *efi_dp_from_eth(void);
+struct efi_device_path *efi_dp_from_http(const char *server);
struct efi_device_path *efi_dp_from_mem(uint32_t mem_type,
uint64_t start_address,
size_t size);
diff --git a/include/env_callback.h b/include/env_callback.h
index bc8ff19..47a31f6 100644
--- a/include/env_callback.h
+++ b/include/env_callback.h
@@ -14,11 +14,6 @@
#define ENV_CALLBACK_VAR ".callbacks"
-/* Board configs can define additional static callback bindings */
-#ifndef CFG_ENV_CALLBACK_LIST_STATIC
-#define CFG_ENV_CALLBACK_LIST_STATIC
-#endif
-
#ifdef CONFIG_SILENT_CONSOLE
#define SILENT_CALLBACK "silent:silent,"
#else
@@ -90,7 +85,7 @@
SILENT_CALLBACK \
"stdin:console,stdout:console,stderr:console," \
"serial#:serialno," \
- CFG_ENV_CALLBACK_LIST_STATIC
+ CONFIG_ENV_CALLBACK_LIST_STATIC
#ifndef CONFIG_XPL_BUILD
void env_callback_init(struct env_entry *var_entry);
diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h
index 28adec2..04acc7f 100644
--- a/include/firmware/imx/sci/rpc.h
+++ b/include/firmware/imx/sci/rpc.h
@@ -231,4 +231,7 @@
#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */
#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
+/* Siemens specific API extension */
+#define TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG 20U /*!< Index for sc_timer_ctrl_pmic_wdog() RPC call */
+
#endif /* SC_RPC_H */
diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h
index 7d8499f..588f367 100644
--- a/include/firmware/imx/sci/sci.h
+++ b/include/firmware/imx/sci/sci.h
@@ -123,6 +123,7 @@
/* Timer API */
int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window);
+int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd);
/* SECO API */
int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
diff --git a/include/handoff.h b/include/handoff.h
index 0072ea8..c0ae7b1 100644
--- a/include/handoff.h
+++ b/include/handoff.h
@@ -32,13 +32,6 @@
void handoff_load_dram_banks(struct spl_handoff *ho);
/**
- * handoff_get() - Get the SPL handoff information
- *
- * Return: Pointer to SPL handoff if received, else NULL
- */
-struct spl_handoff *handoff_get(void);
-
-/**
* handoff_arch_save() - Save arch-specific info into the handoff area
*
* This is defined to an empty function by default, but arch-specific code can
diff --git a/include/image.h b/include/image.h
index c52fced..9be5acd 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1802,6 +1802,30 @@
struct andr_image_data;
/**
+ * android_image_get_bootimg_size() - Extract size of Android boot image
+ *
+ * This is used to extract the size of an Android boot image
+ * from boot image header.
+ *
+ * @hdr: Pointer to boot image header
+ * @boot_img_size: On exit returns the size in bytes of the boot image
+ * Return: true if succeeded, false otherwise
+ */
+bool android_image_get_bootimg_size(const void *hdr, u32 *boot_img_size);
+
+/**
+ * android_image_get_vendor_bootimg_size() - Extract size of Android vendor-boot image
+ *
+ * This is used to extract the size of an Android vendor-boot image
+ * from vendor-boot image header.
+ *
+ * @hdr: Pointer to vendor-boot image header
+ * @vendor_boot_img_size: On exit returns the size in bytes of the vendor-boot image
+ * Return: true if succeeded, false otherwise
+ */
+bool android_image_get_vendor_bootimg_size(const void *hdr, u32 *vendor_boot_img_size);
+
+/**
* android_image_get_data() - Parse Android boot images
*
* This is used to parse boot and vendor-boot header into
diff --git a/include/k3-avs.h b/include/k3-avs.h
index 1014d5d..5a973e4 100644
--- a/include/k3-avs.h
+++ b/include/k3-avs.h
@@ -20,11 +20,13 @@
#define NUM_OPPS 4
+#define AM6_OPP_LOW 0
#define AM6_OPP_NOM 1
#define AM6_OPP_OD 2
#define AM6_OPP_TURBO 3
int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id);
int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq);
+int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id);
#endif
diff --git a/include/net-common.h b/include/net-common.h
index 524ed4a..8fc1bac 100644
--- a/include/net-common.h
+++ b/include/net-common.h
@@ -8,6 +8,7 @@
#include <env.h>
#include <hexdump.h>
#include <linux/if_ether.h>
+#include <linux/sizes.h>
#include <linux/types.h>
#include <rand.h>
#include <time.h>
@@ -425,6 +426,16 @@
*/
struct in_addr string_to_ip(const char *s);
+/**
+ * ip_to_string() - Convert a string to ip address
+ *
+ * Implemented in lib/net_utils.c (built unconditionally)
+ *
+ * @x: Input ip to parse
+ * @s: string containing the parsed ip address
+ */
+void ip_to_string(struct in_addr x, char *s);
+
/* copy a filename (allow for "..." notation, limit length) */
void copy_filename(char *dst, const char *src, int size);
@@ -490,13 +501,16 @@
int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
/**
- * wget_with_dns() - runs dns host IP address resulution before wget
+ * wget_do_request() - sends a wget request
+ *
+ * Sends a wget request, if DNS resolution is enabled it resolves the
+ * given uri.
*
* @dst_addr: destination address to download the file
* @uri: uri string of target file of wget
- * Return: downloaded file size, negative if failed
+ * Return: zero on success, negative if failed
*/
-int wget_with_dns(ulong dst_addr, char *uri);
+int wget_do_request(ulong dst_addr, char *uri);
/**
* wget_validate_uri() - varidate the uri
*
@@ -506,4 +520,55 @@
bool wget_validate_uri(char *uri);
//int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
+/**
+ * enum wget_http_method - http method
+ */
+enum wget_http_method {
+ WGET_HTTP_METHOD_GET,
+ WGET_HTTP_METHOD_POST,
+ WGET_HTTP_METHOD_PATCH,
+ WGET_HTTP_METHOD_OPTIONS,
+ WGET_HTTP_METHOD_CONNECT,
+ WGET_HTTP_METHOD_HEAD,
+ WGET_HTTP_METHOD_PUT,
+ WGET_HTTP_METHOD_DELETE,
+ WGET_HTTP_METHOD_TRACE,
+ WGET_HTTP_METHOD_MAX
+};
+
+/**
+ * define MAX_HTTP_HEADERS_SIZE - maximum headers buffer size
+ *
+ * When receiving http headers, wget fills a buffer with up
+ * to MAX_HTTP_HEADERS_SIZE bytes of header information.
+ */
+#define MAX_HTTP_HEADERS_SIZE SZ_64K
+
+/**
+ * struct wget_http_info - wget parameters
+ * @method: HTTP Method. Filled by client.
+ * @status_code: HTTP status code. Filled by wget.
+ * @file_size: download size. Filled by wget.
+ * @buffer_size: size of client-provided buffer. Filled by client.
+ * @set_bootdev: set boot device with download. Filled by client.
+ * @check_buffer_size: check download does not exceed buffer size.
+ * Filled by client.
+ * @hdr_cont_len: content length according to headers. Filled by wget
+ * @headers: buffer for headers. Filled by wget.
+ */
+struct wget_http_info {
+ enum wget_http_method method;
+ u32 status_code;
+ ulong file_size;
+ ulong buffer_size;
+ bool set_bootdev;
+ bool check_buffer_size;
+ u32 hdr_cont_len;
+ char *headers;
+};
+
+extern struct wget_http_info default_wget_info;
+extern struct wget_http_info *wget_info;
+int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info);
+
#endif /* __NET_COMMON_H__ */
diff --git a/include/net-lwip.h b/include/net-lwip.h
index 1c3583f..4d7f938 100644
--- a/include/net-lwip.h
+++ b/include/net-lwip.h
@@ -17,15 +17,6 @@
int net_lwip_rx(struct udevice *udev, struct netif *netif);
/**
- * wget_with_dns() - runs dns host IP address resulution before wget
- *
- * @dst_addr: destination address to download the file
- * @uri: uri string of target file of wget
- * Return: downloaded file size, negative if failed
- */
-
-int wget_with_dns(ulong dst_addr, char *uri);
-/**
* wget_validate_uri() - varidate the uri
*
* @uri: uri string of target file of wget
diff --git a/include/netdev.h b/include/netdev.h
index 2a06d9a..949245e 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -117,7 +117,7 @@
return num;
}
-struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id);
+struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id);
#ifdef CONFIG_PHYLIB
struct phy_device;
diff --git a/include/ns16550.h b/include/ns16550.h
index 7f48130..5d9ff10 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -25,6 +25,7 @@
#define __ns16550_h
#include <linux/types.h>
+#include <serial.h>
#if CONFIG_IS_ENABLED(DM_SERIAL) || defined(CONFIG_NS16550_DYNAMIC) || \
defined(CONFIG_DEBUG_UART)
@@ -116,6 +117,15 @@
#endif
};
+#if CONFIG_IS_ENABLED(DM_SERIAL)
+#define serial_out(value, addr) \
+ ns16550_writeb(com_port, \
+ (unsigned char *)(addr) - (unsigned char *)com_port, value)
+#define serial_in(addr) \
+ ns16550_readb(com_port, \
+ (unsigned char *)(addr) - (unsigned char *)com_port)
+#endif
+
#define thr rbr
#define iir fcr
#define dll rbr
@@ -225,6 +235,14 @@
char ns16550_getc(struct ns16550 *com_port);
int ns16550_tstc(struct ns16550 *com_port);
void ns16550_reinit(struct ns16550 *com_port, int baud_divisor);
+int ns16550_serial_putc(struct udevice *dev, const char ch);
+int ns16550_serial_pending(struct udevice *dev, bool input);
+int ns16550_serial_getc(struct udevice *dev);
+int ns16550_serial_setbrg(struct udevice *dev, int baudrate);
+int ns16550_serial_setconfig(struct udevice *dev, uint serial_config);
+int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info);
+void ns16550_writeb(struct ns16550 *port, int offset, int value);
+void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor);
/**
* ns16550_calc_divisor() - calculate the divisor given clock and baud rate
diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h
index 2df17ec..0c94487 100644
--- a/include/renesas/rzg2l-pfc.h
+++ b/include/renesas/rzg2l-pfc.h
@@ -22,6 +22,7 @@
#define PIN_CFG_FILONOFF BIT(10)
#define PIN_CFG_FILNUM BIT(11)
#define PIN_CFG_FILCLKSEL BIT(12)
+#define PIN_CFG_OEN BIT(13)
#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
PIN_CFG_SR | \
@@ -77,9 +78,12 @@
#define IEN(n) (0x1800 + (n) * 8)
#define PWPR 0x3014
#define SD_CH(n) (0x3000 + (n) * 4)
+#define ETH_POC(ch) (0x300c + (ch) * 4)
#define QSPI 0x3008
+#define ETH_MODE 0x3018
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
+#define PVDD_2500 2 /* I/O domain voltage 2.5V */
#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
#define PWPR_B0WI BIT(7) /* Bit Write Disable */
diff --git a/include/sysinfo.h b/include/sysinfo.h
index 8a77ef4..027a463 100644
--- a/include/sysinfo.h
+++ b/include/sysinfo.h
@@ -40,29 +40,29 @@
/** enum sysinfo_id - Standard IDs defined by U-Boot */
enum sysinfo_id {
- SYSINFO_ID_NONE,
+ SYSID_NONE,
/* For SMBIOS tables */
- SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER,
- SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT,
- SYSINFO_ID_SMBIOS_SYSTEM_VERSION,
- SYSINFO_ID_SMBIOS_SYSTEM_SERIAL,
- SYSINFO_ID_SMBIOS_SYSTEM_SKU,
- SYSINFO_ID_SMBIOS_SYSTEM_FAMILY,
- SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER,
- SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT,
- SYSINFO_ID_SMBIOS_BASEBOARD_VERSION,
- SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL,
- SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG,
+ SYSID_SM_SYSTEM_MANUFACTURER,
+ SYSID_SM_SYSTEM_PRODUCT,
+ SYSID_SM_SYSTEM_VERSION,
+ SYSID_SM_SYSTEM_SERIAL,
+ SYSID_SM_SYSTEM_SKU,
+ SYSID_SM_SYSTEM_FAMILY,
+ SYSID_SM_BASEBOARD_MANUFACTURER,
+ SYSID_SM_BASEBOARD_PRODUCT,
+ SYSID_SM_BASEBOARD_VERSION,
+ SYSID_SM_BASEBOARD_SERIAL,
+ SYSID_SM_BASEBOARD_ASSET_TAG,
/* For show_board_info() */
- SYSINFO_ID_BOARD_MODEL,
- SYSINFO_ID_BOARD_MANUFACTURER,
- SYSINFO_ID_PRIOR_STAGE_VERSION,
- SYSINFO_ID_PRIOR_STAGE_DATE,
+ SYSID_BOARD_MODEL,
+ SYSID_BOARD_MANUFACTURER,
+ SYSID_PRIOR_STAGE_VERSION,
+ SYSID_PRIOR_STAGE_DATE,
/* First value available for downstream/board used */
- SYSINFO_ID_USER = 0x1000,
+ SYSID_USER = 0x1000,
};
struct sysinfo_ops {
diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h
index c98b1a5..2a52e16 100644
--- a/include/u-boot/md5.h
+++ b/include/u-boot/md5.h
@@ -6,7 +6,9 @@
#ifndef _MD5_H
#define _MD5_H
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#include <linux/kconfig.h>
+
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
#include <mbedtls/md5.h>
#endif
#include "compiler.h"
@@ -14,7 +16,7 @@
#define MD5_SUM_LEN 16
#define MD5_DEF_CHUNK_SZ 0x10000
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
typedef mbedtls_md5_context MD5Context;
#else
typedef struct MD5Context {
diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h
index 2fca7f1..dd66258 100644
--- a/include/u-boot/sha1.h
+++ b/include/u-boot/sha1.h
@@ -14,9 +14,10 @@
#ifndef _SHA1_H
#define _SHA1_H
+#include <linux/kconfig.h>
#include <linux/types.h>
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
/*
* FIXME:
* MbedTLS define the members of "mbedtls_sha256_context" as private,
@@ -47,7 +48,7 @@
extern const uint8_t sha1_der_prefix[];
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
typedef mbedtls_sha1_context sha1_context;
#else
/**
diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h
index b58d5b5..44a9b52 100644
--- a/include/u-boot/sha256.h
+++ b/include/u-boot/sha256.h
@@ -1,9 +1,10 @@
#ifndef _SHA256_H
#define _SHA256_H
+#include <linux/kconfig.h>
#include <linux/types.h>
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
/*
* FIXME:
* MbedTLS define the members of "mbedtls_sha256_context" as private,
@@ -27,7 +28,7 @@
/* Reset watchdog each time we process this many bytes */
#define CHUNKSZ_SHA256 (64 * 1024)
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
typedef mbedtls_sha256_context sha256_context;
#else
typedef struct {
diff --git a/include/u-boot/sha512.h b/include/u-boot/sha512.h
index 7e10f59..92660d9 100644
--- a/include/u-boot/sha512.h
+++ b/include/u-boot/sha512.h
@@ -1,9 +1,10 @@
#ifndef _SHA512_H
#define _SHA512_H
+#include <linux/kconfig.h>
#include <linux/types.h>
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
#include <mbedtls/sha512.h>
#endif
@@ -16,7 +17,7 @@
#define CHUNKSZ_SHA384 (16 * 1024)
#define CHUNKSZ_SHA512 (16 * 1024)
-#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO)
typedef mbedtls_sha512_context sha384_context;
typedef mbedtls_sha512_context sha512_context;
#else
diff --git a/lib/Kconfig b/lib/Kconfig
index 56ffdfa..0b08981 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -45,6 +45,15 @@
locate entries in the firmware image. See binman.h for the available
functionality.
+config BINMAN_DTB
+ string "binman DTB description"
+ depends on BINMAN
+ help
+ This enables option to point to different DTB file with binman node which
+ is outside of DTB used by the firmware. Use this option if information
+ about generated images shouldn't be the part of target binary. Or on system
+ with limited storage.
+
config CC_OPTIMIZE_LIBS_FOR_SPEED
bool "Optimize libraries for speed"
help
diff --git a/lib/Makefile b/lib/Makefile
index dbcfa87..d24ed62 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -97,7 +97,7 @@
obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += libfdt/
obj-$(CONFIG_$(PHASE_)OF_REAL) += fdtdec_common.o fdtdec.o
-obj-$(CONFIG_MBEDTLS_LIB) += mbedtls/
+obj-$(CONFIG_$(XPL_)MBEDTLS_LIB) += mbedtls/
obj-$(CONFIG_NET_LWIP) += lwip/
diff --git a/lib/binman.c b/lib/binman.c
index 93d8554..9047f52 100644
--- a/lib/binman.c
+++ b/lib/binman.c
@@ -137,7 +137,6 @@
{
int ret;
- return 0;
binman = malloc(sizeof(struct binman_info));
if (!binman)
return log_msg_ret("space for binman", -ENOMEM);
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index d93f28b..c46ffe3 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -2,7 +2,7 @@
config EFI_LOADER
bool "Support running UEFI applications"
- depends on OF_LIBFDT && ( \
+ depends on ( \
ARM && (SYS_CPU = arm1136 || \
SYS_CPU = arm1176 || \
SYS_CPU = armv7 || \
@@ -21,6 +21,7 @@
select EVENT_DYNAMIC
select LIB_UUID
select LMB
+ select OF_LIBFDT
imply PARTITION_UUIDS
select REGEX
imply FAT
@@ -476,6 +477,23 @@
replace the transfer via the device-tree. The latter is not
possible on systems using ACPI.
+config EFI_IP4_CONFIG2_PROTOCOL
+ bool "EFI_IP4_CONFIG2_PROTOCOL support"
+ default y if ARCH_QEMU || SANDBOX
+ depends on NET || NET_LWIP
+ help
+ Provides an implementation of the EFI_IP4_CONFIG2_PROTOCOL, this
+ protocol can be used to set and get the current ip address and
+ other network information.
+
+config EFI_HTTP_PROTOCOL
+ bool "EFI_HTTP_PROTOCOL support"
+ default y if ARCH_QEMU || SANDBOX
+ depends on WGET
+ help
+ Provides an EFI HTTP driver implementing the EFI_HTTP_PROTOCOL. and
+ EFI_HTTP_SERVICE_BINDING_PROTOCOL.
+
endmenu
menu "Misc options"
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 87131ab..2a0b417 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -59,6 +59,8 @@
obj-$(CONFIG_VIDEO) += efi_gop.o
obj-$(CONFIG_BLK) += efi_disk.o
obj-$(CONFIG_NETDEVICES) += efi_net.o
+obj-$(CONFIG_EFI_IP4_CONFIG2_PROTOCOL) += efi_ipconfig.o
+obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_http.o
obj-$(CONFIG_ACPI) += efi_acpi.o
obj-$(CONFIG_SMBIOS) += efi_smbios.o
obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o
diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c
index a87006b..b677bbc 100644
--- a/lib/efi_loader/efi_bootbin.c
+++ b/lib/efi_loader/efi_bootbin.c
@@ -93,24 +93,34 @@
image_addr = buffer;
image_size = buffer_size;
+#if IS_ENABLED(CONFIG_NETDEVICES)
+ if (!strcmp(dev, "Net") || !strcmp(dev, "Http")) {
+ ret = efi_net_set_dp(dev, devnr);
+ if (ret != EFI_SUCCESS)
+ goto error;
+ }
+#endif
+
ret = efi_dp_from_name(dev, devnr, path, &device, &image);
- if (ret == EFI_SUCCESS) {
- bootefi_device_path = device;
- if (image) {
- /* FIXME: image should not contain device */
- struct efi_device_path *image_tmp = image;
+ if (ret != EFI_SUCCESS)
+ goto error;
- efi_dp_split_file_path(image, &device, &image);
- efi_free_pool(image_tmp);
- }
- bootefi_image_path = image;
- log_debug("- boot device %pD\n", device);
- if (image)
- log_debug("- image %pD\n", image);
- } else {
- log_debug("- efi_dp_from_name() failed, err=%lx\n", ret);
- efi_clear_bootdev();
+ bootefi_device_path = device;
+ if (image) {
+ /* FIXME: image should not contain device */
+ struct efi_device_path *image_tmp = image;
+
+ efi_dp_split_file_path(image, &device, &image);
+ efi_free_pool(image_tmp);
}
+ bootefi_image_path = image;
+ log_debug("- boot device %pD\n", device);
+ if (image)
+ log_debug("- image %pD\n", image);
+ return;
+error:
+ log_debug("- efi_dp_from_name() failed, err=%lx\n", ret);
+ efi_clear_bootdev();
}
/**
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 8c51a6e..c6124c5 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -479,7 +479,7 @@
}
image_addr = hextoul(s, NULL);
- err = wget_with_dns(image_addr, uridp->uri);
+ err = wget_do_request(image_addr, uridp->uri);
if (err < 0) {
ret = EFI_INVALID_PARAMETER;
goto err;
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index ee387e1..c0633a7 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -974,6 +974,116 @@
return start;
}
+/**
+ * efi_dp_from_ipv4() - set device path from IPv4 address
+ *
+ * Set the device path to an ethernet device path as provided by
+ * efi_dp_from_eth() concatenated with a device path of subtype
+ * DEVICE_PATH_SUB_TYPE_MSG_IPV4, and an END node.
+ *
+ * @ip: IPv4 local address
+ * @mask: network mask
+ * @srv: IPv4 remote/server address
+ * Return: pointer to device path, NULL on error
+ */
+static struct efi_device_path *efi_dp_from_ipv4(struct efi_ipv4_address *ip,
+ struct efi_ipv4_address *mask,
+ struct efi_ipv4_address *srv)
+{
+ struct efi_device_path *dp1, *dp2, *pos;
+ struct {
+ struct efi_device_path_ipv4 ipv4dp;
+ struct efi_device_path end;
+ } dp;
+
+ memset(&dp.ipv4dp, 0, sizeof(dp.ipv4dp));
+ dp.ipv4dp.dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ dp.ipv4dp.dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_IPV4;
+ dp.ipv4dp.dp.length = sizeof(dp.ipv4dp);
+ dp.ipv4dp.protocol = 6;
+ if (ip)
+ memcpy(&dp.ipv4dp.local_ip_address, ip, sizeof(*ip));
+ if (mask)
+ memcpy(&dp.ipv4dp.subnet_mask, mask, sizeof(*mask));
+ if (srv)
+ memcpy(&dp.ipv4dp.remote_ip_address, srv, sizeof(*srv));
+ pos = &dp.end;
+ memcpy(pos, &END, sizeof(END));
+
+ dp1 = efi_dp_from_eth();
+ if (!dp1)
+ return NULL;
+
+ dp2 = efi_dp_concat(dp1, (const struct efi_device_path *)&dp, 0);
+
+ efi_free_pool(dp1);
+
+ return dp2;
+}
+
+/**
+ * efi_dp_from_http() - set device path from http
+ *
+ * Set the device path to an IPv4 path as provided by efi_dp_from_ipv4
+ * concatenated with a device path of subtype DEVICE_PATH_SUB_TYPE_MSG_URI,
+ * and an END node.
+ *
+ * @server: URI of remote server
+ * Return: pointer to HTTP device path, NULL on error
+ */
+struct efi_device_path *efi_dp_from_http(const char *server)
+{
+ struct efi_device_path *dp1, *dp2;
+ struct efi_device_path_uri *uridp;
+ efi_uintn_t uridp_len;
+ char *pos;
+ char tmp[128];
+ struct efi_ipv4_address ip;
+ struct efi_ipv4_address mask;
+
+ if ((server && strlen("http://") + strlen(server) + 1 > sizeof(tmp)) ||
+ (!server && IS_ENABLED(CONFIG_NET_LWIP)))
+ return NULL;
+
+ efi_net_get_addr(&ip, &mask, NULL);
+
+ dp1 = efi_dp_from_ipv4(&ip, &mask, NULL);
+ if (!dp1)
+ return NULL;
+
+ strcpy(tmp, "http://");
+
+ if (server) {
+ strlcat(tmp, server, sizeof(tmp));
+#if !IS_ENABLED(CONFIG_NET_LWIP)
+ } else {
+ ip_to_string(net_server_ip, tmp + strlen("http://"));
+#endif
+ }
+
+ uridp_len = sizeof(struct efi_device_path) + strlen(tmp) + 1;
+ uridp = efi_alloc(uridp_len + sizeof(END));
+ if (!uridp) {
+ log_err("Out of memory\n");
+ return NULL;
+ }
+ uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI;
+ uridp->dp.length = uridp_len;
+ debug("device path: setting uri device path to %s\n", tmp);
+ memcpy(uridp->uri, tmp, strlen(tmp) + 1);
+
+ pos = (char *)uridp + uridp_len;
+ memcpy(pos, &END, sizeof(END));
+
+ dp2 = efi_dp_concat(dp1, (const struct efi_device_path *)uridp, 0);
+
+ efi_free_pool(uridp);
+ efi_free_pool(dp1);
+
+ return dp2;
+}
+
/* Construct a device-path for memory-mapped image */
struct efi_device_path *efi_dp_from_mem(uint32_t memory_type,
uint64_t start_address,
@@ -1074,8 +1184,9 @@
dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
(uintptr_t)image_addr, image_size);
- } else if (IS_ENABLED(CONFIG_NETDEVICES) && !strcmp(dev, "Net")) {
- dp = efi_dp_from_eth();
+ } else if (IS_ENABLED(CONFIG_NETDEVICES) &&
+ (!strcmp(dev, "Net") || !strcmp(dev, "Http"))) {
+ efi_net_get_dp(&dp);
} else if (!strcmp(dev, "Uart")) {
dp = efi_dp_from_uart();
} else {
diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c
index 0c7b30a..481a971 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -8,6 +8,7 @@
#include <blk.h>
#include <efi_loader.h>
#include <malloc.h>
+#include <net.h>
#define MAC_OUTPUT_LEN 22
#define UNKNOWN_OUTPUT_LEN 23
@@ -170,6 +171,28 @@
break;
}
+ case DEVICE_PATH_SUB_TYPE_MSG_IPV4: {
+ struct efi_device_path_ipv4 *idp =
+ (struct efi_device_path_ipv4 *)dp;
+
+ s += sprintf(s, "IPv4(%pI4,", &idp->remote_ip_address);
+ switch (idp->protocol) {
+ case IPPROTO_TCP:
+ s += sprintf(s, "TCP,");
+ case IPPROTO_UDP:
+ s += sprintf(s, "UDP,");
+ default:
+ s += sprintf(s, "0x%x,", idp->protocol);
+ }
+ s += sprintf(s, idp->static_ip_address ? "Static" : "DHCP");
+ s += sprintf(s, ",%pI4", &idp->local_ip_address);
+ if (idp->dp.length == sizeof(struct efi_device_path_ipv4))
+ s += sprintf(s, ",%pI4,%pI4", &idp->gateway_ip_address,
+ &idp->subnet_mask);
+ s += sprintf(s, ")");
+
+ break;
+ }
case DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS: {
struct efi_device_path_usb_class *ucdp =
(struct efi_device_path_usb_class *)dp;
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 6650c2b..112775d 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -281,6 +281,10 @@
}
for (i = 0; i < update_info.num_images; i++) {
+ if (!fw_array[i].fw_name) {
+ log_err("fw_name is not defined. Not generating capsule GUIDs\n");
+ return EFI_INVALID_PARAMETER;
+ }
gen_v5_guid(&namespace,
&fw_array[i].image_type_id,
compatible, strlen(compatible),
diff --git a/lib/efi_loader/efi_http.c b/lib/efi_loader/efi_http.c
new file mode 100644
index 0000000..694e199
--- /dev/null
+++ b/lib/efi_loader/efi_http.c
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * An HTTP driver
+ *
+ * HTTP_PROTOCOL
+ * HTTP_SERVICE_BINDING_PROTOCOL
+ * IP4_CONFIG2_PROTOCOL
+ */
+
+#include <charset.h>
+#include <efi_loader.h>
+#include <image.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <net.h>
+
+static const efi_guid_t efi_http_service_binding_guid = EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID;
+static const efi_guid_t efi_http_guid = EFI_HTTP_PROTOCOL_GUID;
+
+/**
+ * struct efi_http_instance - EFI object representing an HTTP protocol instance
+ *
+ * @http: EFI_HTTP_PROTOCOL interface
+ * @handle: handle to efi object
+ * @configured: configuration status
+ * @http_load_addr: data buffer
+ * @file_size: size of data
+ * @current_offset: offset in data buffer
+ * @status_code: HTTP status code
+ * @num_headers: number of received headers
+ * @headers: array of headers
+ * @headers_buffer: raw buffer with headers
+ */
+struct efi_http_instance {
+ struct efi_http_protocol http;
+ efi_handle_t handle;
+ bool configured;
+ void *http_load_addr;
+ ulong file_size;
+ ulong current_offset;
+ u32 status_code;
+ ulong num_headers;
+ struct http_header headers[MAX_HTTP_HEADERS];
+ char headers_buffer[MAX_HTTP_HEADERS_SIZE];
+};
+
+static int num_instances;
+
+/*
+ * efi_u32_to_httpstatus() - convert u32 to status
+ *
+ */
+enum efi_http_status_code efi_u32_to_httpstatus(u32 status);
+
+/*
+ * efi_http_send_data() - sends data to client
+ *
+ *
+ * @client_buffer: client buffer to send data to
+ * @client_buffer_size: size of the client buffer
+ * @inst: HTTP instance for which to send data
+ *
+ * Return: status code
+ */
+static efi_status_t efi_http_send_data(void *client_buffer,
+ efi_uintn_t *client_buffer_size,
+ struct efi_http_instance *inst)
+{
+ efi_status_t ret = EFI_SUCCESS;
+ ulong total_size, transfer_size;
+ uchar *ptr;
+
+ // Amount of data left;
+ total_size = inst->file_size;
+ transfer_size = total_size - inst->current_offset;
+ debug("efi_http: sending data to client, total size %lu\n", total_size);
+ // Amount of data the client is willing to receive
+ if (transfer_size > *client_buffer_size)
+ transfer_size = *client_buffer_size;
+ else
+ *client_buffer_size = transfer_size;
+ debug("efi_http: transfer size %lu\n", transfer_size);
+ if (!transfer_size) // Ok, only headers
+ goto out;
+
+ if (!client_buffer) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ // Send data
+ ptr = (uchar *)inst->http_load_addr + inst->current_offset;
+ memcpy(client_buffer, ptr, transfer_size);
+
+ inst->current_offset += transfer_size;
+
+ // Whole file served, clean the buffer:
+ if (inst->current_offset == inst->file_size) {
+ efi_free_pool(inst->http_load_addr);
+ inst->http_load_addr = NULL;
+ inst->current_offset = 0;
+ inst->file_size = 0;
+ }
+
+out:
+ return ret;
+}
+
+/* EFI_HTTP_PROTOCOL */
+
+/*
+ * efi_http_get_mode_data() - Gets the current operational status.
+ *
+ * This function implements EFI_HTTP_PROTOCOL.GetModeData().
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @data: pointer to the buffer for operational parameters
+ * of this HTTP instance
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_http_get_mode_data(struct efi_http_protocol *this,
+ struct efi_http_config_data *data)
+{
+ EFI_ENTRY("%p, %p", this, data);
+
+ efi_status_t ret = EFI_UNSUPPORTED;
+
+ return EFI_EXIT(ret);
+}
+
+/*
+ * efi_http_configure() - Initializes operational status for this
+ * EFI HTTP instance.
+ *
+ * This function implements EFI_HTTP_PROTOCOL.Configure().
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @data: pointer to the buffer for operational parameters of
+ * this HTTP instance
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_http_configure(struct efi_http_protocol *this,
+ struct efi_http_config_data *data)
+{
+ EFI_ENTRY("%p, %p", this, data);
+
+ efi_status_t ret = EFI_SUCCESS;
+ enum efi_http_version http_version;
+ struct efi_httpv4_access_point *ipv4_node;
+ struct efi_http_instance *http_instance;
+
+ if (!this) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ http_instance = (struct efi_http_instance *)this;
+
+ if (!data) {
+ efi_free_pool(http_instance->http_load_addr);
+ http_instance->http_load_addr = NULL;
+ http_instance->current_offset = 0;
+ http_instance->configured = false;
+
+ goto out;
+ }
+
+ if (http_instance->configured) {
+ ret = EFI_ALREADY_STARTED;
+ goto out;
+ }
+
+ http_version = data->http_version;
+ ipv4_node = data->access_point.ipv4_node;
+
+ if ((http_version != HTTPVERSION10 &&
+ http_version != HTTPVERSION11) ||
+ data->is_ipv6 || !ipv4_node) { /* Only support ipv4 */
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+
+ if (!ipv4_node->use_default_address) {
+ efi_net_set_addr((struct efi_ipv4_address *)&ipv4_node->local_address,
+ (struct efi_ipv4_address *)&ipv4_node->local_subnet, NULL);
+ }
+
+ http_instance->current_offset = 0;
+ http_instance->configured = true;
+
+out:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * efi_http_request() - Queues an HTTP request to this HTTP instance
+ *
+ * This function implements EFI_HTTP_PROTOCOL.Request().
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @token: pointer to storage containing HTTP request token
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_http_request(struct efi_http_protocol *this,
+ struct efi_http_token *token)
+{
+ EFI_ENTRY("%p, %p", this, token);
+
+ efi_status_t ret = EFI_SUCCESS;
+ u8 *tmp;
+ u8 url_8[1024];
+ u16 *url_16;
+ enum efi_http_method current_method;
+ struct efi_http_instance *http_instance;
+
+ if (!token || !this || !token->message ||
+ !token->message->data.request) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ http_instance = (struct efi_http_instance *)this;
+
+ if (!http_instance->configured) {
+ ret = EFI_NOT_STARTED;
+ goto out;
+ }
+
+ current_method = token->message->data.request->method;
+ url_16 = token->message->data.request->url;
+
+ /* Parse URL. It comes in UCS-2 encoding and follows RFC3986 */
+ tmp = url_8;
+ utf16_utf8_strncpy((char **)&tmp, url_16, 1024);
+
+ ret = efi_net_do_request(url_8, current_method, &http_instance->http_load_addr,
+ &http_instance->status_code, &http_instance->file_size,
+ http_instance->headers_buffer);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ // We have a successful request
+ efi_net_parse_headers(&http_instance->num_headers, http_instance->headers);
+ http_instance->current_offset = 0;
+ token->status = EFI_SUCCESS;
+ goto out_signal;
+
+out_signal:
+ efi_signal_event(token->event);
+out:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * efi_http_cancel() - Abort an asynchronous HTTP request or response token
+ *
+ * This function implements EFI_HTTP_PROTOCOL.Cancel().
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @token: pointer to storage containing HTTP request token
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_http_cancel(struct efi_http_protocol *this,
+ struct efi_http_token *token)
+{
+ EFI_ENTRY("%p, %p", this, token);
+
+ efi_status_t ret = EFI_UNSUPPORTED;
+
+ return EFI_EXIT(ret);
+}
+
+/*
+ * efi_http_response() - Queues an HTTP response to this HTTP instance
+ *
+ * This function implements EFI_HTTP_PROTOCOL.Response().
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @token: pointer to storage containing HTTP request token
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_http_response(struct efi_http_protocol *this,
+ struct efi_http_token *token)
+{
+ EFI_ENTRY("%p, %p", this, token);
+
+ efi_status_t ret = EFI_SUCCESS;
+ struct efi_http_instance *http_instance;
+ struct efi_http_header **client_headers;
+ struct efi_http_response_data *response;
+
+ if (!token || !this || !token->message) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ http_instance = (struct efi_http_instance *)this;
+
+ // Set HTTP status code
+ if (token->message->data.response) { // TODO extra check, see spec.
+ response = token->message->data.response;
+ response->status_code = efi_u32_to_httpstatus(http_instance->status_code);
+ }
+
+ client_headers = &token->message->headers;
+
+ ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA,
+ (http_instance->num_headers) * sizeof(struct efi_http_header),
+ (void **)client_headers); // This is deallocated by the client.
+ if (ret != EFI_SUCCESS)
+ goto out_bad_signal;
+
+ // Send headers
+ token->message->header_count = http_instance->num_headers;
+ for (int i = 0; i < http_instance->num_headers; i++) {
+ (*client_headers)[i].field_name = http_instance->headers[i].name;
+ (*client_headers)[i].field_value = http_instance->headers[i].value;
+ }
+
+ ret = efi_http_send_data(token->message->body, &token->message->body_length, http_instance);
+ if (ret != EFI_SUCCESS)
+ goto out_bad_signal;
+
+ token->status = EFI_SUCCESS;
+ goto out_signal;
+
+out_bad_signal:
+ token->status = EFI_ABORTED;
+out_signal:
+ efi_signal_event(token->event);
+out:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * efi_http_poll() - Polls for incoming data packets and processes outgoing data packets
+ *
+ * This function implements EFI_HTTP_PROTOCOL.Poll().
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @token: pointer to storage containing HTTP request token
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_http_poll(struct efi_http_protocol *this)
+{
+ EFI_ENTRY("%p", this);
+
+ efi_status_t ret = EFI_UNSUPPORTED;
+
+ return EFI_EXIT(ret);
+}
+
+/* EFI_HTTP_SERVICE_BINDING_PROTOCOL */
+
+/*
+ * efi_http_service_binding_create_child() - Creates a child handle
+ * and installs a protocol
+ *
+ * This function implements EFI_HTTP_SERVICE_BINDING.CreateChild().
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @child_handle: pointer to child handle
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_http_service_binding_create_child(
+ struct efi_service_binding_protocol *this,
+ efi_handle_t *child_handle)
+{
+ EFI_ENTRY("%p, %p", this, child_handle);
+
+ efi_status_t ret = EFI_SUCCESS;
+ struct efi_http_instance *new_instance;
+
+ if (!child_handle)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ new_instance = calloc(1, sizeof(struct efi_http_instance));
+ if (!new_instance) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto failure_to_add_protocol;
+ }
+
+ if (*child_handle) {
+ new_instance->handle = *child_handle;
+ goto install;
+ }
+
+ new_instance->handle = calloc(1, sizeof(struct efi_object));
+ if (!new_instance->handle) {
+ efi_free_pool((void *)new_instance);
+ ret = EFI_OUT_OF_RESOURCES;
+ goto failure_to_add_protocol;
+ }
+
+ efi_add_handle(new_instance->handle);
+ *child_handle = new_instance->handle;
+
+install:
+ ret = efi_add_protocol(new_instance->handle, &efi_http_guid,
+ &new_instance->http);
+ if (ret != EFI_SUCCESS)
+ goto failure_to_add_protocol;
+
+ new_instance->http.get_mode_data = efi_http_get_mode_data;
+ new_instance->http.configure = efi_http_configure;
+ new_instance->http.request = efi_http_request;
+ new_instance->http.cancel = efi_http_cancel;
+ new_instance->http.response = efi_http_response;
+ new_instance->http.poll = efi_http_poll;
+ ++num_instances;
+
+ return EFI_EXIT(EFI_SUCCESS);
+
+failure_to_add_protocol:
+ return EFI_EXIT(ret);
+}
+
+/*
+ * efi_http_service_binding_destroy_child() - Destroys a child handle with
+ * a protocol installed on it
+ *
+ * This function implements EFI_HTTP_SERVICE_BINDING.DestroyChild().
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @child_handle: child handle
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_http_service_binding_destroy_child(
+ struct efi_service_binding_protocol *this,
+ efi_handle_t child_handle)
+{
+ EFI_ENTRY("%p, %p", this, child_handle);
+ efi_status_t ret = EFI_SUCCESS;
+ struct efi_http_instance *http_instance;
+ struct efi_handler *phandler;
+ void *protocol_interface;
+
+ if (num_instances == 0)
+ return EFI_EXIT(EFI_NOT_FOUND);
+
+ if (!child_handle)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ efi_search_protocol(child_handle, &efi_http_guid, &phandler);
+
+ if (phandler)
+ protocol_interface = phandler->protocol_interface;
+
+ ret = efi_delete_handle(child_handle);
+ if (ret != EFI_SUCCESS)
+ return EFI_EXIT(ret);
+
+ http_instance = (struct efi_http_instance *)protocol_interface;
+ efi_free_pool(http_instance->http_load_addr);
+ http_instance->http_load_addr = NULL;
+
+ free(protocol_interface);
+
+ num_instances--;
+
+ return EFI_EXIT(EFI_SUCCESS);
+}
+
+/**
+ * efi_http_register() - register the http protocol
+ *
+ */
+efi_status_t efi_http_register(const efi_handle_t handle,
+ struct efi_service_binding_protocol *http_service_binding)
+{
+ efi_status_t r = EFI_SUCCESS;
+
+ r = efi_add_protocol(handle, &efi_http_service_binding_guid,
+ http_service_binding);
+ if (r != EFI_SUCCESS)
+ goto failure_to_add_protocol;
+
+ http_service_binding->create_child = efi_http_service_binding_create_child;
+ http_service_binding->destroy_child = efi_http_service_binding_destroy_child;
+
+ return EFI_SUCCESS;
+failure_to_add_protocol:
+ return r;
+}
+
+enum efi_http_status_code efi_u32_to_httpstatus(u32 status)
+{
+ switch (status) {
+ case 100: return HTTP_STATUS_100_CONTINUE;
+ case 101: return HTTP_STATUS_101_SWITCHING_PROTOCOLS;
+ case 200: return HTTP_STATUS_200_OK;
+ case 201: return HTTP_STATUS_201_CREATED;
+ case 202: return HTTP_STATUS_202_ACCEPTED;
+ case 203: return HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION;
+ case 204: return HTTP_STATUS_204_NO_CONTENT;
+ case 205: return HTTP_STATUS_205_RESET_CONTENT;
+ case 206: return HTTP_STATUS_206_PARTIAL_CONTENT;
+ case 300: return HTTP_STATUS_300_MULTIPLE_CHOICES;
+ case 301: return HTTP_STATUS_301_MOVED_PERMANENTLY;
+ case 302: return HTTP_STATUS_302_FOUND;
+ case 303: return HTTP_STATUS_303_SEE_OTHER;
+ case 304: return HTTP_STATUS_304_NOT_MODIFIED;
+ case 305: return HTTP_STATUS_305_USE_PROXY;
+ case 307: return HTTP_STATUS_307_TEMPORARY_REDIRECT;
+ case 400: return HTTP_STATUS_400_BAD_REQUEST;
+ case 401: return HTTP_STATUS_401_UNAUTHORIZED;
+ case 402: return HTTP_STATUS_402_PAYMENT_REQUIRED;
+ case 403: return HTTP_STATUS_403_FORBIDDEN;
+ case 404: return HTTP_STATUS_404_NOT_FOUND;
+ case 405: return HTTP_STATUS_405_METHOD_NOT_ALLOWED;
+ case 406: return HTTP_STATUS_406_NOT_ACCEPTABLE;
+ case 407: return HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED;
+ case 408: return HTTP_STATUS_408_REQUEST_TIME_OUT;
+ case 409: return HTTP_STATUS_409_CONFLICT;
+ case 410: return HTTP_STATUS_410_GONE;
+ case 411: return HTTP_STATUS_411_LENGTH_REQUIRED;
+ case 412: return HTTP_STATUS_412_PRECONDITION_FAILED;
+ case 413: return HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE;
+ case 414: return HTTP_STATUS_414_REQUEST_URI_TOO_LARGE;
+ case 415: return HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE;
+ case 416: return HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED;
+ case 417: return HTTP_STATUS_417_EXPECTATION_FAILED;
+ case 500: return HTTP_STATUS_500_INTERNAL_SERVER_ERROR;
+ case 501: return HTTP_STATUS_501_NOT_IMPLEMENTED;
+ case 502: return HTTP_STATUS_502_BAD_GATEWAY;
+ case 503: return HTTP_STATUS_503_SERVICE_UNAVAILABLE;
+ case 504: return HTTP_STATUS_504_GATEWAY_TIME_OUT;
+ case 505: return HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED;
+ case 308: return HTTP_STATUS_308_PERMANENT_REDIRECT;
+ default: return HTTP_STATUS_UNSUPPORTED_STATUS;
+ }
+}
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
index 0ddf69a..bb58cf1 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -13,6 +13,7 @@
#include <efi_loader.h>
#include <log.h>
#include <malloc.h>
+#include <mapmem.h>
#include <pe.h>
#include <sort.h>
#include <crypto/mscode.h>
@@ -977,7 +978,7 @@
}
/* Flush cache */
- flush_cache((ulong)efi_reloc,
+ flush_cache(map_to_sysmem(efi_reloc),
ALIGN(virt_size, EFI_CACHELINE_SIZE));
/*
diff --git a/lib/efi_loader/efi_ipconfig.c b/lib/efi_loader/efi_ipconfig.c
new file mode 100644
index 0000000..0b247a4
--- /dev/null
+++ b/lib/efi_loader/efi_ipconfig.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Implementation of EFI_IP4_CONFIG2_PROTOCOL
+ *
+ */
+
+#include <efi_loader.h>
+#include <image.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <net.h>
+
+static const efi_guid_t efi_ip4_config2_guid = EFI_IP4_CONFIG2_PROTOCOL_GUID;
+
+struct efi_ip4_config2_manual_address current_http_ip;
+static enum efi_ip4_config2_policy current_policy;
+static char current_mac_addr[32];
+
+/* EFI_IP4_CONFIG2_PROTOCOL */
+
+/*
+ * efi_ip4_config2_set_data() - Set the configuration for the EFI IPv4 network
+ * stack running on the communication device
+ *
+ * This function implements EFI_IP4_CONFIG2_PROTOCOL.SetData()
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @data_type: the type of data to set
+ * @data_size: size of the buffer pointed to by data in bytes
+ * @data: the data buffer to set
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_ip4_config2_set_data(struct efi_ip4_config2_protocol *this,
+ enum efi_ip4_config2_data_type data_type,
+ efi_uintn_t data_size,
+ void *data)
+{
+ EFI_ENTRY("%p, %d, %zu, %p", this, data_type, data_size, data);
+ efi_status_t ret = EFI_SUCCESS;
+
+ if (!this || (data && !data_size) || (!data && data_size))
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ switch (data_type) {
+ case EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO:
+ return EFI_EXIT(EFI_WRITE_PROTECTED);
+ case EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS:
+ if (current_policy != EFI_IP4_CONFIG2_POLICY_STATIC)
+ return EFI_EXIT(EFI_WRITE_PROTECTED);
+ if (!data_size && !data) {
+ memset((void *)¤t_http_ip, 0,
+ sizeof(current_http_ip));
+ return EFI_EXIT(EFI_SUCCESS);
+ }
+ if (data && data_size == sizeof(struct efi_ip4_config2_manual_address)) {
+ memcpy((void *)¤t_http_ip, data,
+ sizeof(struct efi_ip4_config2_manual_address));
+ efi_net_set_addr(¤t_http_ip.address,
+ ¤t_http_ip.subnet_mask, NULL);
+ return EFI_EXIT(EFI_SUCCESS);
+ }
+ return EFI_EXIT(EFI_BAD_BUFFER_SIZE);
+ case EFI_IP4_CONFIG2_DATA_TYPE_POLICY:
+ if (data && data_size == sizeof(enum efi_ip4_config2_policy)) {
+ current_policy = *(enum efi_ip4_config2_policy *)data;
+ return EFI_EXIT(EFI_SUCCESS);
+ }
+ return EFI_EXIT(EFI_BAD_BUFFER_SIZE);
+
+ default:
+ return EFI_EXIT(EFI_UNSUPPORTED);
+ }
+
+ return EFI_EXIT(ret);
+}
+
+/*
+ * efi_ip4_config2_get_data() - Get the configuration for the EFI IPv4 network
+ * stack running on the communication device
+ *
+ * This function implements EFI_IP4_CONFIG2_PROTOCOL.GetData()
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @data_type: the type of data to get
+ * @data_size: size
+ * @data: the data buffer
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_ip4_config2_get_data(struct efi_ip4_config2_protocol *this,
+ enum efi_ip4_config2_data_type data_type,
+ efi_uintn_t *data_size,
+ void *data)
+{
+ EFI_ENTRY("%p, %d, %p, %p", this, data_type, data_size, data);
+
+ efi_status_t ret = EFI_SUCCESS;
+ struct efi_ip4_config2_interface_info *info;
+ int tmp;
+
+ if (!this || !data_size)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ if (*data_size && !data)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ tmp = sizeof(struct efi_ip4_config2_interface_info) + sizeof(struct efi_ip4_route_table);
+
+ switch (data_type) {
+ case EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO:
+ if (*data_size < tmp) {
+ *data_size = tmp;
+ return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+ }
+
+ info = (struct efi_ip4_config2_interface_info *)data;
+ memset(info, 0, sizeof(*info));
+
+ info->hw_address_size = 6;
+ memcpy(info->hw_address.mac_addr, current_mac_addr, 6);
+ // Set the route table size
+
+ info->route_table_size = 0;
+ break;
+ case EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS:
+ if (*data_size < sizeof(struct efi_ip4_config2_manual_address)) {
+ *data_size = sizeof(struct efi_ip4_config2_manual_address);
+ return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+ }
+
+ efi_net_get_addr(¤t_http_ip.address, ¤t_http_ip.subnet_mask, NULL);
+ memcpy(data, (void *)¤t_http_ip,
+ sizeof(struct efi_ip4_config2_manual_address));
+
+ break;
+ default:
+ return EFI_EXIT(EFI_NOT_FOUND);
+ }
+ return EFI_EXIT(ret);
+}
+
+/*
+ * efi_ip4_config2_register_notify() - Register an event that is to be signaled whenever
+ * a configuration process on the specified configuration
+ * data is done
+ *
+ * This function implements EFI_IP4_CONFIG2_PROTOCOL.RegisterDataNotify()
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @data_type: the type of data to register the event for
+ * @event: the event to register
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_ip4_config2_register_notify(struct efi_ip4_config2_protocol *this,
+ enum efi_ip4_config2_data_type data_type,
+ struct efi_event *event)
+{
+ EFI_ENTRY("%p, %d, %p", this, data_type, event);
+
+ return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+/*
+ * efi_ip4_config2_unregister_notify() - Remove a previously registered eventfor
+ * the specified configuration data
+ *
+ * This function implements EFI_IP4_CONFIG2_PROTOCOL.UnregisterDataNotify()
+ * See the Unified Extensible Firmware Interface
+ * (UEFI) specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @data_type: the type of data to remove the event for
+ * @event: the event to unregister
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_ip4_config2_unregister_notify(struct efi_ip4_config2_protocol *this,
+ enum efi_ip4_config2_data_type data_type,
+ struct efi_event *event)
+{
+ EFI_ENTRY("%p, %d, %p", this, data_type, event);
+
+ return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+/**
+ * efi_ipconfig_register() - register the ip4_config2 protocol
+ *
+ */
+efi_status_t efi_ipconfig_register(const efi_handle_t handle,
+ struct efi_ip4_config2_protocol *ip4config)
+{
+ efi_status_t r = EFI_SUCCESS;
+
+ r = efi_add_protocol(handle, &efi_ip4_config2_guid,
+ ip4config);
+ if (r != EFI_SUCCESS) {
+ log_err("ERROR: Failure to add protocol\n");
+ return r;
+ }
+
+ memcpy(current_mac_addr, eth_get_ethaddr(), 6);
+
+ ip4config->set_data = efi_ip4_config2_set_data;
+ ip4config->get_data = efi_ip4_config2_get_data;
+ ip4config->register_data_notify = efi_ip4_config2_register_notify;
+ ip4config->unregister_data_notify = efi_ip4_config2_unregister_notify;
+
+ return EFI_SUCCESS;
+}
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index e493934..edd7da7 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -814,7 +814,16 @@
{
unsigned long runtime_start, runtime_end, runtime_pages;
unsigned long runtime_mask = EFI_PAGE_MASK;
+ unsigned long uboot_start, uboot_pages;
+ unsigned long uboot_stack_size = CONFIG_STACK_SIZE;
+ /* Add U-Boot */
+ uboot_start = ((uintptr_t)map_sysmem(gd->start_addr_sp, 0) -
+ uboot_stack_size) & ~EFI_PAGE_MASK;
+ uboot_pages = ((uintptr_t)map_sysmem(gd->ram_top - 1, 0) -
+ uboot_start + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
+ efi_add_memory_map_pg(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE,
+ false);
#if defined(__aarch64__)
/*
* Runtime Services must be 64KiB aligned according to the
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
index 7cd5367..67593ef 100644
--- a/lib/efi_loader/efi_net.c
+++ b/lib/efi_loader/efi_net.c
@@ -16,7 +16,10 @@
*/
#include <efi_loader.h>
+#include <dm.h>
+#include <linux/sizes.h>
#include <malloc.h>
+#include <vsprintf.h>
#include <net.h>
static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_PROTOCOL_GUID;
@@ -32,6 +35,19 @@
static struct efi_net_obj *netobj;
/*
+ * The current network device path. This device path is updated when a new
+ * bootfile is downloaded from the network. If then the bootfile is loaded
+ * as an efi image, net_dp is passed as the device path of the loaded image.
+ */
+static struct efi_device_path *net_dp;
+
+static struct wget_http_info efi_wget_info = {
+ .set_bootdev = false,
+ .check_buffer_size = true,
+
+};
+
+/*
* The notification function of this event is called in every timer cycle
* to check if a new network packet has been received.
*/
@@ -44,11 +60,13 @@
/**
* struct efi_net_obj - EFI object representing a network interface
*
- * @header: EFI object header
- * @net: simple network protocol interface
- * @net_mode: status of the network interface
- * @pxe: PXE base code protocol interface
- * @pxe_mode: status of the PXE base code protocol
+ * @header: EFI object header
+ * @net: simple network protocol interface
+ * @net_mode: status of the network interface
+ * @pxe: PXE base code protocol interface
+ * @pxe_mode: status of the PXE base code protocol
+ * @ip4_config2: IP4 Config2 protocol interface
+ * @http_service_binding: Http service binding protocol interface
*/
struct efi_net_obj {
struct efi_object header;
@@ -56,6 +74,12 @@
struct efi_simple_network_mode net_mode;
struct efi_pxe_base_code_protocol pxe;
struct efi_pxe_mode pxe_mode;
+#if IS_ENABLED(CONFIG_EFI_IP4_CONFIG2_PROTOCOL)
+ struct efi_ip4_config2_protocol ip4_config2;
+#endif
+#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL)
+ struct efi_service_binding_protocol http_service_binding;
+#endif
};
/*
@@ -901,8 +925,10 @@
&netobj->net);
if (r != EFI_SUCCESS)
goto failure_to_add_protocol;
+ if (!net_dp)
+ efi_net_set_dp("Net", NULL);
r = efi_add_protocol(&netobj->header, &efi_guid_device_path,
- efi_dp_from_eth());
+ net_dp);
if (r != EFI_SUCCESS)
goto failure_to_add_protocol;
r = efi_add_protocol(&netobj->header, &efi_pxe_base_code_protocol_guid,
@@ -981,6 +1007,25 @@
return r;
}
+#if IS_ENABLED(CONFIG_EFI_IP4_CONFIG2_PROTOCOL)
+ r = efi_ipconfig_register(&netobj->header, &netobj->ip4_config2);
+ if (r != EFI_SUCCESS)
+ goto failure_to_add_protocol;
+#endif
+
+#ifdef CONFIG_EFI_HTTP_PROTOCOL
+ r = efi_http_register(&netobj->header, &netobj->http_service_binding);
+ if (r != EFI_SUCCESS)
+ goto failure_to_add_protocol;
+ /*
+ * No harm on doing the following. If the PXE handle is present, the client could
+ * find it and try to get its IP address from it. In here the PXE handle is present
+ * but the PXE protocol is not yet implmenented, so we add this in the meantime.
+ */
+ efi_net_get_addr((struct efi_ipv4_address *)&netobj->pxe_mode.station_ip,
+ (struct efi_ipv4_address *)&netobj->pxe_mode.subnet_mask, NULL);
+#endif
+
return EFI_SUCCESS;
failure_to_add_protocol:
printf("ERROR: Failure to add protocol\n");
@@ -997,3 +1042,317 @@
printf("ERROR: Out of memory\n");
return EFI_OUT_OF_RESOURCES;
}
+
+/**
+ * efi_net_set_dp() - set device path of efi net device
+ *
+ * This gets called to update the device path when a new boot
+ * file is downloaded
+ *
+ * @dev: dev to set the device path from
+ * @server: remote server address
+ * Return: status code
+ */
+efi_status_t efi_net_set_dp(const char *dev, const char *server)
+{
+ efi_free_pool(net_dp);
+
+ net_dp = NULL;
+ if (!strcmp(dev, "Net"))
+ net_dp = efi_dp_from_eth();
+ else if (!strcmp(dev, "Http"))
+ net_dp = efi_dp_from_http(server);
+
+ if (!net_dp)
+ return EFI_OUT_OF_RESOURCES;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ * efi_net_get_dp() - get device path of efi net device
+ *
+ * Produce a copy of the current device path
+ *
+ * @dp: copy of the current device path, or NULL on error
+ */
+void efi_net_get_dp(struct efi_device_path **dp)
+{
+ if (!dp)
+ return;
+ if (!net_dp)
+ efi_net_set_dp("Net", NULL);
+ if (net_dp)
+ *dp = efi_dp_dup(net_dp);
+}
+
+/**
+ * efi_net_get_addr() - get IP address information
+ *
+ * Copy the current IP address, mask, and gateway into the
+ * efi_ipv4_address structs pointed to by ip, mask and gw,
+ * respectively.
+ *
+ * @ip: pointer to an efi_ipv4_address struct to
+ * be filled with the current IP address
+ * @mask: pointer to an efi_ipv4_address struct to
+ * be filled with the current network mask
+ * @gw: pointer to an efi_ipv4_address struct to be
+ * filled with the current network gateway
+ */
+void efi_net_get_addr(struct efi_ipv4_address *ip,
+ struct efi_ipv4_address *mask,
+ struct efi_ipv4_address *gw)
+{
+#ifdef CONFIG_NET_LWIP
+ char ipstr[] = "ipaddr\0\0";
+ char maskstr[] = "netmask\0\0";
+ char gwstr[] = "gatewayip\0\0";
+ int idx;
+ struct in_addr tmp;
+ char *env;
+
+ idx = dev_seq(eth_get_dev());
+
+ if (idx < 0 || idx > 99) {
+ log_err("unexpected idx %d\n", idx);
+ return;
+ }
+
+ if (idx) {
+ sprintf(ipstr, "ipaddr%d", idx);
+ sprintf(maskstr, "netmask%d", idx);
+ sprintf(gwstr, "gatewayip%d", idx);
+ }
+
+ env = env_get(ipstr);
+ if (env && ip) {
+ tmp = string_to_ip(env);
+ memcpy(ip, &tmp, sizeof(tmp));
+ }
+
+ env = env_get(maskstr);
+ if (env && mask) {
+ tmp = string_to_ip(env);
+ memcpy(mask, &tmp, sizeof(tmp));
+ }
+ env = env_get(gwstr);
+ if (env && gw) {
+ tmp = string_to_ip(env);
+ memcpy(gw, &tmp, sizeof(tmp));
+ }
+#else
+ if (ip)
+ memcpy(ip, &net_ip, sizeof(net_ip));
+ if (mask)
+ memcpy(mask, &net_netmask, sizeof(net_netmask));
+#endif
+}
+
+/**
+ * efi_net_set_addr() - set IP address information
+ *
+ * Set the current IP address, mask, and gateway to the
+ * efi_ipv4_address structs pointed to by ip, mask and gw,
+ * respectively.
+ *
+ * @ip: pointer to new IP address
+ * @mask: pointer to new network mask to set
+ * @gw: pointer to new network gateway
+ */
+void efi_net_set_addr(struct efi_ipv4_address *ip,
+ struct efi_ipv4_address *mask,
+ struct efi_ipv4_address *gw)
+{
+#ifdef CONFIG_NET_LWIP
+ char ipstr[] = "ipaddr\0\0";
+ char maskstr[] = "netmask\0\0";
+ char gwstr[] = "gatewayip\0\0";
+ int idx;
+ struct in_addr *addr;
+ char tmp[46];
+
+ idx = dev_seq(eth_get_dev());
+
+ if (idx < 0 || idx > 99) {
+ log_err("unexpected idx %d\n", idx);
+ return;
+ }
+
+ if (idx) {
+ sprintf(ipstr, "ipaddr%d", idx);
+ sprintf(maskstr, "netmask%d", idx);
+ sprintf(gwstr, "gatewayip%d", idx);
+ }
+
+ if (ip) {
+ addr = (struct in_addr *)ip;
+ ip_to_string(*addr, tmp);
+ env_set(ipstr, tmp);
+ }
+
+ if (mask) {
+ addr = (struct in_addr *)mask;
+ ip_to_string(*addr, tmp);
+ env_set(maskstr, tmp);
+ }
+
+ if (gw) {
+ addr = (struct in_addr *)gw;
+ ip_to_string(*addr, tmp);
+ env_set(gwstr, tmp);
+ }
+#else
+ if (ip)
+ memcpy(&net_ip, ip, sizeof(*ip));
+ if (mask)
+ memcpy(&net_netmask, mask, sizeof(*mask));
+#endif
+}
+
+/**
+ * efi_net_set_buffer() - allocate a buffer of min 64K
+ *
+ * @buffer: allocated buffer
+ * @size: desired buffer size
+ * Return: status code
+ */
+static efi_status_t efi_net_set_buffer(void **buffer, size_t size)
+{
+ efi_status_t ret = EFI_SUCCESS;
+
+ if (size < SZ_64K)
+ size = SZ_64K;
+
+ *buffer = efi_alloc(size);
+ if (!*buffer)
+ ret = EFI_OUT_OF_RESOURCES;
+
+ efi_wget_info.buffer_size = (ulong)size;
+
+ return ret;
+}
+
+/**
+ * efi_net_parse_headers() - parse HTTP headers
+ *
+ * Parses the raw buffer efi_wget_info.headers into an array headers
+ * of efi structs http_headers. The array should be at least
+ * MAX_HTTP_HEADERS long.
+ *
+ * @num_headers: number of headers
+ * @headers: caller provided array of struct http_headers
+ */
+void efi_net_parse_headers(ulong *num_headers, struct http_header *headers)
+{
+ if (!num_headers || !headers)
+ return;
+
+ // Populate info with http headers.
+ *num_headers = 0;
+ const uchar *line_start = efi_wget_info.headers;
+ const uchar *line_end;
+ ulong count;
+ struct http_header *current_header;
+ const uchar *separator;
+ size_t name_length, value_length;
+
+ // Skip the first line (request or status line)
+ line_end = strstr(line_start, "\r\n");
+
+ if (line_end)
+ line_start = line_end + 2;
+
+ while ((line_end = strstr(line_start, "\r\n")) != NULL) {
+ count = *num_headers;
+ if (line_start == line_end || count >= MAX_HTTP_HEADERS)
+ break;
+ current_header = headers + count;
+ separator = strchr(line_start, ':');
+ if (separator) {
+ name_length = separator - line_start;
+ ++separator;
+ while (*separator == ' ')
+ ++separator;
+ value_length = line_end - separator;
+ if (name_length < MAX_HTTP_HEADER_NAME &&
+ value_length < MAX_HTTP_HEADER_VALUE) {
+ strncpy(current_header->name, line_start, name_length);
+ current_header->name[name_length] = '\0';
+ strncpy(current_header->value, separator, value_length);
+ current_header->value[value_length] = '\0';
+ (*num_headers)++;
+ }
+ }
+ line_start = line_end + 2;
+ }
+}
+
+/**
+ * efi_net_do_request() - issue an HTTP request using wget
+ *
+ * @url: url
+ * @method: HTTP method
+ * @buffer: data buffer
+ * @status_code: HTTP status code
+ * @file_size: file size in bytes
+ * @headers_buffer: headers buffer
+ * Return: status code
+ */
+efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer,
+ u32 *status_code, ulong *file_size, char *headers_buffer)
+{
+ efi_status_t ret = EFI_SUCCESS;
+ int wget_ret;
+ static bool last_head;
+
+ if (!buffer || !file_size)
+ return EFI_ABORTED;
+
+ efi_wget_info.method = (enum wget_http_method)method;
+ efi_wget_info.headers = headers_buffer;
+
+ switch (method) {
+ case HTTP_METHOD_GET:
+ ret = efi_net_set_buffer(buffer, last_head ? (size_t)efi_wget_info.hdr_cont_len : 0);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ wget_ret = wget_request((ulong)*buffer, url, &efi_wget_info);
+ if ((ulong)efi_wget_info.hdr_cont_len > efi_wget_info.buffer_size) {
+ // Try again with updated buffer size
+ efi_free_pool(*buffer);
+ ret = efi_net_set_buffer(buffer, (size_t)efi_wget_info.hdr_cont_len);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ if (wget_request((ulong)*buffer, url, &efi_wget_info)) {
+ efi_free_pool(*buffer);
+ ret = EFI_DEVICE_ERROR;
+ goto out;
+ }
+ } else if (wget_ret) {
+ efi_free_pool(*buffer);
+ ret = EFI_DEVICE_ERROR;
+ goto out;
+ }
+ // Pass the actual number of received bytes to the application
+ *file_size = efi_wget_info.file_size;
+ *status_code = efi_wget_info.status_code;
+ last_head = false;
+ break;
+ case HTTP_METHOD_HEAD:
+ ret = efi_net_set_buffer(buffer, 0);
+ if (ret != EFI_SUCCESS)
+ goto out;
+ wget_request((ulong)*buffer, url, &efi_wget_info);
+ *file_size = 0;
+ *status_code = efi_wget_info.status_code;
+ last_head = true;
+ break;
+ default:
+ ret = EFI_UNSUPPORTED;
+ break;
+ }
+
+out:
+ return ret;
+}
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index 4147018..17fbfad 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -52,6 +52,8 @@
obj-$(CONFIG_EFI_ECPT) += efi_selftest_ecpt.o
obj-$(CONFIG_NETDEVICES) += efi_selftest_snp.o
+obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_http.o
+obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_ipconfig.o
obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_selftest_devicepath.o
obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += \
diff --git a/lib/efi_selftest/efi_selftest_http.c b/lib/efi_selftest/efi_selftest_http.c
new file mode 100644
index 0000000..b63c401
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_http.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * efi_selftest_http
+ *
+ * This unit test covers the IPv4 Config2 Protocol, Http Service Binding Protocol,
+ * and Http Protocol.
+ *
+ * An Http HEAD and an Http GET request are sent to the same destination. The test
+ * is successful if the HEAD request gets a response with a valid Content-Length header
+ * and the subsequent GET request receives the amount of bytes informed by the previous
+ * Content-Length header.
+ *
+ */
+
+#include <efi_selftest.h>
+#include <charset.h>
+#include <net.h>
+
+static struct efi_boot_services *boottime;
+
+static struct efi_http_protocol *http;
+static struct efi_service_binding_protocol *http_service;
+static struct efi_ip4_config2_protocol *ip4_config2;
+static efi_handle_t http_protocol_handle;
+
+static const efi_guid_t efi_http_guid = EFI_HTTP_PROTOCOL_GUID;
+static const efi_guid_t efi_http_service_binding_guid = EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID;
+static const efi_guid_t efi_ip4_config2_guid = EFI_IP4_CONFIG2_PROTOCOL_GUID;
+static int callback_done;
+
+/*
+ * Setup unit test.
+ *
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * Return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+ efi_handle_t *net_handle;
+ efi_uintn_t num_handles;
+ efi_handle_t *handles;
+ struct efi_http_config_data http_config;
+ struct efi_httpv4_access_point ipv4_node;
+
+ boottime = systable->boottime;
+
+ num_handles = 0;
+ boottime->locate_handle_buffer(BY_PROTOCOL, &efi_ip4_config2_guid,
+ NULL, &num_handles, &handles);
+
+ if (!num_handles) {
+ efi_st_error("Failed to locate ipv4 config2 protocol\n");
+ return EFI_ST_FAILURE;
+ }
+
+ for (net_handle = handles; num_handles--; net_handle++) {
+ ret = boottime->open_protocol(*net_handle, &efi_ip4_config2_guid,
+ (void **)&ip4_config2, 0, 0,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS || !ip4_config2)
+ continue;
+ ret = boottime->open_protocol(*net_handle,
+ &efi_http_service_binding_guid,
+ (void **)&http_service, 0, 0,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS || !http_service)
+ continue;
+ break; // Get first handle that supports both protocols
+ }
+
+ if (!ip4_config2 || !http_service) {
+ efi_st_error("Failed to open ipv4 config2 or http service binding protocol\n");
+ return EFI_ST_FAILURE;
+ }
+
+ http_protocol_handle = NULL;
+ ret = http_service->create_child(http_service, &http_protocol_handle);
+ if (ret != EFI_SUCCESS || !http_protocol_handle) {
+ efi_st_error("Failed to create an http service instance\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->open_protocol(http_protocol_handle, &efi_http_guid,
+ (void **)&http, 0, 0, EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS || !http) {
+ efi_st_error("Failed to open http protocol\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("HTTP Service Binding: child created successfully\n");
+
+ http_config.http_version = HTTPVERSION11;
+ http_config.is_ipv6 = false;
+ http_config.access_point.ipv4_node = &ipv4_node;
+ ipv4_node.use_default_address = true;
+
+ ret = http->configure(http, &http_config);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to configure http instance\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+void EFIAPI efi_test_http_callback(struct efi_event *event, void *context)
+{
+ callback_done = 1;
+}
+
+/*
+ * Execute unit test.
+ *
+ *
+ * Return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ struct efi_http_request_data request_data;
+ struct efi_http_message request_message;
+ struct efi_http_token request_token;
+ struct efi_http_response_data response_data;
+ struct efi_http_message response_message;
+ struct efi_http_token response_token;
+ enum efi_http_status_code status_code;
+ void *response_buffer;
+ efi_uintn_t len, sum;
+ char *url = "http://example.com/";
+ u16 url_16[64];
+ u16 *tmp;
+
+ /* Setup may have failed */
+ if (!ip4_config2 || !http) {
+ efi_st_error("Cannot proceed with test after setup failure\n");
+ return EFI_ST_FAILURE;
+ }
+
+ tmp = url_16;
+ utf8_utf16_strcpy(&tmp, url);
+ request_data.url = url_16;
+ request_data.method = HTTP_METHOD_GET;
+
+ request_message.data.request = &request_data;
+ request_message.header_count = 3;
+ request_message.body_length = 0;
+ request_message.body = NULL;
+
+ /* request token */
+ request_token.event = NULL;
+ request_token.status = EFI_NOT_READY;
+ request_token.message = &request_message;
+ callback_done = 0;
+ ret = boottime->create_event(EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ efi_test_http_callback,
+ NULL,
+ &request_token.event);
+
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to create request event\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = http->request(http, &request_token);
+
+ if (ret != EFI_SUCCESS) {
+ boottime->close_event(request_token.event);
+ efi_st_printf("Failed to proceed with the http request\n");
+ return EFI_ST_SUCCESS;
+ }
+
+ while (!callback_done)
+ http->poll(http);
+
+ response_data.status_code = HTTP_STATUS_UNSUPPORTED_STATUS;
+ response_message.data.response = &response_data;
+ response_message.header_count = 0;
+ response_message.headers = NULL;
+ response_message.body_length = 0;
+ response_message.body = NULL;
+ response_token.event = NULL;
+
+ ret = boottime->create_event(EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ efi_test_http_callback,
+ NULL,
+ &response_token.event);
+
+ if (ret != EFI_SUCCESS) {
+ boottime->close_event(request_token.event);
+ efi_st_error("Failed to create response event\n");
+ return EFI_ST_FAILURE;
+ }
+
+ response_token.status = EFI_SUCCESS;
+ response_token.message = &response_message;
+
+ callback_done = 0;
+ ret = http->response(http, &response_token);
+
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed http first response\n");
+ goto fail;
+ }
+
+ while (!callback_done)
+ http->poll(http);
+
+ if (response_message.data.response->status_code != HTTP_STATUS_200_OK) {
+ status_code = response_message.data.response->status_code;
+ if (status_code == HTTP_STATUS_404_NOT_FOUND) {
+ efi_st_error("File not found\n");
+ } else {
+ efi_st_error("Bad http status %d\n",
+ response_message.data.response->status_code);
+ }
+ goto fail_free_hdr;
+ }
+
+ ret = boottime->allocate_pool(EFI_LOADER_CODE, response_message.body_length,
+ &response_buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed allocating response buffer\n");
+ goto fail_free_hdr;
+ }
+
+ len = response_message.body_length;
+ sum = 0;
+ while (len) {
+ response_message.data.response = NULL;
+ response_message.header_count = 0;
+ response_message.headers = NULL;
+ response_message.body_length = len;
+ response_message.body = response_buffer + sum;
+
+ response_token.message = &response_message;
+ response_token.status = EFI_NOT_READY;
+
+ callback_done = 0;
+ ret = http->response(http, &response_token);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed http second response\n");
+ goto fail_free_buf;
+ }
+
+ while (!callback_done)
+ http->poll(http);
+
+ if (!response_message.body_length)
+ break;
+
+ len -= response_message.body_length;
+ sum += response_message.body_length;
+ }
+
+ if (len)
+ goto fail_free_buf;
+
+ boottime->free_pool(response_buffer);
+ if (response_message.headers)
+ boottime->free_pool(response_message.headers);
+ boottime->close_event(request_token.event);
+ boottime->close_event(response_token.event);
+ efi_st_printf("Efi Http request executed successfully\n");
+ return EFI_ST_SUCCESS;
+
+fail_free_buf:
+ boottime->free_pool(response_buffer);
+fail_free_hdr:
+ if (response_message.headers)
+ boottime->free_pool(response_message.headers);
+fail:
+ boottime->close_event(request_token.event);
+ boottime->close_event(response_token.event);
+ return EFI_ST_FAILURE;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * Return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t ret;
+ int exit_status = EFI_ST_SUCCESS;
+
+ if (!http_service || !http_protocol_handle) {
+ efi_st_error("No handles to destroy http instance");
+ exit_status = EFI_ST_FAILURE;
+ } else {
+ ret = http_service->destroy_child(http_service, http_protocol_handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to destroy http instance");
+ exit_status = EFI_ST_FAILURE;
+ }
+ efi_st_printf("HTTP Service Binding: child destroyed successfully\n");
+ }
+
+ return exit_status;
+}
+
+EFI_UNIT_TEST(http) = {
+ .name = "http protocol",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+#ifdef CONFIG_SANDBOX
+ /*
+ * Running this test on the sandbox requires setting environment
+ * variable ethact to a network interface connected to a DHCP server and
+ * ethrotate to 'no'.
+ */
+ .on_request = true,
+#endif
+};
diff --git a/lib/efi_selftest/efi_selftest_ipconfig.c b/lib/efi_selftest/efi_selftest_ipconfig.c
new file mode 100644
index 0000000..8d594f5
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_ipconfig.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * efi_selftest_ipconfig
+ *
+ * This unit test covers the IPv4 Config2 Protocol.
+ *
+ */
+
+#include <efi_selftest.h>
+#include <charset.h>
+#include <net.h>
+
+static struct efi_boot_services *boottime;
+
+static struct efi_ip4_config2_protocol *ip4_config2;
+static const efi_guid_t efi_ip4_config2_guid = EFI_IP4_CONFIG2_PROTOCOL_GUID;
+
+/*
+ * Setup unit test.
+ *
+ * Open IPv4 Config2 protocol
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * Return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+ efi_handle_t *net_handle;
+ efi_uintn_t num_handles;
+ efi_handle_t *handles;
+
+ boottime = systable->boottime;
+
+ num_handles = 0;
+ boottime->locate_handle_buffer(BY_PROTOCOL, &efi_ip4_config2_guid,
+ NULL, &num_handles, &handles);
+
+ if (!num_handles) {
+ efi_st_error("Failed to locate ipv4 config2 protocol\n");
+ return EFI_ST_FAILURE;
+ }
+
+ for (net_handle = handles; num_handles--; net_handle++) {
+ ret = boottime->open_protocol(*net_handle, &efi_ip4_config2_guid,
+ (void **)&ip4_config2, 0, 0,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS || !ip4_config2)
+ continue;
+ break; // Get first handle that supports ipv4
+ }
+
+ if (!ip4_config2) {
+ efi_st_error("Failed to open ipv4 config2 protocol\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ *
+ * Return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ enum efi_ip4_config2_policy policy;
+ efi_uintn_t data_size;
+ struct efi_ip4_config2_manual_address manual_address;
+ struct efi_ip4_config2_manual_address orig_address;
+ u8 netmask[] = {255, 255, 255, 0};
+ u8 ip[] = {10, 0, 0, 1};
+
+ /* Setup may have failed */
+ if (!ip4_config2) {
+ efi_st_error("Setup failure, cannot proceed with test\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Set policy to static */
+ policy = EFI_IP4_CONFIG2_POLICY_STATIC;
+ ret = ip4_config2->set_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_POLICY,
+ sizeof(policy), (void *)&policy);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to set policy\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Save original ip address and netmask */
+ data_size = sizeof(manual_address);
+ ret = ip4_config2->get_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS,
+ &data_size, &orig_address);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to save original ip address and netmask\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Set static ip and netmask */
+ memcpy(&manual_address.address, ip,
+ sizeof(struct efi_ipv4_address));
+ memcpy(&manual_address.subnet_mask, netmask,
+ sizeof(struct efi_ipv4_address));
+ ret = ip4_config2->set_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS,
+ sizeof(manual_address), &manual_address);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to get ip address and netmask\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Try to set interface info, this should fail */
+ ret = ip4_config2->set_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO, 0, NULL);
+ if (ret == EFI_SUCCESS) {
+ efi_st_error("Interface info is read-only\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Get ip address and netmask and check that they match with the previously set ones */
+ data_size = sizeof(manual_address);
+ ret = ip4_config2->get_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS,
+ &data_size, &manual_address);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to get ip address and netmask\n");
+ return EFI_ST_FAILURE;
+ }
+ if (memcmp(ip, &manual_address.address,
+ sizeof(struct efi_ipv4_address)) ||
+ memcmp(netmask, &manual_address.subnet_mask,
+ sizeof(struct efi_ipv4_address))) {
+ efi_st_error("Ip address mismatch\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Restore original ip address and netmask */
+ ret = ip4_config2->set_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS,
+ sizeof(orig_address), &orig_address);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to restore original ip address and netmask\n");
+ return EFI_ST_FAILURE;
+ }
+
+ efi_st_printf("Efi ipconfig test execute succeeded\n");
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * Return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ int exit_status = EFI_ST_SUCCESS;
+
+ return exit_status;
+}
+
+EFI_UNIT_TEST(ipconfig) = {
+ .name = "IPv4 config2 protocol",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+#ifdef CONFIG_SANDBOX
+ /*
+ * Running this test on the sandbox requires setting environment
+ * variable ethact to a network interface connected to a DHCP server and
+ * ethrotate to 'no'.
+ */
+ .on_request = true,
+#endif
+};
diff --git a/lib/hashtable.c b/lib/hashtable.c
index e8a59e2..75c263b 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -221,11 +221,32 @@
do_callback(const struct env_entry *e, const char *name, const char *value,
enum env_op op, int flags)
{
+ int ret = 0;
+
#ifndef CONFIG_XPL_BUILD
- if (e->callback)
- return e->callback(name, value, op, flags);
+ static bool in_callback;
+
+ if (!e->callback || in_callback)
+ return 0;
+
+ /*
+ * In case there are two variables which each implement env callback
+ * that performs env_set() on the other variable, the callbacks will
+ * call each other recursively until the stack runs out. Prevent such
+ * a recursion from happening.
+ *
+ * Example which triggers this behavior:
+ * static int on_foo(...) { env_set("bar", 0); ... }
+ * static int on_bar(...) { env_set("foo", 0); ... }
+ * U_BOOT_ENV_CALLBACK(foo, on_foo);
+ * U_BOOT_ENV_CALLBACK(bar, on_bar);
+ */
+ in_callback = true;
+ ret = e->callback(name, value, op, flags);
+ in_callback = false;
#endif
- return 0;
+
+ return ret;
}
/*
diff --git a/lib/lmb.c b/lib/lmb.c
index 14b9b84..b03237b 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -201,15 +201,6 @@
phys_addr_t rgnbase = rgn[i].base;
phys_size_t rgnsize = rgn[i].size;
phys_size_t rgnflags = rgn[i].flags;
- phys_addr_t end = base + size - 1;
- phys_addr_t rgnend = rgnbase + rgnsize - 1;
- if (rgnbase <= base && end <= rgnend) {
- if (flags == rgnflags)
- /* Already have this region, so we're done */
- return 0;
- else
- return -1; /* regions with new flags */
- }
ret = lmb_addrs_adjacent(base, size, rgnbase, rgnsize);
if (ret > 0) {
@@ -615,6 +606,7 @@
void lmb_add_memory(void)
{
int i;
+ phys_addr_t bank_end;
phys_size_t size;
u64 ram_top = gd->ram_top;
struct bd_info *bd = gd->bd;
@@ -628,6 +620,8 @@
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
size = bd->bi_dram[i].size;
+ bank_end = bd->bi_dram[i].start + size;
+
if (size) {
lmb_add(bd->bi_dram[i].start, size);
@@ -639,6 +633,9 @@
if (bd->bi_dram[i].start >= ram_top)
lmb_reserve_flags(bd->bi_dram[i].start, size,
LMB_NOOVERWRITE);
+ else if (bank_end > ram_top)
+ lmb_reserve_flags(ram_top, bank_end - ram_top,
+ LMB_NOOVERWRITE);
}
}
}
diff --git a/lib/lwip/Makefile b/lib/lwip/Makefile
index 19e5c68..fe2b64c 100644
--- a/lib/lwip/Makefile
+++ b/lib/lwip/Makefile
@@ -54,5 +54,5 @@
lwip/src/core/udp.o \
lwip/src/netif/ethernet.o
-obj-$(CONFIG_MBEDTLS_LIB_TLS) += lwip/src/apps/altcp_tls/altcp_tls_mbedtls.o \
+obj-$(CONFIG_$(XPL_)MBEDTLS_LIB_TLS) += lwip/src/apps/altcp_tls/altcp_tls_mbedtls.o \
lwip/src/apps/altcp_tls/altcp_tls_mbedtls_mem.o
diff --git a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c
index 6643b05..4642158 100644
--- a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c
+++ b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c
@@ -692,7 +692,9 @@
if (session && conn && conn->state) {
altcp_mbedtls_state_t *state = (altcp_mbedtls_state_t *)conn->state;
int ret = -1;
+#ifdef MBEDTLS_HAVE_TIME
if (session->data.MBEDTLS_PRIVATE(start))
+#endif
ret = mbedtls_ssl_set_session(&state->ssl_context, &session->data);
return ret < 0 ? ERR_VAL : ERR_OK;
}
diff --git a/lib/lwip/u-boot/lwipopts.h b/lib/lwip/u-boot/lwipopts.h
index 88d6faf..edac74f 100644
--- a/lib/lwip/u-boot/lwipopts.h
+++ b/lib/lwip/u-boot/lwipopts.h
@@ -5,6 +5,8 @@
#ifndef LWIP_UBOOT_LWIPOPTS_H
#define LWIP_UBOOT_LWIPOPTS_H
+#include <linux/kconfig.h>
+
#if defined(CONFIG_LWIP_DEBUG)
#define LWIP_DEBUG 1
#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL
@@ -154,7 +156,7 @@
#define MEMP_MEM_INIT 1
#define MEM_LIBC_MALLOC 1
-#if defined(CONFIG_MBEDTLS_LIB_TLS)
+#if CONFIG_IS_ENABLED(MBEDTLS_LIB_TLS)
#define LWIP_ALTCP 1
#define LWIP_ALTCP_TLS 1
#define LWIP_ALTCP_TLS_MBEDTLS 1
diff --git a/lib/mbedtls/mbedtls_def_config.h b/lib/mbedtls/mbedtls_def_config.h
index d27f017..1d2314e 100644
--- a/lib/mbedtls/mbedtls_def_config.h
+++ b/lib/mbedtls/mbedtls_def_config.h
@@ -92,9 +92,6 @@
/* Generic options */
#define MBEDTLS_ENTROPY_HARDWARE_ALT
-#define MBEDTLS_HAVE_TIME
-#define MBEDTLS_PLATFORM_MS_TIME_ALT
-#define MBEDTLS_PLATFORM_TIME_MACRO rtc_mktime
#define MBEDTLS_PLATFORM_C
#define MBEDTLS_SSL_CLI_C
#define MBEDTLS_SSL_TLS_C
diff --git a/lib/md5.c b/lib/md5.c
index 2d8977b..e3eab8a 100644
--- a/lib/md5.c
+++ b/lib/md5.c
@@ -272,14 +272,16 @@
unsigned int chunk_sz)
{
MD5Context context;
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
const unsigned char *end, *curr;
int chunk;
#endif
MD5Init(&context);
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
curr = input;
end = input + len;
while (curr < end) {
diff --git a/lib/net_utils.c b/lib/net_utils.c
index c70fef0..621f651 100644
--- a/lib/net_utils.c
+++ b/lib/net_utils.c
@@ -152,6 +152,17 @@
}
#endif
+void ip_to_string(struct in_addr x, char *s)
+{
+ x.s_addr = ntohl(x.s_addr);
+ sprintf(s, "%d.%d.%d.%d",
+ (int) ((x.s_addr >> 24) & 0xff),
+ (int) ((x.s_addr >> 16) & 0xff),
+ (int) ((x.s_addr >> 8) & 0xff),
+ (int) ((x.s_addr >> 0) & 0xff)
+ );
+}
+
void string_to_enetaddr(const char *addr, uint8_t *enetaddr)
{
char *end;
diff --git a/lib/sha1.c b/lib/sha1.c
index a9d6497..be502c6 100644
--- a/lib/sha1.c
+++ b/lib/sha1.c
@@ -312,14 +312,16 @@
unsigned char *output, unsigned int chunk_sz)
{
sha1_context ctx;
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
const unsigned char *end, *curr;
int chunk;
#endif
sha1_starts (&ctx);
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
curr = input;
end = input + ilen;
while (curr < end) {
diff --git a/lib/sha256.c b/lib/sha256.c
index 329802f..fb195d9 100644
--- a/lib/sha256.c
+++ b/lib/sha256.c
@@ -273,7 +273,8 @@
unsigned char *output, unsigned int chunk_sz)
{
sha256_context ctx;
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
const unsigned char *end;
unsigned char *curr;
int chunk;
@@ -281,7 +282,8 @@
sha256_starts(&ctx);
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
curr = (unsigned char *)input;
end = input + ilen;
while (curr < end) {
diff --git a/lib/sha512.c b/lib/sha512.c
index ea555ff..0e75c1a 100644
--- a/lib/sha512.c
+++ b/lib/sha512.c
@@ -288,7 +288,8 @@
unsigned char *output, unsigned int chunk_sz)
{
sha512_context ctx;
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
const unsigned char *end;
unsigned char *curr;
int chunk;
@@ -296,7 +297,8 @@
sha384_starts(&ctx);
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
curr = (unsigned char *)input;
end = input + ilen;
while (curr < end) {
@@ -351,7 +353,8 @@
unsigned char *output, unsigned int chunk_sz)
{
sha512_context ctx;
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
const unsigned char *end;
unsigned char *curr;
int chunk;
@@ -359,7 +362,8 @@
sha512_starts(&ctx);
-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#if !defined(USE_HOSTCC) && \
+ (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG))
curr = (unsigned char *)input;
end = input + ilen;
while (curr < end) {
diff --git a/lib/smbios.c b/lib/smbios.c
index 7c24ea1..a36d4b4 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -270,7 +270,7 @@
static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop,
const char *dval)
{
- return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE, dval);
+ return smbios_add_prop_si(ctx, prop, SYSID_NONE, dval);
}
static void smbios_set_eos(struct smbios_ctx *ctx, char *eos)
@@ -393,27 +393,27 @@
fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
smbios_set_eos(ctx, t->eos);
t->manufacturer = smbios_add_prop_si(ctx, "manufacturer",
- SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER,
+ SYSID_SM_SYSTEM_MANUFACTURER,
NULL);
t->product_name = smbios_add_prop_si(ctx, "product",
- SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT,
+ SYSID_SM_SYSTEM_PRODUCT,
NULL);
t->version = smbios_add_prop_si(ctx, "version",
- SYSINFO_ID_SMBIOS_SYSTEM_VERSION,
+ SYSID_SM_SYSTEM_VERSION,
NULL);
if (serial_str) {
t->serial_number = smbios_add_prop(ctx, NULL, serial_str);
strncpy((char *)t->uuid, serial_str, sizeof(t->uuid));
} else {
t->serial_number = smbios_add_prop_si(ctx, "serial",
- SYSINFO_ID_SMBIOS_SYSTEM_SERIAL,
+ SYSID_SM_SYSTEM_SERIAL,
NULL);
}
t->wakeup_type = SMBIOS_WAKEUP_TYPE_UNKNOWN;
t->sku_number = smbios_add_prop_si(ctx, "sku",
- SYSINFO_ID_SMBIOS_SYSTEM_SKU, NULL);
+ SYSID_SM_SYSTEM_SKU, NULL);
t->family = smbios_add_prop_si(ctx, "family",
- SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, NULL);
+ SYSID_SM_SYSTEM_FAMILY, NULL);
len = t->length + smbios_string_table_len(ctx);
*current += len;
@@ -433,20 +433,20 @@
fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
smbios_set_eos(ctx, t->eos);
t->manufacturer = smbios_add_prop_si(ctx, "manufacturer",
- SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER,
+ SYSID_SM_BASEBOARD_MANUFACTURER,
NULL);
t->product_name = smbios_add_prop_si(ctx, "product",
- SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT,
+ SYSID_SM_BASEBOARD_PRODUCT,
NULL);
t->version = smbios_add_prop_si(ctx, "version",
- SYSINFO_ID_SMBIOS_BASEBOARD_VERSION,
+ SYSID_SM_BASEBOARD_VERSION,
NULL);
t->serial_number = smbios_add_prop_si(ctx, "serial",
- SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL,
+ SYSID_SM_BASEBOARD_SERIAL,
NULL);
t->asset_tag_number = smbios_add_prop_si(ctx, "asset-tag",
- SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG,
+ SYSID_SM_BASEBOARD_ASSET_TAG,
NULL);
t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
t->board_type = SMBIOS_BOARD_MOTHERBOARD;
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index cc1dfe6..0503c17 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -312,7 +312,7 @@
*info->bf = 0;
info->bf = p;
- while (*info->bf++ && width > 0)
+ while (width > 0 && info->bf && *info->bf++)
width--;
while (width-- > 0)
info->putc(info, lz ? '0' : ' ');
diff --git a/lib/uuid.c b/lib/uuid.c
index 538a1ba..97388f5 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -175,6 +175,20 @@
"Firmware Management",
EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GUID
},
+#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL)
+ {
+ "HTTP",
+ EFI_HTTP_PROTOCOL_GUID,
+ },
+ {
+ "HTTP Service Binding",
+ EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID,
+ },
+ {
+ "IPv4 Config2",
+ EFI_IP4_CONFIG2_PROTOCOL_GUID,
+ },
+#endif
/* Configuration table GUIDs */
{
"ACPI table",
diff --git a/net/Kconfig b/net/Kconfig
index 76ab7d9..b4bb68d 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -244,6 +244,15 @@
generated. It will be saved to the appropriate environment variable,
too.
+config WGET
+ bool "Enable wget"
+ select PROT_TCP if NET
+ select PROT_TCP_LWIP if NET_LWIP
+ select PROT_DNS_LWIP if NET_LWIP
+ help
+ Selecting this will enable wget, an interface to send HTTP requests
+ via the network stack.
+
config TFTP_BLOCKSIZE
int "TFTP block size"
default 1468
diff --git a/net/Makefile b/net/Makefile
index 209377a..7c917b3 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -29,7 +29,7 @@
obj-$(CONFIG_CMD_WOL) += wol.o
obj-$(CONFIG_PROT_UDP) += udp.o
obj-$(CONFIG_PROT_TCP) += tcp.o
-obj-$(CONFIG_CMD_WGET) += wget.o
+obj-$(CONFIG_WGET) += wget.o
# Disable this warning as it is triggered by:
# sprintf(buf, index ? "foo%d" : "foo", index)
diff --git a/net/lwip/Makefile b/net/lwip/Makefile
index f2558f8..79dd6b3 100644
--- a/net/lwip/Makefile
+++ b/net/lwip/Makefile
@@ -5,4 +5,4 @@
obj-$(CONFIG_CMD_DNS) += dns.o
obj-$(CONFIG_CMD_PING) += ping.o
obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
-obj-$(CONFIG_CMD_WGET) += wget.o
+obj-$(CONFIG_WGET) += wget.o
diff --git a/net/lwip/wget.c b/net/lwip/wget.c
index 062aa7c..b76f6c0 100644
--- a/net/lwip/wget.c
+++ b/net/lwip/wget.c
@@ -27,6 +27,8 @@
};
struct wget_ctx {
+ char server_name[SERVER_NAME_SIZE];
+ u16 port;
char *path;
ulong daddr;
ulong saved_daddr;
@@ -36,6 +38,23 @@
enum done_state done;
};
+static void wget_lwip_fill_info(struct pbuf *hdr, u16_t hdr_len, u32_t hdr_cont_len)
+{
+ if (wget_info->headers) {
+ if (hdr_len < MAX_HTTP_HEADERS_SIZE)
+ pbuf_copy_partial(hdr, (void *)wget_info->headers, hdr_len, 0);
+ else
+ hdr_len = 0;
+ wget_info->headers[hdr_len] = 0;
+ }
+ wget_info->hdr_cont_len = (u32)hdr_cont_len;
+}
+
+static void wget_lwip_set_file_size(u32_t rx_content_len)
+{
+ wget_info->file_size = (ulong)rx_content_len;
+}
+
bool wget_validate_uri(char *uri);
int mbedtls_hardware_poll(void *data, unsigned char *output, size_t len,
@@ -161,7 +180,7 @@
if (rem < n)
return -1;
- strlcpy(p, server, n);
+ strncpy(p, server, n);
p += n;
rem -= n;
if (rem < 1)
@@ -172,7 +191,7 @@
n = strlen(path);
if (rem < n)
return -1;
- strlcpy(p, path, n);
+ strncpy(p, path, n);
p += n;
rem -= n;
if (rem < 1)
@@ -215,6 +234,13 @@
struct wget_ctx *ctx = arg;
ulong elapsed;
+ wget_info->status_code = (u32)srv_res;
+
+ if (err == ERR_BUF) {
+ ctx->done = FAILURE;
+ return;
+ }
+
if (httpc_result != HTTPC_RESULT_OK) {
log_err("\nHTTP client error %d\n", httpc_result);
ctx->done = FAILURE;
@@ -234,8 +260,10 @@
printf("%u bytes transferred in %lu ms (", rx_content_len, elapsed);
print_size(rx_content_len / elapsed * 1000, "/s)\n");
printf("Bytes transferred = %lu (%lx hex)\n", ctx->size, ctx->size);
- efi_set_bootdev("Net", "", ctx->path, map_sysmem(ctx->saved_daddr, 0),
- rx_content_len);
+ if (wget_info->set_bootdev)
+ efi_set_bootdev("Http", ctx->server_name, ctx->path, map_sysmem(ctx->saved_daddr, 0),
+ rx_content_len);
+ wget_lwip_set_file_size(rx_content_len);
if (env_set_hex("filesize", rx_content_len) ||
env_set_hex("fileaddr", ctx->saved_daddr)) {
log_err("Could not set filesize or fileaddr\n");
@@ -246,9 +274,19 @@
ctx->done = SUCCESS;
}
+static err_t httpc_headers_done_cb(httpc_state_t *connection, void *arg, struct pbuf *hdr,
+ u16_t hdr_len, u32_t content_len)
+{
+ wget_lwip_fill_info(hdr, hdr_len, content_len);
+
+ if (wget_info->check_buffer_size && (ulong)content_len > wget_info->buffer_size)
+ return ERR_BUF;
+
+ return ERR_OK;
+}
+
static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri)
{
- char server_name[SERVER_NAME_SIZE];
#if defined CONFIG_WGET_HTTPS
altcp_allocator_t tls_allocator;
#endif
@@ -257,7 +295,6 @@
struct netif *netif;
struct wget_ctx ctx;
char *path;
- u16 port;
bool is_https;
ctx.daddr = dst_addr;
@@ -267,7 +304,7 @@
ctx.prevsize = 0;
ctx.start_time = 0;
- if (parse_url(uri, server_name, &port, &path, &is_https))
+ if (parse_url(uri, ctx.server_name, &ctx.port, &path, &is_https))
return CMD_RET_USAGE;
netif = net_lwip_new_netif(udev);
@@ -279,7 +316,7 @@
if (is_https) {
tls_allocator.alloc = &altcp_tls_alloc;
tls_allocator.arg =
- altcp_tls_create_config_client(NULL, 0, server_name);
+ altcp_tls_create_config_client(NULL, 0, ctx.server_name);
if (!tls_allocator.arg) {
log_err("error: Cannot create a TLS connection\n");
@@ -292,8 +329,9 @@
#endif
conn.result_fn = httpc_result_cb;
+ conn.headers_done_fn = httpc_headers_done_cb;
ctx.path = path;
- if (httpc_get_file_dns(server_name, port, path, &conn, httpc_recv_cb,
+ if (httpc_get_file_dns(ctx.server_name, ctx.port, path, &conn, httpc_recv_cb,
&ctx, &state)) {
net_lwip_remove_netif(netif);
return CMD_RET_FAILURE;
@@ -314,10 +352,13 @@
return -1;
}
-int wget_with_dns(ulong dst_addr, char *uri)
+int wget_do_request(ulong dst_addr, char *uri)
{
eth_set_current();
+ if (!wget_info)
+ wget_info = &default_wget_info;
+
return wget_loop(eth_get_dev(), dst_addr, uri);
}
@@ -344,7 +385,8 @@
if (parse_legacy_arg(url, nurl, sizeof(nurl)))
return CMD_RET_FAILURE;
- if (wget_with_dns(dst_addr, nurl))
+ wget_info = &default_wget_info;
+ if (wget_do_request(dst_addr, nurl))
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
diff --git a/net/net-common.c b/net/net-common.c
index a7f767d..e01b0da 100644
--- a/net/net-common.c
+++ b/net/net-common.c
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
+#include <net-common.h>
void copy_filename(char *dst, const char *src, int size)
{
@@ -11,3 +12,16 @@
*dst++ = *src++;
*dst = '\0';
}
+
+struct wget_http_info default_wget_info = {
+ .method = WGET_HTTP_METHOD_GET,
+ .set_bootdev = true,
+};
+
+struct wget_http_info *wget_info;
+
+int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info)
+{
+ wget_info = info ? info : &default_wget_info;
+ return wget_do_request(dst_addr, uri);
+}
diff --git a/net/net.c b/net/net.c
index f47e9fb..ca35704 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1723,17 +1723,6 @@
return 1;
}
-void ip_to_string(struct in_addr x, char *s)
-{
- x.s_addr = ntohl(x.s_addr);
- sprintf(s, "%d.%d.%d.%d",
- (int) ((x.s_addr >> 24) & 0xff),
- (int) ((x.s_addr >> 16) & 0xff),
- (int) ((x.s_addr >> 8) & 0xff),
- (int) ((x.s_addr >> 0) & 0xff)
- );
-}
-
void vlan_to_string(ushort x, char *s)
{
x = ntohs(x);
diff --git a/net/wget.c b/net/wget.c
index 361817a..d338eaf 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -22,10 +22,11 @@
/* The default, change with environment variable 'httpdstp' */
#define SERVER_PORT 80
-static const char bootfile1[] = "GET ";
+static const char bootfileGET[] = "GET ";
+static const char bootfileHEAD[] = "HEAD ";
static const char bootfile3[] = " HTTP/1.0\r\n\r\n";
static const char http_eom[] = "\r\n\r\n";
-static const char http_ok[] = "200";
+static const char content_len[] = "Content-Length";
static const char linefeed[] = "\r\n";
static struct in_addr web_server_ip;
static int our_port;
@@ -45,6 +46,7 @@
#define PKTQ_SZ (PKTBUFSRX / 4)
static struct pkt_qd pkt_q[PKTQ_SZ];
static int pkt_q_idx;
+static unsigned long content_length;
static unsigned int packets;
static unsigned int initial_data_seq_num;
@@ -75,7 +77,7 @@
ulong newsize = offset + len;
uchar *ptr;
- if (CONFIG_IS_ENABLED(LMB)) {
+ if (CONFIG_IS_ENABLED(LMB) && wget_info->set_bootdev) {
if (store_addr < image_load_addr ||
lmb_read_check(store_addr, len)) {
printf("\nwget error: ");
@@ -130,8 +132,17 @@
IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2;
offset = ptr;
- memcpy(offset, &bootfile1, strlen(bootfile1));
- offset += strlen(bootfile1);
+ switch (wget_info->method) {
+ case WGET_HTTP_METHOD_HEAD:
+ memcpy(offset, &bootfileHEAD, strlen(bootfileHEAD));
+ offset += strlen(bootfileHEAD);
+ break;
+ case WGET_HTTP_METHOD_GET:
+ default:
+ memcpy(offset, &bootfileGET, strlen(bootfileGET));
+ offset += strlen(bootfileGET);
+ break;
+ }
memcpy(offset, image_url, strlen(image_url));
offset += strlen(image_url);
@@ -191,6 +202,52 @@
#define PKT_QUEUE_OFFSET 0x20000
#define PKT_QUEUE_PACKET_SIZE 0x800
+static void wget_fill_info(const uchar *pkt, int hlen)
+{
+ const char *first_space;
+ const char *second_space;
+ char *pos, *end;
+
+ if (wget_info->headers) {
+ if (hlen < MAX_HTTP_HEADERS_SIZE)
+ strncpy(wget_info->headers, pkt, hlen);
+ else
+ hlen = 0;
+ wget_info->headers[hlen] = 0;
+ }
+
+ //Get status code
+ first_space = strchr(pkt, ' ');
+ if (!first_space) {
+ wget_info->status_code = -1;
+ return;
+ }
+
+ second_space = strchr(first_space + 1, ' ');
+ if (!second_space) {
+ wget_info->status_code = -1;
+ return;
+ }
+
+ wget_info->status_code = (u32)simple_strtoul(first_space + 1, &end, 10);
+
+ if (second_space != end)
+ wget_info->status_code = -1;
+
+ pos = strstr((char *)pkt, content_len);
+
+ if (pos) {
+ pos += sizeof(content_len) + 1;
+ while (*pos == ' ')
+ pos++;
+ content_length = simple_strtoul(pos, &end, 10);
+ debug_cond(DEBUG_WGET,
+ "wget: Connected Len %lu\n",
+ content_length);
+ wget_info->hdr_cont_len = content_length;
+ }
+}
+
static void wget_connected(uchar *pkt, unsigned int tcp_seq_num,
u8 action, unsigned int tcp_ack_num, unsigned int len)
{
@@ -239,7 +296,11 @@
initial_data_seq_num = tcp_seq_num + hlen;
next_data_seq_num = tcp_seq_num + len;
+ wget_fill_info(pkt, hlen);
+ debug_cond(DEBUG_WGET,
+ "wget: HTTP Status Code %d\n", wget_info->status_code);
+
- if (strstr((char *)pkt, http_ok) == 0) {
+ if (wget_info->status_code != 200) {
debug_cond(DEBUG_WGET,
"wget: Connected Bad Xfer\n");
wget_loop_state = NETLOOP_FAIL;
@@ -384,10 +445,13 @@
case WGET_TRANSFERRED:
printf("Packets received %d, Transfer Successful\n", packets);
net_set_state(wget_loop_state);
- efi_set_bootdev("Net", "", image_url,
- map_sysmem(image_load_addr, 0),
- net_boot_file_size);
- env_set_hex("filesize", net_boot_file_size);
+ wget_info->file_size = net_boot_file_size;
+ if (wget_info->method == WGET_HTTP_METHOD_GET && wget_info->set_bootdev) {
+ efi_set_bootdev("Http", NULL, image_url,
+ map_sysmem(image_load_addr, 0),
+ net_boot_file_size);
+ env_set_hex("filesize", net_boot_file_size);
+ }
break;
}
}
@@ -412,6 +476,9 @@
void wget_start(void)
{
+ if (!wget_info)
+ wget_info = &default_wget_info;
+
image_url = strchr(net_boot_file_name, ':');
if (image_url > 0) {
web_server_ip = string_to_ip(net_boot_file_name);
@@ -468,8 +535,7 @@
wget_send(TCP_SYN, 0, 0, 0);
}
-#if (IS_ENABLED(CONFIG_CMD_DNS))
-int wget_with_dns(ulong dst_addr, char *uri)
+int wget_do_request(ulong dst_addr, char *uri)
{
int ret;
char *s, *host_name, *file_name, *str_copy;
@@ -488,24 +554,32 @@
s = str_copy + strlen("http://");
host_name = strsep(&s, "/");
if (!s) {
- log_err("Error: invalied uri, no file path\n");
ret = -EINVAL;
goto out;
}
file_name = s;
- /* TODO: If the given uri has ip address for the http server, skip dns */
- net_dns_resolve = host_name;
- net_dns_env_var = "httpserverip";
- if (net_loop(DNS) < 0) {
- log_err("Error: dns lookup of %s failed, check setup\n", net_dns_resolve);
- ret = -EINVAL;
- goto out;
- }
- s = env_get("httpserverip");
- if (!s) {
+ host_name = strsep(&host_name, ":");
+
+ if (string_to_ip(host_name).s_addr) {
+ s = host_name;
+ } else {
+#if IS_ENABLED(CONFIG_CMD_DNS)
+ net_dns_resolve = host_name;
+ net_dns_env_var = "httpserverip";
+ if (net_loop(DNS) < 0) {
+ ret = -EINVAL;
+ goto out;
+ }
+ s = env_get("httpserverip");
+ if (!s) {
+ ret = -EINVAL;
+ goto out;
+ }
+#else
ret = -EINVAL;
goto out;
+#endif
}
strlcpy(net_boot_file_name, s, sizeof(net_boot_file_name));
@@ -517,9 +591,8 @@
out:
free(str_copy);
- return ret;
+ return ret < 0 ? ret : 0;
}
-#endif
/**
* wget_validate_uri() - validate the uri for wget
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index da713d8..e33b08a 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -1199,8 +1199,8 @@
}
BOOTSTD_TEST(bootflow_cros, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT);
-/* Test Android bootmeth */
-static int bootflow_android(struct unit_test_state *uts)
+/* Test Android bootmeth with boot image version 4 */
+static int bootflow_android_image_v4(struct unit_test_state *uts)
{
if (!IS_ENABLED(CONFIG_BOOTMETH_ANDROID))
return -EAGAIN;
@@ -1220,7 +1220,30 @@
return 0;
}
-BOOTSTD_TEST(bootflow_android, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_android_image_v4, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT);
+
+/* Test Android bootmeth with boot image version 2 */
+static int bootflow_android_image_v2(struct unit_test_state *uts)
+{
+ if (!IS_ENABLED(CONFIG_BOOTMETH_ANDROID))
+ return -EAGAIN;
+
+ ut_assertok(scan_mmc_android_bootdev(uts, "mmc8"));
+ ut_assertok(run_command("bootflow list", 0));
+
+ ut_assert_nextlinen("Showing all");
+ ut_assert_nextlinen("Seq");
+ ut_assert_nextlinen("---");
+ ut_assert_nextlinen(" 0 extlinux");
+ ut_assert_nextlinen(" 1 android ready mmc 0 mmc8.bootdev.whole ");
+ ut_assert_nextlinen("---");
+ ut_assert_skip_to_line("(2 bootflows, 2 valid)");
+
+ ut_assert_console_end();
+
+ return 0;
+}
+BOOTSTD_TEST(bootflow_android_image_v2, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT);
/* Test EFI bootmeth */
static int bootflow_efi(struct unit_test_state *uts)
diff --git a/test/boot/bootm.c b/test/boot/bootm.c
index 52b83f1..9455f44 100644
--- a/test/boot/bootm.c
+++ b/test/boot/bootm.c
@@ -28,6 +28,7 @@
/* This tests relies on GD_FLG_SILENT not being set */
gd->flags &= ~GD_FLG_SILENT;
+ env_set("silent_linux", NULL);
*buf = '\0';
ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_ALL));
@@ -183,6 +184,7 @@
ut_asserteq(0, bootm_process_cmdline(buf, 22, BOOTM_CL_SUBST));
/* Check multiple substitutions */
+ ut_assertok(env_set("bvar", NULL));
ut_assertok(env_set("var", "abc"));
strcpy(buf, "some${var}thing${bvar}else");
ut_asserteq(0, bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_SUBST));
@@ -201,6 +203,7 @@
/* Test silent processing in the bootargs variable */
static int bootm_test_silent_var(struct unit_test_state *uts)
{
+ ut_assertok(env_set("var", NULL));
env_set("bootargs", NULL);
ut_assertok(bootm_process_cmdline_env(BOOTM_CL_SUBST));
ut_assertnull(env_get("bootargs"));
diff --git a/test/common/print.c b/test/common/print.c
index 464e425..e3711b1 100644
--- a/test/common/print.c
+++ b/test/common/print.c
@@ -241,7 +241,7 @@
static int print_hexdump_line(struct unit_test_state *uts)
{
- char *linebuf;
+ u8 *linebuf;
u8 *buf;
int i;
@@ -254,10 +254,10 @@
linebuf = map_sysmem(0x400, BUF_SIZE);
memset(linebuf, '\xff', BUF_SIZE);
ut_asserteq(-ENOSPC, hexdump_line(0, buf, 1, 0x10, 0, linebuf, 75));
- ut_asserteq(-1, linebuf[0]);
+ ut_asserteq(0xff, linebuf[0]);
ut_asserteq(0x10, hexdump_line(0, buf, 1, 0x10, 0, linebuf, 76));
- ut_asserteq(0, linebuf[75]);
- ut_asserteq(-1, linebuf[76]);
+ ut_asserteq('\0', linebuf[75]);
+ ut_asserteq(0xff, linebuf[76]);
unmap_sysmem(buf);
diff --git a/test/dm/led.c b/test/dm/led.c
index 884f641..e5b8632 100644
--- a/test/dm/led.c
+++ b/test/dm/led.c
@@ -144,7 +144,7 @@
{
struct udevice *dev
- /* options/u-boot/boot-led is set to "sandbox:green" */
+ /* options/u-boot/boot-led is set to phandle to "sandbox:green" */
ut_assertok(led_get_by_label("sandbox:green", &dev));
ut_asserteq(LEDST_OFF, led_get_state(dev));
ut_assertok(led_boot_on());
@@ -154,14 +154,15 @@
return 0;
}
+DM_TEST(dm_test_led_boot, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test LED boot blink fallback */
#ifndef CONFIG_LED_BLINK
-static int dm_test_led_boot(struct unit_test_state *uts)
+static int dm_test_led_boot_blink(struct unit_test_state *uts)
{
struct udevice *dev
- /* options/u-boot/boot-led is set to "sandbox:green" */
+ /* options/u-boot/boot-led is set to phandle to "sandbox:green" */
ut_assertok(led_get_by_label("sandbox:green", &dev));
ut_asserteq(LEDST_OFF, led_get_state(dev));
ut_assertok(led_boot_blink());
@@ -171,16 +172,17 @@
return 0;
}
+DM_TEST(dm_test_led_boot_blink, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#endif
#endif
/* Test LED activity */
#ifdef CONFIG_LED_ACTIVITY
-static int dm_test_led_boot(struct unit_test_state *uts)
+static int dm_test_led_activity(struct unit_test_state *uts)
{
struct udevice *dev
- /* options/u-boot/activity-led is set to "sandbox:red" */
+ /* options/u-boot/activity-led is set to phandle to "sandbox:red" */
ut_assertok(led_get_by_label("sandbox:red", &dev));
ut_asserteq(LEDST_OFF, led_get_state(dev));
ut_assertok(led_activity_on());
@@ -190,14 +192,15 @@
return 0;
}
+DM_TEST(dm_test_led_activity, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test LED activity blink fallback */
#ifndef CONFIG_LED_BLINK
-static int dm_test_led_boot(struct unit_test_state *uts)
+static int dm_test_led_activityt_blink(struct unit_test_state *uts)
{
struct udevice *dev
- /* options/u-boot/activity-led is set to "sandbox:red" */
+ /* options/u-boot/activity-led is set to phandle to "sandbox:red" */
ut_assertok(led_get_by_label("sandbox:red", &dev));
ut_asserteq(LEDST_OFF, led_get_state(dev));
ut_assertok(led_activity_blink());
@@ -207,5 +210,6 @@
return 0;
}
+DM_TEST(dm_test_led_activityt_blink, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#endif
#endif
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index ce99656..f16b643 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -141,9 +141,16 @@
{
oftree otree = get_other_oftree(uts);
ofnode node;
+ u32 idx;
+ int ret;
+
+ node = oftree_path(otree, "/node");
+ ut_assert(ofnode_valid(node));
- ut_assert(ofnode_valid(oftree_get_by_phandle(oftree_default(), 1)));
- node = oftree_get_by_phandle(otree, 1);
+ ret = ofnode_read_u32(node, "other-phandle", &idx);
+ ut_assertok(ret);
+
+ node = oftree_get_by_phandle(otree, idx);
ut_assert(ofnode_valid(node));
ut_asserteq_str("target", ofnode_get_name(node));
@@ -273,15 +280,16 @@
}
DM_TEST(dm_test_ofnode_read_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
-/* test ofnode_count_/parse_phandle_with_args() */
+/* test ofnode_count_/parse/_phandle_with_args() */
static int dm_test_ofnode_phandle(struct unit_test_state *uts)
{
struct ofnode_phandle_args args;
- ofnode node;
+ ofnode node, phandle, target;
int ret;
const char prop[] = "test-gpios";
const char cell[] = "#gpio-cells";
const char prop2[] = "phandle-value";
+ const char prop3[] = "phandle-nodes";
node = ofnode_path("/a-test");
ut_assert(ofnode_valid(node));
@@ -345,34 +353,117 @@
ret = ofnode_parse_phandle_with_args(node, prop2, NULL, 1, 3, &args);
ut_asserteq(-ENOENT, ret);
+ /* Test ofnode_parse_phandle */
+ phandle = ofnode_parse_phandle(node, "missing", 0);
+ ut_assert(ofnode_equal(ofnode_null(), phandle));
+
+ target = ofnode_path("/phandle-node-1");
+ ut_assert(ofnode_valid(target));
+ phandle = ofnode_parse_phandle(node, prop3, 0);
+ ut_assert(ofnode_equal(target, phandle));
+
+ target = ofnode_path("/phandle-node-2");
+ ut_assert(ofnode_valid(target));
+ phandle = ofnode_parse_phandle(node, prop3, 1);
+ ut_assert(ofnode_equal(target, phandle));
+
+ phandle = ofnode_parse_phandle(node, prop3, 3);
+ ut_assert(ofnode_equal(ofnode_null(), phandle));
+
return 0;
}
DM_TEST(dm_test_ofnode_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
-/* test ofnode_count_/parse_phandle_with_args() with 'other' tree */
+/* test oftree_count_/parse/_phandle_with_args() with 'other' tree */
static int dm_test_ofnode_phandle_ot(struct unit_test_state *uts)
{
oftree otree = get_other_oftree(uts);
struct ofnode_phandle_args args;
- ofnode node;
+ ofnode node, phandle, target;
int ret;
+ const char prop[] = "other-test-gpios";
+ const char cell[] = "#gpio-cells";
+ const char prop2[] = "other-phandle-value";
+ const char prop3[] = "other-phandle-nodes";
- node = oftree_path(otree, "/node");
+ node = oftree_path(otree, "/other-a-test");
+ ut_assert(ofnode_valid(node));
- /* Test ofnode_count_phandle_with_args with cell name */
- ret = ofnode_count_phandle_with_args(node, "missing", "#gpio-cells", 0);
+ /* Test oftree_count_phandle_with_args with cell name */
+ ret = oftree_count_phandle_with_args(otree, node, "missing", cell, 0);
ut_asserteq(-ENOENT, ret);
- ret = ofnode_count_phandle_with_args(node, "target", "#invalid", 0);
+ ret = oftree_count_phandle_with_args(otree, node, prop, "#invalid", 0);
ut_asserteq(-EINVAL, ret);
- ret = ofnode_count_phandle_with_args(node, "target", "#gpio-cells", 0);
- ut_asserteq(1, ret);
+ ret = oftree_count_phandle_with_args(otree, node, prop, cell, 0);
+ ut_asserteq(5, ret);
- ret = ofnode_parse_phandle_with_args(node, "target", "#gpio-cells", 0,
- 0, &args);
+ /* Test oftree_parse_phandle_with_args with cell name */
+ ret = oftree_parse_phandle_with_args(otree, node, "missing", cell, 0, 0,
+ &args);
+ ut_asserteq(-ENOENT, ret);
+ ret = oftree_parse_phandle_with_args(otree, node, prop, "#invalid", 0, 0,
+ &args);
+ ut_asserteq(-EINVAL, ret);
+ ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 0, &args);
+ ut_assertok(ret);
+ ut_asserteq(1, args.args_count);
+ ut_asserteq(1, args.args[0]);
+ ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 1, &args);
ut_assertok(ret);
- ut_asserteq(2, args.args_count);
- ut_asserteq(3, args.args[0]);
- ut_asserteq(4, args.args[1]);
+ ut_asserteq(1, args.args_count);
+ ut_asserteq(4, args.args[0]);
+ ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 2, &args);
+ ut_assertok(ret);
+ ut_asserteq(5, args.args_count);
+ ut_asserteq(5, args.args[0]);
+ ut_asserteq(1, args.args[4]);
+ ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 3, &args);
+ ut_asserteq(-ENOENT, ret);
+ ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 4, &args);
+ ut_assertok(ret);
+ ut_asserteq(1, args.args_count);
+ ut_asserteq(12, args.args[0]);
+ ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 5, &args);
+ ut_asserteq(-ENOENT, ret);
+
+ /* Test oftree_count_phandle_with_args with cell count */
+ ret = oftree_count_phandle_with_args(otree, node, "missing", NULL, 2);
+ ut_asserteq(-ENOENT, ret);
+ ret = oftree_count_phandle_with_args(otree, node, prop2, NULL, 1);
+ ut_asserteq(3, ret);
+
+ /* Test oftree_parse_phandle_with_args with cell count */
+ ret = oftree_parse_phandle_with_args(otree, node, prop2, NULL, 1, 0, &args);
+ ut_assertok(ret);
+ ut_asserteq(1, ofnode_valid(args.node));
+ ut_asserteq(1, args.args_count);
+ ut_asserteq(10, args.args[0]);
+ ret = oftree_parse_phandle_with_args(otree, node, prop2, NULL, 1, 1, &args);
+ ut_asserteq(-EINVAL, ret);
+ ret = oftree_parse_phandle_with_args(otree, node, prop2, NULL, 1, 2, &args);
+ ut_assertok(ret);
+ ut_asserteq(1, ofnode_valid(args.node));
+ ut_asserteq(1, args.args_count);
+ ut_asserteq(30, args.args[0]);
+ ret = oftree_parse_phandle_with_args(otree, node, prop2, NULL, 1, 3, &args);
+ ut_asserteq(-ENOENT, ret);
+
+ /* Test oftree_parse_phandle */
+ phandle = oftree_parse_phandle(otree, node, "missing", 0);
+ ut_assert(ofnode_equal(ofnode_null(), phandle));
+
+ target = oftree_path(otree, "/other-phandle-node-1");
+ ut_assert(ofnode_valid(target));
+ phandle = oftree_parse_phandle(otree, node, prop3, 0);
+ ut_assert(ofnode_equal(target, phandle));
+
+ target = oftree_path(otree, "/other-phandle-node-2");
+ ut_assert(ofnode_valid(target));
+ phandle = oftree_parse_phandle(otree, node, prop3, 1);
+ ut_assert(ofnode_equal(target, phandle));
+
+ phandle = oftree_parse_phandle(otree, node, prop3, 3);
+ ut_assert(ofnode_equal(ofnode_null(), phandle));
return 0;
}
@@ -613,6 +704,10 @@
{
u64 bootscr_address, bootscr_offset;
u64 bootscr_flash_offset, bootscr_flash_size;
+ ofnode node, phandle_node, target;
+
+ node = ofnode_path("/options/u-boot");
+ ut_assert(ofnode_valid(node));
ut_assert(!ofnode_options_read_bool("missing"));
ut_assert(ofnode_options_read_bool("testing-bool"));
@@ -623,6 +718,13 @@
ut_assertnull(ofnode_options_read_str("missing"));
ut_asserteq_str("testing", ofnode_options_read_str("testing-str"));
+ ut_asserteq(-EINVAL, ofnode_options_get_by_phandle("missing", &phandle_node));
+
+ target = ofnode_path("/phandle-node-1");
+ ut_assert(ofnode_valid(target));
+ ut_assertok(ofnode_options_get_by_phandle("testing-phandle", &phandle_node));
+ ut_assert(ofnode_equal(target, phandle_node));
+
ut_assertok(ofnode_read_bootscript_address(&bootscr_address,
&bootscr_offset));
ut_asserteq_64(0, bootscr_address);
diff --git a/test/dm/sysinfo-gpio.c b/test/dm/sysinfo-gpio.c
index 155da3b..de9483c 100644
--- a/test/dm/sysinfo-gpio.c
+++ b/test/dm/sysinfo-gpio.c
@@ -29,9 +29,9 @@
sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_DOWN);
sandbox_gpio_set_flags(gpio, 17, 0);
ut_assertok(sysinfo_detect(sysinfo));
- ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val));
+ ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val));
ut_asserteq(19, val);
- ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf),
+ ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf),
buf));
ut_asserteq_str("rev_a", buf);
@@ -43,9 +43,9 @@
sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_UP);
sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_DOWN);
ut_assertok(sysinfo_detect(sysinfo));
- ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val));
+ ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val));
ut_asserteq(5, val);
- ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf),
+ ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf),
buf));
ut_asserteq_str("foo", buf);
@@ -57,9 +57,9 @@
sandbox_gpio_set_flags(gpio, 16, 0);
sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_UP);
ut_assertok(sysinfo_detect(sysinfo));
- ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val));
+ ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val));
ut_asserteq(15, val);
- ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf),
+ ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf),
buf));
ut_asserteq_str("unknown", buf);
diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c
index 4af0576..9f16a97 100644
--- a/test/env/cmd_ut_env.c
+++ b/test/env/cmd_ut_env.c
@@ -14,23 +14,62 @@
ut_assertok(run_command("setenv non_default_var1 1", 0));
ut_assert_console_end();
- ut_assertok(run_command("setenv non_default_var2 1", 0));
+ ut_assertok(run_command("setenv non_default_var2 2", 0));
ut_assert_console_end();
ut_assertok(run_command("env print non_default_var1", 0));
ut_assert_nextline("non_default_var1=1");
ut_assert_console_end();
- ut_assertok(run_command("env default non_default_var1 non_default_var2", 0));
+ ut_assertok(run_command("env default non_default_var1", 0));
ut_assert_nextline("WARNING: 'non_default_var1' not in imported env, deleting it!");
- ut_assert_nextline("WARNING: 'non_default_var2' not in imported env, deleting it!");
ut_assert_console_end();
ut_asserteq(1, run_command("env exists non_default_var1", 0));
ut_assert_console_end();
+ ut_asserteq(0, run_command("env exists non_default_var2", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("setenv non_default_var1 3", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("env default -k non_default_var1", 0));
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("env exists non_default_var1", 0));
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("env exists non_default_var2", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("env default -k -a -f", 0));
+ ut_assert_nextline("## Resetting to default environment");
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("env exists non_default_var1", 0));
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("env exists non_default_var2", 0));
+ ut_assert_console_end();
+
+ /*
+ * While the following test of "env default -a" by itself
+ * works, it unfortunately causes an unrelated test case,
+ * env_test_fdt_import(), to fail, because the "from_fdt"
+ * variable would be removed.
+ */
+#if 0
+ ut_assertok(run_command("env default -a", 0));
+ ut_assert_nextline("## Resetting to default environment");
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("env exists non_default_var1", 0));
+ ut_assert_console_end();
+
ut_asserteq(1, run_command("env exists non_default_var2", 0));
ut_assert_console_end();
+#endif
return 0;
}
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index c917115..0bd29e2 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -529,6 +529,26 @@
ret = lmb_add(ram, ram_size);
ut_asserteq(ret, 0);
+ /* Try to allocate a page twice */
+ b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE);
+ ut_asserteq(b, alloc_addr_a);
+ b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
+ ut_asserteq(b, 0);
+ b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE);
+ ut_asserteq(b, alloc_addr_a);
+ b = lmb_alloc_addr_flags(alloc_addr_a, 0x2000, LMB_NONE);
+ ut_asserteq(b, alloc_addr_a);
+ ret = lmb_free(alloc_addr_a, 0x2000);
+ ut_asserteq(ret, 0);
+ b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
+ ut_asserteq(b, alloc_addr_a);
+ b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE);
+ ut_asserteq(b, 0);
+ b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
+ ut_asserteq(b, 0);
+ ret = lmb_free(alloc_addr_a, 0x1000);
+ ut_asserteq(ret, 0);
+
/* reserve 3 blocks */
ret = lmb_reserve(alloc_addr_a, 0x10000);
ut_asserteq(ret, 0);
@@ -734,7 +754,7 @@
/* reserve again, same flag */
ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP);
- ut_asserteq(ret, 0);
+ ut_asserteq(ret, -1L);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
0, 0, 0, 0);
diff --git a/test/py/tests/bootstd/flash1.img.xz b/test/py/tests/bootstd/flash1.img.xz
deleted file mode 100644
index 29b78c6..0000000
--- a/test/py/tests/bootstd/flash1.img.xz
+++ /dev/null
Binary files differ
diff --git a/test/py/tests/bootstd/mmc1.img.xz b/test/py/tests/bootstd/mmc1.img.xz
deleted file mode 100644
index cebf7b9..0000000
--- a/test/py/tests/bootstd/mmc1.img.xz
+++ /dev/null
Binary files differ
diff --git a/test/py/tests/bootstd/mmc4.img.xz b/test/py/tests/bootstd/mmc4.img.xz
deleted file mode 100644
index f4db011..0000000
--- a/test/py/tests/bootstd/mmc4.img.xz
+++ /dev/null
Binary files differ
diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py
index 380f4c4..ccfc020 100644
--- a/test/py/tests/fs_helper.py
+++ b/test/py/tests/fs_helper.py
@@ -9,7 +9,7 @@
import os
from subprocess import call, check_call, check_output, CalledProcessError
-def mk_fs(config, fs_type, size, prefix, size_gran = 0x100000):
+def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000):
"""Create a file system volume
Args:
@@ -17,6 +17,7 @@
fs_type (str): File system type, e.g. 'ext4'
size (int): Size of file system in bytes
prefix (str): Prefix string of volume's file name
+ src_dir (str): Root directory to use, or None for none
size_gran (int): Size granularity of file system image in bytes
Raises:
@@ -39,6 +40,12 @@
else:
fs_lnxtype = fs_type
+ if src_dir:
+ if fs_lnxtype == 'ext4':
+ mkfs_opt = mkfs_opt + ' -d ' + src_dir
+ elif fs_lnxtype != 'vfat':
+ raise ValueError(f'src_dir not implemented for fs {fs_lnxtype}')
+
count = (size + size_gran - 1) // size_gran
# Some distributions do not add /sbin to the default PATH, where mkfs lives
@@ -55,6 +62,8 @@
shell=True).decode()
if 'metadata_csum' in sb_content:
check_call(f'tune2fs -O ^metadata_csum {fs_img}', shell=True)
+ elif fs_lnxtype == 'vfat' and src_dir:
+ check_call(f'mcopy -i {fs_img} -vsmpQ {src_dir}/* ::/', shell=True)
return fs_img
except CalledProcessError:
call(f'rm -f {fs_img}', shell=True)
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index fca5448..af2adaf 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -156,64 +156,6 @@
return True
return False
-fuse_mounted = False
-
-def mount_fs(fs_type, device, mount_point):
- """Mount a volume.
-
- Args:
- fs_type: File system type.
- device: Volume's file name.
- mount_point: Mount point.
-
- Return:
- Nothing.
- """
- global fuse_mounted
-
- try:
- check_call('guestmount --pid-file guestmount.pid -a %s -m /dev/sda %s'
- % (device, mount_point), shell=True)
- fuse_mounted = True
- return
- except CalledProcessError:
- fuse_mounted = False
-
- mount_opt = 'loop,rw'
- if re.match('fat', fs_type):
- mount_opt += ',umask=0000'
-
- check_call('sudo mount -o %s %s %s'
- % (mount_opt, device, mount_point), shell=True)
-
- # may not be effective for some file systems
- check_call('sudo chmod a+rw %s' % mount_point, shell=True)
-
-def umount_fs(mount_point):
- """Unmount a volume.
-
- Args:
- mount_point: Mount point.
-
- Return:
- Nothing.
- """
- if fuse_mounted:
- call('sync')
- call('guestunmount %s' % mount_point, shell=True)
-
- try:
- with open("guestmount.pid", "r") as pidfile:
- pid = int(pidfile.read())
- util.waitpid(pid, kill=True)
- os.remove("guestmount.pid")
-
- except FileNotFoundError:
- pass
-
- else:
- call('sudo umount %s' % mount_point, shell=True)
-
#
# Fixture for basic fs test
# derived from test/fs/fs-test.sh
@@ -236,38 +178,21 @@
fs_ubtype = fstype_to_ubname(fs_type)
check_ubconfig(u_boot_config, fs_ubtype)
- mount_dir = u_boot_config.persistent_data_dir + '/mnt'
+ scratch_dir = u_boot_config.persistent_data_dir + '/scratch'
- small_file = mount_dir + '/' + SMALL_FILE
- big_file = mount_dir + '/' + BIG_FILE
+ small_file = scratch_dir + '/' + SMALL_FILE
+ big_file = scratch_dir + '/' + BIG_FILE
try:
-
- # 3GiB volume
- fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0xc0000000, '3GB')
- except CalledProcessError as err:
- pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
- return
-
- try:
- check_call('mkdir -p %s' % mount_dir, shell=True)
+ check_call('mkdir -p %s' % scratch_dir, shell=True)
except CalledProcessError as err:
pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err))
call('rm -f %s' % fs_img, shell=True)
return
try:
- # Mount the image so we can populate it.
- mount_fs(fs_type, fs_img, mount_dir)
- except CalledProcessError as err:
- pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err))
- call('rmdir %s' % mount_dir, shell=True)
- call('rm -f %s' % fs_img, shell=True)
- return
-
- try:
# Create a subdirectory.
- check_call('mkdir %s/SUBDIR' % mount_dir, shell=True)
+ check_call('mkdir %s/SUBDIR' % scratch_dir, shell=True)
# Create big file in this image.
# Note that we work only on the start 1MB, couple MBs in the 2GB range
@@ -326,15 +251,20 @@
% big_file, shell=True).decode()
md5val.append(out.split()[0])
+ try:
+ # 3GiB volume
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0xc0000000, '3GB', scratch_dir)
+ except CalledProcessError as err:
+ pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
+ return
+
except CalledProcessError as err:
pytest.skip('Setup failed for filesystem: ' + fs_type + '. {}'.format(err))
- umount_fs(mount_dir)
return
else:
- umount_fs(mount_dir)
yield [fs_ubtype, fs_img, md5val]
finally:
- call('rmdir %s' % mount_dir, shell=True)
+ call('rm -rf %s' % scratch_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
#
@@ -358,38 +288,21 @@
fs_ubtype = fstype_to_ubname(fs_type)
check_ubconfig(u_boot_config, fs_ubtype)
- mount_dir = u_boot_config.persistent_data_dir + '/mnt'
-
- min_file = mount_dir + '/' + MIN_FILE
- tmp_file = mount_dir + '/tmpfile'
+ scratch_dir = u_boot_config.persistent_data_dir + '/scratch'
- try:
-
- # 128MiB volume
- fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
- except CalledProcessError as err:
- pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
- return
+ min_file = scratch_dir + '/' + MIN_FILE
+ tmp_file = scratch_dir + '/tmpfile'
try:
- check_call('mkdir -p %s' % mount_dir, shell=True)
+ check_call('mkdir -p %s' % scratch_dir, shell=True)
except CalledProcessError as err:
pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err))
call('rm -f %s' % fs_img, shell=True)
return
try:
- # Mount the image so we can populate it.
- mount_fs(fs_type, fs_img, mount_dir)
- except CalledProcessError as err:
- pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err))
- call('rmdir %s' % mount_dir, shell=True)
- call('rm -f %s' % fs_img, shell=True)
- return
-
- try:
# Create a test directory
- check_call('mkdir %s/dir1' % mount_dir, shell=True)
+ check_call('mkdir %s/dir1' % scratch_dir, shell=True)
# Create a small file and calculate md5
check_call('dd if=/dev/urandom of=%s bs=1K count=20'
@@ -427,15 +340,21 @@
md5val.append(out.split()[0])
check_call('rm %s' % tmp_file, shell=True)
+
+ try:
+ # 128MiB volume
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB', scratch_dir)
+ except CalledProcessError as err:
+ pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
+ return
+
except CalledProcessError:
pytest.skip('Setup failed for filesystem: ' + fs_type)
- umount_fs(mount_dir)
return
else:
- umount_fs(mount_dir)
yield [fs_ubtype, fs_img, md5val]
finally:
- call('rmdir %s' % mount_dir, shell=True)
+ call('rm -rf %s' % scratch_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
#
@@ -461,7 +380,7 @@
try:
# 128MiB volume
- fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB', None)
except:
pytest.skip('Setup failed for filesystem: ' + fs_type)
return
@@ -490,63 +409,51 @@
fs_ubtype = fstype_to_ubname(fs_type)
check_ubconfig(u_boot_config, fs_ubtype)
- mount_dir = u_boot_config.persistent_data_dir + '/mnt'
-
- try:
-
- # 128MiB volume
- fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
- except CalledProcessError as err:
- pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
- return
+ scratch_dir = u_boot_config.persistent_data_dir + '/scratch'
try:
- check_call('mkdir -p %s' % mount_dir, shell=True)
+ check_call('mkdir -p %s' % scratch_dir, shell=True)
except CalledProcessError as err:
pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err))
call('rm -f %s' % fs_img, shell=True)
return
try:
- # Mount the image so we can populate it.
- mount_fs(fs_type, fs_img, mount_dir)
- except CalledProcessError as err:
- pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err))
- call('rmdir %s' % mount_dir, shell=True)
- call('rm -f %s' % fs_img, shell=True)
- return
-
- try:
# Test Case 1 & 3
- check_call('mkdir %s/dir1' % mount_dir, shell=True)
+ check_call('mkdir %s/dir1' % scratch_dir, shell=True)
check_call('dd if=/dev/urandom of=%s/dir1/file1 bs=1K count=1'
- % mount_dir, shell=True)
+ % scratch_dir, shell=True)
check_call('dd if=/dev/urandom of=%s/dir1/file2 bs=1K count=1'
- % mount_dir, shell=True)
+ % scratch_dir, shell=True)
# Test Case 2
- check_call('mkdir %s/dir2' % mount_dir, shell=True)
+ check_call('mkdir %s/dir2' % scratch_dir, shell=True)
for i in range(0, 20):
check_call('mkdir %s/dir2/0123456789abcdef%02x'
- % (mount_dir, i), shell=True)
+ % (scratch_dir, i), shell=True)
# Test Case 4
- check_call('mkdir %s/dir4' % mount_dir, shell=True)
+ check_call('mkdir %s/dir4' % scratch_dir, shell=True)
# Test Case 5, 6 & 7
- check_call('mkdir %s/dir5' % mount_dir, shell=True)
+ check_call('mkdir %s/dir5' % scratch_dir, shell=True)
check_call('dd if=/dev/urandom of=%s/dir5/file1 bs=1K count=1'
- % mount_dir, shell=True)
+ % scratch_dir, shell=True)
+
+ try:
+ # 128MiB volume
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB', scratch_dir)
+ except CalledProcessError as err:
+ pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
+ return
except CalledProcessError:
pytest.skip('Setup failed for filesystem: ' + fs_type)
- umount_fs(mount_dir)
return
else:
- umount_fs(mount_dir)
yield [fs_ubtype, fs_img]
finally:
- call('rmdir %s' % mount_dir, shell=True)
+ call('rm -rf %s' % scratch_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
#
@@ -570,38 +477,21 @@
fs_ubtype = fstype_to_ubname(fs_type)
check_ubconfig(u_boot_config, fs_ubtype)
- mount_dir = u_boot_config.persistent_data_dir + '/mnt'
+ scratch_dir = u_boot_config.persistent_data_dir + '/scratch'
- small_file = mount_dir + '/' + SMALL_FILE
- medium_file = mount_dir + '/' + MEDIUM_FILE
+ small_file = scratch_dir + '/' + SMALL_FILE
+ medium_file = scratch_dir + '/' + MEDIUM_FILE
try:
-
- # 1GiB volume
- fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x40000000, '1GB')
- except CalledProcessError as err:
- pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
- return
-
- try:
- check_call('mkdir -p %s' % mount_dir, shell=True)
+ check_call('mkdir -p %s' % scratch_dir, shell=True)
except CalledProcessError as err:
pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err))
call('rm -f %s' % fs_img, shell=True)
return
try:
- # Mount the image so we can populate it.
- mount_fs(fs_type, fs_img, mount_dir)
- except CalledProcessError as err:
- pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err))
- call('rmdir %s' % mount_dir, shell=True)
- call('rm -f %s' % fs_img, shell=True)
- return
-
- try:
# Create a subdirectory.
- check_call('mkdir %s/SUBDIR' % mount_dir, shell=True)
+ check_call('mkdir %s/SUBDIR' % scratch_dir, shell=True)
# Create a small file in this image.
check_call('dd if=/dev/urandom of=%s bs=1M count=1'
@@ -621,15 +511,20 @@
% medium_file, shell=True).decode()
md5val.extend([out.split()[0]])
+ try:
+ # 1GiB volume
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x40000000, '1GB', scratch_dir)
+ except CalledProcessError as err:
+ pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
+ return
+
except CalledProcessError:
pytest.skip('Setup failed for filesystem: ' + fs_type)
- umount_fs(mount_dir)
return
else:
- umount_fs(mount_dir)
yield [fs_ubtype, fs_img, md5val]
finally:
- call('rmdir %s' % mount_dir, shell=True)
+ call('rm -rf %s' % scratch_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
#
@@ -665,7 +560,7 @@
try:
# the volume size depends on the filesystem
- fs_img = fs_helper.mk_fs(u_boot_config, fs_type, fs_size, f'{fs_size}', 1024)
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, fs_size, f'{fs_size}', None, 1024)
except:
pytest.skip('Setup failed for filesystem: ' + fs_type)
return
diff --git a/test/py/tests/test_mmc.py b/test/py/tests/test_mmc.py
index a96c4e8..4624043 100644
--- a/test/py/tests/test_mmc.py
+++ b/test/py/tests/test_mmc.py
@@ -18,16 +18,55 @@
# Setup env__mmc_device_test_skip to not skipping the test. By default, its
# value is set to True. Set it to False to run all tests for MMC device.
env__mmc_device_test_skip = False
+
+# Setup env__mmc_device to set the supported mmc modes to be tested
+env__mmc_device {
+ 'mmc_modes': ['MMC_LEGACY', 'SD_HS'],
+}
+
"""
mmc_set_up = False
controllers = 0
devices = {}
+mmc_modes_name = []
+mmc_modes = []
+
+def setup_mmc_modes(cons):
+ global mmc_modes, mmc_modes_name
+ f = cons.config.env.get('env__mmc_device', None)
+ if f:
+ mmc_modes_name = f.get('mmc_modes', None)
+
+ # Set mmc mode to default mode (legacy), if speed mode config isn't enabled
+ if cons.config.buildconfig.get('config_mmc_speed_mode_set', 'n') != 'y':
+ mmc_modes = [0]
+ return
+
+ if mmc_modes_name:
+ mmc_help = cons.run_command('mmc -help')
+ m = re.search(r"\[MMC_LEGACY(.*\n.+])", mmc_help)
+ modes = [
+ x.strip()
+ for x in m.group()
+ .replace('\n', '')
+ .replace('[', '')
+ .replace(']', '')
+ .split(',')
+ ]
+
+ for mode in mmc_modes_name:
+ mmc_modes += [modes.index(mode)]
+ else:
+ # Set mmc mode to default mode (legacy), if it is not defined in env
+ mmc_modes = [0]
def setup_mmc(u_boot_console):
if u_boot_console.config.env.get('env__mmc_device_test_skip', True):
pytest.skip('MMC device test is not enabled')
+ setup_mmc_modes(u_boot_console)
+
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmc_list(u_boot_console):
setup_mmc(u_boot_console)
@@ -58,21 +97,22 @@
fail = 0
for x in range(0, controllers):
devices[x]['detected'] = 'yes'
- output = u_boot_console.run_command('mmc dev %d' % x)
- # Some sort of switch here
- if 'Card did not respond to voltage select' in output:
- fail = 1
- devices[x]['detected'] = 'no'
+ for y in mmc_modes:
+ output = u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
- if 'no mmc device at slot' in output:
- devices[x]['detected'] = 'no'
+ if 'Card did not respond to voltage select' in output:
+ fail = 1
+ devices[x]['detected'] = 'no'
- if 'MMC: no card present' in output:
- devices[x]['detected'] = 'no'
+ if 'no mmc device at slot' in output:
+ devices[x]['detected'] = 'no'
- if fail:
- pytest.fail('Card not present')
+ if 'MMC: no card present' in output:
+ devices[x]['detected'] = 'no'
+
+ if fail:
+ pytest.fail('Card not present')
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmcinfo(u_boot_console):
@@ -81,19 +121,22 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- output = u_boot_console.run_command('mmcinfo')
- if 'busy timeout' in output:
- pytest.skip('No SD/MMC/eMMC device present')
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
+ output = u_boot_console.run_command('mmcinfo')
+ if 'busy timeout' in output:
+ pytest.skip('No SD/MMC/eMMC device present')
- obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
- try:
- capacity = float(obj.groups()[0])
- print(capacity)
- devices[x]['capacity'] = capacity
- print('Capacity of dev %d is: %g GiB' % (x, capacity))
- except ValueError:
- pytest.fail('MMC capacity not recognized')
+ assert mmc_modes_name[mmc_modes.index(y)] in output
+
+ obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
+ try:
+ capacity = float(obj.groups()[0])
+ print(capacity)
+ devices[x]['capacity'] = capacity
+ print('Capacity of dev %d is: %g GiB' % (x, capacity))
+ except ValueError:
+ pytest.fail('MMC capacity not recognized')
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmc_info(u_boot_console):
@@ -102,19 +145,21 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
- output = u_boot_console.run_command('mmc info')
+ output = u_boot_console.run_command('mmc info')
+ assert mmc_modes_name[mmc_modes.index(y)] in output
- obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
- try:
- capacity = float(obj.groups()[0])
- print(capacity)
- if devices[x]['capacity'] != capacity:
- pytest.fail("MMC capacity doesn't match mmcinfo")
+ obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
+ try:
+ capacity = float(obj.groups()[0])
+ print(capacity)
+ if devices[x]['capacity'] != capacity:
+ pytest.fail("MMC capacity doesn't match mmcinfo")
- except ValueError:
- pytest.fail('MMC capacity not recognized')
+ except ValueError:
+ pytest.fail('MMC capacity not recognized')
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmc_rescan(u_boot_console):
@@ -126,12 +171,13 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- output = u_boot_console.run_command('mmc rescan')
- if output:
- pytest.fail('mmc rescan has something to check')
- output = u_boot_console.run_command('echo $?')
- assert output.endswith('0')
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
+ output = u_boot_console.run_command('mmc rescan')
+ if output:
+ pytest.fail('mmc rescan has something to check')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_mmc')
def test_mmc_part(u_boot_console):
@@ -148,7 +194,8 @@
lines = output.split('\n')
part_fat = []
- part_ext = []
+ part_ext2 = []
+ part_ext4 = []
for line in lines:
obj = re.search(
r'(\d)\s+\d+\s+\d+\s+\w+\d+\w+-\d+\s+(\d+\w+)', line)
@@ -161,15 +208,21 @@
print('Fat detected')
part_fat.append(part_id)
elif part_type == '83':
- print('ext detected')
- part_ext.append(part_id)
+ print('ext(2/4) detected')
+ output = u_boot_console.run_command(
+ 'fstype mmc %d:%d' % x, part_id
+ )
+ if 'ext2' in output:
+ part_ext2.append(part_id)
+ elif 'ext4' in output:
+ part_ext4.append(part_id)
else:
pytest.fail('Unsupported Filesystem on device %d' % x)
- devices[x]['ext4'] = part_ext
- devices[x]['ext2'] = part_ext
+ devices[x]['ext4'] = part_ext4
+ devices[x]['ext2'] = part_ext2
devices[x]['fat'] = part_fat
- if not part_ext and not part_fat:
+ if not part_ext2 and not part_ext4 and not part_fat:
pytest.fail('No partition detected on device %d' % x)
@pytest.mark.buildconfigspec('cmd_mmc')
@@ -185,7 +238,6 @@
fs = 'fat'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -193,20 +245,22 @@
continue
for part in partitions:
- output = u_boot_console.run_command(
- 'fatls mmc %d:%s' % (x, part))
- if 'Unrecognized filesystem type' in output:
- partitions.remove(part)
- pytest.fail('Unrecognized filesystem')
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ output = u_boot_console.run_command(
+ 'fatls mmc %d:%s' % (x, part))
+ if 'Unrecognized filesystem type' in output:
+ partitions.remove(part)
+ pytest.fail('Unrecognized filesystem')
- if not re.search(r'\d file\(s\), \d dir\(s\)', output):
- pytest.fail('%s read failed on device %d' % (fs.upper, x))
- output = u_boot_console.run_command(
- 'fatinfo mmc %d:%s' % (x, part))
- string = 'Filesystem: %s' % fs.upper
- if re.search(string, output):
- pytest.fail('%s FS failed on device %d' % (fs.upper(), x))
- part_detect = 1
+ if not re.search(r'\d file\(s\), \d dir\(s\)', output):
+ pytest.fail('%s read failed on device %d' % (fs.upper, x))
+ output = u_boot_console.run_command(
+ 'fatinfo mmc %d:%s' % (x, part))
+ string = 'Filesystem: %s' % fs.upper
+ if re.search(string, output):
+ pytest.fail('%s FS failed on device %d' % (fs.upper(), x))
+ part_detect = 1
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -226,7 +280,6 @@
fs = 'fat'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -234,49 +287,51 @@
continue
for part in partitions:
- part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
- devices[x]['addr_%d' % part] = addr
- size = random.randint(4, 1 * 1024 * 1024)
- devices[x]['size_%d' % part] = size
- # count CRC32
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- expected_crc32 = m.group(1)
- devices[x]['expected_crc32_%d' % part] = expected_crc32
- # do write
- file = '%s_%d' % ('uboot_test', size)
- devices[x]['file_%d' % part] = file
- output = u_boot_console.run_command(
- '%swrite mmc %d:%s %x %s %x' % (fs, x, part, addr, file, size)
- )
- assert 'Unable to write' not in output
- assert 'Error' not in output
- assert 'overflow' not in output
- expected_text = '%d bytes written' % size
- assert expected_text in output
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ devices[x]['addr_%d' % part] = addr
+ size = random.randint(4, 1 * 1024 * 1024)
+ devices[x]['size_%d' % part] = size
+ # count CRC32
+ output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ m = re.search('==> (.+?)', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ expected_crc32 = m.group(1)
+ devices[x]['expected_crc32_%d' % part] = expected_crc32
+ # do write
+ file = '%s_%d' % ('uboot_test', size)
+ devices[x]['file_%d' % part] = file
+ output = u_boot_console.run_command(
+ '%swrite mmc %d:%s %x %s %x' % (fs, x, part, addr, file, size)
+ )
+ assert 'Unable to write' not in output
+ assert 'Error' not in output
+ assert 'overflow' not in output
+ expected_text = '%d bytes written' % size
+ assert expected_text in output
- alignment = int(
- u_boot_console.config.buildconfig.get(
- 'config_sys_cacheline_size', 128
+ alignment = int(
+ u_boot_console.config.buildconfig.get(
+ 'config_sys_cacheline_size', 128
+ )
+ )
+ offset = random.randrange(alignment, 1024, alignment)
+ output = u_boot_console.run_command(
+ '%sload mmc %d:%s %x %s' % (fs, x, part, addr + offset, file)
)
- )
- offset = random.randrange(alignment, 1024, alignment)
- output = u_boot_console.run_command(
- '%sload mmc %d:%s %x %s' % (fs, x, part, addr + offset, file)
- )
- assert 'Invalid FAT entry' not in output
- assert 'Unable to read file' not in output
- assert 'Misaligned buffer address' not in output
- expected_text = '%d bytes read' % size
- assert expected_text in output
+ assert 'Invalid FAT entry' not in output
+ assert 'Unable to read file' not in output
+ assert 'Misaligned buffer address' not in output
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -300,13 +355,16 @@
print('No %s table on this device' % fs.upper())
continue
- u_boot_console.run_command('mmc dev %d' % x)
for part in partitions:
- output = u_boot_console.run_command('%sls mmc %d:%s' % (fs, x, part))
- if 'Unrecognized filesystem type' in output:
- partitions.remove(part)
- pytest.fail('Unrecognized filesystem')
- part_detect = 1
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ output = u_boot_console.run_command(
+ '%sls mmc %d:%s' % (fs, x, part)
+ )
+ if 'Unrecognized filesystem type' in output:
+ partitions.remove(part)
+ pytest.fail('Unrecognized filesystem')
+ part_detect = 1
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -326,7 +384,6 @@
fs = 'ext4'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -334,42 +391,44 @@
continue
for part in partitions:
- part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
- devices[x]['addr_%d' % part] = addr
- size = random.randint(4, 1 * 1024 * 1024)
- devices[x]['size_%d' % part] = size
- # count CRC32
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- expected_crc32 = m.group(1)
- devices[x]['expected_crc32_%d' % part] = expected_crc32
- # do write
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ devices[x]['addr_%d' % part] = addr
+ size = random.randint(4, 1 * 1024 * 1024)
+ devices[x]['size_%d' % part] = size
+ # count CRC32
+ output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ m = re.search('==> (.+?)', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ expected_crc32 = m.group(1)
+ devices[x]['expected_crc32_%d' % part] = expected_crc32
- file = '%s_%d' % ('uboot_test', size)
- devices[x]['file_%d' % part] = file
- output = u_boot_console.run_command(
- '%swrite mmc %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
- )
- assert 'Unable to write' not in output
- assert 'Error' not in output
- assert 'overflow' not in output
- expected_text = '%d bytes written' % size
- assert expected_text in output
+ # do write
+ file = '%s_%d' % ('uboot_test', size)
+ devices[x]['file_%d' % part] = file
+ output = u_boot_console.run_command(
+ '%swrite mmc %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
+ )
+ assert 'Unable to write' not in output
+ assert 'Error' not in output
+ assert 'overflow' not in output
+ expected_text = '%d bytes written' % size
+ assert expected_text in output
- offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
- '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
- )
- expected_text = '%d bytes read' % size
- assert expected_text in output
+ offset = random.randrange(128, 1024, 128)
+ output = u_boot_console.run_command(
+ '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
+ )
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -387,7 +446,6 @@
fs = 'ext2'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -395,12 +453,16 @@
continue
for part in partitions:
- part_detect = 1
- output = u_boot_console.run_command('%sls mmc %d:%s' % (fs, x, part))
- if 'Unrecognized filesystem type' in output:
- partitions.remove(part)
- pytest.fail('Unrecognized filesystem')
- part_detect = 1
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ output = u_boot_console.run_command(
+ '%sls mmc %d:%s' % (fs, x, part)
+ )
+ if 'Unrecognized filesystem type' in output:
+ partitions.remove(part)
+ pytest.fail('Unrecognized filesystem')
+ part_detect = 1
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -421,7 +483,6 @@
fs = 'ext2'
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -429,23 +490,25 @@
continue
for part in partitions:
- part_detect = 1
- addr = devices[x]['addr_%d' % part]
- size = devices[x]['size_%d' % part]
- expected_crc32 = devices[x]['expected_crc32_%d' % part]
- file = devices[x]['file_%d' % part]
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = devices[x]['addr_%d' % part]
+ size = devices[x]['size_%d' % part]
+ expected_crc32 = devices[x]['expected_crc32_%d' % part]
+ file = devices[x]['file_%d' % part]
- offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
- '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
- )
- expected_text = '%d bytes read' % size
- assert expected_text in output
+ offset = random.randrange(128, 1024, 128)
+ output = u_boot_console.run_command(
+ '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
+ )
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@@ -462,8 +525,7 @@
part_detect = 0
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext4', 'ext2']:
try:
partitions = devices[x][fs]
except:
@@ -471,12 +533,14 @@
continue
for part in partitions:
- part_detect = 1
- output = u_boot_console.run_command('ls mmc %d:%s' % (x, part))
- if re.search(r'No \w+ table on this device', output):
- pytest.fail(
- '%s: Partition table not found %d' % (fs.upper(), x)
- )
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ output = u_boot_console.run_command('ls mmc %d:%s' % (x, part))
+ if re.search(r'No \w+ table on this device', output):
+ pytest.fail(
+ '%s: Partition table not found %d' % (fs.upper(), x)
+ )
if not part_detect:
pytest.skip('No partition detected')
@@ -493,8 +557,7 @@
part_detect = 0
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext4', 'ext2']:
try:
partitions = devices[x][fs]
except:
@@ -502,23 +565,25 @@
continue
for part in partitions:
- part_detect = 1
- addr = devices[x]['addr_%d' % part]
- size = devices[x]['size_%d' % part]
- expected_crc32 = devices[x]['expected_crc32_%d' % part]
- file = devices[x]['file_%d' % part]
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = devices[x]['addr_%d' % part]
+ size = devices[x]['size_%d' % part]
+ expected_crc32 = devices[x]['expected_crc32_%d' % part]
+ file = devices[x]['file_%d' % part]
- offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
- 'load mmc %d:%s %x /%s' % (x, part, addr + offset, file)
- )
- expected_text = '%d bytes read' % size
- assert expected_text in output
+ offset = random.randrange(128, 1024, 128)
+ output = u_boot_console.run_command(
+ 'load mmc %d:%s %x /%s' % (x, part, addr + offset, file)
+ )
+ expected_text = '%d bytes read' % size
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr + offset)
- )
- assert expected_crc32 in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr + offset)
+ )
+ assert expected_crc32 in output
if not part_detect:
pytest.skip('No partition detected')
@@ -535,8 +600,7 @@
part_detect = 0
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext4', 'ext2']:
try:
partitions = devices[x][fs]
except:
@@ -544,18 +608,20 @@
continue
for part in partitions:
- part_detect = 1
- addr = devices[x]['addr_%d' % part]
- size = 0
- file = devices[x]['file_%d' % part]
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = devices[x]['addr_%d' % part]
+ size = 0
+ file = devices[x]['file_%d' % part]
- offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
- 'save mmc %d:%s %x /%s %d'
- % (x, part, addr + offset, file, size)
- )
- expected_text = '%d bytes written' % size
- assert expected_text in output
+ offset = random.randrange(128, 1024, 128)
+ output = u_boot_console.run_command(
+ 'save mmc %d:%s %x /%s %d'
+ % (x, part, addr + offset, file, size)
+ )
+ expected_text = '%d bytes written' % size
+ assert expected_text in output
if not part_detect:
pytest.skip('No partition detected')
@@ -582,7 +648,6 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -590,82 +655,86 @@
continue
for part in partitions:
- part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
- count_f = 0
- addr_l = []
- size_l = []
- file_l = []
- crc32_l = []
- offset_l = []
- addr_l.append(addr)
+ for y in mmc_modes:
+ u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ part_detect = 1
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ count_f = 0
+ addr_l = []
+ size_l = []
+ file_l = []
+ crc32_l = []
+ offset_l = []
+ addr_l.append(addr)
- while count_f < num_files:
- size_l.append(random.randint(4, 1 * 1024 * 1024))
+ while count_f < num_files:
+ size_l.append(random.randint(4, 1 * 1024 * 1024))
- # CRC32 count
- output = u_boot_console.run_command(
- 'crc32 %x %x' % (addr_l[count_f], size_l[count_f])
- )
- m = re.search('==> (.+?)', output)
- if not m:
- pytest.fail('CRC32 failed')
- crc32_l.append(m.group(1))
+ # CRC32 count
+ output = u_boot_console.run_command(
+ 'crc32 %x %x' % (addr_l[count_f], size_l[count_f])
+ )
+ m = re.search('==> (.+?)', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ crc32_l.append(m.group(1))
- # Write operation
- file_l.append('%s_%d_%d' % ('uboot_test', count_f, size_l[count_f]))
- output = u_boot_console.run_command(
- '%swrite mmc %d:%s %x %s %x'
- % (
- fs,
- x,
- part,
- addr_l[count_f],
- file_l[count_f],
- size_l[count_f],
+ # Write operation
+ file_l.append(
+ '%s_%d_%d' % ('uboot_test', count_f, size_l[count_f])
)
- )
- assert 'Unable to write' not in output
- assert 'Error' not in output
- assert 'overflow' not in output
- expected_text = '%d bytes written' % size_l[count_f]
- assert expected_text in output
+ output = u_boot_console.run_command(
+ '%swrite mmc %d:%s %x %s %x'
+ % (
+ fs,
+ x,
+ part,
+ addr_l[count_f],
+ file_l[count_f],
+ size_l[count_f],
+ )
+ )
+ assert 'Unable to write' not in output
+ assert 'Error' not in output
+ assert 'overflow' not in output
+ expected_text = '%d bytes written' % size_l[count_f]
+ assert expected_text in output
- addr_l.append(addr_l[count_f] + size_l[count_f] + 1048576)
- count_f += 1
+ addr_l.append(addr_l[count_f] + size_l[count_f] + 1048576)
+ count_f += 1
- count_f = 0
- while count_f < num_files:
- alignment = int(
- u_boot_console.config.buildconfig.get(
- 'config_sys_cacheline_size', 128
+ count_f = 0
+ while count_f < num_files:
+ alignment = int(
+ u_boot_console.config.buildconfig.get(
+ 'config_sys_cacheline_size', 128
+ )
)
- )
- offset_l.append(random.randrange(alignment, 1024, alignment))
+ offset_l.append(random.randrange(alignment, 1024, alignment))
- # Read operation
- output = u_boot_console.run_command(
- '%sload mmc %d:%s %x %s'
- % (
- fs,
- x,
- part,
- addr_l[count_f] + offset_l[count_f],
- file_l[count_f],
+ # Read operation
+ output = u_boot_console.run_command(
+ '%sload mmc %d:%s %x %s'
+ % (
+ fs,
+ x,
+ part,
+ addr_l[count_f] + offset_l[count_f],
+ file_l[count_f],
+ )
)
- )
- assert 'Invalid FAT entry' not in output
- assert 'Unable to read file' not in output
- assert 'Misaligned buffer address' not in output
- expected_text = '%d bytes read' % size_l[count_f]
- assert expected_text in output
+ assert 'Invalid FAT entry' not in output
+ assert 'Unable to read file' not in output
+ assert 'Misaligned buffer address' not in output
+ expected_text = '%d bytes read' % size_l[count_f]
+ assert expected_text in output
- output = u_boot_console.run_command(
- 'crc32 %x $filesize' % (addr_l[count_f] + offset_l[count_f])
- )
- assert crc32_l[count_f] in output
+ output = u_boot_console.run_command(
+ 'crc32 %x $filesize' % (addr_l[count_f] + offset_l[count_f])
+ )
+ assert crc32_l[count_f] in output
- count_f += 1
+ count_f += 1
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
diff --git a/test/py/tests/test_usb.py b/test/py/tests/test_usb.py
index 2397fd3..e1f203b 100644
--- a/test/py/tests/test_usb.py
+++ b/test/py/tests/test_usb.py
@@ -227,7 +227,8 @@
lines = output.split('\n')
part_fat = []
- part_ext = []
+ part_ext2 = []
+ part_ext4 = []
for line in lines:
obj = re.search(r'(\d)\s+\d+\s+\d+\s+\w+\d+\w+-\d+\s+(\d+\w+)', line)
if obj:
@@ -239,15 +240,21 @@
print('Fat detected')
part_fat.append(part_id)
elif part_type == '83':
- print('ext detected')
- part_ext.append(part_id)
+ print('ext(2/4) detected')
+ output = u_boot_console.run_command(
+ 'fstype usb %d:%d' % i, part_id
+ )
+ if 'ext2' in output:
+ part_ext2.append(part_id)
+ elif 'ext4' in output:
+ part_ext4.append(part_id)
else:
pytest.fail('Unsupported Filesystem on device %d' % i)
- devices[i]['ext4'] = part_ext
- devices[i]['ext2'] = part_ext
+ devices[i]['ext4'] = part_ext4
+ devices[i]['ext2'] = part_ext2
devices[i]['fat'] = part_fat
- if not part_ext and not part_fat:
+ if not part_ext2 and not part_ext4 and not part_fat:
pytest.fail('No partition detected on device %d' % i)
return devices, controllers, storage_device
@@ -497,7 +504,7 @@
for part in partitions:
part_detect = 1
file, size, expected_crc32 = \
- usb_ext4load_ext4write(u_boot_console, 'ext4', x, part)
+ usb_ext4load_ext4write(u_boot_console, fs, x, part)
addr = u_boot_utils.find_ram_base(u_boot_console)
offset = random.randrange(128, 1024, 128)
@@ -526,7 +533,7 @@
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
u_boot_console.run_command('usb dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext2', 'ext4']:
try:
partitions = devices[x][fs]
except:
@@ -556,7 +563,7 @@
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
u_boot_console.run_command('usb dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext2', 'ext4']:
try:
partitions = devices[x][fs]
except:
@@ -570,7 +577,7 @@
if fs == 'fat':
file, size, expected_crc32 = \
usb_fatload_fatwrite(u_boot_console, fs, x, part)
- elif fs == 'ext4':
+ elif fs in ['ext4', 'ext2']:
file, size, expected_crc32 = \
usb_ext4load_ext4write(u_boot_console, fs, x, part)
@@ -600,7 +607,7 @@
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
u_boot_console.run_command('usb dev %d' % x)
- for fs in ['fat', 'ext4']:
+ for fs in ['fat', 'ext2', 'ext4']:
try:
partitions = devices[x][fs]
except:
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 6d44191..10ec7e5 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -8,7 +8,6 @@
# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
"""
import collections
-import getpass
import gzip
import os
import os.path
@@ -28,70 +27,36 @@
if not os.path.exists(dirname):
os.mkdir(dirname)
-def setup_image(cons, devnum, part_type, second_part=False, basename='mmc'):
- """Create a 20MB disk image with a single partition
+def setup_image(cons, devnum, part_type, img_size=20, second_part=False,
+ basename='mmc'):
+ """Create a disk image with a single partition
Args:
cons (ConsoleBase): Console to use
devnum (int): Device number to use, e.g. 1
part_type (int): Partition type, e.g. 0xc for FAT32
+ img_size (int): Image size in MiB
second_part (bool): True to contain a small second partition
basename (str): Base name to use in the filename, e.g. 'mmc'
Returns:
tuple:
str: Filename of MMC image
- str: Directory name of 'mnt' directory
+ str: Directory name of scratch directory
"""
fname = os.path.join(cons.config.source_dir, f'{basename}{devnum}.img')
- mnt = os.path.join(cons.config.persistent_data_dir, 'mnt')
+ mnt = os.path.join(cons.config.persistent_data_dir, 'scratch')
mkdir_cond(mnt)
- spec = f'type={part_type:x}, size=18M, bootable'
+ spec = f'type={part_type:x}, size={img_size - 2}M, start=1M, bootable'
if second_part:
spec += '\ntype=c'
u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
- u_boot_utils.run_and_log(cons, f'sudo sfdisk {fname}',
+ u_boot_utils.run_and_log(cons, f'sfdisk {fname}',
stdin=spec.encode('utf-8'))
return fname, mnt
-def mount_image(cons, fname, mnt, fstype):
- """Create a filesystem and mount it on partition 1
-
- Args:
- cons (ConsoleBase): Console to use
- fname (str): Filename of MMC image
- mnt (str): Directory name of 'mnt' directory
- fstype (str): Filesystem type ('vfat' or 'ext4')
-
- Returns:
- str: Name of loop device used
- """
- out = u_boot_utils.run_and_log(cons, f'sudo losetup --show -f -P {fname}')
- loop = out.strip()
- part = f'{loop}p1'
- u_boot_utils.run_and_log(cons, f'sudo mkfs.{fstype} {part}')
- opts = ''
- if fstype == 'vfat':
- opts += f' -o uid={os.getuid()},gid={os.getgid()}'
- u_boot_utils.run_and_log(cons, f'sudo mount -o loop {part} {mnt}{opts}')
- u_boot_utils.run_and_log(cons, f'sudo chown {getpass.getuser()} {mnt}')
- return loop
-
-def copy_prepared_image(cons, devnum, fname, basename='mmc'):
- """Use a prepared image since we cannot create one
-
- Args:
- cons (ConsoleBase): Console touse
- devnum (int): device number
- fname (str): Filename of MMC image
- basename (str): Base name to use in the filename, e.g. 'mmc'
- """
- infname = os.path.join(cons.config.source_dir,
- f'test/py/tests/bootstd/{basename}{devnum}.img.xz')
- u_boot_utils.run_and_log(cons, ['sh', '-c', f'xz -dc {infname} >{fname}'])
-
def setup_bootmenu_image(cons):
"""Create a 20MB disk image with a single ext4 partition
@@ -100,14 +65,7 @@
mmc_dev = 4
fname, mnt = setup_image(cons, mmc_dev, 0x83)
- loop = None
- mounted = False
- complete = False
- try:
- loop = mount_image(cons, fname, mnt, 'ext4')
- mounted = True
-
- script = '''# DO NOT EDIT THIS FILE
+ script = '''# DO NOT EDIT THIS FILE
#
# Please edit /boot/armbianEnv.txt to set supported parameters
#
@@ -181,64 +139,52 @@
# Recompile with:
# mkimage -C none -A arm -T script -d /boot/boot.cmd /boot/boot.scr
'''
- bootdir = os.path.join(mnt, 'boot')
- mkdir_cond(bootdir)
- cmd_fname = os.path.join(bootdir, 'boot.cmd')
- scr_fname = os.path.join(bootdir, 'boot.scr')
- with open(cmd_fname, 'w', encoding='ascii') as outf:
- print(script, file=outf)
-
- infname = os.path.join(cons.config.source_dir,
- 'test/py/tests/bootstd/armbian.bmp.xz')
- bmp_file = os.path.join(bootdir, 'boot.bmp')
- u_boot_utils.run_and_log(
- cons,
- ['sh', '-c', f'xz -dc {infname} >{bmp_file}'])
+ bootdir = os.path.join(mnt, 'boot')
+ mkdir_cond(bootdir)
+ cmd_fname = os.path.join(bootdir, 'boot.cmd')
+ scr_fname = os.path.join(bootdir, 'boot.scr')
+ with open(cmd_fname, 'w', encoding='ascii') as outf:
+ print(script, file=outf)
- u_boot_utils.run_and_log(
- cons, f'mkimage -C none -A arm -T script -d {cmd_fname} {scr_fname}')
-
- kernel = 'vmlinuz-5.15.63-rockchip64'
- target = os.path.join(bootdir, kernel)
- with open(target, 'wb') as outf:
- print('kernel', outf)
+ infname = os.path.join(cons.config.source_dir,
+ 'test/py/tests/bootstd/armbian.bmp.xz')
+ bmp_file = os.path.join(bootdir, 'boot.bmp')
+ u_boot_utils.run_and_log(
+ cons,
+ ['sh', '-c', f'xz -dc {infname} >{bmp_file}'])
- symlink = os.path.join(bootdir, 'Image')
- if os.path.exists(symlink):
- os.remove(symlink)
- u_boot_utils.run_and_log(
- cons, f'echo here {kernel} {symlink}')
- os.symlink(kernel, symlink)
+ mkimage = cons.config.build_dir + '/tools/mkimage'
+ u_boot_utils.run_and_log(
+ cons, f'{mkimage} -C none -A arm -T script -d {cmd_fname} {scr_fname}')
- complete = True
+ kernel = 'vmlinuz-5.15.63-rockchip64'
+ target = os.path.join(bootdir, kernel)
+ with open(target, 'wb') as outf:
+ print('kernel', outf)
- except ValueError as exc:
- print(f'Falled to create image, failing back to prepared copy: {exc}')
- finally:
- if mounted:
- u_boot_utils.run_and_log(cons, f'sudo umount --lazy {mnt}')
- if loop:
- u_boot_utils.run_and_log(cons, f'sudo losetup -d {loop}')
+ symlink = os.path.join(bootdir, 'Image')
+ if os.path.exists(symlink):
+ os.remove(symlink)
+ u_boot_utils.run_and_log(
+ cons, f'echo here {kernel} {symlink}')
+ os.symlink(kernel, symlink)
- if not complete:
- copy_prepared_image(cons, mmc_dev, fname)
+ fsfile = 'ext18M.img'
+ u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}')
+ u_boot_utils.run_and_log(cons, f'mkfs.ext4 {fsfile} -d {mnt}')
+ u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1')
+ u_boot_utils.run_and_log(cons, f'rm -rf {mnt}')
+ u_boot_utils.run_and_log(cons, f'rm -f {fsfile}')
def setup_bootflow_image(cons):
"""Create a 20MB disk image with a single FAT partition"""
mmc_dev = 1
fname, mnt = setup_image(cons, mmc_dev, 0xc, second_part=True)
- loop = None
- mounted = False
- complete = False
- try:
- loop = mount_image(cons, fname, mnt, 'vfat')
- mounted = True
-
- vmlinux = 'vmlinuz-5.3.7-301.fc31.armv7hl'
- initrd = 'initramfs-5.3.7-301.fc31.armv7hl.img'
- dtbdir = 'dtb-5.3.7-301.fc31.armv7hl'
- script = '''# extlinux.conf generated by appliance-creator
+ vmlinux = 'vmlinuz-5.3.7-301.fc31.armv7hl'
+ initrd = 'initramfs-5.3.7-301.fc31.armv7hl.img'
+ dtbdir = 'dtb-5.3.7-301.fc31.armv7hl'
+ script = '''# extlinux.conf generated by appliance-creator
ui menu.c32
menu autoboot Welcome to Fedora-Workstation-armhfp-31-1.9. Automatic boot in # second{,s}. Press a key for options.
menu title Fedora-Workstation-armhfp-31-1.9 Boot Options.
@@ -251,39 +197,36 @@
append ro root=UUID=9732b35b-4cd5-458b-9b91-80f7047e0b8a rhgb quiet LANG=en_US.UTF-8 cma=192MB cma=256MB
fdtdir /%s/
initrd /%s''' % (vmlinux, dtbdir, initrd)
- ext = os.path.join(mnt, 'extlinux')
- mkdir_cond(ext)
+ ext = os.path.join(mnt, 'extlinux')
+ mkdir_cond(ext)
- conf = os.path.join(ext, 'extlinux.conf')
- with open(conf, 'w', encoding='ascii') as fd:
- print(script, file=fd)
+ conf = os.path.join(ext, 'extlinux.conf')
+ with open(conf, 'w', encoding='ascii') as fd:
+ print(script, file=fd)
- inf = os.path.join(cons.config.persistent_data_dir, 'inf')
- with open(inf, 'wb') as fd:
- fd.write(gzip.compress(b'vmlinux'))
- u_boot_utils.run_and_log(
- cons, f'mkimage -f auto -d {inf} {os.path.join(mnt, vmlinux)}')
+ inf = os.path.join(cons.config.persistent_data_dir, 'inf')
+ with open(inf, 'wb') as fd:
+ fd.write(gzip.compress(b'vmlinux'))
+ mkimage = cons.config.build_dir + '/tools/mkimage'
+ u_boot_utils.run_and_log(
+ cons, f'{mkimage} -f auto -d {inf} {os.path.join(mnt, vmlinux)}')
- with open(os.path.join(mnt, initrd), 'w', encoding='ascii') as fd:
- print('initrd', file=fd)
+ with open(os.path.join(mnt, initrd), 'w', encoding='ascii') as fd:
+ print('initrd', file=fd)
- mkdir_cond(os.path.join(mnt, dtbdir))
+ mkdir_cond(os.path.join(mnt, dtbdir))
- dtb_file = os.path.join(mnt, f'{dtbdir}/sandbox.dtb')
- u_boot_utils.run_and_log(
- cons, f'dtc -o {dtb_file}', stdin=b'/dts-v1/; / {};')
- complete = True
- except ValueError as exc:
- print(f'Falled to create image, failing back to prepared copy: {exc}')
- finally:
- if mounted:
- u_boot_utils.run_and_log(cons, f'sudo umount --lazy {mnt}')
- if loop:
- u_boot_utils.run_and_log(cons, f'sudo losetup -d {loop}')
-
- if not complete:
- copy_prepared_image(cons, mmc_dev, fname)
+ dtb_file = os.path.join(mnt, f'{dtbdir}/sandbox.dtb')
+ u_boot_utils.run_and_log(
+ cons, f'dtc -o {dtb_file}', stdin=b'/dts-v1/; / {};')
+ fsfile = 'vfat18M.img'
+ u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}')
+ u_boot_utils.run_and_log(cons, f'mkfs.vfat {fsfile}')
+ u_boot_utils.run_and_log(cons, ['sh', '-c', f'mcopy -i {fsfile} {mnt}/* ::/'])
+ u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1')
+ u_boot_utils.run_and_log(cons, f'rm -rf {mnt}')
+ u_boot_utils.run_and_log(cons, f'rm -f {fsfile}')
def setup_cros_image(cons):
"""Create a 20MB disk image with ChromiumOS partitions"""
@@ -334,8 +277,6 @@
mmc_dev = 5
fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
- #mnt = os.path.join(cons.config.persistent_data_dir, 'mnt')
- #mkdir_cond(mnt)
u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
uuid_state = 'ebd0a0a2-b9e5-4433-87c0-68b6b72699c7'
@@ -501,6 +442,55 @@
print(f'wrote to {fname}')
+ mmc_dev = 8
+ fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
+ u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
+ u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+
+ ptr = 40
+
+ # Number of sectors in 1MB
+ sect_size = 512
+ sect_1mb = (1 << 20) // sect_size
+
+ required_parts = [
+ {'num': 1, 'label':'misc', 'size': '1M'},
+ {'num': 2, 'label':'boot_a', 'size': '4M'},
+ {'num': 3, 'label':'boot_b', 'size': '4M'},
+ ]
+
+ for part in required_parts:
+ size_str = part['size']
+ if 'M' in size_str:
+ size = int(size_str[:-1]) * sect_1mb
+ else:
+ size = int(size_str)
+ u_boot_utils.run_and_log(
+ cons,
+ f"cgpt add -i {part['num']} -b {ptr} -s {size} -l {part['label']} -t basicdata {fname}")
+ ptr += size
+
+ u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
+ out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+
+ # Create a dict (indexed by partition number) containing the above info
+ for line in out.splitlines():
+ start, size, num, name = line.split(maxsplit=3)
+ parts[int(num)] = Partition(int(start), int(size), name)
+
+ with open(fname, 'rb') as inf:
+ disk_data = inf.read()
+
+ test_abootimg.AbootimgTestDiskImage(cons, 'boot.img', test_abootimg.img_hex)
+ boot_img = os.path.join(cons.config.result_dir, 'boot.img')
+ with open(boot_img, 'rb') as inf:
+ set_part_data(2, inf.read())
+
+ with open(fname, 'wb') as outf:
+ outf.write(disk_data)
+
+ print(f'wrote to {fname}')
+
return fname
def setup_cedit_file(cons):
@@ -540,8 +530,8 @@
u_boot_utils.run_and_log(
u_boot_console, f'sfdisk {fn}', stdin=b'type=83')
- fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB')
- fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB')
+ fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB', None)
+ fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB', None)
mmc_dev = 6
fn = os.path.join(u_boot_console.config.source_dir, f'mmc{mmc_dev}.img')
@@ -557,35 +547,23 @@
fname, mnt = setup_image(cons, devnum, 0xc, second_part=True,
basename=basename)
- loop = None
- mounted = False
- complete = False
- try:
- loop = mount_image(cons, fname, mnt, 'ext4')
- mounted = True
- efi_dir = os.path.join(mnt, 'EFI')
- mkdir_cond(efi_dir)
- bootdir = os.path.join(efi_dir, 'BOOT')
- mkdir_cond(bootdir)
- efi_src = os.path.join(cons.config.build_dir,
- f'lib/efi_loader/testapp.efi')
- efi_dst = os.path.join(bootdir, 'BOOTSBOX.EFI')
- with open(efi_src, 'rb') as inf:
- with open(efi_dst, 'wb') as outf:
- outf.write(inf.read())
- complete = True
- except ValueError as exc:
- print(f'Falled to create image, failing back to prepared copy: {exc}')
-
- finally:
- if mounted:
- u_boot_utils.run_and_log(cons, 'sudo umount --lazy %s' % mnt)
- if loop:
- u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
-
- if not complete:
- copy_prepared_image(cons, devnum, fname, basename)
-
+ efi_dir = os.path.join(mnt, 'EFI')
+ mkdir_cond(efi_dir)
+ bootdir = os.path.join(efi_dir, 'BOOT')
+ mkdir_cond(bootdir)
+ efi_src = os.path.join(cons.config.build_dir,
+ 'lib/efi_loader/testapp.efi')
+ efi_dst = os.path.join(bootdir, 'BOOTSBOX.EFI')
+ with open(efi_src, 'rb') as inf:
+ with open(efi_dst, 'wb') as outf:
+ outf.write(inf.read())
+ fsfile = 'vfat18M.img'
+ u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}')
+ u_boot_utils.run_and_log(cons, f'mkfs.vfat {fsfile}')
+ u_boot_utils.run_and_log(cons, ['sh', '-c', f'mcopy -vs -i {fsfile} {mnt}/* ::/'])
+ u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1')
+ u_boot_utils.run_and_log(cons, f'rm -rf {mnt}')
+ u_boot_utils.run_and_log(cons, f'rm -f {fsfile}')
@pytest.mark.buildconfigspec('cmd_bootflow')
@pytest.mark.buildconfigspec('sandbox')
diff --git a/test/py/tests/test_zynqmp_rpu.py b/test/py/tests/test_zynqmp_rpu.py
index 479a612..22f687d 100644
--- a/test/py/tests/test_zynqmp_rpu.py
+++ b/test/py/tests/test_zynqmp_rpu.py
@@ -70,7 +70,7 @@
# Initialize tcm
def tcminit(u_boot_console, rpu_mode):
- output = u_boot_console.run_command('zynqmp tcminit %s' % rpu_mode)
+ output = u_boot_console.run_command(f'zynqmp tcminit {rpu_mode}')
assert 'Initializing TCM overwrites TCM content' in output
return ret_code(u_boot_console)
@@ -89,6 +89,13 @@
for num in cpu_nums:
u_boot_console.run_command(f'cpu {num} disable')
+# Get random RPU mode between string and integer
+def get_rpu_mode(rpu_mode):
+ if rpu_mode == 0 or rpu_mode == 'lockstep':
+ return random.choice(['lockstep', 0])
+ elif rpu_mode == 1 or rpu_mode == 'split':
+ return random.choice(['split', 1])
+
# Load apps on RPU cores
def rpu_apps_load(u_boot_console, rpu_mode):
apps, procs, cpu_nums, addrs, outputs, tftp_addrs = get_rpu_apps_env(
@@ -98,20 +105,20 @@
test_net.test_net_setup_static(u_boot_console)
try:
- assert tcminit(u_boot_console, rpu_mode).endswith('0')
+ assert tcminit(u_boot_console, get_rpu_mode(rpu_mode)).endswith('0')
for i in range(len(apps)):
if rpu_mode == 'lockstep' and procs[i] != 'rpu0':
continue
load_app_ddr(u_boot_console, tftp_addrs[i], apps[i])
- rel_addr = int(addrs[i] + 0x3C)
+ rel_addr = hex(int(addrs[i] + 0x3C))
# Release cpu at app load address
cpu_num = cpu_nums[i]
- cmd = 'cpu %d release %x %s' % (cpu_num, rel_addr, rpu_mode)
+ cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}'
output = u_boot_console.run_command(cmd)
- exp_op = f'Using TCM jump trampoline for address {hex(rel_addr)}'
+ exp_op = f'Using TCM jump trampoline for address {rel_addr}'
assert exp_op in output
assert f'R5 {rpu_mode} mode' in output
u_boot_console.wait_for(outputs[i])
@@ -133,16 +140,13 @@
u_boot_console)
# Invalid commands
- u_boot_console.run_command('zynqmp tcminit mode')
- assert ret_code(u_boot_console).endswith('1')
-
rand_str = ''.join(random.choices(string.ascii_lowercase, k=4))
- u_boot_console.run_command('zynqmp tcminit %s' % rand_str)
- assert ret_code(u_boot_console).endswith('1')
-
rand_num = random.randint(2, 100)
- u_boot_console.run_command('zynqmp tcminit %d' % rand_num)
- assert ret_code(u_boot_console).endswith('1')
+ inv_modes = ['mode', rand_str, rand_num, 'splittt', 'locksteppp', '00', 11]
+
+ for mode in inv_modes:
+ u_boot_console.run_command(f'zynqmp tcminit {mode}')
+ assert ret_code(u_boot_console).endswith('1')
test_net.test_net_dhcp(u_boot_console)
if not test_net.net_set_up:
@@ -150,56 +154,66 @@
try:
rpu_mode = 'split'
- assert tcminit(u_boot_console, rpu_mode).endswith('0')
+ assert tcminit(u_boot_console, get_rpu_mode(rpu_mode)).endswith('0')
+ inv_modes += [0, 1]
for i in range(len(apps)):
load_app_ddr(u_boot_console, tftp_addrs[i], apps[i])
# Run in split mode at different load address
- rel_addr = int(addrs[i]) + random.randint(200, 1000)
+ rel_addr = hex(int(addrs[i]) + random.randint(200, 1000))
cpu_num = cpu_nums[i]
- cmd = 'cpu %d release %x %s' % (cpu_num, rel_addr, rpu_mode)
+ cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}'
output = u_boot_console.run_command(cmd)
- exp_op = f'Using TCM jump trampoline for address {hex(rel_addr)}'
+ exp_op = f'Using TCM jump trampoline for address {rel_addr}'
assert exp_op in output
assert f'R5 {rpu_mode} mode' in output
assert not outputs[i] in output
# Invalid rpu mode
- rand_str = ''.join(random.choices(string.ascii_lowercase, k=4))
- cmd = 'cpu %d release %x %s' % (cpu_num, rel_addr, rand_str)
- output = u_boot_console.run_command(cmd)
- assert exp_op in output
- assert f'Unsupported mode' in output
- assert not ret_code(u_boot_console).endswith('0')
+ for mode in inv_modes:
+ cmd = f'cpu {cpu_num} release {rel_addr} {mode}'
+ output = u_boot_console.run_command(cmd)
+ assert exp_op in output
+ assert f'Unsupported mode' in output
+ assert not ret_code(u_boot_console).endswith('0')
# Switch to lockstep mode, without disabling CPUs
rpu_mode = 'lockstep'
- u_boot_console.run_command('zynqmp tcminit %s' % rpu_mode)
- assert not ret_code(u_boot_console).endswith('0')
+ output = u_boot_console.run_command(
+ f'zynqmp tcminit {get_rpu_mode(rpu_mode)}'
+ )
+ assert 'ERROR: ' in output
# Disable cpus
disable_cpus(u_boot_console, cpu_nums)
# Switch to lockstep mode, after disabling CPUs
- output = u_boot_console.run_command('zynqmp tcminit %s' % rpu_mode)
+ output = u_boot_console.run_command(
+ f'zynqmp tcminit {get_rpu_mode(rpu_mode)}'
+ )
assert 'Initializing TCM overwrites TCM content' in output
assert ret_code(u_boot_console).endswith('0')
- # Run lockstep mode for RPU1
+ # Run lockstep mode for RPU1/RPU0
for i in range(len(apps)):
- if procs[i] == 'rpu0':
- continue
-
load_app_ddr(u_boot_console, tftp_addrs[i], apps[i])
- rel_addr = int(addrs[i] + 0x3C)
+ rel_addr = hex(int(addrs[i] + 0x3C))
cpu_num = cpu_nums[i]
- cmd = 'cpu %d release %x %s' % (cpu_num, rel_addr, rpu_mode)
+ cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}'
output = u_boot_console.run_command(cmd)
- exp_op = f'Using TCM jump trampoline for address {hex(rel_addr)}'
+ exp_op = f'Using TCM jump trampoline for address {rel_addr}'
assert exp_op in output
- assert f'R5 {rpu_mode} mode' in output
- assert u_boot_console.p.expect([outputs[i]])
+
+ if procs[i] == 'rpu1':
+ assert 'Lockstep mode should run on ZYNQMP_CORE_RPU0' in output
+ assert not ret_code(u_boot_console).endswith('0')
+ elif procs[i] == 'rpu0':
+ assert f'R5 {rpu_mode} mode' in output
+ u_boot_console.wait_for(outputs[i])
+ assert ret_code(u_boot_console).endswith('0')
+ else:
+ assert False, 'ERROR: Invalid processor!'
finally:
disable_cpus(u_boot_console, cpu_nums)
# This forces the console object to be shutdown, so any subsequent test
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index fa9cd57..7eaceb3 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -342,11 +342,12 @@
# indentation.
return self.p.before.strip('\r\n')
except Timeout as exc:
- handle_exception(self.config, self, self.log, exc, 'Lab failure',
- True)
+ handle_exception(self.config, self, self.log, exc,
+ f"Lab failure: Timeout executing '{cmd}'", True)
raise
except BootFail as exc:
- handle_exception(self.config, self, self.log, exc, 'Boot fail',
+ handle_exception(self.config, self, self.log, exc,
+ f"'Boot fail '{cmd}'",
True, self.get_spawn_output())
raise
finally:
diff --git a/tools/buildman/boards.py b/tools/buildman/boards.py
index 3c28227..9e7b486 100644
--- a/tools/buildman/boards.py
+++ b/tools/buildman/boards.py
@@ -19,7 +19,10 @@
from buildman import board
from buildman import kconfiglib
+from u_boot_pylib import command
from u_boot_pylib.terminal import print_clear, tprint
+from u_boot_pylib import tools
+from u_boot_pylib import tout
### constant variables ###
OUTPUT_FILE = 'boards.cfg'
@@ -202,6 +205,7 @@
os.environ['KCONFIG_OBJDIR'] = ''
self._tmpfile = None
self._conf = kconfiglib.Kconfig(warn=False)
+ self._srctree = srctree
def __del__(self):
"""Delete a leftover temporary file before exit.
@@ -239,7 +243,26 @@
expect_target, match, rear = leaf.partition('_defconfig')
assert match and not rear, f'{leaf} : invalid defconfig'
- self._conf.load_config(defconfig)
+ temp = None
+ if b'#include' in tools.read_file(defconfig):
+ cmd = [
+ os.getenv('CPP', 'cpp'),
+ '-nostdinc', '-P',
+ '-I', self._srctree,
+ '-undef',
+ '-x', 'assembler-with-cpp',
+ defconfig]
+ result = command.run_pipe([cmd], capture=True, capture_stderr=True)
+ temp = tempfile.NamedTemporaryFile(prefix='buildman-')
+ tools.write_file(temp.name, result.stdout, False)
+ fname = temp.name
+ tout.info(f'Processing #include to produce {defconfig}')
+ else:
+ fname = defconfig
+
+ self._conf.load_config(fname)
+ if temp:
+ del temp
self._tmpfile = None
params = {}
diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst
index e873611..924564b 100644
--- a/tools/buildman/buildman.rst
+++ b/tools/buildman/buildman.rst
@@ -186,23 +186,22 @@
#. Create ~/.buildman to tell buildman where to find tool chains (see
buildman_settings_ for details). As an example::
- # Buildman settings file
+ # Buildman settings file
- [toolchain]
- root: /
- rest: /toolchains/*
- eldk: /opt/eldk-4.2
- arm: /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux
- aarch64: /opt/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.10_linux
+ [toolchain]
+ root: /
+ rest: /toolchains/*
+ eldk: /opt/eldk-4.2
+ arm: /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux
+ aarch64: /opt/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.10_linux
- [toolchain-prefix]
- arc = /opt/arc/arc_gnu_2021.03_prebuilt_elf32_le_linux_install/bin/arc-elf32-
-
- [toolchain-alias]
- riscv = riscv32
- sh = sh4
- x86: i386
+ [toolchain-prefix]
+ arc = /opt/arc/arc_gnu_2021.03_prebuilt_elf32_le_linux_install/bin/arc-elf32-
+ [toolchain-alias]
+ riscv = riscv32
+ sh = sh4
+ x86: i386
This selects the available toolchain paths. Add the base directory for
each of your toolchains here. Buildman will search inside these directories
@@ -934,6 +933,18 @@
For example powerpc-linux-gcc will be noted as a toolchain for 'powerpc'
and CROSS_COMPILE will be set to powerpc-linux- when using it.
+ The tilde character ``~`` is supported in paths, to represent the home
+ directory.
+
+'[toolchain-prefix]' section
+ This can be used to provide the full toolchain-prefix for one or more
+ architectures. The full CROSS_COMPILE prefix must be provided. These
+ typically have a higher priority than matches in the '[toolchain]', due to
+ this prefix.
+
+ The tilde character ``~`` is supported in paths, to represent the home
+ directory.
+
'[toolchain-alias]' section
This converts toolchain architecture names to U-Boot names. For example,
if an x86 toolchains is called i386-linux-gcc it will not normally be
@@ -1112,6 +1123,30 @@
Internally, buildman writes out an out-env file into the build directory for
later comparison.
+defconfig fragments
+-------------------
+
+Buildman provides some initial support for configuration fragments. It can scan
+these when present in defconfig files and handle the resuiting Kconfig
+correctly. Thus it is possible to build a board which has a ``#include`` in the
+defconfig file.
+
+For now, Buildman simply includes the files to produce a single output file,
+using the C preprocessor. It does not call the ``merge_config.sh`` script. The
+redefined/redundant logic in that script could fairly easily be repeated in
+Buildman, to detect potential problems. For now it is not clear that this is
+useful.
+
+To specify the C preprocessor to use, set the ``CPP`` environment variable. The
+default is ``cpp``.
+
+Note that Buildman does not support adding fragments to existing boards, e.g.
+like::
+
+ make qemu_riscv64_defconfig acpi.config
+
+This is partly because there is no way for Buildman to know which fragments are
+valid on which boards.
Building with clang
-------------------
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index 0ac9fc7..4e12c67 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -2,8 +2,10 @@
# Copyright (c) 2014 Google, Inc
#
+import io
import os
from pathlib import Path
+import re
import shutil
import sys
import tempfile
@@ -373,6 +375,22 @@
def _HandleCommandSize(self, args):
return command.CommandResult(return_code=0)
+ def _HandleCommandCpp(self, args):
+ # args ['-nostdinc', '-P', '-I', '/tmp/tmp7f17xk_o/src', '-undef',
+ # '-x', 'assembler-with-cpp', fname]
+ fname = args[7]
+ buf = io.StringIO()
+ for line in tools.read_file(fname, False).splitlines():
+ if line.startswith('#include'):
+ # Example: #include <configs/renesas_rcar2.config>
+ m_incfname = re.match('#include <(.*)>', line)
+ data = tools.read_file(m_incfname.group(1), False)
+ for line in data.splitlines():
+ print(line, file=buf)
+ else:
+ print(line, file=buf)
+ return command.CommandResult(stdout=buf.getvalue(), return_code=0)
+
def _HandleCommand(self, **kwargs):
"""Handle a command execution.
@@ -406,6 +424,8 @@
return self._HandleCommandObjcopy(args)
elif cmd.endswith( 'size'):
return self._HandleCommandSize(args)
+ elif cmd.endswith( 'cpp'):
+ return self._HandleCommandCpp(args)
if not result:
# Not handled, so abort
@@ -1067,3 +1087,68 @@
result = self._RunControl('--print-arch', 'board0')
self.assertEqual('arm\n', stdout.getvalue())
self.assertEqual('', stderr.getvalue())
+
+ def test_kconfig_scanner(self):
+ """Test using the kconfig scanner to determine important values
+
+ Note that there is already a test_scan_defconfigs() which checks the
+ higher-level scan_defconfigs() function. This test checks just the
+ scanner itself
+ """
+ src = self._git_dir
+ scanner = boards.KconfigScanner(src)
+
+ # First do a simple sanity check
+ norm = os.path.join(src, 'board0_defconfig')
+ tools.write_file(norm, 'CONFIG_TARGET_BOARD0=y', False)
+ res = scanner.scan(norm, True)
+ self.assertEqual(({
+ 'arch': 'arm',
+ 'cpu': 'armv7',
+ 'soc': '-',
+ 'vendor': 'Tester',
+ 'board': 'ARM Board 0',
+ 'config': 'config0',
+ 'target': 'board0'}, []), res)
+
+ # Check that the SoC cannot be changed and the filename does not affect
+ # the resulting board
+ tools.write_file(norm, '''CONFIG_TARGET_BOARD2=y
+CONFIG_SOC="fred"
+''', False)
+ res = scanner.scan(norm, True)
+ self.assertEqual(({
+ 'arch': 'powerpc',
+ 'cpu': 'ppc',
+ 'soc': 'mpc85xx',
+ 'vendor': 'Tester',
+ 'board': 'PowerPC board 1',
+ 'config': 'config2',
+ 'target': 'board0'}, []), res)
+
+ # Check handling of missing information
+ tools.write_file(norm, '', False)
+ res = scanner.scan(norm, True)
+ self.assertEqual(({
+ 'arch': '-',
+ 'cpu': '-',
+ 'soc': '-',
+ 'vendor': '-',
+ 'board': '-',
+ 'config': '-',
+ 'target': 'board0'},
+ ['WARNING: board0_defconfig: No TARGET_BOARD0 enabled']), res)
+
+ # check handling of #include files; see _HandleCommandCpp()
+ inc = os.path.join(src, 'common')
+ tools.write_file(inc, b'CONFIG_TARGET_BOARD0=y\n')
+ tools.write_file(norm, f'#include <{inc}>', False)
+ res = scanner.scan(norm, True)
+ self.assertEqual(({
+ 'arch': 'arm',
+ 'cpu': 'armv7',
+ 'soc': '-',
+ 'vendor': 'Tester',
+ 'board': 'ARM Board 0',
+ 'config': 'config0',
+ 'target': 'board0'}, []), res)
diff --git a/tools/buildman/main.py b/tools/buildman/main.py
index 3cf877e..a948f36 100755
--- a/tools/buildman/main.py
+++ b/tools/buildman/main.py
@@ -25,6 +25,7 @@
from buildman import control
from u_boot_pylib import test_util
from u_boot_pylib import tools
+from u_boot_pylib import tout
def run_tests(skip_net_tests, debug, verbose, args):
"""Run the buildman tests
@@ -93,8 +94,12 @@
# Build selected commits for selected boards
else:
- bsettings.setup(args.config_file)
- ret_code = control.do_buildman(args)
+ try:
+ tout.init(tout.INFO if args.verbose else tout.WARNING)
+ bsettings.setup(args.config_file)
+ ret_code = control.do_buildman(args)
+ finally:
+ tout.uninit()
return ret_code
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index 15801f6..385a34e 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -46,6 +46,16 @@
wrapper = ccache
'''
+settings_data_homedir = '''
+# Buildman settings file
+
+[toolchain]
+main = ~/mypath
+
+[toolchain-prefix]
+x86 = ~/mypath-x86-
+'''
+
migration = '''===================== WARNING ======================
This board does not use CONFIG_DM. CONFIG_DM will be
compulsory starting with the v2020.01 release.
@@ -1030,6 +1040,46 @@
finally:
os.environ['PATH'] = old_path
+ def testHomedir(self):
+ """Test using ~ in a toolchain or toolchain-prefix section"""
+ # Add some test settings
+ bsettings.setup(None)
+ bsettings.add_file(settings_data_homedir)
+
+ # Set up the toolchains
+ home = os.path.expanduser('~')
+ toolchains = toolchain.Toolchains()
+ toolchains.GetSettings()
+ self.assertEqual([f'{home}/mypath'], toolchains.paths)
+
+ # Check scanning
+ with test_util.capture_sys_output() as (stdout, _):
+ toolchains.Scan(verbose=True, raise_on_error=False)
+ lines = iter(stdout.getvalue().splitlines() + ['##done'])
+ self.assertEqual('Scanning for tool chains', next(lines))
+ self.assertEqual(f" - scanning prefix '{home}/mypath-x86-'",
+ next(lines))
+ self.assertEqual(
+ f"Error: No tool chain found for prefix '{home}/mypath-x86-gcc'",
+ next(lines))
+ self.assertEqual(f" - scanning path '{home}/mypath'", next(lines))
+ self.assertEqual(f" - looking in '{home}/mypath/.'", next(lines))
+ self.assertEqual(f" - looking in '{home}/mypath/bin'", next(lines))
+ self.assertEqual(f" - looking in '{home}/mypath/usr/bin'",
+ next(lines))
+ self.assertEqual('##done', next(lines))
+
+ # Check adding a toolchain
+ with test_util.capture_sys_output() as (stdout, _):
+ toolchains.Add('~/aarch64-linux-gcc', test=True, verbose=True)
+ lines = iter(stdout.getvalue().splitlines() + ['##done'])
+ self.assertEqual('Tool chain test: BAD', next(lines))
+ self.assertEqual(f'Command: {home}/aarch64-linux-gcc --version',
+ next(lines))
+ self.assertEqual('', next(lines))
+ self.assertEqual('', next(lines))
+ self.assertEqual('##done', next(lines))
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 0c8a4fa..958f36f 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -65,12 +65,13 @@
"""Create a new toolchain object.
Args:
- fname: Filename of the gcc component
+ fname: Filename of the gcc component, possibly with ~ or $HOME in it
test: True to run the toolchain to test it
verbose: True to print out the information
priority: Priority to use for this toolchain, or PRIORITY_CALC to
calculate it
"""
+ fname = os.path.expanduser(fname)
self.gcc = fname
self.path = os.path.dirname(fname)
self.override_toolchain = override_toolchain
@@ -109,7 +110,7 @@
self.priority))
else:
print('BAD')
- print('Command: ', cmd)
+ print(f"Command: {' '.join(cmd)}")
print(result.stdout)
print(result.stderr)
else:
@@ -296,10 +297,11 @@
paths = []
for name, value in toolchains:
+ fname = os.path.expanduser(value)
if '*' in value:
- paths += glob.glob(value)
+ paths += glob.glob(fname)
else:
- paths.append(value)
+ paths.append(fname)
return paths
def GetSettings(self, show_warning=True):
@@ -327,16 +329,17 @@
toolchain = Toolchain(fname, test, verbose, priority, arch,
self.override_toolchain)
add_it = toolchain.ok
- if toolchain.arch in self.toolchains:
- add_it = (toolchain.priority <
- self.toolchains[toolchain.arch].priority)
if add_it:
- self.toolchains[toolchain.arch] = toolchain
- elif verbose:
- print(("Toolchain '%s' at priority %d will be ignored because "
- "another toolchain for arch '%s' has priority %d" %
- (toolchain.gcc, toolchain.priority, toolchain.arch,
- self.toolchains[toolchain.arch].priority)))
+ if toolchain.arch in self.toolchains:
+ add_it = (toolchain.priority <
+ self.toolchains[toolchain.arch].priority)
+ if add_it:
+ self.toolchains[toolchain.arch] = toolchain
+ elif verbose:
+ print(("Toolchain '%s' at priority %d will be ignored because "
+ "another toolchain for arch '%s' has priority %d" %
+ (toolchain.gcc, toolchain.priority, toolchain.arch,
+ self.toolchains[toolchain.arch].priority)))
def ScanPath(self, path, verbose):
"""Scan a path for a valid toolchain
@@ -372,7 +375,7 @@
pathname_list.append(pathname)
return pathname_list
- def Scan(self, verbose):
+ def Scan(self, verbose, raise_on_error=True):
"""Scan for available toolchains and select the best for each arch.
We look for all the toolchains we can file, figure out the
@@ -384,11 +387,12 @@
"""
if verbose: print('Scanning for tool chains')
for name, value in self.prefixes:
- if verbose: print(" - scanning prefix '%s'" % value)
- if os.path.exists(value):
- self.Add(value, True, verbose, PRIORITY_FULL_PREFIX, name)
+ fname = os.path.expanduser(value)
+ if verbose: print(" - scanning prefix '%s'" % fname)
+ if os.path.exists(fname):
+ self.Add(fname, True, verbose, PRIORITY_FULL_PREFIX, name)
continue
- fname = value + 'gcc'
+ fname += 'gcc'
if os.path.exists(fname):
self.Add(fname, True, verbose, PRIORITY_PREFIX_GCC, name)
continue
@@ -396,8 +400,11 @@
for f in fname_list:
self.Add(f, True, verbose, PRIORITY_PREFIX_GCC_PATH, name)
if not fname_list:
- raise ValueError("No tool chain found for prefix '%s'" %
- value)
+ msg = f"No tool chain found for prefix '{fname}'"
+ if raise_on_error:
+ raise ValueError(msg)
+ else:
+ print(f'Error: {msg}')
for path in self.paths:
if verbose: print(" - scanning path '%s'" % path)
fnames = self.ScanPath(path, verbose)
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index 967ac89..ce1ad7c 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -6,33 +6,58 @@
LABEL org.opencontainers.image.authors="Tom Rini <trini@konsulko.com>"
LABEL org.opencontainers.image.description=" This image is for building U-Boot inside a container"
+# Used by docker to set the target platform: valid values are linux/arm64/v8
+# and linux/amd64
+ARG TARGETPLATFORM
+
+# Used by docker to set the build platform: the only valid value is linux/amd64
+ARG BUILDPLATFORM
+
# Make sure apt is happy
ENV DEBIAN_FRONTEND=noninteractive
+# Set architectures to build for (leaving out ARM which is an exception)
+ENV ARCHS="aarch64 arc i386 m68k mips microblaze nios2 powerpc riscv64 riscv32 sh2 x86_64"
+
+# Mirror containing the toolchains
+ENV MIRROR=https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin
+
+# Toolchain version
+ENV TCVER=13.2.0
+
+RUN echo "Building on $BUILDPLATFORM, for target $TARGETPLATFORM"
+
# Add LLVM repository
-RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/*
+RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \
+ --mount=type=cache,target=/var/lib/apt,sharing=locked \
+ apt-get update && apt-get install -y gnupg2 wget xz-utils
RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-17 main | tee /etc/apt/sources.list.d/llvm.list
-# Manually install the kernel.org "Crosstool" based toolchains for gcc-13.2.0
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-arc-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ
+# Create a list of URLs to process, then pass them into a 'while read' loop
+RUN if [ "$TARGETPLATFORM" = "linux/amd64" ]; then HOSTARCH=x86_64; else HOSTARCH=arm64; fi; ( \
+ # Manually install the kernel.org "Crosstool"-based toolchains
+ for arch in $ARCHS; do \
+ echo $MIRROR/$HOSTARCH/$TCVER/${HOSTARCH}-gcc-$TCVER-nolibc-${arch}-linux.tar.xz; \
+ done; \
+ \
+ # Deal with ARM, which has a 'gnueabi' suffix
+ echo $MIRROR/${HOSTARCH}/$TCVER/${HOSTARCH}-gcc-$TCVER-nolibc-arm-linux-gnueabi.tar.xz; \
+ \
+ ) | while read url; do \
+ # Read the URL and unpack it into /opt
+ wget -O - $url | tar -C /opt -xJ; \
+ done
# Manually install other toolchains
-RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz
+RUN if [ "$TARGETPLATFORM" = "linux/amd64" ]; then \
+ wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz; \
+ fi
# Update and install things from apt now
-RUN apt-get update && apt-get install -y \
+RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \
+ --mount=type=cache,target=/var/lib/apt,sharing=locked \
+ apt-get update && apt-get install -y \
automake \
autopoint \
bc \
@@ -54,17 +79,15 @@
flex \
gawk \
gdisk \
+ gettext \
git \
gnu-efi \
gnutls-dev \
graphviz \
- grub-efi-amd64-bin \
- grub-efi-ia32-bin \
help2man \
iasl \
imagemagick \
iputils-ping \
- libc6-i386 \
libconfuse-dev \
libgit2-dev \
libjson-glib-dev \
@@ -82,7 +105,7 @@
libtool \
libudev-dev \
libusb-1.0-0-dev \
- linux-image-kvm \
+ linux-image-generic \
lzma-alone \
lzop \
mount \
@@ -118,8 +141,7 @@
vboot-utils \
xilinx-bootgen \
xxd \
- zip \
- && rm -rf /var/lib/apt/lists/*
+ zip
# Make kernels readable for libguestfs tools to work correctly
RUN chmod +r /boot/vmlinu*
@@ -127,11 +149,9 @@
# Build GRUB UEFI targets for ARM & RISC-V, 32-bit and 64-bit
RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \
cd /tmp/grub && \
- git checkout grub-2.06 && \
+ git checkout grub-2.12 && \
git config --global user.name "GitLab CI Runner" && \
git config --global user.email trini@konsulko.com && \
- git cherry-pick 049efdd72eb7baa7b2bf8884391ee7fe650da5a0 && \
- git cherry-pick 403d6540cd608b2706cfa0cb4713f7e4b490ff45 && \
./bootstrap && \
mkdir -p /opt/grub && \
./configure --target=aarch64 --with-platform=efi \
@@ -141,7 +161,7 @@
TARGET_STRIP=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \
TARGET_NM=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \
TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \
- make && \
+ make -j$(nproc) && \
./grub-mkimage -O arm64-efi -o /opt/grub/grubaa64.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot \
@@ -155,7 +175,7 @@
TARGET_STRIP=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \
TARGET_NM=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \
TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \
- make && \
+ make -j$(nproc) && \
./grub-mkimage -O arm-efi -o /opt/grub/grubarm.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot \
@@ -169,12 +189,34 @@
TARGET_STRIP=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \
TARGET_NM=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \
TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \
- make && \
+ make -j$(nproc) && \
./grub-mkimage -O riscv64-efi -o /opt/grub/grubriscv64.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot \
search search_fs_file search_fs_uuid search_label serial sleep test \
true && \
+ make clean && \
+ ./configure --target=i386 --with-platform=efi \
+ CC=gcc \
+ TARGET_CC=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-gcc \
+ TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-objcopy \
+ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-strip \
+ TARGET_NM=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-nm \
+ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-ranlib && \
+ make -j$(nproc) && \
+ ./grub-mkimage -O i386-efi -o /opt/grub/grub_x86.efi --prefix= -d \
+ grub-core normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd && \
+ make clean && \
+ ./configure --target=x86_64 --with-platform=efi \
+ CC=gcc \
+ TARGET_CC=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-gcc \
+ TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-objcopy \
+ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-strip \
+ TARGET_NM=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-nm \
+ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-ranlib && \
+ make -j$(nproc) && \
+ ./grub-mkimage -O x86_64-efi -o /opt/grub/grub_x64.efi --prefix= -d \
+ grub-core normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd && \
rm -rf /tmp/grub
RUN git clone https://gitlab.com/qemu-project/qemu.git /tmp/qemu && \
@@ -195,7 +237,7 @@
cd /tmp/tf-a/ && \
git checkout v2.10.0 && \
cd tools/fiptool && \
- make && \
+ make -j$(nproc) && \
mkdir -p /usr/local/bin && \
cp fiptool /usr/local/bin && \
rm -rf /tmp/tf-a
@@ -280,9 +322,8 @@
RUN /bin/echo -e "kernelorg = /opt/gcc-13.2.0-nolibc/*" >> ~/.buildman
RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman;
RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
-RUN /bin/echo -e "\nsandbox = x86_64" >> ~/.buildman
RUN /bin/echo -e "\nx86 = i386" >> ~/.buildman;
# Add mkbootimg tool
RUN git clone https://android.googlesource.com/platform/system/tools/mkbootimg /home/uboot/mkbootimg
-ENV PYTHONPATH "${PYTHONPATH}:/home/uboot/mkbootimg"
+ENV PYTHONPATH="${PYTHONPATH}:/home/uboot/mkbootimg"
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 7a06081..15510d3 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -734,7 +734,7 @@
fclose(fd);
if (header.tag != IVT_HEADER_TAG_B0) {
- fprintf(stderr, "header tag mismatched \n");
+ fprintf(stderr, "header tag mismatched file %s\n", img_sp->filename);
exit(EXIT_FAILURE);
} else {
file_off +=
diff --git a/tools/imx_cntr_image.sh b/tools/imx_cntr_image.sh
index 972b95c..07acd38 100755
--- a/tools/imx_cntr_image.sh
+++ b/tools/imx_cntr_image.sh
@@ -14,6 +14,10 @@
continue
fi
+ if [ $f = "spl/u-boot-spl.bin" ]; then
+ continue
+ fi
+
if [ -f $f ]; then
continue
fi