Fixed mips_io_port_base build errors.
This patch has been sent on:
- 29 Sep 2007
Although mips_io_port_base is currently a part of IDE command, it is quite
fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move
it to MIPS general part, and introduce `set_io_port_base()' from Linux.
This patch is triggered by multiple definition of `mips_io_port_base' build
error on gth2 (and tb0229 also needs this fix.)
board/gth2/libgth2.a(gth2.o): In function `log_serial_char':
/home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base'
common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here
make: *** [u-boot] Error 1
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
index d29e8d5..a13eeeb 100644
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -25,6 +25,7 @@
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
+#include <asm/io.h>
long int initdram(int board_type)
{
@@ -77,6 +78,9 @@
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
+
+ set_io_port_base(0);
+
#ifdef CONFIG_IDE_PCMCIA
/* Enable 3.3 V on slot 0 ( VCC )
No 5V */
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index ffeaf58..1593f02 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -26,14 +26,13 @@
#include <asm/au1x00.h>
#include <asm/addrspace.h>
#include <asm/mipsregs.h>
+#include <asm/io.h>
#include <watchdog.h>
#include "ee_access.h"
static int wdi_status = 0;
-unsigned long mips_io_port_base = 0;
-
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
@@ -147,6 +146,9 @@
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
+
+ set_io_port_base(0);
+
#ifdef CONFIG_IDE_PCMCIA
/* PCMCIA is on a 36 bit physical address.
We need to map it into a 32 bit addresses */
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index b5d9e00..dbf0ecc 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -25,7 +25,7 @@
#include <command.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
-
+#include <asm/io.h>
extern uint incaip_get_cpuclk(void);
@@ -85,7 +85,6 @@
int checkboard (void)
{
-
unsigned long chipid = *INCA_IP_WDT_CHIPID;
int part_num;
@@ -107,5 +106,7 @@
printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
+ set_io_port_base(0);
+
return 0;
}
diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
index 40ac2a4..95b7d82 100644
--- a/board/pb1x00/pb1x00.c
+++ b/board/pb1x00/pb1x00.c
@@ -25,6 +25,7 @@
#include <command.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
+#include <asm/io.h>
long int initdram(int board_type)
{
@@ -69,6 +70,9 @@
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
+
+ set_io_port_base(0);
+
#if defined(CONFIG_IDE_PCMCIA) && 0
/* Enable 3.3 V on slot 0 ( VCC )
No 5V */
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 4c3e5b4..74718af 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -26,6 +26,7 @@
#include <asm/inca-ip.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
+#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
@@ -145,6 +146,8 @@
printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
+ set_io_port_base(0);
+
return 0;
}
diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c
index e7914bd..61c2e9b 100644
--- a/board/tb0229/tb0229.c
+++ b/board/tb0229/tb0229.c
@@ -13,10 +13,9 @@
#include <command.h>
#include <asm/addrspace.h>
#include <asm/inca-ip.h>
+#include <asm/io.h>
#include <pci.h>
-unsigned long mips_io_port_base = 0;
-
#if defined(CONFIG_PCI)
static struct pci_controller hose;
@@ -26,17 +25,17 @@
}
#endif
-
long int initdram(int board_type)
{
return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
}
-
int checkboard (void)
{
printf("Board: TANBAC TB0229 ");
printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
+ set_io_port_base(0);
+
return 0;
}