clk: mediatek: mt7986: rename CK to CLK
Rename each entry from CK to CLK to match the include in upstream kernel
linux.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index a44f538..f871f23 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -78,7 +78,7 @@
compatible = "mediatek,mt7986-timer";
reg = <0x10008000 0x1000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_F26M_SEL>;
+ clocks = <&topckgen CLK_TOP_F26M_SEL>;
clock-names = "gpt-clk";
bootph-all;
};
@@ -147,18 +147,18 @@
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_PWM_SEL>,
- <&infracfg CK_INFRA_PWM_BSEL>,
- <&infracfg CK_INFRA_PWM1_CK>,
- <&infracfg CK_INFRA_PWM2_CK>;
- assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
- <&infracfg CK_INFRA_PWM_BSEL>,
- <&infracfg CK_INFRA_PWM1_SEL>,
- <&infracfg CK_INFRA_PWM2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_MPLL_D4>,
- <&topckgen CK_TOP_PWM_SEL>,
- <&topckgen CK_TOP_PWM_SEL>,
- <&topckgen CK_TOP_PWM_SEL>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_SEL>,
+ <&infracfg CLK_INFRA_PWM2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D4>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>;
clock-names = "top", "main", "pwm1", "pwm2";
status = "disabled";
bootph-all;
@@ -168,11 +168,11 @@
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg CK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
- <&topckgen CK_TOP_UART_SEL>;
+ clocks = <&infracfg CLK_INFRA_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
bootph-all;
@@ -182,9 +182,9 @@
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_UART1_CK>;
- assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
+ clocks = <&infracfg CLK_INFRA_UART1_CK>;
+ assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -193,9 +193,9 @@
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_UART2_CK>;
- assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
+ clocks = <&infracfg CLK_INFRA_UART2_CK>;
+ assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -205,14 +205,14 @@
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
- clocks = <&infracfg CK_INFRA_SPINFI1_CK>,
- <&infracfg CK_INFRA_NFI1_CK>,
- <&infracfg CK_INFRA_NFI_HCK_CK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+ <&infracfg CLK_INFRA_NFI1_CK>,
+ <&infracfg CLK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_MPLL_D8>,
- <&topckgen CK_TOP_MPLL_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
+ <&topckgen CLK_TOP_MPLL_D8>;
status = "disabled";
};
@@ -251,12 +251,12 @@
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
- clocks = <&infracfg CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_MPLL_D2>,
- <&topckgen CK_TOP_SPI_SEL>;
+ clocks = <&infracfg CLK_INFRA_SPI0_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
clock-names = "sel-clk", "spi-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -274,13 +274,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
- <&topckgen CK_TOP_EMMC_250M_SEL>,
- <&infracfg CK_INFRA_MSDC_CK>;
- assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
- <&topckgen CK_TOP_EMMC_250M_SEL>;
- assigned-clock-parents = <&fixed_plls CK_APMIXED_MPLL>,
- <&topckgen CK_TOP_NET1PLL_D5_D2>;
+ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
+ <&topckgen CLK_TOP_EMMC_250M_SEL>,
+ <&infracfg CLK_INFRA_MSDC_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
+ <&topckgen CLK_TOP_EMMC_250M_SEL>;
+ assigned-clock-parents = <&fixed_plls CLK_APMIXED_MPLL>,
+ <&topckgen CLK_TOP_NET1PLL_D5_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};