imx9: soc: Configure TRDC for M33 TCM access
On OSCCA part, M33 TCM is used for ROM PATCH and protected by ELE ROM.
So after release TRDC, we need to configure TRDC for M33 TCM,
otherwise A55 can't access the TCM.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 9953c33..fb6de53 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -25,6 +25,7 @@
#define ANATOP_BASE_ADDR 0x44480000UL
#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x42420000
+#define BLK_CTRL_NS_ANOMIX_BASE_ADDR 0x44210000
#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f0000
#define SRC_IPS_BASE_ADDR (0x44460000)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 3ee2f3d..06032f2 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -792,7 +792,7 @@
(struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
struct blk_ctrl_s_aonmix_regs *s_regs =
(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
- u32 val;
+ u32 val, i;
if (m33_is_rom_kicked())
return -EPERM;
@@ -817,6 +817,18 @@
/* Set ELE LP handshake for M33 reset */
setbits_le32(&s_regs->lp_handshake[0], BIT(6));
+ /* OSCCA enabled, reconfigure TRDC for TCM access, otherwise ECC init will raise error */
+ val = readl(BLK_CTRL_NS_ANOMIX_BASE_ADDR + 0x28);
+ if (val & BIT(0)) {
+ trdc_mbc_set_control(0x44270000, 1, 0, 0x6600);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x44270000, 1, 3, 0, i, true, 0);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x44270000, 1, 3, 1, i, true, 0);
+ }
+
/* Clear M33 TCM for ECC */
memset((void *)(ulong)0x201e0000, 0, 0x40000);