| commit | 0603dd2b96a75e8052916b70268ae425db74d092 | [log] [tgz] |
|---|---|---|
| author | Stephen Warren <swarren@nvidia.com> | Wed Jan 03 14:32:33 2018 -0700 |
| committer | Tom Warren <twarren@nvidia.com> | Fri Jan 12 09:52:11 2018 -0700 |
| tree | b2489877c517ff9b3a68eb8d74b5493f44e05618 | |
| parent | eab36059ebd20d50d1005692522bc2363765a30d [diff] |
ARM: Tegra186: mem parsing fixes from downstream Apply a few small fixes for the DTB /memory node parsing from NVIDIA's downstream U-Boot: - Allow arbitrary number of DRAM banks. - Correctly calculate the number of DRAM banks. - Clip PCIe memory in the same way as U-Boot CPU memory use. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>