net: mediatek: use correct register field for SGMII speed selection
The register field for SGMII speed selection is a 2-bit field with
value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
So it's necessary to set both bits instead of just setting/clearing
only the lower bit.
diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
index fd31c78..4f9ae52 100644
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -108,7 +108,8 @@
#define SGMSYS_GEN2_SPEED 0x2028
#define SGMSYS_GEN2_SPEED_V2 0x128
-#define SGMSYS_SPEED_2500 BIT(2)
+#define SGMSYS_SPEED_MASK GENMASK(3, 2)
+#define SGMSYS_SPEED_2500 1
/* USXGMII subsystem config registers */
/* Register to control USXGMII XFI PLL digital */