| commit | 0535efd6cc705d87e50b188a3261792f93d673d1 | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Tue Dec 17 16:39:23 2024 +0800 |
| committer | Tom Rini <trini@konsulko.com> | Tue Dec 31 10:58:52 2024 -0600 |
| tree | 42abfbccbf70c21179e3633c1203818f53f8a080 | |
| parent | 68295d6c71c90d91a6910c4cef1cefb744988f10 [diff] |
net: mediatek: use correct register field for SGMII speed selection The register field for SGMII speed selection is a 2-bit field with value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved). So it's necessary to set both bits instead of just setting/clearing only the lower bit.