tree e4201de6e106653a02a04c13f21cf3685bc878ee
parent e7eaf6291eac8dc1111ba1b15974b7fedb587d06
author York Sun <york.sun@nxp.com> 1512500274 -0800
committer York Sun <york.sun@nxp.com> 1512600852 -0800

powerpc: mpc85xx: Fix static TLB table for SDRAM

Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.

Signed-off-by: York Sun <york.sun@nxp.com>