Merge tag 'xilinx-for-v2024.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
AMD/Xilinx changes for v2024.10-rc1
common:
- spl: Introduce SoC specific init function
xilinx:
- Enable FF-A and NVMEM
- Rename spl_board_init() to spl_soc_init()
zynqmp:
- DT alignments
- Enable reset from SPL
- Enable USB3 for KD240
- Align multiboot register on Kria for proper reboot
- Allow multiboot environment write even in saved environment
- Move zynqmp commands from board/ to arch/
- Clean up xilinx_zynqmp.h
versal:
- Do not prioritize boot device if driver is not enabled
versal-net:
- Setup location for redundant variables in SPI
versal2:
- Add support for new SOC
mmc:
- Fix tap delay for SD on Versal NET
spi:
- Add SPI_NOR_OCTAL_READ flag for mx66uw2g345gx0 flash part
gpio:
- Cover MODEPIN firmware dependency
diff --git a/MAINTAINERS b/MAINTAINERS
index 66783d6..6b32a6d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -534,6 +534,7 @@
F: arch/arm/mach-rockchip/
F: board/amarula/vyasa-rk3288/
F: board/anbernic/rgxx3_rk3566/
+F: board/armsom/sige7-rk3588/
F: board/chipspark/popmetal_rk3288
F: board/engicam/px30_core/
F: board/firefly/
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 14e851b..2be36cf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -52,14 +52,6 @@
dtb-$(CONFIG_MACH_S700) += \
s700-cubieboard7.dtb
-dtb-$(CONFIG_ROCKCHIP_PX30) += \
- px30-evb.dtb \
- px30-firefly.dtb \
- px30-engicam-px30-core-ctouch2.dtb \
- px30-engicam-px30-core-ctouch2-of10.dtb \
- px30-engicam-px30-core-edimm2.2.dtb \
- rk3326-odroid-go2.dtb
-
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
@@ -1197,15 +1189,12 @@
k3-am642-r5-sk.dtb \
k3-am642-r5-phycore-som-2gb.dtb
-dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
- k3-am625-r5-sk.dtb \
- k3-am625-beagleplay.dtb \
+dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-r5-sk.dtb \
k3-am625-r5-beagleplay.dtb \
k3-am625-verdin-r5.dtb \
k3-am625-r5-phycore-som-2gb.dtb
-dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
- k3-am62a7-r5-sk.dtb
+dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb
diff --git a/arch/arm/dts/k3-am62-lp-sk-binman.dtsi b/arch/arm/dts/k3-am62-lp-sk-binman.dtsi
new file mode 100644
index 0000000..18341d0
--- /dev/null
+++ b/arch/arm/dts/k3-am62-lp-sk-binman.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-binman.dtsi"
+#include "k3-am625-sk-binman.dtsi"
+
+#ifdef CONFIG_TARGET_AM625_A53_EVM
+
+#define SPL_AM62_LP_SK_DTB "spl/dts/ti/k3-am62-lp-sk.dtb"
+
+&spl_am625_sk_dtb {
+ filename = SPL_AM62_LP_SK_DTB;
+};
+
+&spl_am625_sk_dtb_unsigned {
+ filename = SPL_AM62_LP_SK_DTB;
+};
+
+#endif
diff --git a/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
new file mode 100644
index 0000000..cbcc7f3
--- /dev/null
+++ b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62x LP SK dts file for SPLs
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am62-lp-sk-binman.dtsi"
+
+/ {
+ chosen {
+ tick-timer = &main_timer0;
+ };
+};
+
+&main_timer0 {
+ clock-frequency = <25000000>;
+};
diff --git a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
new file mode 100644
index 0000000..c255ae6
--- /dev/null
+++ b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
@@ -0,0 +1,2190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file was generated with the
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07
+ * Wed Mar 01 2023 17:52:11 GMT-0600 (Central Standard Time)
+ * DDR Type: LPDDR4
+ * F0 = 50MHz F1 = NA F2 = 800MHz
+ * Density (per channel): 16Gb
+ * Write DBI: Enable
+ * Number of Ranks: 1
+ */
+
+#define DDRSS_PLL_FHS_CNT 3
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x00027100
+#define DDRSS_CTL_12_DATA 0x00186A00
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000640
+#define DDRSS_CTL_15_DATA 0x00027100
+#define DDRSS_CTL_16_DATA 0x00186A00
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000640
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00002020
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x0000040C
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000081C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x0000081C
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x05000804
+#define DDRSS_CTL_45_DATA 0x00000700
+#define DDRSS_CTL_46_DATA 0x09090004
+#define DDRSS_CTL_47_DATA 0x00000203
+#define DDRSS_CTL_48_DATA 0x00320007
+#define DDRSS_CTL_49_DATA 0x09090023
+#define DDRSS_CTL_50_DATA 0x0000190F
+#define DDRSS_CTL_51_DATA 0x00320007
+#define DDRSS_CTL_52_DATA 0x09090023
+#define DDRSS_CTL_53_DATA 0x0900190F
+#define DDRSS_CTL_54_DATA 0x000A0A09
+#define DDRSS_CTL_55_DATA 0x040006DB
+#define DDRSS_CTL_56_DATA 0x09092004
+#define DDRSS_CTL_57_DATA 0x00000C0A
+#define DDRSS_CTL_58_DATA 0x06006DB0
+#define DDRSS_CTL_59_DATA 0x09092006
+#define DDRSS_CTL_60_DATA 0x00000C0A
+#define DDRSS_CTL_61_DATA 0x06006DB0
+#define DDRSS_CTL_62_DATA 0x03042006
+#define DDRSS_CTL_63_DATA 0x04050002
+#define DDRSS_CTL_64_DATA 0x100F100F
+#define DDRSS_CTL_65_DATA 0x01010008
+#define DDRSS_CTL_66_DATA 0x041F1F07
+#define DDRSS_CTL_67_DATA 0x03111103
+#define DDRSS_CTL_68_DATA 0x00001111
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x00130803
+#define DDRSS_CTL_73_DATA 0x000000BB
+#define DDRSS_CTL_74_DATA 0x00000130
+#define DDRSS_CTL_75_DATA 0x00000C28
+#define DDRSS_CTL_76_DATA 0x00000130
+#define DDRSS_CTL_77_DATA 0x00000C28
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x0000000A
+#define DDRSS_CTL_80_DATA 0x00000010
+#define DDRSS_CTL_81_DATA 0x00000098
+#define DDRSS_CTL_82_DATA 0x0000017E
+#define DDRSS_CTL_83_DATA 0x00000098
+#define DDRSS_CTL_84_DATA 0x0000017E
+#define DDRSS_CTL_85_DATA 0x03004000
+#define DDRSS_CTL_86_DATA 0x00001201
+#define DDRSS_CTL_87_DATA 0x00060005
+#define DDRSS_CTL_88_DATA 0x00000006
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x05121208
+#define DDRSS_CTL_91_DATA 0x05030A05
+#define DDRSS_CTL_92_DATA 0x05030C06
+#define DDRSS_CTL_93_DATA 0x01030C06
+#define DDRSS_CTL_94_DATA 0x02010201
+#define DDRSS_CTL_95_DATA 0x00001401
+#define DDRSS_CTL_96_DATA 0x01360014
+#define DDRSS_CTL_97_DATA 0x01360136
+#define DDRSS_CTL_98_DATA 0x00000136
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x05010303
+#define DDRSS_CTL_101_DATA 0x0C040505
+#define DDRSS_CTL_102_DATA 0x06050203
+#define DDRSS_CTL_103_DATA 0x030C0605
+#define DDRSS_CTL_104_DATA 0x05060502
+#define DDRSS_CTL_105_DATA 0x03030306
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00002EC0
+#define DDRSS_CTL_120_DATA 0x00002EC0
+#define DDRSS_CTL_121_DATA 0x00002EC0
+#define DDRSS_CTL_122_DATA 0x00002EC0
+#define DDRSS_CTL_123_DATA 0x00002EC0
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000051D
+#define DDRSS_CTL_126_DATA 0x00030A00
+#define DDRSS_CTL_127_DATA 0x00030A00
+#define DDRSS_CTL_128_DATA 0x00030A00
+#define DDRSS_CTL_129_DATA 0x00030A00
+#define DDRSS_CTL_130_DATA 0x00030A00
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x00005518
+#define DDRSS_CTL_133_DATA 0x00030A00
+#define DDRSS_CTL_134_DATA 0x00030A00
+#define DDRSS_CTL_135_DATA 0x00030A00
+#define DDRSS_CTL_136_DATA 0x00030A00
+#define DDRSS_CTL_137_DATA 0x00030A00
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x00005518
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x03050000
+#define DDRSS_CTL_157_DATA 0x03050305
+#define DDRSS_CTL_158_DATA 0x00000000
+#define DDRSS_CTL_159_DATA 0x08010000
+#define DDRSS_CTL_160_DATA 0x000E0808
+#define DDRSS_CTL_161_DATA 0x01000000
+#define DDRSS_CTL_162_DATA 0x0E080808
+#define DDRSS_CTL_163_DATA 0x00000000
+#define DDRSS_CTL_164_DATA 0x08080801
+#define DDRSS_CTL_165_DATA 0x0000080E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000002
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x0005000A
+#define DDRSS_CTL_193_DATA 0x0404000D
+#define DDRSS_CTL_194_DATA 0x0000000D
+#define DDRSS_CTL_195_DATA 0x005000A0
+#define DDRSS_CTL_196_DATA 0x060600C8
+#define DDRSS_CTL_197_DATA 0x000000C8
+#define DDRSS_CTL_198_DATA 0x005000A0
+#define DDRSS_CTL_199_DATA 0x060600C8
+#define DDRSS_CTL_200_DATA 0x000000C8
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000004
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000024
+#define DDRSS_CTL_209_DATA 0x00000012
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000024
+#define DDRSS_CTL_212_DATA 0x00000012
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000004
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000024
+#define DDRSS_CTL_218_DATA 0x00000012
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000024
+#define DDRSS_CTL_221_DATA 0x00000012
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000031
+#define DDRSS_CTL_225_DATA 0x000000B1
+#define DDRSS_CTL_226_DATA 0x000000B1
+#define DDRSS_CTL_227_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x000000B1
+#define DDRSS_CTL_229_DATA 0x000000B1
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x46004646
+#define DDRSS_CTL_255_DATA 0x00002746
+#define DDRSS_CTL_256_DATA 0x00000027
+#define DDRSS_CTL_257_DATA 0x00000027
+#define DDRSS_CTL_258_DATA 0x00000027
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x0000000F
+#define DDRSS_CTL_264_DATA 0x0000000F
+#define DDRSS_CTL_265_DATA 0x0000000F
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00001000
+#define DDRSS_CTL_271_DATA 0x00000015
+#define DDRSS_CTL_272_DATA 0x00000015
+#define DDRSS_CTL_273_DATA 0x00000010
+#define DDRSS_CTL_274_DATA 0x00000015
+#define DDRSS_CTL_275_DATA 0x00000015
+#define DDRSS_CTL_276_DATA 0x00000020
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000100
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00020000
+#define DDRSS_CTL_306_DATA 0x00400100
+#define DDRSS_CTL_307_DATA 0x00080032
+#define DDRSS_CTL_308_DATA 0x01000200
+#define DDRSS_CTL_309_DATA 0x03200040
+#define DDRSS_CTL_310_DATA 0x00020018
+#define DDRSS_CTL_311_DATA 0x00400100
+#define DDRSS_CTL_312_DATA 0x00180320
+#define DDRSS_CTL_313_DATA 0x00030000
+#define DDRSS_CTL_314_DATA 0x00280028
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x00FFFF00
+#define DDRSS_CTL_322_DATA 0x0B000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x01000100
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x00000000
+#define DDRSS_CTL_331_DATA 0x01030303
+#define DDRSS_CTL_332_DATA 0x00000001
+#define DDRSS_CTL_333_DATA 0x00000000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x01000101
+#define DDRSS_CTL_372_DATA 0x01010001
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x01050503
+#define DDRSS_CTL_375_DATA 0x05020201
+#define DDRSS_CTL_376_DATA 0x08080C0C
+#define DDRSS_CTL_377_DATA 0x00080308
+#define DDRSS_CTL_378_DATA 0x000B030E
+#define DDRSS_CTL_379_DATA 0x000B0310
+#define DDRSS_CTL_380_DATA 0x0B0B0810
+#define DDRSS_CTL_381_DATA 0x01000000
+#define DDRSS_CTL_382_DATA 0x03020301
+#define DDRSS_CTL_383_DATA 0x04000102
+#define DDRSS_CTL_384_DATA 0x1B000004
+#define DDRSS_CTL_385_DATA 0x00000176
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x00000693
+#define DDRSS_CTL_391_DATA 0x00000E9C
+#define DDRSS_CTL_392_DATA 0x03050202
+#define DDRSS_CTL_393_DATA 0x00250201
+#define DDRSS_CTL_394_DATA 0x00001850
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00006D68
+#define DDRSS_CTL_400_DATA 0x0000F320
+#define DDRSS_CTL_401_DATA 0x070D0402
+#define DDRSS_CTL_402_DATA 0x00250405
+#define DDRSS_CTL_403_DATA 0x00001850
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00006D68
+#define DDRSS_CTL_409_DATA 0x0000F320
+#define DDRSS_CTL_410_DATA 0x070D0402
+#define DDRSS_CTL_411_DATA 0x00000405
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x10100600
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00010000
+#define DDRSS_PI_24_DATA 0x280A0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x01010102
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x000000AA
+#define DDRSS_PI_36_DATA 0x00000055
+#define DDRSS_PI_37_DATA 0x000000B5
+#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_39_DATA 0x00000056
+#define DDRSS_PI_40_DATA 0x000000A9
+#define DDRSS_PI_41_DATA 0x000000A9
+#define DDRSS_PI_42_DATA 0x000000B5
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000015
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x03000000
+#define DDRSS_PI_55_DATA 0x00000000
+#define DDRSS_PI_56_DATA 0x00001701
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x0A0A140A
+#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_62_DATA 0x01000210
+#define DDRSS_PI_63_DATA 0x05000404
+#define DDRSS_PI_64_DATA 0x00010001
+#define DDRSS_PI_65_DATA 0x0001000E
+#define DDRSS_PI_66_DATA 0x01010100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x08000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000400
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x0000000A
+#define DDRSS_PI_137_DATA 0x000186A0
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010001
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000800
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00101001
+#define DDRSS_PI_167_DATA 0x00000034
+#define DDRSS_PI_168_DATA 0x00000042
+#define DDRSS_PI_169_DATA 0x00020042
+#define DDRSS_PI_170_DATA 0x02000200
+#define DDRSS_PI_171_DATA 0x00000004
+#define DDRSS_PI_172_DATA 0x0000080C
+#define DDRSS_PI_173_DATA 0x00081C00
+#define DDRSS_PI_174_DATA 0x001C0000
+#define DDRSS_PI_175_DATA 0x00000013
+#define DDRSS_PI_176_DATA 0x000000BB
+#define DDRSS_PI_177_DATA 0x00000130
+#define DDRSS_PI_178_DATA 0x00000C28
+#define DDRSS_PI_179_DATA 0x00000130
+#define DDRSS_PI_180_DATA 0x04000C28
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001501
+#define DDRSS_PI_183_DATA 0x001D001D
+#define DDRSS_PI_184_DATA 0x01000100
+#define DDRSS_PI_185_DATA 0x00000100
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x05050503
+#define DDRSS_PI_188_DATA 0x01010C0C
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x000C0C0A
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x04000000
+#define DDRSS_PI_194_DATA 0x04020808
+#define DDRSS_PI_195_DATA 0x04040204
+#define DDRSS_PI_196_DATA 0x00090031
+#define DDRSS_PI_197_DATA 0x00110039
+#define DDRSS_PI_198_DATA 0x00110039
+#define DDRSS_PI_199_DATA 0x01010101
+#define DDRSS_PI_200_DATA 0x0002000D
+#define DDRSS_PI_201_DATA 0x000200C8
+#define DDRSS_PI_202_DATA 0x010000C8
+#define DDRSS_PI_203_DATA 0x000E000E
+#define DDRSS_PI_204_DATA 0x00C90100
+#define DDRSS_PI_205_DATA 0x010000C9
+#define DDRSS_PI_206_DATA 0x00C900C9
+#define DDRSS_PI_207_DATA 0x32103200
+#define DDRSS_PI_208_DATA 0x01013210
+#define DDRSS_PI_209_DATA 0x0A070601
+#define DDRSS_PI_210_DATA 0x0D09070D
+#define DDRSS_PI_211_DATA 0x0D09070D
+#define DDRSS_PI_212_DATA 0x000C000D
+#define DDRSS_PI_213_DATA 0x00001000
+#define DDRSS_PI_214_DATA 0x00000C00
+#define DDRSS_PI_215_DATA 0x00001000
+#define DDRSS_PI_216_DATA 0x00000C00
+#define DDRSS_PI_217_DATA 0x02001000
+#define DDRSS_PI_218_DATA 0x0016000D
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x000000C8
+#define DDRSS_PI_221_DATA 0x00001900
+#define DDRSS_PI_222_DATA 0x32000056
+#define DDRSS_PI_223_DATA 0x06000101
+#define DDRSS_PI_224_DATA 0x001D0204
+#define DDRSS_PI_225_DATA 0x32120058
+#define DDRSS_PI_226_DATA 0x05000101
+#define DDRSS_PI_227_DATA 0x001D0408
+#define DDRSS_PI_228_DATA 0x32120058
+#define DDRSS_PI_229_DATA 0x05000101
+#define DDRSS_PI_230_DATA 0x00000408
+#define DDRSS_PI_231_DATA 0x05030900
+#define DDRSS_PI_232_DATA 0x00040900
+#define DDRSS_PI_233_DATA 0x0000062B
+#define DDRSS_PI_234_DATA 0x20010004
+#define DDRSS_PI_235_DATA 0x0A0A0A03
+#define DDRSS_PI_236_DATA 0x11090000
+#define DDRSS_PI_237_DATA 0x1009000F
+#define DDRSS_PI_238_DATA 0x000062B8
+#define DDRSS_PI_239_DATA 0x20030023
+#define DDRSS_PI_240_DATA 0x0C0A0C0C
+#define DDRSS_PI_241_DATA 0x11090000
+#define DDRSS_PI_242_DATA 0x1009000F
+#define DDRSS_PI_243_DATA 0x000062B8
+#define DDRSS_PI_244_DATA 0x20030023
+#define DDRSS_PI_245_DATA 0x0C0A0C0C
+#define DDRSS_PI_246_DATA 0x00000000
+#define DDRSS_PI_247_DATA 0x00000176
+#define DDRSS_PI_248_DATA 0x00000E9C
+#define DDRSS_PI_249_DATA 0x00001850
+#define DDRSS_PI_250_DATA 0x0000F320
+#define DDRSS_PI_251_DATA 0x00001850
+#define DDRSS_PI_252_DATA 0x0000F320
+#define DDRSS_PI_253_DATA 0x01360014
+#define DDRSS_PI_254_DATA 0x03030136
+#define DDRSS_PI_255_DATA 0x00000003
+#define DDRSS_PI_256_DATA 0x00000000
+#define DDRSS_PI_257_DATA 0x05030503
+#define DDRSS_PI_258_DATA 0x00000503
+#define DDRSS_PI_259_DATA 0x00002710
+#define DDRSS_PI_260_DATA 0x000186A0
+#define DDRSS_PI_261_DATA 0x00000005
+#define DDRSS_PI_262_DATA 0x00000064
+#define DDRSS_PI_263_DATA 0x00000014
+#define DDRSS_PI_264_DATA 0x00027100
+#define DDRSS_PI_265_DATA 0x000186A0
+#define DDRSS_PI_266_DATA 0x00000005
+#define DDRSS_PI_267_DATA 0x00000640
+#define DDRSS_PI_268_DATA 0x00000136
+#define DDRSS_PI_269_DATA 0x00027100
+#define DDRSS_PI_270_DATA 0x000186A0
+#define DDRSS_PI_271_DATA 0x00000005
+#define DDRSS_PI_272_DATA 0x00000640
+#define DDRSS_PI_273_DATA 0x01000136
+#define DDRSS_PI_274_DATA 0x00320040
+#define DDRSS_PI_275_DATA 0x00010008
+#define DDRSS_PI_276_DATA 0x03200040
+#define DDRSS_PI_277_DATA 0x00010018
+#define DDRSS_PI_278_DATA 0x03200040
+#define DDRSS_PI_279_DATA 0x00000318
+#define DDRSS_PI_280_DATA 0x00280028
+#define DDRSS_PI_281_DATA 0x03040404
+#define DDRSS_PI_282_DATA 0x00000303
+#define DDRSS_PI_283_DATA 0x02020101
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000000
+#define DDRSS_PI_286_DATA 0x55000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x3C00005A
+#define DDRSS_PI_289_DATA 0x00005500
+#define DDRSS_PI_290_DATA 0x00005A00
+#define DDRSS_PI_291_DATA 0x0D100F3C
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000000
+#define DDRSS_PI_298_DATA 0x00000004
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000031
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00100F27
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x00000024
+#define DDRSS_PI_307_DATA 0x00000012
+#define DDRSS_PI_308_DATA 0x000000B1
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00000000
+#define DDRSS_PI_311_DATA 0x46000000
+#define DDRSS_PI_312_DATA 0x00150F27
+#define DDRSS_PI_313_DATA 0x00000000
+#define DDRSS_PI_314_DATA 0x00000024
+#define DDRSS_PI_315_DATA 0x00000012
+#define DDRSS_PI_316_DATA 0x000000B1
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00000000
+#define DDRSS_PI_319_DATA 0x46000000
+#define DDRSS_PI_320_DATA 0x00150F27
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000004
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000031
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00100F27
+#define DDRSS_PI_329_DATA 0x00000000
+#define DDRSS_PI_330_DATA 0x00000024
+#define DDRSS_PI_331_DATA 0x00000012
+#define DDRSS_PI_332_DATA 0x000000B1
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000000
+#define DDRSS_PI_335_DATA 0x46000000
+#define DDRSS_PI_336_DATA 0x00150F27
+#define DDRSS_PI_337_DATA 0x00000000
+#define DDRSS_PI_338_DATA 0x00000024
+#define DDRSS_PI_339_DATA 0x00000012
+#define DDRSS_PI_340_DATA 0x000000B1
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00000000
+#define DDRSS_PI_343_DATA 0x46000000
+#define DDRSS_PI_344_DATA 0x00150F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01000000
+#define DDRSS_PHY_6_DATA 0x03000400
+#define DDRSS_PHY_7_DATA 0x00000001
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x01010000
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00001
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660601
+#define DDRSS_PHY_16_DATA 0x00000003
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00071020
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000001
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CC0B01
+#define DDRSS_PHY_75_DATA 0x1003CC0B
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x00100303
+#define DDRSS_PHY_80_DATA 0x00000000
+#define DDRSS_PHY_81_DATA 0x00000000
+#define DDRSS_PHY_82_DATA 0x00021000
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_88_DATA 0x51516041
+#define DDRSS_PHY_89_DATA 0x31C06000
+#define DDRSS_PHY_90_DATA 0x07AB0340
+#define DDRSS_PHY_91_DATA 0x0000C0C0
+#define DDRSS_PHY_92_DATA 0x04050000
+#define DDRSS_PHY_93_DATA 0x00000504
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C1D
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x007A0120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001CC
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000005
+#define DDRSS_PHY_103_DATA 0x76543210
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x034C034C
+#define DDRSS_PHY_106_DATA 0x034C034C
+#define DDRSS_PHY_107_DATA 0x034C034C
+#define DDRSS_PHY_108_DATA 0x034C034C
+#define DDRSS_PHY_109_DATA 0x0000034C
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01800080
+#define DDRSS_PHY_120_DATA 0x01000000
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x0000F0F0
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01000000
+#define DDRSS_PHY_262_DATA 0x03000400
+#define DDRSS_PHY_263_DATA 0x00000001
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x01010000
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00001
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660601
+#define DDRSS_PHY_272_DATA 0x00000003
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00071020
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CC0B01
+#define DDRSS_PHY_331_DATA 0x1003CC0B
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x00100303
+#define DDRSS_PHY_336_DATA 0x00000000
+#define DDRSS_PHY_337_DATA 0x00000000
+#define DDRSS_PHY_338_DATA 0x00021000
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_344_DATA 0x51516041
+#define DDRSS_PHY_345_DATA 0x31C06000
+#define DDRSS_PHY_346_DATA 0x07AB0340
+#define DDRSS_PHY_347_DATA 0x0000C0C0
+#define DDRSS_PHY_348_DATA 0x04050000
+#define DDRSS_PHY_349_DATA 0x00000504
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C1D
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x007A0120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001CC
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000005
+#define DDRSS_PHY_359_DATA 0x76543210
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x034C034C
+#define DDRSS_PHY_362_DATA 0x034C034C
+#define DDRSS_PHY_363_DATA 0x034C034C
+#define DDRSS_PHY_364_DATA 0x034C034C
+#define DDRSS_PHY_365_DATA 0x0000034C
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01800080
+#define DDRSS_PHY_376_DATA 0x01000000
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x0000F0F0
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000200
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00400000
+#define DDRSS_PHY_524_DATA 0x00000080
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x03000000
+#define DDRSS_PHY_527_DATA 0x00200000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x0000002A
+#define DDRSS_PHY_533_DATA 0x00000015
+#define DDRSS_PHY_534_DATA 0x00000015
+#define DDRSS_PHY_535_DATA 0x0000002A
+#define DDRSS_PHY_536_DATA 0x00000033
+#define DDRSS_PHY_537_DATA 0x0000000C
+#define DDRSS_PHY_538_DATA 0x0000000C
+#define DDRSS_PHY_539_DATA 0x00000033
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x003F0000
+#define DDRSS_PHY_542_DATA 0x000F013F
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000803E
+#define DDRSS_PHY_553_DATA 0x00000003
+#define DDRSS_PHY_554_DATA 0x00000002
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000200
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00400000
+#define DDRSS_PHY_780_DATA 0x00000080
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x03000000
+#define DDRSS_PHY_783_DATA 0x00200000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x0000002A
+#define DDRSS_PHY_789_DATA 0x00000015
+#define DDRSS_PHY_790_DATA 0x00000015
+#define DDRSS_PHY_791_DATA 0x0000002A
+#define DDRSS_PHY_792_DATA 0x00000033
+#define DDRSS_PHY_793_DATA 0x0000000C
+#define DDRSS_PHY_794_DATA 0x0000000C
+#define DDRSS_PHY_795_DATA 0x00000033
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000803E
+#define DDRSS_PHY_809_DATA 0x00000003
+#define DDRSS_PHY_810_DATA 0x00000002
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x0000002A
+#define DDRSS_PHY_1045_DATA 0x00000015
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x0000002A
+#define DDRSS_PHY_1048_DATA 0x00000033
+#define DDRSS_PHY_1049_DATA 0x0000000C
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x00000033
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10000000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000803E
+#define DDRSS_PHY_1065_DATA 0x00000003
+#define DDRSS_PHY_1066_DATA 0x00000002
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00010100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000000
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x00002001
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x01010100
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00041B42
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07030101
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000076
+#define DDRSS_PHY_1334_DATA 0x00000400
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00040198
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x0001F7C2
+#define DDRSS_PHY_1372_DATA 0x00020002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x03020000
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03000300
+#define DDRSS_PHY_1382_DATA 0x03000300
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x3183BF77
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000DFF
+#define DDRSS_PHY_1390_DATA 0x30000DFF
+#define DDRSS_PHY_1391_DATA 0x3F0DFF11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x780DFFCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x00018011
+#define DDRSS_PHY_1396_DATA 0x0089FF00
+#define DDRSS_PHY_1397_DATA 0x000C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x000C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x3F0DFF11
+#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1403_DATA 0x00018011
+#define DDRSS_PHY_1404_DATA 0x0089FF00
+#define DDRSS_PHY_1405_DATA 0x20040004
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
deleted file mode 100644
index e9cffca..0000000
--- a/arch/arm/dts/k3-am62-main.dtsi
+++ /dev/null
@@ -1,1058 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC Family Main Domain peripherals
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_main {
- oc_sram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x00 0x70000000 0x00 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x70000000 0x10000>;
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0xc0000>, /* GICR */
- <0x00 0x01880000 0x00 0xc0000>, /* GICR */
- <0x01 0x00000000 0x00 0x2000>, /* GICC */
- <0x01 0x00010000 0x00 0x1000>, /* GICH */
- <0x01 0x00020000 0x00 0x2000>; /* GICV */
- /*
- * vcpumntirq:
- * virtual CPU interface maintenance interrupt
- */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- main_conf: bus@100000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x00100000 0x20000>;
-
- phy_gmii_sel: phy@4044 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4044 0x8>;
- #phy-cells = <1>;
- };
-
- epwm_tbclk: clock-controller@4130 {
- compatible = "ti,am62-epwm-tbclk";
- reg = <0x4130 0x4>;
- #clock-cells = <1>;
- };
-
- audio_refclk0: clock-controller@82e0 {
- compatible = "ti,am62-audio-refclk";
- reg = <0x82e0 0x4>;
- clocks = <&k3_clks 157 0>;
- assigned-clocks = <&k3_clks 157 0>;
- assigned-clock-parents = <&k3_clks 157 8>;
- #clock-cells = <0>;
- };
-
- audio_refclk1: clock-controller@82e4 {
- compatible = "ti,am62-audio-refclk";
- reg = <0x82e4 0x4>;
- clocks = <&k3_clks 157 10>;
- assigned-clocks = <&k3_clks 157 10>;
- assigned-clock-parents = <&k3_clks 157 18>;
- #clock-cells = <0>;
- };
- };
-
- dmss: bus@48000000 {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- dma-ranges;
- ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
-
- ti,sci-dev-id = <25>;
-
- secure_proxy_main: mailbox@4d000000 {
- bootph-all;
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x4d000000 0x00 0x80000>,
- <0x00 0x4a600000 0x00 0x80000>,
- <0x00 0x4a400000 0x00 0x80000>;
- interrupt-names = "rx_012";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- inta_main_dmss: interrupt-controller@48000000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x48000000 0x00 0x100000>;
- #interrupt-cells = <0>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- msi-controller;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <28>;
- ti,interrupt-ranges = <4 68 36>;
- ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
- };
-
- main_bcdma: dma-controller@485c0100 {
- compatible = "ti,am64-dmss-bcdma";
- reg = <0x00 0x485c0100 0x00 0x100>,
- <0x00 0x4c000000 0x00 0x20000>,
- <0x00 0x4a820000 0x00 0x20000>,
- <0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>,
- <0x00 0x48600000 0x00 0x8000>,
- <0x00 0x484a4000 0x00 0x2000>,
- <0x00 0x484c2000 0x00 0x2000>,
- <0x00 0x48420000 0x00 0x2000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "bchan";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <3>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <26>;
- ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
- ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
- ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
- };
-
- main_pktdma: dma-controller@485c0000 {
- compatible = "ti,am64-dmss-pktdma";
- reg = <0x00 0x485c0000 0x00 0x100>,
- <0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
- <0x00 0x485e0000 0x00 0x10000>,
- <0x00 0x484a0000 0x00 0x2000>,
- <0x00 0x484c0000 0x00 0x2000>,
- <0x00 0x48430000 0x00 0x1000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "rflow";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <2>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <30>;
- ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
- <0x24>, /* CPSW_TX_CHAN */
- <0x25>, /* SAUL_TX_0_CHAN */
- <0x26>; /* SAUL_TX_1_CHAN */
- ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
- <0x11>, /* RING_CPSW_TX_CHAN */
- <0x12>, /* RING_SAUL_TX_0_CHAN */
- <0x13>; /* RING_SAUL_TX_1_CHAN */
- ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
- <0x2b>, /* CPSW_RX_CHAN */
- <0x2d>, /* SAUL_RX_0_CHAN */
- <0x2f>, /* SAUL_RX_1_CHAN */
- <0x31>, /* SAUL_RX_2_CHAN */
- <0x33>; /* SAUL_RX_3_CHAN */
- ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
- <0x2c>, /* FLOW_CPSW_RX_CHAN */
- <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
- <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
- };
- };
-
- dmsc: system-controller@44043000 {
- bootph-all;
- compatible = "ti,k2g-sci";
- ti,host-id = <12>;
- mbox-names = "rx", "tx";
- mboxes = <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
- reg-names = "debug_messages";
- reg = <0x00 0x44043000 0x00 0xfe0>;
-
- k3_pds: power-controller {
- bootph-all;
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- };
-
- k3_clks: clock-controller {
- bootph-all;
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- bootph-all;
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
- };
-
- crypto: crypto@40900000 {
- compatible = "ti,am62-sa3ul";
- reg = <0x00 0x40900000 0x00 0x1200>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
-
- dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
- <&main_pktdma 0x7507 0>;
- dma-names = "tx", "rx1", "rx2";
- };
-
- secure_proxy_sa3: mailbox@43600000 {
- bootph-pre-ram;
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x43600000 0x00 0x10000>,
- <0x00 0x44880000 0x00 0x20000>,
- <0x00 0x44860000 0x00 0x20000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- main_pmx0: pinctrl@f4000 {
- bootph-all;
- compatible = "pinctrl-single";
- reg = <0x00 0xf4000 0x00 0x2ac>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_esm: esm@420000 {
- bootph-pre-ram;
- compatible = "ti,j721e-esm";
- reg = <0x00 0x420000 0x00 0x1000>;
- ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
- };
-
- main_timer0: timer@2400000 {
- bootph-all;
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 36 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 36 2>;
- assigned-clock-parents = <&k3_clks 36 3>;
- power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 37 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 37 2>;
- assigned-clock-parents = <&k3_clks 37 3>;
- power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 38 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 38 2>;
- assigned-clock-parents = <&k3_clks 38 3>;
- power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 39 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 39 2>;
- assigned-clock-parents = <&k3_clks 39 3>;
- power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 40 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 40 2>;
- assigned-clock-parents = <&k3_clks 40 3>;
- power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 41 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 41 2>;
- assigned-clock-parents = <&k3_clks 41 3>;
- power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 42 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 42 2>;
- assigned-clock-parents = <&k3_clks 42 3>;
- power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 43 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 43 2>;
- assigned-clock-parents = <&k3_clks 43 3>;
- power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 146 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 152 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 153 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart3: serial@2830000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02830000 0x00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 154 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart4: serial@2840000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02840000 0x00 0x100>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 155 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart5: serial@2850000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02850000 0x00 0x100>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 156 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart6: serial@2860000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02860000 0x00 0x100>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 158 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_i2c0: i2c@20000000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20000000 0x00 0x100>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c1: i2c@20010000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20010000 0x00 0x100>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 103 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c2: i2c@20020000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20020000 0x00 0x100>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 104 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c3: i2c@20030000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20030000 0x00 0x100>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 105 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_spi0: spi@20100000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x20100000 0x00 0x400>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 141 0>;
- status = "disabled";
- };
-
- main_spi1: spi@20110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20110000 0x00 0x400>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 142 0>;
- status = "disabled";
- };
-
- main_spi2: spi@20120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20120000 0x00 0x400>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 143 0>;
- status = "disabled";
- };
-
- main_gpio_intr: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x00a00000 0x00 0x800>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <3>;
- ti,interrupt-ranges = <0 32 16>;
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00600000 0x0 0x100>;
- gpio-ranges = <&main_pmx0 0 0 32>,
- <&main_pmx0 32 33 38>,
- <&main_pmx0 70 72 22>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <190>, <191>, <192>,
- <193>, <194>, <195>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <92>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 77 0>;
- clock-names = "gpio";
- };
-
- main_gpio1: gpio@601000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00601000 0x0 0x100>;
- gpio-controller;
- gpio-ranges = <&main_pmx0 0 94 41>,
- <&main_pmx0 41 136 6>,
- <&main_pmx0 47 143 3>,
- <&main_pmx0 50 149 2>;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <180>, <181>, <182>,
- <183>, <184>, <185>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <52>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 78 0>;
- clock-names = "gpio";
- };
-
- sdhci0: mmc@fa10000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
- clock-names = "clk_ahb", "clk_xin";
- assigned-clocks = <&k3_clks 57 6>;
- assigned-clock-parents = <&k3_clks 57 8>;
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-ddr52 = <0x5>;
- ti,otap-del-sel-hs200 = <0x5>;
- ti,itap-del-sel-legacy = <0xa>;
- ti,itap-del-sel-mmc-hs = <0x1>;
- status = "disabled";
- };
-
- sdhci1: mmc@fa00000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x8>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x4>;
- ti,itap-del-sel-legacy = <0xa>;
- ti,itap-del-sel-sd-hs = <0x1>;
- ti,itap-del-sel-sdr12 = <0xa>;
- ti,itap-del-sel-sdr25 = <0x1>;
- status = "disabled";
- };
-
- sdhci2: mmc@fa20000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x8>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0x0>;
- ti,otap-del-sel-sdr25 = <0x0>;
- ti,otap-del-sel-sdr50 = <0x8>;
- ti,otap-del-sel-sdr104 = <0x7>;
- ti,otap-del-sel-ddr50 = <0x8>;
- ti,itap-del-sel-legacy = <0xa>;
- ti,itap-del-sel-sd-hs = <0xa>;
- ti,itap-del-sel-sdr12 = <0xa>;
- ti,itap-del-sel-sdr25 = <0x1>;
- status = "disabled";
- };
-
- usbss0: dwc3-usb@f900000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f900000 0x00 0x800>;
- clocks = <&k3_clks 161 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb0: usb@31000000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31000000 0x00 0x50000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- snps,usb2-gadget-lpm-disable;
- snps,usb2-lpm-disable;
- };
- };
-
- usbss1: dwc3-usb@f910000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f910000 0x00 0x800>;
- clocks = <&k3_clks 162 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb1: usb@31100000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31100000 0x00 0x50000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- snps,usb2-gadget-lpm-disable;
- snps,usb2-lpm-disable;
- };
- };
-
- fss: bus@fc00000 {
- compatible = "simple-bus";
- reg = <0x00 0x0fc00000 0x00 0x70000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ospi0: spi@fc40000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x00 0x0fc40000 0x00 0x100>,
- <0x05 0x00000000 0x01 0x00000000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 75 7>;
- assigned-clocks = <&k3_clks 75 7>;
- assigned-clock-parents = <&k3_clks 75 8>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- gpu: gpu@fd00000 {
- compatible = "ti,am62-gpu", "img,img-axe";
- reg = <0x00 0x0fd00000 0x00 0x20000>;
- clocks = <&k3_clks 187 0>;
- clock-names = "core";
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
- };
-
- cpsw3g: ethernet@8000000 {
- compatible = "ti,am642-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x00 0x08000000 0x00 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
- clocks = <&k3_clks 13 0>;
- assigned-clocks = <&k3_clks 13 3>;
- assigned-clock-parents = <&k3_clks 13 11>;
- clock-names = "fck";
- power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&main_pktdma 0xc600 15>,
- <&main_pktdma 0xc601 15>,
- <&main_pktdma 0xc602 15>,
- <&main_pktdma 0xc603 15>,
- <&main_pktdma 0xc604 15>,
- <&main_pktdma 0xc605 15>,
- <&main_pktdma 0xc606 15>,
- <&main_pktdma 0xc607 15>,
- <&main_pktdma 0x4600 15>;
- dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
- "tx7", "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- phys = <&phy_gmii_sel 1>;
- mac-address = [00 00 00 00 00 00];
- ti,syscon-efuse = <&wkup_conf 0x200>;
- };
-
- cpsw_port2: port@2 {
- reg = <2>;
- ti,mac-only;
- label = "port2";
- phys = <&phy_gmii_sel 2>;
- mac-address = [00 00 00 00 00 00];
- };
- };
-
- cpsw3g_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x00 0xf00 0x00 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 13 0>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpts@3d000 {
- compatible = "ti,j721e-cpts";
- reg = <0x00 0x3d000 0x00 0x400>;
- clocks = <&k3_clks 13 3>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- dss: dss@30200000 {
- compatible = "ti,am625-dss";
- reg = <0x00 0x30200000 0x00 0x1000>, /* common */
- <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
- <0x00 0x30206000 0x00 0x1000>, /* vid */
- <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
- <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
- <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
- <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
- <0x00 0x30201000 0x00 0x1000>; /* common1 */
- reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2", "common1";
- power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 186 6>,
- <&dss_vp1_clk>,
- <&k3_clks 186 2>;
- clock-names = "fck", "vp1", "vp2";
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
- dss_ports: ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- hwspinlock: spinlock@2a000000 {
- compatible = "ti,am64-hwspinlock";
- reg = <0x00 0x2a000000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster0: mailbox@29000000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29000000 0x00 0x200>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- ecap0: pwm@23100000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23100000 0x00 0x100>;
- power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 51 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap1: pwm@23110000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23110000 0x00 0x100>;
- power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 52 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap2: pwm@23120000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23120000 0x00 0x100>;
- power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 53 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_mcan0: can@20701000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x20701000 0x00 0x200>,
- <0x00 0x20708000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_rti0: watchdog@e000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e000000 0x00 0x100>;
- clocks = <&k3_clks 125 0>;
- power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 125 0>;
- assigned-clock-parents = <&k3_clks 125 2>;
- };
-
- main_rti1: watchdog@e010000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e010000 0x00 0x100>;
- clocks = <&k3_clks 126 0>;
- power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 126 0>;
- assigned-clock-parents = <&k3_clks 126 2>;
- };
-
- main_rti2: watchdog@e020000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e020000 0x00 0x100>;
- clocks = <&k3_clks 127 0>;
- power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 127 0>;
- assigned-clock-parents = <&k3_clks 127 2>;
- };
-
- main_rti3: watchdog@e030000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e030000 0x00 0x100>;
- clocks = <&k3_clks 128 0>;
- power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 128 0>;
- assigned-clock-parents = <&k3_clks 128 2>;
- };
-
- main_rti15: watchdog@e0f0000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e0f0000 0x00 0x100>;
- clocks = <&k3_clks 130 0>;
- power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 130 0>;
- assigned-clock-parents = <&k3_clks 130 2>;
- };
-
- epwm0: pwm@23000000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23000000 0x00 0x100>;
- power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm1: pwm@23010000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23010000 0x00 0x100>;
- power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm2: pwm@23020000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23020000 0x00 0x100>;
- power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- mcasp0: audio-controller@2b00000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b00000 0x00 0x2000>,
- <0x00 0x02b08000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 190 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 190 0>;
- assigned-clock-parents = <&k3_clks 190 2>;
- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp1: audio-controller@2b10000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b10000 0x00 0x2000>,
- <0x00 0x02b18000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 191 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 191 0>;
- assigned-clock-parents = <&k3_clks 191 2>;
- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp2: audio-controller@2b20000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b20000 0x00 0x2000>,
- <0x00 0x02b28000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 192 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 192 0>;
- assigned-clock-parents = <&k3_clks 192 2>;
- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- ti_csi2rx0: ticsi2rx@30102000 {
- compatible = "ti,j721e-csi2rx-shim";
- dmas = <&main_bcdma 0 0x4700 0>;
- dma-names = "rx0";
- reg = <0x00 0x30102000 0x00 0x1000>;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- cdns_csi2rx0: csi-bridge@30101000 {
- compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
- reg = <0x00 0x30101000 0x00 0x1000>;
- clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
- <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
- clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
- phys = <&dphy0>;
- phy-names = "dphy";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- csi0_port0: port@0 {
- reg = <0>;
- status = "disabled";
- };
-
- csi0_port1: port@1 {
- reg = <1>;
- status = "disabled";
- };
-
- csi0_port2: port@2 {
- reg = <2>;
- status = "disabled";
- };
-
- csi0_port3: port@3 {
- reg = <3>;
- status = "disabled";
- };
-
- csi0_port4: port@4 {
- reg = <4>;
- status = "disabled";
- };
- };
- };
- };
-
- dphy0: phy@30110000 {
- compatible = "cdns,dphy-rx";
- reg = <0x00 0x30110000 0x00 0x1100>;
- #phy-cells = <0>;
- power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
-};
diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi
deleted file mode 100644
index e66d486..0000000
--- a/arch/arm/dts/k3-am62-mcu.dtsi
+++ /dev/null
@@ -1,176 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC Family MCU Domain peripherals
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu {
- mcu_pmx0: pinctrl@4084000 {
- bootph-all;
- compatible = "pinctrl-single";
- reg = <0x00 0x04084000 0x00 0x88>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- mcu_esm: esm@4100000 {
- bootph-pre-ram;
- compatible = "ti,j721e-esm";
- reg = <0x00 0x4100000 0x00 0x1000>;
- ti,esm-pins = <0>, <1>, <2>, <85>;
- };
-
- /*
- * The MCU domain timer interrupts are routed only to the ESM module,
- * and not currently available for Linux. The MCU domain timers are
- * of limited use without interrupts, and likely reserved by the ESM.
- */
- mcu_timer0: timer@4800000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4800000 0x00 0x400>;
- clocks = <&k3_clks 35 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer1: timer@4810000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4810000 0x00 0x400>;
- clocks = <&k3_clks 48 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer2: timer@4820000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4820000 0x00 0x400>;
- clocks = <&k3_clks 49 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer3: timer@4830000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4830000 0x00 0x400>;
- clocks = <&k3_clks 50 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_uart0: serial@4a00000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x04a00000 0x00 0x100>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 149 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- mcu_i2c0: i2c@4900000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x04900000 0x00 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 106 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcu_spi0: spi@4b00000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x04b00000 0x00 0x400>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 147 0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@4b10000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x04b10000 0x00 0x400>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 148 0>;
- status = "disabled";
- };
-
- mcu_gpio_intr: interrupt-controller@4210000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x04210000 0x00 0x200>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <5>;
- ti,interrupt-ranges = <0 104 4>;
- };
-
- mcu_gpio0: gpio@4201000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x4201000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&mcu_gpio_intr>;
- interrupts = <30>, <31>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <24>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 79 0>;
- clock-names = "gpio";
- };
-
- mcu_rti0: watchdog@4880000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x04880000 0x00 0x100>;
- clocks = <&k3_clks 131 0>;
- power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 131 0>;
- assigned-clock-parents = <&k3_clks 131 2>;
- /* Tightly coupled to M4F */
- status = "reserved";
- };
-
- mcu_mcan0: can@4e08000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e08000 0x00 0x200>,
- <0x00 0x4e00000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- mcu_mcan1: can@4e18000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e18000 0x00 0x200>,
- <0x00 0x4e10000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts
new file mode 100644
index 0000000..ec5d3f4
--- /dev/null
+++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62x LP SK dts file for R5 SPL
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am62-lp-sk.dts"
+#include "k3-am62-lp4-50-800-800.dtsi"
+#include "k3-am62-ddr.dtsi"
+
+#include "k3-am62-lp-sk-u-boot.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ serial0 = &wkup_uart0;
+ serial3 = &main_uart1;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <36>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ bootph-pre-ram;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&secure_proxy_sa3 {
+ /* We require this for boot handshake */
+ status = "okay";
+};
+
+&cbass_main {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>,
+ <&secure_proxy_sa3 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-pre-ram;
+ };
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ status = "okay";
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-am62-thermal.dtsi b/arch/arm/dts/k3-am62-thermal.dtsi
deleted file mode 100644
index 12ba833..0000000
--- a/arch/arm/dts/k3-am62-thermal.dtsi
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/thermal/thermal.h>
-
-thermal_zones: thermal-zones {
- main0_thermal: main0-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 0>;
-
- trips {
- main0_crit: main0-crit {
- temperature = <105000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- main1_thermal: main1-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 1>;
-
- trips {
- main1_crit: main1-crit {
- temperature = <105000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-};
diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi
deleted file mode 100644
index 23ce1bf..0000000
--- a/arch/arm/dts/k3-am62-wakeup.dtsi
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/bus/ti-sysc.h>
-
-&cbass_wakeup {
- wkup_conf: syscon@43000000 {
- bootph-all;
- compatible = "syscon", "simple-mfd";
- reg = <0x00 0x43000000 0x00 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x43000000 0x20000>;
-
- chipid: chipid@14 {
- bootph-all;
- compatible = "ti,am654-chipid";
- reg = <0x14 0x4>;
- };
- };
-
- target-module@2b300050 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x00 0x2b300050 0x00 0x4>,
- <0x00 0x2b300054 0x00 0x4>,
- <0x00 0x2b300058 0x00 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- ti,no-reset-on-init;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x2b300000 0x100000>;
-
- wkup_uart0: serial@0 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- };
-
- wkup_i2c0: i2c@2b200000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2b200000 0x00 0x100>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 107 4>;
- clock-names = "fck";
- status = "disabled";
- };
-
- wkup_rtc0: rtc@2b1f0000 {
- compatible = "ti,am62-rtc";
- reg = <0x00 0x2b1f0000 0x00 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
- clock-names = "vbus", "osc32k";
- power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
- wakeup-source;
- };
-
- wkup_rti0: watchdog@2b000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2b000000 0x00 0x100>;
- clocks = <&k3_clks 132 0>;
- power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 132 0>;
- assigned-clock-parents = <&k3_clks 132 2>;
- /* Used by DM firmware */
- status = "reserved";
- };
-
- wkup_vtm0: temperature-sensor@b00000 {
- compatible = "ti,j7200-vtm";
- reg = <0x00 0xb00000 0x00 0x400>,
- <0x00 0xb01000 0x00 0x400>;
- power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-};
diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi
deleted file mode 100644
index f0781f2..0000000
--- a/arch/arm/dts/k3-am62.dtsi
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62 SoC Family
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
- model = "Texas Instruments K3 AM625 SoC";
- compatible = "ti,am625";
- interrupt-parent = <&gic500>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- psci: psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
- };
-
- a53_timer0: timer-cl0-cpu0 {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
- };
-
- pmu: pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cbass_main: bus@f0000 {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
-
- ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
- <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
- <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
- <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
- <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
- <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
- <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
- <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
- <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
- <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
- <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
- <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
- <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
- <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
- <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
- <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
- <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
- <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
- <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
- <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
- <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
- <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
-
- /* MCU Domain Range */
- <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
-
- /* Wakeup Domain Range */
- <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
- <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
-
- cbass_mcu: bus@4000000 {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
- };
-
- cbass_wakeup: bus@b00000 {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
- <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
- };
- };
-
- dss_vp1_clk: clock-divider-oldi {
- compatible = "fixed-factor-clock";
- clocks = <&k3_clks 186 0>;
- #clock-cells = <0>;
- clock-div = <7>;
- clock-mult = <1>;
- };
-
- #include "k3-am62-thermal.dtsi"
-};
-
-/* Now include the peripherals for each bus segments */
-#include "k3-am62-main.dtsi"
-#include "k3-am62-mcu.dtsi"
-#include "k3-am62-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index 9ac4a82..1766adc 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -66,9 +66,9 @@
#ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY
#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
-#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
+#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/ti/k3-am625-beagleplay.dtb"
#define UBOOT_NODTB "u-boot-nodtb.bin"
-#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb"
+#define AM625_BEAGLEPLAY_DTB "dts/upstream/src/arm64/ti/k3-am625-beagleplay.dtb"
&binman {
ti-dm {
@@ -214,6 +214,33 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See beagleplay.h
+#define BEAGLEPLAY_SPL_IMAGE_GUID_STR "b2e7cc49-1a5a-4036-ae01-3387c3bef657"
+#define BEAGLEPLAY_UBOOT_IMAGE_GUID_STR "92c92b11-a7ee-486f-aaa2-713d84425b0e"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = BEAGLEPLAY_SPL_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tispl.bin_unsigned";
+ };
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = BEAGLEPLAY_UBOOT_IMAGE_GUID_STR;
+
+ blob {
+ filename = "u-boot.img_unsigned";
+ };
+ };
+};
+
#endif
&main_bcdma {
diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts
deleted file mode 100644
index 8ab838f..0000000
--- a/arch/arm/dts/k3-am625-beagleplay.dts
+++ /dev/null
@@ -1,932 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * https://beagleplay.org/
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "k3-am625.dtsi"
-
-/ {
- compatible = "beagle,am625-beagleplay", "ti,am625";
- model = "BeagleBoard.org BeaglePlay";
-
- aliases {
- ethernet0 = &cpsw_port1;
- ethernet1 = &cpsw_port2;
- gpio0 = &main_gpio0;
- gpio1 = &main_gpio1;
- gpio2 = &mcu_gpio0;
- i2c0 = &main_i2c0;
- i2c1 = &main_i2c1;
- i2c2 = &main_i2c2;
- i2c3 = &main_i2c3;
- i2c4 = &wkup_i2c0;
- i2c5 = &mcu_i2c0;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- mmc2 = &sdhci2;
- rtc0 = &rtc;
- serial0 = &main_uart5;
- serial1 = &main_uart6;
- serial2 = &main_uart0;
- usb0 = &usb0;
- usb1 = &usb1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- memory@80000000 {
- bootph-pre-ram;
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ramoops: ramoops@9ca00000 {
- compatible = "ramoops";
- reg = <0x00 0x9ca00000 0x00 0x00100000>;
- record-size = <0x8000>;
- console-size = <0x8000>;
- ftrace-size = <0x00>;
- pmsg-size = <0x8000>;
- };
-
- secure_tfa_ddr: tfa@9e780000 {
- reg = <0x00 0x9e780000 0x00 0x80000>;
- no-map;
- };
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>;
- no-map;
- };
-
- wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9db00000 0x00 0xc00000>;
- no-map;
- };
- };
-
- vsys_5v0: regulator-1 {
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vsys_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_3v3: regulator-2 {
- /* output of TLV62595DMQR-U12 */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vdd_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vsys_5v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- wlan_en: regulator-3 {
- /* OUTPUT of SN74AVC2T244DQMR */
- compatible = "regulator-fixed";
- regulator-name = "wlan_en";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- enable-active-high;
- regulator-always-on;
- vin-supply = <&vdd_3v3>;
- gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_en_pins_default>;
- };
-
- vdd_3v3_sd: regulator-4 {
- /* output of TPS22918DBVR-U21 */
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_3v3_sd_pins_default>;
-
- compatible = "regulator-fixed";
- regulator-name = "vdd_3v3_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- regulator-always-on;
- vin-supply = <&vdd_3v3>;
- gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_sd_dv: regulator-5 {
- bootph-all;
- compatible = "regulator-gpio";
- regulator-name = "sd_hs200_switch";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_sd_dv_pins_default>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- vin-supply = <&ldo1_reg>;
- gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- };
-
- leds {
- bootph-all;
- compatible = "gpio-leds";
-
- led-0 {
- bootph-all;
- gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- function = LED_FUNCTION_HEARTBEAT;
- default-state = "off";
- };
-
- led-1 {
- bootph-all;
- gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "disk-activity";
- function = LED_FUNCTION_DISK_ACTIVITY;
- default-state = "keep";
- };
-
- led-2 {
- bootph-all;
- gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_CPU;
- };
-
- led-3 {
- bootph-all;
- gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_LAN;
- };
-
- led-4 {
- bootph-all;
- gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_WLAN;
- };
- };
-
- gpio_keys: gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&usr_button_pins_default>;
-
- usr: button-usr {
- label = "User Key";
- linux,code = <BTN_0>;
- gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>;
- };
-
- };
-
- hdmi0: connector-hdmi {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&it66121_out>;
- };
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "it66121 HDMI";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&hdmi_dailink_master>;
- simple-audio-card,frame-master = <&hdmi_dailink_master>;
-
- hdmi_dailink_master: simple-audio-card,cpu {
- sound-dai = <&mcasp1>;
- system-clock-direction-out;
- };
-
- simple-audio-card,codec {
- sound-dai = <&it66121>;
- };
- };
-
-};
-
-&main_pmx0 {
- gpio0_pins_default: gpio0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
- AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
- AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */
- AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */
- AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */
- AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */
- AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */
- AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */
- AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */
- AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */
- AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */
- AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */
- AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */
- AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */
- >;
- };
-
- vdd_sd_dv_pins_default: vdd-sd-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
- >;
- };
-
- usr_button_pins_default: usr-button-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */
- >;
- };
-
- grove_pins_default: grove-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
- AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
- >;
- };
-
- local_i2c_pins_default: local-i2c-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
- AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
- >;
- };
-
- i2c2_1v8_pins_default: i2c2-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
- AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
- >;
- };
-
- mdio0_pins_default: mdio0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
- AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
- AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */
- AM62X_IOPAD(0x018c, PIN_INPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */
- >;
- };
-
- rgmii1_pins_default: rgmii1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
- AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
- AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
- AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
- AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
- AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
- AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
- AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
- AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
- AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
- AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
- AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
- >;
- };
-
- emmc_pins_default: emmc-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
- AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
- AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
- AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
- AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
- AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
- AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
- AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
- AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
- AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
- >;
- };
-
- vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
- >;
- };
-
- sd_pins_default: sd-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
- AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
- AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
- AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
- AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
- AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
- AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */
- >;
- };
-
- wifi_pins_default: wifi-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */
- AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */
- AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */
- AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */
- AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */
- AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */
- AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */
- AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */
- >;
- };
-
- wifi_en_pins_default: wifi-en-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */
- >;
- };
-
- wifi_wlirq_pins_default: wifi-wlirq-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */
- >;
- };
-
- spe_pins_default: spe-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */
- AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */
- AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */
- AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */
- AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */
- AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */
- AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */
- AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */
- AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */
- AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */
- >;
- };
-
- mikrobus_i2c_pins_default: mikrobus-i2c-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */
- AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */
- >;
- };
-
- mikrobus_uart_pins_default: mikrobus-uart-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */
- AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */
- >;
- };
-
- mikrobus_spi_pins_default: mikrobus-spi-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
- AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
- AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */
- AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
- >;
- };
-
- mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
- AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
- AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
- >;
- };
-
- main_uart0_pins_default: main-uart0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
- AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
- >;
- };
-
- wifi_debug_uart_pins_default: wifi-debug-uart-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */
- AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */
- >;
- };
-
- usb1_pins_default: usb1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */
- >;
- };
-
- pmic_irq_pins_default: pmic-irq-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */
- >;
- };
-
- hdmi_gpio_pins_default: hdmi-gpio-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0094, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */
- AM62X_IOPAD(0x0054, PIN_OUTPUT_PULLUP, 7) /* (P21) GPMC0_AD6.GPIO0_21 */
- >;
- };
-
- mcasp_hdmi_pins_default: mcasp-hdmi-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
- AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */
- AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */
- AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */
- AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVn_ALE.MCASP1_AXR2 */
- AM62X_IOPAD(0x007c, PIN_INPUT, 2) /* (P25) GPMC0_CLK.MCASP1_AXR3 */
- >;
- };
-
- dss0_pins_default: dss0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
- AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
- AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
- AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
- AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
- AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
- AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
- AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
- AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
- AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
- AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
- AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
- AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
- AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
- AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
- AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
- AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
- AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
- AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
- AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
- AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
- AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
- AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
- AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
- AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
- AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
- AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
- AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
- >;
- };
-};
-
-&mcu_pmx0 {
- i2c_qwiic_pins_default: i2c-qwiic-default-pins {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */
- AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */
- >;
- };
-
- gbe_pmx_obsclk: gbe-pmx-obsclk-default-pins {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */
- >;
- };
-
- i2c_csi_pins_default: i2c-csi-default-pins {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */
- AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */
- >;
- };
-
- wifi_32k_clk: mcu-clk-out-default-pins {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */
- >;
- };
-};
-
-&a53_opp_table {
- /* Requires VDD_CORE to be at 0.85V */
- opp-1400000000 {
- opp-hz = /bits/ 64 <1400000000>;
- opp-supported-hw = <0x01 0x0004>;
- };
-};
-
-&wkup_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_csi_pins_default>;
- clock-frequency = <400000>;
- /* Enable with overlay for camera sensor */
-};
-
-&mcu_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_qwiic_pins_default>;
- clock-frequency = <100000>;
- status = "okay";
-};
-
-&usbss0 {
- bootph-all;
- ti,vbus-divider;
- status = "okay";
-};
-
-&usb0 {
- bootph-all;
- dr_mode = "peripheral";
-};
-
-&usbss1 {
- ti,vbus-divider;
- status = "okay";
-};
-
-&usb1 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins_default>;
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>,
- <&gbe_pmx_obsclk>;
- assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>;
- assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>;
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
- phy-mode = "rmii";
- phy-handle = <&cpsw3g_phy1>;
-};
-
-&cpsw3g_mdio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mdio0_pins_default>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- reg = <0>;
- reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <50000>;
- };
-
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
- reset-assert-us = <25>;
- reset-deassert-us = <60000>; /* T2 */
- };
-};
-
-&main_gpio0 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&gpio0_pins_default>;
- gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */
- "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */
- "EEPROM_WP", /* 10 */
- "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */
- "CC1352P7_BOOT", "CC1352P7_RSTN", "GBE_RSTN", "", "", /* 13-17 */
- "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */
- "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */
- "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */
- "", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */
- "", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */
- "", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */
- "", "", "", "", "", "", /* 79-84 */
- "BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */
- "", "", "", "", ""; /* 87-91 */
-};
-
-&main_gpio1 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&mikrobus_gpio_pins_default>;
- gpio-line-names = "", "", "", "", "", /* 0-4 */
- "SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */
- "MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */
- "MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */
- "MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */
- "MIKROBUS_GPIO1_14", /* 14 */
- "", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */
- "MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */
- "MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */
- "", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */
- "", "", "", "", "", "", "", "", "", "", /* 38-47 */
- "SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */
-};
-
-&main_i2c0 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&local_i2c_pins_default>;
- clock-frequency = <400000>;
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c32";
- reg = <0x50>;
- };
-
- rtc: rtc@68 {
- compatible = "ti,bq32000";
- reg = <0x68>;
- interrupt-parent = <&main_gpio0>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- };
-
- tps65219: pmic@30 {
- bootph-all;
- compatible = "ti,tps65219";
- reg = <0x30>;
- buck1-supply = <&vsys_5v0>;
- buck2-supply = <&vsys_5v0>;
- buck3-supply = <&vsys_5v0>;
- ldo1-supply = <&vdd_3v3>;
- ldo2-supply = <&buck2_reg>;
- ldo3-supply = <&vdd_3v3>;
- ldo4-supply = <&vdd_3v3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_irq_pins_default>;
- interrupt-parent = <&gic500>;
- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- system-power-controller;
- ti,power-button;
-
- regulators {
- buck1_reg: buck1 {
- regulator-name = "VDD_CORE";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck2_reg: buck2 {
- regulator-name = "VDD_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck3_reg: buck3 {
- regulator-name = "VDD_1V2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- /*
- * Regulator is left as is unused, vdd_sd
- * is controlled via GPIO with bypass config
- * as per the NVM configuration
- */
- regulator-name = "VDD_SD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-allow-bypass;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2_reg: ldo2 {
- regulator-name = "VDDA_0V85";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3_reg: ldo3 {
- regulator-name = "VDDA_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4_reg: ldo4 {
- regulator-name = "VDD_2V5";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&main_i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&grove_pins_default>;
- clock-frequency = <100000>;
- status = "okay";
-};
-
-&main_i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_1v8_pins_default>;
- clock-frequency = <100000>;
- status = "okay";
-
- it66121: bridge-hdmi@4c {
- compatible = "ite,it66121";
- reg = <0x4c>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_gpio_pins_default>;
- vcn33-supply = <&vdd_3v3>;
- vcn18-supply = <&buck2_reg>;
- vrf12-supply = <&buck3_reg>;
- reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&main_gpio0>;
- interrupts = <36 IRQ_TYPE_EDGE_FALLING>;
- #sound-dai-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- it66121_in: endpoint {
- bus-width = <24>;
- remote-endpoint = <&dpi1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- it66121_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&main_i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mikrobus_i2c_pins_default>;
- clock-frequency = <400000>;
- status = "okay";
-};
-
-&main_spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mikrobus_spi_pins_default>;
- status = "okay";
-};
-
-&sdhci0 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_pins_default>;
- disable-wp;
- status = "okay";
-};
-
-&sdhci1 {
- /* SD/MMC */
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&sd_pins_default>;
-
- vmmc-supply = <&vdd_3v3_sd>;
- vqmmc-supply = <&vdd_sd_dv>;
- disable-wp;
- cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
- cd-debounce-delay-ms = <100>;
- ti,fails-without-test-cd;
- status = "okay";
-};
-
-&sdhci2 {
- vmmc-supply = <&wlan_en>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>;
- non-removable;
- ti,fails-without-test-cd;
- cap-power-off-card;
- keep-power-in-suspend;
- assigned-clocks = <&k3_clks 157 158>;
- assigned-clock-parents = <&k3_clks 157 160>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- wlcore: wlcore@2 {
- compatible = "ti,wl1807";
- reg = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_wlirq_pins_default>;
- interrupt-parent = <&main_gpio0>;
- interrupts = <41 IRQ_TYPE_EDGE_FALLING>;
- };
-};
-
-&main_uart0 {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_uart1 {
- /* Main UART1 is used by TIFS firmware */
- status = "reserved";
-};
-
-&main_uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&mikrobus_uart_pins_default>;
- status = "okay";
-};
-
-&main_uart6 {
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_debug_uart_pins_default>;
- status = "okay";
-
- mcu {
- compatible = "ti,cc1352p7";
- reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
- vdds-supply = <&vdd_3v3>;
- };
-};
-
-&dss {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&dss0_pins_default>;
-};
-
-&dss_ports {
- /* VP2: DPI Output */
- port@1 {
- reg = <1>;
-
- dpi1_out: endpoint {
- remote-endpoint = <&it66121_in>;
- };
- };
-};
-
-&mcasp1 {
- status = "okay";
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcasp_hdmi_pins_default>;
- auxclk-fs-ratio = <2177>;
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 0 0 0
- 0 0 0 0
- 0 0 0 0
- 0 0 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
-};
diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts
index 9db58f0..162d480 100644
--- a/arch/arm/dts/k3-am625-r5-beagleplay.dts
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -114,3 +114,18 @@
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See beagleplay.h
+#define BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR "0e225a09-f720-4d57-9120-e28f737f5a5e"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tiboot3-am62x-gp-evm.bin";
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi
index eddf055..534eb14 100644
--- a/arch/arm/dts/k3-am625-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am625-sk-binman.dtsi
@@ -137,11 +137,22 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See am62x_evm.h
+#define AM62X_SK_TIBOOT3_IMAGE_GUID_STR "abcb83d2-9cb6-4351-b8f1-6494bbe3700a"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = AM62X_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_AM625_A53_EVM
-#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb"
+#define SPL_AM625_SK_DTB "spl/dts/ti/k3-am625-sk.dtb"
#define AM625_SK_DTB "u-boot.dtb"
&binman {
@@ -453,4 +464,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See am62x_evm.h
+#define AM62X_SK_SPL_IMAGE_GUID_STR "aee355fc-bf97-4264-8c82-437255efdc1d"
+#define AM62X_SK_UBOOT_IMAGE_GUID_STR "28ab8c6c-fca8-41d3-8ea1-5f171b7d2929"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = AM62X_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = AM62X_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts
deleted file mode 100644
index ae81ebb..0000000
--- a/arch/arm/dts/k3-am625-sk.dts
+++ /dev/null
@@ -1,299 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * AM625 SK: https://www.ti.com/lit/zip/sprr448
- *
- * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-am62x-sk-common.dtsi"
-
-/ {
- compatible = "ti,am625-sk", "ti,am625";
- model = "Texas Instruments AM625 SK";
-
- opp-table {
- /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
- opp-1400000000 {
- opp-hz = /bits/ 64 <1400000000>;
- opp-supported-hw = <0x01 0x0004>;
- clock-latency-ns = <6000000>;
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
- };
-
- vmain_pd: regulator-0 {
- /* TPS65988 PD CONTROLLER OUTPUT */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vmain_pd";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_5v0: regulator-1 {
- /* Output of LM34936 */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vcc_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vmain_pd>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_3v3_sys: regulator-2 {
- /* output of LM61460-Q1 */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sys";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vmain_pd>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: regulator-3 {
- /* TPS22918DBVR */
- bootph-all;
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vcc_3v3_sys>;
- gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_sd_dv: regulator-4 {
- /* Output of TLV71033 */
- bootph-all;
- compatible = "regulator-gpio";
- regulator-name = "tlv71033";
- pinctrl-names = "default";
- pinctrl-0 = <&vdd_sd_dv_pins_default>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- vin-supply = <&vcc_5v0>;
- gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0>,
- <3300000 0x1>;
- };
-
- vcc_1v8: regulator-5 {
- /* output of TPS6282518DMQ */
- compatible = "regulator-fixed";
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3_sys>;
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&main_pmx0 {
- main_rgmii2_pins_default: main-rgmii2-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
- AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
- AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
- AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
- AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
- AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
- AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
- AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
- AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
- AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
- AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
- AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
- >;
- };
-
- ospi0_pins_default: ospi0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
- AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
- AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
- AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
- AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
- AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
- AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
- AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
- AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
- AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
- AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
- >;
- };
-
- vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
- >;
- };
-
- main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
- >;
- };
-};
-
-&main_gpio0 {
- bootph-all;
-};
-
-&main_gpio1 {
- bootph-all;
-};
-
-&main_i2c1 {
- bootph-all;
- exp1: gpio@22 {
- bootph-all;
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
- "PRU_DETECT", "MMC1_SD_EN",
- "VPP_LDO_EN", "EXP_PS_3V3_En",
- "EXP_PS_5V0_En", "EXP_HAT_DETECT",
- "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
- "UART1_FET_BUF_EN", "WL_LT_EN",
- "GPIO_HDMI_RSTn", "CSI_GPIO1",
- "CSI_GPIO2", "PRU_3V3_EN",
- "HDMI_INTn", "PD_I2C_IRQ",
- "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
- "MCASP1_FET_SEL", "UART1_FET_SEL",
- "TSINT#", "IO_EXP_TEST_LED";
-
- interrupt-parent = <&main_gpio1>;
- interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
- };
-};
-
-&sdhci1 {
- vmmc-supply = <&vdd_mmc1>;
- vqmmc-supply = <&vdd_sd_dv>;
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
-};
-
-&cpsw_port2 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy1>;
-};
-
-&cpsw3g_mdio {
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,min-output-impedance;
- };
-};
-
-&mailbox0_cluster0 {
- mbox_m4_0: mbox-m4-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-};
-
-&fss {
- bootph-all;
-};
-
-&ospi0 {
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ospi0_pins_default>;
-
- flash@0 {
- bootph-all;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <4>;
-
- partitions {
- bootph-all;
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ospi.tiboot3";
- reg = <0x0 0x80000>;
- };
-
- partition@80000 {
- label = "ospi.tispl";
- reg = <0x80000 0x200000>;
- };
-
- partition@280000 {
- label = "ospi.u-boot";
- reg = <0x280000 0x400000>;
- };
-
- partition@680000 {
- label = "ospi.env";
- reg = <0x680000 0x40000>;
- };
-
- partition@6c0000 {
- label = "ospi.env.backup";
- reg = <0x6c0000 0x40000>;
- };
-
- partition@800000 {
- label = "ospi.rootfs";
- reg = <0x800000 0x37c0000>;
- };
-
- partition@3fc0000 {
- bootph-pre-ram;
- label = "ospi.phypattern";
- reg = <0x3fc0000 0x40000>;
- };
- };
- };
-};
-
-&tlv320aic3106 {
- DVDD-supply = <&vcc_1v8>;
-};
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
index a9b86b6..0e61889 100644
--- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
@@ -448,4 +448,72 @@
};
};
+&binman {
+ firmware-verdin-am62-gp.bin {
+ filename = "firmware-verdin-am62-gp.bin";
+
+ blob-ext@1 {
+ filename = "tiboot3-am62x-gp-verdin.bin";
+ };
+
+ blob-ext@2 {
+ filename = "tispl.bin_unsigned";
+ /*
+ * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ * from R5 SPL config.
+ */
+ offset = <0x80000>;
+ };
+
+ blob-ext@3 {
+ filename = "u-boot.img_unsigned";
+ offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
+ };
+ };
+
+ firmware-verdin-am62-hs.bin {
+ filename = "firmware-verdin-am62-hs.bin";
+
+ blob-ext@1 {
+ filename = "tiboot3-am62x-hs-verdin.bin";
+ };
+
+ blob-ext@2 {
+ filename = "tispl.bin";
+ /*
+ * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ * from R5 SPL config.
+ */
+ offset = <0x80000>;
+ };
+
+ blob-ext@3 {
+ filename = "u-boot.img";
+ offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
+ };
+ };
+
+ firmware-verdin-am62-hs-fs.bin {
+ filename = "firmware-verdin-am62-hs-fs.bin";
+
+ blob-ext@1 {
+ filename = "tiboot3-am62x-hs-fs-verdin.bin";
+ };
+
+ blob-ext@2 {
+ filename = "tispl.bin";
+ /*
+ * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ * from R5 SPL config.
+ */
+ offset = <0x80000>;
+ };
+
+ blob-ext@3 {
+ filename = "u-boot.img";
+ offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>;
+ };
+ };
+};
+
#endif /* CONFIG_TARGET_VERDIN_AM62_A53 */
diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi
deleted file mode 100644
index 4014add..0000000
--- a/arch/arm/dts/k3-am625.dtsi
+++ /dev/null
@@ -1,155 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC family in Quad core configuration
- *
- * TRM: https://www.ti.com/lit/pdf/spruiv7
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-am62.dtsi"
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0: cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
-
- core2 {
- cpu = <&cpu2>;
- };
-
- core3 {
- cpu = <&cpu3>;
- };
- };
- };
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53";
- reg = <0x000>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- operating-points-v2 = <&a53_opp_table>;
- clocks = <&k3_clks 135 0>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53";
- reg = <0x001>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- operating-points-v2 = <&a53_opp_table>;
- clocks = <&k3_clks 136 0>;
- };
-
- cpu2: cpu@2 {
- compatible = "arm,cortex-a53";
- reg = <0x002>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- operating-points-v2 = <&a53_opp_table>;
- clocks = <&k3_clks 137 0>;
- };
-
- cpu3: cpu@3 {
- compatible = "arm,cortex-a53";
- reg = <0x003>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&L2_0>;
- operating-points-v2 = <&a53_opp_table>;
- clocks = <&k3_clks 138 0>;
- };
- };
-
- a53_opp_table: opp-table {
- compatible = "operating-points-v2-ti-cpu";
- opp-shared;
- syscon = <&wkup_conf>;
-
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-supported-hw = <0x01 0x0007>;
- clock-latency-ns = <6000000>;
- };
-
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-supported-hw = <0x01 0x0007>;
- clock-latency-ns = <6000000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-supported-hw = <0x01 0x0007>;
- clock-latency-ns = <6000000>;
- };
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-supported-hw = <0x01 0x0007>;
- clock-latency-ns = <6000000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-supported-hw = <0x01 0x0006>;
- clock-latency-ns = <6000000>;
- };
-
- opp-1250000000 {
- opp-hz = /bits/ 64 <1250000000>;
- opp-supported-hw = <0x01 0x0004>;
- clock-latency-ns = <6000000>;
- opp-suspend;
- };
- };
-
- L2_0: l2-cache0 {
- compatible = "cache";
- cache-unified;
- cache-level = <2>;
- cache-size = <0x80000>;
- cache-line-size = <64>;
- cache-sets = <512>;
- };
-};
diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi
deleted file mode 100644
index aa1e057..0000000
--- a/arch/arm/dts/k3-am62a-main.dtsi
+++ /dev/null
@@ -1,1054 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62A SoC Family Main Domain peripherals
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_main {
- oc_sram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x00 0x70000000 0x00 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x70000000 0x10000>;
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0xc0000>, /* GICR */
- <0x00 0x01880000 0x00 0xc0000>, /* GICR */
- <0x01 0x00000000 0x00 0x2000>, /* GICC */
- <0x01 0x00010000 0x00 0x1000>, /* GICH */
- <0x01 0x00020000 0x00 0x2000>; /* GICV */
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- /*
- * vcpumntirq:
- * virtual CPU interface maintenance interrupt
- */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- main_conf: bus@100000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x00100000 0x20000>;
-
- phy_gmii_sel: phy@4044 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4044 0x8>;
- #phy-cells = <1>;
- };
-
- epwm_tbclk: clock-controller@4130 {
- compatible = "ti,am62-epwm-tbclk";
- reg = <0x4130 0x4>;
- #clock-cells = <1>;
- };
- };
-
- dmss: bus@48000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- dma-ranges;
- ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
-
- ti,sci-dev-id = <25>;
-
- secure_proxy_main: mailbox@4d000000 {
- compatible = "ti,am654-secure-proxy";
- reg = <0x00 0x4d000000 0x00 0x80000>,
- <0x00 0x4a600000 0x00 0x80000>,
- <0x00 0x4a400000 0x00 0x80000>;
- reg-names = "target_data", "rt", "scfg";
- #mbox-cells = <1>;
- interrupt-names = "rx_012";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- inta_main_dmss: interrupt-controller@48000000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x48000000 0x00 0x100000>;
- #interrupt-cells = <0>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- msi-controller;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <28>;
- ti,interrupt-ranges = <6 70 34>;
- ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
- };
-
- main_bcdma: dma-controller@485c0100 {
- compatible = "ti,am64-dmss-bcdma";
- reg = <0x00 0x485c0100 0x00 0x100>,
- <0x00 0x4c000000 0x00 0x20000>,
- <0x00 0x4a820000 0x00 0x20000>,
- <0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>,
- <0x00 0x48600000 0x00 0x8000>,
- <0x00 0x484a4000 0x00 0x2000>,
- <0x00 0x484c2000 0x00 0x2000>,
- <0x00 0x48420000 0x00 0x2000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "bchan";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <3>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <26>;
- ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
- ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
- ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
- };
-
- main_pktdma: dma-controller@485c0000 {
- compatible = "ti,am64-dmss-pktdma";
- reg = <0x00 0x485c0000 0x00 0x100>,
- <0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
- <0x00 0x485e0000 0x00 0x10000>,
- <0x00 0x484a0000 0x00 0x2000>,
- <0x00 0x484c0000 0x00 0x2000>,
- <0x00 0x48430000 0x00 0x1000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "rflow";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <2>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <30>;
- ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
- <0x24>, /* CPSW_TX_CHAN */
- <0x25>, /* SAUL_TX_0_CHAN */
- <0x26>; /* SAUL_TX_1_CHAN */
- ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
- <0x11>, /* RING_CPSW_TX_CHAN */
- <0x12>, /* RING_SAUL_TX_0_CHAN */
- <0x13>; /* RING_SAUL_TX_1_CHAN */
- ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
- <0x2b>, /* CPSW_RX_CHAN */
- <0x2d>, /* SAUL_RX_0_CHAN */
- <0x2f>, /* SAUL_RX_1_CHAN */
- <0x31>, /* SAUL_RX_2_CHAN */
- <0x33>; /* SAUL_RX_3_CHAN */
- ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
- <0x2c>, /* FLOW_CPSW_RX_CHAN */
- <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
- <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
- };
- };
-
- dmss_csi: bus@4e000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- dma-ranges;
- ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
-
- ti,sci-dev-id = <198>;
-
- inta_main_dmss_csi: interrupt-controller@4e0a0000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x4e0a0000 0x00 0x8000>;
- #interrupt-cells = <0>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- msi-controller;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <200>;
- ti,interrupt-ranges = <0 237 8>;
- ti,unmapped-event-sources = <&main_bcdma_csi>;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- };
-
- main_bcdma_csi: dma-controller@4e230000 {
- compatible = "ti,am62a-dmss-bcdma-csirx";
- reg = <0x00 0x4e230000 0x00 0x100>,
- <0x00 0x4e180000 0x00 0x8000>,
- <0x00 0x4e100000 0x00 0x10000>;
- reg-names = "gcfg", "rchanrt", "ringrt";
- msi-parent = <&inta_main_dmss_csi>;
- #dma-cells = <3>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <199>;
- ti,sci-rm-range-rchan = <0x21>;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- };
- };
-
- dmsc: system-controller@44043000 {
- compatible = "ti,k2g-sci";
- reg = <0x00 0x44043000 0x00 0xfe0>;
- reg-names = "debug_messages";
- ti,host-id = <12>;
- mbox-names = "rx", "tx";
- mboxes = <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- };
-
- k3_clks: clock-controller {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
- };
-
- secure_proxy_sa3: mailbox@43600000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x43600000 0x00 0x10000>,
- <0x00 0x44880000 0x00 0x20000>,
- <0x00 0x44860000 0x00 0x20000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- };
-
- main_pmx0: pinctrl@f4000 {
- compatible = "pinctrl-single";
- reg = <0x00 0xf4000 0x00 0x2ac>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_timer0: timer@2400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 36 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 36 2>;
- assigned-clock-parents = <&k3_clks 36 3>;
- power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 37 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 37 2>;
- assigned-clock-parents = <&k3_clks 37 3>;
- power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 38 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 38 2>;
- assigned-clock-parents = <&k3_clks 38 3>;
- power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 39 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 39 2>;
- assigned-clock-parents = <&k3_clks 39 3>;
- power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 40 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 40 2>;
- assigned-clock-parents = <&k3_clks 40 3>;
- power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 41 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 41 2>;
- assigned-clock-parents = <&k3_clks 41 3>;
- power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 42 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 42 2>;
- assigned-clock-parents = <&k3_clks 42 3>;
- power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 43 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 43 2>;
- assigned-clock-parents = <&k3_clks 43 3>;
- power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 146 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 152 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 153 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart3: serial@2830000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02830000 0x00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 154 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart4: serial@2840000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02840000 0x00 0x100>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 155 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart5: serial@2850000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02850000 0x00 0x100>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 156 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart6: serial@2860000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02860000 0x00 0x100>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 158 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_i2c0: i2c@20000000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20000000 0x00 0x100>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c1: i2c@20010000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20010000 0x00 0x100>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 103 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c2: i2c@20020000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20020000 0x00 0x100>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 104 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c3: i2c@20030000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20030000 0x00 0x100>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 105 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_spi0: spi@20100000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x20100000 0x00 0x400>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 141 0>;
- status = "disabled";
- };
-
- main_spi1: spi@20110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20110000 0x00 0x400>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 142 0>;
- status = "disabled";
- };
-
- main_spi2: spi@20120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20120000 0x00 0x400>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 143 0>;
- status = "disabled";
- };
-
- main_gpio_intr: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x00a00000 0x00 0x800>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <3>;
- ti,interrupt-ranges = <0 32 16>;
- status = "disabled";
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00600000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <190>, <191>, <192>,
- <193>, <194>, <195>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <92>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 77 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- main_gpio1: gpio@601000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00601000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <180>, <181>, <182>,
- <183>, <184>, <185>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <52>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 78 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- sdhci0: mmc@fa10000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
- clock-names = "clk_ahb", "clk_xin";
- assigned-clocks = <&k3_clks 57 6>;
- assigned-clock-parents = <&k3_clks 57 8>;
- bus-width = <8>;
- mmc-hs200-1_8v;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-hs200 = <0x6>;
- status = "disabled";
- };
-
- sdhci1: mmc@fa00000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x6>;
- ti,otap-del-sel-ddr50 = <0x9>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- no-1-8-v;
- status = "disabled";
- };
-
- sdhci2: mmc@fa20000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x6>;
- ti,otap-del-sel-ddr50 = <0x9>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- no-1-8-v;
- status = "disabled";
- };
-
- usbss0: dwc3-usb@f900000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f900000 0x00 0x800>;
- clocks = <&k3_clks 161 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb0: usb@31000000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31000000 0x00 0x50000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- };
- };
-
- usbss1: dwc3-usb@f910000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f910000 0x00 0x800>;
- clocks = <&k3_clks 162 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb1: usb@31100000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31100000 0x00 0x50000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- };
- };
-
- fss: bus@fc00000 {
- compatible = "simple-bus";
- reg = <0x00 0x0fc00000 0x00 0x70000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- ospi0: spi@fc40000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x00 0x0fc40000 0x00 0x100>,
- <0x05 0x00000000 0x01 0x00000000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 75 7>;
- assigned-clocks = <&k3_clks 75 7>;
- assigned-clock-parents = <&k3_clks 75 8>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- cpsw3g: ethernet@8000000 {
- compatible = "ti,am642-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x0 0x8000000 0x0 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
- clocks = <&k3_clks 13 0>;
- assigned-clocks = <&k3_clks 13 3>;
- assigned-clock-parents = <&k3_clks 13 11>;
- clock-names = "fck";
- power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
-
- dmas = <&main_pktdma 0xc600 15>,
- <&main_pktdma 0xc601 15>,
- <&main_pktdma 0xc602 15>,
- <&main_pktdma 0xc603 15>,
- <&main_pktdma 0xc604 15>,
- <&main_pktdma 0xc605 15>,
- <&main_pktdma 0xc606 15>,
- <&main_pktdma 0xc607 15>,
- <&main_pktdma 0x4600 15>;
- dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
- "tx7", "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- phys = <&phy_gmii_sel 1>;
- mac-address = [00 00 00 00 00 00];
- ti,syscon-efuse = <&wkup_conf 0x200>;
- };
-
- cpsw_port2: port@2 {
- reg = <2>;
- ti,mac-only;
- label = "port2";
- phys = <&phy_gmii_sel 2>;
- mac-address = [00 00 00 00 00 00];
- };
- };
-
- cpsw3g_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 13 0>;
- clock-names = "fck";
- bus_freq = <1000000>;
- };
-
- cpts@3d000 {
- compatible = "ti,j721e-cpts";
- reg = <0x0 0x3d000 0x0 0x400>;
- clocks = <&k3_clks 13 3>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- hwspinlock: spinlock@2a000000 {
- compatible = "ti,am64-hwspinlock";
- reg = <0x00 0x2a000000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster0: mailbox@29000000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29000000 0x00 0x200>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- mailbox0_cluster1: mailbox@29010000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29010000 0x00 0x200>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- mailbox0_cluster2: mailbox@29020000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29020000 0x00 0x200>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- mailbox0_cluster3: mailbox@29030000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29030000 0x00 0x200>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
-
- main_mcan0: can@20701000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x20701000 0x00 0x200>,
- <0x00 0x20708000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_rti0: watchdog@e000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e000000 0x00 0x100>;
- clocks = <&k3_clks 125 0>;
- power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 125 0>;
- assigned-clock-parents = <&k3_clks 125 2>;
- };
-
- main_rti1: watchdog@e010000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e010000 0x00 0x100>;
- clocks = <&k3_clks 126 0>;
- power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 126 0>;
- assigned-clock-parents = <&k3_clks 126 2>;
- };
-
- main_rti2: watchdog@e020000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e020000 0x00 0x100>;
- clocks = <&k3_clks 127 0>;
- power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 127 0>;
- assigned-clock-parents = <&k3_clks 127 2>;
- };
-
- main_rti3: watchdog@e030000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e030000 0x00 0x100>;
- clocks = <&k3_clks 128 0>;
- power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 128 0>;
- assigned-clock-parents = <&k3_clks 128 2>;
- };
-
- main_rti4: watchdog@e040000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e040000 0x00 0x100>;
- clocks = <&k3_clks 205 0>;
- power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 205 0>;
- assigned-clock-parents = <&k3_clks 205 2>;
- };
-
- epwm0: pwm@23000000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23000000 0x00 0x100>;
- power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm1: pwm@23010000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23010000 0x00 0x100>;
- power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm2: pwm@23020000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23020000 0x00 0x100>;
- power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ecap0: pwm@23100000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23100000 0x00 0x100>;
- power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 51 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap1: pwm@23110000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23110000 0x00 0x100>;
- power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 52 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap2: pwm@23120000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23120000 0x00 0x100>;
- power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 53 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcasp0: audio-controller@2b00000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b00000 0x00 0x2000>,
- <0x00 0x02b08000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 190 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 190 0>;
- assigned-clock-parents = <&k3_clks 190 2>;
- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp1: audio-controller@2b10000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b10000 0x00 0x2000>,
- <0x00 0x02b18000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 191 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 191 0>;
- assigned-clock-parents = <&k3_clks 191 2>;
- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp2: audio-controller@2b20000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b20000 0x00 0x2000>,
- <0x00 0x02b28000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 192 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 192 0>;
- assigned-clock-parents = <&k3_clks 192 2>;
- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- ti_csi2rx0: ticsi2rx@30102000 {
- compatible = "ti,j721e-csi2rx-shim";
- dmas = <&main_bcdma_csi 0 0x5000 0>;
- dma-names = "rx0";
- reg = <0x00 0x30102000 0x00 0x1000>;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- cdns_csi2rx0: csi-bridge@30101000 {
- compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
- reg = <0x00 0x30101000 0x00 0x1000>;
- clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
- <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
- clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
- phys = <&dphy0>;
- phy-names = "dphy";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- csi0_port0: port@0 {
- reg = <0>;
- status = "disabled";
- };
-
- csi0_port1: port@1 {
- reg = <1>;
- status = "disabled";
- };
-
- csi0_port2: port@2 {
- reg = <2>;
- status = "disabled";
- };
-
- csi0_port3: port@3 {
- reg = <3>;
- status = "disabled";
- };
-
- csi0_port4: port@4 {
- reg = <4>;
- status = "disabled";
- };
- };
- };
- };
-
- dphy0: phy@30110000 {
- compatible = "cdns,dphy-rx";
- reg = <0x00 0x30110000 0x00 0x1100>;
- #phy-cells = <0>;
- power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- dss: dss@30200000 {
- compatible = "ti,am62a7-dss";
- reg = <0x00 0x30200000 0x00 0x1000>, /* common */
- <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
- <0x00 0x30206000 0x00 0x1000>, /* vid */
- <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
- <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
- <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */
- <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
- <0x00 0x30201000 0x00 0x1000>; /* common1 */
- reg-names = "common", "vidl1", "vid",
- "ovr1", "ovr2", "vp1", "vp2", "common1";
- power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 186 6>,
- <&k3_clks 186 0>,
- <&k3_clks 186 2>;
- clock-names = "fck", "vp1", "vp2";
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
- dss_ports: ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi
deleted file mode 100644
index 8c36e56..0000000
--- a/arch/arm/dts/k3-am62a-mcu.dtsi
+++ /dev/null
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM625 SoC Family MCU Domain peripherals
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu {
- mcu_pmx0: pinctrl@4084000 {
- compatible = "pinctrl-single";
- reg = <0x00 0x04084000 0x00 0x88>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- status = "disabled";
- };
-
- /*
- * The MCU domain timer interrupts are routed only to the ESM module,
- * and not currently available for Linux. The MCU domain timers are
- * of limited use without interrupts, and likely reserved by the ESM.
- */
- mcu_timer0: timer@4800000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4800000 0x00 0x400>;
- clocks = <&k3_clks 35 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer1: timer@4810000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4810000 0x00 0x400>;
- clocks = <&k3_clks 48 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer2: timer@4820000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4820000 0x00 0x400>;
- clocks = <&k3_clks 49 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer3: timer@4830000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4830000 0x00 0x400>;
- clocks = <&k3_clks 50 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_uart0: serial@4a00000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x04a00000 0x00 0x100>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 149 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- mcu_i2c0: i2c@4900000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x04900000 0x00 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 106 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcu_spi0: spi@4b00000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x04b00000 0x00 0x400>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 147 0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@4b10000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x04b10000 0x00 0x400>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 148 0>;
- status = "disabled";
- };
-
- mcu_gpio_intr: interrupt-controller@4210000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x04210000 0x00 0x200>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <5>;
- ti,interrupt-ranges = <0 104 4>;
- };
-
- mcu_gpio0: gpio@4201000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x04201000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&mcu_gpio_intr>;
- interrupts = <30>, <31>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <24>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 79 0>;
- clock-names = "gpio";
- status = "disabled";
- };
-
- mcu_rti0: watchdog@4880000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x04880000 0x00 0x100>;
- clocks = <&k3_clks 131 0>;
- power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 131 0>;
- assigned-clock-parents = <&k3_clks 131 2>;
- /* Tightly coupled to M4F */
- status = "reserved";
- };
-
- mcu_mcan0: can@4e08000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e08000 0x00 0x200>,
- <0x00 0x4e00000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- mcu_mcan1: can@4e18000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e18000 0x00 0x200>,
- <0x00 0x4e10000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi
index 6f82f26..2a8c260 100644
--- a/arch/arm/dts/k3-am62a-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi
@@ -144,7 +144,7 @@
#ifdef CONFIG_TARGET_AM62A7_A53_EVM
-#define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb"
+#define SPL_AM62A7_SK_DTB "spl/dts/ti/k3-am62a7-sk.dtb"
#define AM62A7_SK_DTB "u-boot.dtb"
&binman {
@@ -155,11 +155,105 @@
optional;
};
};
+
+ tifsstub-hs {
+ filename = "tifsstub.bin_hs";
+ ti-secure-rom {
+ content = <&tifsstub_hs_cert>;
+ core = "secure";
+ load = <0x60000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "custMpk.pem";
+ countersign;
+ tifsstub;
+ };
+ tifsstub_hs_cert: tifsstub-hs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_hs_enc: tifsstub-hs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
+ tifsstub-fs {
+ filename = "tifsstub.bin_fs";
+ tifsstub_fs_cert: tifsstub-fs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_fs_enc: tifsstub-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ };
+
+ tifsstub-gp {
+ filename = "tifsstub.bin_gp";
+ ti-secure-rom {
+ content = <&tifsstub_gp>;
+ core = "secure";
+ load = <0x60000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "ti-degenerate-key.pem";
+ tifsstub;
+ };
+ tifsstub_gp: tifsstub-gp.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
ti-spl {
insert-template = <&ti_spl_template>;
fit {
images {
+ tifsstub-hs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-hs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_hs";
+ };
+ };
+
+ tifsstub-fs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-fs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_fs";
+ };
+ };
+
+ tifsstub-gp {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-gp";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_gp";
+ };
+ };
dm {
ti-secure {
content = <&dm>;
@@ -193,7 +287,8 @@
conf-0 {
description = "k3-am62a7-sk";
firmware = "atf";
- loadables = "tee", "dm", "spl";
+ loadables = "tee", "dm", "spl",
+ "tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
fdt = "fdt-0";
};
};
@@ -250,6 +345,44 @@
fit {
images {
+ tifsstub-hs {
+ description = "tifsstub";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-hs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_hs";
+ };
+ };
+
+ tifsstub-fs {
+ description = "tifsstub";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-fs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_fs";
+ };
+ };
+
+ tifsstub-gp {
+ description = "tifsstub";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-gp";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_gp";
+ };
+ };
dm {
ti-dm {
filename = "ti-dm.bin";
@@ -273,7 +406,8 @@
conf-0 {
description = "k3-am62a7-sk";
firmware = "atf";
- loadables = "tee", "dm", "spl";
+ loadables = "tee", "dm", "spl",
+ "tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
fdt = "fdt-0";
};
};
diff --git a/arch/arm/dts/k3-am62a-thermal.dtsi b/arch/arm/dts/k3-am62a-thermal.dtsi
deleted file mode 100644
index c7486fb..0000000
--- a/arch/arm/dts/k3-am62a-thermal.dtsi
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/thermal/thermal.h>
-
-thermal_zones: thermal-zones {
- main0_thermal: main0-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 0>;
-
- trips {
- main0_crit: main0-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- main1_thermal: main1-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 1>;
-
- trips {
- main1_crit: main1-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- main2_thermal: main2-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&wkup_vtm0 2>;
-
- trips {
- main2_crit: main2-crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-};
diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi
deleted file mode 100644
index f7bec48..0000000
--- a/arch/arm/dts/k3-am62a-wakeup.dtsi
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_wakeup {
- wkup_conf: syscon@43000000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00 0x43000000 0x00 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x43000000 0x20000>;
-
- chipid: chipid@14 {
- compatible = "ti,am654-chipid";
- reg = <0x14 0x4>;
- };
- };
-
- wkup_uart0: serial@2b300000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x2b300000 0x00 0x100>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- wkup_i2c0: i2c@2b200000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2b200000 0x00 0x100>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 107 4>;
- clock-names = "fck";
- status = "disabled";
- };
-
- wkup_rtc0: rtc@2b1f0000 {
- compatible = "ti,am62-rtc";
- reg = <0x00 0x2b1f0000 0x00 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
- clock-names = "vbus", "osc32k";
- power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
- wakeup-source;
- status = "disabled";
- };
-
- wkup_rti0: watchdog@2b000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2b000000 0x00 0x100>;
- clocks = <&k3_clks 132 0>;
- power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 132 0>;
- assigned-clock-parents = <&k3_clks 132 2>;
- /* Used by DM firmware */
- status = "reserved";
- };
-
- wkup_vtm0: temperature-sensor@b00000 {
- compatible = "ti,j7200-vtm";
- reg = <0x00 0xb00000 0x00 0x400>,
- <0x00 0xb01000 0x00 0x400>;
- power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-};
diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi
deleted file mode 100644
index b1b8846..0000000
--- a/arch/arm/dts/k3-am62a.dtsi
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62A SoC Family
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
- model = "Texas Instruments K3 AM62A SoC";
- compatible = "ti,am62a7";
- interrupt-parent = <&gic500>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- psci: psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
- };
-
- a53_timer0: timer-cl0-cpu0 {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
- };
-
- pmu: pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cbass_main: bus@f0000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
-
- ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
- <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
- <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
- <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
- <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
- <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
- <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
- <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
- <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
- <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
- <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
- <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
- <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
- <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
- <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
- <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
- <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
- <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
- <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
- <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
- <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
- <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
- <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */
- <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
-
- /* MCU Domain Range */
- <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
- <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
- <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
- <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
- <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */
-
- /* Wakeup Domain Range */
- <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
- <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
- <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
- <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */
-
- cbass_mcu: bus@4000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
- <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
- <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
- <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
- <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
- };
-
- cbass_wakeup: bus@b00000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
- <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
- <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
- <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
- };
- };
-
- #include "k3-am62a-thermal.dtsi"
-};
-
-/* Now include the peripherals for each bus segments */
-#include "k3-am62a-main.dtsi"
-#include "k3-am62a-mcu.dtsi"
-#include "k3-am62a-wakeup.dtsi"
diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
deleted file mode 100644
index f241637..0000000
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ /dev/null
@@ -1,702 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * AM62A SK: https://www.ti.com/lit/zip/sprr459
- *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am62a7.dtsi"
-
-/ {
- compatible = "ti,am62a7-sk", "ti,am62a7";
- model = "Texas Instruments AM62A7 SK";
-
- aliases {
- serial0 = &wkup_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_tfa_ddr: tfa@9e780000 {
- reg = <0x00 0x9e780000 0x00 0x80000>;
- alignment = <0x1000>;
- no-map;
- };
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
-
- wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9c900000 0x00 0x01e00000>;
- no-map;
- };
- };
-
- vmain_pd: regulator-0 {
- /* TPS25750 PD CONTROLLER OUTPUT */
- compatible = "regulator-fixed";
- regulator-name = "vmain_pd";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_5v0: regulator-1 {
- /* Output of TPS63070 */
- compatible = "regulator-fixed";
- regulator-name = "vcc_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vmain_pd>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_3v3_main: regulator-2 {
- /* output of LM5141-Q1 */
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_main";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vmain_pd>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: regulator-3 {
- /* TPS22918DBVR */
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
- };
-
- vcc_3v3_sys: regulator-4 {
- /* output of TPS222965DSGT */
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sys";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_3v3_main>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&usr_led_pins_default>;
-
- led-0 {
- label = "am62a-sk:green:heartbeat";
- gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- function = LED_FUNCTION_HEARTBEAT;
- default-state = "off";
- };
- };
-
- tlv320_mclk: clk-0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12288000>;
- };
-
- hdmi0: connector-hdmi {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&sii9022_out>;
- };
- };
- };
-
- codec_audio: sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "AM62Ax-SKEVM";
- simple-audio-card,widgets =
- "Headphone", "Headphone Jack",
- "Line", "Line In",
- "Microphone", "Microphone Jack";
- simple-audio-card,routing =
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT",
- "LINE1L", "Line In",
- "LINE1R", "Line In",
- "MIC3R", "Microphone Jack",
- "Microphone Jack", "Mic Bias";
- simple-audio-card,format = "dsp_b";
- simple-audio-card,bitclock-master = <&sound_master>;
- simple-audio-card,frame-master = <&sound_master>;
- simple-audio-card,bitclock-inversion;
-
- simple-audio-card,cpu {
- sound-dai = <&mcasp1>;
- };
-
- sound_master: simple-audio-card,codec {
- sound-dai = <&tlv320aic3106>;
- clocks = <&tlv320_mclk>;
- };
- };
-};
-
-&mcu_pmx0 {
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- pinctrl-single,pins = <
- AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
- AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
- AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
- AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
- >;
- };
-};
-
-/* WKUP UART0 is used for DM firmware logs */
-&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
- status = "reserved";
-};
-
-&main_pmx0 {
- main_dss0_pins_default: main-dss0-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */
- AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */
- AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */
- AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */
- AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
- AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */
- AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */
- AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */
- AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */
- AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */
- AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */
- AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */
- AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */
- AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */
- AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */
- AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */
- AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */
- AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */
- AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */
- AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */
- AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */
- AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */
- AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */
- AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */
- AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
- AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */
- AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */
- AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */
- >;
- };
-
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
- AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
- AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
- AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
- AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
- AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
- AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
- >;
- };
-
- main_i2c2_pins_default: main-i2c2-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
- AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
- >;
- };
-
- main_mmc0_pins_default: main-mmc0-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
- AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
- AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
- AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
- AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
- AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
- AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
- AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
- AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
- AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
- AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
- AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
- AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
- AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
- AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
- AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
- AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
- >;
- };
-
- usr_led_pins_default: usr-led-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
- >;
- };
-
- main_usb1_pins_default: main-usb1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
- >;
- };
-
- main_mdio1_pins_default: main-mdio1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
- AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
- >;
- };
-
- main_rgmii1_pins_default: main-rgmii1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
- AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
- AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
- AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
- AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
- AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
- AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
- AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
- AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
- AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
- AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
- AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
- >;
- };
-
- main_mcasp1_pins_default: main-mcasp1-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */
- AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */
- AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */
- AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
- >;
- };
-
- main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
- pinctrl-single,pins = <
- AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */
- >;
- };
-};
-
-&mcu_pmx0 {
- status = "okay";
-
- pmic_irq_pins_default: pmic-irq-default-pins {
- pinctrl-single,pins = <
- AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
- >;
- };
-};
-
-&mcu_gpio0 {
- status = "okay";
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- typec_pd0: usb-power-controller@3f {
- compatible = "ti,tps6598x";
- reg = <0x3f>;
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- self-powered;
- data-role = "dual";
- power-role = "sink";
- port {
- usb_con_hs: endpoint {
- remote-endpoint = <&usb0_hs_ep>;
- };
- };
- };
- };
-
- tps659312: pmic@48 {
- compatible = "ti,tps6593-q1";
- reg = <0x48>;
- ti,primary-pmic;
- system-power-controller;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_irq_pins_default>;
- interrupt-parent = <&mcu_gpio0>;
- interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
-
- buck123-supply = <&vcc_3v3_sys>;
- buck4-supply = <&vcc_3v3_sys>;
- buck5-supply = <&vcc_3v3_sys>;
- ldo1-supply = <&vcc_3v3_sys>;
- ldo2-supply = <&vcc_3v3_sys>;
- ldo3-supply = <&buck5>;
- ldo4-supply = <&vcc_3v3_sys>;
-
- regulators {
- buck123: buck123 {
- regulator-name = "vcc_core";
- regulator-min-microvolt = <715000>;
- regulator-max-microvolt = <895000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck4: buck4 {
- regulator-name = "vcc_1v1";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5: buck5 {
- regulator-name = "vcc_1v8_sys";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1: ldo1 {
- regulator-name = "vddshv5_sdio";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2: ldo2 {
- regulator-name = "vpp_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3: ldo3 {
- regulator-name = "vcc_0v85";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4: ldo4 {
- regulator-name = "vdda_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <100000>;
-
- exp1: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio1>;
- interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
-
- gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
- "BT_EN_SOC", "MMC1_SD_EN",
- "VPP_EN", "EXP_PS_3V3_En",
- "EXP_PS_5V0_En", "EXP_HAT_DETECT",
- "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
- "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC",
- "GPIO_HDMI_RSTn", "CSI_GPIO0",
- "CSI_GPIO1", "WLAN_ALERTn",
- "HDMI_INTn", "TEST_GPIO2",
- "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
- "MCASP1_FET_SEL", "UART1_FET_SEL",
- "PD_I2C_IRQ", "IO_EXP_TEST_LED";
- };
-
- tlv320aic3106: audio-codec@1b {
- #sound-dai-cells = <0>;
- compatible = "ti,tlv320aic3106";
- reg = <0x1b>;
- ai3x-micbias-vg = <1>; /* 2.0V */
-
- /* Regulators */
- AVDD-supply = <&vcc_3v3_sys>;
- IOVDD-supply = <&vcc_3v3_sys>;
- DRVDD-supply = <&vcc_3v3_sys>;
- DVDD-supply = <&buck5>;
- };
-
- exp2: gpio@23 {
- compatible = "ti,tca6424";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names = "", "",
- "", "",
- "", "",
- "", "",
- "WL_LT_EN", "CSI_RSTz",
- "", "",
- "", "",
- "", "",
- "SPI0_FET_SEL", "SPI0_FET_OE",
- "RGMII2_BRD_CONN_DET", "CSI_SEL2",
- "CSI_EN", "AUTO_100M_1000M_CONFIG",
- "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
- };
-
- sii9022: bridge-hdmi@3b {
- compatible = "sil,sii9022";
- reg = <0x3b>;
- interrupt-parent = <&exp1>;
- interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
- #sound-dai-cells = <0>;
- sil,i2s-data-lanes = < 0 >;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sii9022_in: endpoint {
- remote-endpoint = <&dpi1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- sii9022_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&main_i2c2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c2_pins_default>;
- clock-frequency = <400000>;
-};
-
-&sdhci0 {
- /* eMMC */
- status = "okay";
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
- disable-wp;
-};
-
-&sdhci1 {
- /* SD/MMC */
- status = "okay";
- vmmc-supply = <&vdd_mmc1>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- disable-wp;
-};
-
-&main_gpio0 {
- status = "okay";
-};
-
-&main_gpio1 {
- status = "okay";
-};
-
-&main_gpio_intr {
- status = "okay";
-};
-
-&main_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-/* Main UART1 is used for TIFS firmware logs */
-&main_uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
- status = "reserved";
-};
-
-&usbss0 {
- status = "okay";
- ti,vbus-divider;
-};
-
-&usb0 {
- usb-role-switch;
-
- port {
- usb0_hs_ep: endpoint {
- remote-endpoint = <&usb_con_hs>;
- };
- };
-};
-
-&usbss1 {
- status = "okay";
-};
-
-&usb1 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb1_pins_default>;
-};
-
-&cpsw3g {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_rgmii1_pins_default>;
-};
-
-&cpsw_port1 {
- status = "okay";
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
- status = "disabled";
-};
-
-&cpsw3g_mdio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mdio1_pins_default>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,min-output-impedance;
- };
-};
-
-&mcasp1 {
- status = "okay";
- #sound-dai-cells = <0>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcasp1_pins_default>;
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
-
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 0 2 0
- 0 0 0 0
- 0 0 0 0
- 0 0 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
-};
-
-&dss {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_dss0_pins_default>;
-};
-
-&dss_ports {
- /* VP2: DPI Output */
- port@1 {
- reg = <1>;
-
- dpi1_out: endpoint {
- remote-endpoint = <&sii9022_in>;
- };
- };
-};
diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi
index 2233921..2177d54 100644
--- a/arch/arm/dts/k3-am62p-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi
@@ -59,6 +59,17 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See am62px_evm.h
+#define AM62PX_SK_TIBOOT3_IMAGE_GUID_STR "b08471b7-be2d-4489-87a1-cab28a0cf743"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = AM62PX_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
#endif /* CONFIG_TARGET_AM62P5_R5_EVM */
#if IS_ENABLED(CONFIG_TARGET_AM62P5_A53_EVM)
@@ -75,12 +86,74 @@
optional;
};
};
+ tifsstub-hs {
+ filename = "tifsstub.bin_hs";
+ ti-secure-rom {
+ content = <&tifsstub_hs_cert>;
+ core = "secure";
+ load = <0x60000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "custMpk.pem";
+ countersign;
+ tifsstub;
+ };
+ tifsstub_hs_cert: tifsstub-hs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_hs_enc: tifsstub-hs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
+ tifsstub-fs {
+ filename = "tifsstub.bin_fs";
+ tifsstub_fs_cert: tifsstub-fs-cert.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ tifsstub_fs_enc: tifsstub-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ };
ti-spl {
insert-template = <&ti_spl_template>;
fit {
images {
+ tifsstub-hs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-hs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_hs";
+ };
+ };
+
+ tifsstub-fs {
+ description = "TIFSSTUB";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "tifsstub-fs";
+ load = <0x9ca00000>;
+ entry = <0x9ca00000>;
+ blob-ext {
+ filename = "tifsstub.bin_fs";
+ };
+ };
dm {
ti-secure {
content = <&dm>;
@@ -117,7 +190,8 @@
conf-0 {
description = "k3-am62px-sk";
firmware = "atf";
- loadables = "tee", "dm", "spl";
+ loadables = "tee", "dm", "spl",
+ "tifsstub-hs", "tifsstub-fs";
fdt = "fdt-0";
};
};
@@ -171,4 +245,22 @@
};
};
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See am62px_evm.h
+#define AM62PX_SK_SPL_IMAGE_GUID_STR "d02ed781-6d71-4c1a-a999-3c6a41c36324"
+#define AM62PX_SK_UBOOT_IMAGE_GUID_STR "7e6aea51-965c-44ab-b388-daeb03b54f66"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = AM62PX_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = AM62PX_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif /* CONFIG_TARGET_AM62P5_A53_EVM */
diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi
deleted file mode 100644
index 3c45782..0000000
--- a/arch/arm/dts/k3-am62x-sk-common.dtsi
+++ /dev/null
@@ -1,535 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Common dtsi for AM62x SK and derivatives
- *
- * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am625.dtsi"
-
-/ {
- aliases {
- serial2 = &main_uart0;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- mmc2 = &sdhci2;
- spi0 = &ospi0;
- ethernet0 = &cpsw_port1;
- ethernet1 = &cpsw_port2;
- usb0 = &usb0;
- usb1 = &usb1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- memory@80000000 {
- bootph-pre-ram;
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ramoops@9ca00000 {
- compatible = "ramoops";
- reg = <0x00 0x9ca00000 0x00 0x00100000>;
- record-size = <0x8000>;
- console-size = <0x8000>;
- ftrace-size = <0x00>;
- pmsg-size = <0x8000>;
- };
-
- secure_tfa_ddr: tfa@9e780000 {
- reg = <0x00 0x9e780000 0x00 0x80000>;
- alignment = <0x1000>;
- no-map;
- };
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
-
- wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9db00000 0x00 0xc00000>;
- no-map;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&usr_led_pins_default>;
-
- led-0 {
- label = "am62-sk:green:heartbeat";
- gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- function = LED_FUNCTION_HEARTBEAT;
- default-state = "off";
- };
- };
-
- tlv320_mclk: clk-0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12288000>;
- };
-
- codec_audio: sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "AM62x-SKEVM";
- simple-audio-card,widgets =
- "Headphone", "Headphone Jack",
- "Line", "Line In",
- "Microphone", "Microphone Jack";
- simple-audio-card,routing =
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT",
- "LINE1L", "Line In",
- "LINE1R", "Line In",
- "MIC3R", "Microphone Jack",
- "Microphone Jack", "Mic Bias";
- simple-audio-card,format = "dsp_b";
- simple-audio-card,bitclock-master = <&sound_master>;
- simple-audio-card,frame-master = <&sound_master>;
- simple-audio-card,bitclock-inversion;
-
- simple-audio-card,cpu {
- sound-dai = <&mcasp1>;
- };
-
- sound_master: simple-audio-card,codec {
- sound-dai = <&tlv320aic3106>;
- clocks = <&tlv320_mclk>;
- };
- };
-
- hdmi0: connector-hdmi {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&sii9022_out>;
- };
- };
- };
-};
-
-&main_pmx0 {
- /* First pad number is ALW package and second is AMC package */
- main_uart0_pins_default: main-uart0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */
- AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */
- AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */
- AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */
- AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */
- AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */
- AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */
- >;
- };
-
- main_i2c2_pins_default: main-i2c2-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */
- AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */
- >;
- };
-
- main_mmc0_pins_default: main-mmc0-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */
- AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */
- AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */
- AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */
- AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */
- AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */
- AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */
- AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */
- AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */
- AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */
- AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */
- AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */
- AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */
- AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */
- AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */
- AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */
- >;
- };
-
- usr_led_pins_default: usr-led-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */
- >;
- };
-
- main_mdio1_pins_default: main-mdio1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */
- AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */
- >;
- };
-
- main_rgmii1_pins_default: main-rgmii1-default-pins {
- bootph-all;
- pinctrl-single,pins = <
- AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
- AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */
- AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16/AA17) RGMII1_RD2 */
- AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15/Y15) RGMII1_RD3 */
- AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17/AA16) RGMII1_RXC */
- AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17/W14) RGMII1_RX_CTL */
- AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20/U14) RGMII1_TD0 */
- AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20/AA19) RGMII1_TD1 */
- AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18/Y17) RGMII1_TD2 */
- AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18/AA18) RGMII1_TD3 */
- AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19/W16) RGMII1_TXC */
- AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */
- >;
- };
-
- main_usb1_pins_default: main-usb1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */
- >;
- };
-
- main_mcasp1_pins_default: main-mcasp1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */
- AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */
- AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */
- AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
- >;
- };
-
- main_dss0_pins_default: main-dss0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
- AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
- AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
- AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
- AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
- AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
- AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
- AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
- AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
- AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
- AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
- AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
- AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
- AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
- AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
- AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
- AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
- AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
- AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
- AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
- AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
- AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
- AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
- AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
- AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
- AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
- AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
- AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
- >;
- };
-};
-
-&mcu_pmx0 {
- wkup_uart0_pins_default: wkup-uart0-default-pins {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */
- AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */
- AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */
- AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */
- >;
- };
-};
-
-&wkup_uart0 {
- /* WKUP UART0 is used by DM firmware */
- bootph-pre-ram;
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&main_uart0 {
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-&main_uart1 {
- /* Main UART1 is used by TIFS firmware */
- bootph-pre-ram;
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@51 {
- /* AT24C512C-MAHM-T or M24512-DFMC6TG */
- compatible = "atmel,24c512";
- reg = <0x51>;
- };
-
- typec_pd0: tps6598x@3f {
- compatible = "ti,tps6598x";
- reg = <0x3f>;
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- self-powered;
- data-role = "dual";
- power-role = "sink";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usb_con_hs: endpoint {
- remote-endpoint = <&usb0_hs_ep>;
- };
- };
- };
- };
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <100000>;
-
- tlv320aic3106: audio-codec@1b {
- #sound-dai-cells = <0>;
- compatible = "ti,tlv320aic3106";
- reg = <0x1b>;
- ai3x-micbias-vg = <1>; /* 2.0V */
-
- /* Regulators */
- AVDD-supply = <&vcc_3v3_sys>;
- IOVDD-supply = <&vcc_3v3_sys>;
- DRVDD-supply = <&vcc_3v3_sys>;
- };
-
- sii9022: bridge-hdmi@3b {
- compatible = "sil,sii9022";
- reg = <0x3b>;
- interrupt-parent = <&exp1>;
- interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
- #sound-dai-cells = <0>;
- sil,i2s-data-lanes = < 0 >;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sii9022_in: endpoint {
- remote-endpoint = <&dpi1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- sii9022_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&main_i2c2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c2_pins_default>;
- clock-frequency = <400000>;
-};
-
-&sdhci0 {
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc0_pins_default>;
- disable-wp;
-};
-
-&sdhci1 {
- /* SD/MMC */
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- disable-wp;
-};
-
-&cpsw3g {
- bootph-all;
- pinctrl-names = "default";
- pinctrl-0 = <&main_rgmii1_pins_default>;
-};
-
-&cpsw_port1 {
- bootph-all;
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw3g_mdio {
- bootph-all;
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mdio1_pins_default>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- bootph-all;
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- ti,min-output-impedance;
- };
-};
-
-&mailbox0_cluster0 {
- mbox_m4_0: mbox-m4-0 {
- ti,mbox-rx = <0 0 0>;
- ti,mbox-tx = <1 0 0>;
- };
-};
-
-&usbss0 {
- bootph-all;
- status = "okay";
- ti,vbus-divider;
-};
-
-&usbss1 {
- status = "okay";
- ti,vbus-divider;
-};
-
-&usb0 {
- bootph-all;
- #address-cells = <1>;
- #size-cells = <0>;
- usb-role-switch;
-
- port@0 {
- reg = <0>;
- usb0_hs_ep: endpoint {
- remote-endpoint = <&usb_con_hs>;
- };
- };
-};
-
-&usb1 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb1_pins_default>;
-};
-
-&mcasp1 {
- status = "okay";
- #sound-dai-cells = <0>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcasp1_pins_default>;
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
-
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 0 2 0
- 0 0 0 0
- 0 0 0 0
- 0 0 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
-};
-
-&dss {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_dss0_pins_default>;
-};
-
-&dss_ports {
- /* VP2: DPI Output */
- port@1 {
- reg = <1>;
-
- dpi1_out: endpoint {
- remote-endpoint = <&sii9022_in>;
- };
- };
-};
-
-/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
-&mcu_gpio0 {
- status = "reserved";
-};
-
-&mcu_gpio_intr {
- status = "reserved";
-};
diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi
index 37817ba..f768c4d 100644
--- a/arch/arm/dts/k3-am64x-binman.dtsi
+++ b/arch/arm/dts/k3-am64x-binman.dtsi
@@ -114,6 +114,17 @@
};
};
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See am64x_evm.h
+#define AM64X_SK_TIBOOT3_IMAGE_GUID_STR "ede0a0d5-9116-4bfb-aa54-09e97b5afe1a"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = AM64X_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_AM642_A53_EVM
@@ -373,4 +384,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See am64x_evm.h
+#define AM64X_SK_SPL_IMAGE_GUID_STR "77678f5c-64d4-4910-ad75-52c9d95cdb1d"
+#define AM64X_SK_UBOOT_IMAGE_GUID_STR "c6ad43a9-7d31-4f5d-83e9-b8efecae05bf"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = AM64X_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = AM64X_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-binman-capsule-r5.dtsi b/arch/arm/dts/k3-binman-capsule-r5.dtsi
new file mode 100644
index 0000000..959ceb7
--- /dev/null
+++ b/arch/arm/dts/k3-binman-capsule-r5.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&binman {
+ capsule_tiboot3: capsule-tiboot3 {
+ filename = "tiboot3-capsule.bin";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = "00000000-0000-0000-0000-000000000000";
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "tiboot3.bin";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-binman-capsule.dtsi b/arch/arm/dts/k3-binman-capsule.dtsi
new file mode 100644
index 0000000..17e83c9
--- /dev/null
+++ b/arch/arm/dts/k3-binman-capsule.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&binman {
+ capsule_tispl: capsule-tispl {
+ filename = "tispl-capsule.bin";
+ efi-capsule {
+ image-index = <0x2>;
+ image-guid = "00000000-0000-0000-0000-000000000000";
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "tispl.bin";
+ };
+ };
+ };
+};
+
+&binman {
+ capsule_uboot: capsule-uboot {
+ filename = "uboot-capsule.bin";
+ efi-capsule {
+ image-index = <0x3>;
+ image-guid = "00000000-0000-0000-0000-000000000000";
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "u-boot.img";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
index e202ae1..884f442 100644
--- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
@@ -351,4 +351,27 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See beagleboneai64.h
+#define BEAGLEBONEAI64_SPL_IMAGE_GUID_STR "83447222-1e26-40cd-a395-b7de0957e875"
+#define BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR "4249ff77-c17d-4eb7-a1db-45aa9887d49e"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = BEAGLEBONEAI64_SPL_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tispl.bin_unsigned";
+ };
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
index bffce03..0d60729 100644
--- a/arch/arm/dts/k3-j721e-binman.dtsi
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -295,6 +295,36 @@
};
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See j721e_evm.h
+#define J721E_SK_TIBOOT3_IMAGE_GUID_STR "e672b518-7cd7-4014-bd8d-40724d0ad4dc"
+#define J721E_SK_SYSFW_IMAGE_GUID_STR "6fd10680-361b-431f-80aa-899455819e11"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = J721E_SK_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
+&binman {
+ capsule-sysfw {
+ filename = "sysfw-capsule.bin";
+ efi-capsule {
+ image-index = <0x4>;
+ image-guid = J721E_SK_SYSFW_IMAGE_GUID_STR;
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "sysfw.itb";
+ };
+ };
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_J721E_A72_EVM
@@ -587,4 +617,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See j721e_evm.h
+#define J721E_SK_SPL_IMAGE_GUID_STR "86f710ad-10cf-46ea-ac67-856ae06efad2"
+#define J721E_SK_UBOOT_IMAGE_GUID_STR "81b58fb0-3b00-4add-a20a-c185bbaca1ed"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = J721E_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = J721E_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
index 4f97af4..586ddb6 100644
--- a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
+++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
@@ -107,3 +107,32 @@
};
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsue update GUIDs. See beagleboneai64.h.
+#define BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR "772a4810-2194-4923-8754-0115870ef367"
+#define BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR "dfc9c683-49b7-46bd-b3c1-3a3b2fdb135b"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR;
+ };
+};
+
+&binman {
+ capsule-sysfw {
+ filename = "sysfw-capsule.bin";
+ efi-capsule {
+ image-index = <0x4>;
+ image-guid = BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR;
+ private-key = "arch/arm/mach-k3/keys/custMpk.pem";
+ public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt";
+ monotonic-count = <0x1>;
+
+ blob {
+ filename = "sysfw.itb";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi
index 146cd76..85bdd1f 100644
--- a/arch/arm/dts/k3-j784s4-binman.dtsi
+++ b/arch/arm/dts/k3-j784s4-binman.dtsi
@@ -157,6 +157,22 @@
};
};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form. See j784s4_evm.h
+#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR;
+
+ blob {
+ filename = "tiboot3-j784s4-hs-fs-evm.bin";
+ };
+ };
+};
+
#endif
#ifdef CONFIG_TARGET_J784S4_A72_EVM
@@ -343,4 +359,23 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form. See j784s4_evm.h
+#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e"
+#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617"
+
+&capsule_tispl {
+ efi-capsule {
+ image-guid = AM69_SK_SPL_IMAGE_GUID_STR;
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR;
+ };
+};
+
#endif
diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi
deleted file mode 100644
index 3429e12..0000000
--- a/arch/arm/dts/px30-engicam-common.dtsi
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/ {
- aliases {
- mmc1 = &sdmmc;
- mmc2 = &sdio;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys"; /* +5V */
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&xin32k>;
- clock-names = "ext_clock";
- post-power-on-delay-ms = <80>;
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
- };
-
- vcc3v3_btreg: vcc3v3-btreg {
- compatible = "regulator-gpio";
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&bt_enable_h>;
- regulator-name = "btreg-gpio-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- states = <3300000 0x0>;
- };
-
- vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_rf_aux_mod";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vcc5v0_sys>;
- };
-
- xin32k: xin32k {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- };
-};
-
-&sdio {
- #address-cells = <1>;
- #size-cells = <0>;
- bus-width = <4>;
- clock-frequency = <50000000>;
- cap-sdio-irq;
- cap-sd-highspeed;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- sd-uhs-sdr104;
- status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- };
-};
-
-&gmac {
- clock_in_out = "output";
- phy-supply = <&vcc_3v3>; /* +3V3_SOM */
- snps,reset-active-low;
- snps,reset-delays-us = <0 50000 50000>;
- snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&sdmmc {
- cap-sd-highspeed;
- card-detect-delay = <800>;
- vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */
- vqmmc-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_host: host-port {
- status = "okay";
- };
-
- u2phy_otg: otg-port {
- status = "okay";
- };
-};
-
-&uart2 {
- pinctrl-0 = <&uart2m1_xfer>;
- status = "okay";
-};
-
-&usb20_otg {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi
deleted file mode 100644
index bf10a3d..0000000
--- a/arch/arm/dts/px30-engicam-ctouch2.dtsi
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-#include "px30-engicam-common.dtsi"
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdio_pwrseq {
- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-};
-
-&vcc3v3_btreg {
- enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
-};
diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
deleted file mode 100644
index 449b8eb..0000000
--- a/arch/arm/dts/px30-engicam-edimm2.2.dtsi
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-#include "px30-engicam-common.dtsi"
-
-/ {
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm0 0 25000 0>;
- };
-
- panel {
- compatible = "yes-optoelectronics,ytc700tlag-05-201c";
- backlight = <&backlight>;
- data-mapping = "vesa-24";
- power-supply = <&vcc3v3_lcd>;
-
- port {
- panel_in_lvds: endpoint {
- remote-endpoint = <&lvds_out_panel>;
- };
- };
- };
-};
-
-&display_subsystem {
- status = "okay";
-};
-
-&dsi_dphy {
- status = "okay";
-};
-
-/* LVDS_B(secondary) */
-&lvds {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
-
- lvds_out_panel: endpoint {
- remote-endpoint = <&panel_in_lvds>;
- };
- };
- };
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
deleted file mode 100644
index 47aa305..0000000
--- a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include "px30-engicam-ctouch2.dtsi"
-#include "px30-engicam-px30-core.dtsi"
-
-/ {
- model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
- compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
- "rockchip,px30";
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm0 0 25000 0>;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- panel {
- compatible = "ampire,am-1280800n3tzqw-t00h";
- backlight = <&backlight>;
- power-supply = <&vcc3v3_lcd>;
- data-mapping = "vesa-24";
-
- port {
- panel_in_lvds: endpoint {
- remote-endpoint = <&lvds_out_panel>;
- };
- };
- };
-};
-
-&display_subsystem {
- status = "okay";
-};
-
-&dsi_dphy {
- status = "okay";
-};
-
-&lvds {
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
-
- lvds_out_panel: endpoint {
- remote-endpoint = <&panel_in_lvds>;
- };
- };
- };
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
deleted file mode 100644
index 5a0ecb8..0000000
--- a/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include "px30-engicam-ctouch2.dtsi"
-#include "px30-engicam-px30-core.dtsi"
-
-/ {
- model = "Engicam PX30.Core C.TOUCH 2.0";
- compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
- "rockchip,px30";
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-};
diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
deleted file mode 100644
index d759478..0000000
--- a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include "px30-engicam-edimm2.2.dtsi"
-#include "px30-engicam-px30-core.dtsi"
-
-/ {
- model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
- compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
- "rockchip,px30";
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-};
-
-&pinctrl {
- bt {
- bt_enable_h: bt-enable-h {
- rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&sdio_pwrseq {
- reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
-};
-
-&vcc3v3_btreg {
- enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
-};
diff --git a/arch/arm/dts/px30-engicam-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi
deleted file mode 100644
index 7249871..0000000
--- a/arch/arm/dts/px30-engicam-px30-core.dtsi
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutons
- * Copyright (c) 2020 Amarula Solutons(India)
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-
-/ {
- compatible = "engicam,px30-core", "rockchip,px30";
-
- aliases {
- mmc0 = &emmc;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
- rockchip,system-power-controller;
- wakeup-source;
- #clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v3: DCDC_REG4 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc3v3_sys: DCDC_REG5 {
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v0: LDO_REG1 {
- regulator-name = "vcc_1v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_1v8: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_1v0: LDO_REG3 {
- regulator-name = "vdd_1v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc3v0_pmu: LDO_REG4 {
- regulator-name = "vcc3v0_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
-
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc3v3_lcd: SWITCH_REG1 {
- regulator-boot-on;
- regulator-name = "vcc3v3_lcd";
- };
-
- vcc5v0_host: SWITCH_REG2 {
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&io_domains {
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vcc_3v3>;
- vccio3-supply = <&vcc_3v3>;
- vccio4-supply = <&vcc_3v3>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&pinctrl {
- pmic {
- pmic_int: pmic_int {
- rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc_3v3>;
- pmuio2-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts
deleted file mode 100644
index 848bc39..0000000
--- a/arch/arm/dts/px30-evb.dts
+++ /dev/null
@@ -1,634 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "px30.dtsi"
-
-/ {
- model = "Rockchip PX30 EVB";
- compatible = "rockchip,px30-evb", "rockchip,px30";
-
- aliases {
- mmc0 = &sdmmc;
- mmc1 = &sdio;
- mmc2 = &emmc;
- };
-
- chosen {
- stdout-path = "serial5:115200n8";
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
- poll-interval = <100>;
-
- esc-key {
- label = "esc";
- linux,code = <KEY_ESC>;
- press-threshold-microvolt = <1310000>;
- };
-
- home-key {
- label = "home";
- linux,code = <KEY_HOME>;
- press-threshold-microvolt = <624000>;
- };
-
- menu-key {
- label = "menu";
- linux,code = <KEY_MENU>;
- press-threshold-microvolt = <987000>;
- };
-
- vol-down-key {
- label = "volume down";
- linux,code = <KEY_VOLUMEDOWN>;
- press-threshold-microvolt = <300000>;
- };
-
- vol-up-key {
- label = "volume up";
- linux,code = <KEY_VOLUMEUP>;
- press-threshold-microvolt = <17000>;
- };
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 25000 0>;
- power-supply = <&vcc3v3_lcd>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- pinctrl-0 = <&emmc_reset>;
- pinctrl-names = "default";
- reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h>;
-
- /*
- * On the module itself this is one of these (depending
- * on the actual card populated):
- * - SDIO_RESET_L_WL_REG_ON
- * - PDN (power down when low)
- */
- reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
- };
-
- vcc5v0_sys: vccsys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&csi_dphy {
- status = "okay";
-};
-
-&display_subsystem {
- status = "okay";
-};
-
-&dsi {
- status = "okay";
-
- ports {
- mipi_out: port@1 {
- reg = <1>;
-
- mipi_out_panel: endpoint {
- remote-endpoint = <&mipi_in_panel>;
- };
- };
- };
-
- panel@0 {
- compatible = "xinpeng,xpp055c272";
- reg = <0>;
- backlight = <&backlight>;
- iovcc-supply = <&vcc_1v8>;
- vci-supply = <&vcc3v3_lcd>;
-
- port {
- mipi_in_panel: endpoint {
- remote-endpoint = <&mipi_out_panel>;
- };
- };
- };
-};
-
-&dsi_dphy {
- status = "okay";
-};
-
-&emmc {
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- non-removable;
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v0>;
- vqmmc-supply = <&vccio_flash>;
- status = "okay";
-};
-
-&gmac {
- clock_in_out = "output";
- phy-supply = <&vcc_rmii>;
- snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 50000 50000>;
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_log>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
- rockchip,system-power-controller;
- wakeup-source;
- #clock-cells = <0>;
- clock-output-names = "xin32k";
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v0: vcc_rmii: DCDC_REG4 {
- regulator-name = "vcc_3v0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_sys: DCDC_REG5 {
- regulator-name = "vcc3v3_sys";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v0: LDO_REG1 {
- regulator-name = "vcc_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_1v0: LDO_REG3 {
- regulator-name = "vdd_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc3v0_pmu: LDO_REG4 {
- regulator-name = "vcc3v0_pmu";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_sd: LDO_REG6 {
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc2v8_dvp: LDO_REG7 {
- regulator-name = "vcc2v8_dvp";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <2800000>;
- };
- };
-
- vcc1v8_dvp: LDO_REG8 {
- regulator-name = "vcc1v8_dvp";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v5_dvp: LDO_REG9 {
- regulator-name = "vcc1v5_dvp";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcc3v3_lcd: SWITCH_REG1 {
- regulator-name = "vcc3v3_lcd";
- regulator-boot-on;
- };
-
- vcc5v0_host: SWITCH_REG2 {
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-
- sensor@d {
- compatible = "asahi-kasei,ak8963";
- reg = <0x0d>;
- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- vdd-supply = <&vcc3v0_pmu>;
- mount-matrix = "1", /* x0 */
- "0", /* y0 */
- "0", /* z0 */
- "0", /* x1 */
- "1", /* y1 */
- "0", /* z1 */
- "0", /* x2 */
- "0", /* y2 */
- "1"; /* z2 */
- };
-
- touchscreen@14 {
- compatible = "goodix,gt1151";
- reg = <0x14>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
- irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
- reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
- VDDIO-supply = <&vcc3v3_lcd>;
- };
-
- sensor@4c {
- compatible = "fsl,mma7660";
- reg = <0x4c>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&i2c2 {
- status = "okay";
-
- clock-frequency = <100000>;
-
- /* These are relatively safe rise/fall times; TODO: measure */
- i2c-scl-falling-time-ns = <50>;
- i2c-scl-rising-time-ns = <300>;
-
- ov5695: ov5695@36 {
- compatible = "ovti,ov5695";
- reg = <0x36>;
- avdd-supply = <&vcc2v8_dvp>;
- clocks = <&cru SCLK_CIF_OUT>;
- clock-names = "xvclk";
- dvdd-supply = <&vcc1v5_dvp>;
- dovdd-supply = <&vcc1v8_dvp>;
- pinctrl-names = "default";
- pinctrl-0 = <&cif_clkout_m0>;
- reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
-
- port {
- ucam_out: endpoint {
- remote-endpoint = <&mipi_in_ucam>;
- data-lanes = <1 2>;
- };
- };
- };
-};
-
-&i2s1_2ch {
- status = "okay";
-};
-
-&io_domains {
- status = "okay";
-
- vccio1-supply = <&vccio_sdio>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_3v0>;
- vccio4-supply = <&vcc3v0_pmu>;
- vccio5-supply = <&vcc_3v0>;
- vccio6-supply = <&vccio_flash>;
-};
-
-&isp {
- status = "okay";
-
- ports {
- port@0 {
- mipi_in_ucam: endpoint@0 {
- reg = <0>;
- data-lanes = <1 2>;
- remote-endpoint = <&ucam_out>;
- };
- };
- };
-};
-
-&isp_mmu {
- status = "okay";
-};
-
-&pinctrl {
- headphone {
- hp_det: hp-det {
- rockchip,pins =
- <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- emmc {
- emmc_reset: emmc-reset {
- rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic_int {
- rockchip,pins =
- <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- soc_slppin_gpio: soc_slppin_gpio {
- rockchip,pins =
- <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
- };
-
- soc_slppin_slp: soc_slppin_slp {
- rockchip,pins =
- <0 RK_PA4 1 &pcfg_pull_none>;
- };
-
- soc_slppin_rst: soc_slppin_rst {
- rockchip,pins =
- <0 RK_PA4 2 &pcfg_pull_none>;
- };
- };
-
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins =
- <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- status = "okay";
-
- pmuio1-supply = <&vcc3v0_pmu>;
- pmuio2-supply = <&vcc3v0_pmu>;
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- cap-mmc-highspeed;
- cap-sd-highspeed;
- card-detect-delay = <800>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sdio {
- cap-sd-highspeed;
- keep-power-in-suspend;
- non-removable;
- mmc-pwrseq = <&sdio_pwrseq>;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <1>;
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_host: host-port {
- status = "okay";
- };
-
- u2phy_otg: otg-port {
- status = "okay";
- };
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts>;
- status = "okay";
-};
-
-&uart5 {
- status = "okay";
-};
-
-&usb20_otg {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&vopl {
- status = "okay";
-};
-
-&vopl_mmu {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
index e04766a..29ea276 100644
--- a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
+++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi
@@ -15,14 +15,6 @@
};
};
-&binman {
- simple-bin {
- fit {
- offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>;
- };
- };
-};
-
&emmc_clk {
bootph-all;
};
diff --git a/arch/arm/dts/px30-ringneck-haikou.dts b/arch/arm/dts/px30-ringneck-haikou.dts
deleted file mode 100644
index 08a3ad3..0000000
--- a/arch/arm/dts/px30-ringneck-haikou.dts
+++ /dev/null
@@ -1,232 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-#include "px30-ringneck.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit";
- compatible = "tsd,px30-ringneck-haikou", "rockchip,px30";
-
- aliases {
- mmc2 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&haikou_keys_pin>;
- pinctrl-names = "default";
-
- button-batlow-n {
- label = "BATLOW#";
- linux,code = <KEY_BATTERY>;
- gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
- };
-
- button-slp-btn-n {
- label = "SLP_BTN#";
- linux,code = <KEY_SLEEP>;
- gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
- };
-
- button-wake-n {
- label = "WAKE#";
- linux,code = <KEY_WAKEUP>;
- gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
- wakeup-source;
- };
-
- switch-lid-btn-n {
- label = "LID_BTN#";
- linux,code = <SW_LID>;
- linux,input-type = <EV_SW>;
- gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
-
- sd_card_led: led-1 {
- gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc2";
- function = LED_FUNCTION_SD;
- color = <LED_COLOR_ID_BLUE>;
- };
- };
-
- i2s0-sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,name = "Haikou,I2S-codec";
- simple-audio-card,mclk-fs = <512>;
-
- simple-audio-card,codec {
- clocks = <&sgtl5000_clk>;
- sound-dai = <&sgtl5000>;
- };
-
- simple-audio-card,cpu {
- bitclock-master;
- frame-master;
- sound-dai = <&i2s0_8ch>;
- };
- };
-
- sgtl5000_clk: sgtl5000-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- };
-
- dc_12v: dc-12v-regulator {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc3v3_baseboard: vcc3v3-baseboard-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_baseboard";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_baseboard: vcc5v0-baseboard-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_baseboard";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vdda_codec: vdda-codec-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vdda_codec";
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_baseboard>;
- };
-
- vddd_codec: vddd-codec-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vddd_codec";
- regulator-boot-on;
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1600000>;
- vin-supply = <&vcc5v0_baseboard>;
- };
-};
-
-&i2c2 {
- status = "okay";
- clock-frequency = <400000>;
-
- sgtl5000: codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- clocks = <&sgtl5000_clk>;
- #sound-dai-cells = <0>;
- VDDA-supply = <&vdda_codec>;
- VDDIO-supply = <&vcc3v3_baseboard>;
- VDDD-supply = <&vddd_codec>;
- };
-};
-
-&i2c3 {
- eeprom@50 {
- reg = <0x50>;
- compatible = "atmel,24c01";
- pagesize = <8>;
- size = <128>;
- vcc-supply = <&vcc3v3_baseboard>;
- };
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&pinctrl {
- haikou {
- haikou_keys_pin: haikou-keys-pin {
- rockchip,pins =
- /* WAKE# */
- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
- /* SLP_BTN# */
- <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
- /* LID_BTN */
- <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- /* BATLOW# */
- <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
- /* BIOS_DISABLE# */
- <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- leds {
- sd_card_led_pin: sd-card-led-pin {
- rockchip,pins =
- <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm0 {
- status = "okay";
-};
-
-&sdmmc {
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
- disable-wp;
- vmmc-supply = <&vcc3v3_baseboard>;
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-};
-
-&u2phy_otg {
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart5 {
- pinctrl-0 = <&uart5_xfer>;
- status = "okay";
-};
-
-&usb20_otg {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-ringneck.dtsi b/arch/arm/dts/px30-ringneck.dtsi
deleted file mode 100644
index 1239775..0000000
--- a/arch/arm/dts/px30-ringneck.dtsi
+++ /dev/null
@@ -1,382 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include <dt-bindings/leds/common.h>
-
-/ {
- aliases {
- mmc0 = &emmc;
- mmc1 = &sdio;
- rtc0 = &rtc_twi;
- rtc1 = &rk809;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- pinctrl-0 = <&emmc_reset>;
- pinctrl-names = "default";
- reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&module_led_pin>;
- status = "okay";
-
- module_led: led-0 {
- gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_HEARTBEAT;
- linux,default-trigger = "heartbeat";
- color = <LED_COLOR_ID_AMBER>;
- };
- };
-
- vcc5v0_sys: vccsys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- supports-emmc;
- mmc-pwrseq = <&emmc_pwrseq>;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_emmc>;
-
- status = "okay";
-};
-
-/* On-module TI DP83825I PHY but no connector, enable in carrierboard */
-&gmac {
- snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 50000 50000>;
- phy-supply = <&vcc_3v3>;
- clock_in_out = "output";
-};
-
-&gpio2 {
- /*
- * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module
- * eMMC powered-down initially (in fact it keeps the reset signal
- * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after
- * the SPL has been booted from SD Card.
- */
- bios-disable-override-hog {
- gpios = <RK_PB5 GPIO_ACTIVE_LOW>;
- output-high;
- line-name = "bios_disable_override";
- gpio-hog;
- };
-
- /*
- * The BIOS_DISABLE hog is a feedback pin for the actual status of the
- * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually
- * represents the state of a switch on the baseboard.
- */
- bios-disable-n-hog {
- gpios = <RK_PC2 GPIO_ACTIVE_LOW>;
- line-name = "bios_disable";
- input;
- gpio-hog;
- };
-};
-
-&gpu {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-0 = <&pmic_int>;
- pinctrl-names = "default";
- #clock-cells = <0>;
- clock-output-names = "xin32k";
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
- vcc4-supply = <&vcc5v0_sys>;
- vcc5-supply = <&vcc_3v3>;
- vcc6-supply = <&vcc_3v3>;
- vcc7-supply = <&vcc_3v3>;
- vcc9-supply = <&vcc5v0_sys>;
-
- regulators {
- vdd_log: DCDC_REG1 {
- regulator-name = "vdd_log";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v0_1v8: vcc_emmc: DCDC_REG4 {
- regulator-name = "vcc_3v0_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc_3v3: DCDC_REG5 {
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v8: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_1v0: LDO_REG3 {
- regulator-name = "vcc_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_lcd: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-name = "vcc_lcd";
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_1v8_lcd: LDO_REG8 {
- regulator-name = "vcc_1v8_lcd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca_1v8: LDO_REG9 {
- regulator-name = "vcca_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-
- /* SE05x is limited to Fast Mode */
- clock-frequency = <400000>;
-
- fan: fan@18 {
- compatible = "ti,amc6821";
- reg = <0x18>;
- #cooling-cells = <2>;
- };
-
- rtc_twi: rtc@6f {
- compatible = "isil,isl1208";
- reg = <0x6f>;
- };
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&i2s0_8ch {
- rockchip,trcm-sync-tx-only;
-
- pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx
- &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>;
-};
-
-&io_domains {
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_3v3>;
- vccio4-supply = <&vcc_3v3>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_emmc>;
- vccio-oscgpi-supply = <&vcc_3v3>;
-
- status = "okay";
-};
-
-&pinctrl {
- emmc {
- emmc_reset: emmc-reset {
- rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- leds {
- module_led_pin: module-led-pin {
- rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic-int {
- rockchip,pins =
- <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- vqmmc-supply = <&vccio_sd>;
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-};
-
-&u2phy_host {
- status = "okay";
-};
-
-/* Mule UCAN */
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&wdt {
- status = "okay";
-};
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 046da02..59fa9f4 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -33,11 +33,27 @@
bootph-all;
};
+&uart2m0_xfer {
+ bootph-all;
+};
+
&uart5 {
clock-frequency = <24000000>;
bootph-all;
};
+&uart5_cts {
+ bootph-all;
+};
+
+&uart5_rts {
+ bootph-all;
+};
+
+&uart5_xfer {
+ bootph-all;
+};
+
&sdmmc {
bootph-all;
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 04028bf..a31dea8 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -74,6 +74,21 @@
bootph-all;
};
+&rk817 {
+ regulators {
+ vcc_cam: LDO_REG9 {
+ regulator-name = "vcc_cam";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+ };
+};
+
&saradc {
bootph-all;
status = "okay";
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
deleted file mode 100644
index ea0695b..0000000
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ /dev/null
@@ -1,642 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Hardkernel Co., Ltd
- * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3326.dtsi"
-
-/ {
- model = "ODROID-GO Advance";
- compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
-
- aliases {
- mmc0 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- adc-joystick {
- compatible = "adc-joystick";
- io-channels = <&saradc 1>,
- <&saradc 2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- axis@0 {
- reg = <0>;
- abs-flat = <10>;
- abs-fuzz = <10>;
- abs-range = <172 772>;
- linux,code = <ABS_X>;
- };
-
- axis@1 {
- reg = <1>;
- abs-flat = <10>;
- abs-fuzz = <10>;
- abs-range = <278 815>;
- linux,code = <ABS_Y>;
- };
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- power-supply = <&vcc_bl>;
- pwms = <&pwm1 0 25000 0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&btn_pins>;
-
- /*
- * *** ODROIDGO2-Advance Switch layout ***
- * |------------------------------------------------|
- * | sw15 sw16 |
- * |------------------------------------------------|
- * | sw1 |-------------------| sw8 |
- * | sw3 sw4 | | sw7 sw5 |
- * | sw2 | LCD Display | sw6 |
- * | | | |
- * | |-------------------| |
- * | sw9 sw10 sw11 sw12 sw13 sw14 |
- * |------------------------------------------------|
- */
-
- sw1 {
- gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
- label = "DPAD-UP";
- linux,code = <BTN_DPAD_UP>;
- };
- sw2 {
- gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
- label = "DPAD-DOWN";
- linux,code = <BTN_DPAD_DOWN>;
- };
- sw3 {
- gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
- label = "DPAD-LEFT";
- linux,code = <BTN_DPAD_LEFT>;
- };
- sw4 {
- gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
- label = "DPAD-RIGHT";
- linux,code = <BTN_DPAD_RIGHT>;
- };
- sw5 {
- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
- label = "BTN-A";
- linux,code = <BTN_EAST>;
- };
- sw6 {
- gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "BTN-B";
- linux,code = <BTN_SOUTH>;
- };
- sw7 {
- gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
- label = "BTN-Y";
- linux,code = <BTN_WEST>;
- };
- sw8 {
- gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
- label = "BTN-X";
- linux,code = <BTN_NORTH>;
- };
- sw9 {
- gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
- label = "F1";
- linux,code = <BTN_TRIGGER_HAPPY1>;
- };
- sw10 {
- gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
- label = "F2";
- linux,code = <BTN_TRIGGER_HAPPY2>;
- };
- sw11 {
- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
- label = "F3";
- linux,code = <BTN_TRIGGER_HAPPY3>;
- };
- sw12 {
- gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
- label = "F4";
- linux,code = <BTN_TRIGGER_HAPPY4>;
- };
- sw13 {
- gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
- label = "F5";
- linux,code = <BTN_TRIGGER_HAPPY5>;
- };
- sw14 {
- gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "F6";
- linux,code = <BTN_TRIGGER_HAPPY6>;
- };
- sw15 {
- gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
- label = "TOP-LEFT";
- linux,code = <BTN_TL>;
- };
- sw16 {
- gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
- label = "TOP-RIGHT";
- linux,code = <BTN_TR>;
- };
- };
-
- leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&blue_led_pin>;
-
- blue_led: led-0 {
- label = "blue:heartbeat";
- gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- rk817-sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "Analog";
- simple-audio-card,format = "i2s";
- simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Headphone", "Headphones",
- "Speaker", "Speaker";
- simple-audio-card,routing =
- "MICL", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR",
- "Speaker", "SPKO";
-
- simple-audio-card,codec {
- sound-dai = <&rk817>;
- };
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_2ch>;
- };
- };
-
- vccsys: vccsys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v8_sys";
- regulator-always-on;
- regulator-min-microvolt = <3800000>;
- regulator-max-microvolt = <3800000>;
- };
-
- vcc_host: vcc_host {
- compatible = "regulator-fixed";
- regulator-name = "vcc_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&usb_midu>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cru {
- assigned-clocks = <&cru PLL_NPLL>,
- <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
- <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
- <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
- <&cru PLL_CPLL>;
-
- assigned-clock-rates = <1188000000>,
- <200000000>, <200000000>,
- <150000000>, <150000000>,
- <100000000>, <200000000>,
- <17000000>;
-};
-
-&display_subsystem {
- status = "okay";
-};
-
-&dsi {
- status = "okay";
-
- ports {
- mipi_out: port@1 {
- reg = <1>;
-
- mipi_out_panel: endpoint {
- remote-endpoint = <&mipi_in_panel>;
- };
- };
- };
-
- panel@0 {
- compatible = "elida,kd35t133";
- reg = <0>;
- backlight = <&backlight>;
- iovcc-supply = <&vcc_lcd>;
- reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
- rotation = <270>;
- vdd-supply = <&vcc_lcd>;
-
- port {
- mipi_in_panel: endpoint {
- remote-endpoint = <&mipi_out_panel>;
- };
- };
- };
-};
-
-&dsi_dphy {
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_logic>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-falling-time-ns = <16>;
- i2c-scl-rising-time-ns = <280>;
- status = "okay";
-
- rk817: pmic@20 {
- compatible = "rockchip,rk817";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
- clock-output-names = "rk808-clkout1", "xin32k";
- clock-names = "mclk";
- clocks = <&cru SCLK_I2S1_OUT>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
- wakeup-source;
- #clock-cells = <1>;
- #sound-dai-cells = <0>;
-
- vcc1-supply = <&vccsys>;
- vcc2-supply = <&vccsys>;
- vcc3-supply = <&vccsys>;
- vcc4-supply = <&vccsys>;
- vcc5-supply = <&vccsys>;
- vcc6-supply = <&vccsys>;
- vcc7-supply = <&vccsys>;
- vcc8-supply = <&vccsys>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v3: DCDC_REG4 {
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v8: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_1v0: LDO_REG3 {
- regulator-name = "vdd_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc3v3_pmu: LDO_REG4 {
- regulator-name = "vcc3v3_pmu";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_sd: LDO_REG6 {
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_bl: LDO_REG7 {
- regulator-name = "vcc_bl";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_lcd: LDO_REG8 {
- regulator-name = "vcc_lcd";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <2800000>;
- };
- };
-
- vcc_cam: LDO_REG9 {
- regulator-name = "vcc_cam";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- usb_midu: BOOST {
- regulator-name = "usb_midu";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5400000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
-
- rk817_codec: codec {
- rockchip,mic-in-differential;
- };
- };
-};
-
-/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
-&i2c1 {
- clock-frequency = <400000>;
- status = "okay";
-};
-
-/* I2S 1 Channel Used */
-&i2s1_2ch {
- status = "okay";
-};
-
-&io_domains {
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_3v3>;
- vccio4-supply = <&vcc_3v3>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- status = "okay";
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- cap-sd-highspeed;
- card-detect-delay = <200>;
- cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sfc {
- pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <108000000>;
- spi-rx-bus-width = <2>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_host: host-port {
- status = "okay";
- };
-
- u2phy_otg: otg-port {
- status = "disabled";
- };
-};
-
-&usb20_otg {
- status = "okay";
-};
-
-/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m1_xfer>;
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&pinctrl {
- btns {
- btn_pins: btn-pins {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- headphone {
- hp_det: hp-det {
- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- leds {
- blue_led_pin: blue-led-pin {
- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- dc_det: dc-det {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pmic_int: pmic-int {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- soc_slppin_gpio: soc_slppin_gpio {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
- };
-
- soc_slppin_rst: soc_slppin_rst {
- rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
- };
-
- soc_slppin_slp: soc_slppin_slp {
- rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
- };
- };
-};
diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
index 5a9bd32..55895d0 100644
--- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
@@ -33,12 +33,6 @@
};
&binman {
- simple-bin {
- fit {
- offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>;
- };
- };
-
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
simple-bin-spi {
fit {
diff --git a/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
new file mode 100644
index 0000000..af96d2f
--- /dev/null
+++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 ArmSoM Technology Co., Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 0000000..275ae6f
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+};
+
+&emmc_pwrseq {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_reset {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdhci {
+ /* U-Boot currently cannot handle anything below HS200 for eMMC on RK3588 */
+ /delete-property/ mmc-ddr-1_8v;
+ /delete-property/ cap-mmc-highspeed;
+};
+
+&uart2m2_xfer {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
index 4623580..bfe6645 100644
--- a/arch/arm/dts/rk3588-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-u-boot.dtsi
@@ -4,77 +4,3 @@
*/
#include "rk3588s-u-boot.dtsi"
-
-/ {
- usb_host1_xhci: usb@fc400000 {
- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
- reg = <0x0 0xfc400000 0x0 0x400000>;
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
- <&cru ACLK_USB3OTG1>;
- clock-names = "ref_clk", "suspend_clk", "bus_clk";
- dr_mode = "otg";
- phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- power-domains = <&power RK3588_PD_USB>;
- resets = <&cru SRST_A_USB3OTG1>;
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- status = "disabled";
- };
-
- usbdpphy1_grf: syscon@fd5cc000 {
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
- reg = <0x0 0xfd5cc000 0x0 0x4000>;
- };
-
- usb2phy1_grf: syscon@fd5d4000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfd5d4000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy1: usb2phy@4000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x4000 0x10>;
- #clock-cells = <0>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy1";
- interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
- reset-names = "phy", "apb";
- status = "disabled";
-
- u2phy1_otg: otg-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- usbdp_phy1: phy@fed90000 {
- compatible = "rockchip,rk3588-usbdp-phy";
- reg = <0x0 0xfed90000 0x0 0x10000>;
- #phy-cells = <1>;
- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
- <&cru CLK_USBDP_PHY1_IMMORTAL>,
- <&cru PCLK_USBDPPHY1>,
- <&u2phy1>;
- clock-names = "refclk", "immortal", "pclk", "utmi";
- resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
- <&cru SRST_USBDP_COMBO_PHY1_CMN>,
- <&cru SRST_USBDP_COMBO_PHY1_LANE>,
- <&cru SRST_USBDP_COMBO_PHY1_PCS>,
- <&cru SRST_P_USBDPPHY1>;
- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
- rockchip,u2phy-grf = <&usb2phy1_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
- rockchip,vo-grf = <&vo0_grf>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index e9d38d5..09d8b31 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -19,95 +19,10 @@
bootph-all;
};
- usb_host0_xhci: usb@fc000000 {
- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
- reg = <0x0 0xfc000000 0x0 0x400000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
- <&cru ACLK_USB3OTG0>;
- clock-names = "ref_clk", "suspend_clk", "bus_clk";
- dr_mode = "otg";
- phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- power-domains = <&power RK3588_PD_USB>;
- resets = <&cru SRST_A_USB3OTG0>;
- snps,dis_enblslpm_quirk;
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- status = "disabled";
- };
-
- vo0_grf: syscon@fd5a6000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a6000 0x0 0x2000>;
- clocks = <&cru PCLK_VO0GRF>;
- };
-
- usb_grf: syscon@fd5ac000 {
- compatible = "rockchip,rk3588-usb-grf", "syscon";
- reg = <0x0 0xfd5ac000 0x0 0x4000>;
- };
-
- usbdpphy0_grf: syscon@fd5c8000 {
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
- reg = <0x0 0xfd5c8000 0x0 0x4000>;
- };
-
- usb2phy0_grf: syscon@fd5d0000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfd5d0000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy0: usb2phy@0 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x0 0x10>;
- #clock-cells = <0>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy0";
- interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
- reset-names = "phy", "apb";
- status = "disabled";
-
- u2phy0_otg: otg-port {
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
rng: rng@fe378000 {
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
};
-
- usbdp_phy0: phy@fed80000 {
- compatible = "rockchip,rk3588-usbdp-phy";
- reg = <0x0 0xfed80000 0x0 0x10000>;
- #phy-cells = <1>;
- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
- <&cru CLK_USBDP_PHY0_IMMORTAL>,
- <&cru PCLK_USBDPPHY0>,
- <&u2phy0>;
- clock-names = "refclk", "immortal", "pclk", "utmi";
- resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
- <&cru SRST_USBDP_COMBO_PHY0_CMN>,
- <&cru SRST_USBDP_COMBO_PHY0_LANE>,
- <&cru SRST_USBDP_COMBO_PHY0_PCS>,
- <&cru SRST_P_USBDPPHY0>;
- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
- rockchip,u2phy-grf = <&usb2phy0_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
- rockchip,vo-grf = <&vo0_grf>;
- status = "disabled";
- };
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 661e7fd..14b3ab1 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -3,6 +3,7 @@
config ROCKCHIP_PX30
bool "Support Rockchip PX30"
select ARM64
+ imply OF_UPSTREAM
select SUPPORT_SPL
select SUPPORT_TPL
select SPL
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 820e979..9a35c7d 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -161,6 +161,31 @@
USB PD over USB Type-C
Size: 100mm x 72mm (Pico-ITX form factor)
+config TARGET_SIGE7_RK3588
+ bool "ArmSoM Sige7 RK3588 board"
+ select BOARD_LATE_INIT
+ help
+ ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer)
+ by ArmSoM.
+
+ There are two variants depending on the DRAM size : 8G and 16G.
+
+ Specification:
+
+ Rockchip Rk3588 SoC
+ 4x ARM Cortex-A76, 4x ARM Cortex-A55
+ 8/16GB memory LPDDR4x
+ Mali G610MC4 GPU
+ 2x MIPI CSI 2 multiple lanes connector
+ 64GB/128GB on board eMMC
+ uSD slot
+ 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C
+ 1x HDMI 2.1 output
+ 2x 2.5 Gbps Ethernet port
+ 40-pin IO header including UART, SPI and I2C
+ USB PD over USB Type-C
+ Size: 92mm x 62mm
+
config TARGET_QUARTZPRO64_RK3588
bool "Pine64 QuartzPro64 RK3588 board"
select BOARD_LATE_INIT
@@ -168,6 +193,36 @@
Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
Computer) by Pine64.
+config TARGET_TIGER_RK3588
+ bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)"
+ select BOARD_LATE_INIT
+ help
+ The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
+ connector) system-on-module from Theobroma Systems, featuring the
+ Rockchip RK3588.
+
+ It provides the following feature set:
+ * up to 16GB LPDDR4x
+ * on-module eMMC
+ * SD card (on a baseboard) via edge connector
+ * Gigabit Ethernet with on-module GbE PHY
+ * HDMI/eDP
+ * MIPI-DSI
+ * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
+ * HDMI input over FPC connector
+ * CAN
+ * USB
+ - 1x USB 3.0 dual-role (direct connection)
+ - 2x USB 3.0 host + 1x USB 2.0 host
+ * PCIe
+ - 1x PCIe 2.1 Gen3, 4 lanes
+ - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
+ * on-module ATtiny816 companion controller, implementing:
+ - low-power RTC functionality (ISL1208 emulation)
+ - fan controller (AMC6821 emulation)
+ * on-module Secure Element with Global Platform 2.2.1 compliant
+ JavaCard environment
+
config TARGET_TURINGRK1_RK3588
bool "Turing Machines RK1 RK3588 board"
select BOARD_LATE_INIT
@@ -230,6 +285,7 @@
config TEXT_BASE
default 0x00a00000
+source "board/armsom/sige7-rk3588/Kconfig"
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
source "board/indiedroid/nova/Kconfig"
@@ -240,5 +296,6 @@
source "board/rockchip/evb_rk3588/Kconfig"
source "board/rockchip/toybrick_rk3588/Kconfig"
source "board/theobroma-systems/jaguar_rk3588/Kconfig"
+source "board/theobroma-systems/tiger_rk3588/Kconfig"
endif
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index 6bfde5e..d0a0a45 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -108,26 +108,6 @@
return 0;
};
-#if defined(CONFIG_WATCHDOG)
-void watchdog_reset(void)
-{
- mbar_writeShort(MCF_WTM_WSR, 0x5555);
- mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
-}
-
-int watchdog_disable(void)
-{
- mbar_writeShort(MCF_WTM_WCR, 0);
- return (0);
-}
-
-int watchdog_init(void)
-{
- mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
- return (0);
-}
-#endif /* #ifdef CONFIG_WATCHDOG */
-
#endif
#ifdef CONFIG_M5272
@@ -174,49 +154,6 @@
};
#endif /* CONFIG_DISPLAY_CPUINFO */
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- out_be16(&wdt->wdog_wcr, 0);
-}
-
-int watchdog_disable(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- /* reset watchdog counter */
- out_be16(&wdt->wdog_wcr, 0);
- /* disable watchdog interrupt */
- out_be16(&wdt->wdog_wirr, 0);
- /* disable watchdog timer */
- out_be16(&wdt->wdog_wrrr, 0);
-
- puts("WATCHDOG:disabled\n");
- return (0);
-}
-
-int watchdog_init(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- /* disable watchdog interrupt */
- out_be16(&wdt->wdog_wirr, 0);
-
- /* set timeout and enable watchdog */
- out_be16(&wdt->wdog_wrrr,
- (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
-
- /* reset watchdog counter */
- out_be16(&wdt->wdog_wcr, 0);
-
- puts("WATCHDOG:enabled\n");
- return (0);
-}
-#endif /* #ifdef CONFIG_WATCHDOG */
-
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5275
@@ -243,51 +180,6 @@
};
#endif /* CONFIG_DISPLAY_CPUINFO */
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- out_be16(&wdt->wsr, 0x5555);
- out_be16(&wdt->wsr, 0xaaaa);
-}
-
-int watchdog_disable(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- /* reset watchdog counter */
- out_be16(&wdt->wsr, 0x5555);
- out_be16(&wdt->wsr, 0xaaaa);
-
- /* disable watchdog timer */
- out_be16(&wdt->wcr, 0);
-
- puts("WATCHDOG:disabled\n");
- return (0);
-}
-
-int watchdog_init(void)
-{
- wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
-
- /* disable watchdog */
- out_be16(&wdt->wcr, 0);
-
- /* set timeout and enable watchdog */
- out_be16(&wdt->wmr,
- (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
-
- /* reset watchdog counter */
- out_be16(&wdt->wsr, 0x5555);
- out_be16(&wdt->wsr, 0xaaaa);
-
- puts("WATCHDOG:enabled\n");
- return (0);
-}
-#endif /* #ifdef CONFIG_WATCHDOG */
-
#endif /* #ifdef CONFIG_M5275 */
#ifdef CONFIG_M5282
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index e0be938..3c8cbd4 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -164,21 +164,6 @@
}
#endif
-#if defined(CONFIG_WATCHDOG) && !defined(CONFIG_WDT)
-void watchdog_reset (void)
-{
- int re_enable = disable_interrupts();
-
- /* Reset the 83xx watchdog */
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- immr->wdt.swsrr = 0x556c;
- immr->wdt.swsrr = 0xaa39;
-
- if (re_enable)
- enable_interrupts();
-}
-#endif
-
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 6356b02..ebce2fe 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -349,37 +349,6 @@
}
-#ifndef CONFIG_WDT
-#if defined(CONFIG_WATCHDOG)
-#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
-void
-init_85xx_watchdog(void)
-{
- mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
- TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC));
-}
-
-void
-reset_85xx_watchdog(void)
-{
- /*
- * Clear TSR(WIS) bit by writing 1
- */
- mtspr(SPRN_TSR, TSR_WIS);
-}
-
-void
-watchdog_reset(void)
-{
- int re_enable = disable_interrupts();
-
- reset_85xx_watchdog();
- if (re_enable)
- enable_interrupts();
-}
-#endif /* CONFIG_WATCHDOG */
-#endif
-
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
diff --git a/arch/sh/cpu/sh4/Makefile b/arch/sh/cpu/sh4/Makefile
index 7403a2c..6d7e05e 100644
--- a/arch/sh/cpu/sh4/Makefile
+++ b/arch/sh/cpu/sh4/Makefile
@@ -6,4 +6,4 @@
# (C) Copyright 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-obj-y = cpu.o interrupts.o watchdog.o cache.o
+obj-y = cpu.o interrupts.o cache.o
diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c
index b0ad685..47a8549 100644
--- a/arch/sh/cpu/sh4/cpu.c
+++ b/arch/sh/cpu/sh4/cpu.c
@@ -10,6 +10,16 @@
#include <net.h>
#include <netdev.h>
#include <asm/processor.h>
+#include <asm/system.h>
+
+void reset_cpu(void)
+{
+ /* Address error with SR.BL=1 first. */
+ trigger_address_error();
+
+ while (1)
+ ;
+}
int checkcpu(void)
{
diff --git a/arch/sh/cpu/sh4/watchdog.c b/arch/sh/cpu/sh4/watchdog.c
deleted file mode 100644
index c597433..0000000
--- a/arch/sh/cpu/sh4/watchdog.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <cpu_func.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/io.h>
-
-#define WDT_BASE WTCNT
-
-#define WDT_WD (1 << 6)
-#define WDT_RST_P (0)
-#define WDT_RST_M (1 << 5)
-#define WDT_ENABLE (1 << 7)
-
-#if defined(CONFIG_WATCHDOG)
-static unsigned char csr_read(void)
-{
- return inb(WDT_BASE + 0x04);
-}
-
-static void cnt_write(unsigned char value)
-{
- outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
-}
-
-static void csr_write(unsigned char value)
-{
- outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
-}
-
-void watchdog_reset(void)
-{
- outl(0x55000000, WDT_BASE + 0x08);
-}
-
-int watchdog_init(void)
-{
- /* Set overflow time*/
- cnt_write(0);
- /* Power on reset */
- csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
-
- return 0;
-}
-
-int watchdog_disable(void)
-{
- csr_write(csr_read() & ~WDT_ENABLE);
- return 0;
-}
-#endif
-
-void reset_cpu(void)
-{
- /* Address error with SR.BL=1 first. */
- trigger_address_error();
-
- while (1)
- ;
-}
diff --git a/board/Marvell/octeon_nic23/board.c b/board/Marvell/octeon_nic23/board.c
index bc9332c..cf20c97 100644
--- a/board/Marvell/octeon_nic23/board.c
+++ b/board/Marvell/octeon_nic23/board.c
@@ -249,7 +249,7 @@
* read the incorrect device ID 0x9700 (reset value) instead of 0x9702
* (restored value).
*/
-static void octeon_board_restore_pf(void *ctx)
+static void octeon_board_restore_pf(struct cyclic_info *c)
{
union cvmx_spemx_flr_pf_stopreq stopreq;
static bool start_initialized[2] = {false, false};
@@ -357,10 +357,13 @@
board_configure_qlms();
/* Register cyclic function for PCIe FLR fixup */
- cyclic = cyclic_register(octeon_board_restore_pf, 100,
- "pcie_flr_fix", NULL);
- if (!cyclic)
+ cyclic = calloc(1, sizeof(*cyclic));
+ if (cyclic) {
+ cyclic_register(cyclic, octeon_board_restore_pf, 100,
+ "pcie_flr_fix");
+ } else {
printf("Registering of cyclic function failed\n");
+ }
return 0;
}
diff --git a/board/armsom/sige7-rk3588/Kconfig b/board/armsom/sige7-rk3588/Kconfig
new file mode 100644
index 0000000..793985f
--- /dev/null
+++ b/board/armsom/sige7-rk3588/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SIGE7_RK3588
+
+config SYS_BOARD
+ default "sige7-rk3588"
+
+config SYS_VENDOR
+ default "armsom"
+
+config SYS_CONFIG_NAME
+ default "sige7-rk3588"
+
+endif
diff --git a/board/armsom/sige7-rk3588/MAINTAINERS b/board/armsom/sige7-rk3588/MAINTAINERS
new file mode 100644
index 0000000..0fba39b
--- /dev/null
+++ b/board/armsom/sige7-rk3588/MAINTAINERS
@@ -0,0 +1,7 @@
+SIGE7-RK3588
+M: Jianfeng Liu <liujianfeng1994@gmail.com>
+S: Maintained
+F: board/armsom/sige7-rk3588
+F: include/configs/sige7-rk3588.h
+F: configs/sige7-rk3588_defconfig
+F: arch/arm/dts/rk3588-armsom-sige7*
diff --git a/board/theobroma-systems/tiger_rk3588/Kconfig b/board/theobroma-systems/tiger_rk3588/Kconfig
new file mode 100644
index 0000000..2c6ac6a
--- /dev/null
+++ b/board/theobroma-systems/tiger_rk3588/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_TIGER_RK3588
+
+config SYS_BOARD
+ default "tiger_rk3588"
+
+config SYS_VENDOR
+ default "theobroma-systems"
+
+config SYS_CONFIG_NAME
+ default "tiger_rk3588"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ENV_IS_NOWHERE
+
+endif
diff --git a/board/theobroma-systems/tiger_rk3588/MAINTAINERS b/board/theobroma-systems/tiger_rk3588/MAINTAINERS
new file mode 100644
index 0000000..e5aab4b
--- /dev/null
+++ b/board/theobroma-systems/tiger_rk3588/MAINTAINERS
@@ -0,0 +1,13 @@
+TIGER-RK3588 (SOM-RK3588-Q7)
+M: Klaus Goger <klaus.goger@cherry.de>
+M: Quentin Schulz <quentin.schulz@cherry.de>
+M: Heiko Stuebner <heiko.stuebner@cherry.de>
+S: Maintained
+F: board/theobroma-systems/tiger_rk3588
+F: board/theobroma-systems/common
+F: doc/board/theobroma-systems/
+F: include/configs/tiger_rk3588.h
+F: arch/arm/dts/rk3588-tiger*
+F: configs/tiger-rk3588_defconfig
+W: https://embedded.cherry.de/product/tiger-som-rk3588-q7/
+T: git git://git.embedded.cherry.de/tiger-u-boot.git
diff --git a/board/theobroma-systems/tiger_rk3588/Makefile b/board/theobroma-systems/tiger_rk3588/Makefile
new file mode 100644
index 0000000..5c4c484
--- /dev/null
+++ b/board/theobroma-systems/tiger_rk3588/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += tiger_rk3588.o
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += ../common/common.o
+endif
diff --git a/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c b/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c
new file mode 100644
index 0000000..a6d44f1
--- /dev/null
+++ b/board/theobroma-systems/tiger_rk3588/tiger_rk3588.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <phy.h>
+#include <eth_phy.h>
+
+#include <asm/types.h>
+#include <asm/arch-rockchip/cru_rk3588.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/ioc_rk3588.h>
+#include <asm-generic/u-boot.h>
+#include <dm/device.h>
+#include <dm/uclass-id.h>
+#include <linux/bitfield.h>
+
+#include "../common/common.h"
+
+#define GPIO2C3_SEL_MASK GENMASK(15, 12)
+#define GPIO2C3_ETH0_REFCLKO_25M FIELD_PREP(GPIO2C3_SEL_MASK, 1)
+
+#define REFCLKO25M_ETH0_OUT_SEL_MASK BIT(15)
+#define REFCLKO25M_ETH0_OUT_SEL_CPLL FIELD_PREP(REFCLKO25M_ETH0_OUT_SEL_MASK, 1)
+#define REFCLKO25M_ETH0_OUT_DIV_MASK GENMASK(14, 8)
+#define REFCLKO25M_ETH0_OUT_DIV(x) FIELD_PREP(REFCLKO25M_ETH0_OUT_DIV_MASK, (x) - 1)
+
+#define REFCLKO25M_ETH0_OUT_EN BIT(4)
+
+void setup_eth0refclko(void)
+{
+ /* Configure and enable ETH0_REFCLKO_25MHz */
+ static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
+ static struct rk3588_cru * const cru = (void *)CRU_BASE;
+
+ /* 1. Pinmux */
+ rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l, GPIO2C3_SEL_MASK, GPIO2C3_ETH0_REFCLKO_25M);
+ /* 2. Parent clock selection + divider => CPLL (1.5GHz) / 60 => 25MHz */
+ rk_clrsetreg(&cru->clksel_con[15],
+ REFCLKO25M_ETH0_OUT_SEL_MASK | REFCLKO25M_ETH0_OUT_DIV_MASK,
+ REFCLKO25M_ETH0_OUT_SEL_CPLL | REFCLKO25M_ETH0_OUT_DIV(60));
+ /* 3. Enable clock */
+ rk_clrreg(&cru->clkgate_con[5], REFCLKO25M_ETH0_OUT_EN);
+}
+
+int rockchip_early_misc_init_r(void)
+{
+ setup_boottargets();
+
+ setup_eth0refclko();
+
+ return 0;
+}
diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS
index 105e741..562a5c6 100644
--- a/board/ti/am62x/MAINTAINERS
+++ b/board/ti/am62x/MAINTAINERS
@@ -1,8 +1,10 @@
AM62x BOARD
-M: Dave Gerlach <d-gerlach@ti.com>
+M: Bryan Brattlof <bb@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/am62x/
F: include/configs/am62x_evm.h
F: configs/am62x_evm_r5_defconfig
F: configs/am62x_evm_a53_defconfig
+F: configs/am62x_lpsk_r5_defconfig
+F: configs/am62x_lpsk_a53_defconfig
diff --git a/cmd/cyclic.c b/cmd/cyclic.c
index 40e966d..339dd4a 100644
--- a/cmd/cyclic.c
+++ b/cmd/cyclic.c
@@ -15,14 +15,16 @@
#include <time.h>
#include <vsprintf.h>
#include <linux/delay.h>
+#include <linux/kernel.h>
struct cyclic_demo_info {
+ struct cyclic_info cyclic;
uint delay_us;
};
-static void cyclic_demo(void *ctx)
+static void cyclic_demo(struct cyclic_info *c)
{
- struct cyclic_demo_info *info = ctx;
+ struct cyclic_demo_info *info = container_of(c, struct cyclic_demo_info, cyclic);
/* Just a small dummy delay here */
udelay(info->delay_us);
@@ -32,7 +34,6 @@
char *const argv[])
{
struct cyclic_demo_info *info;
- struct cyclic_info *cyclic;
uint time_ms;
if (argc < 3)
@@ -48,10 +49,7 @@
info->delay_us = simple_strtoul(argv[2], NULL, 0);
/* Register demo cyclic function */
- cyclic = cyclic_register(cyclic_demo, time_ms * 1000, "cyclic_demo",
- info);
- if (!cyclic)
- printf("Registering of cyclic_demo failed\n");
+ cyclic_register(&info->cyclic, cyclic_demo, time_ms * 1000, "cyclic_demo");
printf("Registered function \"%s\" to be executed all %dms\n",
"cyclic_demo", time_ms);
diff --git a/cmd/elf.c b/cmd/elf.c
index a02361f..32b7462 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -19,21 +19,6 @@
#include <linux/linkage.h>
#endif
-/* Allow ports to override the default behavior */
-static unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]),
- int argc, char *const argv[])
-{
- unsigned long ret;
-
- /*
- * pass address parameter as argv[0] (aka command name),
- * and all remaining args
- */
- ret = entry(argc, argv);
-
- return ret;
-}
-
/* Interpreter command to boot an arbitrary ELF image from memory */
int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
@@ -43,8 +28,8 @@
#endif
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
- char *sload = NULL;
- int rcode = 0;
+ int rcode = CMD_RET_SUCCESS;
+ Bootelf_flags flags = {0};
/* Consume 'bootelf' */
argc--; argv++;
@@ -52,7 +37,10 @@
/* Check for [-p|-s] flag. */
if (argc >= 1 && (argv[0][0] == '-' && \
(argv[0][1] == 'p' || argv[0][1] == 's'))) {
- sload = argv[0];
+ if (argv[0][1] == 'p')
+ flags.phdr = 1;
+ log_debug("Using ELF header format %s\n",
+ flags.phdr ? "phdr" : "shdr");
/* Consume flag. */
argc--; argv++;
}
@@ -75,17 +63,9 @@
} else
addr = image_load_addr;
- if (!valid_elf_image(addr))
- return 1;
-
- if (sload && sload[1] == 'p')
- addr = load_elf_image_phdr(addr);
- else
- addr = load_elf_image_shdr(addr);
-
#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
if (fdt_addr) {
- printf("## Setting up FDT at 0x%08lx ...\n", fdt_addr);
+ log_debug("Setting up FDT at 0x%08lx ...\n", fdt_addr);
flush();
if (image_setup_libfdt(&img, (void *)fdt_addr, NULL))
@@ -93,21 +73,27 @@
}
#endif
- if (!env_get_autostart())
- return rcode;
-
- printf("## Starting application at 0x%08lx ...\n", addr);
- flush();
+ if (env_get_autostart()) {
+ flags.autostart = 1;
+ log_debug("Starting application at 0x%08lx ...\n", addr);
+ flush();
+ }
/*
* pass address parameter as argv[0] (aka command name),
- * and all remaining args
+ * and all remaining arguments
*/
- rc = do_bootelf_exec((void *)addr, argc, argv);
+ rc = bootelf(addr, flags, argc, argv);
if (rc != 0)
- rcode = 1;
+ rcode = CMD_RET_FAILURE;
- printf("## Application terminated, rc = 0x%lx\n", rc);
+ if (flags.autostart)
+ {
+ if (ENOEXEC == errno)
+ log_err("Invalid ELF image\n");
+ else
+ log_debug("## Application terminated, rc = 0x%lx\n", rc);
+ }
return rcode;
}
diff --git a/common/cyclic.c b/common/cyclic.c
index a49bfc8..ec38fad 100644
--- a/common/cyclic.c
+++ b/common/cyclic.c
@@ -26,34 +26,22 @@
return (struct hlist_head *)&gd->cyclic_list;
}
-struct cyclic_info *cyclic_register(cyclic_func_t func, uint64_t delay_us,
- const char *name, void *ctx)
+void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func,
+ uint64_t delay_us, const char *name)
{
- struct cyclic_info *cyclic;
-
- cyclic = calloc(1, sizeof(struct cyclic_info));
- if (!cyclic) {
- pr_debug("Memory allocation error\n");
- return NULL;
- }
+ memset(cyclic, 0, sizeof(*cyclic));
/* Store values in struct */
cyclic->func = func;
- cyclic->ctx = ctx;
- cyclic->name = strdup(name);
+ cyclic->name = name;
cyclic->delay_us = delay_us;
cyclic->start_time_us = timer_get_us();
hlist_add_head(&cyclic->list, cyclic_get_list());
-
- return cyclic;
}
-int cyclic_unregister(struct cyclic_info *cyclic)
+void cyclic_unregister(struct cyclic_info *cyclic)
{
hlist_del(&cyclic->list);
- free(cyclic);
-
- return 0;
}
void cyclic_run(void)
@@ -76,7 +64,7 @@
if (time_after_eq64(now, cyclic->next_call)) {
/* Call cyclic function and account it's cpu-time */
cyclic->next_call = now + cyclic->delay_us;
- cyclic->func(cyclic->ctx);
+ cyclic->func(cyclic);
cyclic->run_cnt++;
cpu_time = timer_get_us() - now;
cyclic->cpu_time_us += cpu_time;
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 0f7797b..af43b5f 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1301,7 +1301,7 @@
config SPL_NVME
bool "NVM Express device support"
- depends on BLK
+ depends on SPL_BLK
select FS_LOADER
select SPL_BLK_FS
help
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 6b29a4b..2a71b06 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -8,7 +8,7 @@
CONFIG_TARGET_AM62A7_A53_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
-CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-sk"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62a7-sk"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -39,6 +39,7 @@
CONFIG_CMD_MMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
index ec62670..455dd86 100644
--- a/configs/am62x_beagleplay_a53_defconfig
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -10,7 +10,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-beagleplay"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -58,6 +58,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index 16294a6..9bfe156 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -10,7 +10,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-sk"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -56,6 +56,7 @@
CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
diff --git a/configs/am62x_lpsk_a53_defconfig b/configs/am62x_lpsk_a53_defconfig
new file mode 100644
index 0000000..a86bfb5
--- /dev/null
+++ b/configs/am62x_lpsk_a53_defconfig
@@ -0,0 +1,8 @@
+#include <configs/am62x_evm_a53_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62-lp-sk"
+CONFIG_OF_UPSTREAM=y
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_AM625_A53_EVM=y
diff --git a/configs/am62x_lpsk_r5_defconfig b/configs/am62x_lpsk_r5_defconfig
new file mode 100644
index 0000000..9112bc2
--- /dev/null
+++ b/configs/am62x_lpsk_r5_defconfig
@@ -0,0 +1,7 @@
+#include <configs/am62x_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62-r5-lp-sk"
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_AM625_R5_EVM=y
diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig
index 8f20f65..eb5743d 100644
--- a/configs/cortina_presidio-asic-base_defconfig
+++ b/configs/cortina_presidio-asic-base_defconfig
@@ -38,3 +38,4 @@
CONFIG_CORTINA_UART=y
CONFIG_WDT=y
CONFIG_WDT_CORTINA=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/cortina_presidio-asic-pnand_defconfig b/configs/cortina_presidio-asic-pnand_defconfig
index 94dc3e1..c7367d4 100644
--- a/configs/cortina_presidio-asic-pnand_defconfig
+++ b/configs/cortina_presidio-asic-pnand_defconfig
@@ -43,3 +43,4 @@
CONFIG_CORTINA_UART=y
CONFIG_WDT=y
CONFIG_WDT_CORTINA=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs305-1g-4s-bit_defconfig b/configs/crs305-1g-4s-bit_defconfig
index a8f1757..c3d4594 100644
--- a/configs/crs305-1g-4s-bit_defconfig
+++ b/configs/crs305-1g-4s-bit_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig
index c66d291..1919e8c 100644
--- a/configs/crs305-1g-4s_defconfig
+++ b/configs/crs305-1g-4s_defconfig
@@ -48,3 +48,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs326-24g-2s-bit_defconfig b/configs/crs326-24g-2s-bit_defconfig
index b754dac..a584c26 100644
--- a/configs/crs326-24g-2s-bit_defconfig
+++ b/configs/crs326-24g-2s-bit_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs326-24g-2s_defconfig b/configs/crs326-24g-2s_defconfig
index 870127d..43f7455 100644
--- a/configs/crs326-24g-2s_defconfig
+++ b/configs/crs326-24g-2s_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs328-4c-20s-4s-bit_defconfig b/configs/crs328-4c-20s-4s-bit_defconfig
index 2373775..7bf6716 100644
--- a/configs/crs328-4c-20s-4s-bit_defconfig
+++ b/configs/crs328-4c-20s-4s-bit_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/crs328-4c-20s-4s_defconfig b/configs/crs328-4c-20s-4s_defconfig
index 9bac122..2f50bda 100644
--- a/configs/crs328-4c-20s-4s_defconfig
+++ b/configs/crs328-4c-20s-4s_defconfig
@@ -47,3 +47,4 @@
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 73a3c61..488a259 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -2,27 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
-CONFIG_DEFAULT_DEVICE_TREE="px30-evb"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_EVB_PX30=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
-CONFIG_DEBUG_UART_BASE=0xFF160000
+CONFIG_DEBUG_UART_BASE=0xff178000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
@@ -39,9 +27,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
@@ -63,7 +51,7 @@
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 0a14b39..3fe1dc3 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -2,27 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
CONFIG_DEFAULT_DEVICE_TREE="px30-firefly"
-CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_EVB_PX30=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
@@ -64,6 +52,7 @@
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+# CONFIG_OF_UPSTREAM is not set
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig
index 00a9211..d37749b 100644
--- a/configs/gxp_defconfig
+++ b/configs/gxp_defconfig
@@ -59,3 +59,4 @@
CONFIG_GXP_TIMER=y
# CONFIG_RANDOM_UUID is not set
CONFIG_SHA512=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index b69cf4c..36bf34d 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -5,7 +5,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
-CONFIG_ENV_SIZE=0x1f000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-jaguar"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 51a9d0f..c5c3a69 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -63,3 +63,4 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig
index 817e4b3..3989c79 100644
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -64,4 +64,5 @@
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig
index 35227eb..4d0cc85 100644
--- a/configs/mt7986_rfb_defconfig
+++ b/configs/mt7986_rfb_defconfig
@@ -64,4 +64,5 @@
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
index 7f11e6f..4c8a596 100644
--- a/configs/mx6memcal_defconfig
+++ b/configs/mx6memcal_defconfig
@@ -44,3 +44,4 @@
CONFIG_FSL_USDHC=y
CONFIG_MXC_UART=y
CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 3c1abb8..a9af415 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -2,29 +2,17 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4000
-CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3326-odroid-go2"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_ODROID_GO2=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -44,11 +32,11 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig
index 2be9e24..61513c9 100644
--- a/configs/pg_wcom_expu1_defconfig
+++ b/configs/pg_wcom_expu1_defconfig
@@ -104,5 +104,6 @@
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
CONFIG_POST=y
CONFIG_HUSH_OLD_PARSER=y
diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig
index 9245a56..ec0f975 100644
--- a/configs/pg_wcom_expu1_update_defconfig
+++ b/configs/pg_wcom_expu1_update_defconfig
@@ -102,5 +102,6 @@
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
CONFIG_POST=y
CONFIG_HUSH_OLD_PARSER=y
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index 033dd82..82923d3 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig
@@ -104,5 +104,6 @@
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
CONFIG_POST=y
CONFIG_HUSH_OLD_PARSER=y
diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig
index 4d34ef6..41931e2 100644
--- a/configs/pg_wcom_seli8_update_defconfig
+++ b/configs/pg_wcom_seli8_update_defconfig
@@ -102,5 +102,6 @@
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
CONFIG_POST=y
CONFIG_HUSH_OLD_PARSER=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 34a0b57..5319239 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -6,7 +6,6 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_SIZE=0x3000
-CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-puma-haikou"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
@@ -29,7 +28,12 @@
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
-CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_VBE is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -41,6 +45,8 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_SQUASHFS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_OVERWRITE=y
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig
index 87a39e1..fdcbd8a 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -2,27 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
-CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-ctouch2-of10"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_PX30_CORE=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index 7162c11..343fd0b 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -2,27 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
-CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-ctouch2"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_PX30_CORE=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 1182f60..aa0bff4 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -2,27 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
-CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
-CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-engicam-px30-core-edimm2.2"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
CONFIG_TARGET_PX30_CORE=y
CONFIG_DEBUG_UART_CHANNEL=1
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -40,9 +28,9 @@
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 0c4b1ee..9983dbd 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -81,3 +81,4 @@
CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 94179dc..2320479 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -4,7 +4,7 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-ringneck-haikou"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_PX30=y
# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
@@ -14,18 +14,18 @@
CONFIG_DEBUG_UART_BASE=0xFF030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
-CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTD_FULL=y
CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_PAD_TO=0x38000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
@@ -34,12 +34,15 @@
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
-# CONFIG_CMD_BOOTD is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_VBE is not set
+# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
@@ -47,9 +50,11 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_SLEEP is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_SQUASHFS=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
diff --git a/configs/sige7-rk3588_defconfig b/configs/sige7-rk3588_defconfig
new file mode 100644
index 0000000..d15fc09
--- /dev/null
+++ b/configs/sige7-rk3588_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-armsom-sige7"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_SIGE7_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-armsom-sige7.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHYLIB=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 54a0379..256190d 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -39,3 +39,4 @@
CONFIG_MTD=y
CONFIG_SAMSUNG_ONENAND=y
CONFIG_SMC911X=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index f0a364a..0fff908 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -68,3 +68,4 @@
CONFIG_CADENCE_QSPI=y
# CONFIG_SPL_WDT is not set
CONFIG_SYS_TIMER_COUNTS_DOWN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig
index 9fbd7eb..87038cc 100644
--- a/configs/stm32mp25_defconfig
+++ b/configs/stm32mp25_defconfig
@@ -48,6 +48,7 @@
CONFIG_WDT_STM32MP=y
CONFIG_WDT_ARM_SMC=y
CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_LMB_MEMORY_REGIONS=2
CONFIG_LMB_RESERVED_REGIONS=32
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index 247e32d..b754cc0 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -36,3 +36,4 @@
# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SKIP_INIT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig
new file mode 100644
index 0000000..8fcdd06
--- /dev/null
+++ b/configs/tiger-rk3588_defconfig
@@ -0,0 +1,113 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-tiger-haikou"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_TIGER_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xfeb50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-tiger-haikou.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CYCLIC=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SF is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+# CONFIG_CMD_EFICONFIG is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_SQUASHFS=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+# CONFIG_SPI_FLASH is not set
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 9d3924c..b97bf5e 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -62,4 +62,5 @@
# CONFIG_MMC is not set
CONFIG_ARM_DCC=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index 7a11035..8f16259 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -72,4 +72,5 @@
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=200000000
CONFIG_CADENCE_OSPI_VERSAL=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index 58945a1..8fbde1c 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -76,4 +76,5 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index 7dac1ec..d6ebd08 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -71,4 +71,5 @@
CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
index d78c9f8..872a4a5 100644
--- a/configs/xilinx_versal_net_mini_ospi_defconfig
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -70,4 +70,5 @@
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=200000000
CONFIG_CADENCE_OSPI_VERSAL=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index b0567f8..00319e0 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -74,4 +74,5 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ZYNQMP_GQSPI=y
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index 7fdd2ee..4b45074 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -60,4 +60,5 @@
CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index d2e920f..b471953 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -60,4 +60,5 @@
CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index 31f6473..7ede176 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -59,4 +59,5 @@
CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 957ae07..0d79ece 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -92,4 +92,5 @@
CONFIG_ZYNQMP_GQSPI=y
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 48473d7..750ea0d 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -79,4 +79,5 @@
CONFIG_ARM_DCC=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 9f2b738..3155fe0 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -83,4 +83,5 @@
CONFIG_ARM_DCC=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 5b861bd..f2e1aa6 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -93,4 +93,5 @@
CONFIG_ZYNQ_QSPI=y
CONFIG_SYS_TIMER_COUNTS_DOWN=y
# CONFIG_GZIP is not set
+# CONFIG_EFI_LOADER is not set
# CONFIG_LMB is not set
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index cfbf641..eaf7167 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -119,6 +119,7 @@
- Radxa ROCK 3 Model A (rock-3a-rk3568)
* rk3588
+ - ArmSoM Sige7 (sige7-rk3588)
- Rockchip EVB (evb-rk3588)
- Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
@@ -130,6 +131,7 @@
- Radxa ROCK 5B (rock5b-rk3588)
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
- Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
+ - Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588)
- Turing Machines RK1 (turing-rk1-rk3588)
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
diff --git a/doc/board/theobroma-systems/index.rst b/doc/board/theobroma-systems/index.rst
index b4da261..73e07f7 100644
--- a/doc/board/theobroma-systems/index.rst
+++ b/doc/board/theobroma-systems/index.rst
@@ -9,3 +9,4 @@
jaguar_rk3588
puma_rk3399
ringneck_px30
+ tiger_rk3588
diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst
new file mode 100644
index 0000000..a73eec7
--- /dev/null
+++ b/doc/board/theobroma-systems/tiger_rk3588.rst
@@ -0,0 +1,102 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+SOM-RK3588-Q7 Tiger
+===================
+
+The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
+connector) system-on-module from Theobroma Systems, featuring the
+Rockchip RK3588.
+
+It provides the following feature set:
+ * up to 16GB LPDDR4x
+ * on-module eMMC
+ * SD card (on a baseboard) via edge connector
+ * Gigabit Ethernet with on-module GbE PHY
+ * HDMI/eDP
+ * MIPI-DSI
+ * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
+ * HDMI input over FPC connector
+ * CAN
+ * USB
+ - 1x USB 3.0 dual-role (direct connection)
+ - 2x USB 3.0 host + 1x USB 2.0 host
+ * PCIe
+ - 1x PCIe 2.1 Gen3, 4 lanes
+ - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
+ * on-module ATtiny816 companion controller, implementing:
+ - low-power RTC functionality (ISL1208 emulation)
+ - fan controller (AMC6821 emulation)
+ * on-module Secure Element with Global Platform 2.2.1 compliant
+ JavaCard environment
+
+Here is the step-by-step to boot to U-Boot on SOM-RK3588-Q7 Tiger from Theobroma
+Systems.
+
+Get the TF-A and DDR init (TPL) binaries
+----------------------------------------
+
+.. prompt:: bash
+
+ git clone https://github.com/rockchip-linux/rkbin
+ cd rkbin
+ export RKBIN=$(pwd)
+ export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf
+ export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin
+ sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
+ sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt
+ ./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL"
+ ./tools/boot_merger RKBOOT/RK3588MINIALL.ini
+ export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
+
+This will setup all required external dependencies for compiling U-Boot. This will
+be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot
+gains support for open-source DRAM initialization in TPL.
+
+Build U-Boot
+------------
+
+.. prompt:: bash
+
+ cd ../u-boot
+ make CROSS_COMPILE=aarch64-linux-gnu- tiger-rk3588_defconfig all
+
+This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
+(eMMC or SD card).
+
+Flash the image
+---------------
+
+Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC.
+
+SD-Card
+~~~~~~~
+
+.. prompt:: bash
+
+ dd if=u-boot-rockchip.bin of=/dev/sdX seek=64
+
+.. note::
+
+ Replace ``/dev/sdX`` to match your SD card kernel device.
+
+eMMC
+~~~~
+
+``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface
+with help of the Rockchip loader binary.
+
+To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a
+micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into
+``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch
+back to ``Normal Boot`` mode. A new USB device should have appeared on your PC
+(check with ``lsusb -d 2207:350b``).
+
+To flash U-Boot on the eMMC with ``rkdeveloptool``:
+
+.. prompt:: bash
+
+ git clone https://github.com/rockchip-linux/rkdeveloptool
+ cd rkdeveloptool
+ autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make
+ ./rkdeveloptool db "$RKDB"
+ ./rkdeveloptool wl 64 ../u-boot-rockchip.bin
diff --git a/doc/develop/cyclic.rst b/doc/develop/cyclic.rst
index 6783149..893c269 100644
--- a/doc/develop/cyclic.rst
+++ b/doc/develop/cyclic.rst
@@ -19,20 +19,26 @@
To register a cyclic function, use something like this::
- static void cyclic_demo(void *ctx)
+ struct donkey {
+ struct cyclic_info cyclic;
+ void (*say)(const char *s);
+ };
+
+ static void cyclic_demo(struct cyclic_info *c)
{
- /* Just a small dummy delay here */
- udelay(10);
+ struct donkey *donkey = container_of(c, struct donkey, cyclic);
+
+ donkey->say("Are we there yet?");
}
-
- int board_init(void)
+
+ int donkey_init(void)
{
- struct cyclic_info *cyclic;
-
+ struct donkey *donkey;
+
+ /* Initialize donkey ... */
+
/* Register demo cyclic function */
- cyclic = cyclic_register(cyclic_demo, 10 * 1000, "cyclic_demo", NULL);
- if (!cyclic)
- printf("Registering of cyclic_demo failed\n");
+ cyclic_register(&donkey->cyclic, cyclic_demo, 10 * 1000, "cyclic_demo");
return 0;
}
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 9bc5283..6cca561 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -61,7 +61,6 @@
config DWC_AHSATA
bool "Enable DWC AHSATA driver support"
select LIBATA
- depends on BLK
help
Enable this driver to support the DWC AHSATA SATA controller found
in i.MX5 and i.MX6 SoCs.
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 6ad1888..48529a6 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -1,8 +1,8 @@
config BLK
bool # "Support block devices"
depends on DM
- default y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA
- default y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK
+ def_bool y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA
+ def_bool y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK
help
Enable support for block devices, such as SCSI, MMC and USB
flash sticks. These provide a block-level interface which permits
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index d094479..8b13a08 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -41,7 +41,6 @@
config DM_MMC
bool "Enable MMC controllers using Driver Model"
depends on DM
- select BLK
help
This enables the MultiMediaCard (MMC) uclass which supports MMC and
Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
@@ -249,7 +248,6 @@
bool "Cortina specific extensions for Synopsys DW Memory Card Interface"
depends on DM_MMC
depends on MMC_DW
- depends on BLK
help
This selects support for Cortina SoC specific extensions to the
Synopsys DesignWare Memory Card Interface driver. Select this option
@@ -313,7 +311,7 @@
config MMC_MESON_GX
bool "Meson GX EMMC controller support"
- depends on DM_MMC && BLK && ARCH_MESON
+ depends on DM_MMC && ARCH_MESON
help
Support for EMMC host controller on Meson GX ARM SoCs platform (S905)
@@ -367,7 +365,7 @@
config MVEBU_MMC
bool "Kirkwood MMC controller support"
- depends on DM_MMC && BLK && ARCH_KIRKWOOD
+ depends on DM_MMC && ARCH_KIRKWOOD
help
Support for MMC host controller on Kirkwood SoCs.
If you are on a Kirkwood architecture, say Y here.
@@ -420,7 +418,7 @@
config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on OF_CONTROL
help
This selects support for the Matsushita SD/MMC Host Controller on
@@ -429,7 +427,7 @@
config RENESAS_SDHI
bool "Renesas R-Car SD/MMC Host Controller support"
depends on ARCH_RENESAS
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on OF_CONTROL
select BOUNCE_BUFFER
help
@@ -439,7 +437,7 @@
config MMC_BCM2835
bool "BCM2835 family custom SD/MMC Host Controller support"
depends on ARCH_BCM283X
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on OF_CONTROL
default y
help
@@ -459,7 +457,7 @@
config MMC_SANDBOX
bool "Sandbox MMC support"
depends on SANDBOX
- depends on BLK && DM_MMC && OF_CONTROL
+ depends on DM_MMC && OF_CONTROL
help
This select a dummy sandbox MMC driver. At present this does nothing
other than allow sandbox to be build with MMC support. This
@@ -561,7 +559,7 @@
config MMC_SDHCI_ATMEL
bool "Atmel SDHCI controller support"
depends on ARCH_AT91
- depends on DM_MMC && BLK && ARCH_AT91
+ depends on DM_MMC && ARCH_AT91
depends on MMC_SDHCI
help
This enables support for the Atmel SDHCI controller, which supports
@@ -596,7 +594,7 @@
config MMC_SDHCI_CADENCE
bool "SDHCI support for the Cadence SD/SDIO/eMMC controller"
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on MMC_SDHCI
depends on OF_CONTROL
help
@@ -608,7 +606,7 @@
config MMC_SDHCI_CV1800B
bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller"
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on MMC_SDHCI
depends on OF_CONTROL
help
@@ -643,7 +641,7 @@
config MMC_SDHCI_F_SDH30
bool "SDHCI support for Fujitsu Semiconductor/Socionext F_SDH30"
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on MMC_SDHCI
help
This selects the Secure Digital Host Controller Interface (SDHCI)
@@ -663,7 +661,7 @@
config MMC_SDHCI_MSM
bool "Qualcomm SDHCI controller"
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on MMC_SDHCI
help
Enables support for SDHCI 2.0 controller present on some Qualcomm
@@ -829,7 +827,7 @@
config GENERIC_ATMEL_MCI
bool "Atmel Multimedia Card Interface support"
- depends on DM_MMC && BLK && ARCH_AT91
+ depends on DM_MMC && ARCH_AT91
help
This enables support for Atmel High Speed Multimedia Card Interface
(HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3,
@@ -838,7 +836,7 @@
config STM32_SDMMC2
bool "STMicroelectronics STM32H7 SD/MMC Host Controller support"
- depends on DM_MMC && BLK && OF_CONTROL
+ depends on DM_MMC && OF_CONTROL
help
This selects support for the SD/MMC controller on STM32H7 SoCs.
If you have a board based on such a SoC and with a SD/MMC slot,
@@ -858,7 +856,7 @@
config MMC_MTK
bool "MediaTek SD/MMC Card Interface support"
depends on ARCH_MEDIATEK || ARCH_MTMIPS
- depends on BLK && DM_MMC
+ depends on DM_MMC
depends on OF_CONTROL
help
This selects the MediaTek(R) Secure digital and Multimedia card Interface.
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 12ff26a..617bb51 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -6,6 +6,7 @@
#include <dm.h>
#include <dm/lists.h>
+#include <bitfield.h>
#include <errno.h>
#include <log.h>
#include <linux/bitfield.h>
@@ -277,10 +278,9 @@
return ret;
priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
- show_variant = priv->variant;
+ show_variant = bitfield_extract_by_mask(priv->variant, RK8XX_ID_MSK);
switch (priv->variant) {
case RK808_ID:
- show_variant = 0x808; /* RK808 hardware ID is 0 */
break;
case RK805_ID:
case RK816_ID:
@@ -311,7 +311,7 @@
init_data_num = ARRAY_SIZE(rk806_init_reg);
break;
default:
- printf("Unknown PMIC: RK%x!!\n", priv->variant);
+ printf("Unknown PMIC: RK%x!!\n", show_variant);
return -EINVAL;
}
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 4963385..42b6971 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -291,9 +291,9 @@
serial_out(c, &com_port->thr);
/*
- * Call watchdog_reset() upon newline. This is done here in putc
+ * Call schedule() upon newline. This is done here in putc
* since the environment code uses a single puts() to print the complete
- * environment upon "printenv". So we can't put this watchdog call
+ * environment upon "printenv". So we can't put this schedule call
* in puts().
*/
if (c == '\n')
@@ -390,9 +390,9 @@
serial_out(ch, &com_port->thr);
/*
- * Call watchdog_reset() upon newline. This is done here in putc
+ * Call schedule() upon newline. This is done here in putc
* since the environment code uses a single puts() to print the complete
- * environment upon "printenv". So we can't put this watchdog call
+ * environment upon "printenv". So we can't put this schedule call
* in puts().
*/
if (ch == '\n')
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index c88312e..10be334 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -17,17 +17,20 @@
#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <linux/kernel.h>
DECLARE_GLOBAL_DATA_PTR;
#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
struct wdt_priv {
+ /* The udevice owning this wdt_priv. */
+ struct udevice *dev;
/* Timeout, in seconds, to configure this device to. */
u32 timeout;
/*
* Time, in milliseconds, between calling the device's ->reset()
- * method from watchdog_reset().
+ * method from schedule().
*/
ulong reset_period;
/*
@@ -40,18 +43,17 @@
/* autostart */
bool autostart;
- struct cyclic_info *cyclic;
+ struct cyclic_info cyclic;
};
-static void wdt_cyclic(void *ctx)
+static void wdt_cyclic(struct cyclic_info *c)
{
- struct udevice *dev = ctx;
- struct wdt_priv *priv;
+ struct wdt_priv *priv = container_of(c, struct wdt_priv, cyclic);
+ struct udevice *dev = priv->dev;
if (!device_active(dev))
return;
- priv = dev_get_uclass_priv(dev);
if (!priv->running)
return;
@@ -121,24 +123,20 @@
struct wdt_priv *priv = dev_get_uclass_priv(dev);
char str[16];
- priv->running = true;
-
memset(str, 0, 16);
if (IS_ENABLED(CONFIG_WATCHDOG)) {
+ if (priv->running)
+ cyclic_unregister(&priv->cyclic);
+
/* Register the watchdog driver as a cyclic function */
- priv->cyclic = cyclic_register(wdt_cyclic,
- priv->reset_period * 1000,
- dev->name, dev);
- if (!priv->cyclic) {
- printf("cyclic_register for %s failed\n",
- dev->name);
- return -ENODEV;
- } else {
- snprintf(str, 16, "every %ldms",
- priv->reset_period);
- }
+ cyclic_register(&priv->cyclic, wdt_cyclic,
+ priv->reset_period * 1000,
+ dev->name);
+
+ snprintf(str, 16, "every %ldms", priv->reset_period);
}
+ priv->running = true;
printf("WDT: Started %s with%s servicing %s (%ds timeout)\n",
dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out",
str, (u32)lldiv(timeout_ms, 1000));
@@ -159,6 +157,9 @@
if (ret == 0) {
struct wdt_priv *priv = dev_get_uclass_priv(dev);
+ if (IS_ENABLED(CONFIG_WATCHDOG) && priv->running)
+ cyclic_unregister(&priv->cyclic);
+
priv->running = false;
}
@@ -220,21 +221,6 @@
return ret;
}
-
-#if defined(CONFIG_WATCHDOG)
-/*
- * Called by macro WATCHDOG_RESET. This function be called *very* early,
- * so we need to make sure, that the watchdog driver is ready before using
- * it in this function.
- */
-void watchdog_reset(void)
-{
- /*
- * Empty function for now. The actual WDT handling is now done in
- * the cyclic function instead.
- */
-}
-#endif
static int wdt_pre_probe(struct udevice *dev)
{
@@ -257,12 +243,13 @@
autostart = true;
}
priv = dev_get_uclass_priv(dev);
+ priv->dev = dev;
priv->timeout = timeout;
priv->reset_period = reset_period;
priv->autostart = autostart;
/*
* Pretend this device was last reset "long" ago so the first
- * watchdog_reset will actually call its ->reset method.
+ * schedule() will actually call its ->reset method.
*/
priv->next_reset = get_timer(0);
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
new file mode 100644
index 0000000..98c622b
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
@@ -0,0 +1,721 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "ArmSoM Sige7";
+ compatible = "armsom,sige7", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_8ch_p0>;
+ label = "rk3588-es8316";
+ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_g>;
+
+ led_green: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led_red: led-1 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 95 145 195 255>;
+ fan-supply = <&vcc5v0_sys>;
+ pwms = <&pwm1 0 50000 0>;
+ #cooling-cells = <2>;
+ };
+
+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ es8316: audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
+};
+
+/* phy1 - right ethernet port */
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* phy2 - WiFi */
+&pcie2x1l1 {
+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* phy0 - left ethernet port */
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_rgb_g: led-rgb-g {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ led_rgb_r: led-rgb-r {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&avcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ system-power-controller;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usbdp_phy1 {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
index 94ecb9b..170501a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
@@ -357,7 +357,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
index c0d4a15..d9bf675 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
@@ -182,7 +182,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
index 39d6500..7d7303f 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
@@ -452,7 +452,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts
index d672198..e4b7a0a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts
@@ -113,6 +113,16 @@
vin-supply = <&dc_12v>;
};
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ };
+
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
@@ -137,6 +147,10 @@
status = "okay";
};
+&extcon_usb3 {
+ status = "okay";
+};
+
&gmac0 {
status = "okay";
};
@@ -199,6 +213,13 @@
<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
+
+ usb2 {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins =
+ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&sdmmc {
@@ -214,6 +235,23 @@
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
@@ -231,25 +269,38 @@
};
&uart2 {
- pinctrl-0 = <&uart2m2_xfer>;
status = "okay";
};
&uart5 {
rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
+};
+
+&usbdp_phy0 {
status = "okay";
};
-/* host0 on Q7_USB_P2, lower usb3 port */
+&usbdp_phy1 {
+ status = "okay";
+};
+
+/* host0 on Q7_USB_P2, upper usb3 port */
&usb_host0_ehci {
status = "okay";
};
-/* host0 on Q7_USB_P2, lower usb3 port */
+/* host0 on Q7_USB_P2, upper usb3 port */
&usb_host0_ohci {
status = "okay";
};
+/* host0_xhci on Q7_USB_P1, usb3-otg port */
+&usb_host0_xhci {
+ dr_mode = "otg";
+ extcon = <&extcon_usb3>;
+ status = "okay";
+};
+
/* host1 on Q7_USB_P3, usb2 port */
&usb_host1_ehci {
status = "okay";
@@ -260,7 +311,13 @@
status = "okay";
};
+/* host1_xhci on Q7_USB_P0, lower usb3 port */
+&usb_host1_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
-/* host2 on Q7_USB_P2, lower usb3 port */
+/* host2 on Q7_USB_P2, upper usb3 port */
&usb_host2_xhci {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
index 1eb2543..aebe1fe 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
@@ -23,6 +23,14 @@
reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
};
+ extcon_usb3: extcon-usb3 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_id>;
+ status = "disabled";
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -46,7 +54,7 @@
pcie_refclk_gen: pcie-refclk-gen-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <1000000000>;
+ clock-frequency = <100000000>;
};
pcie_refclk: pcie-refclk-clock {
@@ -139,6 +147,11 @@
snps,reset-delays-us = <0 10000 100000>;
};
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-0 = <&i2c1m0_xfer>;
};
@@ -322,6 +335,13 @@
rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb3 {
+ usb3_id: usb3-id {
+ rockchip,pins =
+ <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&saradc {
@@ -396,7 +416,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
@@ -683,6 +703,11 @@
status = "okay";
};
+/* Routed to UART0 on the Q7 connector */
+&uart2 {
+ pinctrl-0 = <&uart2m2_xfer>;
+};
+
/* Mule-ATtiny UPDI */
&uart4 {
pinctrl-0 = <&uart4m2_xfer>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
index dc08da5..6b9206c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
@@ -318,7 +318,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 5519c14..5984016 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -7,6 +7,26 @@
#include "rk3588-pinctrl.dtsi"
/ {
+ usb_host1_xhci: usb@fc400000 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc400000 0x0 0x400000>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dr_mode = "otg";
+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG1>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+
pcie30_phy_grf: syscon@fd5b8000 {
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
reg = <0x0 0xfd5b8000 0x0 0x10000>;
@@ -17,6 +37,36 @@
reg = <0x0 0xfd5c0000 0x0 0x100>;
};
+ usbdpphy1_grf: syscon@fd5cc000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
+ };
+
+ usb2phy1_grf: syscon@fd5d4000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy1: usb2phy@4000 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x4000 0x10>;
+ #clock-cells = <0>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy1";
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -310,6 +360,28 @@
};
};
+ usbdp_phy1: phy@fed90000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed90000 0x0 0x10000>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY1_IMMORTAL>,
+ <&cru PCLK_USBDPPHY1>,
+ <&u2phy1>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
+ <&cru SRST_USBDP_COMBO_PHY1_CMN>,
+ <&cru SRST_USBDP_COMBO_PHY1_LANE>,
+ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
+ <&cru SRST_P_USBDPPHY1>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ status = "disabled";
+ };
+
combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
index e037bf9..7f4d7bb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
@@ -479,7 +479,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
index ce8119c..a5b76e2 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
@@ -528,7 +528,7 @@
vcca-supply = <&vcc5v0_sys>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
index 25de436..73700d7 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
@@ -336,7 +336,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
index 00afb90..5c99636 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
@@ -414,7 +414,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 87b83c8..6ac5ac8 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -347,6 +347,11 @@
};
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
firmware {
optee: optee {
compatible = "linaro,optee-tz";
@@ -394,11 +399,6 @@
#clock-cells = <0>;
};
- display_subsystem: display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- };
-
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -436,6 +436,84 @@
};
};
+ gpu: gpu@fb000000 {
+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
+ reg = <0x0 0xfb000000 0x0 0x200000>;
+ #cooling-cells = <2>;
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <200000000>;
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
+ <&cru CLK_GPU_STACKS>;
+ clock-names = "core", "coregroup", "stacks";
+ dynamic-power-coefficient = <2982>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3588_PD_GPU>;
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <700000 700000 850000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <750000 750000 850000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <800000 800000 850000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <850000 850000 850000>;
+ };
+ };
+ };
+
+ usb_host0_xhci: usb@fc000000 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
+ <&cru ACLK_USB3OTG0>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dr_mode = "otg";
+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3588_PD_USB>;
+ resets = <&cru SRST_A_USB3OTG0>;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@fc800000 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";
reg = <0x0 0xfc800000 0x0 0x40000>;
@@ -501,6 +579,30 @@
status = "disabled";
};
+ mmu600_pcie: iommu@fc900000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfc900000 0x0 0x200000>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ mmu600_php: iommu@fcb00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0xfcb00000 0x0 0x200000>;
+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
pmu1grf: syscon@fd58a000 {
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfd58a000 0x0 0x10000>;
@@ -516,12 +618,23 @@
reg = <0x0 0xfd5a4000 0x0 0x2000>;
};
+ vo0_grf: syscon@fd5a6000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
+ clocks = <&cru PCLK_VO0GRF>;
+ };
+
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};
+ usb_grf: syscon@fd5ac000 {
+ compatible = "rockchip,rk3588-usb-grf", "syscon";
+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
+ };
+
php_grf: syscon@fd5b0000 {
compatible = "rockchip,rk3588-php-grf", "syscon";
reg = <0x0 0xfd5b0000 0x0 0x1000>;
@@ -537,22 +650,52 @@
reg = <0x0 0xfd5c4000 0x0 0x100>;
};
+ usbdpphy0_grf: syscon@fd5c8000 {
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
+ };
+
+ usb2phy0_grf: syscon@fd5d0000 {
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfd5d0000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy0: usb2phy@0 {
+ compatible = "rockchip,rk3588-usb2phy";
+ reg = <0x0 0x10>;
+ #clock-cells = <0>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy0";
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d8000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
- u2phy2: usb2-phy@8000 {
+ u2phy2: usb2phy@8000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x8000 0x10>;
- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy2";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy2_host: host-port {
@@ -568,16 +711,16 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy3: usb2-phy@c000 {
+ u2phy3: usb2phy@c000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0xc000 0x10>;
- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy3";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy3_host: host-port {
@@ -646,74 +789,6 @@
status = "disabled";
};
- vop: vop@fdd90000 {
- compatible = "rockchip,rk3588-vop";
- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
- reg-names = "vop", "gamma-lut";
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_VOP>,
- <&cru HCLK_VOP>,
- <&cru DCLK_VOP0>,
- <&cru DCLK_VOP1>,
- <&cru DCLK_VOP2>,
- <&cru DCLK_VOP3>,
- <&cru PCLK_VOP_ROOT>;
- clock-names = "aclk",
- "hclk",
- "dclk_vp0",
- "dclk_vp1",
- "dclk_vp2",
- "dclk_vp3",
- "pclk_vop";
- iommus = <&vop_mmu>;
- power-domains = <&power RK3588_PD_VOP>;
- rockchip,grf = <&sys_grf>;
- rockchip,vop-grf = <&vop_grf>;
- rockchip,vo1-grf = <&vo1_grf>;
- rockchip,pmu = <&pmu>;
- status = "disabled";
-
- vop_out: ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vp0: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- vp1: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-
- vp2: port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- vp3: port@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
- };
- };
-
- vop_mmu: iommu@fdd97e00 {
- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- power-domains = <&power RK3588_PD_VOP>;
- status = "disabled";
- };
-
uart0: serial@fd890000 {
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
reg = <0x0 0xfd890000 0x0 0x100>;
@@ -1084,6 +1159,87 @@
};
};
+ av1d: video-codec@fdc70000 {
+ compatible = "rockchip,rk3588-av1-vpu";
+ reg = <0x0 0xfdc70000 0x0 0x800>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdpu";
+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ assigned-clock-rates = <400000000>, <400000000>;
+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3588_PD_AV1>;
+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
+ };
+
+ vop: vop@fdd90000 {
+ compatible = "rockchip,rk3588-vop";
+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
+ reg-names = "vop", "gamma-lut";
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&cru PCLK_VOP_ROOT>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+ "pclk_vop";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3588_PD_VOP>;
+ rockchip,grf = <&sys_grf>;
+ rockchip,vop-grf = <&vop_grf>;
+ rockchip,vo1-grf = <&vo1_grf>;
+ rockchip,pmu = <&pmu>;
+ status = "disabled";
+
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vp0: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ vp1: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ vp2: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ vp3: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+ };
+
+ vop_mmu: iommu@fdd97e00 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_VOP>;
+ status = "disabled";
+ };
+
i2s4_8ch: i2s@fddc0000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc0000 0x0 0x1000>;
@@ -1375,6 +1531,16 @@
reg = <0x0 0xfdf82200 0x0 0x20>;
};
+ dfi: dfi@fe060000 {
+ reg = <0x00 0xfe060000 0x00 0x10000>;
+ compatible = "rockchip,rk3588-dfi";
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
+ rockchip,pmu = <&pmu1grf>;
+ };
+
pcie2x1l1: pcie@fe180000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
bus-range = <0x30 0x3f>;
@@ -1477,16 +1643,6 @@
};
};
- dfi: dfi@fe060000 {
- reg = <0x00 0xfe060000 0x00 0x10000>;
- compatible = "rockchip,rk3588-dfi";
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
- rockchip,pmu = <&pmu1grf>;
- };
-
gmac1: ethernet@fe1c0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1c0000 0x0 0x10000>;
@@ -2380,6 +2536,28 @@
status = "disabled";
};
+ usbdp_phy0: phy@fed80000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed80000 0x0 0x10000>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
+ <&cru PCLK_USBDPPHY0>,
+ <&u2phy0>;
+ clock-names = "refclk", "immortal", "pclk", "utmi";
+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
+ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
+ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
+ <&cru SRST_P_USBDPPHY0>;
+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
+ status = "disabled";
+ };
+
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
@@ -2487,19 +2665,6 @@
#interrupt-cells = <2>;
};
};
-
- av1d: video-codec@fdc70000 {
- compatible = "rockchip,rk3588-av1-vpu";
- reg = <0x0 0xfdc70000 0x0 0x800>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "vdpu";
- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
- assigned-clock-rates = <400000000>, <400000000>;
- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
- clock-names = "aclk", "hclk";
- power-domains = <&power RK3588_PD_AV1>;
- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
- };
};
#include "rk3588s-pinctrl.dtsi"
diff --git a/fs/erofs/data.c b/fs/erofs/data.c
index f4b21d7..95b609d 100644
--- a/fs/erofs/data.c
+++ b/fs/erofs/data.c
@@ -313,7 +313,7 @@
}
if (!(map.m_flags & EROFS_MAP_MAPPED)) {
- memset(buffer + end - offset, 0, length);
+ memset(buffer + end - offset, 0, length - skip);
end = map.m_la;
continue;
}
diff --git a/include/configs/sige7-rk3588.h b/include/configs/sige7-rk3588.h
new file mode 100644
index 0000000..fd08da5
--- /dev/null
+++ b/include/configs/sige7-rk3588.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024 ArmSoM Technology Co., Ltd.
+ */
+
+#ifndef __SIGE7_RK3588_H
+#define __SIGE7_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __SIGE7_RK3588_H */
diff --git a/include/configs/tiger_rk3588.h b/include/configs/tiger_rk3588.h
new file mode 100644
index 0000000..7a32adf
--- /dev/null
+++ b/include/configs/tiger_rk3588.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#ifndef __TIGER_RK3588_H
+#define __TIGER_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __TIGER_RK3588_H */
diff --git a/include/cyclic.h b/include/cyclic.h
index 44ad3cb..2c3d383 100644
--- a/include/cyclic.h
+++ b/include/cyclic.h
@@ -18,7 +18,6 @@
* struct cyclic_info - Information about cyclic execution function
*
* @func: Function to call periodically
- * @ctx: Context pointer to get passed to this function
* @name: Name of the cyclic function, e.g. shown in the commands
* @delay_ns: Delay is ns after which this function shall get executed
* @start_time_us: Start time in us, when this function started its execution
@@ -27,11 +26,13 @@
* @next_call: Next time in us, when the function shall be executed again
* @list: List node
* @already_warned: Flag that we've warned about exceeding CPU time usage
+ *
+ * When !CONFIG_CYCLIC, this struct is empty.
*/
struct cyclic_info {
- void (*func)(void *ctx);
- void *ctx;
- char *name;
+#if defined(CONFIG_CYCLIC)
+ void (*func)(struct cyclic_info *c);
+ const char *name;
uint64_t delay_us;
uint64_t start_time_us;
uint64_t cpu_time_us;
@@ -39,31 +40,34 @@
uint64_t next_call;
struct hlist_node list;
bool already_warned;
+#endif
};
/** Function type for cyclic functions */
-typedef void (*cyclic_func_t)(void *ctx);
+typedef void (*cyclic_func_t)(struct cyclic_info *c);
#if defined(CONFIG_CYCLIC)
/**
* cyclic_register - Register a new cyclic function
*
+ * @cyclic: Cyclic info structure
* @func: Function to call periodically
* @delay_us: Delay is us after which this function shall get executed
* @name: Cyclic function name/id
- * @ctx: Context to pass to the function
- * @return: pointer to cyclic_struct if OK, NULL on error
+ *
+ * The function @func will be called with @cyclic as its
+ * argument. @cyclic will usually be embedded in some device-specific
+ * structure, which the callback can retrieve using container_of().
*/
-struct cyclic_info *cyclic_register(cyclic_func_t func, uint64_t delay_us,
- const char *name, void *ctx);
+void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func,
+ uint64_t delay_us, const char *name);
/**
* cyclic_unregister - Unregister a cyclic function
*
* @cyclic: Pointer to cyclic_struct of the function that shall be removed
- * @return: 0 if OK, -ve on error
*/
-int cyclic_unregister(struct cyclic_info *cyclic);
+void cyclic_unregister(struct cyclic_info *cyclic);
/**
* cyclic_unregister_all() - Clean up cyclic functions
@@ -97,17 +101,14 @@
*/
void schedule(void);
#else
-static inline struct cyclic_info *cyclic_register(cyclic_func_t func,
- uint64_t delay_us,
- const char *name,
- void *ctx)
+
+static inline void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func,
+ uint64_t delay_us, const char *name)
{
- return NULL;
}
-static inline int cyclic_unregister(struct cyclic_info *cyclic)
+static inline void cyclic_unregister(struct cyclic_info *cyclic)
{
- return 0;
}
static inline void cyclic_run(void)
diff --git a/include/elf.h b/include/elf.h
index a4ba74d..b88e6cf 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -12,6 +12,12 @@
#ifndef __ASSEMBLY__
#include "compiler.h"
+/* Flag param bits for bootelf() function */
+typedef struct {
+ unsigned phdr : 1; /* load via program (not section) headers */
+ unsigned autostart : 1; /* Start ELF after loading */
+} Bootelf_flags;
+
/* This version doesn't work for 64-bit ABIs - Erik */
/* These typedefs need to be handled better */
@@ -700,6 +706,10 @@
#define R_RISCV_RELATIVE 3
#ifndef __ASSEMBLY__
+unsigned long bootelf_exec(ulong (*entry)(int, char * const[]),
+ int argc, char *const argv[]);
+unsigned long bootelf(unsigned long addr, Bootelf_flags flags,
+ int argc, char *const argv[]);
int valid_elf_image(unsigned long addr);
unsigned long load_elf64_image_phdr(unsigned long addr);
unsigned long load_elf64_image_shdr(unsigned long addr);
diff --git a/include/watchdog.h b/include/watchdog.h
index ac5f11e..d1956fa 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -40,7 +40,4 @@
void hw_watchdog_init(void);
#endif
-#if defined(CONFIG_MPC85xx)
- void init_85xx_watchdog(void);
-#endif
#endif /* _WATCHDOG_H_ */
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 430bb7f..ee71f41 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -10,9 +10,9 @@
depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
- depends on BLK
depends on !EFI_APP
default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
+ select BLK
select CHARSET
# We need to send DM events, dynamically, in the EFI block driver
select DM_EVENT
diff --git a/lib/elf.c b/lib/elf.c
index 9a794f9..dc13935 100644
--- a/lib/elf.c
+++ b/lib/elf.c
@@ -7,6 +7,7 @@
#include <cpu_func.h>
#include <elf.h>
#include <env.h>
+#include <errno.h>
#include <net.h>
#include <vxworks.h>
#ifdef CONFIG_X86
@@ -15,6 +16,59 @@
#include <linux/linkage.h>
#endif
+/**
+ * bootelf_exec() - start the ELF image execution.
+ *
+ * @entry: address of entry point of ELF.
+ *
+ * May by used to allow ports to override the default behavior.
+ */
+unsigned long bootelf_exec(ulong (*entry)(int, char * const[]),
+ int argc, char *const argv[])
+{
+ return entry(argc, argv);
+}
+
+/**
+ * bootelf() - Boot ELF from memory.
+ *
+ * @addr: Loading address of ELF in memory.
+ * @flags: Bits like ELF_PHDR to control boot details.
+ * @argc: May be used to pass command line arguments (maybe unused).
+ * Necessary for backward compatibility with the CLI command.
+ * If unused, must be 0.
+ * @argv: see @argc. If unused, must be NULL.
+ * Return: Number returned by ELF application.
+ *
+ * Sets errno = ENOEXEC if the ELF image is not valid.
+ */
+unsigned long bootelf(unsigned long addr, Bootelf_flags flags,
+ int argc, char *const argv[])
+{
+ unsigned long entry_addr;
+ char *args[] = {"", NULL};
+
+ errno = 0;
+
+ if (!valid_elf_image(addr)) {
+ errno = ENOEXEC;
+ return 1;
+ }
+
+ entry_addr = flags.phdr ? load_elf_image_phdr(addr)
+ : load_elf_image_shdr(addr);
+
+ if (!flags.autostart)
+ return 0;
+
+ if (!argc && !argv) {
+ argc = 1;
+ argv = args;
+ }
+
+ return bootelf_exec((void *)entry_addr, argc, argv);
+}
+
/*
* A very simple ELF64 loader, assumes the image is valid, returns the
* entry point address.
diff --git a/test/common/cyclic.c b/test/common/cyclic.c
index 461f8cf..51a07c5 100644
--- a/test/common/cyclic.c
+++ b/test/common/cyclic.c
@@ -12,22 +12,27 @@
#include <linux/delay.h>
/* Test that cyclic function is called */
-static bool cyclic_active = false;
+static struct cyclic_test {
+ struct cyclic_info cyclic;
+ bool called;
+} cyclic_test;
-static void cyclic_test(void *ctx)
+static void test_cb(struct cyclic_info *c)
{
- cyclic_active = true;
+ struct cyclic_test *t = container_of(c, struct cyclic_test, cyclic);
+ t->called = true;
}
static int dm_test_cyclic_running(struct unit_test_state *uts)
{
- cyclic_active = false;
- ut_assertnonnull(cyclic_register(cyclic_test, 10 * 1000, "cyclic_demo",
- NULL));
+ cyclic_test.called = false;
+ cyclic_register(&cyclic_test.cyclic, test_cb, 10 * 1000, "cyclic_test");
/* Execute all registered cyclic functions */
schedule();
- ut_asserteq(true, cyclic_active);
+ ut_asserteq(true, cyclic_test.called);
+
+ cyclic_unregister(&cyclic_test.cyclic);
return 0;
}
diff --git a/tools/Kconfig b/tools/Kconfig
index 667807b..5c75af4 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -98,7 +98,7 @@
config TOOLS_MKEFICAPSULE
bool "Build efimkcapsule command"
- default y if EFI_CAPSULE_ON_DISK
+ default y if EFI_LOADER
help
This command allows users to create a UEFI capsule file and,
optionally sign that file. If you want to enable UEFI capsule