| commit | 04e1c3fbf7213a46d0ac82e9fea7f8c2630dcf94 | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marex@denx.de> | Tue May 02 20:27:41 2017 +0200 |
| committer | Tom Rini <trini@konsulko.com> | Thu Jun 29 13:30:28 2017 -0400 |
| tree | 943eb63d7f3989a5eaa893019e516bf5209d5404 | |
| parent | 6efde71e101d3c781c9f08b9c3fe4821537ca38c [diff] |
ARM: at91: ma5d4: Switch DDR2 controller to sequencial address decoding According to the datasheet, sequential mapping is used for DDR SDRAM, while interleaved mapping is used for regular SDRAM. Incorrect configuration of this bit does indeed cause sporadic memory instability. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com>