Merge branch '2023-08-17-ti-k3-am64-dt-resync' into next
To quote the author:
This series syncs AM64 DT files from Linux v6.5-rc1.
Tested on AM642-EVM GP SR1.0 and AM642-SK-EVM HS-FS SR2.0.
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index 5e8036f..1664d9f 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -228,12 +228,161 @@
};
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 36 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 36 1>;
+ assigned-clock-parents = <&k3_clks 36 2>;
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 37 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 37 1>;
+ assigned-clock-parents = <&k3_clks 37 2>;
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 38 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 38 1>;
+ assigned-clock-parents = <&k3_clks 38 2>;
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 39 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 39 1>;
+ assigned-clock-parents = <&k3_clks 39 2>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 40 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 40 1>;
+ assigned-clock-parents = <&k3_clks 40 2>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 41 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 41 1>;
+ assigned-clock-parents = <&k3_clks 41 2>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 42 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 42 1>;
+ assigned-clock-parents = <&k3_clks 42 2>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 43 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 43 1>;
+ assigned-clock-parents = <&k3_clks 43 2>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 44 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 44 1>;
+ assigned-clock-parents = <&k3_clks 44 2>;
+ power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 45 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 45 1>;
+ assigned-clock-parents = <&k3_clks 45 2>;
+ power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 46 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 46 1>;
+ assigned-clock-parents = <&k3_clks 46 2>;
+ power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 47 1>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 47 1>;
+ assigned-clock-parents = <&k3_clks 47 2>;
+ power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_esm: esm@420000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x420000 0x00 0x1000>;
+ ti,esm-pins = <160>, <161>;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
@@ -245,7 +394,6 @@
reg = <0x00 0x02810000 0x00 0x100>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
@@ -257,7 +405,6 @@
reg = <0x00 0x02820000 0x00 0x100>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 0>;
clock-names = "fclk";
@@ -269,7 +416,6 @@
reg = <0x00 0x02830000 0x00 0x100>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 154 0>;
clock-names = "fclk";
@@ -281,7 +427,6 @@
reg = <0x00 0x02840000 0x00 0x100>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 155 0>;
clock-names = "fclk";
@@ -293,7 +438,6 @@
reg = <0x00 0x02850000 0x00 0x100>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 156 0>;
clock-names = "fclk";
@@ -305,7 +449,6 @@
reg = <0x00 0x02860000 0x00 0x100>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- current-speed = <115200>;
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 158 0>;
clock-names = "fclk";
@@ -676,6 +819,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@29030000 {
@@ -686,6 +830,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@29040000 {
@@ -696,6 +841,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@29050000 {
@@ -706,6 +852,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@29060000 {
@@ -715,6 +862,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@29070000 {
@@ -724,6 +872,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
+ status = "disabled";
};
main_r5fss0: r5fss@78000000 {
@@ -1392,4 +1541,12 @@
clock-names = "fck";
status = "disabled";
};
+
+ main_vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi
index 38ddf0b..686d497 100644
--- a/arch/arm/dts/k3-am64-mcu.dtsi
+++ b/arch/arm/dts/k3-am64-mcu.dtsi
@@ -6,11 +6,55 @@
*/
&cbass_mcu {
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@4800000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4800000 0x00 0x400>;
+ clocks = <&k3_clks 35 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@4810000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4810000 0x00 0x400>;
+ clocks = <&k3_clks 48 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@4820000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4820000 0x00 0x400>;
+ clocks = <&k3_clks 49 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@4830000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4830000 0x00 0x400>;
+ clocks = <&k3_clks 50 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
@@ -21,7 +65,6 @@
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- current-speed = <115200>;
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 160 0>;
clock-names = "fclk";
@@ -109,4 +152,10 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
+
+ mcu_esm: esm@4100000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x4100000 0x00 0x1000>;
+ ti,esm-pins = <0>, <1>;
+ };
};
diff --git a/arch/arm/dts/k3-am64-thermal.dtsi b/arch/arm/dts/k3-am64-thermal.dtsi
new file mode 100644
index 0000000..036db56
--- /dev/null
+++ b/arch/arm/dts/k3-am64-thermal.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&main_vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&main_vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
index c858725..8e9c2bc 100644
--- a/arch/arm/dts/k3-am64.dtsi
+++ b/arch/arm/dts/k3-am64.dtsi
@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM642 SoC";
compatible = "ti,am642";
@@ -18,22 +19,6 @@
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- serial0 = &mcu_uart0;
- serial1 = &mcu_uart1;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial4 = &main_uart2;
- serial5 = &main_uart3;
- serial6 = &main_uart4;
- serial7 = &main_uart5;
- serial8 = &main_uart6;
- ethernet0 = &cpsw_port1;
- ethernet1 = &cpsw_port2;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- };
-
chosen { };
firmware {
@@ -69,6 +54,7 @@
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
@@ -105,6 +91,8 @@
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
};
+
+ #include "k3-am64-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 73577e8..c85f57d 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -7,8 +7,7 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
+ tick-timer = &main_timer0;
};
memory@80000000 {
@@ -16,15 +15,21 @@
};
};
-&cbass_main{
+&vtt_supply {
bootph-pre-ram;
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x2400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
+};
+
+&cbass_main {
+ bootph-pre-ram;
+};
+
+&cbass_mcu {
+ bootph-pre-ram;
+};
+
+&main_timer0 {
+ bootph-pre-ram;
+ clock-frequency = <200000000>;
};
&main_conf {
@@ -36,23 +41,20 @@
&main_pmx0 {
bootph-pre-ram;
- main_i2c0_pins_default: main-i2c0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
- AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
- >;
- };
+};
+
+&main_i2c0_pins_default {
+ bootph-pre-ram;
};
&main_i2c0 {
- status = "okay";
bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
};
+&main_uart0_pins_default {
+ bootph-pre-ram;
+};
+
&main_uart0 {
bootph-pre-ram;
};
@@ -111,18 +113,7 @@
};
&cpsw3g {
- reg = <0x0 0x8000000 0x0 0x200000>,
- <0x0 0x43000200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
- pinctrl-0 = <&mdio1_pins_default /* HACK: as MDIO driver is not DM enabled */
- &rgmii1_pins_default
- &rgmii2_pins_default>;
-
- cpsw-phy-sel@04044 {
- compatible = "ti,am64-phy-gmii-sel";
- reg = <0x0 0x43004044 0x0 0x8>;
- };
+ bootph-pre-ram;
};
&cpsw_port2 {
diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts
index 39feea7..15c282c 100644
--- a/arch/arm/dts/k3-am642-evm.dts
+++ b/arch/arm/dts/k3-am642-evm.dts
@@ -17,15 +17,26 @@
model = "Texas Instruments AM642 EVM";
chosen {
- stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ stdout-path = &main_uart0;
};
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &main_uart1;
+ serial2 = &main_uart0;
+ serial3 = &main_uart3;
+ i2c0 = &main_i2c0;
+ i2c1 = &main_i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
+ };
+
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
};
reserved-memory {
@@ -94,7 +105,7 @@
};
};
- evm_12v0: fixedregulator-evm12v0 {
+ evm_12v0: regulator-0 {
/* main DC jack */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
@@ -104,7 +115,7 @@
regulator-boot-on;
};
- vsys_5v0: fixedregulator-vsys5v0 {
+ vsys_5v0: regulator-1 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
@@ -115,7 +126,7 @@
regulator-boot-on;
};
- vsys_3v3: fixedregulator-vsys3v3 {
+ vsys_3v3: regulator-2 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
@@ -126,7 +137,7 @@
regulator-boot-on;
};
- vdd_mmc1: fixed-regulator-sd {
+ vdd_mmc1: regulator-3 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@@ -138,12 +149,26 @@
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
};
- vddb: fixedregulator-vddb {
+ vddb: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vtt_supply: regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ddr_vtt_pins_default>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
vin-supply = <&vsys_3v3>;
+ enable-active-high;
regulator-always-on;
regulator-boot-on;
};
@@ -201,7 +226,7 @@
};
&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
@@ -215,7 +240,16 @@
>;
};
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
+ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
@@ -224,7 +258,7 @@
>;
};
- main_spi0_pins_default: main-spi0-pins-default {
+ main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
@@ -233,21 +267,28 @@
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
- mdio1_pins_default: mdio1-pins-default {
+ mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
- rgmii1_pins_default: rgmii1-pins-default {
+ rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
@@ -264,7 +305,7 @@
>;
};
- rgmii2_pins_default: rgmii2-pins-default {
+ rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
@@ -281,13 +322,13 @@
>;
};
- main_usb0_pins_default: main-usb0-pins-default {
+ main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
- ospi0_pins_default: ospi0-pins-default {
+ ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
@@ -303,38 +344,60 @@
>;
};
- main_ecap0_pins_default: main-ecap0-pins-default {
+ main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
- main_mcan0_pins_default: main-mcan0-pins-default {
+ main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
>;
};
- main_mcan1_pins_default: main-mcan1-pins-default {
+ main_mcan1_pins_default: main-mcan1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
>;
};
+
+ ddr_vtt_pins_default: ddr-vtt-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
+ >;
+ };
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ current-speed = <115200>;
};
/* main_uart1 is reserved for firmware usage */
&main_uart1 {
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
};
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ /* AT24CM01 */
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
+};
+
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
@@ -425,8 +488,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default
- &rgmii2_pins_default>;
+ pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
@@ -471,10 +533,53 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ospi.tispl";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "ospi.u-boot";
+ reg = <0x300000 0x400000>;
+ };
+
+ partition@700000 {
+ label = "ospi.env";
+ reg = <0x700000 0x40000>;
+ };
+
+ partition@740000 {
+ label = "ospi.env.backup";
+ reg = <0x740000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
};
};
&mailbox0_cluster2 {
+ status = "okay";
+
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -486,11 +591,9 @@
};
};
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
&mailbox0_cluster4 {
+ status = "okay";
+
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -502,41 +605,35 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
&mailbox0_cluster6 {
+ status = "okay";
+
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index b490641..73461f8 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -1,34 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
-/dts-v1/;
-
-#include "k3-am642.dtsi"
+#include "k3-am642-evm.dts"
#include "k3-am64-evm-ddr4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
-#include "k3-am64x-binman.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
+#include "k3-am642-evm-u-boot.dtsi"
+/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
- bootph-pre-ram;
- };
-
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
@@ -46,34 +32,12 @@
bootph-pre-ram;
};
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
- };
-
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
-
- vtt_supply: vtt-supply {
- compatible = "regulator-gpio";
- regulator-name = "vtt";
- regulator-min-microvolt = <0>;
- regulator-max-microvolt = <3300000>;
- gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
- states = <0 0x0 3300000 0x1>;
- bootph-pre-ram;
- };
};
&cbass_main {
@@ -85,131 +49,12 @@
};
};
-&cbass_main {
- main_esm: esm@420000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x420000 0x0 0x1000>;
- ti,esm-pins = <160>, <161>;
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu {
+&main_esm {
bootph-pre-ram;
- mcu_esm: esm@4100000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x4100000 0x0 0x1000>;
- ti,esm-pins = <0>, <1>;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&mcu_esm {
bootph-pre-ram;
- main_uart0_pins_default: main-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
- AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
- AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
- AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
- AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
- AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
- AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
- >;
- };
-
- main_mmc0_pins_default: main-mmc0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
- AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
- AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
- >;
- };
-
- ddr_vtt_pins_default: ddr-vtt-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
- >;
- };
-
- main_usb0_pins_default: main-usb0-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
- >;
- };
-
- mdio1_pins_default: mdio1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
- >;
- };
-
- rgmii1_pins_default: rgmii1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
- AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
- AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
- AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
- AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
- AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
- >;
- };
-
- rgmii2_pins_default: rgmii2-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
- >;
- };
};
&dmsc {
@@ -221,65 +66,41 @@
ti,secure-host;
};
-&main_uart0 {
- /delete-property/ power-domains;
- /delete-property/ clocks;
- /delete-property/ clock-names;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_uart1 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&memorycontroller {
- vtt-supply = <&vtt_supply>;
- pinctrl-names = "default";
- pinctrl-0 = <&ddr_vtt_pins_default>;
-};
-
&sdhci0 {
- /delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
- ti,driver-strength-ohm = <50>;
- disable-wp;
- pinctrl-0 = <&main_mmc0_pins_default>;
};
&sdhci1 {
- /delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
- ti,driver-strength-ohm = <50>;
- disable-wp;
- pinctrl-0 = <&main_mmc1_pins_default>;
};
&main_gpio0 {
bootph-pre-ram;
- /delete-property/ power-domains;
};
-/* EEPROM might be read before SYSFW is available */
-&main_i2c0 {
+/* UART is initialized before SYSFW is started
+ * so we can't do any power-domain/clock operations.
+ * Delete clock/power-domain properties to avoid
+ * UART init failure
+ */
+&main_uart0 {
/delete-property/ power-domains;
-};
-
-&usbss0 {
- ti,vbus-divider;
- ti,usb2-only;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
};
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "high-speed";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb0_pins_default>;
+/* timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ power-domains;
};
-
-#include "k3-am642-evm-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index 32d4c31..def4622 100644
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -3,33 +3,18 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
-/dts-v1/;
-
-#include <dt-bindings/mux/ti-serdes.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am642.dtsi"
+#include "k3-am642-sk.dts"
#include "k3-am64-sk-lp4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
+#include "k3-am642-sk-u-boot.dtsi"
+/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- bootph-pre-ram;
- };
-
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
@@ -47,18 +32,6 @@
bootph-pre-ram;
};
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
- };
-
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -76,108 +49,12 @@
};
};
-&cbass_main {
- main_esm: esm@420000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x420000 0x0 0x1000>;
- ti,esm-pins = <160>, <161>;
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu {
+&main_esm {
bootph-pre-ram;
- mcu_esm: esm@4100000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x4100000 0x0 0x1000>;
- ti,esm-pins = <0>, <1>;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&mcu_esm {
bootph-pre-ram;
- main_uart0_pins_default: main-uart0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
- AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
- AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
- AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
- AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
- AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
- AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
- AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
- AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
- >;
- };
-
- main_usb0_pins_default: main-usb0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
- >;
- };
-
- mdio1_pins_default: mdio1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
- >;
- };
-
- rgmii1_pins_default: rgmii1-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
- AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
- AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
- AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
- AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
- AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
- >;
- };
-
- rgmii2_pins_default: rgmii2-pins-default {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
- >;
- };
};
&dmsc {
@@ -189,79 +66,36 @@
ti,secure-host;
};
-&main_uart0 {
- /delete-property/ power-domains;
- /delete-property/ clocks;
- /delete-property/ clock-names;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_uart1 {
- bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
&sdhci1 {
- /delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
- ti,driver-strength-ohm = <50>;
- disable-wp;
- pinctrl-0 = <&main_mmc1_pins_default>;
};
-&serdes_ln_ctrl {
- idle-states = <AM64_SERDES0_LANE0_USB>;
-};
-
&serdes_wiz0 {
status = "okay";
};
-&serdes0 {
- serdes0_usb_link: link@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_USB3>;
- resets = <&serdes_wiz0 1>;
- };
-};
-
-&usbss0 {
- ti,vbus-divider;
-};
-
-&usb0 {
- dr_mode = "host";
- maximum-speed = "super-speed";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb0_pins_default>;
- phys = <&serdes0_usb_link>;
- phy-names = "cdns3,usb3-phy";
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
- &rgmii2_pins_default>;
-};
-
-&cpsw_port2 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy1>;
+/* UART is initialized before SYSFW is started
+ * so we can't do any power-domain/clock operations.
+ * Delete clock/power-domain properties to avoid
+ * UART init failure
+ */
+&main_uart0 {
+ /delete-property/ power-domains;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
};
-&cpsw3g_mdio {
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
+/* timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&main_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ power-domains;
};
-
-#include "k3-am642-sk-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 3d6be02..c277ef8 100644
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -7,14 +7,9 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
+ tick-timer = &main_timer0;
};
- aliases {
- mmc1 = &sdhci1;
- };
-
memory@80000000 {
bootph-pre-ram;
};
@@ -22,15 +17,17 @@
&cbass_main{
bootph-pre-ram;
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x2400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
+};
+
+&cbass_mcu {
+ bootph-pre-ram;
};
+&main_timer0 {
+ bootph-pre-ram;
+ clock-frequency = <200000000>;
+};
+
&main_conf {
bootph-pre-ram;
chipid@14 {
@@ -40,81 +37,18 @@
&main_pmx0 {
bootph-pre-ram;
- main_i2c0_pins_default: main-i2c0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
- AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
- >;
- };
};
-&main_i2c0 {
+&main_i2c0_pins_default {
bootph-pre-ram;
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- tps65219: pmic@30 {
- compatible = "ti,tps65219";
- reg = <0x30>;
-
- regulators {
- buck1_reg: buck1 {
- regulator-name = "VDD_CORE";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <750000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck2_reg: buck2 {
- regulator-name = "VCC1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck3_reg: buck3 {
- regulator-name = "VDD_LPDDR4";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- regulator-name = "VDDSHV_SD_IO_PMIC";
- regulator-min-microvolt = <33000000>;
- regulator-max-microvolt = <33000000>;
- };
-
- ldo2_reg: ldo2 {
- regulator-name = "VDDAR_CORE";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-boot-on;
- regulator-always-on;
- };
+};
- ldo3_reg: ldo3 {
- regulator-name = "VDDA_1V8";
- regulator-min-microvolt = <18000000>;
- regulator-max-microvolt = <18000000>;
- regulator-boot-on;
- regulator-always-on;
- };
+&main_i2c0 {
+ bootph-pre-ram;
+};
- ldo4_reg: ldo4 {
- regulator-name = "VDD_PHY_2V5";
- regulator-min-microvolt = <25000000>;
- regulator-max-microvolt = <25000000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
+&main_uart0_pins_default {
+ bootph-pre-ram;
};
&main_uart0 {
@@ -163,18 +97,8 @@
};
&cpsw3g {
- reg = <0x0 0x8000000 0x0 0x200000>,
- <0x0 0x43000200 0x0 0x8>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
bootph-pre-ram;
- cpsw-phy-sel@04044 {
- compatible = "ti,am64-phy-gmii-sel";
- reg = <0x0 0x43004044 0x0 0x8>;
- bootph-pre-ram;
- };
-
ethernet-ports {
bootph-pre-ram;
};
@@ -221,7 +145,6 @@
};
&usb0 {
- dr_mode = "host";
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts
index 2e2d40d..cbce43d 100644
--- a/arch/arm/dts/k3-am642-sk.dts
+++ b/arch/arm/dts/k3-am642-sk.dts
@@ -17,15 +17,25 @@
model = "Texas Instruments AM642 SK";
chosen {
- stdout-path = "serial2:115200n8";
- bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ stdout-path = &main_uart0;
};
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &main_uart1;
+ serial2 = &main_uart0;
+ i2c0 = &main_i2c0;
+ i2c1 = &main_i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
+ };
+
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
};
reserved-memory {
@@ -94,7 +104,7 @@
};
};
- vusb_main: fixed-regulator-vusb-main5v0 {
+ vusb_main: regulator-0 {
/* USB MAIN INPUT 5V DC */
compatible = "regulator-fixed";
regulator-name = "vusb_main5v0";
@@ -104,7 +114,7 @@
regulator-boot-on;
};
- vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
+ vcc_3v3_sys: regulator-1 {
/* output of LP8733xx */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
@@ -115,7 +125,7 @@
regulator-boot-on;
};
- vdd_mmc1: fixed-regulator-sd {
+ vdd_mmc1: regulator-2 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@@ -127,7 +137,7 @@
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
- com8_ls_en: regulator-1 {
+ com8_ls_en: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "com8_ls_en";
regulator-min-microvolt = <3300000>;
@@ -139,7 +149,7 @@
gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
};
- wlan_en: regulator-2 {
+ wlan_en: regulator-4 {
/* output of SN74AVC4T245RSVR */
compatible = "regulator-fixed";
regulator-name = "wlan_en";
@@ -222,20 +232,21 @@
};
&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
- AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
>;
};
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
@@ -244,27 +255,43 @@
>;
};
- main_usb0_pins_default: main-usb0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
+ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
+ >;
+ };
+
+ main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+ >;
+ };
+
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
- mdio1_pins_default: mdio1-pins-default {
+ mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
- rgmii1_pins_default: rgmii1-pins-default {
+ rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
@@ -281,7 +308,7 @@
>;
};
- rgmii2_pins_default: rgmii2-pins-default {
+ rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
@@ -298,7 +325,7 @@
>;
};
- ospi0_pins_default: ospi0-pins-default {
+ ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
@@ -314,24 +341,24 @@
>;
};
- main_ecap0_pins_default: main-ecap0-pins-default {
+ main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
- main_wlan_en_pins_default: main-wlan-en-pins-default {
+ main_wlan_en_pins_default: main-wlan-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
>;
};
- main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
+ main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
>;
};
- main_wlan_pins_default: main-wlan-pins-default {
+ main_wlan_pins_default: main-wlan-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
>;
@@ -342,13 +369,28 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ current-speed = <115200>;
};
&main_uart1 {
/* main_uart1 is reserved for firmware usage */
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
};
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@51 {
+ compatible = "atmel,24c512";
+ reg = <0x51>;
+ };
+};
+
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
@@ -439,8 +481,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default
- &rgmii2_pins_default>;
+ pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
@@ -490,10 +531,53 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ospi.tispl";
+ reg = <0x100000 0x200000>;
+ };
+
+ partition@300000 {
+ label = "ospi.u-boot";
+ reg = <0x300000 0x400000>;
+ };
+
+ partition@700000 {
+ label = "ospi.env";
+ reg = <0x700000 0x40000>;
+ };
+
+ partition@740000 {
+ label = "ospi.env.backup";
+ reg = <0x740000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
};
};
&mailbox0_cluster2 {
+ status = "okay";
+
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -505,11 +589,9 @@
};
};
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
&mailbox0_cluster4 {
+ status = "okay";
+
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@@ -521,41 +603,35 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
&mailbox0_cluster6 {
+ status = "okay";
+
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
diff --git a/arch/arm/dts/k3-am642.dtsi b/arch/arm/dts/k3-am642.dtsi
index 8a76f48..7a6eede 100644
--- a/arch/arm/dts/k3-am642.dtsi
+++ b/arch/arm/dts/k3-am642.dtsi
@@ -58,6 +58,7 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <256>;
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index 96f4e30..a080b2b 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -18,7 +18,8 @@
#include "../common/board_detect.h"
-#define board_is_am64x_gpevm() board_ti_k3_is("AM64-GPEVM")
+#define board_is_am64x_gpevm() (board_ti_k3_is("AM64-GPEVM") || \
+ board_ti_k3_is("AM64-HSEVM"))
#define board_is_am64x_skevm() (board_ti_k3_is("AM64-SKEVM") || \
board_ti_k3_is("AM64B-SKEVM"))
diff --git a/doc/board/ti/am64x_evm.rst b/doc/board/ti/am64x_evm.rst
new file mode 100644
index 0000000..8d3795e
--- /dev/null
+++ b/doc/board/ti/am64x_evm.rst
@@ -0,0 +1,197 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Nishanth Menon <nm@ti.com>
+
+AM64 Platforms
+==============
+
+Introduction:
+-------------
+The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
+providing advanced system integration to enable applications such as
+Motor Drives, PLC, Remote IO and IoT Gateways.
+
+Some highlights of this SoC are:
+
+* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
+ MCUs, and a single Cortex-M4F.
+* Two Gigabit Industrial Communication Subsystems (ICSSG).
+* Integrated Ethernet switch supporting up to a total of two external
+ ports.
+* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
+ controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
+ peripherals.
+* Centralized System Controller for Security, Power, and Resource
+ Management (DMSC).
+
+More details can be found in the Technical Reference Manual:
+ https://www.ti.com/lit/pdf/spruim2
+
+Platform information:
+
+* AM64-EVM: https://www.ti.com/tool/TMDS64EVM
+* AM64-SK: https://www.ti.com/tool/SK-AM64B
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: img/boot_diagram_am64.svg
+
+- Here TIFS acts as master and provides all the critical services. R5/A53
+ requests TIFS to get these services done as shown in the above diagram.
+
+Sources:
+--------
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=am64x_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=am64x_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am64x
+ $ # we dont use any extra TFA parameters
+ $ unset OPTEE_EXTRA_ARGS
+
+.. am64x_evm_rst_include_start_build_steps
+
+1. Trusted Firmware-A:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_tfa
+ :end-before: .. k3_rst_include_end_build_steps_tfa
+
+
+2. OP-TEE:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_optee
+ :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 4.1 R5:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 4.2 A53:
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+.. am64x_evm_rst_include_end_build_steps
+
+Target Images
+--------------
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
+variant (GP, HS-FS, HS-SE) requires a different source for these files.
+
+ - GP
+
+ * tiboot3-am64x-gp-evm.bin from step 3.1
+ * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2
+
+ - HS-FS
+
+ * tiboot3-am64x-hs-fs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+ * tiboot3-am64x-hs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+
+- tispl.bin
+
+.. image:: img/nodm_tispl.bin.svg
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on AM64 platform. More
+details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruim2 under the `Boot Mode Pins` section.
+
+.. list-table:: Boot Modes for AM64x-EVM
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW2: 12345678
+ - SW3: 12345678
+
+ * - SD/MMC
+ - 11000010
+ - 01000000
+
+ * - xSPI/SFDP (OSPI)
+ - 11001110
+ - 01000000
+
+ * - UART
+ - 11011100
+ - 00000000
+
+.. note ::
+
+ For SW2 and SW3, the switch state in the "ON" position = 1.
+
+.. list-table:: Boot Modes for AM64x-SK
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW2: 12345678
+ - SW3: 12345678
+
+ * - SD/MMC
+ - 00000010
+ - 01000011
+
+ * - xSPI/SFDP (OSPI)
+ - 00000010
+ - 01110011
+
+ * - UART
+ - 00000000
+ - 00111011
+
+.. note ::
+
+ For SW2 and SW3, the switch state in the "ON" position = 1.
+ Boot bits on SK is reversed bits to the bootmode signals
diff --git a/doc/board/ti/img/boot_diagram_am64.svg b/doc/board/ti/img/boot_diagram_am64.svg
new file mode 100644
index 0000000..9c922a5
--- /dev/null
+++ b/doc/board/ti/img/boot_diagram_am64.svg
@@ -0,0 +1,1702 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!--SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause-->
+
+<!--Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/-->
+
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+ version="1.1"
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+ data-drawio-colors="color: rgb(0, 0, 0); ">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Load Aux core f/w<xhtml:br />
+
+(optional)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="544"
+ y="840"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
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+ id="text322">Load Aux core f/w...</text>
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+ y="860"
+ width="103"
+ height="32"
+ rx="4.8"
+ ry="4.8"
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+ stroke="rgb(0, 0, 0)"
+ pointer-events="all"
+ id="rect328" />
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g334">
+ <switch
+ id="switch332">
+ <foreignObject
+ style="overflow: visible; text-align: left;"
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 101px; height: 1px; padding-top: 876px; margin-left: 493px;">
+ <xhtml:div
+ style="box-sizing: border-box; font-size: 0px; text-align: center;"
+ data-drawio-colors="color: rgb(0, 0, 0); ">
+ <xhtml:div
+ style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Start Aux core<xhtml:br />
+
+(optional)</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="544"
+ y="880"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="12px"
+ text-anchor="middle"
+ id="text330">Start Aux core...</text>
+ </switch>
+ </g>
+ <path
+ d="M 132 909 L 628.38 909"
+ fill="none"
+ stroke="rgb(0, 0, 0)"
+ stroke-miterlimit="10"
+ pointer-events="stroke"
+ id="path336" />
+ <path
+ d="M 633.63 909 L 626.63 912.5 L 628.38 909 L 626.63 905.5 Z"
+ fill="rgb(0, 0, 0)"
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+ stroke-miterlimit="10"
+ pointer-events="all"
+ id="path338" />
+ <g
+ transform="translate(-0.5 -0.5)"
+ id="g344">
+ <switch
+ id="switch342">
+ <foreignObject
+ style="overflow: visible; text-align: left;"
+ pointer-events="none"
+ width="100%"
+ height="100%"
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility">
+ <xhtml:div
+ style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 900px; margin-left: 203px;">
+ <xhtml:div
+ style="box-sizing: border-box; font-size: 0px; text-align: center;"
+ data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); ">
+ <xhtml:div
+ style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Release Reset</xhtml:div>
+ </xhtml:div>
+ </xhtml:div>
+ </foreignObject>
+ <text
+ x="203"
+ y="903"
+ fill="rgb(0, 0, 0)"
+ font-family="Helvetica"
+ font-size="11px"
+ text-anchor="middle"
+ id="text340">Release Re...</text>
+ </switch>
+ </g>
+ </g>
+ <switch
+ id="switch354">
+ <g
+ requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"
+ id="g348" />
+ <a
+ transform="translate(0,-5)"
+ xlink:href="https://www.drawio.com/doc/faq/svg-export-text-problems"
+ target="_blank"
+ id="a352">
+ <text
+ text-anchor="middle"
+ font-size="10px"
+ x="50%"
+ y="100%"
+ id="text350">Text is not SVG - cannot display</text>
+ </a>
+ </switch>
+</svg>
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index d2f86b0..02cfd93 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -32,6 +32,7 @@
am62x_sk
../toradex/verdin-am62
+ am64x_evm
am65x_evm
j7200_evm
j721e_evm
