keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
index 4147811..df33a78 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
@@ -56,10 +56,26 @@
DDR3_PLL,
};
+enum {
+ SPD800,
+ SPD850,
+ SPD1000,
+ SPD1250,
+ SPD1350,
+ SPD1400,
+ SPD1500,
+ SPD_RSV
+};
+
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
+#define CORE_PLL_1250 {CORE_PLL, 25, 1, 2}
+#define CORE_PLL_1350 {CORE_PLL, 27, 1, 2}
+#define CORE_PLL_1400 {CORE_PLL, 28, 1, 2}
+#define CORE_PLL_1500 {CORE_PLL, 30, 1, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
index 784a0be..bdb869b 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -63,21 +63,35 @@
DDR3B_PLL,
};
+enum {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD_RSV
+};
+
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_999 {CORE_PLL, 122, 15, 1}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
+#define CORE_PLL_1200 {CORE_PLL, 625, 32, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
+#define TETRIS_PLL_800 {TETRIS_PLL, 32, 5, 1}
#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
+#define TETRIS_PLL_1000 {TETRIS_PLL, 40, 5, 1}
#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
+#define TETRIS_PLL_1350 {TETRIS_PLL, 54, 5, 1}
#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
index 1513c76..dae000e 100644
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -38,12 +38,16 @@
};
extern const struct keystone_pll_regs keystone_pll_regs[];
+extern int dev_speeds[];
+extern int arm_speeds[];
void init_plls(int num_pll, struct pll_init_data *config);
void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
+int get_max_dev_speed(void);
+int get_max_arm_speed(void);
#endif
#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index ddeb06e..d6726a1 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -138,6 +138,10 @@
/* Flag from ks2_debug options to check if DSPs need to stay ON */
#define DBG_LEAVE_DSPS_ON 0x1
+/* Device speed */
+#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
+#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+
/* Queue manager */
#define KS2_QM_MANAGER_BASE 0x02a02000
#define KS2_QM_DESC_SETUP_BASE 0x02a03000