Merge branch '2022-12-05-Kconfig-migrations-and-renames' into next - First batch of the patches that end up with scripts/config_whitelist.tx being empty. Mostly migrations and a little bit of code removal and CFG renaming.

commit: 040227f76d410c389d4403dc505f43173a9b3875 [log] [tgz]
author: Tom Rini <trini@konsulko.com> Mon Dec 05 21:04:24 2022 -0500
committer: Tom Rini <trini@konsulko.com> Mon Dec 05 21:04:24 2022 -0500
tree: 23ec41dc6f0aff10b800c69396a32ac5ac926817
parent: ca8f571310240395b01f69929726b06ca277913b [diff]
parent: 9e7eeec7347177f53d12d93cb4049e19d1db9a67 [diff]
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index d02c663..add8847 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml

@@ -30,7 +30,7 @@
           %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
         displayName: 'Install Toolchain'
       - script: |
-          echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh
+          echo make tools-only_defconfig tools-only > build-tools.sh
           %CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh"
         displayName: 'Build Host Tools'
         env:
@@ -47,7 +47,7 @@
       - script: brew install make ossp-uuid
         displayName: Brew install dependencies
       - script: |
-          gmake tools-only_config tools-only NO_SDL=1 \
+          gmake tools-only_config tools-only \
             HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \
             HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \
             -j$(sysctl -n hw.logicalcpu)

diff --git a/.checkpatch.conf b/.checkpatch.conf
index 9e40ea06..c368d41 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf

@@ -4,7 +4,7 @@
 # Temporary for false positive in checkpatch
 --ignore COMPLEX_MACRO
 
-# For CONFIG_SYS_I2C_NOPROBES
+# For CFG_SYS_I2C_NOPROBES
 --ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
 
 # For simple_strtoul

diff --git a/Kconfig b/Kconfig
index 67f4646..297281e 100644
--- a/Kconfig
+++ b/Kconfig

@@ -264,8 +264,8 @@
 	default y if TFABOOT
 	help
 	  Typically, we use an initial stack pointer address that is calculated
-	  by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
-	  statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
+	  by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the
+	  statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the
 	  build-time constant of GENERATED_GBL_DATA_SIZE.  On MIPS a different
 	  but statica calculation is performed.  However, some platforms will
 	  take a different approach.  Say Y here to define the address statically
@@ -333,7 +333,7 @@
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
-	  It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
+	  It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new
 	  malloc() region in SDRAM once it is inited.
 
 config TPL_SYS_MALLOC_F_LEN

diff --git a/Makefile b/Makefile
index de57463..d48f52f 100644
--- a/Makefile
+++ b/Makefile

@@ -1138,10 +1138,10 @@
 	$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
 		$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
 	$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
-	@# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
+	@# CFG_SYS_TIMER_RATE has brackets in it for some boards which
 	@# confuses this rule. Use if() to send just a single character which
 	@# is enable to tell 'deprecated' that one of these symbols exists
-	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x))
+	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
 	$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
 	$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
 	@# Check that this build does not use CONFIG options that we do not
@@ -1361,8 +1361,8 @@
 # U-Boot entry point, needed for booting of full-blown U-Boot
 # from the SPL U-Boot version.
 #
-ifndef CONFIG_SYS_UBOOT_START
-CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
+ifndef CFG_SYS_UBOOT_START
+CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
 endif
 
 # Boards with more complex image requirements can provide an .its source file
@@ -1387,7 +1387,7 @@
 
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
@@ -1395,10 +1395,10 @@
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
 else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
 endif
@@ -1429,7 +1429,7 @@
 UBOOT_BIN := u-boot.bin
 
 MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 
 u-boot.bin.lzma: u-boot.bin FORCE

diff --git a/README b/README
index d75c3fb..103562b 100644
--- a/README
+++ b/README

@@ -341,7 +341,7 @@
 
 		CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
 		Physical address from the view of DDR controllers. It is the
-		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
+		same as CFG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
 		it could be different for ARM SoCs.
 
 - MIPS CPU options:
@@ -352,7 +352,7 @@
 		be swapped if a flash programmer is used.
 
 - ARM options:
-		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+		CFG_SYS_EXCEPTION_VECTORS_HIGH
 
 		Select high exception vectors of the ARM core, e.g., do not
 		clear the V bit of the c1 register of CP15.
@@ -415,7 +415,7 @@
 		the defaults discussed just above.
 
 - Cache Configuration for ARM:
-		CONFIG_SYS_PL310_BASE - Physical base address of PL310
+		CFG_SYS_PL310_BASE - Physical base address of PL310
 					controller register space
 
 - Serial Ports:
@@ -460,33 +460,8 @@
 		to 0 disables calling WATCHDOG_RESET() from the timer
 		interrupt.
 
-- Real-Time Clock:
-
-		When CONFIG_CMD_DATE is selected, the type of the RTC
-		has to be selected, too. Define exactly one of the
-		following options:
-
-		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
-		CONFIG_RTC_MC13XXX	- use MC13783 or MC13892 RTC
-		CONFIG_RTC_MC146818	- use MC146818 RTC
-		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
-		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
-		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
-		CONFIG_RTC_DS1339	- use Maxim, Inc. DS1339 RTC
-		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
-		CONFIG_RTC_ISL1208	- use Intersil ISL1208 RTC
-		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC
-		CONFIG_RTC_DS1337_NOOSC	- Turn off the OSC output for DS1337
-		CONFIG_SYS_RV3029_TCR	- enable trickle charger on
-					  RV3029 RTC.
-
-		Note that if the RTC uses I2C, then the I2C interface
-		must also be configured. See I2C Support, below.
-
 - GPIO Support:
-		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
-
-		The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
+		The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of
 		chip-ngpio pairs that tell the PCA953X driver the number of
 		pins supported by a particular chip.
 
@@ -654,13 +629,6 @@
 		variable usbtty to be cdc_acm should suffice. The following
 		might be defined in YourBoardName.h
 
-			CONFIG_USB_DEVICE
-			Define this to build a UDC device
-
-			CONFIG_USB_TTY
-			Define this to have a tty type of device available to
-			talk to the UDC device
-
 			CONFIG_USBD_HS
 			Define this to enable the high speed support for usb
 			device and usbtty. If this feature is enabled, a routine
@@ -923,26 +891,26 @@
 		with a list of GPIO LEDs that have inverted polarity.
 
 - I2C Support:
-		CONFIG_SYS_NUM_I2C_BUSES
+		CFG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c buses you want to use.
 
 		CONFIG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
-		if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
+		if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
 		omit this define.
 
-		CONFIG_SYS_I2C_MAX_HOPS
+		CFG_SYS_I2C_MAX_HOPS
 		define how many muxes are maximal consecutively connected
 		on one i2c bus. If you not use i2c muxes, omit this
 		define.
 
-		CONFIG_SYS_I2C_BUSES
+		CFG_SYS_I2C_BUSES
 		hold a list of buses you want to use, only used if
 		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
-		a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
-		CONFIG_SYS_NUM_I2C_BUSES = 9:
+		a board with CFG_SYS_I2C_MAX_HOPS = 1 and
+		CFG_SYS_NUM_I2C_BUSES = 9:
 
-		 CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
+		 CFG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
@@ -1045,7 +1013,7 @@
 		active.	 To switch to a different bus, use the 'i2c dev' command.
 		Note that bus numbering is zero-based.
 
-		CONFIG_SYS_I2C_NOPROBES
+		CFG_SYS_I2C_NOPROBES
 
 		This option specifies a list of I2C devices that will be skipped
 		when the 'i2c probe' command is issued.	 If CONFIG_I2C_MULTI_BUS
@@ -1054,16 +1022,16 @@
 
 		e.g.
 			#undef	CONFIG_I2C_MULTI_BUS
-			#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
+			#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
 
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 
 			#define CONFIG_I2C_MULTI_BUS
-			#define CONFIG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
+			#define CFG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
 
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 
-		CONFIG_SYS_RTC_BUS_NUM
+		CFG_SYS_RTC_BUS_NUM
 
 		If defined, then this indicates the I2C bus number for the RTC.
 		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
@@ -1121,19 +1089,19 @@
 		configuration if the INIT_B line goes low (which
 		indicated a CRC error).
 
-		CONFIG_SYS_FPGA_WAIT_INIT
+		CFG_SYS_FPGA_WAIT_INIT
 
 		Maximum time to wait for the INIT_B line to de-assert
 		after PROB_B has been de-asserted during a Virtex II
 		FPGA configuration sequence. The default time is 500
 		ms.
 
-		CONFIG_SYS_FPGA_WAIT_BUSY
+		CFG_SYS_FPGA_WAIT_BUSY
 
 		Maximum time to wait for BUSY to de-assert during
 		Virtex II FPGA configuration. The default is 5 ms.
 
-		CONFIG_SYS_FPGA_WAIT_CONFIG
+		CFG_SYS_FPGA_WAIT_CONFIG
 
 		Time to wait after FPGA configuration. The default is
 		200 ms.
@@ -1364,24 +1332,20 @@
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
 		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
-		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
-		CONFIG_SYS_NAND_ECCBYTES
+		CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
+		CFG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 
-		CONFIG_SYS_NAND_U_BOOT_DST
+		CFG_SYS_NAND_U_BOOT_DST
 		Location in memory to load U-Boot to
 
-		CONFIG_SYS_NAND_U_BOOT_SIZE
+		CFG_SYS_NAND_U_BOOT_SIZE
 		Size of image to load
 
-		CONFIG_SYS_NAND_U_BOOT_START
+		CFG_SYS_NAND_U_BOOT_START
 		Entry point in loaded image to jump to
 
-		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-		Define this if you need to first read the OOB and then the
-		data. This is used, for example, on davinci platforms.
-
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 
@@ -1434,22 +1398,22 @@
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
 		prompt for user input.
 
-- CONFIG_SYS_BAUDRATE_TABLE:
+- CFG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 
-- CONFIG_SYS_MEM_RESERVE_SECURE
+- CFG_SYS_MEM_RESERVE_SECURE
 		Only implemented for ARMv8 for now.
-		If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
+		If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
 		is substracted from total RAM and won't be reported to OS.
 		This memory can be used as secure memory. A variable
 		gd->arch.secure_ram is used to track the location. In systems
 		the RAM base is not zero, or RAM is divided into banks,
 		this variable needs to be recalcuated to get the address.
 
-- CONFIG_SYS_SDRAM_BASE:
+- CFG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 
-- CONFIG_SYS_FLASH_BASE:
+- CFG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 
 - CONFIG_SYS_MALLOC_LEN:
@@ -1473,16 +1437,16 @@
 		boards which do not use the full malloc in SPL (which is
 		enabled with CONFIG_SYS_SPL_MALLOC).
 
-- CONFIG_SYS_BOOTMAPSZ:
+- CFG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
 		the Linux kernel (bd_info, boot arguments, FDT blob if
 		used) must be put below this limit, unless "bootm_low"
 		environment variable is defined and non-zero. In such case
 		all data for the Linux kernel must be between "bootm_low"
-		and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.	 The environment
+		and "bootm_low" + CFG_SYS_BOOTMAPSZ.	 The environment
 		variable "bootm_mapsize" will override the value of
-		CONFIG_SYS_BOOTMAPSZ.  If CONFIG_SYS_BOOTMAPSZ is undefined,
+		CFG_SYS_BOOTMAPSZ.  If CFG_SYS_BOOTMAPSZ is undefined,
 		then the value in "bootm_size" will be used instead.
 
 - CONFIG_SYS_BOOT_GET_CMDLINE:
@@ -1623,13 +1587,6 @@
 - CONFIG_SYS_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.
 
-- CONFIG_NS16550_MIN_FUNCTIONS:
-		Define this if you desire to only have use of the NS16550_init
-		and NS16550_putc functions for the serial driver located at
-		drivers/serial/ns16550.c.  This option is useful for saving
-		space for already greatly restricted images, including but not
-		limited to NAND_SPL configurations.
-
 - CONFIG_DISPLAY_BOARDINFO
 		Display information about the board that U-Boot is running on
 		when U-Boot starts up. The board function checkboard() is called
@@ -1650,11 +1607,11 @@
 		Default (power-on reset) physical address of CCSR on Freescale
 		PowerPC SOCs.
 
-- CONFIG_SYS_CCSRBAR:
+- CFG_SYS_CCSRBAR:
 		Virtual address of CCSR.  On a 32-bit build, this is typically
 		the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
 
-- CONFIG_SYS_CCSRBAR_PHYS:
+- CFG_SYS_CCSRBAR_PHYS:
 		Physical address of CCSR.  CCSR can be relocated to a new
 		physical address, if desired.  In this case, this macro should
 		be set to that address.	 Otherwise, it should be set to the
@@ -1662,17 +1619,17 @@
 		is typically relocated on 36-bit builds.  It is recommended
 		that this macro be defined via the _HIGH and _LOW macros:
 
-		#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
-			* 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
+		#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH
+			* 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
 
-- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
-		Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS.	This value is typically
+- CFG_SYS_CCSRBAR_PHYS_HIGH:
+		Bits 33-36 of CFG_SYS_CCSRBAR_PHYS.	This value is typically
 		either 0 (32-bit build) or 0xF (36-bit build).	This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 
-- CONFIG_SYS_CCSRBAR_PHYS_LOW:
-		Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS.  This macro is
+- CFG_SYS_CCSRBAR_PHYS_LOW:
+		Lower 32-bits of CFG_SYS_CCSRBAR_PHYS.  This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 
@@ -1680,7 +1637,7 @@
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx systems only]
 
-- CONFIG_SYS_INIT_RAM_ADDR:
+- CFG_SYS_INIT_RAM_ADDR:
 
 		Start address of memory area that can be used for
 		initial data and stack; please note that this must be
@@ -1698,18 +1655,6 @@
 - CONFIG_SYS_OR_TIMING_SDRAM:
 		SDRAM timing
 
-- CONFIG_SYS_SRIO:
-		Chip has SRIO or not
-
-- CONFIG_SRIO1:
-		Board has SRIO 1 port available
-
-- CONFIG_SRIO2:
-		Board has SRIO 2 port available
-
-- CONFIG_SRIO_PCIE_BOOT_MASTER
-		Board can support master function for Boot from SRIO and PCIE
-
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region
 
@@ -1731,13 +1676,6 @@
 		Sets the EBC0_CFG register for the NDFC. If not defined
 		a default value will be used.
 
-- CONFIG_SPD_EEPROM
-		Get DDR timing information from an I2C EEPROM. Common
-		with pluggable memory modules such as SODIMMs
-
-  SPD_EEPROM_ADDRESS
-		I2C address of the SPD EEPROM
-
 - CONFIG_SYS_SPD_BUS_NUM
 		If SPD EEPROM is on an I2C bus other than the first
 		one, specify here. Note that the value must resolve
@@ -1810,11 +1748,6 @@
 		If defined, the x86 reset vector code is included. This is not
 		needed when U-Boot is running from Coreboot.
 
-- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
-		Option to disable subpage write in NAND driver
-		driver that uses this:
-		drivers/mtd/nand/raw/davinci_nand.c
-
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 
@@ -2766,7 +2699,7 @@
 	cause you grief during the initial boot! It is frequently not
 	used.
 
-	CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
+	CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
 	with your processor/board/system design. The default value
 	you will find in any recent u-boot distribution in
 	walnut.h should work for you. I'd set it to a value larger

diff --git a/arch/Kconfig b/arch/Kconfig
index ae39716..51d46a4 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig

@@ -146,6 +146,7 @@
 	select DM_SPI
 	select DM_SPI_FLASH
 	select GZIP_COMPRESSED
+	select IO_TRACE
 	select LZO
 	select OF_BOARD_SETUP
 	select PCI_ENDPOINT

diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 8c5a6f6..805fe93 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp

@@ -251,3 +251,6 @@
 config HAS_FSL_DR_USB
 	def_bool y
 	depends on USB_EHCI_HCD && PPC
+
+config SYS_DPAA_FMAN
+	bool

diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 4c696cb..d97a578 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c

@@ -476,9 +476,9 @@
 static void arc_ioc_setup(void)
 {
 	/* IOC Aperture start is equal to DDR start */
-	unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+	unsigned int ap_base = CFG_SYS_SDRAM_BASE;
 	/* IOC Aperture size is equal to DDR size */
-	long ap_size = CONFIG_SYS_SDRAM_SIZE;
+	long ap_size = CFG_SYS_SDRAM_SIZE;
 
 	/* Unsupported configuration. See [ NOTE 2 ] for more details. */
 	if (!slc_exists())

diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index 6b21520..1567857 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c

@@ -20,7 +20,7 @@
 	timer_init();
 
 	gd->cpu_clk = get_board_sys_clk();
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 
 	cache_init();
 

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3f68d09..fb696ab 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig

@@ -1245,6 +1245,7 @@
 	bool "Freescale Vybrid"
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
+	select IOMUX_SHARE_CONF_REG
 	select MACH_IMX
 	select SYS_FSL_ERRATUM_ESDHC111
 	imply CMD_MTDPARTS
@@ -2341,6 +2342,7 @@
 source "board/isee/igep003x/Kconfig"
 source "board/kontron/sl28/Kconfig"
 source "board/myir/mys_6ulx/Kconfig"
+source "board/samsung/common/Kconfig"
 source "board/siemens/common/Kconfig"
 source "board/seeed/npi_imx6ull/Kconfig"
 source "board/socionext/developerbox/Kconfig"

diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 5a15365..9e76a4a 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S

@@ -18,7 +18,7 @@
 #include <linux/linkage.h>
 
 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
+#define CONFIG_SYS_PHY_UBOOT_BASE	CFG_SYS_UBOOT_BASE
 #endif
 
 /*

diff --git a/arch/arm/cpu/arm920t/imx/Makefile b/arch/arm/cpu/arm920t/imx/Makefile
deleted file mode 100644
index 04bc129..0000000
--- a/arch/arm/cpu/arm920t/imx/Makefile
+++ /dev/null

@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= generic.o
-obj-y	+= speed.o
-obj-y	+= timer.o

diff --git a/arch/arm/cpu/arm920t/imx/generic.c b/arch/arm/cpu/arm920t/imx/generic.c
deleted file mode 100644
index dbb908e..0000000
--- a/arch/arm/cpu/arm920t/imx/generic.c
+++ /dev/null

@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  arch/arm/mach-imx/generic.c
- *
- *  author: Sascha Hauer
- *  Created: april 20th, 2004
- *  Copyright: Synertronixx GmbH
- *
- *  Common code for i.MX machines
- */
-
-#include <common.h>
-
-#ifdef CONFIG_IMX
-
-#include <asm/arch/imx-regs.h>
-
-void imx_gpio_mode(int gpio_mode)
-{
-	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
-	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
-	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
-	unsigned int tmp;
-
-	/* Pullup enable */
-	if(gpio_mode & GPIO_PUEN)
-		PUEN(port) |= (1<<pin);
-	else
-		PUEN(port) &= ~(1<<pin);
-
-	/* Data direction */
-	if(gpio_mode & GPIO_OUT)
-		DDIR(port) |= 1<<pin;
-	else
-		DDIR(port) &= ~(1<<pin);
-
-	/* Primary / alternate function */
-	if(gpio_mode & GPIO_AF)
-		GPR(port) |= (1<<pin);
-	else
-		GPR(port) &= ~(1<<pin);
-
-	/* use as gpio? */
-	if( ocr == 3 )
-		GIUS(port) |= (1<<pin);
-	else
-		GIUS(port) &= ~(1<<pin);
-
-	/* Output / input configuration */
-	/* FIXME: I'm not very sure about OCR and ICONF, someone
-	 * should have a look over it
-	 */
-	if(pin<16) {
-		tmp = OCR1(port);
-		tmp &= ~( 3<<(pin*2));
-		tmp |= (ocr << (pin*2));
-		OCR1(port) = tmp;
-
-		if( gpio_mode &	GPIO_AOUT )
-			ICONFA1(port) &= ~( 3<<(pin*2));
-		if( gpio_mode &	GPIO_BOUT )
-			ICONFB1(port) &= ~( 3<<(pin*2));
-	} else {
-		tmp = OCR2(port);
-		tmp &= ~( 3<<((pin-16)*2));
-		tmp |= (ocr << ((pin-16)*2));
-		OCR2(port) = tmp;
-
-		if( gpio_mode &	GPIO_AOUT )
-			ICONFA2(port) &= ~( 3<<((pin-16)*2));
-		if( gpio_mode &	GPIO_BOUT )
-			ICONFB2(port) &= ~( 3<<((pin-16)*2));
-	}
-}
-
-#endif /* CONFIG_IMX */

diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
deleted file mode 100644
index c19206a..0000000
--- a/arch/arm/cpu/arm920t/imx/speed.c
+++ /dev/null

@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- */
-
-
-#include <common.h>
-#if defined (CONFIG_IMX)
-#include <clock_legacy.h>
-
-#include <asm/arch/imx-regs.h>
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * get_board_sys_clk() should be defined as the input frequency of the PLL.
- * SH FIXME: 16780000 in our case
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-ulong get_systemPLLCLK(void)
-{
-	/* FIXME: We assume System_SEL = 0 here */
-	u32 spctl0 = SPCTL0;
-	u32 mfi = (spctl0 >> 10) & 0xf;
-	u32 mfn = spctl0 & 0x3f;
-	u32 mfd = (spctl0 >> 16) & 0x3f;
-	u32 pd =  (spctl0 >> 26) & 0xf;
-
-	mfi = mfi<=5 ? 5 : mfi;
-
-	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
-}
-
-ulong get_mcuPLLCLK(void)
-{
-	/* FIXME: We assume System_SEL = 0 here */
-	u32 mpctl0 = MPCTL0;
-	u32 mfi = (mpctl0 >> 10) & 0xf;
-	u32 mfn = mpctl0 & 0x3f;
-	u32 mfd = (mpctl0 >> 16) & 0x3f;
-	u32 pd =  (mpctl0 >> 26) & 0xf;
-
-	mfi = mfi<=5 ? 5 : mfi;
-
-	return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
-}
-
-ulong get_FCLK(void)
-{
-	return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
-	printf("bclkdiv: %d\n", bclkdiv);
-	return get_systemPLLCLK() / bclkdiv;
-}
-
-/* return BCLK frequency */
-ulong get_BCLK(void)
-{
-	return get_HCLK();
-}
-
-ulong get_PERCLK1(void)
-{
-	return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
-}
-
-ulong get_PERCLK2(void)
-{
-	return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
-}
-
-ulong get_PERCLK3(void)
-{
-	return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
-}
-
-#endif /* defined (CONFIG_IMX) */

diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c
deleted file mode 100644
index 0cd3a03..0000000
--- a/arch/arm/cpu/arm920t/imx/timer.c
+++ /dev/null

@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <time.h>
-#if defined (CONFIG_IMX)
-
-#include <asm/arch/imx-regs.h>
-#include <linux/delay.h>
-
-int timer_init (void)
-{
-	int i;
-	/* setup GP Timer 1 */
-	TCTL1 = TCTL_SWR;
-	for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
-	TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
-	TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
-
-	/* Reset the timer */
-	TCTL1 &= ~TCTL_TEN;
-	TCTL1 |= TCTL_TEN; /* Enable timer */
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-static ulong get_timer_masked (void)
-{
-	return TCN1;
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong endtime = get_timer_masked() + usec;
-	signed long diff;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out
- */
-void reset_cpu(void)
-{
-	/* Disable watchdog and set Time-Out field to 0 */
-	WCR = 0x00000000;
-
-	/* Write Service Sequence */
-	WSR = 0x00005555;
-	WSR = 0x0000AAAA;
-
-	/* Enable watchdog */
-	WCR = 0x00000001;
-
-	while (1);
-	/*NOTREACHED*/
-}
-
-#endif /* defined (CONFIG_IMX) */

diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 7f1436d..7e7ad4f 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile

@@ -12,7 +12,6 @@
 endif
 endif
 
-obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/

diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile
deleted file mode 100644
index ac5ebaf..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ /dev/null

@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-
-obj-y	+= generic.o timer.o reset.o relocate.o

diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c
deleted file mode 100644
index 8b9d3a2..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ /dev/null

@@ -1,378 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <div64.h>
-#include <net.h>
-#include <netdev.h>
-#include <vsprintf.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/mach-imx/sys_proto.h>
-#ifdef CONFIG_MMC_MXC
-#include <asm/arch/mxcmmc.h>
-#endif
-
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
-{
-	unsigned int mfi = (pll >> 10) & 0xf;
-	unsigned int mfn = pll & 0x3ff;
-	unsigned int mfd = (pll >> 16) & 0x3ff;
-	unsigned int pd =  (pll >> 26) & 0xf;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-
-	return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
-			(mfd + 1) * (pd + 1));
-}
-
-static ulong clk_in_32k(void)
-{
-	return 1024 * CONFIG_MX27_CLK32;
-}
-
-static ulong clk_in_26m(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
-		/* divide by 1.5 */
-		return 26000000 * 2 / 3;
-	} else {
-		return 26000000;
-	}
-}
-
-static ulong imx_get_mpllclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref;
-
-	if (cscr & CSCR_MCU_SEL)
-		fref = clk_in_26m();
-	else
-		fref = clk_in_32k();
-
-	return imx_decode_pll(readl(&pll->mpctl0), fref);
-}
-
-static ulong imx_get_armclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref = imx_get_mpllclk();
-	ulong div;
-
-	if (!(cscr & CSCR_ARM_SRC_MPLL))
-		fref = lldiv((fref * 2), 3);
-
-	div = ((cscr >> 12) & 0x3) + 1;
-
-	return lldiv(fref, div);
-}
-
-static ulong imx_get_ahbclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref = imx_get_mpllclk();
-	ulong div;
-
-	div = ((cscr >> 8) & 0x3) + 1;
-
-	return lldiv(fref * 2, 3 * div);
-}
-
-static __attribute__((unused)) ulong imx_get_spllclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref;
-
-	if (cscr & CSCR_SP_SEL)
-		fref = clk_in_26m();
-	else
-		fref = clk_in_32k();
-
-	return imx_decode_pll(readl(&pll->spctl0), fref);
-}
-
-static ulong imx_decode_perclk(ulong div)
-{
-	return lldiv((imx_get_mpllclk() * 2), (div * 3));
-}
-
-static ulong imx_get_perclk1(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
-}
-
-static ulong imx_get_perclk2(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
-}
-
-static __attribute__((unused)) ulong imx_get_perclk3(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
-}
-
-static __attribute__((unused)) ulong imx_get_perclk4(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-	switch (clk) {
-	case MXC_ARM_CLK:
-		return imx_get_armclk();
-	case MXC_I2C_CLK:
-		return imx_get_ahbclk()/2;
-	case MXC_UART_CLK:
-		return imx_get_perclk1();
-	case MXC_FEC_CLK:
-		return imx_get_ahbclk();
-	case MXC_ESDHC_CLK:
-		return imx_get_perclk2();
-	}
-	return -1;
-}
-
-
-u32 get_cpu_rev(void)
-{
-	return MXC_CPU_MX27 << 12;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	char buf[32];
-
-	printf("CPU:   Freescale i.MX27 at %s MHz\n\n",
-			strmhz(buf, imx_get_mpllclk()));
-	return 0;
-}
-#endif
-
-int cpu_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FEC_MXC)
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	/* enable FEC clock */
-	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
-	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
-	return fecmxc_initialize(bis);
-#else
-	return 0;
-#endif
-}
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(struct bd_info *bis)
-{
-#ifdef CONFIG_MMC_MXC
-	return mxc_mmc_init(bis);
-#else
-	return 0;
-#endif
-}
-
-void imx_gpio_mode(int gpio_mode)
-{
-	struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
-	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
-	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
-	unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
-	unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
-	unsigned int tmp;
-
-	/* Pullup enable */
-	if (gpio_mode & GPIO_PUEN) {
-		writel(readl(&regs->port[port].puen) | (1 << pin),
-				&regs->port[port].puen);
-	} else {
-		writel(readl(&regs->port[port].puen) & ~(1 << pin),
-				&regs->port[port].puen);
-	}
-
-	/* Data direction */
-	if (gpio_mode & GPIO_OUT) {
-		writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
-				&regs->port[port].gpio_dir);
-	} else {
-		writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
-				&regs->port[port].gpio_dir);
-	}
-
-	/* Primary / alternate function */
-	if (gpio_mode & GPIO_AF) {
-		writel(readl(&regs->port[port].gpr) | (1 << pin),
-				&regs->port[port].gpr);
-	} else {
-		writel(readl(&regs->port[port].gpr) & ~(1 << pin),
-				&regs->port[port].gpr);
-	}
-
-	/* use as gpio? */
-	if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
-		writel(readl(&regs->port[port].gius) | (1 << pin),
-				&regs->port[port].gius);
-	} else {
-		writel(readl(&regs->port[port].gius) & ~(1 << pin),
-				&regs->port[port].gius);
-	}
-
-	/* Output / input configuration */
-	if (pin < 16) {
-		tmp = readl(&regs->port[port].ocr1);
-		tmp &= ~(3 << (pin * 2));
-		tmp |= (ocr << (pin * 2));
-		writel(tmp, &regs->port[port].ocr1);
-
-		writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfa1);
-		writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
-				&regs->port[port].iconfa1);
-		writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfb1);
-		writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
-				&regs->port[port].iconfb1);
-	} else {
-		pin -= 16;
-
-		tmp = readl(&regs->port[port].ocr2);
-		tmp &= ~(3 << (pin * 2));
-		tmp |= (ocr << (pin * 2));
-		writel(tmp, &regs->port[port].ocr2);
-
-		writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfa2);
-		writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
-				&regs->port[port].iconfa2);
-		writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfb2);
-		writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
-				&regs->port[port].iconfb2);
-	}
-}
-
-#ifdef CONFIG_MXC_UART
-void mx27_uart1_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PE12_PF_UART1_TXD,
-		PE13_PF_UART1_RXD,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-#endif /* CONFIG_MXC_UART */
-
-#ifdef CONFIG_FEC_MXC
-void mx27_fec_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PD0_AIN_FEC_TXD0,
-		PD1_AIN_FEC_TXD1,
-		PD2_AIN_FEC_TXD2,
-		PD3_AIN_FEC_TXD3,
-		PD4_AOUT_FEC_RX_ER,
-		PD5_AOUT_FEC_RXD1,
-		PD6_AOUT_FEC_RXD2,
-		PD7_AOUT_FEC_RXD3,
-		PD8_AF_FEC_MDIO,
-		PD9_AIN_FEC_MDC | GPIO_PUEN,
-		PD10_AOUT_FEC_CRS,
-		PD11_AOUT_FEC_TX_CLK,
-		PD12_AOUT_FEC_RXD0,
-		PD13_AOUT_FEC_RX_DV,
-		PD14_AOUT_FEC_CLR,
-		PD15_AOUT_FEC_COL,
-		PD16_AIN_FEC_TX_ER,
-		PF23_AIN_FEC_TX_EN,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-}
-
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-	int i;
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[0];
-	struct fuse_bank0_regs *fuse =
-			(struct fuse_bank0_regs *)bank->fuse_regs;
-
-	for (i = 0; i < 6; i++)
-		mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif /* CONFIG_FEC_MXC */
-
-#ifdef CONFIG_MMC_MXC
-void mx27_sd1_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PE18_PF_SD1_D0,
-		PE19_PF_SD1_D1,
-		PE20_PF_SD1_D2,
-		PE21_PF_SD1_D3,
-		PE22_PF_SD1_CMD,
-		PE23_PF_SD1_CLK,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-
-void mx27_sd2_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PB4_PF_SD2_D0,
-		PB5_PF_SD2_D1,
-		PB6_PF_SD2_D2,
-		PB7_PF_SD2_D3,
-		PB8_PF_SD2_CMD,
-		PB9_PF_SD2_CLK,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-#endif /* CONFIG_MMC_MXC */

diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S
deleted file mode 100644
index 5dfa272..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/relocate.S
+++ /dev/null

@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  relocate - i.MX27-specific vector relocation
- *
- *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <linux/linkage.h>
-
-/*
- * The i.MX27 SoC is very specific with respect to exceptions: it
- * does not provide RAM at the high vectors address (0xFFFF0000),
- * thus only the low address (0x00000000) is useable; but that is
- * in ROM. Therefore, vectors cannot be changed at all.
- *
- * However, these ROM-based vectors actually just perform indirect
- * calls through pointers located in RAM at SoC-specific addresses,
- * as follows:
- *
- * Offset      Exception              Use by ROM code
- * 0x00000000  reset                  indirect branch to [0x00000014]
- * 0x00000004  undefined instruction  indirect branch to [0xfffffef0]
- * 0x00000008  software interrupt     indirect branch to [0xfffffef4]
- * 0x0000000c  prefetch abort         indirect branch to [0xfffffef8]
- * 0x00000010  data abort             indirect branch to [0xfffffefc]
- * 0x00000014  (reserved in ARMv5)    vector to ROM reset: 0xc0000000
- * 0x00000018  IRQ                    indirect branch to [0xffffff00]
- * 0x0000001c  FIQ                    indirect branch to [0xffffff04]
- *
- * In order to initialize exceptions on i.MX27, we must copy U-Boot's
- * indirect (not exception!) vector table into 0xfffffef0..0xffffff04
- * taking care not to copy vectors number 5 (reserved exception).
- */
-
-	.section	.text.relocate_vectors,"ax",%progbits
-
-ENTRY(relocate_vectors)
-
-	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
-	ldr	r1, =32			/* size of vector table */
-	add	r0, r0, r1		/* skip to indirect table */
-	ldr	r1, =0xFFFFFEF0		/* i.MX27 indirect table */
-	ldmia	r0!, {r2-r8}		/* load indirect vectors 1..7 */
-	stmia	r1!, {r2-r5, r7,r8}	/* write all but vector 5 */
-
-	bx	lr
-
-ENDPROC(relocate_vectors)

diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c
deleted file mode 100644
index 496fb30..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/reset.c
+++ /dev/null

@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void reset_cpu(void)
-{
-	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
-	/* Disable watchdog and set Time-Out field to 0 */
-	writew(0x0000, &regs->wcr);
-
-	/* Write Service Sequence */
-	writew(0x5555, &regs->wsr);
-	writew(0xAAAA, &regs->wsr);
-
-	/* Enable watchdog */
-	writew(WCR_WDE, &regs->wcr);
-
-	while (1);
-	/*NOTREACHED*/
-}

diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c
deleted file mode 100644
index 4fd6a80..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/timer.c
+++ /dev/null

@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <div64.h>
-#include <init.h>
-#include <time.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/ptrace.h>
-#include <linux/delay.h>
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
-#define GPTCR_FRR		(1 << 8)	/* Freerun / restart	*/
-#define GPTCR_CLKSOURCE_32	(4 << 1)	/* Clock source		*/
-#define GPTCR_TEN		1		/* Timer enable		*/
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp	(gd->arch.tbl)
-#define lastinc		(gd->arch.lastinc)
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX27_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_MX27_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_MX27_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
-		CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX27_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32768Hz 32-bit timer overruns in 131072 seconds */
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	/* setup GP Timer 1 */
-	writel(GPTCR_SWR, &regs->gpt_tctl);
-
-	writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
-	writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
-
-	for (i = 0; i < 100; i++)
-		writel(0, &regs->gpt_tctl); /* We have no udelay by now */
-	writel(0, &regs->gpt_tprer); /* 32Khz */
-	/* Freerun Mode, PERCLK1 input */
-	writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
-			&regs->gpt_tctl);
-	writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
-
-	return 0;
-}
-
-unsigned long long get_ticks(void)
-{
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	ulong now = readl(&regs->gpt_tcn); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-static ulong get_timer_masked(void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-ulong get_tbclk(void)
-{
-	return CONFIG_MX27_CLK32;
-}

diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index aca7793..c882bd3 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S

@@ -95,7 +95,7 @@
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
 	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
 #else
 	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */

diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index d96406f..17bd53d 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c

@@ -14,7 +14,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_HZ_CLOCK
+#ifndef CFG_SYS_HZ_CLOCK
 static inline u32 read_cntfrq(void)
 {
 	u32 frq;
@@ -29,8 +29,8 @@
 	gd->arch.tbl = 0;
 	gd->arch.tbu = 0;
 
-#ifdef CONFIG_SYS_HZ_CLOCK
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#ifdef CFG_SYS_HZ_CLOCK
+	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
 #else
 	gd->arch.timer_rate_hz = read_cntfrq();
 #endif

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index e75a895..7e138e0 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -1,6 +1,8 @@
 config ARCH_LS1021A
 	bool
+	select FSL_DEVICE_DISABLE
 	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
+	select LS102XA_STREAM_ID
 	select SYS_FSL_DDR_BE if SYS_FSL_DDR
 	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
 	select SYS_FSL_IFC_BE
@@ -30,9 +32,15 @@
 menu "LS102xA architecture"
 	depends on ARCH_LS1021A
 
+config FSL_DEVICE_DISABLE
+	bool
+
 config LS1_DEEP_SLEEP
 	bool "Deep sleep"
 
+config LS102XA_STREAM_ID
+	bool
+
 config MAX_CPUS
 	int "Maximum number of CPUs permitted for LS102xA"
 	default 2

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d530e06..25e4b49 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c

@@ -168,18 +168,18 @@
 	/* Level 1 has 512 entries */
 	for (i = 0; i < 512; i++) {
 		/* Mapping for PCIe 1 */
-		if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
-		    va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
-				 CONFIG_SYS_PCIE_MMAP_SIZE))
+		if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR &&
+		    va_start < (CFG_SYS_PCIE1_VIRT_ADDR +
+				 CFG_SYS_PCIE_MMAP_SIZE))
 			set_pgsection(level1_table, i,
-				      CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+				      CFG_SYS_PCIE1_PHYS_BASE + va_start,
 				      MT_DEVICE_MEM);
 		/* Mapping for PCIe 2 */
-		else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
-			 va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
-				     CONFIG_SYS_PCIE_MMAP_SIZE))
+		else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR &&
+			 va_start < (CFG_SYS_PCIE2_VIRT_ADDR +
+				     CFG_SYS_PCIE_MMAP_SIZE))
 			set_pgsection(level1_table, i,
-				      CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+				      CFG_SYS_PCIE2_PHYS_BASE + va_start,
 				      MT_DEVICE_MEM);
 		else
 			set_pgsection(level1_table, i,
@@ -313,9 +313,9 @@
 
 int arch_cpu_init(void)
 {
-	void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *rcpm2_base =
-		(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+		(void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
 	struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	u32 state;
 

diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index c01cebb..599b7e1 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c

@@ -125,7 +125,7 @@
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
-			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+			       "clock-frequency", CFG_SYS_NS16550_CLK, 1);
 #endif
 
 	sysclk_path = fdt_get_alias(blob, "sysclk");
@@ -183,7 +183,7 @@
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
-					    CONFIG_SYS_IFC_ADDR);
+					    CFG_SYS_IFC_ADDR);
 	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 #else
 	off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,

diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index b4d113d..dbb0766 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -29,7 +29,7 @@
  */
 static void __secure ls1_save_ddr_head(void)
 {
-	const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+	const char *src = (const char *)CFG_SYS_SDRAM_BASE;
 	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
 	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	int i;
@@ -42,7 +42,7 @@
 
 static void __secure ls1_fsm_setup(void)
 {
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
 
 	out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@@ -118,7 +118,7 @@
 
 static void __secure ls1_start_fsm(void)
 {
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
 	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;

diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c
index 67764cc..f7cc457 100644
--- a/arch/arm/cpu/armv7/stv0991/timer.c
+++ b/arch/arm/cpu/armv7/stv0991/timer.c

@@ -18,7 +18,7 @@
 				(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
 
 #define READ_TIMER()	(readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define GPT_RESOLUTION	(CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,7 +67,7 @@
 {
 	ulong tmo;
 	ulong start = get_timer_masked();
-	ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
+	ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
 	ulong rndoff;
 
 	rndoff = (usec % 10) ? 1 : 0;

diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c
index 556eaf8..c30af4f 100644
--- a/arch/arm/cpu/armv7m/systick-timer.c
+++ b/arch/arm/cpu/armv7m/systick-timer.c

@@ -18,7 +18,7 @@
  * The number of reference clock ticks that correspond to 10ms is normally
  * defined in the SysTick Calibration register's TENMS field. However, on some
  * devices this is wrong, so this driver allows the clock rate to be defined
- * using CONFIG_SYS_HZ_CLOCK.
+ * using CFG_SYS_HZ_CLOCK.
  */
 
 #include <common.h>
@@ -76,10 +76,10 @@
 
 	/*
 	 * If the TENMS field is inexact or wrong, specify the clock rate using
-	 * CONFIG_SYS_HZ_CLOCK.
+	 * CFG_SYS_HZ_CLOCK.
 	 */
-#if defined(CONFIG_SYS_HZ_CLOCK)
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#if defined(CFG_SYS_HZ_CLOCK)
+	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
 #else
 	gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
 #endif

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ebca11d..2862257 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -69,6 +69,7 @@
 	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select SKIP_LOWLEVEL_INIT
+	select SYS_DPAA_FMAN
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -106,6 +107,7 @@
 	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select SKIP_LOWLEVEL_INIT
+	select SYS_DPAA_FMAN
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c11341a..99413ef 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -114,7 +114,7 @@
 	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
-	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+	{ CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 	  CONFIG_SYS_FSL_IFC_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
@@ -130,9 +130,9 @@
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 #ifdef CONFIG_FSL_IFC
-	/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+	/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-	  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+	  CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
 #endif
@@ -257,26 +257,26 @@
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE,
+	{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+	  CFG_SYS_PCIE1_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE,
+	{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+	  CFG_SYS_PCIE2_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+	{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+	  CFG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #endif
-#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-	  CONFIG_SYS_PCIE4_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+	{ CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR,
+	  CFG_SYS_PCIE4_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -368,19 +368,19 @@
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE,
+	{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+	  CFG_SYS_PCIE1_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE,
+	{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+	  CFG_SYS_PCIE2_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+	{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+	  CFG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -391,7 +391,7 @@
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 #endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	{},	/* space holder for secure mem */
 #endif
 	{},
@@ -445,7 +445,7 @@
 	if (el == 3)
 		gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
 	else
-		gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
+		gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
 	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 	gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 
@@ -477,25 +477,25 @@
 	    (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 		for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 			switch (final_map[i].phys) {
-			case CONFIG_SYS_PCIE1_PHYS_ADDR:
+			case CFG_SYS_PCIE1_PHYS_ADDR:
 				final_map[i].phys = 0x2000000000ULL;
 				final_map[i].virt = 0x2000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
-			case CONFIG_SYS_PCIE2_PHYS_ADDR:
+			case CFG_SYS_PCIE2_PHYS_ADDR:
 				final_map[i].phys = 0x2800000000ULL;
 				final_map[i].virt = 0x2800000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-			case CONFIG_SYS_PCIE3_PHYS_ADDR:
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+			case CFG_SYS_PCIE3_PHYS_ADDR:
 				final_map[i].phys = 0x3000000000ULL;
 				final_map[i].virt = 0x3000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
 #endif
-#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-			case CONFIG_SYS_PCIE4_PHYS_ADDR:
+#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+			case CFG_SYS_PCIE4_PHYS_ADDR:
 				final_map[i].phys = 0x3800000000ULL;
 				final_map[i].virt = 0x3800000000ULL;
 				final_map[i].size = 0x800000000ULL;
@@ -568,7 +568,7 @@
 		}
 	}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		if (el == 3) {
 			/*
@@ -580,7 +580,7 @@
 			gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 			final_map[index].virt = gd->arch.secure_ram & ~0x3;
 			final_map[index].phys = final_map[index].virt;
-			final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
+			final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
 			final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 			gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 			tlb_addr_save = gd->arch.tlb_addr;
@@ -1323,10 +1323,10 @@
 		ea_size = gd->ram_size;
 	}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	/* Check if we have enough space for secure memory */
-	if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
-		ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+	if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
+		ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
 	else
 		printf("Error: No enough space for secure memory.\n");
 #endif
@@ -1433,7 +1433,7 @@
 	 * gd->arch.secure_ram should be done to avoid running it repeatedly.
 	 */
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		debug("No need to run again, skip %s\n", __func__);
 
@@ -1441,12 +1441,12 @@
 	}
 #endif
 
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
 		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_DDR_BLOCK1_SIZE;
+					  CFG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 		if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
@@ -1458,17 +1458,17 @@
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 	}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->bd->bi_dram[0].size >
-				CONFIG_SYS_MEM_RESERVE_SECURE) {
+				CFG_SYS_MEM_RESERVE_SECURE) {
 		gd->bd->bi_dram[0].size -=
-				CONFIG_SYS_MEM_RESERVE_SECURE;
+				CFG_SYS_MEM_RESERVE_SECURE;
 		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 				      gd->bd->bi_dram[0].size;
 		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-		gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+		gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
 	}
-#endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
+#endif	/* CFG_SYS_MEM_RESERVE_SECURE */
 
 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
@@ -1520,7 +1520,7 @@
 	}
 #endif
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	debug("%s is called. gd->ram_size is reduced to %lu\n",
 	      __func__, (ulong)gd->ram_size);
 #endif
@@ -1571,7 +1571,7 @@
 
 	if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
 		mmu_change_region_attr(
-					CONFIG_SYS_SDRAM_BASE,
+					CFG_SYS_SDRAM_BASE,
 					gd->ram_size,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1579,8 +1579,8 @@
 					PTE_TYPE_VALID);
 	} else {
 		mmu_change_region_attr(
-					CONFIG_SYS_SDRAM_BASE,
-					CONFIG_SYS_DDR_BLOCK1_SIZE,
+					CFG_SYS_SDRAM_BASE,
+					CFG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
@@ -1589,10 +1589,10 @@
 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
 #endif
-		if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
+		if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
 		    CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			mmu_change_region_attr(
-					CONFIG_SYS_DDR_BLOCK2_BASE,
+					CFG_SYS_DDR_BLOCK2_BASE,
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1601,7 +1601,7 @@
 			mmu_change_region_attr(
 					CONFIG_SYS_DDR_BLOCK3_BASE,
 					gd->ram_size -
-					CONFIG_SYS_DDR_BLOCK1_SIZE -
+					CFG_SYS_DDR_BLOCK1_SIZE -
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1611,9 +1611,9 @@
 #endif
 		{
 			mmu_change_region_attr(
-					CONFIG_SYS_DDR_BLOCK2_BASE,
+					CFG_SYS_DDR_BLOCK2_BASE,
 					gd->ram_size -
-					CONFIG_SYS_DDR_BLOCK1_SIZE,
+					CFG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index 9119d60..6f3fe7c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3

@@ -116,10 +116,10 @@
 Environment Variables
 =====================
 mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
-		the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+		the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
 
 mcmemsize:	MC DRAM block size in hex. If this variable is not defined, the value
-		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+		CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
 
 mcinitcmd:	This environment variable is defined to initiate MC and DPL deployment
 		from the location where it is stored(NOR, NAND, SD, SATA, USB)during

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index ee73457..4f91db4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -646,7 +646,7 @@
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "fsl,ns16550",
-			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+			       "clock-frequency", CFG_SYS_NS16550_CLK, 1);
 #endif
 
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 6440ce7..f18407b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -24,11 +24,7 @@
 /* rcw_tmp is needed to get FMAN clock, or to get cluster group A
  * mux 2 clock for LS1043A/LS1046A.
  */
-#if defined(CONFIG_SYS_DPAA_FMAN) || \
-	    defined(CONFIG_ARCH_LS1046A) || \
-	    defined(CONFIG_ARCH_LS1043A)
-	u32 rcw_tmp;
-#endif
+	__maybe_unused u32 rcw_tmp;
 	struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[8] = {
@@ -96,7 +92,7 @@
 
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
 	rcw_tmp = in_be32(&gur->rcwsr[7]);
 	switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
 	case 2:

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index e972603..ad20d71 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c

@@ -41,7 +41,7 @@
 	/* setup general icid offsets */
 	set_icid(icid_tbl, icid_tbl_sz);
 
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
 	set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
 #endif
 }

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
index 3bd993b..e3c3fc6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c

@@ -10,7 +10,7 @@
 #include <fsl_sec.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@@ -59,7 +59,7 @@
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
 
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
 struct fman_icid_id_table fman_icid_tbl[] = {
 	/* port id, icid */
 	SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index abd847b..333d7e2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c

@@ -9,7 +9,7 @@
 #include <asm/arch-fsl-layerscape/fsl_portals.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@@ -58,7 +58,7 @@
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
 
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
 struct fman_icid_id_table fman_icid_tbl[] = {
 	/* port id, icid */
 	SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 89a6262..359cbc0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -531,7 +531,7 @@
 
 	porsr1 = in_be32(&gur->porsr1);
 	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
-	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+	out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 		 porsr1);
 	out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
 #endif
@@ -643,8 +643,8 @@
 	out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
 		 | SCFG_RD_QOS1_PFE2_QOS));
 
-	ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
-	out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+	ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+	out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
 		 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
 }
 #endif

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 3a4b665..61fced4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -116,7 +116,7 @@
 #endif
 	dram_init();
 #ifdef CONFIG_SPL_FSL_LS_PPA
-#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifndef CFG_SYS_MEM_RESERVE_SECURE
 #error Need secure RAM for PPA
 #endif
 	/*

diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 540436b..c0e8726 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c

@@ -198,7 +198,7 @@
 		goto out;
 	}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	/*
 	 * The SEC Firmware must be stored in secure memory.
 	 * Append SEC Firmware to secure mmu table.
@@ -211,7 +211,7 @@
 	sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
 			gd->arch.tlb_size;
 #else
-#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
+#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
 #endif
 
 	/* Align SEC Firmware base address to 4K */

diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi
index 328ba90..d84c10c 100644
--- a/arch/arm/dts/rockchip-optee.dtsi
+++ b/arch/arm/dts/rockchip-optee.dtsi

@@ -32,8 +32,8 @@
 					arch = "arm";
 					os = "tee";
 					compression = "none";
-					load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
-					entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
+					load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+					entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
 
 					blob-ext {
 						filename = "tee.bin";

diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
index 327c0e0..fd8dad3 100644
--- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
+++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h

@@ -11,12 +11,8 @@
 /* uArchitecture specifics */
 
 /* Serial Info */
-/* Post pad 3 bytes after each reg addr */
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_MEM32
-
-#define CONFIG_SYS_NS16550_CLK		100000000
-#define CONFIG_SYS_NS16550_CLK_DIV	54
-#define CONFIG_SYS_NS16550_COM3		0x18023000
+#define CFG_SYS_NS16550_CLK		100000000
+#define CFG_SYS_NS16550_CLK_DIV	54
+#define CFG_SYS_NS16550_COM3		0x18023000
 
 #endif /* __ARCH_CONFIGS_H */

diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h
index 05fa9b9..0d4baf3 100644
--- a/arch/arm/include/asm/arch-bcmnsp/configs.h
+++ b/arch/arm/include/asm/arch-bcmnsp/configs.h

@@ -11,10 +11,7 @@
 /* uArchitecture specifics */
 
 /* Serial Info */
-/* no padding */
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-
-#define CONFIG_SYS_NS16550_CLK		0x03b9aca0
-#define CONFIG_SYS_NS16550_COM1		0x18000300
+#define CFG_SYS_NS16550_CLK		0x03b9aca0
+#define CFG_SYS_NS16550_COM1		0x18000300
 
 #endif /* __ARCH_CONFIGS_H */

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index ff752c2..c9c72e3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h

@@ -20,13 +20,13 @@
  * Reserve secure memory
  * To be aligned with MMU block size
  */
-#define CONFIG_SYS_MEM_RESERVE_SECURE	(66 * 1024 * 1024)	/* 66MB */
+#define CFG_SYS_MEM_RESERVE_SECURE	(66 * 1024 * 1024)	/* 66MB */
 #define SPL_TLB_SETBACK	0x1000000	/* 16MB under effective memory top */
 
 #ifdef CONFIG_ARCH_LS2080A
 #define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #define	SRDS_MAX_LANES	8
-#define CONFIG_SYS_PAGE_SIZE		0x10000
+#define CFG_SYS_PAGE_SIZE		0x10000
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT		6
 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
@@ -37,8 +37,8 @@
 #define CFG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE			0x06000000
@@ -96,7 +96,7 @@
 
 #elif defined(CONFIG_ARCH_LS1088A)
 #define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
-#define CONFIG_SYS_PAGE_SIZE		0x10000
+#define CFG_SYS_PAGE_SIZE		0x10000
 
 #define	SRDS_MAX_LANES	4
 #define	SRDS_BITS_PER_LANE	4
@@ -122,8 +122,8 @@
 #define SMMU_BASE			0x05000000 /* GR0 Base */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 /* DCFG - GUR */
 #define CFG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
@@ -141,15 +141,15 @@
 #endif
 #define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 1, 1, 4, 4, 4, 4 }
 
-#define CONFIG_SYS_PAGE_SIZE			0x10000
+#define CFG_SYS_PAGE_SIZE			0x10000
 
 #define CFG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
 #define CFG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE				0x06000000
@@ -192,8 +192,8 @@
 #define SMMU_BASE				0x05000000 /* GR0 Base */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 /* SEC */
 
@@ -209,11 +209,11 @@
 
 /* SoC related */
 #ifdef CONFIG_ARCH_LS1043A
-#define CONFIG_SYS_NUM_FMAN			1
-#define CONFIG_SYS_NUM_FM1_DTSEC		7
-#define CONFIG_SYS_NUM_FM1_10GEC		1
-#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_NUM_FMAN			1
+#define CFG_SYS_NUM_FM1_DTSEC		7
+#define CFG_SYS_NUM_FM1_10GEC		1
+#define CFG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CFG_SYS_DDR_BLOCK1_SIZE
 
 #define QE_MURAM_SIZE		0x6000UL
 #define MAX_QE_RISC		1
@@ -251,15 +251,15 @@
 #elif defined(CONFIG_ARCH_LS1012A)
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
-#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CFG_SYS_DDR_BLOCK1_SIZE
 
 #elif defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_SYS_NUM_FMAN			1
-#define CONFIG_SYS_NUM_FM1_DTSEC		8
-#define CONFIG_SYS_NUM_FM1_10GEC		2
-#define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_NUM_FMAN			1
+#define CFG_SYS_NUM_FM1_DTSEC		8
+#define CFG_SYS_NUM_FM1_10GEC		2
+#define CFG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED           CFG_SYS_DDR_BLOCK1_SIZE
 
 /* SMMU Defintions */
 #define SMMU_BASE		0x09000000

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 4db4791..20f9671 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h

@@ -35,17 +35,17 @@
 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
 #ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE1_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE2_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE3_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE4_PHYS_SIZE	0x200000000
 #else
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
-#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#ifndef CFG_SYS_PCIE3_PHYS_SIZE
+#define CFG_SYS_PCIE3_PHYS_SIZE	0x800000000
 #endif
-#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE4_PHYS_SIZE	0x800000000
 #define SYS_PCIE5_PHYS_SIZE		0x800000000
 #define SYS_PCIE6_PHYS_SIZE		0x800000000
 #endif
@@ -83,9 +83,9 @@
 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x10000000
 #define CONFIG_SYS_FSL_DRAM_BASE2	0x880000000
 #define CONFIG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE3_PHYS_SIZE	0x800000000
 #define CONFIG_SYS_FSL_DRAM_BASE3	0x8800000000
 #define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
 #endif

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 9cddb41..d5f63f4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h

@@ -75,7 +75,7 @@
 
 #define SET_USB_ICID(usb_num, compat, streamid) \
 	SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
-		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+		CFG_SYS_XHCI_USB##usb_num##_ADDR)
 
 #define SET_SATA_ICID(compat, streamid) \
 	SET_SCFG_ICID(compat, streamid, sata_icid,\
@@ -142,7 +142,7 @@
 
 #define SET_USB_ICID(usb_num, compat, streamid) \
 	SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
-		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+		CFG_SYS_XHCI_USB##usb_num##_ADDR)
 
 #define SET_SATA_ICID(sata_num, compat, streamid) \
 	SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index e8bd8d2..9794db0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h

@@ -11,11 +11,11 @@
 #include <linux/bitops.h>
 #endif
 
-#define CONFIG_SYS_DCSRBAR			0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00140000)
+#define CFG_SYS_DCSRBAR			0x20000000
+#define CFG_SYS_DCSR_DCFG_ADDR	(CFG_SYS_DCSRBAR + 0x00140000)
 
 #define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define CFG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x00550000)
 #define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
 #define CFG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
@@ -26,44 +26,41 @@
 #define CFG_SYS_FSL_QMAN_ADDR		(CONFIG_SYS_IMMR + 0x00880000)
 #define CFG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
 #define CFG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
-#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
-#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
-#define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
-#define CONFIG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
-#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
-#define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
+#define CFG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
+#define CFG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
+#define CFG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
+#define CFG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
+#define CFG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
+#define CFG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
+#define CFG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CFG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CFG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
+#define CFG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
 
-#define CONFIG_SYS_BMAN_NUM_PORTALS	10
-#define CONFIG_SYS_BMAN_MEM_BASE	0x508000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	(0xf00000000ull + \
-						CONFIG_SYS_BMAN_MEM_BASE)
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x08000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x10000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x10000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
-#define CONFIG_SYS_QMAN_NUM_PORTALS	10
-#define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x08000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x10000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x10000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0x3680
+#define CFG_SYS_BMAN_NUM_PORTALS	10
+#define CFG_SYS_BMAN_MEM_BASE	0x508000000
+#define CFG_SYS_BMAN_MEM_PHYS	(0xf00000000ull + \
+						CFG_SYS_BMAN_MEM_BASE)
+#define CFG_SYS_BMAN_MEM_SIZE	0x08000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE    0x10000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x10000
+#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG    0x3E80
+#define CFG_SYS_QMAN_NUM_PORTALS	10
+#define CFG_SYS_QMAN_MEM_BASE	0x500000000
+#define CFG_SYS_QMAN_MEM_PHYS	CFG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_SIZE	0x08000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x10000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0x3680
 
 #define CFG_SYS_FSL_TIMER_ADDR		0x02b00000
 
@@ -93,9 +90,9 @@
 #define QDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x07380000)
 #define QMAN_CQSIDR_REG				0x20a80
 
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
 /* LUT registers */
 #ifdef CONFIG_ARCH_LS1012A
 #define PCIE_LUT_BASE				0xC0000
@@ -137,20 +134,20 @@
 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 #define TP_INIT_PER_CLUSTER     4
 
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR		0x01000000
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR		0x01000000
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
+#define CFG_SYS_CCSRBAR_PHYS_HIGH	0
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	0x01000000
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW	0x01000000
 #endif
 
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
-				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CFG_SYS_CCSRBAR_PHYS_LOW)
 
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
@@ -160,7 +157,7 @@
 	unsigned long freq_localbus;
 	unsigned long freq_cga_m2;
 #ifdef CONFIG_SYS_DPAA_FMAN
-	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+	unsigned long freq_fman[CFG_SYS_NUM_FMAN];
 #endif
 	unsigned long freq_qman;
 };

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index f1ffb23..ca5e333 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

@@ -33,10 +33,10 @@
 #define FSL_ESDHC1_BASE_ADDR			CFG_SYS_FSL_ESDHC_ADDR
 #define FSL_ESDHC2_BASE_ADDR			(CONFIG_SYS_IMMR + 0x01150000)
 #ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
+#define CFG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
 #endif
-#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
-#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
+#define CFG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
+#define CFG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR	0x023d0000
 #define CFG_SYS_FSL_TIMER_ADDR		0x023e0000
 #define CFG_SYS_FSL_PMU_CLTBENR		(CFG_SYS_FSL_PMU_ADDR + \
@@ -67,8 +67,8 @@
 #define GPIO4_GPDIR_ADDR			(GPIO4_BASE_ADDR + 0x0)
 #define GPIO4_GPDAT_ADDR			(GPIO4_BASE_ADDR + 0x8)
 
-#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)
+#define CFG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)
 
 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */
@@ -105,7 +105,7 @@
 #define GPU_BASE_ADDR				(CONFIG_SYS_IMMR + 0x0e0c0000)
 
 /* SFP */
-#define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
+#define CFG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
 
 /* SEC */
 #define CFG_SYS_FSL_SEC_OFFSET		0x07000000ull
@@ -173,7 +173,7 @@
 #endif
 
 /* Security Monitor */
-#define CONFIG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)
+#define CFG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)
 
 /* MMU 500 */
 #define SMMU_SCR0			(SMMU_BASE + 0x0)
@@ -192,37 +192,35 @@
 
 
 /* PCIe */
-#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
-#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
+#define CFG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CFG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define SYS_PCIE5_ADDR				(CONFIG_SYS_IMMR + 0x2800000)
 #define SYS_PCIE6_ADDR				(CONFIG_SYS_IMMR + 0x2900000)
 #endif
 
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x9000000000ULL
-#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x9800000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x9000000000ULL
+#define CFG_SYS_PCIE4_PHYS_ADDR		0x9800000000ULL
 #define SYS_PCIE5_PHYS_ADDR			0xa000000000ULL
 #define SYS_PCIE6_PHYS_ADDR			0xa800000000ULL
 #elif CONFIG_ARCH_LS1088A
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x2000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x2800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x3000000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x2000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x2800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x3000000000ULL
 #elif CONFIG_ARCH_LS1028A
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x01f0000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x01f0000000ULL
 /* this is used by integrated PCI on LS1028, includes ECAM and register space */
-#define CONFIG_SYS_PCIE3_PHYS_SIZE		0x0010000000ULL
+#define CFG_SYS_PCIE3_PHYS_SIZE		0x0010000000ULL
 #else
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
-#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
+#define CFG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
 #endif
 
 /* Device Configuration */
@@ -306,7 +304,7 @@
 	unsigned long freq_localbus;
 	unsigned long freq_qe;
 #ifdef CONFIG_SYS_DPAA_FMAN
-	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+	unsigned long freq_fman[CFG_SYS_NUM_FMAN];
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	unsigned long freq_qman;

diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index dc414c7..4116038 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h

@@ -11,19 +11,11 @@
 
 /* Basic CPU architecture */
 
-/* UART configuration */
-#if	(CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \
-	(CONFIG_CONS_INDEX == 7)
-#if !defined(CONFIG_LPC32XX_HSUART)
-#define CONFIG_LPC32XX_HSUART
-#endif
-#endif
-
-#if !defined(CONFIG_SYS_NS16550_CLK)
-#define CONFIG_SYS_NS16550_CLK		13000000
+#if !defined(CFG_SYS_NS16550_CLK)
+#define CFG_SYS_NS16550_CLK		13000000
 #endif
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_BAUDRATE_TABLE	\
 		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
 
 /* NAND */
@@ -32,24 +24,24 @@
 #define NAND_SMALL_BLOCK_PAGE_SIZE	0x200
 
 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS		{ 10, 11, 12, 13, 14, 15, }
+#define CFG_SYS_NAND_ECCPOS		{ 10, 11, 12, 13, 14, 15, }
 #else
 #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
 #endif
 
-#define CONFIG_SYS_NAND_ECCSIZE		0x100
-#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCSIZE		0x100
+#define CFG_SYS_NAND_ECCBYTES	3
 #endif	/* CONFIG_NAND_LPC32XX_SLC */
 
 /* NOR Flash */
 
 /* USB OHCI */
 #if defined(CONFIG_USB_OHCI_LPC32XX)
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		USB_BASE
+#define CFG_SYS_USB_OHCI_REGS_BASE		USB_BASE
 #endif
 
 #endif /* _LPC32XX_CONFIG_H */

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index e85918e..6413a30 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h

@@ -11,36 +11,36 @@
 #define OCRAM_BASE_S_ADDR			0x10010000
 #define OCRAM_S_SIZE				0x00010000
 
-#define CONFIG_SYS_DCSRBAR			0x20000000
+#define CFG_SYS_DCSRBAR			0x20000000
 
-#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00220000)
-#define SYS_FSL_DCSR_RCPM_ADDR	(CONFIG_SYS_DCSRBAR + 0x00222000)
+#define CFG_SYS_DCSR_DCFG_ADDR	(CFG_SYS_DCSRBAR + 0x00220000)
+#define SYS_FSL_DCSR_RCPM_ADDR	(CFG_SYS_DCSRBAR + 0x00222000)
 
 #define SYS_FSL_GIC_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
 #define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CFG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define CFG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
 #define CFG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
 #define CFG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
 #define CFG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
-#define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0x00e90000)
-#define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0x00e80200)
+#define CFG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0x00e90000)
+#define CFG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0x00e80200)
 #define CFG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
 #define CFG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
 #define CFG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
 #define CFG_SYS_FSL_RCPM_ADDR		(CONFIG_SYS_IMMR + 0x00ee2000)
-#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
-#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
-#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CFG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
+#define CFG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
+#define CFG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
 
 #define CFG_SYS_FSL_SEC_OFFSET		0x00700000
 #define CFG_SYS_FSL_JR0_OFFSET		0x00710000
-#define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
-#define CONFIG_SYS_MDIO1_OFFSET			0x01d24000
+#define CFG_SYS_TSEC1_OFFSET			0x01d10000
+#define CFG_SYS_MDIO1_OFFSET			0x01d24000
 
-#define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR	(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 
 #define SCTR_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01b00000)
 
@@ -55,22 +55,22 @@
 
 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
 
-#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CFG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CFG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 
-#define CONFIG_SYS_PCIE1_PHYS_BASE		0x4000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_BASE		0x4800000000ULL
-#define CONFIG_SYS_PCIE1_VIRT_ADDR		0x24000000UL
-#define CONFIG_SYS_PCIE2_VIRT_ADDR		0x34000000UL
-#define CONFIG_SYS_PCIE_MMAP_SIZE		(192 * 1024 * 1024) /* 192M */
+#define CFG_SYS_PCIE1_PHYS_BASE		0x4000000000ULL
+#define CFG_SYS_PCIE2_PHYS_BASE		0x4800000000ULL
+#define CFG_SYS_PCIE1_VIRT_ADDR		0x24000000UL
+#define CFG_SYS_PCIE2_VIRT_ADDR		0x34000000UL
+#define CFG_SYS_PCIE_MMAP_SIZE		(192 * 1024 * 1024) /* 192M */
 /*
  * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
  * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
  */
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		(CONFIG_SYS_PCIE1_PHYS_BASE + \
-						 CONFIG_SYS_PCIE1_VIRT_ADDR)
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		(CONFIG_SYS_PCIE2_PHYS_BASE + \
-						 CONFIG_SYS_PCIE2_VIRT_ADDR)
+#define CFG_SYS_PCIE1_PHYS_ADDR		(CFG_SYS_PCIE1_PHYS_BASE + \
+						 CFG_SYS_PCIE1_VIRT_ADDR)
+#define CFG_SYS_PCIE2_PHYS_ADDR		(CFG_SYS_PCIE2_PHYS_BASE + \
+						 CFG_SYS_PCIE2_VIRT_ADDR)
 
 /* SATA */
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index b0acf67..a0c3da7 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

@@ -42,24 +42,24 @@
 
 #define DCFG_DCSR_PORCR1		0
 
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_IMMR
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR		CONFIG_SYS_IMMR
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#define CFG_SYS_CCSRBAR_PHYS_HIGH	0xf
 #else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#define CFG_SYS_CCSRBAR_PHYS_HIGH	0
 #endif
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
 #endif
 
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
-				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CFG_SYS_CCSRBAR_PHYS_LOW)
 
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];

diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index fb5ded8..acd8c69 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h

@@ -12,14 +12,14 @@
 	{ .compat = name, \
 	  .id = { idA }, .num_ids = 1, \
 	  .reg_offset = off + CONFIG_SYS_IMMR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
 	{ .compat = name, \
 	  .id = { idA, idB }, .num_ids = 2, \
 	  .reg_offset = off + CONFIG_SYS_IMMR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 /*

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index d5c0ed8..a0ab3a0 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h

@@ -899,9 +899,9 @@
  * Generic timer support
  */
 #ifdef CONFIG_MX31_CLK32
-#define	CONFIG_SYS_TIMER_RATE	CONFIG_MX31_CLK32
+#define	CFG_SYS_TIMER_RATE	CONFIG_MX31_CLK32
 #else
-#define	CONFIG_SYS_TIMER_RATE	32768
+#define	CFG_SYS_TIMER_RATE	32768
 #endif
 
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */

diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
index 5b12d90..eb1ddca 100644
--- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h

@@ -36,6 +36,6 @@
 #define GPT_FREE_RUNNING		0xFFFF
 
 /* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ_CLOCK		((27 * 1000 * 1000) / GPT_PRESCALER_128)
+#define CFG_SYS_HZ_CLOCK		((27 * 1000 * 1000) / GPT_PRESCALER_128)
 
 #endif

diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index 3525f22..241b449 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h

@@ -18,6 +18,6 @@
 #endif
 
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
-#define CONFIG_SYS_TCLK		24000000
+#define CFG_SYS_TCLK		24000000
 
 #endif

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 97211f4..fa3a978 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h

@@ -103,9 +103,6 @@
 
 #define QSPI0_AMBA_BASE		0x20000000
 
-/* MUX mode and PAD ctrl are in one register */
-#define CONFIG_IOMUX_SHARE_CONF_REG
-
 #define FEC_QUIRK_ENET_MAC
 #define I2C_QUIRK_REG
 

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 3542434..2141a45 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h

@@ -583,7 +583,7 @@
 	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
 	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
 	(DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
-	(CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
+	(CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
 
 #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
 	(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\

diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index cd6112d..9e746e3 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h

@@ -54,7 +54,7 @@
 	unsigned long tlb_emerg;
 #endif
 #endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 #define MEM_RESERVE_SECURE_SECURED	0x1
 #define MEM_RESERVE_SECURE_MAINTAINED	0x2
 #define MEM_RESERVE_SECURE_ADDR_MASK	(~0x3)

diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h
index 4733c07..c63c27d 100644
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ b/arch/arm/include/asm/iproc-common/configs.h

@@ -12,6 +12,6 @@
 #define CONFIG_IPROC
 
 /* Memory Info */
-#define CONFIG_SYS_SDRAM_BASE		0x61000000
+#define CFG_SYS_SDRAM_BASE		0x61000000
 
 #endif /* __IPROC_COMMON_CONFIGS_H */

diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h
index a4cc27e..38a1a6e 100644
--- a/arch/arm/include/asm/ti-common/davinci_nand.h
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h

@@ -18,13 +18,13 @@
 #define MASK_CLE		0x10
 #define MASK_ALE		0x08
 
-#ifdef CONFIG_SYS_NAND_MASK_CLE
+#ifdef CFG_SYS_NAND_MASK_CLE
 #undef MASK_CLE
-#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#define MASK_CLE CFG_SYS_NAND_MASK_CLE
 #endif
-#ifdef CONFIG_SYS_NAND_MASK_ALE
+#ifdef CFG_SYS_NAND_MASK_ALE
 #undef MASK_ALE
-#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#define MASK_ALE CFG_SYS_NAND_MASK_ALE
 #endif
 
 struct davinci_emif_regs {

diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
index 22fd541..6de0ce9 100644
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c

@@ -15,8 +15,7 @@
 #include <linux/kbuild.h>
 #include <linux/arm-smccc.h>
 
-#if defined(CONFIG_MX27) \
-	|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #include <asm/arch/imx-regs.h>
 #endif
 
@@ -35,32 +34,6 @@
 	 * code. Is it better to define the macros directly in headers?
 	 */
 
-#if defined(CONFIG_MX27)
-	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
-	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
-	DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
-	DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
-
-	DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
-	DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
-	DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
-	DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
-	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
-	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
-	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
-
-	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
-	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
-	DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
-	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
-	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
-
-	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
-		offsetof(struct system_control_regs, gpcr));
-	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
-		offsetof(struct system_control_regs, fmcr));
-#endif
-
 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 	/* Round up to make sure size gives nice stack alignment */
 	DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));

diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index 826e09e..5e6eaad 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c

@@ -29,7 +29,7 @@
 	struct bd_info *bd = gd->bd;
 
 	bdinfo_print_num_l("arch_number", bd->bi_arch_number);
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
 		bdinfo_print_num_ll("Secure ram",
 				    gd->arch.secure_ram &

diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
index bbaaaa4..d05314e 100644
--- a/arch/arm/lib/cache-pl310.c
+++ b/arch/arm/lib/cache-pl310.c

@@ -11,7 +11,7 @@
 #include <config.h>
 #include <common.h>
 
-struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 static void pl310_cache_sync(void)
 {

diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index a2bf2e5..1a589c7 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c

@@ -152,7 +152,7 @@
 	debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
 	      gd->arch.tlb_addr + gd->arch.tlb_size);
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	/*
 	 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
 	 * with location within secure ram.

diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index a54c84b..7cf7d16 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S

@@ -83,8 +83,8 @@
  */
 
 _start:
-#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
-	.word	CONFIG_SYS_DV_NOR_BOOT_CFG
+#ifdef CFG_SYS_DV_NOR_BOOT_CFG
+	.word	CFG_SYS_DV_NOR_BOOT_CFG
 #endif
 	ARM_VECTORS
 #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */

diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c
index aca2002..bae1027 100644
--- a/arch/arm/mach-aspeed/ast2500/board_common.c
+++ b/arch/arm/mach-aspeed/ast2500/board_common.c

@@ -31,7 +31,7 @@
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c
index 82ff219..dc6cdc3 100644
--- a/arch/arm/mach-aspeed/ast2600/board_common.c
+++ b/arch/arm/mach-aspeed/ast2600/board_common.c

@@ -54,7 +54,7 @@
 	int i = 0, rc;
 	struct udevice *dev;
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	while (1) {
 		rc = uclass_get_device(UCLASS_MISC, i++, &dev);

diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c
index c744027..09ac66d 100644
--- a/arch/arm/mach-at91/arm920t/clock.c
+++ b/arch/arm/mach-at91/arm920t/clock.c

@@ -26,7 +26,7 @@
 {
 	switch (css) {
 	case AT91_PMC_MCKR_CSS_SLOW:
-		return CONFIG_SYS_AT91_SLOW_CLOCK;
+		return CFG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
 		return gd->arch.main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
@@ -107,7 +107,7 @@
 {
 	unsigned freq, mckr;
 	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
 	unsigned tmp;
 	/*
 	 * When the bootloader initialized the main oscillator correctly,
@@ -120,7 +120,7 @@
 			tmp = readl(&pmc->mcfr);
 		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
 		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+		main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
 	gd->arch.main_clk_rate_hz = main_clock;

diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c
index 44c079c..9bf03fd 100644
--- a/arch/arm/mach-at91/arm920t/cpu.c
+++ b/arch/arm/mach-at91/arm920t/cpu.c

@@ -16,11 +16,11 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
 #endif
 
 int arch_cpu_init(void)
 {
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+	return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
 }

diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S
index 57e51c8..6b7d3cb 100644
--- a/arch/arm/mach-at91/arm920t/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S

@@ -94,11 +94,11 @@
 	.word AT91_ASM_MC_SMC_CSR0
 	.word CONFIG_SYS_SMC_CSR0_VAL
 	.word AT91_ASM_PMC_PLLAR
-	.word CONFIG_SYS_PLLAR_VAL
+	.word CFG_SYS_PLLAR_VAL
 	.word AT91_ASM_PMC_PLLBR
 	.word CONFIG_SYS_PLLBR_VAL
 	.word AT91_ASM_PMC_MCKR
-	.word CONFIG_SYS_MCKR_VAL
+	.word CFG_SYS_MCKR_VAL
 SMRDATAE:
 	/* here there's a delay */
 SMRDATA1:
@@ -107,45 +107,45 @@
 	.word AT91_ASM_PIOC_BSR
 	.word CONFIG_SYS_PIOC_BSR_VAL
 	.word AT91_ASM_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL
+	.word CFG_SYS_PIOC_PDR_VAL
 	.word AT91_ASM_MC_EBI_CSA
 	.word CONFIG_SYS_EBI_CSA_VAL
 	.word AT91_ASM_MC_SDRAMC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
+	.word CFG_SYS_SDRC_CR_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRC_MR_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRC_MR_VAL1
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word CONFIG_SYS_SDRAM1
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRC_MR_VAL2
+	.word CFG_SYS_SDRAM1
+	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRC_TR_VAL
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
 	.word AT91_ASM_MC_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
+	.word CFG_SYS_SDRC_MR_VAL3
+	.word CFG_SYS_SDRAM
+	.word CFG_SYS_SDRAM_VAL
 SMRDATA1E:
 	/* SMRDATA1 is 176 bytes long */
 #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c
index c400e87..8ef5764 100644
--- a/arch/arm/mach-at91/arm920t/timer.c
+++ b/arch/arm/mach-at91/arm920t/timer.c

@@ -27,7 +27,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
+#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
 
 int timer_init(void)
 {
@@ -92,7 +92,7 @@
 	u32 endtime;
 	signed long diff;
 
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo = CFG_SYS_HZ_CLOCK / 1000;
 	tmo *= usec;
 	tmo /= 1000;
 

diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
index c68e0c0..013daf4 100644
--- a/arch/arm/mach-at91/arm926ejs/clock.c
+++ b/arch/arm/mach-at91/arm926ejs/clock.c

@@ -26,7 +26,7 @@
 {
 	switch (css) {
 	case AT91_PMC_MCKR_CSS_SLOW:
-		return CONFIG_SYS_AT91_SLOW_CLOCK;
+		return CFG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
 		return gd->arch.main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
@@ -115,7 +115,7 @@
 {
 	unsigned freq, mckr;
 	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
 	unsigned tmp;
 	/*
 	 * When the bootloader initialized the main oscillator correctly,
@@ -128,7 +128,7 @@
 			tmp = readl(&pmc->mcfr);
 		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
 		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+		main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
 	gd->arch.main_clk_rate_hz = main_clock;

diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c
index 761edb6..5e84b0a 100644
--- a/arch/arm/mach-at91/arm926ejs/cpu.c
+++ b/arch/arm/mach-at91/arm926ejs/cpu.c

@@ -15,13 +15,13 @@
 #include <asm/arch/at91_gpbr.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
 #endif
 
 int arch_cpu_init(void)
 {
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+	return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
 }
 
 void arch_preboot_os(void)

diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
index c51eee2..e159a74 100644
--- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S

@@ -21,8 +21,8 @@
 #ifdef CONFIG_ATMEL_LEGACY
 #include <asm/arch/at91sam9_matrix.h>
 #endif
-#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
-#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
+#ifndef CFG_SYS_MATRIX_EBICSA_VAL
+#define CFG_SYS_MATRIX_EBICSA_VAL CFG_SYS_MATRIX_EBI0CSA_VAL
 #endif
 
 .globl lowlevel_init
@@ -67,7 +67,7 @@
 	ldr	r1, =(AT91_ASM_PMC_MOR)
 	ldr	r2, =(AT91_ASM_PMC_SR)
 	/* Main oscillator Enable register PMC_MOR: */
-	ldr	r0, =CONFIG_SYS_MOR_VAL
+	ldr	r0, =CFG_SYS_MOR_VAL
 	str	r0, [r1]
 
 	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
@@ -85,7 +85,7 @@
  * ----------------------------------------------------------------------------
  */
 	ldr	r1, =(AT91_ASM_PMC_PLLAR)
-	ldr	r0, =CONFIG_SYS_PLLAR_VAL
+	ldr	r0, =CFG_SYS_PLLAR_VAL
 	str	r0, [r1]
 
 	/* Reading the PMC Status register to detect when the PLLA is locked */
@@ -105,7 +105,7 @@
 	ldr	r1, =(AT91_ASM_PMC_MCKR)
 
 	/* -Master Clock Controller register PMC_MCKR */
-	ldr	r0, =CONFIG_SYS_MCKR1_VAL
+	ldr	r0, =CFG_SYS_MCKR1_VAL
 	str	r0, [r1]
 
 	/* Reading the PMC Status to detect when the Master clock is ready */
@@ -116,7 +116,7 @@
 	cmp	r3, #AT91_PMC_IXR_MCKRDY
 	bne	MCKRDY_Loop
 
-	ldr	r0, =CONFIG_SYS_MCKR2_VAL
+	ldr	r0, =CFG_SYS_MCKR2_VAL
 	str	r0, [r1]
 
 	/* Reading the PMC Status to detect when the Master clock is ready */
@@ -158,84 +158,84 @@
 
 SMRDATA:
 	.word AT91_ASM_WDT_MR
-	.word CONFIG_SYS_WDTC_WDMR_VAL
+	.word CFG_SYS_WDTC_WDMR_VAL
 	/* configure PIOx as EBI0 D[16-31] */
 #if defined(CONFIG_AT91SAM9263)
 	.word AT91_ASM_PIOD_PDR
-	.word CONFIG_SYS_PIOD_PDR_VAL1
+	.word CFG_SYS_PIOD_PDR_VAL1
 	.word AT91_ASM_PIOD_PUDR
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
+	.word CFG_SYS_PIOD_PPUDR_VAL
 	.word AT91_ASM_PIOD_ASR
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
+	.word CFG_SYS_PIOD_PPUDR_VAL
 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
 	|| defined(CONFIG_AT91SAM9G20)
 	.word AT91_ASM_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL1
+	.word CFG_SYS_PIOC_PDR_VAL1
 	.word AT91_ASM_PIOC_PUDR
-	.word CONFIG_SYS_PIOC_PPUDR_VAL
+	.word CFG_SYS_PIOC_PPUDR_VAL
 #endif
 	.word AT91_ASM_MATRIX_CSA0
-	.word CONFIG_SYS_MATRIX_EBICSA_VAL
+	.word CFG_SYS_MATRIX_EBICSA_VAL
 
 	/* flash */
 	.word AT91_ASM_SMC_MODE0
-	.word CONFIG_SYS_SMC0_MODE0_VAL
+	.word CFG_SYS_SMC0_MODE0_VAL
 
 	.word AT91_ASM_SMC_CYCLE0
-	.word CONFIG_SYS_SMC0_CYCLE0_VAL
+	.word CFG_SYS_SMC0_CYCLE0_VAL
 
 	.word AT91_ASM_SMC_PULSE0
-	.word CONFIG_SYS_SMC0_PULSE0_VAL
+	.word CFG_SYS_SMC0_PULSE0_VAL
 
 	.word AT91_ASM_SMC_SETUP0
-	.word CONFIG_SYS_SMC0_SETUP0_VAL
+	.word CFG_SYS_SMC0_SETUP0_VAL
 
 SMRDATA1:
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word CFG_SYS_SDRC_MR_VAL1
 	.word AT91_ASM_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL1
+	.word CFG_SYS_SDRC_TR_VAL1
 	.word AT91_ASM_SDRAMC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
+	.word CFG_SYS_SDRC_CR_VAL
 	.word AT91_ASM_SDRAMC_MDR
-	.word CONFIG_SYS_SDRC_MDR_VAL
+	.word CFG_SYS_SDRC_MDR_VAL
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL1
+	.word CFG_SYS_SDRC_MR_VAL2
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL1
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL2
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL3
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL4
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL5
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL6
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL7
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL8
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL9
+	.word CFG_SYS_SDRC_MR_VAL3
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL2
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL3
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL4
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL5
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL6
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL7
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL8
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL9
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL4
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL10
+	.word CFG_SYS_SDRC_MR_VAL4
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL10
 	.word AT91_ASM_SDRAMC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL5
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL11
+	.word CFG_SYS_SDRC_MR_VAL5
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL11
 	.word AT91_ASM_SDRAMC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL2
-	.word CONFIG_SYS_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL12
+	.word CFG_SYS_SDRC_TR_VAL2
+	.word CFG_SYS_SDRAM_BASE
+	.word CFG_SYS_SDRAM_VAL12
 	/* User reset enable*/
 	.word AT91_ASM_RSTC_MR
-	.word CONFIG_SYS_RSTC_RMR_VAL
+	.word CFG_SYS_RSTC_RMR_VAL
 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
 	/* MATRIX_MCFG - REMAP all masters */
 	.word AT91_ASM_MATRIX_MCFG

diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index aa6bb6b..6bfa02d 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c

@@ -28,7 +28,7 @@
 {
 	switch (css) {
 	case AT91_PMC_MCKR_CSS_SLOW:
-		return CONFIG_SYS_AT91_SLOW_CLOCK;
+		return CFG_SYS_AT91_SLOW_CLOCK;
 	case AT91_PMC_MCKR_CSS_MAIN:
 		return gd->arch.main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
@@ -58,7 +58,7 @@
 {
 	unsigned freq, mckr;
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
 	unsigned tmp;
 	/*
 	 * When the bootloader initialized the main oscillator correctly,
@@ -71,7 +71,7 @@
 			tmp = readl(&pmc->mcfr);
 		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
 		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+		main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
 	}
 #endif
 	gd->arch.main_clk_rate_hz = main_clock;
@@ -271,7 +271,7 @@
 	clk_source = regval & AT91_PMC_PCR_GCKCSS;
 	switch (clk_source) {
 	case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
-		freq = CONFIG_SYS_AT91_SLOW_CLOCK;
+		freq = CFG_SYS_AT91_SLOW_CLOCK;
 		break;
 	case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
 		freq = gd->arch.main_clk_rate_hz;

diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c
index 9b37534..616621a 100644
--- a/arch/arm/mach-at91/armv7/cpu.c
+++ b/arch/arm/mach-at91/armv7/cpu.c

@@ -18,8 +18,8 @@
 #include <asm/arch/at91_gpbr.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#ifndef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK 0
 #endif
 
 int arch_cpu_init(void)
@@ -27,7 +27,7 @@
 #if defined(CONFIG_CLK_CCF)
 	return 0;
 #else
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+	return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
 #endif
 }
 

diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 2daeb4f..103db26 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h

@@ -128,7 +128,7 @@
 #define ATMEL_BASE_CS7		0x80000000
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines

diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index d5de8d5..2b252f1 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h

@@ -112,7 +112,7 @@
 #define ATMEL_BASE_CS7		0x80000000
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines

diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index c9fff93..0aa1862 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h

@@ -127,7 +127,7 @@
 #define ATMEL_BASE_CS7		0x80000000
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines

diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 5880325..22116f3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h

@@ -132,7 +132,7 @@
 #define ATMEL_BASE_CS7		0x80000000
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines

diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 8f9155c..b2c074e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h

@@ -112,7 +112,7 @@
 #define ATMEL_BASE_CS5		0x60000000	/* Compact Flash Slot 1 */
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffd3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffd3c
 
 /*
  * Other misc defines

diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index e3c494c..0efb4a9 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h

@@ -162,7 +162,7 @@
 #endif
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffe3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffe3c
 
 /*
  * Other misc defines

diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h
index c08d19c..47c7c72 100644
--- a/arch/arm/mach-at91/include/mach/sam9x60.h
+++ b/arch/arm/mach-at91/include/mach/sam9x60.h

@@ -140,7 +140,7 @@
 #define ATMEL_CPU_NAME	get_cpu_name()
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffe4c
+#define CFG_SYS_TIMER_COUNTER	0xfffffe4c
 
 /*
  * Other misc defines

diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index 5ff20e9..567cdd3 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h

@@ -238,7 +238,7 @@
 #define cpu_is_sama5d2	_cpu_is_sama5d2
 
 /* PIT Timer(PIT_PIIR) */
-#define CONFIG_SYS_TIMER_COUNTER	0xf804803c
+#define CFG_SYS_TIMER_COUNTER	0xf804803c
 
 #ifndef __ASSEMBLY__
 unsigned int get_chip_id(void);

diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 83f18a8..9efcf5f 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h

@@ -185,7 +185,7 @@
 #define CPU_HAS_PCR
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfffffe3c
+#define CFG_SYS_TIMER_COUNTER	0xfffffe3c
 
 /*
  * PMECC table in ROM

diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index e2edb6a..9c80286 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h

@@ -217,7 +217,7 @@
 		(get_extension_chip_id() == ARCH_EXID_SAMA5D44))
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfc06863c
+#define CFG_SYS_TIMER_COUNTER	0xfc06863c
 
 /*
  * No PMECC Galois table in ROM

diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index ea19ec3..dfba9f7 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c

@@ -101,17 +101,17 @@
 	at91_pllicpr_init(0x00);
 
 	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
-	at91_plla_init(CONFIG_SYS_AT91_PLLA);
+	at91_plla_init(CFG_SYS_AT91_PLLA);
 
 	/* PCK = PLLA = 2 * MCK */
-	at91_mck_init(CONFIG_SYS_MCKR);
+	at91_mck_init(CFG_SYS_MCKR);
 
 	/* Switch MCK on PLLA output */
-	at91_mck_init(CONFIG_SYS_MCKR_CSS);
+	at91_mck_init(CFG_SYS_MCKR_CSS);
 
-#if defined(CONFIG_SYS_AT91_PLLB)
+#if defined(CFG_SYS_AT91_PLLB)
 	/* Configure PLLB */
-	at91_pllb_init(CONFIG_SYS_AT91_PLLB);
+	at91_pllb_init(CFG_SYS_AT91_PLLB);
 #endif
 
 	/* Enable External Reset */
@@ -120,7 +120,7 @@
 	/* Initialize matrix */
 	matrix_init();
 
-	gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
+	gd->arch.mck_rate_hz = CFG_SYS_MASTER_CLOCK;
 	/*
 	 * init timer long enough for using in spl.
 	 */

diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 217ed12..a30c4f6 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c

@@ -124,7 +124,7 @@
 	/* PMC configuration */
 	at91_pmc_init();
 
-	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+	at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
 
 	matrix_init();
 

diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index 0f68f9f..dae6026 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c

@@ -42,7 +42,7 @@
 	int pll_out;
 	unsigned int pll_base;
 
-	pll_out = CONFIG_SYS_OSCIN_FREQ;
+	pll_out = CFG_SYS_OSCIN_FREQ;
 
 	if (id == DAVINCI_AUXCLK_CLKID)
 		goto out;

diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c
index 759c937..08c8f59 100644
--- a/arch/arm/mach-davinci/da850_lowlevel.c
+++ b/arch/arm/mach-davinci/da850_lowlevel.c

@@ -185,9 +185,9 @@
 		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
 	}
 	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
-	writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+	writel(CFG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
 
-	if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+	if (CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
 		/* DDR2 */
 		clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
 			(1 << DDR_SLEW_DDR_PDENA_BIT) |
@@ -211,19 +211,19 @@
 	 * At the same time, set the TIMUNLOCK bit to allow changing
 	 * the timing registers
 	 */
-	tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
+	tmp = CFG_SYS_DA850_DDR2_SDBCR;
 	tmp &= ~DV_DDR_BOOTUNLOCK;
 	tmp |= DV_DDR_TIMUNLOCK;
 	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 
 	/* write memory configuration and timing */
-	if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+	if (!(CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
 		/* MOBILE DDR only*/
-		writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+		writel(CFG_SYS_DA850_DDR2_SDBCR2,
 			&dv_ddr2_regs_ctrl->sdbcr2);
 	}
-	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
-	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+	writel(CFG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+	writel(CFG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 
 	/* clear the TIMUNLOCK bit and write the value of the CL field */
 	tmp &= ~DV_DDR_TIMUNLOCK;
@@ -233,7 +233,7 @@
 	 * LPMODEN and MCLKSTOPEN must be set!
 	 * Without this bits set, PSC don;t switch states !!
 	 */
-	writel(CONFIG_SYS_DA850_DDR2_SDRCR |
+	writel(CFG_SYS_DA850_DDR2_SDRCR |
 		(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
 		(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
 		&dv_ddr2_regs_ctrl->sdrcr);
@@ -246,7 +246,7 @@
 	/* disable self refresh */
 	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
 		DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
-	writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+	writel(CFG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
 
 	return 0;
 }
@@ -265,7 +265,7 @@
 	writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
 
 	dv_maskbits(&davinci_syscfg_regs->suspsrc,
-		CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
+		CFG_SYS_DA850_SYSCFG_SUSPSRC);
 
 	/* configure pinmux settings */
 	if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
@@ -273,8 +273,8 @@
 
 #if defined(CONFIG_SYS_DA850_PLL_INIT)
 	/* PLL setup */
-	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
-	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
+	da850_pll_init(davinci_pllc0_regs, CFG_SYS_DA850_PLL0_PLLM);
+	da850_pll_init(davinci_pllc1_regs, CFG_SYS_DA850_PLL1_PLLM);
 #endif
 	/* setup CSn config */
 #if defined(CONFIG_SYS_DA850_CS2CFG)
@@ -290,8 +290,8 @@
 	board_gpio_init();
 
 #if !CONFIG_IS_ENABLED(DM_SERIAL)
-	ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM1),
+		     CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 #endif
 	/*
 	 * Fix Power and Emulation Management Register
@@ -299,7 +299,7 @@
 	 */
 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
 		DAVINCI_UART_PWREMU_MGMT_UTRST),
-#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
+#if (CFG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
 	       &davinci_uart0_ctrl_regs->pwremu_mgmt);
 #else
 	       &davinci_uart2_ctrl_regs->pwremu_mgmt);

diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c
index 73fdd1f..42078b3 100644
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c

@@ -26,14 +26,14 @@
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
-			(void *)CONFIG_SYS_SDRAM_BASE,
+			(void *)CFG_SYS_SDRAM_BASE,
 			CONFIG_MAX_RAM_BANK_SIZE);
 	return 0;
 }
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	return 0;

diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c
index 54aff78..5f5b9eb 100644
--- a/arch/arm/mach-davinci/spl.c
+++ b/arch/arm/mach-davinci/spl.c

@@ -27,9 +27,9 @@
 void putc(char c)
 {
 	if (c == '\n')
-		ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), '\r');
+		ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), '\r');
 
-	ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), c);
+	ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), c);
 }
 #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
 

diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c
index 43e0574..83c190b 100644
--- a/arch/arm/mach-davinci/timer.c
+++ b/arch/arm/mach-davinci/timer.c

@@ -32,7 +32,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct davinci_timer * const timer =
-	(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
+	(struct davinci_timer *)CFG_SYS_TIMERBASE;
 
 #define TIMER_LOAD_VAL	0xffffffff
 
@@ -47,7 +47,7 @@
 	writel(0x0, &timer->tim34);
 	writel(TIMER_LOAD_VAL, &timer->prd34);
 	writel(2 << 22, &timer->tcr);
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV;
 	gd->arch.timer_reset_value = 0;
 
 	return(0);

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 8410290..29e35e44 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig

@@ -67,10 +67,12 @@
 	select SUPPORT_SPL
 
 config TARGET_TRATS
+	select MISC_COMMON
 	bool "Exynos4210 Trats board"
 
 config TARGET_S5PC210_UNIVERSAL
 	bool "EXYNOS4210 Universal C210 board"
+	select MISC_COMMON
 
 config TARGET_ORIGEN
 	bool "Exynos4412 Origen board"
@@ -79,9 +81,11 @@
 
 config TARGET_TRATS2
 	bool "Exynos4412 Trat2 board"
+	select MISC_COMMON
 
 config TARGET_ODROID
 	bool "Exynos4412 Odroid board"
+	select MISC_COMMON
 
 endchoice
 endif
@@ -113,6 +117,7 @@
 	bool "Exynos5422 Odroid board"
 	select EXYNOS5_DT
 	select EXYNOS5420
+	select MISC_COMMON
 	select OF_CONTROL
 
 config TARGET_ARNDALE

diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index fa867f2..cad8ccc 100644
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c

@@ -236,7 +236,7 @@
  * better have similar timings, since there's only a single adjustment that is
  * shared by both chips).
  */
-const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
+const unsigned int test_addr = CFG_SYS_SDRAM_BASE;
 
 /* Test pattern with which RAM will be tested */
 static const unsigned int test_pattern[] = {

diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index f518539..553dac7 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c

@@ -141,7 +141,7 @@
 {
 	int upto, todo;
 	int i, timeout = 100;
-	struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
+	struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE;
 
 	set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
 	/* set the spi1 GPIO */

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b72b6af..ee5f199 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig

@@ -195,3 +195,9 @@
 	help
 	  This is to specific the cfg file for generating container
 	  image which will be loaded by SPL.
+
+config IOMUX_LPSR
+	bool
+
+config IOMUX_SHARE_CONF_REG
+	bool

diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index 0e76786..06ee608 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c

@@ -248,13 +248,13 @@
 	int end;
 
 	/* Calculate the image set end,
-	 * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000),
-	 * we use CONFIG_SYS_UBOOT_BASE
+	 * if it is less than CFG_SYS_UBOOT_BASE(0x8281000),
+	 * we use CFG_SYS_UBOOT_BASE
 	 * Otherwise, use the calculated address
 	 */
 	end = get_imageset_end((void *)NULL, QSPI_NOR_DEV);
-	if (end <= CONFIG_SYS_UBOOT_BASE)
-		end = CONFIG_SYS_UBOOT_BASE;
+	if (end <= CFG_SYS_UBOOT_BASE)
+		end = CFG_SYS_UBOOT_BASE;
 	else
 		end = ROUND(end, SZ_1K);
 

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index a486328..8050406 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c

@@ -178,7 +178,7 @@
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
-		if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+		if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
 			return i;
 
 	hang();	/* Entry not found, this must never happen. */

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 802cb0e..5d95fb8 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c

@@ -373,7 +373,7 @@
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
-		if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+		if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
 			return i;
 
 	hang();	/* Entry not found, this must never happen. */

diff --git a/arch/arm/mach-imx/mx5/lowlevel_init.S b/arch/arm/mach-imx/mx5/lowlevel_init.S
index b42cc3e..6ec38dc 100644
--- a/arch/arm/mach-imx/mx5/lowlevel_init.S
+++ b/arch/arm/mach-imx/mx5/lowlevel_init.S

@@ -205,7 +205,7 @@
 
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]
@@ -215,7 +215,7 @@
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x19239145
 	str r1, [r0, #CLKCTL_CBCDR]
-	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 
 	setup_pll PLL3_BASE_ADDR, 216
@@ -240,10 +240,10 @@
 
 	/* setup the rest */
 	/* Use lp_apm (24MHz) source for perclk */
-	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
-	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+	ldr r1, =CFG_SYS_CLKTL_CBCDR
 	str r1, [r0, #CLKCTL_CBCDR]
 
 	/* Restore the default values in the Gate registers */
@@ -378,7 +378,7 @@
 	mov r10, lr
 	mov r4, #0	/* Fix R4 to 0 */
 
-#if defined(CONFIG_SYS_MAIN_PWR_ON)
+#if defined(CFG_SYS_MAIN_PWR_ON)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
 	orr r1, r1, #1 << 23

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 752c57f..e6b0ee7 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig

@@ -168,6 +168,7 @@
 	select BOARD_LATE_INIT
 	select DM
 	select DM_THERMAL
+	select IOMUX_LPSR
 
 config TARGET_DART_6UL
 	bool "Variscite imx6ULL dart(DART-SOM-6ULL)"
@@ -396,6 +397,7 @@
 	select BOARD_LATE_INIT
 	select DM
 	select DM_THERMAL
+	select IOMUX_LPSR
 	imply CMD_DM
 
 config TARGET_MX6SXSABRESD
@@ -464,6 +466,7 @@
 	select BOARD_LATE_INIT
 	select DM
 	select DM_THERMAL
+	select IOMUX_LPSR
 	imply CMD_DM
 
 config TARGET_MX6ULZ_SMM_M2

diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c
index 699a3dc..2ba3245 100644
--- a/arch/arm/mach-imx/mx6/litesom.c
+++ b/arch/arm/mach-imx/mx6/litesom.c

@@ -172,7 +172,7 @@
 	 * Get actual RAM size, so we can adjust DDR row size for <512M
 	 * memories
 	 */
-	ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
+	ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M);
 	if (ram_size < SZ_512M) {
 		mem_ddr.rowaddr = 14;
 		mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);

diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index e9d7874..38ead8a 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c

@@ -44,7 +44,7 @@
 int board_init(void)
 {
 	/* Address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_FEC_MXC
 	setup_fec();

diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 3c38818..0bb18f6 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig

@@ -6,6 +6,7 @@
 	select ARCH_SUPPORT_PSCI
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select IOMUX_LPSR
 	select ROM_UNIFIED_SECTIONS
 	select SYSCOUNTER_TIMER
 	imply CMD_FUSE

diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 6b8f411..cb9801b 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c

@@ -349,7 +349,7 @@
 #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = imx_ddr_size();
 
 	return 0;

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 227706e..d5e1f8e 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c

@@ -561,7 +561,7 @@
 void spl_enable_dcache(void)
 {
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-	phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+	phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
 
 	dram_init();
 

diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk
index 9cc1f9e..7bc8af8 100644
--- a/arch/arm/mach-k3/config_secure.mk
+++ b/arch/arm/mach-k3/config_secure.mk

@@ -30,7 +30,7 @@
 	$(call if_changed,mkfitimage)
 
 MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
 

diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c
index 3d2ff67..2aec962 100644
--- a/arch/arm/mach-k3/r5_mpu.c
+++ b/arch/arm/mach-k3/r5_mpu.c

@@ -24,7 +24,7 @@
 	 O_I_WB_RD_WR_ALLOC, REGION_8MB},
 
 	/* U-Boot's code area marking it as WB and Write allocate */
-	{CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
+	{CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
 	 O_I_WB_RD_WR_ALLOC, REGION_2GB},
 	/* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
 	{0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,

diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c
index 4734e4c..dc97bac 100644
--- a/arch/arm/mach-keystone/cmd_mon.c
+++ b/arch/arm/mach-keystone/cmd_mon.c

@@ -23,7 +23,7 @@
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
-	freq = CONFIG_SYS_HZ_CLOCK;
+	freq = CFG_SYS_HZ_CLOCK;
 
 	addr = hextoul(argv[1], NULL);
 

diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 53117c2..ea7d0b9 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c

@@ -318,7 +318,7 @@
 	}
 
 	ddr3_ecc_init_range(base);
-	ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
+	ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size);
 
 	/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
 #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)

diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 98a8f05..424c32a 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h

@@ -263,7 +263,7 @@
 /* MSMC segment size shift bits */
 #define KS2_MSMC_SEG_SIZE_SHIFT		12
 #define KS2_MSMC_MAP_SEG_NUM		(2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
-#define KS2_MSMC_DST_SEG_BASE		(CONFIG_SYS_LPAE_SDRAM_BASE >> \
+#define KS2_MSMC_DST_SEG_BASE		(CFG_SYS_LPAE_SDRAM_BASE >> \
 					KS2_MSMC_SEG_SIZE_SHIFT)
 
 /* Device speed */

diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index 5b95f60..1954e69 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c

@@ -185,8 +185,8 @@
 	 * driver doesn't handle this.
 	 */
 #ifndef CONFIG_DM_SERIAL
-	ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM2),
+		     CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 #endif
 
 	return 0;

diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index d877be1..a6de767 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h

@@ -34,8 +34,7 @@
  * NAND configuration
  */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
+#define CFG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
 #define NAND_ALLOW_ERASE_ALL		1
 #endif
 
@@ -52,9 +51,8 @@
 
 /* Use common timer */
 #ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(MVEBU_TIMER_BASE + 0x14)
-#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_TCLK
+#define CFG_SYS_TIMER_COUNTER	(MVEBU_TIMER_BASE + 0x14)
+#define CFG_SYS_TIMER_RATE		CFG_SYS_TCLK
 #endif
 
 #endif /* _KW_CONFIG_H */

diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
index c44eacf..d3a3a83 100644
--- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h

@@ -15,6 +15,6 @@
 #define KW_REGS_PHY_BASE		KW88F6192_REGS_PHYS_BASE
 
 /* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK	  166000000 /* 166MHz */
+#define CFG_SYS_TCLK	  166000000 /* 166MHz */
 
 #endif /* _CONFIG_KW88F6192_H */

diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
index f86cd0b..7f8e156 100644
--- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h

@@ -15,7 +15,7 @@
 #define KW_REGS_PHY_BASE		KW88F6281_REGS_PHYS_BASE
 
 /* TCLK Core Clock definition */
-#define CONFIG_SYS_TCLK			((readl(CONFIG_SAR_REG) & BIT(21)) ? \
+#define CFG_SYS_TCLK			((readl(CONFIG_SAR_REG) & BIT(21)) ? \
 					166666667 : 200000000)
 
 #endif /* _ASM_ARCH_KW88F6281_H */

diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c
index 0a4fef2..6a67a35 100644
--- a/arch/arm/mach-lpc32xx/devices.c
+++ b/arch/arm/mach-lpc32xx/devices.c

@@ -6,7 +6,6 @@
 #include <common.h>
 #include <dm.h>
 #include <ns16550.h>
-#include <dm/platform_data/lpc32xx_hsuart.h>
 
 #include <asm/arch/clk.h>
 #include <asm/arch/uart.h>
@@ -44,35 +43,20 @@
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct ns16550_plat lpc32xx_uart[] = {
 	{ .base = UART3_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 	{ .base = UART4_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 	{ .base = UART5_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 	{ .base = UART6_BASE, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 };
 
-#if defined(CONFIG_LPC32XX_HSUART)
-static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
-	{ HS_UART1_BASE, },
-	{ HS_UART2_BASE, },
-	{ HS_UART7_BASE, },
-};
-#endif
-
 U_BOOT_DRVINFOS(lpc32xx_uarts) = {
-#if defined(CONFIG_LPC32XX_HSUART)
-	{ "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
-	{ "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
-#endif
 	{ "ns16550_serial", &lpc32xx_uart[0], },
 	{ "ns16550_serial", &lpc32xx_uart[1], },
 	{ "ns16550_serial", &lpc32xx_uart[2], },
 	{ "ns16550_serial", &lpc32xx_uart[3], },
-#if defined(CONFIG_LPC32XX_HSUART)
-	{ "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
-#endif
 };
 #endif
 

diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c
index 5d837e0..988b057 100644
--- a/arch/arm/mach-mediatek/mt7623/init.c
+++ b/arch/arm/mach-mediatek/mt7623/init.c

@@ -25,7 +25,7 @@
 {
 	u32 i;
 
-	if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+	if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) &&
 	    ((size_t)preloader_param % sizeof(size_t) == 0) &&
 	    preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
 	    preloader_param->dram_rank_num <=
@@ -35,7 +35,7 @@
 		for (i = 0; i < preloader_param->dram_rank_num; i++)
 			gd->ram_size += preloader_param->dram_rank_size[i];
 	} else {
-		gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+		gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
 					    SZ_2G);
 	}
 

diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c
index a895506..d8b10f0 100644
--- a/arch/arm/mach-mediatek/mt7981/init.c
+++ b/arch/arm/mach-mediatek/mt7981/init.c

@@ -14,7 +14,7 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
 
 	return 0;
 }

diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c
index cf89e63..fb74b2f 100644
--- a/arch/arm/mach-mediatek/mt7986/init.c
+++ b/arch/arm/mach-mediatek/mt7986/init.c

@@ -14,7 +14,7 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
 
 	return 0;
 }

diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c
index cc7f979..8204d96 100644
--- a/arch/arm/mach-mvebu/alleycat5/cpu.c
+++ b/arch/arm/mach-mvebu/alleycat5/cpu.c

@@ -21,8 +21,8 @@
 static struct mm_region ac5_mem_map[] = {
 	{
 		/* RAM */
-		.phys = CONFIG_SYS_SDRAM_BASE,
-		.virt = CONFIG_SYS_SDRAM_BASE,
+		.phys = CFG_SYS_SDRAM_BASE,
+		.virt = CFG_SYS_SDRAM_BASE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	},
@@ -102,7 +102,7 @@
 	/*
 	 * Config single DRAM bank
 	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	return 0;

diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index e3098a7..2c94f89 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c

@@ -32,7 +32,7 @@
 
 phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
-	unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
+	unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
 
 	return (gd->ram_top > top) ? top : gd->ram_top;
 }

diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c
index bab375e..6c801bf 100644
--- a/arch/arm/mach-mvebu/armada8k/dram.c
+++ b/arch/arm/mach-mvebu/armada8k/dram.c

@@ -38,7 +38,7 @@
 	 */
 	phys_size_t max_bank0_size = SZ_4G - SZ_1G;
 
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	if (gd->ram_size <= max_bank0_size) {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 		return 0;

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 1f8cdf8..67ad5e5 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c

@@ -659,7 +659,7 @@
 void v7_outer_cache_enable(void)
 {
 	struct pl310_regs *const pl310 =
-		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+		(struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 	/* The L2 cache is already disabled at this point */
 
@@ -691,7 +691,7 @@
 void v7_outer_cache_disable(void)
 {
 	struct pl310_regs *const pl310 =
-		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+		(struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 3b96188..e6383d4 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h

@@ -54,7 +54,7 @@
 
 #define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
 #define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
-#define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
+#define CFG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
 #define MVEBU_TWSI1_BASE	(MVEBU_REGISTER(0x11100))
 #define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
@@ -146,7 +146,7 @@
 #define BOOT_FROM_UART		0x30
 #define BOOT_FROM_SPI		0x38
 
-#define CONFIG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(20)) ? \
+#define CFG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(20)) ? \
 				 200000000 : 166000000)
 #elif defined(CONFIG_ARMADA_38X)
 /* SAR values for Armada 38x */
@@ -169,7 +169,7 @@
 #define BOOT_FROM_MMC		0x30
 #define BOOT_FROM_MMC_ALT	0x31
 
-#define CONFIG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(15)) ? \
+#define CFG_SYS_TCLK		((readl(CONFIG_SAR_REG) & BIT(15)) ? \
 				 200000000 : 250000000)
 #elif defined(CONFIG_ARMADA_MSYS)
 /* SAR values for MSYS */
@@ -188,7 +188,7 @@
 #define BOOT_FROM_UART		0x2
 #define BOOT_FROM_SPI		0x3
 
-#define CONFIG_SYS_TCLK		200000000	/* 200MHz */
+#define CFG_SYS_TCLK		200000000	/* 200MHz */
 #elif defined(CONFIG_ARMADA_XP)
 /* SAR values for Armada XP */
 #define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18230))
@@ -209,7 +209,7 @@
 #define BOOT_FROM_UART		0x2
 #define BOOT_FROM_SPI		0x3
 
-#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+#define CFG_SYS_TCLK		250000000	/* 250MHz */
 #endif
 
 #endif /* _MVEBU_SOC_H */

diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S
index 60c2072..6c9783a 100644
--- a/arch/arm/mach-mvebu/lowlevel.S
+++ b/arch/arm/mach-mvebu/lowlevel.S

@@ -35,10 +35,10 @@
 	 * Disable L2 cache
 	 *
 	 * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
-	 *       but CONFIG_SYS_PL310_BASE is already calculated from base
+	 *       but CFG_SYS_PL310_BASE is already calculated from base
 	 *       address SOC_REGS_PHY_BASE.
 	 */
-	ldr	r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
+	ldr	r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
 	ldr	r0, [r1, #L2X0_CTRL_OFF]
 	bic	r0, #L2X0_CTRL_EN
 	str	r0, [r1, #L2X0_CTRL_OFF]

diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
index cba2e34..ed4b1ca 100644
--- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
+++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c

@@ -11,7 +11,7 @@
 
 void set_pl310_ctrl(u32 enable)
 {
-	struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 	writel(enable, &pl310->pl310_ctrl);
 }

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 78317e4..3bf9720 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig

@@ -144,6 +144,9 @@
 	help
 	  Defines the MPU clock speed (in MHz).
 
+config SYS_OMAP_ABE_SYSCK
+	bool
+
 config TI_SECURE_EMIF_REGION_START
 	hex "Reserved EMIF region start address"
 	depends on TI_SECURE_DEVICE

diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index f393ff9..86755d6 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c

@@ -72,14 +72,14 @@
 
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
-			(void *)CONFIG_SYS_SDRAM_BASE,
+			(void *)CFG_SYS_SDRAM_BASE,
 			CONFIG_MAX_RAM_BANK_SIZE);
 	return 0;
 }
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	return 0;
@@ -87,29 +87,29 @@
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct ns16550_plat am33xx_serial[] = {
-	{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-# ifdef CONFIG_SYS_NS16550_COM2
-	{ .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-#  ifdef CONFIG_SYS_NS16550_COM3
-	{ .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-	{ .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-	{ .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-	{ .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
-	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	{ .base = CFG_SYS_NS16550_COM1, .reg_shift = 2,
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+# ifdef CFG_SYS_NS16550_COM2
+	{ .base = CFG_SYS_NS16550_COM2, .reg_shift = 2,
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+#  ifdef CFG_SYS_NS16550_COM3
+	{ .base = CFG_SYS_NS16550_COM3, .reg_shift = 2,
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	{ .base = CFG_SYS_NS16550_COM4, .reg_shift = 2,
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	{ .base = CFG_SYS_NS16550_COM5, .reg_shift = 2,
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+	{ .base = CFG_SYS_NS16550_COM6, .reg_shift = 2,
+	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 #  endif
 # endif
 };
 
 U_BOOT_DRVINFOS(am33xx_uarts) = {
 	{ "ns16550_serial", &am33xx_serial[0] },
-#  ifdef CONFIG_SYS_NS16550_COM2
+#  ifdef CFG_SYS_NS16550_COM2
 	{ "ns16550_serial", &am33xx_serial[1] },
-#   ifdef CONFIG_SYS_NS16550_COM3
+#   ifdef CFG_SYS_NS16550_COM3
 	{ "ns16550_serial", &am33xx_serial[2] },
 	{ "ns16550_serial", &am33xx_serial[3] },
 	{ "ns16550_serial", &am33xx_serial[4] },
@@ -520,7 +520,7 @@
 	sdram_init();
 	/* dram_init must store complete ramsize in gd->ram_size */
 	gd->ram_size = get_ram_size(
-			(void *)CONFIG_SYS_SDRAM_BASE,
+			(void *)CFG_SYS_SDRAM_BASE,
 			CONFIG_MAX_RAM_BANK_SIZE);
 }
 #endif

diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk
index f76262b..24ddcdb 100644
--- a/arch/arm/mach-omap2/config_secure.mk
+++ b/arch/arm/mach-omap2/config_secure.mk

@@ -102,7 +102,7 @@
 ifdef CONFIG_SPL_LOAD_FIT
 
 MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
 

diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c
index 312f868..a6a97af 100644
--- a/arch/arm/mach-omap2/emif-common.c
+++ b/arch/arm/mach-omap2/emif-common.c

@@ -389,7 +389,7 @@
 		/* Set region1 memory with 0 */
 		rgn_start = (regs->emif_ecc_address_range_1 &
 			     EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
-		rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+		rgn = rgn_start + CFG_SYS_SDRAM_BASE;
 		size = (regs->emif_ecc_address_range_1 &
 			EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
 
@@ -400,7 +400,7 @@
 		/* Set region2 memory with 0 */
 		rgn_start = (regs->emif_ecc_address_range_2 &
 			     EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
-		rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+		rgn = rgn_start + CFG_SYS_SDRAM_BASE;
 		size = (regs->emif_ecc_address_range_2 &
 			EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
 
@@ -1340,7 +1340,7 @@
 
 	mapped_size = 0;
 	section_cnt = 3;
-	sys_addr = CONFIG_SYS_SDRAM_BASE;
+	sys_addr = CFG_SYS_SDRAM_BASE;
 	emif1_size = get_emif_mem_size(EMIF1_BASE);
 	emif2_size = get_emif_mem_size(EMIF2_BASE);
 	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
@@ -1568,7 +1568,7 @@
 		size_prog = log_2_n_round_down(size_prog);
 		size_prog = (1 << size_prog);
 
-		size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+		size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
 						size_prog);
 		/* Compare with the size programmed */
 		if (size_detect != size_prog) {

diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c
index 2dcf0cf..1919748 100644
--- a/arch/arm/mach-omap2/mem-common.c
+++ b/arch/arm/mach-omap2/mem-common.c

@@ -124,25 +124,25 @@
 #if defined(CONFIG_NOR)
 	case MTD_DEV_TYPE_NOR:
 		gpmc_regs = gpmc_regs_nor;
-		base = CONFIG_SYS_FLASH_BASE;
-		size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
-		      ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
-		      ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
-		      ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
+		base = CFG_SYS_FLASH_BASE;
+		size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
+		      ((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+		      ((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
+		      ((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
 		                                              GPMC_SIZE_16M)));
 		break;
 #endif
 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
 	case MTD_DEV_TYPE_NAND:
 		gpmc_regs = gpmc_regs_nand;
-		base = CONFIG_SYS_NAND_BASE;
+		base = CFG_SYS_NAND_BASE;
 		size = GPMC_SIZE_16M;
 		break;
 #endif
 #if defined(CONFIG_CMD_ONENAND)
 	case MTD_DEV_TYPE_ONENAND:
 		gpmc_regs = gpmc_regs_onenand;
-		base = CONFIG_SYS_ONENAND_BASE;
+		base = CFG_SYS_ONENAND_BASE;
 		size = GPMC_SIZE_128M;
 		break;
 #endif

diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index 4c2f990..0787d19 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig

@@ -1,7 +1,12 @@
 if OMAP54XX
 
+config IODELAY_RECALIBRATION
+	bool
+
 config DRA7XX
 	bool
+	select IODELAY_RECALIBRATION
+	select SYS_OMAP_ABE_SYSCK
 	help
 	  DRA7xx is an OMAP based SOC with Dual Core A-15s.
 

diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c
index 0551bc1..0f9b915 100644
--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c

@@ -198,11 +198,11 @@
 	 */
 	if (sec_mem_start == 0)
 		sec_mem_start =
-			(CONFIG_SYS_SDRAM_BASE + (
+			(CFG_SYS_SDRAM_BASE + (
 #if defined(CONFIG_OMAP54XX)
 			omap_sdram_size()
 #else
-			get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+			get_ram_size((void *)CFG_SYS_SDRAM_BASE,
 				     CONFIG_MAX_RAM_BANK_SIZE)
 #endif
 			- sec_mem_size));

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 00d91c1..71fdf5b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c

@@ -27,7 +27,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+static struct gptimer *timer_base = (struct gptimer *)CFG_SYS_TIMERBASE;
 static ulong get_timer_masked(void);
 
 /*

diff --git a/arch/arm/mach-orion5x/include/mach/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h
index 0e9fe0d..ee0aa94 100644
--- a/arch/arm/mach-orion5x/include/mach/mv88f5182.h
+++ b/arch/arm/mach-orion5x/include/mach/mv88f5182.h

@@ -18,6 +18,6 @@
 #define ORION5X_REGS_PHY_BASE		F88F5182_REGS_PHYS_BASE
 
 /* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+#define CFG_SYS_TCLK			166000000 /* 166MHz */
 
 #endif /* _CONFIG_88F5182_H */

diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c
index d7ea2e3..b373e59 100644
--- a/arch/arm/mach-orion5x/timer.c
+++ b/arch/arm/mach-orion5x/timer.c

@@ -74,7 +74,7 @@
 static inline ulong read_timer(void)
 {
 	return readl(CNTMR_VAL_REG(UBOOT_CNTR))
-	      / (CONFIG_SYS_TCLK / 1000);
+	      / (CFG_SYS_TCLK / 1000);
 }
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -92,7 +92,7 @@
 	} else {
 		/* we have an overflow ... */
 		timestamp += lastdec +
-			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+			(TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now;
 	}
 	lastdec = now;
 
@@ -115,7 +115,7 @@
 	ulong delayticks;
 
 	current = uboot_cntr_val();
-	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+	delayticks = (usec * (CFG_SYS_TCLK / 1000000));
 
 	if (current < delayticks) {
 		delayticks -= current;

diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c
index 4baef2e..f0f46f2 100644
--- a/arch/arm/mach-owl/soc.c
+++ b/arch/arm/mach-owl/soc.c

@@ -50,7 +50,7 @@
 /* This is called after dram_init() so use get_ram_size result */
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	return 0;

diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
index a07eff7..31badc5 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32

@@ -8,6 +8,7 @@
 	bool "Renesas RCar Gen2"
 	select PHY
 	select PHY_RCAR_GEN2
+	select TMU_TIMER
 
 config R8A7740
 	bool "Renesas SoC R8A7740"
@@ -121,6 +122,9 @@
 
 endchoice
 
+config TMU_TIMER
+	bool
+
 config SYS_SOC
 	default "rmobile"
 

diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h
index ef74d59..485ea7e 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h

@@ -24,10 +24,7 @@
 #define MSTP11_BITS	0x00000000
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
-#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
-#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 4
 
 #define R8A7790_CUT_ES2X	2
 #define IS_R8A7790_ES2()	\

diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h
index 681d1ea..2006ad58 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h

@@ -14,9 +14,7 @@
  */
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
-#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
 
 #define DBSC3_1_QOS_R0_BASE	0xE67A1000
 #define DBSC3_1_QOS_R1_BASE	0xE67A1100

diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h
index 06db64a..cc1b00d 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7792.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h

@@ -24,6 +24,6 @@
 #define MSTP11_BITS	0x00000008
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 1
 
 #endif /* __ASM_ARCH_R8A7792_H */

diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h
index 31433c3..02f4286 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7793.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h

@@ -15,9 +15,7 @@
  */
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
-#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
 
 #define DBSC3_1_QOS_R0_BASE	0xE67A1000
 #define DBSC3_1_QOS_R1_BASE	0xE67A1100

diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h
index 3baa423..a2a949d 100644
--- a/arch/arm/mach-rmobile/include/mach/r8a7794.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h

@@ -24,9 +24,7 @@
 #define MSTP11_BITS	0x000001C0
 
 /* SDHI */
-#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
-#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
-#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
 
 #define R8A7794_CUT_ES2		2
 #define IS_R8A7794_ES2()	\

diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h
index 4c98dff..e422e91 100644
--- a/arch/arm/mach-rmobile/include/mach/rcar-base.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h

@@ -70,15 +70,6 @@
 #define SMSTPCR10		0xE6150998
 #define SMSTPCR11		0xE615099C
 
-/* RCAR-I2C */
-#define CONFIG_SYS_RCAR_I2C0_BASE	0xE6508000
-#define CONFIG_SYS_RCAR_I2C1_BASE	0xE6518000
-#define CONFIG_SYS_RCAR_I2C2_BASE	0xE6530000
-#define CONFIG_SYS_RCAR_I2C3_BASE	0xE6540000
-
-/* SDHI */
-#define CONFIG_SYS_SH_SDHI0_BASE	0xEE100000
-
 #define S3C_BASE		0xE6784000
 #define S3C_INT_BASE		0xE6784A00
 #define S3C_MEDIA_BASE		0xE6784B00

diff --git a/arch/arm/mach-rmobile/timer.c b/arch/arm/mach-rmobile/timer.c
index ba06535..293c23b 100644
--- a/arch/arm/mach-rmobile/timer.c
+++ b/arch/arm/mach-rmobile/timer.c

@@ -40,8 +40,8 @@
 {
 	u64 timer = get_cpu_global_timer();
 
-	timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
-	do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
+	timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1));
+	do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK));
 	return timer;
 }
 
@@ -65,7 +65,7 @@
 	u64 wait;
 
 	start = get_cpu_global_timer();
-	wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
+	wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2);
 	do {
 		current = get_cpu_global_timer();
 	} while ((current - start) < wait);
@@ -83,5 +83,5 @@
 
 ulong get_tbclk(void)
 {
-	return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
+	return (ulong)(CFG_SYS_CPU_CLK >> 2);
 }

diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 12f1d7e..e086c47 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c

@@ -37,7 +37,7 @@
 
 int dram_init_banksize(void)
 {
-	size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+	size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE),
 			 (unsigned long)(gd->ram_top));
 
 #ifdef CONFIG_ARM64
@@ -48,26 +48,26 @@
 #ifdef CONFIG_SPL_OPTEE_IMAGE
 	struct tos_parameter_t *tos_parameter;
 
-	tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+	tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE +
 			TRUST_PARAMETER_OFFSET);
 
 	if (tos_parameter->tee_mem.flags == 1) {
-		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 		gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
-					- CONFIG_SYS_SDRAM_BASE;
+					- CFG_SYS_SDRAM_BASE;
 		gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
 					tos_parameter->tee_mem.size;
 		gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
 	} else {
-		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 		gd->bd->bi_dram[0].size = 0x8400000;
 		/* Reserve 32M for OPTEE with TA */
-		gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+		gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
 					+ gd->bd->bi_dram[0].size + 0x2000000;
 		gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
 	}
 #else
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
 #endif
 #endif
@@ -207,7 +207,7 @@
 
 phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
-	unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
+	unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
 
 	return (gd->ram_top > top) ? top : gd->ram_top;
 }

diff --git a/arch/arm/mach-s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig
index 8cffced..b6a4b0b 100644
--- a/arch/arm/mach-s5pc1xx/Kconfig
+++ b/arch/arm/mach-s5pc1xx/Kconfig

@@ -9,6 +9,7 @@
 	select OF_CONTROL
 	select BLK
 	select DM_MMC
+	select MISC_COMMON
 
 config TARGET_SMDKC100
 	bool "Support smdkc100 board"

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index b49006c..09e0919 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c

@@ -46,7 +46,7 @@
 int board_init(void)
 {
 	/* Address of boot parameters for ATAG (if ATAG is used) */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 9c19157..5b5a81a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c

@@ -34,7 +34,7 @@
 
 #ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	(struct pl310_regs *)CFG_SYS_PL310_BASE;
 #endif
 
 struct bsel bsel_str[] = {

diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 7ce888d..93c9e8b 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c

@@ -60,7 +60,7 @@
 
 #if defined(CONFIG_SPL_BUILD)
 static struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	(struct pl310_regs *)CFG_SYS_PL310_BASE;
 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
 	(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
 
@@ -256,7 +256,7 @@
 	/* If we're still in OCRAM, don't set the XN bit on it */
 	if (!(gd->flags & GD_FLG_RELOC)) {
 		set_section_dcache(
-			CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+			CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
 			DCACHE_WRITETHROUGH);
 	}
 

diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 4edf4f9..e7500c1 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c

@@ -31,7 +31,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	(struct pl310_regs *)CFG_SYS_PL310_BASE;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static struct scu_registers *scu_regs =

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index 2c567ed..9edbbf4 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c

@@ -41,7 +41,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define BOOTROM_SHARED_MEM_SIZE		0x800	/* 2KB */
-#define BOOTROM_SHARED_MEM_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+#define BOOTROM_SHARED_MEM_ADDR		(CFG_SYS_INIT_RAM_ADDR + \
 					 SOCFPGA_PHYS_OCRAM_SIZE - \
 					 BOOTROM_SHARED_MEM_SIZE)
 #define RST_STATUS_SHARED_ADDR		(BOOTROM_SHARED_MEM_ADDR + 0x438)

diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index a58f1cf..d9e8c84 100644
--- a/arch/arm/mach-socfpga/timer.c
+++ b/arch/arm/mach-socfpga/timer.c

@@ -10,7 +10,7 @@
 
 #define TIMER_LOAD_VAL		0xFFFFFFFF
 
-static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+static const struct socfpga_timer *timer_base = (void *)CFG_SYS_TIMERBASE;
 
 /*
  * Timer initialization

diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index 2c87319..cdf2750 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c

@@ -33,11 +33,11 @@
 bool mctl_mem_matches(u32 offset)
 {
 	/* Try to write different values to RAM at two addresses */
-	writel(0, CONFIG_SYS_SDRAM_BASE);
-	writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+	writel(0, CFG_SYS_SDRAM_BASE);
+	writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
 	dsb();
 	/* Check if the same value is actually observed when reading back */
-	return readl(CONFIG_SYS_SDRAM_BASE) ==
-	       readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
+	return readl(CFG_SYS_SDRAM_BASE) ==
+	       readl((ulong)CFG_SYS_SDRAM_BASE + offset);
 }
 #endif

diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c
index 56c2d55..3aa3ce7 100644
--- a/arch/arm/mach-sunxi/dram_suniv.c
+++ b/arch/arm/mach-sunxi/dram_suniv.c

@@ -175,9 +175,9 @@
 	u32 k = 0;
 
 	for (k = 0; k < 32; k++)
-		writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k);
+		writel(k, CFG_SYS_SDRAM_BASE + 4 * k);
 	for (k = 0; k < 32; k++) {
-		if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k)
+		if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k)
 			return 0;
 	}
 	return 1;
@@ -266,11 +266,11 @@
 	dram_para_setup(para);
 	dram_scan_readpipe(para);
 	for (i = 0; i < 32; i++) {
-		*((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
-		*((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
+		*((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
+		*((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
 	}
 	for (i = 0; i < 32; i++) {
-		val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i));
+		val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i));
 		if (val1 == 0x22)
 			count++;
 	}
@@ -283,11 +283,11 @@
 	para->row_width = rowflag;
 	dram_para_setup(para);
 	if (colflag == 10) {
-		addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000;
-		addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000;
+		addr1 = CFG_SYS_SDRAM_BASE + 0x400000;
+		addr2 = CFG_SYS_SDRAM_BASE + 0xc00000;
 	} else {
-		addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000;
-		addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000;
+		addr1 = CFG_SYS_SDRAM_BASE + 0x200000;
+		addr2 = CFG_SYS_SDRAM_BASE + 0x600000;
 	}
 	for (i = 0; i < 32; i++) {
 		*((u8 *)(addr1 + i)) = 0x33;
@@ -319,7 +319,7 @@
 
 static void simple_dram_check(void)
 {
-	volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE;
+	volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE;
 	int i;
 
 	for (i = 0; i < 0x40; i++)

diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 9107b11..4af5922 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c

@@ -711,7 +711,7 @@
  */
 static void mctl_r40_detect_rank_count(struct dram_para *para)
 {
-	ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE +
+	ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE +
 			   mctl_calc_rank_size(&para->ranks[0]);
 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
@@ -744,10 +744,10 @@
 
 static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
 {
-	mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, &para->ranks[0]);
+	mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, &para->ranks[0]);
 
 	if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) {
-		mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(&para->ranks[0]), &para->ranks[1]);
+		mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(&para->ranks[0]), &para->ranks[1]);
 	}
 }
 

diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index 95d6555..f8b61a2 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c

@@ -259,9 +259,9 @@
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 static struct ns16550_plat ns16550_com1_pdata = {
-	.base = CONFIG_SYS_NS16550_COM1,
+	.base = CFG_SYS_NS16550_COM1,
 	.reg_shift = 2,
-	.clock = CONFIG_SYS_NS16550_CLK,
+	.clock = CFG_SYS_NS16550_CLK,
 	.fcr = UART_FCR_DEFVAL,
 };
 

diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 82d3d33..54bbd8a 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c

@@ -370,7 +370,7 @@
 
 	/* fall back to default DRAM bank size computation */
 
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
 
 #ifdef CONFIG_PCI
@@ -412,5 +412,5 @@
 
 	/* fall back to default usable RAM computation */
 
-	return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
+	return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
 }

diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig
index 5c4d35b..345563f 100644
--- a/arch/arm/mach-tegra/tegra20/Kconfig
+++ b/arch/arm/mach-tegra/tegra20/Kconfig

@@ -1,5 +1,15 @@
 if TEGRA20
 
+config TEGRA_LP0
+	bool
+	select TEGRA_CLOCK_SCALING
+
+config TEGRA_PMU
+	bool
+
+config TEGRA_CLOCK_SCALING
+	bool
+
 choice
 	prompt "Tegra20 board select"
 	optional
@@ -23,6 +33,8 @@
 config TARGET_SEABOARD
 	bool "NVIDIA Seaboard"
 	select BOARD_LATE_INIT
+	select TEGRA_LP0
+	select TEGRA_PMU
 
 config TARGET_TEC
 	bool "Avionic Design Tamonten Evaluation Carrier"

diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c
index 3d3758f..5e3a9eb 100644
--- a/arch/arm/mach-tegra/tegra20/warmboot.c
+++ b/arch/arm/mach-tegra/tegra20/warmboot.c

@@ -23,10 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
-#endif
-
 /*
  * This is the place in SRAM where the SDRAM parameters are stored. There
  * are 4 blocks, one for each RAM code

diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c
index f9fd4fe..05a9134 100644
--- a/arch/arm/mach-u8500/cache.c
+++ b/arch/arm/mach-u8500/cache.c

@@ -22,7 +22,7 @@
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_disable(void)
 {
-	struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+	struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
 
 	/*
 	 * Linux expects the L2 cache to be turned off by the bootloader.

diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c
index a40bdf1..58247c2 100644
--- a/arch/arm/mach-uniphier/arm32/timer.c
+++ b/arch/arm/mach-uniphier/arm32/timer.c

@@ -10,7 +10,7 @@
 #include "arm-mpcore.h"
 
 #define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
-#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
+#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1)
 
 static void *get_global_timer_base(void)
 {

diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c
index 739cb29..b471412 100644
--- a/arch/arm/mach-versatile/timer.c
+++ b/arch/arm/mach-versatile/timer.c

@@ -36,9 +36,9 @@
 	ulong	tmr_ctrl_val;
 
 	/* 1st disable the Timer */
-	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+	tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
 	tmr_ctrl_val &= ~TIMER_ENABLE;
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+	*(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
 
 	/*
 	 * The Timer Control Register has one Undefined/Shouldn't Use Bit
@@ -52,11 +52,11 @@
 	 * Tmr Siz : 16 Bit Counter
 	 * Tmr in Wrapping Mode
 	 */
-	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+	tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
 	tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
 	tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
 
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+	*(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
 
 	return 0;
 }

diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index ac595ee..3b6518c 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c

@@ -54,7 +54,7 @@
 	writel(0x757BDF0D, &devcfg_base->unlock);
 	writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
 
-#if (CONFIG_SYS_SDRAM_BASE == 0)
+#if (CFG_SYS_SDRAM_BASE == 0)
 	/* remap DDR to zero, FILTERSTART */
 	writel(0, &scu_base->filter_start);
 

diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c
index e44656d..ba2c228 100644
--- a/arch/m68k/cpu/mcf523x/cpu.c
+++ b/arch/m68k/cpu/mcf523x/cpu.c

@@ -92,7 +92,7 @@
 	u32 wdog_module = 0;
 
 	/* set timeout and enable watchdog */
-	wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
+	wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT_MSECS);
 	wdog_module |= (wdog_module / 8192);
 	out_be16(&wdp->mr, wdog_module);
 

diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c
index 87effa7..10be738 100644
--- a/arch/m68k/cpu/mcf523x/cpu_init.c
+++ b/arch/m68k/cpu/mcf523x/cpu_init.c

@@ -47,36 +47,36 @@
 	out_be16(&wdog->cr, 0);
 #endif
 
-	out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+	out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
 
 	/* Port configuration */
 	out_8(&gpio->par_cs, 0);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-	out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+	out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
-	out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+	out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
-	out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+	out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
-	out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+	out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
@@ -108,8 +108,8 @@
 #endif
 
 #ifdef CONFIG_SYS_I2C_FSL
-	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
-	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+	CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+	CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
 #endif
 
 	icache_enable();

diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c
index f41f977..6b08a12 100644
--- a/arch/m68k/cpu/mcf523x/speed.c
+++ b/arch/m68k/cpu/mcf523x/speed.c

@@ -29,7 +29,7 @@
 	while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
 		;
 
-	gd->bus_clk = CONFIG_SYS_CLK;
+	gd->bus_clk = CFG_SYS_CLK;
 	gd->cpu_clk = (gd->bus_clk * 2);
 
 #ifdef CONFIG_SYS_I2C_FSL

diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index 4c9c96d..d2a21c3 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S

@@ -91,10 +91,10 @@
 	move.w	#0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
@@ -116,7 +116,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l  #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,

diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index 8f72ef5..d7cbf11 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c

@@ -87,7 +87,7 @@
 
 	/* set timeout and enable watchdog */
 	out_be16(&wdt->mr,
-		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+		(CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
 
 	/* reset watchdog counter */
 	out_be16(&wdt->sr, 0x5555);
@@ -132,11 +132,11 @@
 
 	if (cpu_model)
 		printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
-		       cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
+		       cpu_model, prn, strmhz(buf, CFG_SYS_CLK));
 	else
 		printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
 		       " (PIN: 0x%x) rev. %hu, at %s MHz\n",
-		       pin, prn, strmhz(buf, CONFIG_SYS_CLK));
+		       pin, prn, strmhz(buf, CFG_SYS_CLK));
 
 	return 0;
 }
@@ -253,7 +253,7 @@
 
 	/* set timeout and enable watchdog */
 	out_be16(&wdt->wdog_wrrr,
-		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+		(CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
 
 	/* reset watchdog counter */
 	out_be16(&wdt->wdog_wcr, 0);
@@ -284,7 +284,7 @@
 	char buf[32];
 
 	printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
-			strmhz(buf, CONFIG_SYS_CLK));
+			strmhz(buf, CFG_SYS_CLK));
 	return 0;
 };
 #endif /* CONFIG_DISPLAY_CPUINFO */
@@ -323,7 +323,7 @@
 
 	/* set timeout and enable watchdog */
 	out_be16(&wdt->wmr,
-		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+		(CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
 
 	/* reset watchdog counter */
 	out_be16(&wdt->wsr, 0x5555);
@@ -370,7 +370,7 @@
 	char buf[32];
 
 	printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
-	       strmhz(buf, CONFIG_SYS_CLK));
+	       strmhz(buf, CFG_SYS_CLK));
 	return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
@@ -394,7 +394,7 @@
 
 	unsigned char resetsource = mbar_readLong(SIM_RSR);
 	printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
-	       strmhz(buf, CONFIG_SYS_CLK));
+	       strmhz(buf, CFG_SYS_CLK));
 
 	if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
 		printf("Reset:%s%s\n",

diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index 9d4a10f..99eb61f 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c

@@ -36,31 +36,31 @@
 {
 	fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
-     && defined(CONFIG_SYS_CS0_CTRL))
-	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+     && defined(CFG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #else
 #warning "Chip Select 0 are not initialized/used"
 #endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
-     && defined(CONFIG_SYS_CS1_CTRL))
-	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+     && defined(CFG_SYS_CS1_CTRL))
+	out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
-     && defined(CONFIG_SYS_CS2_CTRL))
-	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+     && defined(CFG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
-     && defined(CONFIG_SYS_CS3_CTRL))
-	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+     && defined(CFG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
@@ -214,9 +214,9 @@
 	init_fbcs();
 
 #ifdef CONFIG_SYS_I2C_FSL
-	CONFIG_SYS_I2C_PINMUX_REG =
-	    CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
-	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+	CFG_SYS_I2C_PINMUX_REG =
+	    CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR;
+	CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
 #ifdef CONFIG_SYS_I2C2_OFFSET
 	CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
 	CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
@@ -335,21 +335,21 @@
 	 * already initialized.
 	 */
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+	sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR);
 	gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
 	csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
 
-	out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
-	out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
+	out_be16(&sysctrl->sc_scr, CFG_SYS_SCR);
+	out_be16(&sysctrl->sc_spr, CFG_SYS_SPR);
 
 	/* Setup Ports: */
-	out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
-	out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
-	out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
-	out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
-	out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
-	out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
-	out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
+	out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT);
+	out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR);
+	out_be16(&gpio->gpio_padat, CFG_SYS_PADAT);
+	out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT);
+	out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR);
+	out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT);
+	out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT);
 
 	/* Memory Controller: */
 	out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
@@ -472,8 +472,8 @@
 #endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 
 #ifdef CONFIG_SYS_I2C_FSL
-	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
-	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+	CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+	CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
 #endif
 
 	/* enable instruction cache now */
@@ -560,8 +560,8 @@
 #ifndef CONFIG_MONITOR_IS_IN_RAM
 	/* Set speed /PLL */
 	MCFCLOCK_SYNCR =
-	    MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
-	    MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+	    MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) |
+	    MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD);
 	while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
 
 	MCFGPIO_PBCDPAR = 0xc0;
@@ -573,17 +573,17 @@
 #ifdef	CONFIG_SYS_PFPAR
 	MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
 #endif
-#ifdef CONFIG_SYS_PJPAR
-	MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
+#ifdef CFG_SYS_PJPAR
+	MCFGPIO_PJPAR = CFG_SYS_PJPAR;
 #endif
 #ifdef CONFIG_SYS_PSDPAR
 	MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
 #endif
-#ifdef CONFIG_SYS_PASPAR
-	MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
+#ifdef CFG_SYS_PASPAR
+	MCFGPIO_PASPAR = CFG_SYS_PASPAR;
 #endif
-#ifdef CONFIG_SYS_PEHLPAR
-	MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+#ifdef CFG_SYS_PEHLPAR
+	MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
 #endif
 #ifdef CONFIG_SYS_PQSPAR
 	MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
@@ -600,15 +600,15 @@
 #ifdef CONFIG_SYS_PTDPAR
 	MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
 #endif
-#ifdef CONFIG_SYS_PUAPAR
-	MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
+#ifdef CFG_SYS_PUAPAR
+	MCFGPIO_PUAPAR = CFG_SYS_PUAPAR;
 #endif
 
 #if defined(CONFIG_SYS_DDRD)
 	MCFGPIO_DDRD = CONFIG_SYS_DDRD;
 #endif
-#ifdef CONFIG_SYS_DDRUA
-	MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
+#ifdef CFG_SYS_DDRUA
+	MCFGPIO_DDRUA = CFG_SYS_DDRUA;
 #endif
 
 	/* FlexBus Chipselect */
@@ -652,10 +652,10 @@
 {
 	if (setclear) {
 		MCFGPIO_PASPAR |= 0x0F00;
-		MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+		MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
 	} else {
 		MCFGPIO_PASPAR &= 0xF0FF;
-		MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+		MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR;
 	}
 	return 0;
 }
@@ -678,12 +678,12 @@
 	 *        which is their primary function.
 	 *        ~Jeremy
 	 */
-	mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
-	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
-	mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
-	mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
-	mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
-	mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
+	mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC);
+	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC);
+	mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN);
+	mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN);
+	mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT);
+	mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT);
 
 	/*
 	 *  dBug Compliance:

diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c
index 045908a..6c76282 100644
--- a/arch/m68k/cpu/mcf52x2/speed.c
+++ b/arch/m68k/cpu/mcf52x2/speed.c

@@ -23,19 +23,19 @@
 #if defined(CONFIG_M5208)
 	pll_t *pll = (pll_t *) MMAP_PLL;
 
-	out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
-	out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
+	out_8(&pll->odr, CFG_SYS_PLL_ODR);
+	out_8(&pll->fdr, CFG_SYS_PLL_FDR);
 #endif
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
 	unsigned long pllcr;
 
-#ifndef CONFIG_SYS_PLL_BYPASS
+#ifndef CFG_SYS_PLL_BYPASS
 
 #ifdef CONFIG_M5249
 	/* Setup the PLL to run at the specified speed */
-#ifdef CONFIG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
 	pllcr = 0x925a3100;	/* ~140MHz clock (PLL bypass = 0) */
 #else
 	pllcr = 0x135a4140;	/* ~72MHz clock (PLL bypass = 0) */
@@ -43,7 +43,7 @@
 #endif				/* CONFIG_M5249 */
 
 #ifdef CONFIG_M5253
-	pllcr = CONFIG_SYS_PLLCR;
+	pllcr = CFG_SYS_PLLCR;
 #endif				/* CONFIG_M5253 */
 
 	cpll = cpll & 0xfffffffe;	/* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -52,7 +52,7 @@
 	pllcr ^= 0x00000001;	/* Set pll bypass to 1 */
 	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* Start locking (pll bypass = 1) */
 	udelay(0x20);		/* Wait for a lock ... */
-#endif				/* #ifndef CONFIG_SYS_PLL_BYPASS */
+#endif				/* #ifndef CFG_SYS_PLL_BYPASS */
 
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
 
@@ -68,7 +68,7 @@
 		;
 #endif
 
-	gd->cpu_clk = CONFIG_SYS_CLK;
+	gd->cpu_clk = CFG_SYS_CLK;
 #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;

diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 6dddbe7..d48d019 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S

@@ -35,7 +35,7 @@
  */
 _vectors:
 .long	0x00000000		/* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
 .long	_start - CONFIG_TEXT_BASE
 #else
 .long	_START
@@ -81,9 +81,9 @@
 
 .text
 
-#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
+#if defined(CFG_SYS_INT_FLASH_BASE) && \
     (defined(CONFIG_M5282) || defined(CONFIG_M5281))
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
 .long	0x55AA55AA,0xAA55AA55		/* CFM Backdoorkey */
 .long	0xFFFFFFFF			/* all sectors protected */
 .long	0x00000000			/* supervisor/User restriction */
@@ -100,53 +100,53 @@
 
 #if defined(CONFIG_M5208)
 	/* Initialize RAMBAR: locate SRAM and validate it */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 #endif
 
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	/* set MBAR address + valid flag */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	#(CFG_SYS_MBAR + 1), %d0
 	move.c	%d0, %MBAR
 
 	/*** The 5249 has MBAR2 as well ***/
-#ifdef CONFIG_SYS_MBAR2
+#ifdef CFG_SYS_MBAR2
 	/* Get MBAR2 address */
-	move.l	#(CONFIG_SYS_MBAR2 + 1), %d0
+	move.l	#(CFG_SYS_MBAR2 + 1), %d0
 	 /* Set MBAR2 */
 	movec	%d0, #0xc0e
 #endif
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + 1), %d0
 	movec	%d0, %RAMBAR0
 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
 
 #if defined(CONFIG_M5282) || defined(CONFIG_M5271)
 	/* set MBAR address + valid flag */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	#(CFG_SYS_MBAR + 1), %d0
 	move.l	%d0, 0x40000000
 
 	/* Initialize RAMBAR1: locate SRAM and validate it */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
 	movec	%d0, %RAMBAR1
 
 #if defined(CONFIG_M5282)
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
 	/*
 	 * Setup code in SRAM to initialize FLASHBAR,
 	 * if start from internal Flash
 	 */
-	move.l	#(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
-	move.l	#(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR), %a2
+	move.l	#(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0
+	move.l	#(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1
+	move.l	#(CFG_SYS_INIT_RAM_ADDR), %a2
 _copy_flash:
 	move.l	(%a0)+, (%a2)+
 	cmp.l	%a0, %a1
 	bgt.s	_copy_flash
-	jmp	CONFIG_SYS_INIT_RAM_ADDR
+	jmp	CFG_SYS_INIT_RAM_ADDR
 
 _flashbar_setup:
 	/* Initialize FLASHBAR: locate internal Flash and validate it */
-	move.l	#(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+	move.l	#(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
 	movec	%d0, %FLASHBAR
 	jmp	_after_flashbar_copy.L	/* Force jump to absolute address */
 _flashbar_setup_end:
@@ -154,9 +154,9 @@
 _after_flashbar_copy:
 #else
 	/* Setup code to initialize FLASHBAR, if start from external Memory */
-	move.l	#(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+	move.l	#(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
 	movec	%d0, %FLASHBAR
-#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
+#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */
 
 #endif
 #endif
@@ -165,22 +165,22 @@
 	 * therefore no VBR to set
 	 */
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
-	move.l	#CONFIG_SYS_INT_FLASH_BASE, %d0
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
+	move.l	#CFG_SYS_INT_FLASH_BASE, %d0
 #else
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 #endif
 	movec	%d0, %VBR
 #endif
 
 #ifdef CONFIG_M5275
 	/* set MBAR address + valid flag */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	#(CFG_SYS_MBAR + 1), %d0
 	move.l	%d0, 0x40000000
 /*	movec	%d0, %MBAR */
 
 	/* Initialize RAMBAR: locate SRAM and validate it */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
 	movec	%d0, %RAMBAR1
 #endif
 
@@ -195,7 +195,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,

diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c
index 0659bf6..53a25d8 100644
--- a/arch/m68k/cpu/mcf530x/cpu.c
+++ b/arch/m68k/cpu/mcf530x/cpu.c

@@ -33,7 +33,7 @@
 	char buf[32];
 
 	printf("CPU:   Freescale Coldfire MCF5307 at %s MHz\n",
-	       strmhz(buf, CONFIG_SYS_CPU_CLK));
+	       strmhz(buf, CFG_SYS_CPU_CLK));
 	return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */

diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c
index 8352940..dad47d8 100644
--- a/arch/m68k/cpu/mcf530x/cpu_init.c
+++ b/arch/m68k/cpu/mcf530x/cpu_init.c

@@ -40,35 +40,35 @@
 {
 	csm_t *csm = (csm_t *)(MMAP_CSM);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
-	defined(CONFIG_SYS_CS0_CTRL))
-	out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
-	out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
-	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \
+	defined(CFG_SYS_CS0_CTRL))
+	out_be16(&csm->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&csm->csmr0, CFG_SYS_CS0_MASK);
+	out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL);
+	MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0);
 #else
 #warning "Chip Select 0 are not initialized/used"
 #endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
-	defined(CONFIG_SYS_CS1_CTRL))
-	out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
-	out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
-	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \
+	defined(CFG_SYS_CS1_CTRL))
+	out_be16(&csm->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&csm->csmr1, CFG_SYS_CS1_MASK);
+	out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL);
+	MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1);
 #endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
-	defined(CONFIG_SYS_CS2_CTRL))
-	out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
-	out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
-	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \
+	defined(CFG_SYS_CS2_CTRL))
+	out_be16(&csm->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&csm->csmr2, CFG_SYS_CS2_MASK);
+	out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL);
+	MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2);
 #endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
-	defined(CONFIG_SYS_CS3_CTRL))
-	out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
-	out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
-	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \
+	defined(CFG_SYS_CS3_CTRL))
+	out_be16(&csm->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&csm->csmr3, CFG_SYS_CS3_MASK);
+	out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL);
+	MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3);
 #endif
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
 	defined(CONFIG_SYS_CS4_CTRL))

diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c
index 03d9abe..c8d0790 100644
--- a/arch/m68k/cpu/mcf530x/speed.c
+++ b/arch/m68k/cpu/mcf530x/speed.c

@@ -16,8 +16,8 @@
 int get_clocks(void)
 {
 #if defined(CONFIG_M5307)
-	gd->bus_clk = CONFIG_SYS_CLK;
-	gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+	gd->bus_clk = CFG_SYS_CLK;
+	gd->cpu_clk = CFG_SYS_CPU_CLK;
 #endif
 
 	return 0;

diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index 644c372..dbe2b54 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S

@@ -39,7 +39,7 @@
 /* Flash offset is 0 until we setup CS0 */
 .long	0x00000000
 #if defined(CONFIG_M5307) && \
-	   (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+	   (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
 .long	_start - CONFIG_TEXT_BASE
 #else
 .long	_START
@@ -92,10 +92,10 @@
 	move.w	#0x2700,%sr
 
 	/* set MBAR address + valid flag */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0
+	move.l	#(CFG_SYS_MBAR + 1), %d0
 	move.c	%d0, %MBAR
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + 1), %d0
 	move.c	%d0, %RAMBAR
 
 	/* DS 4.8.2 (Cache Organization) invalidate and disable cache */
@@ -110,7 +110,7 @@
 	 * therefore no VBR to set
 	 */
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 #endif
 
@@ -125,7 +125,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,

diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c
index 1dadffd..548cbca 100644
--- a/arch/m68k/cpu/mcf532x/cpu.c
+++ b/arch/m68k/cpu/mcf532x/cpu.c

@@ -131,7 +131,7 @@
 	u32 wdog_module = 0;
 
 	/* set timeout and enable watchdog */
-	wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
+	wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT_MSECS);
 #ifdef CONFIG_M5329
 	out_be16(&wdp->mr, wdog_module / 8192);
 #else

diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c
index 1311f39..844d2cd 100644
--- a/arch/m68k/cpu/mcf532x/cpu_init.c
+++ b/arch/m68k/cpu/mcf532x/cpu_init.c

@@ -37,34 +37,34 @@
 	out_be32(&scm1->pacrf, 0);
 	out_be32(&scm1->pacrg, 0);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
-     && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+     && defined(CFG_SYS_CS0_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
-	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+	out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
-     && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+     && defined(CFG_SYS_CS1_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
-	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+	out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
-     && defined(CONFIG_SYS_CS2_CTRL))
-	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+     && defined(CFG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
-     && defined(CONFIG_SYS_CS3_CTRL))
-	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+     && defined(CFG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
@@ -102,8 +102,8 @@
 	rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
 	rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
 
-	out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
-	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
+	out_be32(&rtcex->gocu, CFG_SYS_RTC_CNT);
+	out_be32(&rtcex->gocl, CFG_SYS_RTC_SETUP);
 
 #endif
 #ifdef CONFIG_MCFFEC
@@ -236,36 +236,36 @@
 	/* Port configuration */
 	out_8(&gpio->par_cs, 0);
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
-     && defined(CONFIG_SYS_CS0_CTRL))
-	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+     && defined(CFG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
-     && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+     && defined(CFG_SYS_CS1_CTRL))
 	/* Latch chipselect */
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
-	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+	out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
-     && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+     && defined(CFG_SYS_CS2_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
-	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+	out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
-     && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+     && defined(CFG_SYS_CS3_CTRL))
 	setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
-	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+	out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
@@ -327,7 +327,7 @@
 		clrbits_8(&gpio->par_feci2c, 0x00ff);
 		setbits_8(&gpio->par_feci2c,
 			GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
-#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
+#elif defined(CFG_SYS_UART2_ALT3_GPIO)
 		clrbits_be16(&gpio->par_ssi, 0x0f00);
 		setbits_be16(&gpio->par_ssi,
 			GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));

diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c
index e298579..32ffac08 100644
--- a/arch/m68k/cpu/mcf532x/speed.c
+++ b/arch/m68k/cpu/mcf532x/speed.c

@@ -239,7 +239,7 @@
 	 * software workaround for SDRAM opeartion after exiting LIMP
 	 * mode errata
 	 */
-	out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
+	out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE);
 #endif
 
 	/* wait for DQS logic to relock */
@@ -252,7 +252,7 @@
 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
 int get_clocks(void)
 {
-	gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
+	gd->bus_clk = clock_pll(CFG_SYS_CLK / 1000, 0) * 1000;
 	gd->cpu_clk = (gd->bus_clk * 3);
 
 #ifdef CONFIG_SYS_I2C_FSL

diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index 2672891..72a2f99 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S

@@ -98,11 +98,11 @@
 
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 	/* Set vector base register at the beginning of the Flash */
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 #endif
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
@@ -131,7 +131,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l  #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,

diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 9b3f9f0..1ce2448 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c

@@ -29,30 +29,30 @@
 	fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
 
 #if !defined(CONFIG_SERIAL_BOOT)
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
-	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+	out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
 #endif
 #endif
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
 	/* Latch chipselect */
-	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
-	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+	out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
-	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
-	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
+	out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
-	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
-	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
+	out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
@@ -208,14 +208,14 @@
 	/* FlexBus Chipselect */
 	init_fbcs();
 
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
 	/*
 	 * now the flash base address is no longer at 0 (Newer ColdFire family
 	 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
 	 * also move to the new location.
 	 */
-	if (CONFIG_SYS_CS0_BASE != 0)
-		setvbr(CONFIG_SYS_CS0_BASE);
+	if (CFG_SYS_CS0_BASE != 0)
+		setvbr(CFG_SYS_CS0_BASE);
 #endif
 
 	icache_enable();

diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index aea8f30..a083c3d 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S

@@ -27,10 +27,10 @@
 
 #if defined(CONFIG_SERIAL_BOOT)
 #define ASM_DRAMINIT	(asm_dram_init - CONFIG_TEXT_BASE + \
-	CONFIG_SYS_INIT_RAM_ADDR)
+	CFG_SYS_INIT_RAM_ADDR)
 #define ASM_DRAMINIT_N	(asm_dram_init - CONFIG_TEXT_BASE)
 #define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_TEXT_BASE + \
-	CONFIG_SYS_INIT_RAM_ADDR)
+	CFG_SYS_INIT_RAM_ADDR)
 #endif
 
 .text
@@ -123,18 +123,18 @@
 
 #ifdef CONFIG_SYS_NAND_BOOT
 	/* for assembly stack */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
 	clr.l	%sp@-
 #endif
 
 #ifdef CONFIG_CF_SBF
-	move.l	#CONFIG_SYS_INIT_RAM_ADDR, %d0
+	move.l	#CFG_SYS_INIT_RAM_ADDR, %d0
 	movec	%d0, %VBR
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
 	/* initialize general use internal ram */
@@ -145,7 +145,7 @@
 	move.l	%d0, (%a2)
 
 	/* invalidate and disable cache */
-	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+	move.l	#(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
 	movec	%d0, %CACR		/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -153,17 +153,17 @@
 	movec	%d0, %ACR2
 	movec	%d0, %ACR3
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
 	clr.l	%sp@-
 
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
 	/* Must disable global address */
 	move.l	#0xFC008000, %a1
-	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#(CFG_SYS_CS0_BASE), (%a1)
 	move.l	#0xFC008008, %a1
-	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#(CFG_SYS_CS0_CTRL), (%a1)
 	move.l	#0xFC008004, %a1
-	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+	move.l	#(CFG_SYS_CS0_MASK), (%a1)
 #endif
 #endif /* CONFIG_CF_SBF */
 
@@ -216,8 +216,8 @@
 	move.l	(%a1)+, %d5
 	move.l	(%a1), %a4
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
-	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0
+	move.l	#(CFG_SYS_SBFHDR_SIZE), %d4
 
 	move.l	#0xFC05C02C, %a1	/* dspi status */
 
@@ -334,14 +334,14 @@
 	movec	%d0, %ACR2
 	movec	%d0, %ACR3
 
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
 	/* Must disable global address */
 	move.l	#0xFC008000, %a1
-	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#(CFG_SYS_CS0_BASE), (%a1)
 	move.l	#0xFC008008, %a1
-	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#(CFG_SYS_CS0_CTRL), (%a1)
 	move.l	#0xFC008004, %a1
-	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+	move.l	#(CFG_SYS_CS0_MASK), (%a1)
 #endif
 
 	/* NAND port configuration */
@@ -442,10 +442,10 @@
 	move.w	#0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
+	move.l	#CFG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
 	/* initialize general use internal ram */
@@ -456,7 +456,7 @@
 	move.l	%d0, (%a2)
 
 	/* invalidate and disable cache */
-	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+	move.l	#(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
 	movec	%d0, %CACR		/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -464,7 +464,7 @@
 	movec	%d0, %ACR2
 	movec	%d0, %ACR3
 #else
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 #endif
 
@@ -472,7 +472,7 @@
 	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,

diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index ceb462f..c05356f 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h

@@ -135,28 +135,28 @@
 #endif				/* CONFIG_CF_V4 */
 
 
-#ifndef CONFIG_SYS_CACHE_ICACR
-#define CONFIG_SYS_CACHE_ICACR	0
+#ifndef CFG_SYS_CACHE_ICACR
+#define CFG_SYS_CACHE_ICACR	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_DCACR
-#ifdef CONFIG_SYS_CACHE_ICACR
-#define CONFIG_SYS_CACHE_DCACR	CONFIG_SYS_CACHE_ICACR
+#ifndef CFG_SYS_CACHE_DCACR
+#ifdef CFG_SYS_CACHE_ICACR
+#define CFG_SYS_CACHE_DCACR	CFG_SYS_CACHE_ICACR
 #else
-#define CONFIG_SYS_CACHE_DCACR	0
+#define CFG_SYS_CACHE_DCACR	0
 #endif
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR0
-#define CONFIG_SYS_CACHE_ACR0	0
+#ifndef CFG_SYS_CACHE_ACR0
+#define CFG_SYS_CACHE_ACR0	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR1
-#define CONFIG_SYS_CACHE_ACR1	0
+#ifndef CFG_SYS_CACHE_ACR1
+#define CFG_SYS_CACHE_ACR1	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR2
-#define CONFIG_SYS_CACHE_ACR2	0
+#ifndef CFG_SYS_CACHE_ACR2
+#define CFG_SYS_CACHE_ACR2	0
 #endif
 
 #ifndef CONFIG_SYS_CACHE_ACR3

diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index ead62cd..dab8b26 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h

@@ -14,7 +14,7 @@
 #include <asm/m520x.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -37,7 +37,7 @@
 #include <asm/m5235.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -59,7 +59,7 @@
 #include <asm/immap_5249.h>
 #include <asm/m5249.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
 #define CONFIG_SYS_NUM_IRQS		(64)
@@ -82,7 +82,7 @@
 #include <asm/m5249.h>
 #include <asm/m5253.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
 #define CONFIG_SYS_NUM_IRQS		(64)
@@ -105,7 +105,7 @@
 #include <asm/m5271.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -128,7 +128,7 @@
 #include <asm/m5272.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
 #define CONFIG_SYS_NUM_IRQS		(64)
@@ -152,7 +152,7 @@
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(192)
@@ -175,7 +175,7 @@
 #include <asm/m5282.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
 #define CONFIG_SYS_NUM_IRQS		(128)
@@ -198,7 +198,7 @@
 #include <asm/m5307.h>
 
 #define CONFIG_SYS_UART_BASE            (MMAP_UART0 + \
-					(CONFIG_SYS_UART_PORT * 0x40))
+					(CFG_SYS_UART_PORT * 0x40))
 #define CONFIG_SYS_INTR_BASE            (MMAP_INTC)
 #define CONFIG_SYS_NUM_IRQS             (64)
 
@@ -223,7 +223,7 @@
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -246,7 +246,7 @@
 #include <asm/m5329.h>
 
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
@@ -271,12 +271,12 @@
 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
 
-#if (CONFIG_SYS_UART_PORT < 4)
+#if (CFG_SYS_UART_PORT < 4)
 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + \
-					(CONFIG_SYS_UART_PORT * 0x4000))
+					(CFG_SYS_UART_PORT * 0x4000))
 #else
 #define CONFIG_SYS_UART_BASE		(MMAP_UART4 + \
-					((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+					((CFG_SYS_UART_PORT - 4) * 0x4000))
 #endif
 
 #define MMAP_DSPI			MMAP_DSPI0
@@ -320,7 +320,7 @@
 #define FEC1_TX_INIT		31
 #endif
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
 
 #ifdef CONFIG_SLTTMR
 #define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
@@ -337,10 +337,10 @@
 #define CONFIG_SYS_NUM_IRQS		(128)
 
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_BAR0		(0x40000000)
-#define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_BAR0		(0x40000000)
+#define CFG_SYS_PCI_BAR1		(CFG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_TBATR0		(CFG_SYS_MBAR)
+#define CFG_SYS_PCI_TBATR1		(CFG_SYS_SDRAM_BASE)
 #endif
 #endif				/* CONFIG_M547x */
 

diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h
index bb12374..7c7443b 100644
--- a/arch/m68k/include/asm/immap_520x.h
+++ b/arch/m68k/include/asm/immap_520x.h

@@ -9,32 +9,32 @@
 #ifndef __IMMAP_520X__
 #define __IMMAP_520X__
 
-#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00030000)
-#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040000)
-#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_EPORT0	(CONFIG_SYS_MBAR + 0x00088000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x0008C000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000A8000)
+#define MMAP_SCM1	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS	(CFG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00008000)
+#define MMAP_FEC0	(CFG_SYS_MBAR + 0x00030000)
+#define MMAP_SCM2	(CFG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA	(CFG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00048000)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00058000)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00084000)
+#define MMAP_EPORT0	(CFG_SYS_MBAR + 0x00088000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x0008C000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00090000)
+#define MMAP_RCM	(CFG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x000A4000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x000A8000)
 
 #include <asm/coldfire/crossbar.h>
 #include <asm/coldfire/edma.h>

diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h
index 27d905e..a1825c2 100644
--- a/arch/m68k/include/asm/immap_5235.h
+++ b/arch/m68k/include/asm/immap_5235.h

@@ -9,42 +9,42 @@
 #ifndef __IMMAP_5235__
 #define __IMMAP_5235__
 
-#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_ETPU	(CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
+#define MMAP_SCM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1	(CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU	(CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2	(CFG_SYS_MBAR + 0x001F0000)
 
 #include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>

diff --git a/arch/m68k/include/asm/immap_5249.h b/arch/m68k/include/asm/immap_5249.h
index b599ca6..aa4c3ef 100644
--- a/arch/m68k/include/asm/immap_5249.h
+++ b/arch/m68k/include/asm/immap_5249.h

@@ -8,13 +8,13 @@
 #ifndef __IMMAP_5249__
 #define __IMMAP_5249__
 
-#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1		(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_QSPI		(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_INTC		(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0		(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0		(CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1		(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_QSPI		(CFG_SYS_MBAR + 0x00000400)
 
 #include <asm/coldfire/flexbus.h>
 #include <asm/coldfire/qspi.h>

diff --git a/arch/m68k/include/asm/immap_5253.h b/arch/m68k/include/asm/immap_5253.h
index 883782a..1ab7243 100644
--- a/arch/m68k/include/asm/immap_5253.h
+++ b/arch/m68k/include/asm/immap_5253.h

@@ -9,20 +9,20 @@
 #ifndef __IMMAP_5253__
 #define __IMMAP_5253__
 
-#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1		(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_I2C0		(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_QSPI		(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_CAN0		(CONFIG_SYS_MBAR + 0x00010000)
-#define MMAP_CAN1		(CONFIG_SYS_MBAR + 0x00011000)
+#define MMAP_INTC		(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0		(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0		(CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1		(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_I2C0		(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_QSPI		(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_CAN0		(CFG_SYS_MBAR + 0x00010000)
+#define MMAP_CAN1		(CFG_SYS_MBAR + 0x00011000)
 
-#define MMAP_PAR		(CONFIG_SYS_MBAR2 + 0x0000019C)
-#define MMAP_I2C1		(CONFIG_SYS_MBAR2 + 0x00000440)
-#define MMAP_UART2		(CONFIG_SYS_MBAR2 + 0x00000C00)
+#define MMAP_PAR		(CFG_SYS_MBAR2 + 0x0000019C)
+#define MMAP_I2C1		(CFG_SYS_MBAR2 + 0x00000440)
+#define MMAP_UART2		(CFG_SYS_MBAR2 + 0x00000C00)
 
 #include <asm/coldfire/ata.h>
 #include <asm/coldfire/flexbus.h>

diff --git a/arch/m68k/include/asm/immap_5271.h b/arch/m68k/include/asm/immap_5271.h
index 27d7861..a5bf18c 100644
--- a/arch/m68k/include/asm/immap_5271.h
+++ b/arch/m68k/include/asm/immap_5271.h

@@ -9,42 +9,42 @@
 #ifndef __IMMAP_5271__
 #define __IMMAP_5271__
 
-#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_ETPU	(CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
+#define MMAP_SCM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1	(CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU	(CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2	(CFG_SYS_MBAR + 0x001F0000)
 
 #include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>

diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h
index cd7b672..c5c3cc7 100644
--- a/arch/m68k/include/asm/immap_5272.h
+++ b/arch/m68k/include/asm/immap_5272.h

@@ -8,24 +8,24 @@
 #ifndef __IMMAP_5272__
 #define __IMMAP_5272__
 
-#define MMAP_CFG	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_INTC	(CONFIG_SYS_MBAR + 0x00000020)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x000000A0)
-#define MMAP_PWM	(CONFIG_SYS_MBAR + 0x000000C0)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x000000E0)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_TMR0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_TMR1	(CONFIG_SYS_MBAR + 0x00000220)
-#define MMAP_TMR2	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_TMR3	(CONFIG_SYS_MBAR + 0x00000260)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_PLIC	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00000840)
-#define MMAP_USB	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_CFG	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC	(CFG_SYS_MBAR + 0x00000020)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x000000A0)
+#define MMAP_PWM	(CFG_SYS_MBAR + 0x000000C0)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x000000E0)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_TMR0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_TMR1	(CFG_SYS_MBAR + 0x00000220)
+#define MMAP_TMR2	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_TMR3	(CFG_SYS_MBAR + 0x00000260)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_PLIC	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_FEC	(CFG_SYS_MBAR + 0x00000840)
+#define MMAP_USB	(CFG_SYS_MBAR + 0x00001000)
 
 #include <asm/coldfire/pwm.h>
 

diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h
index 8b1a08b..9b8d71d 100644
--- a/arch/m68k/include/asm/immap_5275.h
+++ b/arch/m68k/include/asm/immap_5275.h

@@ -10,44 +10,44 @@
 #ifndef __IMMAP_5275__
 #define __IMMAP_5275__
 
-#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FEC0FIFO	(CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00001800)
-#define MMAP_FEC1FIFO	(CONFIG_SYS_MBAR + 0x00001C00)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110004)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_USB	(CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_PWM0	(CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_SCM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC0	(CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FEC0FIFO	(CFG_SYS_MBAR + 0x00001400)
+#define MMAP_FEC1	(CFG_SYS_MBAR + 0x00001800)
+#define MMAP_FEC1FIFO	(CFG_SYS_MBAR + 0x00001C00)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00100000)
+#define MMAP_RCM	(CFG_SYS_MBAR + 0x00110000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x00110004)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_USB	(CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_PWM0	(CFG_SYS_MBAR + 0x001D0000)
 
 #include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>

diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h
index d7c68f5..f810a4d 100644
--- a/arch/m68k/include/asm/immap_5282.h
+++ b/arch/m68k/include/asm/immap_5282.h

@@ -8,42 +8,42 @@
 #ifndef __IMMAP_5282__
 #define __IMMAP_5282__
 
-#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAMC	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_QADC	(CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_GPTMRA	(CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_GPTMRB	(CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN	(CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_CFMC	(CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CFMMEM	(CONFIG_SYS_MBAR + 0x04000000)
+#define MMAP_SCM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAMC	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DMA2	(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_DMA3	(CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x00180000)
+#define MMAP_QADC	(CFG_SYS_MBAR + 0x00190000)
+#define MMAP_GPTMRA	(CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_GPTMRB	(CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN	(CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_CFMC	(CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CFMMEM	(CFG_SYS_MBAR + 0x04000000)
 
 #include <asm/coldfire/eport.h>
 #include <asm/coldfire/flexbus.h>

diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h
index 29e6086..e1f7858 100644
--- a/arch/m68k/include/asm/immap_5301x.h
+++ b/arch/m68k/include/asm/immap_5301x.h

@@ -9,46 +9,46 @@
 #ifndef __IMMAP_5301X__
 #define __IMMAP_5301X__
 
-#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_MPU	(CONFIG_SYS_MBAR + 0x00014000)
-#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00030000)
-#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00034000)
-#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040000)
-#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x0004C000)
-#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_DSPI	(CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00088000)
-#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x0008C000)
-#define MMAP_EPORT0	(CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_EPORT1	(CONFIG_SYS_MBAR + 0x00094000)
-#define MMAP_VOICOD	(CONFIG_SYS_MBAR + 0x0009C000)
-#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_RTC	(CONFIG_SYS_MBAR + 0x000A8000)
-#define MMAP_SIM	(CONFIG_SYS_MBAR + 0x000AC000)
-#define MMAP_USBOTG	(CONFIG_SYS_MBAR + 0x000B0000)
-#define MMAP_USBH	(CONFIG_SYS_MBAR + 0x000B4000)
-#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000B8000)
-#define MMAP_SSI	(CONFIG_SYS_MBAR + 0x000BC000)
-#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x000C0000)
-#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x000C4000)
-#define MMAP_IIM	(CONFIG_SYS_MBAR + 0x000C8000)
-#define MMAP_ESDHC	(CONFIG_SYS_MBAR + 0x000CC000)
+#define MMAP_SCM1	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS	(CFG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS	(CFG_SYS_MBAR + 0x00008000)
+#define MMAP_MPU	(CFG_SYS_MBAR + 0x00014000)
+#define MMAP_FEC0	(CFG_SYS_MBAR + 0x00030000)
+#define MMAP_FEC1	(CFG_SYS_MBAR + 0x00034000)
+#define MMAP_SCM2	(CFG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA	(CFG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0	(CFG_SYS_MBAR + 0x00048000)
+#define MMAP_INTC1	(CFG_SYS_MBAR + 0x0004C000)
+#define MMAP_INTCACK	(CFG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C	(CFG_SYS_MBAR + 0x00058000)
+#define MMAP_DSPI	(CFG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2	(CFG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CFG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CFG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CFG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1	(CFG_SYS_MBAR + 0x00084000)
+#define MMAP_PIT2	(CFG_SYS_MBAR + 0x00088000)
+#define MMAP_PIT3	(CFG_SYS_MBAR + 0x0008C000)
+#define MMAP_EPORT0	(CFG_SYS_MBAR + 0x00090000)
+#define MMAP_EPORT1	(CFG_SYS_MBAR + 0x00094000)
+#define MMAP_VOICOD	(CFG_SYS_MBAR + 0x0009C000)
+#define MMAP_RCM	(CFG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM	(CFG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x000A4000)
+#define MMAP_RTC	(CFG_SYS_MBAR + 0x000A8000)
+#define MMAP_SIM	(CFG_SYS_MBAR + 0x000AC000)
+#define MMAP_USBOTG	(CFG_SYS_MBAR + 0x000B0000)
+#define MMAP_USBH	(CFG_SYS_MBAR + 0x000B4000)
+#define MMAP_SDRAM	(CFG_SYS_MBAR + 0x000B8000)
+#define MMAP_SSI	(CFG_SYS_MBAR + 0x000BC000)
+#define MMAP_PLL	(CFG_SYS_MBAR + 0x000C0000)
+#define MMAP_RNG	(CFG_SYS_MBAR + 0x000C4000)
+#define MMAP_IIM	(CFG_SYS_MBAR + 0x000C8000)
+#define MMAP_ESDHC	(CFG_SYS_MBAR + 0x000CC000)
 
 #include <asm/coldfire/crossbar.h>
 #include <asm/coldfire/dspi.h>

diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h
index 930e089..d6442d9 100644
--- a/arch/m68k/include/asm/immap_5307.h
+++ b/arch/m68k/include/asm/immap_5307.h

@@ -7,15 +7,15 @@
 #ifndef __IMMAP_5307__
 #define __IMMAP_5307__
 
-#define MMAP_SIM	(CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_INTC	(CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_CSM	(CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DRAMC	(CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000244)
+#define MMAP_SIM	(CFG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC	(CFG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM	(CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DRAMC	(CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DTMR0	(CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1	(CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0	(CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1	(CFG_SYS_MBAR + 0x00000200)
+#define MMAP_GPIO	(CFG_SYS_MBAR + 0x00000244)
 
 typedef struct sim {
 	u8  rsr;

diff --git a/arch/m68k/include/asm/m5249.h b/arch/m68k/include/asm/m5249.h
index 9303629..afafb4e 100644
--- a/arch/m68k/include/asm/m5249.h
+++ b/arch/m68k/include/asm/m5249.h

@@ -14,14 +14,14 @@
 /*
  * useful definitions for reading/writing MBAR offset memory
  */
-#define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
-#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar2_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x))
-#define mbar2_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y
-#define mbar2_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y
-#define mbar2_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y
+#define mbar_readLong(x)	*((volatile unsigned long *) (CFG_SYS_MBAR + x))
+#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
+#define mbar2_readLong(x)	*((volatile unsigned long *) (CFG_SYS_MBAR2 + x))
+#define mbar2_writeLong(x,y)	*((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y
+#define mbar2_writeShort(x,y)	*((volatile unsigned short *) (CFG_SYS_MBAR2 + x)) = y
+#define mbar2_writeByte(x,y)	*((volatile unsigned char *) (CFG_SYS_MBAR2 + x)) = y
 
 /*
  * Size of internal RAM

diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h
index 7ebeddb..e63b42c 100644
--- a/arch/m68k/include/asm/m5271.h
+++ b/arch/m68k/include/asm/m5271.h

@@ -11,12 +11,12 @@
 #ifndef	_MCF5271_H_
 #define	_MCF5271_H_
 
-#define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
-#define mbar_readShort(x)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
-#define mbar_readByte(x)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
-#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_readLong(x)	*((volatile unsigned long *) (CFG_SYS_MBAR + x))
+#define mbar_readShort(x)	*((volatile unsigned short *) (CFG_SYS_MBAR + x))
+#define mbar_readByte(x)	*((volatile unsigned char *) (CFG_SYS_MBAR + x))
+#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
 
 #define MCF_FMPLL_SYNCR				0x120000
 #define MCF_FMPLL_SYNSR				0x120004

diff --git a/arch/m68k/include/asm/m5282.h b/arch/m68k/include/asm/m5282.h
index 0c91cf4..180f203 100644
--- a/arch/m68k/include/asm/m5282.h
+++ b/arch/m68k/include/asm/m5282.h

@@ -108,112 +108,112 @@
 
 /* General Purpose I/O Module GPIO */
 
-#define MCFGPIO_PORTA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100000))
-#define MCFGPIO_PORTB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100001))
-#define MCFGPIO_PORTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100002))
-#define MCFGPIO_PORTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100003))
-#define MCFGPIO_PORTE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100004))
-#define MCFGPIO_PORTF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100005))
-#define MCFGPIO_PORTG		(*(vu_char *) (CONFIG_SYS_MBAR+0x100006))
-#define MCFGPIO_PORTH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100007))
-#define MCFGPIO_PORTJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100008))
-#define MCFGPIO_PORTDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100009))
-#define MCFGPIO_PORTEH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000A))
-#define MCFGPIO_PORTEL		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000B))
-#define MCFGPIO_PORTAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000C))
-#define MCFGPIO_PORTQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000D))
-#define MCFGPIO_PORTSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000E))
-#define MCFGPIO_PORTTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000F))
-#define MCFGPIO_PORTTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100010))
-#define MCFGPIO_PORTUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100011))
+#define MCFGPIO_PORTA		(*(vu_char *) (CFG_SYS_MBAR+0x100000))
+#define MCFGPIO_PORTB		(*(vu_char *) (CFG_SYS_MBAR+0x100001))
+#define MCFGPIO_PORTC		(*(vu_char *) (CFG_SYS_MBAR+0x100002))
+#define MCFGPIO_PORTD		(*(vu_char *) (CFG_SYS_MBAR+0x100003))
+#define MCFGPIO_PORTE		(*(vu_char *) (CFG_SYS_MBAR+0x100004))
+#define MCFGPIO_PORTF		(*(vu_char *) (CFG_SYS_MBAR+0x100005))
+#define MCFGPIO_PORTG		(*(vu_char *) (CFG_SYS_MBAR+0x100006))
+#define MCFGPIO_PORTH		(*(vu_char *) (CFG_SYS_MBAR+0x100007))
+#define MCFGPIO_PORTJ		(*(vu_char *) (CFG_SYS_MBAR+0x100008))
+#define MCFGPIO_PORTDD		(*(vu_char *) (CFG_SYS_MBAR+0x100009))
+#define MCFGPIO_PORTEH		(*(vu_char *) (CFG_SYS_MBAR+0x10000A))
+#define MCFGPIO_PORTEL		(*(vu_char *) (CFG_SYS_MBAR+0x10000B))
+#define MCFGPIO_PORTAS		(*(vu_char *) (CFG_SYS_MBAR+0x10000C))
+#define MCFGPIO_PORTQS		(*(vu_char *) (CFG_SYS_MBAR+0x10000D))
+#define MCFGPIO_PORTSD		(*(vu_char *) (CFG_SYS_MBAR+0x10000E))
+#define MCFGPIO_PORTTC		(*(vu_char *) (CFG_SYS_MBAR+0x10000F))
+#define MCFGPIO_PORTTD		(*(vu_char *) (CFG_SYS_MBAR+0x100010))
+#define MCFGPIO_PORTUA		(*(vu_char *) (CFG_SYS_MBAR+0x100011))
 
-#define MCFGPIO_DDRA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100014))
-#define MCFGPIO_DDRB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100015))
-#define MCFGPIO_DDRC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100016))
-#define MCFGPIO_DDRD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100017))
-#define MCFGPIO_DDRE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100018))
-#define MCFGPIO_DDRF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100019))
-#define MCFGPIO_DDRG		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001A))
-#define MCFGPIO_DDRH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001B))
-#define MCFGPIO_DDRJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001C))
-#define MCFGPIO_DDRDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001D))
-#define MCFGPIO_DDREH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001E))
-#define MCFGPIO_DDREL		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001F))
-#define MCFGPIO_DDRAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100020))
-#define MCFGPIO_DDRQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100021))
-#define MCFGPIO_DDRSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100022))
-#define MCFGPIO_DDRTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100023))
-#define MCFGPIO_DDRTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100024))
-#define MCFGPIO_DDRUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100025))
+#define MCFGPIO_DDRA		(*(vu_char *) (CFG_SYS_MBAR+0x100014))
+#define MCFGPIO_DDRB		(*(vu_char *) (CFG_SYS_MBAR+0x100015))
+#define MCFGPIO_DDRC		(*(vu_char *) (CFG_SYS_MBAR+0x100016))
+#define MCFGPIO_DDRD		(*(vu_char *) (CFG_SYS_MBAR+0x100017))
+#define MCFGPIO_DDRE		(*(vu_char *) (CFG_SYS_MBAR+0x100018))
+#define MCFGPIO_DDRF		(*(vu_char *) (CFG_SYS_MBAR+0x100019))
+#define MCFGPIO_DDRG		(*(vu_char *) (CFG_SYS_MBAR+0x10001A))
+#define MCFGPIO_DDRH		(*(vu_char *) (CFG_SYS_MBAR+0x10001B))
+#define MCFGPIO_DDRJ		(*(vu_char *) (CFG_SYS_MBAR+0x10001C))
+#define MCFGPIO_DDRDD		(*(vu_char *) (CFG_SYS_MBAR+0x10001D))
+#define MCFGPIO_DDREH		(*(vu_char *) (CFG_SYS_MBAR+0x10001E))
+#define MCFGPIO_DDREL		(*(vu_char *) (CFG_SYS_MBAR+0x10001F))
+#define MCFGPIO_DDRAS		(*(vu_char *) (CFG_SYS_MBAR+0x100020))
+#define MCFGPIO_DDRQS		(*(vu_char *) (CFG_SYS_MBAR+0x100021))
+#define MCFGPIO_DDRSD		(*(vu_char *) (CFG_SYS_MBAR+0x100022))
+#define MCFGPIO_DDRTC		(*(vu_char *) (CFG_SYS_MBAR+0x100023))
+#define MCFGPIO_DDRTD		(*(vu_char *) (CFG_SYS_MBAR+0x100024))
+#define MCFGPIO_DDRUA		(*(vu_char *) (CFG_SYS_MBAR+0x100025))
 
-#define MCFGPIO_PORTAP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
-#define MCFGPIO_PORTBP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
-#define MCFGPIO_PORTCP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
-#define MCFGPIO_PORTDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
-#define MCFGPIO_PORTEP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
-#define MCFGPIO_PORTFP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
-#define MCFGPIO_PORTGP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
-#define MCFGPIO_PORTHP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
-#define MCFGPIO_PORTJP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
-#define MCFGPIO_PORTDDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
-#define MCFGPIO_PORTEHP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
-#define MCFGPIO_PORTELP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
-#define MCFGPIO_PORTASP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
-#define MCFGPIO_PORTQSP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
-#define MCFGPIO_PORTSDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
-#define MCFGPIO_PORTTCP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
-#define MCFGPIO_PORTTDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
-#define MCFGPIO_PORTUAP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+#define MCFGPIO_PORTAP		(*(vu_char *) (CFG_SYS_MBAR+0x100028))
+#define MCFGPIO_PORTBP		(*(vu_char *) (CFG_SYS_MBAR+0x100029))
+#define MCFGPIO_PORTCP		(*(vu_char *) (CFG_SYS_MBAR+0x10002A))
+#define MCFGPIO_PORTDP		(*(vu_char *) (CFG_SYS_MBAR+0x10002B))
+#define MCFGPIO_PORTEP		(*(vu_char *) (CFG_SYS_MBAR+0x10002C))
+#define MCFGPIO_PORTFP		(*(vu_char *) (CFG_SYS_MBAR+0x10002D))
+#define MCFGPIO_PORTGP		(*(vu_char *) (CFG_SYS_MBAR+0x10002E))
+#define MCFGPIO_PORTHP		(*(vu_char *) (CFG_SYS_MBAR+0x10002F))
+#define MCFGPIO_PORTJP		(*(vu_char *) (CFG_SYS_MBAR+0x100030))
+#define MCFGPIO_PORTDDP		(*(vu_char *) (CFG_SYS_MBAR+0x100031))
+#define MCFGPIO_PORTEHP		(*(vu_char *) (CFG_SYS_MBAR+0x100032))
+#define MCFGPIO_PORTELP		(*(vu_char *) (CFG_SYS_MBAR+0x100033))
+#define MCFGPIO_PORTASP		(*(vu_char *) (CFG_SYS_MBAR+0x100034))
+#define MCFGPIO_PORTQSP		(*(vu_char *) (CFG_SYS_MBAR+0x100035))
+#define MCFGPIO_PORTSDP		(*(vu_char *) (CFG_SYS_MBAR+0x100036))
+#define MCFGPIO_PORTTCP		(*(vu_char *) (CFG_SYS_MBAR+0x100037))
+#define MCFGPIO_PORTTDP		(*(vu_char *) (CFG_SYS_MBAR+0x100038))
+#define MCFGPIO_PORTUAP		(*(vu_char *) (CFG_SYS_MBAR+0x100039))
 
-#define MCFGPIO_SETA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
-#define MCFGPIO_SETB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
-#define MCFGPIO_SETC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
-#define MCFGPIO_SETD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
-#define MCFGPIO_SETE		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
-#define MCFGPIO_SETF		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
-#define MCFGPIO_SETG		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
-#define MCFGPIO_SETH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
-#define MCFGPIO_SETJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
-#define MCFGPIO_SETDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
-#define MCFGPIO_SETEH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
-#define MCFGPIO_SETEL		(*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
-#define MCFGPIO_SETAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
-#define MCFGPIO_SETQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
-#define MCFGPIO_SETSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
-#define MCFGPIO_SETTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
-#define MCFGPIO_SETTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
-#define MCFGPIO_SETUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+#define MCFGPIO_SETA		(*(vu_char *) (CFG_SYS_MBAR+0x100028))
+#define MCFGPIO_SETB		(*(vu_char *) (CFG_SYS_MBAR+0x100029))
+#define MCFGPIO_SETC		(*(vu_char *) (CFG_SYS_MBAR+0x10002A))
+#define MCFGPIO_SETD		(*(vu_char *) (CFG_SYS_MBAR+0x10002B))
+#define MCFGPIO_SETE		(*(vu_char *) (CFG_SYS_MBAR+0x10002C))
+#define MCFGPIO_SETF		(*(vu_char *) (CFG_SYS_MBAR+0x10002D))
+#define MCFGPIO_SETG		(*(vu_char *) (CFG_SYS_MBAR+0x10002E))
+#define MCFGPIO_SETH		(*(vu_char *) (CFG_SYS_MBAR+0x10002F))
+#define MCFGPIO_SETJ		(*(vu_char *) (CFG_SYS_MBAR+0x100030))
+#define MCFGPIO_SETDD		(*(vu_char *) (CFG_SYS_MBAR+0x100031))
+#define MCFGPIO_SETEH		(*(vu_char *) (CFG_SYS_MBAR+0x100032))
+#define MCFGPIO_SETEL		(*(vu_char *) (CFG_SYS_MBAR+0x100033))
+#define MCFGPIO_SETAS		(*(vu_char *) (CFG_SYS_MBAR+0x100034))
+#define MCFGPIO_SETQS		(*(vu_char *) (CFG_SYS_MBAR+0x100035))
+#define MCFGPIO_SETSD		(*(vu_char *) (CFG_SYS_MBAR+0x100036))
+#define MCFGPIO_SETTC		(*(vu_char *) (CFG_SYS_MBAR+0x100037))
+#define MCFGPIO_SETTD		(*(vu_char *) (CFG_SYS_MBAR+0x100038))
+#define MCFGPIO_SETUA		(*(vu_char *) (CFG_SYS_MBAR+0x100039))
 
-#define MCFGPIO_CLRA		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003C))
-#define MCFGPIO_CLRB		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003D))
-#define MCFGPIO_CLRC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003E))
-#define MCFGPIO_CLRD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003F))
-#define MCFGPIO_CLRE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100040))
-#define MCFGPIO_CLRF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100041))
-#define MCFGPIO_CLRG		(*(vu_char *) (CONFIG_SYS_MBAR+0x100042))
-#define MCFGPIO_CLRH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100043))
-#define MCFGPIO_CLRJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100044))
-#define MCFGPIO_CLRDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100045))
-#define MCFGPIO_CLREH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100046))
-#define MCFGPIO_CLREL		(*(vu_char *) (CONFIG_SYS_MBAR+0x100047))
-#define MCFGPIO_CLRAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100048))
-#define MCFGPIO_CLRQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100049))
-#define MCFGPIO_CLRSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004A))
-#define MCFGPIO_CLRTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004B))
-#define MCFGPIO_CLRTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004C))
-#define MCFGPIO_CLRUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004D))
+#define MCFGPIO_CLRA		(*(vu_char *) (CFG_SYS_MBAR+0x10003C))
+#define MCFGPIO_CLRB		(*(vu_char *) (CFG_SYS_MBAR+0x10003D))
+#define MCFGPIO_CLRC		(*(vu_char *) (CFG_SYS_MBAR+0x10003E))
+#define MCFGPIO_CLRD		(*(vu_char *) (CFG_SYS_MBAR+0x10003F))
+#define MCFGPIO_CLRE		(*(vu_char *) (CFG_SYS_MBAR+0x100040))
+#define MCFGPIO_CLRF		(*(vu_char *) (CFG_SYS_MBAR+0x100041))
+#define MCFGPIO_CLRG		(*(vu_char *) (CFG_SYS_MBAR+0x100042))
+#define MCFGPIO_CLRH		(*(vu_char *) (CFG_SYS_MBAR+0x100043))
+#define MCFGPIO_CLRJ		(*(vu_char *) (CFG_SYS_MBAR+0x100044))
+#define MCFGPIO_CLRDD		(*(vu_char *) (CFG_SYS_MBAR+0x100045))
+#define MCFGPIO_CLREH		(*(vu_char *) (CFG_SYS_MBAR+0x100046))
+#define MCFGPIO_CLREL		(*(vu_char *) (CFG_SYS_MBAR+0x100047))
+#define MCFGPIO_CLRAS		(*(vu_char *) (CFG_SYS_MBAR+0x100048))
+#define MCFGPIO_CLRQS		(*(vu_char *) (CFG_SYS_MBAR+0x100049))
+#define MCFGPIO_CLRSD		(*(vu_char *) (CFG_SYS_MBAR+0x10004A))
+#define MCFGPIO_CLRTC		(*(vu_char *) (CFG_SYS_MBAR+0x10004B))
+#define MCFGPIO_CLRTD		(*(vu_char *) (CFG_SYS_MBAR+0x10004C))
+#define MCFGPIO_CLRUA		(*(vu_char *) (CFG_SYS_MBAR+0x10004D))
 
-#define MCFGPIO_PBCDPAR	(*(vu_char *) (CONFIG_SYS_MBAR+0x100050))
-#define MCFGPIO_PFPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100051))
-#define MCFGPIO_PEPAR		(*(vu_short *)(CONFIG_SYS_MBAR+0x100052))
-#define MCFGPIO_PJPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100054))
-#define MCFGPIO_PSDPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100055))
-#define MCFGPIO_PASPAR		(*(vu_short *)(CONFIG_SYS_MBAR+0x100056))
-#define MCFGPIO_PEHLPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100058))
-#define MCFGPIO_PQSPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100059))
-#define MCFGPIO_PTCPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005A))
-#define MCFGPIO_PTDPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005B))
-#define MCFGPIO_PUAPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005C))
+#define MCFGPIO_PBCDPAR	(*(vu_char *) (CFG_SYS_MBAR+0x100050))
+#define MCFGPIO_PFPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100051))
+#define MCFGPIO_PEPAR		(*(vu_short *)(CFG_SYS_MBAR+0x100052))
+#define MCFGPIO_PJPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100054))
+#define MCFGPIO_PSDPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100055))
+#define MCFGPIO_PASPAR		(*(vu_short *)(CFG_SYS_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100058))
+#define MCFGPIO_PQSPAR		(*(vu_char *) (CFG_SYS_MBAR+0x100059))
+#define MCFGPIO_PTCPAR		(*(vu_char *) (CFG_SYS_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR		(*(vu_char *) (CFG_SYS_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR		(*(vu_char *) (CFG_SYS_MBAR+0x10005C))
 
 /* Bit level definitions and macros */
 #define MCFGPIO_PORT7			(0x80)
@@ -310,25 +310,25 @@
 
 /* System Conrol Module SCM */
 
-#define MCFSCM_RAMBAR		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000008))
-#define MCFSCM_CRSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000010))
-#define MCFSCM_CWCR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000011))
-#define MCFSCM_LPICR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000012))
-#define MCFSCM_CWSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000013))
+#define MCFSCM_RAMBAR		(*(vu_long *) (CFG_SYS_MBAR+0x00000008))
+#define MCFSCM_CRSR		(*(vu_char *) (CFG_SYS_MBAR+0x00000010))
+#define MCFSCM_CWCR		(*(vu_char *) (CFG_SYS_MBAR+0x00000011))
+#define MCFSCM_LPICR		(*(vu_char *) (CFG_SYS_MBAR+0x00000012))
+#define MCFSCM_CWSR		(*(vu_char *) (CFG_SYS_MBAR+0x00000013))
 
-#define MCFSCM_MPARK		(*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C))
-#define MCFSCM_MPR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000020))
-#define MCFSCM_PACR0		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000024))
-#define MCFSCM_PACR1		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000025))
-#define MCFSCM_PACR2		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000026))
-#define MCFSCM_PACR3		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000027))
-#define MCFSCM_PACR4		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000028))
-#define MCFSCM_PACR5		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A))
-#define MCFSCM_PACR6		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B))
-#define MCFSCM_PACR7		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C))
-#define MCFSCM_PACR8		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E))
-#define MCFSCM_GPACR0		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000030))
-#define MCFSCM_GPACR1		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000031))
+#define MCFSCM_MPARK		(*(vu_long *) (CFG_SYS_MBAR+0x0000001C))
+#define MCFSCM_MPR		(*(vu_char *) (CFG_SYS_MBAR+0x00000020))
+#define MCFSCM_PACR0		(*(vu_char *) (CFG_SYS_MBAR+0x00000024))
+#define MCFSCM_PACR1		(*(vu_char *) (CFG_SYS_MBAR+0x00000025))
+#define MCFSCM_PACR2		(*(vu_char *) (CFG_SYS_MBAR+0x00000026))
+#define MCFSCM_PACR3		(*(vu_char *) (CFG_SYS_MBAR+0x00000027))
+#define MCFSCM_PACR4		(*(vu_char *) (CFG_SYS_MBAR+0x00000028))
+#define MCFSCM_PACR5		(*(vu_char *) (CFG_SYS_MBAR+0x0000002A))
+#define MCFSCM_PACR6		(*(vu_char *) (CFG_SYS_MBAR+0x0000002B))
+#define MCFSCM_PACR7		(*(vu_char *) (CFG_SYS_MBAR+0x0000002C))
+#define MCFSCM_PACR8		(*(vu_char *) (CFG_SYS_MBAR+0x0000002E))
+#define MCFSCM_GPACR0		(*(vu_char *) (CFG_SYS_MBAR+0x00000030))
+#define MCFSCM_GPACR1		(*(vu_char *) (CFG_SYS_MBAR+0x00000031))
 
 #define MCFSCM_CRSR_EXT		(0x80)
 #define MCFSCM_CRSR_CWDR	(0x20)
@@ -337,8 +337,8 @@
 
 /* Reset Controller Module RCM */
 
-#define MCFRESET_RCR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00110000))
-#define MCFRESET_RSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00110001))
+#define MCFRESET_RCR		(*(vu_char *) (CFG_SYS_MBAR+0x00110000))
+#define MCFRESET_RSR		(*(vu_char *) (CFG_SYS_MBAR+0x00110001))
 
 #define MCFRESET_RCR_SOFTRST	(0x80)
 #define MCFRESET_RCR_FRCRSTOUT	(0x40)
@@ -360,9 +360,9 @@
 
 /* Chip Configuration Module CCM */
 
-#define MCFCCM_CCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00110004))
-#define MCFCCM_RCON		(*(vu_short *)(CONFIG_SYS_MBAR+0x00110008))
-#define MCFCCM_CIR		(*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A))
+#define MCFCCM_CCR		(*(vu_short *)(CFG_SYS_MBAR+0x00110004))
+#define MCFCCM_RCON		(*(vu_short *)(CFG_SYS_MBAR+0x00110008))
+#define MCFCCM_CIR		(*(vu_short *)(CFG_SYS_MBAR+0x0011000A))
 
 /* Bit level definitions and macros */
 #define MCFCCM_CCR_LOAD		(0x8000)
@@ -377,18 +377,18 @@
 
 /* Clock Module */
 
-#define MCFCLOCK_SYNCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x120000))
-#define MCFCLOCK_SYNSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x120002))
+#define MCFCLOCK_SYNCR		(*(vu_short *)(CFG_SYS_MBAR+0x120000))
+#define MCFCLOCK_SYNSR		(*(vu_char *) (CFG_SYS_MBAR+0x120002))
 
 #define MCFCLOCK_SYNCR_MFD(x)	(((x)&0x0007)<<12)
 #define MCFCLOCK_SYNCR_RFD(x)	(((x)&0x0007)<<8)
 #define MCFCLOCK_SYNSR_LOCK	0x08
 
-#define MCFSDRAMC_DCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00000040))
-#define MCFSDRAMC_DACR0		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000048))
-#define MCFSDRAMC_DMR0		(*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c))
-#define MCFSDRAMC_DACR1		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000050))
-#define MCFSDRAMC_DMR1		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000054))
+#define MCFSDRAMC_DCR		(*(vu_short *)(CFG_SYS_MBAR+0x00000040))
+#define MCFSDRAMC_DACR0		(*(vu_long *) (CFG_SYS_MBAR+0x00000048))
+#define MCFSDRAMC_DMR0		(*(vu_long *) (CFG_SYS_MBAR+0x0000004c))
+#define MCFSDRAMC_DACR1		(*(vu_long *) (CFG_SYS_MBAR+0x00000050))
+#define MCFSDRAMC_DMR1		(*(vu_long *) (CFG_SYS_MBAR+0x00000054))
 
 #define MCFSDRAMC_DCR_NAM	(0x2000)
 #define MCFSDRAMC_DCR_COC	(0x1000)
@@ -418,60 +418,60 @@
 #define MCFSDRAMC_DMR_UD	(0x00000002)
 #define MCFSDRAMC_DMR_V		(0x00000001)
 
-#define MCFWTM_WCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140000))
-#define MCFWTM_WMR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140002))
-#define MCFWTM_WCNTR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
-#define MCFWTM_WSR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
+#define MCFWTM_WCR		(*(vu_short *)(CFG_SYS_MBAR+0x00140000))
+#define MCFWTM_WMR		(*(vu_short *)(CFG_SYS_MBAR+0x00140002))
+#define MCFWTM_WCNTR		(*(vu_short *)(CFG_SYS_MBAR+0x00140004))
+#define MCFWTM_WSR		(*(vu_short *)(CFG_SYS_MBAR+0x00140006))
 
 /*********************************************************************
 * General Purpose Timer (GPT) Module
 *********************************************************************/
 
-#define MCFGPTA_GPTIOS		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000))
-#define MCFGPTA_GPTCFORC	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001))
-#define MCFGPTA_GPTOC3M		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002))
-#define MCFGPTA_GPTOC3D		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003))
-#define MCFGPTA_GPTCNT		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004))
-#define MCFGPTA_GPTSCR1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006))
-#define MCFGPTA_GPTTOV		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008))
-#define MCFGPTA_GPTCTL1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009))
-#define MCFGPTA_GPTCTL2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B))
-#define MCFGPTA_GPTIE		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C))
-#define MCFGPTA_GPTSCR2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D))
-#define MCFGPTA_GPTFLG1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E))
-#define MCFGPTA_GPTFLG2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F))
-#define MCFGPTA_GPTC0		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010))
-#define MCFGPTA_GPTC1		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012))
-#define MCFGPTA_GPTC2		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014))
-#define MCFGPTA_GPTC3		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016))
-#define MCFGPTA_GPTPACTL	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018))
-#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019))
-#define MCFGPTA_GPTPACNT	(*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A))
-#define MCFGPTA_GPTPORT		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D))
-#define MCFGPTA_GPTDDR		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E))
+#define MCFGPTA_GPTIOS		(*(vu_char *)(CFG_SYS_MBAR+0x1A0000))
+#define MCFGPTA_GPTCFORC	(*(vu_char *)(CFG_SYS_MBAR+0x1A0001))
+#define MCFGPTA_GPTOC3M		(*(vu_char *)(CFG_SYS_MBAR+0x1A0002))
+#define MCFGPTA_GPTOC3D		(*(vu_char *)(CFG_SYS_MBAR+0x1A0003))
+#define MCFGPTA_GPTCNT		(*(vu_short *)(CFG_SYS_MBAR+0x1A0004))
+#define MCFGPTA_GPTSCR1		(*(vu_char *)(CFG_SYS_MBAR+0x1A0006))
+#define MCFGPTA_GPTTOV		(*(vu_char *)(CFG_SYS_MBAR+0x1A0008))
+#define MCFGPTA_GPTCTL1		(*(vu_char *)(CFG_SYS_MBAR+0x1A0009))
+#define MCFGPTA_GPTCTL2		(*(vu_char *)(CFG_SYS_MBAR+0x1A000B))
+#define MCFGPTA_GPTIE		(*(vu_char *)(CFG_SYS_MBAR+0x1A000C))
+#define MCFGPTA_GPTSCR2		(*(vu_char *)(CFG_SYS_MBAR+0x1A000D))
+#define MCFGPTA_GPTFLG1		(*(vu_char *)(CFG_SYS_MBAR+0x1A000E))
+#define MCFGPTA_GPTFLG2		(*(vu_char *)(CFG_SYS_MBAR+0x1A000F))
+#define MCFGPTA_GPTC0		(*(vu_short *)(CFG_SYS_MBAR+0x1A0010))
+#define MCFGPTA_GPTC1		(*(vu_short *)(CFG_SYS_MBAR+0x1A0012))
+#define MCFGPTA_GPTC2		(*(vu_short *)(CFG_SYS_MBAR+0x1A0014))
+#define MCFGPTA_GPTC3		(*(vu_short *)(CFG_SYS_MBAR+0x1A0016))
+#define MCFGPTA_GPTPACTL	(*(vu_char *)(CFG_SYS_MBAR+0x1A0018))
+#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CFG_SYS_MBAR+0x1A0019))
+#define MCFGPTA_GPTPACNT	(*(vu_short *)(CFG_SYS_MBAR+0x1A001A))
+#define MCFGPTA_GPTPORT		(*(vu_char *)(CFG_SYS_MBAR+0x1A001D))
+#define MCFGPTA_GPTDDR		(*(vu_char *)(CFG_SYS_MBAR+0x1A001E))
 
-#define MCFGPTB_GPTIOS		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000))
-#define MCFGPTB_GPTCFORC	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001))
-#define MCFGPTB_GPTOC3M		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002))
-#define MCFGPTB_GPTOC3D		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003))
-#define MCFGPTB_GPTCNT		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004))
-#define MCFGPTB_GPTSCR1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006))
-#define MCFGPTB_GPTTOV		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008))
-#define MCFGPTB_GPTCTL1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009))
-#define MCFGPTB_GPTCTL2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B))
-#define MCFGPTB_GPTIE		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C))
-#define MCFGPTB_GPTSCR2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D))
-#define MCFGPTB_GPTFLG1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E))
-#define MCFGPTB_GPTFLG2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F))
-#define MCFGPTB_GPTC0		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010))
-#define MCFGPTB_GPTC1		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012))
-#define MCFGPTB_GPTC2		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014))
-#define MCFGPTB_GPTC3		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016))
-#define MCFGPTB_GPTPACTL	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018))
-#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019))
-#define MCFGPTB_GPTPACNT	(*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A))
-#define MCFGPTB_GPTPORT		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D))
-#define MCFGPTB_GPTDDR		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E))
+#define MCFGPTB_GPTIOS		(*(vu_char *)(CFG_SYS_MBAR+0x1B0000))
+#define MCFGPTB_GPTCFORC	(*(vu_char *)(CFG_SYS_MBAR+0x1B0001))
+#define MCFGPTB_GPTOC3M		(*(vu_char *)(CFG_SYS_MBAR+0x1B0002))
+#define MCFGPTB_GPTOC3D		(*(vu_char *)(CFG_SYS_MBAR+0x1B0003))
+#define MCFGPTB_GPTCNT		(*(vu_short *)(CFG_SYS_MBAR+0x1B0004))
+#define MCFGPTB_GPTSCR1		(*(vu_char *)(CFG_SYS_MBAR+0x1B0006))
+#define MCFGPTB_GPTTOV		(*(vu_char *)(CFG_SYS_MBAR+0x1B0008))
+#define MCFGPTB_GPTCTL1		(*(vu_char *)(CFG_SYS_MBAR+0x1B0009))
+#define MCFGPTB_GPTCTL2		(*(vu_char *)(CFG_SYS_MBAR+0x1B000B))
+#define MCFGPTB_GPTIE		(*(vu_char *)(CFG_SYS_MBAR+0x1B000C))
+#define MCFGPTB_GPTSCR2		(*(vu_char *)(CFG_SYS_MBAR+0x1B000D))
+#define MCFGPTB_GPTFLG1		(*(vu_char *)(CFG_SYS_MBAR+0x1B000E))
+#define MCFGPTB_GPTFLG2		(*(vu_char *)(CFG_SYS_MBAR+0x1B000F))
+#define MCFGPTB_GPTC0		(*(vu_short *)(CFG_SYS_MBAR+0x1B0010))
+#define MCFGPTB_GPTC1		(*(vu_short *)(CFG_SYS_MBAR+0x1B0012))
+#define MCFGPTB_GPTC2		(*(vu_short *)(CFG_SYS_MBAR+0x1B0014))
+#define MCFGPTB_GPTC3		(*(vu_short *)(CFG_SYS_MBAR+0x1B0016))
+#define MCFGPTB_GPTPACTL	(*(vu_char *)(CFG_SYS_MBAR+0x1B0018))
+#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CFG_SYS_MBAR+0x1B0019))
+#define MCFGPTB_GPTPACNT	(*(vu_short *)(CFG_SYS_MBAR+0x1B001A))
+#define MCFGPTB_GPTPORT		(*(vu_char *)(CFG_SYS_MBAR+0x1B001D))
+#define MCFGPTB_GPTDDR		(*(vu_char *)(CFG_SYS_MBAR+0x1B001E))
 
 /* Bit level definitions and macros */
 #define MCFGPT_GPTIOS_IOS3		(0x08)
@@ -556,7 +556,7 @@
 
 /* Coldfire Flash Module CFM */
 
-#define MCFCFM_MCR			(*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000))
+#define MCFCFM_MCR			(*(vu_short *)(CFG_SYS_MBAR+0x1D0000))
 #define MCFCFM_MCR_LOCK			(0x0400)
 #define MCFCFM_MCR_PVIE			(0x0200)
 #define MCFCFM_MCR_AEIE			(0x0100)
@@ -564,23 +564,23 @@
 #define MCFCFM_MCR_CCIE			(0x0040)
 #define MCFCFM_MCR_KEYACC		(0x0020)
 
-#define MCFCFM_CLKD			(*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002))
+#define MCFCFM_CLKD			(*(vu_char *)(CFG_SYS_MBAR+0x1D0002))
 
-#define MCFCFM_SEC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008))
+#define MCFCFM_SEC			(*(vu_long*) (CFG_SYS_MBAR+0x1D0008))
 #define MCFCFM_SEC_KEYEN		(0x80000000)
 #define MCFCFM_SEC_SECSTAT		(0x40000000)
 
-#define MCFCFM_PROT			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010))
-#define MCFCFM_SACC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014))
-#define MCFCFM_DACC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018))
-#define MCFCFM_USTAT			(*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020))
+#define MCFCFM_PROT			(*(vu_long*) (CFG_SYS_MBAR+0x1D0010))
+#define MCFCFM_SACC			(*(vu_long*) (CFG_SYS_MBAR+0x1D0014))
+#define MCFCFM_DACC			(*(vu_long*) (CFG_SYS_MBAR+0x1D0018))
+#define MCFCFM_USTAT			(*(vu_char*) (CFG_SYS_MBAR+0x1D0020))
 #define MCFCFM_USTAT_CBEIF		0x80
 #define MCFCFM_USTAT_CCIF		0x40
 #define MCFCFM_USTAT_PVIOL		0x20
 #define MCFCFM_USTAT_ACCERR		0x10
 #define MCFCFM_USTAT_BLANK		0x04
 
-#define MCFCFM_CMD			(*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024))
+#define MCFCFM_CMD			(*(vu_char*) (CFG_SYS_MBAR+0x1D0024))
 #define MCFCFM_CMD_ERSVER		0x05
 #define MCFCFM_CMD_PGERSVER		0x06
 #define MCFCFM_CMD_PGM			0x20

diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index 7eca672..0b4629f 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c

@@ -16,7 +16,7 @@
 {
 	struct bd_info *bd = gd->bd;
 
-	bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
+	bd->bi_mbar_base = CFG_SYS_MBAR; /* base of internal registers */
 
 	bd->bi_intfreq = gd->cpu_clk;	/* Internal Freq, in Hz */
 	bd->bi_busfreq = gd->bus_clk;	/* Bus Freq,      in Hz */
@@ -38,7 +38,7 @@
 	struct bd_info *bd = gd->bd;
 
 	bdinfo_print_mhz("busfreq", bd->bi_busfreq);
-#if defined(CONFIG_SYS_MBAR)
+#if defined(CFG_SYS_MBAR)
 	bdinfo_print_num_l("mbar", bd->bi_mbar_base);
 #endif
 	bdinfo_print_mhz("cpufreq", bd->bi_intfreq);

diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index aa2b93e..4ddda69 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c

@@ -34,18 +34,18 @@
 	*cf_icache_status = 1;
 
 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
-	__asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
+	__asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2));
 	__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
 #if defined(CONFIG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
 	__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
 #endif
 #else
-	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
-	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
 #endif
 
-	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_ICACR));
 }
 
 void icache_disable(void)
@@ -72,9 +72,9 @@
 {
 	u32 temp;
 
-	temp = CONFIG_SYS_ICACHE_INV;
+	temp = CFG_SYS_ICACHE_INV;
 	if (*cf_icache_status)
-		temp |= CONFIG_SYS_CACHE_ICACR;
+		temp |= CFG_SYS_CACHE_ICACR;
 
 	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
 }
@@ -89,15 +89,15 @@
 	*cf_dcache_status = 1;
 
 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
-	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
-	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
 #if defined(CONFIG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
 	__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
 #endif
 #endif
 
-	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_DCACR));
 }
 
 void dcache_disable(void)
@@ -124,11 +124,11 @@
 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
 	u32 temp;
 
-	temp = CONFIG_SYS_DCACHE_INV;
+	temp = CFG_SYS_DCACHE_INV;
 	if (*cf_dcache_status)
-		temp |= CONFIG_SYS_CACHE_DCACR;
+		temp |= CFG_SYS_CACHE_DCACR;
 	if (*cf_icache_status)
-		temp |= CONFIG_SYS_CACHE_ICACR;
+		temp |= CFG_SYS_CACHE_ICACR;
 
 	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
 #endif

diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c
index 0c2c1a9..28fe803 100644
--- a/arch/m68k/lib/traps.c
+++ b/arch/m68k/lib/traps.c

@@ -62,7 +62,7 @@
 
 int arch_initr_trap(void)
 {
-	trap_init(CONFIG_SYS_SDRAM_BASE);
+	trap_init(CFG_SYS_SDRAM_BASE);
 
 	return 0;
 }

diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index 7577fdd..7a682f2 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c

@@ -135,7 +135,7 @@
 
 int arch_initr_trap(void)
 {
-	trap_init(CONFIG_SYS_SDRAM_BASE);
+	trap_init(CFG_SYS_SDRAM_BASE);
 
 	return 0;
 }

diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c
index cff98b0..15d1eff 100644
--- a/arch/mips/mach-jz47xx/jz4780/jz4780.c
+++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c

@@ -78,7 +78,7 @@
 
 phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
-	return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
+	return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
 }
 
 int print_cpuinfo(void)

diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index 5bc3100..d484eb92 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c

@@ -17,16 +17,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
+#if CFG_SYS_SDRAM_SIZE <= SZ_64M
 #define MSCC_RAM_TLB_SIZE   SZ_64M
 #define MSCC_ATTRIB2   MMU_REGIO_INVAL
-#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
+#elif CFG_SYS_SDRAM_SIZE <= SZ_128M
 #define MSCC_RAM_TLB_SIZE   SZ_64M
 #define MSCC_ATTRIB2   MMU_REGIO_RW
-#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
+#elif CFG_SYS_SDRAM_SIZE <= SZ_256M
 #define MSCC_RAM_TLB_SIZE   SZ_256M
 #define MSCC_ATTRIB2   MMU_REGIO_INVAL
-#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
+#elif CFG_SYS_SDRAM_SIZE <= SZ_512M
 #define MSCC_RAM_TLB_SIZE   SZ_256M
 #define MSCC_ATTRIB2   MMU_REGIO_RW
 #else

diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index c53a420..f7fbd33 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c

@@ -67,6 +67,6 @@
 
 int dram_init(void)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 	return 0;
 }

diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
index d52eabb..75fb3ca 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h

@@ -13,7 +13,7 @@
 #include <mach/common.h>
 
 #define MIPS_VCOREIII_MEMORY_DDR3
-#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE
+#define MIPS_VCOREIII_DDR_SIZE CFG_SYS_SDRAM_SIZE
 
 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA)	/* Serval1 Refboard */
 

diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S
index 3cad356..7063f32 100644
--- a/arch/mips/mach-mtmips/mt7621/spl/start.S
+++ b/arch/mips/mach-mtmips/mt7621/spl/start.S

@@ -18,8 +18,8 @@
 #include "dram.h"
 
 #ifndef CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
-				CONFIG_SYS_INIT_SP_OFFSET)
+#define CONFIG_SYS_INIT_SP_ADDR	(CFG_SYS_SDRAM_BASE + \
+				CFG_SYS_INIT_SP_OFFSET)
 #endif
 
 #define SP_ADDR_TEMP		0xbe10dff0

diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
index 9c5789b..85cb084 100644
--- a/arch/mips/mach-octeon/dram.c
+++ b/arch/mips/mach-octeon/dram.c

@@ -81,7 +81,7 @@
 {
 	if (IS_ENABLED(CONFIG_RAM_OCTEON)) {
 		/* Map a maximum of 256MiB - return not size but address */
-		return CONFIG_SYS_SDRAM_BASE + min(gd->ram_size,
+		return CFG_SYS_SDRAM_BASE + min(gd->ram_size,
 						   UBOOT_RAM_SIZE_MAX);
 	} else {
 		return gd->ram_top;

diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index 4dd9c10..8554450 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c

@@ -73,7 +73,7 @@
 	if (ret)
 		return ret;
 
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 #ifndef CONFIG_ROM_STUBS
 	copy_exception_trampoline();
 #endif

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c355a95..0fc4ced 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig

@@ -34,6 +34,10 @@
 
 endchoice
 
+config FSL_LBC
+	def_bool y
+	depends on (MPC85xx || MPC83xx) && !FSL_IFC
+
 config HIGH_BATS
 	bool "Enable high BAT registers"
 	help
@@ -44,6 +48,21 @@
 	bool "Lock some portion of L1 for initial ram stack"
 	depends on MPC83xx || MPC85xx
 
+config SYS_SRIO
+	bool "Serial RapidIO support"
+
+config SRIO1
+	bool "Board has SRIO 1 port available"
+	depends on SYS_SRIO
+
+config SRIO2
+	bool "Board has SRIO 2 port available"
+	depends on SYS_SRIO
+
+config SRIO_PCIE_BOOT_MASTER
+	bool "Board can support master function for Boot from SRIO and PCIE"
+	depends on SYS_SRIO
+
 source "arch/powerpc/cpu/mpc83xx/Kconfig"
 source "arch/powerpc/cpu/mpc85xx/Kconfig"
 source "arch/powerpc/cpu/mpc8xx/Kconfig"

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index ec3405e..563f52c 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig

@@ -196,6 +196,10 @@
 config FSL_ELBC
 	bool
 
+config FSL_SERDES
+	bool "SerDes initialization"
+	depends on !MPC83XX_SERDES
+
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/gdsys/mpc8308/Kconfig"
 

diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 33835ee..63c2729 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c

@@ -77,10 +77,10 @@
 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 		SCCR_TSECCM |
 #endif
-#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 		SCCR_TSEC1CM |
 #endif
-#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 		SCCR_TSEC2CM |
 #endif
 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
@@ -92,10 +92,10 @@
 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 		SCCR_USBMPHCM |
 #endif
-#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 		SCCR_USBDRCM |
 #endif
-#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
 		SCCR_SATACM |
 #endif
 		0;
@@ -115,11 +115,11 @@
 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 		(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 #endif
-#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
-		(CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+		(CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 #endif
-#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
-		(CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+		(CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 #endif
 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 		(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
@@ -130,11 +130,11 @@
 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 		(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 #endif
-#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
-		(CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+		(CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 #endif
-#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
-		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
+		(CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 #endif
 		0;
 
@@ -175,26 +175,26 @@
 	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 
 	/* System General Purpose Register */
-#ifdef CONFIG_SYS_SICRH
+#ifdef CFG_SYS_SICRH
 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
-	__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
+	__raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH,
 		     &im->sysconf.sicrh);
 #else
-	__raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
+	__raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh);
 #endif
 #endif
-#ifdef CONFIG_SYS_SICRL
-	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
+#ifdef CFG_SYS_SICRL
+	__raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl);
 #endif
-#ifdef CONFIG_SYS_GPR1
-	__raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#ifdef CFG_SYS_GPR1
+	__raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1);
 #endif
-#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
-	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
+#ifdef CFG_SYS_DDRCDR /* DDR control driver register */
+	__raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 #endif
-#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
-	__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
+#ifdef CFG_SYS_OBIR /* Output buffer impedance register */
+	__raw_writel(CFG_SYS_OBIR, &im->sysconf.obir);
 #endif
 
 #if !defined(CONFIG_PINCTRL)

diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
index e795cd1..b0b9a1e 100644
--- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
+++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h

@@ -1,16 +1,16 @@
 #if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
 #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
 #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
 #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
+#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
+#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
 #endif

diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index d2b6b05..47ca74c5 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c

@@ -24,13 +24,13 @@
 	u32 size;
 } mpc83xx_pcie_cfg_space[] = {
 	{
-		.base = CONFIG_SYS_PCIE1_CFG_BASE,
-		.size = CONFIG_SYS_PCIE1_CFG_SIZE,
+		.base = CFG_SYS_PCIE1_CFG_BASE,
+		.size = CFG_SYS_PCIE1_CFG_SIZE,
 	},
-#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
+#if defined(CFG_SYS_PCIE2_CFG_BASE) && defined(CFG_SYS_PCIE2_CFG_SIZE)
 	{
-		.base = CONFIG_SYS_PCIE2_CFG_BASE,
-		.size = CONFIG_SYS_PCIE2_CFG_SIZE,
+		.base = CFG_SYS_PCIE2_CFG_BASE,
+		.size = CFG_SYS_PCIE2_CFG_SIZE,
 	},
 #endif
 };

diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c
index bb963ee..d4848b2 100644
--- a/arch/powerpc/cpu/mpc83xx/serdes.c
+++ b/arch/powerpc/cpu/mpc83xx/serdes.c

@@ -8,8 +8,6 @@
  * Author: Li Yang <leoli@freescale.com>
  */
 
-#ifndef CONFIG_MPC83XX_SERDES
-
 #include <config.h>
 #include <common.h>
 #include <asm/io.h>
@@ -151,5 +149,3 @@
 	tmp |= FSL_SRDSRSTCTL_RST;
 	out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
 }
-
-#endif /* !CONFIG_MPC83XX_SERDES */

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index e12043b..4f982b8 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c

@@ -59,9 +59,9 @@
 
 	printf(", %s MHz)", strmhz(buf, gd->mem_clk));
 
-#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
+#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE)
 	puts("\nSDRAM: ");
-	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+	print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
 #endif
 }
 
@@ -204,12 +204,12 @@
 		return 0;
 	}
 
-#ifdef CONFIG_SYS_DDRCDR_VALUE
+#ifdef CFG_SYS_DDRCDR_VALUE
 	/*
 	 * Adjust DDR II IO voltage biasing.  It just makes it work.
 	 */
 	if(spd.mem_type == SPD_MEMTYPE_DDR2) {
-		immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+		immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
 	}
 	udelay(50000);
 #endif
@@ -288,7 +288,7 @@
 	/*
 	 * Set up LAWBAR for all of DDR.
 	 */
-	ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+	ecm->bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
 	ecm->ar  = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
 	debug("DDR:bar=0x%08x\n", ecm->bar);
 	debug("DDR:ar=0x%08x\n", ecm->ar);
@@ -693,7 +693,7 @@
 		ddr->sdram_mode =
 			(0
 			 | (1 << (16 + 10))             /* DQS Differential disable */
-#ifdef CONFIG_SYS_DDR_MODE_WEAK
+#ifdef CFG_SYS_DDR_MODE_WEAK
 			 | (1 << (16 + 1))		/* weak driver (~60%) */
 #endif
 			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
@@ -767,8 +767,8 @@
 		debug("DDR: sdram_cfg2  = 0x%08x\n", ddr->sdram_cfg2);
 	}
 
-#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL	/* Optional platform specific value */
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL	/* Optional platform specific value */
+	ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
 #endif
 	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 

diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index d8f6cfe..7cc0383 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c

@@ -54,12 +54,12 @@
 	im->sysconf.spcr |= SPCR_TBEN;
 
 	/* DDR control driver register */
-#ifdef CONFIG_SYS_DDRCDR
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
+#ifdef CFG_SYS_DDRCDR
+	im->sysconf.ddrcdr = CFG_SYS_DDRCDR;
 #endif
 	/* Output buffer impedance register */
-#ifdef CONFIG_SYS_OBIR
-	im->sysconf.obir = CONFIG_SYS_OBIR;
+#ifdef CFG_SYS_OBIR
+	im->sysconf.obir = CFG_SYS_OBIR;
 #endif
 
 	/*
@@ -71,16 +71,16 @@
 	 * has been determined
 	 */
 
-#if defined(CONFIG_SYS_NAND_BR_PRELIM)  \
-	&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
+#if defined(CFG_SYS_NAND_BR_PRELIM)  \
+	&& defined(CFG_SYS_NAND_OR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
 	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
 	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
 #else
-#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
+#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
 #endif
 }
 

diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 8a351b9..52326f0 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S

@@ -246,7 +246,7 @@
 
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
 
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
 #error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
 #endif
 
@@ -486,7 +486,7 @@
 #if defined(CONFIG_WATCHDOG)
 	/* Initialise the Watchdog values and reset it (if req) */
 	/*------------------------------------------------------*/
-	lis r4, CONFIG_SYS_WATCHDOG_VALUE
+	lis r4, CFG_SYS_WATCHDOG_VALUE
 	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
 	stw r4, SWCRR(r3)
 
@@ -1048,10 +1048,10 @@
 lock_ram_in_cache:
 	/* Allocate Initial RAM in data cache.
 	 */
-	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
-	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
-		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+	lis	r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h
+	ori	r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l
+	li	r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
+		     (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:
 	dcbz	r0, r3
@@ -1070,10 +1070,10 @@
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
-	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
-	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
-		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+	lis	r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h
+	ori	r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l
+	li	r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
+		     (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:	icbi	r0, r3
 	dcbi	r0, r3
@@ -1122,14 +1122,14 @@
 	 * LBIU Local Access Widow 0 will not cover this memory space.  So, we
 	 * need another window to map in it.
 	 */
-	lis r4, (CONFIG_SYS_FLASH_BASE)@h
-	ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
-	stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
+	lis r4, (CFG_SYS_FLASH_BASE)@h
+	ori r4, r4, (CFG_SYS_FLASH_BASE)@l
+	stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_SYS_FLASH_BASE */
 
-	/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
+	/* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR1 */
 	lis r4, (0x80000012)@h
 	ori r4, r4, (0x80000012)@l
-	li r5, CONFIG_SYS_FLASH_SIZE
+	li r5, CFG_SYS_FLASH_SIZE
 1:	srawi. r5, r5, 1	/* r5 = r5 >> 1 */
 	addi r4, r4, 1
 	bne 1b
@@ -1150,24 +1150,24 @@
 	lwz r4, BR0(r3)
 	li  r5, 0x7FFF
 	and r4, r4, r5
-	lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
-	ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
+	lis r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@h
+	ori r5, r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@l
 	or  r5, r5, r4
-	stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
+	stw r5, BR0(r3) /* r5 <= (CFG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
 
 	lwz r4, OR0(r3)
-	lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
+	lis r5, ~((CFG_SYS_FLASH_SIZE << 4) - 1)
 	or r4, r4, r5
 	stw r4, OR0(r3)
 
-	lis r4, (CONFIG_SYS_FLASH_BASE)@h
-	ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
-	stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
+	lis r4, (CFG_SYS_FLASH_BASE)@h
+	ori r4, r4, (CFG_SYS_FLASH_BASE)@l
+	stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_SYS_FLASH_BASE */
 
-	/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
+	/* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR0 */
 	lis r4, (0x80000012)@h
 	ori r4, r4, (0x80000012)@l
-	li r5, CONFIG_SYS_FLASH_SIZE
+	li r5, CFG_SYS_FLASH_SIZE
 1:	srawi. r5, r5, 1 /* r5 = r5 >> 1 */
 	addi r4, r4, 1
 	bne 1b

diff --git a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h
index f8c2f10..b2f9807 100644
--- a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h
+++ b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h

@@ -1,7 +1,7 @@
 #ifdef CONFIG_ARCH_MPC8308
 
-#ifndef CONFIG_SYS_SICRL
-#define CONFIG_SYS_SICRL (\
+#ifndef CFG_SYS_SICRL
+#define CFG_SYS_SICRL (\
 	CONFIG_SICRL_SPI |\
 	CONFIG_SICRL_UART |\
 	CONFIG_SICRL_IRQ |\
@@ -10,8 +10,8 @@
 )
 #endif
 
-#ifndef CONFIG_SYS_SICRH
-#define CONFIG_SYS_SICRH (\
+#ifndef CFG_SYS_SICRH
+#define CFG_SYS_SICRH (\
 	CONFIG_SICRH_ESDHC_A |\
 	CONFIG_SICRH_ESDHC_B |\
 	CONFIG_SICRH_ESDHC_C |\

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 24d3f1f..f236156 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig

@@ -252,6 +252,8 @@
 	bool "Support kmcent2"
 	select VENDOR_KM
 	select FSL_CORENET
+	select SYS_DPAA_FMAN
+	select SYS_DPAA_PME
 	select SYS_L3_SIZE_256KB
 
 endchoice
@@ -618,6 +620,9 @@
 	select E500MC
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
+	select SYS_DPAA_FMAN
+	select SYS_DPAA_PME
+	select SYS_DPAA_RMAN
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A004849
 	select SYS_FSL_ERRATUM_A005275
@@ -762,6 +767,7 @@
 	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
+	select SYS_DPAA_FMAN
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008378
 	select SYS_FSL_ERRATUM_A008109
@@ -792,6 +798,8 @@
 	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
+	select SYS_DPAA_FMAN
+	select SYS_DPAA_PME
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008044
 	select SYS_FSL_ERRATUM_A008378
@@ -822,6 +830,8 @@
 	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
+	select SYS_DPAA_FMAN
+	select SYS_DPAA_PME
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008044
 	select SYS_FSL_ERRATUM_A008378
@@ -851,6 +861,10 @@
 	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
+	select SYS_DPAA_DCE if !NOBQFMAN
+	select SYS_DPAA_FMAN if !NOBQFMAN
+	select SYS_DPAA_PME if !NOBQFMAN
+	select SYS_DPAA_RMAN if !NOBQFMAN
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006593
@@ -871,6 +885,7 @@
 	select SYS_FSL_SRIO_LIODN
 	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select SYS_FSL_USB_DUAL_PHY_ENABLE
+	select SYS_PMAN if !NOBQFMAN
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_SATA
@@ -886,6 +901,10 @@
 	select FSL_CORENET
 	select FSL_LAW
 	select SYS_CACHE_SHIFT_6
+	select SYS_DPAA_DCE if !NOBQFMAN
+	select SYS_DPAA_FMAN if !NOBQFMAN
+	select SYS_DPAA_PME if !NOBQFMAN
+	select SYS_DPAA_RMAN if !NOBQFMAN
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A004468
 	select SYS_FSL_ERRATUM_A005871
@@ -907,6 +926,7 @@
 	select SYS_FSL_SRIO_LIODN
 	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select SYS_FSL_USB_DUAL_PHY_ENABLE
+	select SYS_PMAN if !NOBQFMAN
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_SATA
@@ -947,6 +967,9 @@
 	help
 		Enable PowerPC E6500 core
 
+config NOBQFMAN
+	bool
+
 config FSL_LAW
 	bool
 	help
@@ -1019,6 +1042,15 @@
 		if changed by pre-boot regime. The value here must match
 		the current value in SoC. If not sure, do not change.
 
+config SYS_DPAA_PME
+	bool
+
+config SYS_DPAA_DCE
+	bool
+
+config SYS_DPAA_RMAN
+	bool
+
 config A003399_NOR_WORKAROUND
 	bool
 	help
@@ -1195,6 +1227,9 @@
 config FSL_PCIE_RESET
 	bool
 
+config SYS_PMAN
+	bool
+
 config SYS_FSL_RAID_ENGINE
 	bool
 

diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 3dccc0e..013a171 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c

@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ed89011..c7d473d 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -23,7 +23,7 @@
  */
 static void check_erratum_a4849(uint32_t svr)
 {
-	void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
+	void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000;
 	unsigned int i;
 
 #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
@@ -120,7 +120,7 @@
  */
 static void check_erratum_a007212(void)
 {
-	u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
+	u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
 
 	if (in_be32(plldgdcr) & 0x1fe) {
 		/* check if PLL ratio is set by workaround */

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 49a1aac..be85c54 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c

@@ -264,7 +264,7 @@
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-	for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
+	for (i = 0; i < CFG_SYS_NUM_FMAN; i++) {
 		printf("       FMAN%d: %s MHz\n", i + 1,
 			strmhz(buf1, sysinfo.freq_fman[i]));
 	}
@@ -417,14 +417,14 @@
 /* Common ddr init for non-corenet fsl 85xx platforms */
 #ifndef CONFIG_FSL_CORENET
 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
-	!defined(CONFIG_SYS_INIT_L2_ADDR)
+	!defined(CFG_SYS_INIT_L2_ADDR)
 int dram_init(void)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
 	defined(CONFIG_ARCH_QEMU_E500)
 	gd->ram_size = fsl_ddr_sdram_size();
 #else
-	gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
 
 	return 0;
@@ -486,7 +486,7 @@
 #endif /* CONFIG_SYS_RAMBOOT */
 #endif
 
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+#if CFG_POST & CFG_SYS_POST_MEMORY
 
 /* Board-specific functions defined in each board's ddr.c */
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
@@ -591,7 +591,7 @@
 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
 {
-	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+	u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
 	unsigned long epn;
 	u32 tsize, valid, ptr;
 	int ddr_esel;
@@ -624,8 +624,8 @@
 	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
 
 #if !defined(CONFIG_PHYS_64BIT) || \
-    !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
-	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+    !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
+	(CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
 		test_cap = p_size;
 #else
 		test_cap = gd->ram_size;
@@ -635,7 +635,7 @@
 		p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
 		if (reset_tlb(p_addr, p_size, phys_offset) == -1)
 			return -1;
-		*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+		*vstart = CFG_SYS_DDR_SDRAM_BASE;
 		*size = (u32) p_size;
 		printf("Testing 0x%08llx - 0x%08llx\n",
 			(u64)(*vstart) + (*phys_offset),
@@ -651,13 +651,13 @@
 {
 	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
 
-	*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+	*vstart = CFG_SYS_DDR_SDRAM_BASE;
 	*size = (u32) p_size;	/* CONFIG_MAX_MEM_MAPPED < 4G */
 	*phys_offset = 0;
 
 #if !defined(CONFIG_PHYS_64BIT) || \
-    !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
-	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+    !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
+	(CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
 		if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
 			puts("Cannot test more than ");
 			print_size(CONFIG_MAX_MEM_MAPPED,

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 47bea51..f07e8ab 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -162,10 +162,10 @@
 
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
 
-	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+	for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
 		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 			/* find and disable LAW of SRAM */
-			struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
+			struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR);
 
 			if (law.index == -1) {
 				printf("\nFatal error happened\n");
@@ -232,7 +232,7 @@
 			have_hwconfig = true;
 	}
 
-	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+	for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
 		if (have_hwconfig) {
 			sprintf(cpc_subarg, "cpc%u", i + 1);
 			cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
@@ -273,7 +273,7 @@
 	int i;
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
 
-	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+	for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
 		/* skip CPC when it used as all SRAM */
 		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
 			continue;
@@ -315,15 +315,15 @@
 {
 	ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 ddr_pll_ratio;
-	u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
-	u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
-	u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
+	u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
+	u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28);
+	u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
-	u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
-	u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
+	u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40);
+	u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
-	u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
-	u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
+	u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60);
+	u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68);
 #endif
 #endif
 	/*
@@ -378,7 +378,7 @@
 ulong cpu_init_f(void)
 {
 	extern void m8560_cpm_reset (void);
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
@@ -403,7 +403,7 @@
 
 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
 	/* Disable the LAW created for NOR flash by the PBI commands */
-	law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
+	law = find_law(CFG_SYS_PBI_FLASH_BASE);
 	if (law.index != -1)
 		disable_law(law.index);
 
@@ -430,7 +430,7 @@
 	/* Invalidate the CPC before DDR gets enabled */
 	invalidate_cpc();
 
- #ifdef CONFIG_SYS_DCSRBAR_PHYS
+ #ifdef CFG_SYS_DCSRBAR_PHYS
 	/* set DCSRCR so that DCSR space is 1G */
 	setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
 	in_be32(&gur->dcsrcr);
@@ -533,7 +533,7 @@
 	asm("msync;isync");
 	cache_ctl = l2cache->l2ctl;
 
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR)
 	if (cache_ctl & MPC85xx_L2CTL_L2E) {
 		/* Clear L2 SRAM memory-mapped base address */
 		out_be32(&l2cache->l2srbar0, 0x0);
@@ -590,15 +590,15 @@
 
 	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 		puts("already enabled");
-#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
+#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE)
 		u32 l2srbar = l2cache->l2srbar0;
 		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
-				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
-			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
+				&& l2srbar >= CFG_SYS_FLASH_BASE) {
+			l2srbar = CFG_SYS_INIT_L2_ADDR;
 			l2cache->l2srbar0 = l2srbar;
-			printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
+			printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR);
 		}
-#endif /* CONFIG_SYS_INIT_L2_ADDR */
+#endif /* CFG_SYS_INIT_L2_ADDR */
 		puts("\n");
 	} else {
 		asm("msync;isync");
@@ -625,9 +625,9 @@
 #endif
 
 	/* enable the cache */
-	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
+	mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0);
 
-	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
+	if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 		while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 			;
 		print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
@@ -656,7 +656,7 @@
 int cpu_init_r(void)
 {
 	__maybe_unused u32 svr = get_svr();
-#ifdef CONFIG_SYS_LBC_LCRR
+#ifdef CFG_SYS_LBC_LCRR
 	fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
 #endif
 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
@@ -763,13 +763,13 @@
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
 	if (IS_SVR_REV(svr, 1, 0)) {
 		int i;
-		__be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
+		__be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c;
 
 		for (i = 0; i < 12; i++) {
 			p += i + (i > 5 ? 11 : 0);
 			out_be32(p, 0x2);
 		}
-		p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
+		p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108;
 		out_be32(p, 0x34);
 	}
 #endif
@@ -799,18 +799,18 @@
 	{
 		if (SVR_MAJ(svr) < 3) {
 			void *p;
-			p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+			p = (void *)CFG_SYS_DCSRBAR + 0x20520;
 			setbits_be32(p, 1 << (31 - 14));
 		}
 	}
 #endif
 
-#ifdef CONFIG_SYS_LBC_LCRR
+#ifdef CFG_SYS_LBC_LCRR
 	/*
 	 * Modify the CLKDIV field of LCRR register to improve the writing
 	 * speed for NOR flash.
 	 */
-	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
+	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR);
 	__raw_readl(&lbc->lcrr);
 	isync();
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
@@ -850,7 +850,7 @@
 	 */
 	if (IS_SVR_REV(get_svr(), 1, 0)) {
 		struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
-			(CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
+			(CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET);
 		setbits_be32(&dcfg->ecccr1,
 				(DCSR_DCFG_ECC_DISABLE_USB1 |
 				 DCSR_DCFG_ECC_DISABLE_USB2));

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 18bfa2a..a67f37e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c

@@ -17,15 +17,15 @@
 #ifdef CONFIG_A003399_NOR_WORKAROUND
 void setup_ifc(void)
 {
-	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	struct fsl_ifc ifc_regs = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
-	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
+	phys_addr_t flash_phys = CFG_SYS_FLASH_BASE_PHYS;
 
 	/*
 	 * Adjust the TLB we were running out of to match the phys addr of the
 	 * chip select we are adjusting and will return to.
 	 */
-	flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
+	flash_phys += (~CFG_SYS_AMASK0) + 1 - 4*1024*1024;
 
 	_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
 	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
@@ -52,7 +52,7 @@
  *
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  * bacause flash's physical address is going to change as
- * CONFIG_SYS_FLASH_BASE_PHYS.
+ * CFG_SYS_FLASH_BASE_PHYS.
  */
 	_mas0 = MAS0_TLBSEL(1) |
 			MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
@@ -72,9 +72,9 @@
 #endif
 
 	/* Change flash's physical address */
-	ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
-	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
-	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+	ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CFG_SYS_CSPR0);
+	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CFG_SYS_CSOR0);
+	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CFG_SYS_AMASK0);
 
 	return;
 }
@@ -101,7 +101,7 @@
 
 #ifdef CONFIG_ARCH_QEMU_E500
 	/*
-	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
+	 * CFG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
 	 * so we need to populate it before it accesses it.
 	 */
 	gd->fdt_blob = fdt;
@@ -109,9 +109,9 @@
 
 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
 	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
-	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
-	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
-	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
+	mas2 = FSL_BOOKE_MAS2(CFG_SYS_CCSRBAR, MAS2_I|MAS2_G);
+	mas3 = FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
+	mas7 = FSL_BOOKE_MAS7(CFG_SYS_CCSRBAR_PHYS);
 
 	write_tlb(mas0, mas1, mas2, mas3, mas7);
 

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 1161938..a7e1df1 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c

@@ -144,14 +144,14 @@
 	}
 #ifdef CONFIG_DEEP_SLEEP
 #ifdef CONFIG_SPL_MMC_BOOT
-	off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
-		CONFIG_SYS_MMC_U_BOOT_SIZE);
+	off = fdt_add_mem_rsv(blob, CFG_SYS_MMC_U_BOOT_START,
+		CFG_SYS_MMC_U_BOOT_SIZE);
 	if (off < 0)
 		printf("Failed to reserve memory for SD deep sleep: %s\n",
 		       fdt_strerror(off));
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
-		CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
+	off = fdt_add_mem_rsv(blob, CFG_SYS_SPI_FLASH_U_BOOT_START,
+		CFG_SYS_SPI_FLASH_U_BOOT_SIZE);
 	if (off < 0)
 		printf("Failed to reserve memory for SPI deep sleep: %s\n",
 		       fdt_strerror(off));
@@ -167,7 +167,7 @@
 	cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
 	u32 cfg0 = in_be32(&cpc->cpccfg0);
 
-	size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
+	size = CPC_CFG0_SZ_K(cfg0) * 1024 * CFG_SYS_NUM_CPC;
 	num_ways = CPC_CFG0_NUM_WAYS(cfg0);
 	line_size = CPC_CFG0_LINE_SZ(cfg0);
 	num_sets = size / (line_size * num_ways);
@@ -448,7 +448,7 @@
 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
 			  unsigned long freq)
 {
-	phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
+	phys_addr_t phys = offset + CFG_SYS_CCSRBAR_PHYS;
 	int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
 
 	if (off >= 0) {
@@ -469,7 +469,7 @@
 	ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
 			sysinfo.freq_fman[0]);
 
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
 			sysinfo.freq_fman[1]);
 #endif
@@ -649,7 +649,7 @@
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "ns16550",
-		"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+		"clock-frequency", CFG_SYS_NS16550_CLK, 1);
 #endif
 
 #ifdef CONFIG_FSL_CORENET
@@ -679,17 +679,17 @@
 
 	ft_fixup_dpaa_clks(blob);
 
-#if defined(CONFIG_SYS_BMAN_MEM_PHYS)
+#if defined(CFG_SYS_BMAN_MEM_PHYS)
 	fdt_portal(blob, "fsl,bman-portal", "bman-portals",
-			(u64)CONFIG_SYS_BMAN_MEM_PHYS,
-			CONFIG_SYS_BMAN_MEM_SIZE);
+			(u64)CFG_SYS_BMAN_MEM_PHYS,
+			CFG_SYS_BMAN_MEM_SIZE);
 	fdt_fixup_bportals(blob);
 #endif
 
-#if defined(CONFIG_SYS_QMAN_MEM_PHYS)
+#if defined(CFG_SYS_QMAN_MEM_PHYS)
 	fdt_portal(blob, "fsl,qman-portal", "qman-portals",
-			(u64)CONFIG_SYS_QMAN_MEM_PHYS,
-			CONFIG_SYS_QMAN_MEM_SIZE);
+			(u64)CFG_SYS_QMAN_MEM_PHYS,
+			CFG_SYS_QMAN_MEM_SIZE);
 
 	fdt_fixup_qportals(blob);
 #endif
@@ -737,7 +737,7 @@
  * beginning of CCSR.
  */
 #define CCSR_VIRT_TO_PHYS(x) \
-	(CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
+	(CFG_SYS_CCSRBAR_PHYS + ((x) - CFG_SYS_CCSRBAR))
 
 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
 {
@@ -751,7 +751,7 @@
  * This function compares several CONFIG_xxx macros that contain physical
  * addresses with the corresponding nodes in the device tree, to see if
  * the physical addresses are all correct.  For example, if
- * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
+ * CFG_SYS_NS16550_COM1 is defined, then it contains the virtual address
  * of the first UART.  We convert this to a physical address and compare
  * that with the physical address of the first ns16550-compatible node
  * in the device tree.  If they don't match, then we display a warning.
@@ -783,8 +783,8 @@
 		return 0;
 	}
 
-	if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
-		msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
+	if (addr != CFG_SYS_CCSRBAR_PHYS) {
+		msg("CCSR", CFG_SYS_CCSRBAR_PHYS, addr);
 		/* No point in checking anything else */
 		return 0;
 	}
@@ -796,15 +796,15 @@
 	 */
 	aliases = fdt_path_offset(fdt, "/aliases");
 	if (aliases > 0) {
-#ifdef CONFIG_SYS_NS16550_COM1
+#ifdef CFG_SYS_NS16550_COM1
 		if (!fdt_verify_alias_address(fdt, aliases, "serial0",
-			CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
+			CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM1)))
 			return 0;
 #endif
 
-#ifdef CONFIG_SYS_NS16550_COM2
+#ifdef CFG_SYS_NS16550_COM2
 		if (!fdt_verify_alias_address(fdt, aliases, "serial1",
-			CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
+			CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM2)))
 			return 0;
 #endif
 	}
@@ -818,12 +818,12 @@
 	 * the 'reg' property to be wrong, so check it here.  For now, we
 	 * only check for "fsl,elbc" nodes.
 	 */
-#ifdef CONFIG_SYS_LBC_ADDR
+#ifdef CFG_SYS_LBC_ADDR
 	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
 	if (off > 0) {
 		const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
 		if (reg) {
-			uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
+			uint64_t uaddr = CCSR_VIRT_TO_PHYS(CFG_SYS_LBC_ADDR);
 
 			addr = fdt_translate_address(fdt, off, reg);
 			if (uaddr != addr) {

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 3a6ce32..9b6577e 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c

@@ -203,7 +203,7 @@
 	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
 	struct ccsr_sfp_regs  __iomem *sfp_regs =
-			(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+			(struct ccsr_sfp_regs __iomem *)(CFG_SYS_SFP_ADDR);
 	u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
 	u32 bc_status, fc_status, dc_status, pll_sr2;
 	serdes_corenet_t  __iomem *srds_regs = (void *)sd_addr;

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 437ecde..7c2de02 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c

@@ -264,9 +264,9 @@
 }
 #endif
 
-#ifndef CONFIG_SYS_DCSRBAR_PHYS
-#define CONFIG_SYS_DCSRBAR_PHYS	0x80000000 /* Must be 1GB-aligned for rev1.0 */
-#define CONFIG_SYS_DCSRBAR	0x80000000
+#ifndef CFG_SYS_DCSRBAR_PHYS
+#define CFG_SYS_DCSRBAR_PHYS	0x80000000 /* Must be 1GB-aligned for rev1.0 */
+#define CFG_SYS_DCSRBAR	0x80000000
 #define __DCSR_NOT_DEFINED_BY_CONFIG
 #endif
 
@@ -315,16 +315,16 @@
 	 */
 	{
 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
-		struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
+		struct law_entry law = find_law(CFG_SYS_DCSRBAR_PHYS);
 		int law_index;
 		if (law.index == -1)
-			law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
+			law_index = set_next_law(CFG_SYS_DCSRBAR_PHYS,
 						 LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
 		else
-			set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
+			set_law(law.index, CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
 				LAW_TRGT_IF_DCSR);
 #endif
-		u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
+		u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114;
 		out_be32(p, rcw5);
 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
 		if (law.index == -1)

diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 9ad48d4..d5df02d 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c

@@ -104,7 +104,7 @@
 		fm = (void *)CFG_SYS_FSL_FM1_ADDR;
 		break;
 
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	case FSL_HW_PORTAL_FMAN2:
 		fm = (void *)CFG_SYS_FSL_FM2_ADDR;
 		break;
@@ -201,7 +201,7 @@
 	setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl,
 				fman1_liodn_tbl_sz);
 
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	set_fman_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz);
 	setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl,
 				fman2_liodn_tbl_sz);
@@ -373,7 +373,7 @@
 	fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz);
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_liodn_tbl_fman(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz);
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	fdt_fixup_liodn_tbl_fman(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz);
 #endif
 #endif
@@ -387,7 +387,7 @@
 	fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
 #endif
 
-	ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR;
+	ccsr_pcix_t *pcix = (ccsr_pcix_t *)CFG_SYS_PCIE1_ADDR;
 	int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0;
 
 	if (pci_ver >= 0x0204) {

diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index f109ecb..44f8ed8 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c

@@ -195,7 +195,7 @@
 	/* use last 4K of mapped memory */
 	bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
 		CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
-		CONFIG_SYS_SDRAM_BASE - 4096;
+		CFG_SYS_SDRAM_BASE - 4096;
 	if (pagesize)
 		*pagesize = 4096;
 

diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
index 8a83346..540a6e6 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c

@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1,  2,  1, 0),
 	SET_QP_INFO(3,  4,  2, 1),
@@ -66,7 +66,7 @@
 	SET_FMAN_RX_1G_LIODN(1, 2, 12),
 	SET_FMAN_RX_1G_LIODN(1, 3, 13),
 	SET_FMAN_RX_1G_LIODN(1, 4, 14),
-#if (CONFIG_SYS_NUM_FM1_10GEC == 1)
+#if (CFG_SYS_NUM_FM1_10GEC == 1)
 	SET_FMAN_RX_10G_LIODN(1, 0, 15),
 #endif
 };

diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c
index 7db05d9..8f64525 100644
--- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c

@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1,  2,  1, 0),
 	SET_QP_INFO(3,  4,  2, 1),

diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index 5b766f1..db41116 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c

@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO( 1,  2,  1, 0),
 	SET_QP_INFO( 3,  4,  2, 1),
@@ -62,7 +62,7 @@
 };
 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
 
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 struct fman_liodn_id_table fman2_liodn_tbl[] = {
 	SET_FMAN_RX_1G_LIODN(2, 0, 16),
 	SET_FMAN_RX_1G_LIODN(2, 1, 17),
@@ -101,7 +101,7 @@
 	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(96, 106),
 #ifdef CONFIG_SYS_DPAA_FMAN
 	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64),
 #endif
 #endif

diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
index e3d163a..bd05eae 100644
--- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c

@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 2, 1, 0),
 	SET_QP_INFO(3, 4, 2, 1),
@@ -57,7 +57,7 @@
 };
 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
 
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 struct fman_liodn_id_table fman2_liodn_tbl[] = {
 	SET_FMAN_RX_1G_LIODN(2, 0, 17),
 	SET_FMAN_RX_1G_LIODN(2, 1, 18),
@@ -101,7 +101,7 @@
 #ifdef CONFIG_SYS_DPAA_FMAN
 	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
 #endif
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160),
 #endif
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index d37e1cc..391751c 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S

@@ -276,8 +276,8 @@
 	mtspr	SPRN_L2CSR1,r3
 #endif
 
-	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
-	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
+	lis	r3,CFG_SYS_INIT_L2CSR0@h
+	ori	r3,r3,CFG_SYS_INIT_L2CSR0@l
 	mtspr	SPRN_L2CSR0,r3
 	isync
 2:

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 31d0481..a6e352c 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c

@@ -218,22 +218,22 @@
 #ifndef CONFIG_PME_PLAT_CLK_DIV
 	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK];
 		break;
 	case 2:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 2;
 		break;
 	case 3:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 3;
 		break;
 	case 4:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 4;
 		break;
 	case 6:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 2;
 		break;
 	case 7:
-		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
+		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown PME clock select!\n");
@@ -243,7 +243,7 @@
 
 	}
 #else
-	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
+	sys_info->freq_pme = sys_info->freq_systembus / CFG_SYS_PME_CLK;
 
 #endif
 #endif
@@ -380,25 +380,25 @@
 #ifndef CONFIG_FM_PLAT_CLK_DIV
 	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK];
 		break;
 	case 2:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 2;
 		break;
 	case 3:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 3;
 		break;
 	case 4:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 4;
 		break;
 	case 5:
 		sys_info->freq_fman[0] = sys_info->freq_systembus;
 		break;
 	case 6:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 2;
 		break;
 	case 7:
-		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
+		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan1 clock select!\n");
@@ -406,32 +406,32 @@
 		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
 		break;
 	}
-#if (CONFIG_SYS_NUM_FMAN) == 2
-#ifdef CONFIG_SYS_FM2_CLK
+#if (CFG_SYS_NUM_FMAN) == 2
+#ifdef CFG_SYS_FM2_CLK
 #define FM2_CLK_SEL	0x00000038
 #define FM2_CLK_SHIFT	3
 	rcw_tmp = in_be32(&gur->rcwsr[15]);
 	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
 	case 1:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1];
 		break;
 	case 2:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 2;
 		break;
 	case 3:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 3;
 		break;
 	case 4:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 4;
 		break;
 	case 5:
 		sys_info->freq_fman[1] = sys_info->freq_systembus;
 		break;
 	case 6:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 2;
 		break;
 	case 7:
-		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
+		sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan2 clock select!\n");
@@ -440,9 +440,9 @@
 		break;
 	}
 #endif
-#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
+#endif	/* CFG_SYS_NUM_FMAN == 2 */
 #else
-	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
+	sys_info->freq_fman[0] = sys_info->freq_systembus / CFG_SYS_FM1_CLK;
 #endif
 #endif
 
@@ -491,7 +491,7 @@
 	} else {
 		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
 	}
-#if (CONFIG_SYS_NUM_FMAN) == 2
+#if (CFG_SYS_NUM_FMAN) == 2
 	if (rcw_tmp & FM2_CLK_SEL) {
 		if (rcw_tmp & HWA_ASYNC_DIV)
 			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;

diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index 47df3c2..ce2b9c2 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c

@@ -14,10 +14,10 @@
 
 ulong cpu_init_f(void)
 {
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
 	ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
 
-	out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
+	out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR);
 
 	/* set MBECCDIS=1, SBECCDIS=1 */
 	out_be32(&l2cache->l2errdis,

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 5341756..562b699 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S

@@ -128,7 +128,7 @@
 	.Lconf_pair_start:
 
 	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
-	.long CONFIG_SYS_INIT_L2_ADDR
+	.long CFG_SYS_INIT_L2_ADDR
 
 	.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
 	.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
@@ -428,12 +428,12 @@
 	mtspr	SPRN_BUCSR,r0
 #endif
 
-#if defined(CONFIG_SYS_INIT_DBCR)
+#if defined(CFG_SYS_INIT_DBCR)
 	lis	r1,0xffff
 	ori	r1,r1,0xffff
 	mtspr	DBSR,r1			/* Clear all status bits */
-	lis	r0,CONFIG_SYS_INIT_DBCR@h	/* DBCR0[IDM] must be set */
-	ori	r0,r0,CONFIG_SYS_INIT_DBCR@l
+	lis	r0,CFG_SYS_INIT_DBCR@h	/* DBCR0[IDM] must be set */
+	ori	r0,r0,CFG_SYS_INIT_DBCR@l
 	mtspr	DBCR0,r0
 #endif
 
@@ -573,34 +573,34 @@
  * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
  * long-term TLBs, so we use TLB0 here.
  */
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS)
 
-#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
-#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
+#if !defined(CFG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CFG_SYS_CCSRBAR_PHYS_LOW)
+#error "CFG_SYS_CCSRBAR_PHYS_HIGH and CFG_SYS_CCSRBAR_PHYS_LOW) must be defined."
 #endif
 
 create_ccsr_new_tlb:
 	/*
 	 * Create a TLB for the new location of CCSR.  Register R8 is reserved
-	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
+	 * for the virtual address of this TLB (CFG_SYS_CCSRBAR).
 	 */
-	lis	r8, CONFIG_SYS_CCSRBAR@h
-	ori	r8, r8, CONFIG_SYS_CCSRBAR@l
-	lis	r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
-	ori	r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
+	lis	r8, CFG_SYS_CCSRBAR@h
+	ori	r8, r8, CFG_SYS_CCSRBAR@l
+	lis	r9, (CFG_SYS_CCSRBAR + 0x1000)@h
+	ori	r9, r9, (CFG_SYS_CCSRBAR + 0x1000)@l
 	create_tlb0_entry 0, \
 		0, BOOKE_PAGESZ_4K, \
-		CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
-		CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
-		CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+		CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
+		CFG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
+		CFG_SYS_CCSRBAR_PHYS_HIGH, r3
 	/*
 	 * Create a TLB for the current location of CCSR.  Register R9 is reserved
-	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
+	 * for the virtual address of this TLB (CFG_SYS_CCSRBAR + 0x1000).
 	 */
 create_ccsr_old_tlb:
 	create_tlb0_entry 1, \
 		0, BOOKE_PAGESZ_4K, \
-		CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
+		CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
 		CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
 		0, r3 /* The default CCSR address is always a 32-bit number */
 
@@ -634,7 +634,7 @@
 
 #ifdef CONFIG_FSL_CORENET
 
-#define CCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
+#define CCSR_LAWBARH0	(CFG_SYS_CCSRBAR + 0x1000)
 #define LAW_SIZE_4K	0xb
 #define CCSRBAR_LAWAR	(LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
 #define CCSRAR_C	0x80000000	/* Commit */
@@ -644,10 +644,10 @@
 	 * On CoreNet systems, we create the temporary LAW using a special LAW
 	 * target ID of 0x1e.  LAWBARH is at offset 0xc00 in CCSR.
 	 */
-	lis     r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
-	ori     r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
-	lis     r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
-	ori     r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+	lis     r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h
+	ori     r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l
+	lis     r1, CFG_SYS_CCSRBAR_PHYS_LOW@h
+	ori     r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l
 	lis     r2, CCSRBAR_LAWAR@h
 	ori     r2, r2, CCSRBAR_LAWAR@l
 
@@ -683,10 +683,10 @@
 	 * instruction.
 	 */
 write_new_ccsrbar:
-	lis	r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
-	ori	r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
-	lis	r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
-	ori	r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+	lis	r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h
+	ori	r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l
+	lis	r1, CFG_SYS_CCSRBAR_PHYS_LOW@h
+	ori	r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l
 	lis	r2, CCSRAR_C@h
 	ori	r2, r2, CCSRAR_C@l
 
@@ -723,9 +723,9 @@
 	lwz	r0, 0(r9)
 	isync
 
-/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
-#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
-			   (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
+/* CFG_SYS_CCSRBAR_PHYS right shifted by 12 */
+#define CCSRBAR_PHYS_RS12 ((CFG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
+			   (CFG_SYS_CCSRBAR_PHYS_LOW >> 12))
 
 	/* Write the new value to CCSRBAR. */
 	lis	r0, CCSRBAR_PHYS_RS12@h
@@ -752,10 +752,10 @@
 
 	/* Delete the temporary TLBs */
 delete_temp_tlbs:
-	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
-	delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
+	delete_tlb0_entry 0, CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
+	delete_tlb0_entry 1, CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
 
-#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
+#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) */
 
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 create_ccsr_l2_tlb:
@@ -765,14 +765,14 @@
 	 */
 	create_tlb0_entry 0, \
 		0, BOOKE_PAGESZ_4K, \
-		CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
-		CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
-		CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+		CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
+		CFG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
+		CFG_SYS_CCSRBAR_PHYS_HIGH, r3
 
 enable_l2_cluster_l2:
 	/* enable L2 cache */
-	lis	r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
-	ori	r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
+	lis	r3, (CFG_SYS_CCSRBAR + 0xC20000)@h
+	ori	r3, r3, (CFG_SYS_CCSRBAR + 0xC20000)@l
 	li	r4, 33	/* stash id */
 	stw	r4, 4(r3)
 	lis	r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
@@ -813,7 +813,7 @@
 	beq	1b
 
 delete_ccsr_l2_tlb:
-	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
+	delete_tlb0_entry 0, CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
 #endif
 
 	/*
@@ -863,7 +863,7 @@
 	andi.	r1,r3,L1CSR0_DCE@l
 	beq	2b
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
-#define DCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
+#define DCSR_LAWBARH0	(CFG_SYS_CCSRBAR + 0x1000)
 #define LAW_SIZE_1M	0x13
 #define DCSRBAR_LAWAR	(LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
 
@@ -884,13 +884,13 @@
 	rlwimi	r0, r8, 16, MAS0_ESEL_MSK
 	lis	r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
 	ori	r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
-	lis	r7, CONFIG_SYS_CCSRBAR@h
-	ori	r7, r7, CONFIG_SYS_CCSRBAR@l
+	lis	r7, CFG_SYS_CCSRBAR@h
+	ori	r7, r7, CFG_SYS_CCSRBAR@l
 	ori	r2, r7, MAS2_I|MAS2_G
-	lis	r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
-	ori	r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
-	lis	r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
-	ori	r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+	lis	r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
+	ori	r3, r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
+	lis	r4, CFG_SYS_CCSRBAR_PHYS_HIGH@h
+	ori	r4, r4, CFG_SYS_CCSRBAR_PHYS_HIGH@l
 	mtspr	MAS0, r0
 	mtspr	MAS1, r1
 	mtspr	MAS2, r2
@@ -1132,7 +1132,7 @@
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
 		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
-		CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CFG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
 /*
@@ -1148,7 +1148,7 @@
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
 		CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \
-		CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
 #else
@@ -1164,19 +1164,19 @@
 #endif
 
 	/* create a temp mapping in AS=1 to the stack */
-#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
-    defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
+#if defined(CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
+    defined(CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
 	create_tlb1_entry 14, \
 		1, BOOKE_PAGESZ_16K, \
-		CONFIG_SYS_INIT_RAM_ADDR, 0, \
-		CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
-		CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
+		CFG_SYS_INIT_RAM_ADDR, 0, \
+		CFG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
 
 #else
 	create_tlb1_entry 14, \
 		1, BOOKE_PAGESZ_16K, \
-		CONFIG_SYS_INIT_RAM_ADDR, 0, \
-		CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CFG_SYS_INIT_RAM_ADDR, 0, \
+		CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 #endif
 
@@ -1194,8 +1194,8 @@
 
 	/* Allocate Initial RAM in data cache.
 	 */
-	lis	r3,CONFIG_SYS_INIT_RAM_ADDR@h
-	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+	lis	r3,CFG_SYS_INIT_RAM_ADDR@h
+	ori	r3,r3,CFG_SYS_INIT_RAM_ADDR@l
 	mfspr	r2, L1CFG0
 	andi.	r2, r2, 0x1ff
 	/* cache size * 1024 / (2 * L1 line size) */
@@ -1230,11 +1230,11 @@
 	.globl	_start_cont
 _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
-	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
-	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+	lis	r3,(CFG_SYS_INIT_RAM_ADDR)@h
+	ori	r3,r3,((CFG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
 
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
-#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE
 #error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
 #endif
 
@@ -1243,8 +1243,8 @@
 #endif
 
 	/* End of RAM */
-	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
-	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+	lis	r4,(CFG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CFG_SYS_INIT_RAM_SIZE)@l
 
 	li	r0,0
 
@@ -1826,8 +1826,8 @@
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
-	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
-	ori	r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
+	lis	r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
+	ori	r3,r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
 	mfspr	r4,L1CFG0
 	andi.	r4,r4,0x1ff
 	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
@@ -1844,8 +1844,8 @@
 	sync
 
 	/* Invalidate the TLB entries for the cache */
-	lis	r3,CONFIG_SYS_INIT_RAM_ADDR@h
-	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+	lis	r3,CFG_SYS_INIT_RAM_ADDR@h
+	ori	r3,r3,CFG_SYS_INIT_RAM_ADDR@l
 	tlbivax	0,r3
 	addi	r3,r3,0x1000
 	tlbivax	0,r3

diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
index d2744bb..bab076b 100644
--- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c

@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),

diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index 99b52ba..59f4f9c 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c

@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),

diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c
index 17521dc..390bb11 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c

@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index 172dbdb..37ea778 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c

@@ -8,7 +8,7 @@
 #include <asm/fsl_liodn.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	/* dqrr liodn, frame data liodn, liodn off, sdest */
 	SET_QP_INFO(1, 27, 1, 0),
 	SET_QP_INFO(2, 28, 1, 0),
@@ -122,7 +122,7 @@
 	SET_FMAN_RX_10G_LIODN(1, 1, 95),
 };
 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 struct fman_liodn_id_table fman2_liodn_tbl[] = {
 	SET_FMAN_RX_1G_LIODN(2, 0, 88),
 	SET_FMAN_RX_1G_LIODN(2, 1, 89),
@@ -175,7 +175,7 @@
 	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
 #ifdef CONFIG_SYS_DPAA_FMAN
 	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069),
 #endif
 #endif

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 81e6072..5d21bef 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c

@@ -302,7 +302,7 @@
 unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
 				 unsigned int memsize_in_meg)
 {
-	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+	unsigned int ram_tlb_address = (unsigned int)CFG_SYS_DDR_SDRAM_BASE;
 	u64 memsize = (u64)memsize_in_meg << 20;
 	u64 size;
 
@@ -324,13 +324,13 @@
 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 {
 	return
-		setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+		setup_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
 }
 
 /* Invalidate the DDR TLBs for the requested size */
 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 {
-	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+	u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
 	unsigned long epn;
 	u32 tsize, valid, ptr;
 	phys_addr_t rpn = 0;
@@ -351,7 +351,7 @@
 
 void clear_ddr_tlbs(unsigned int memsize_in_meg)
 {
-	clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+	clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
 }
 
 

diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index f28826c..d918b43 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds

@@ -64,7 +64,7 @@
 	_end = .;
 
 #if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
-#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS)
 	mmc_u_boot_offs = .;
 #endif
 #endif
@@ -101,7 +101,7 @@
 	.resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : {
 		KEEP(*(.resetvec))
 	} = 0xffff
-#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS)
 	mmc_u_boot_offs = .;
 #endif
 #endif

diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S
index 0ebb7b3..1f1107e 100644
--- a/arch/powerpc/cpu/mpc8xx/start.S
+++ b/arch/powerpc/cpu/mpc8xx/start.S

@@ -141,8 +141,8 @@
 	mtspr	DER, r2
 
 	/* set up the stack on top of internal DPRAM */
-	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
-	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
+	lis	r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h
+	ori	r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l
 	stw	r0, -4(r3)
 	stw	r0, -8(r3)
 	addi	r1, r3, -8

diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
index 1101b91..1c051d1 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c

@@ -230,7 +230,7 @@
 
 int pamu_init(void)
 {
-	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	u32 base_addr = CFG_SYS_PAMU_ADDR;
 	struct ccsr_pamu *regs;
 	u32 i = 0;
 	u64 ppaact_phys, ppaact_lim, ppaact_size;
@@ -292,7 +292,7 @@
 void pamu_enable(void)
 {
 	u32 i = 0;
-	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	u32 base_addr = CFG_SYS_PAMU_ADDR;
 	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
 		setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
 			     PAMU_PCR_PE);
@@ -304,7 +304,7 @@
 void pamu_reset(void)
 {
 	u32 i  = 0;
-	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	u32 base_addr = CFG_SYS_PAMU_ADDR;
 	struct ccsr_pamu *regs;
 
 	for (i = 0; i < CONFIG_NUM_PAMU; i++) {
@@ -328,7 +328,7 @@
 void pamu_disable(void)
 {
 	u32 i  = 0;
-	u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+	u32 base_addr = CFG_SYS_PAMU_ADDR;
 
 
 	for (i = 0; i < CONFIG_NUM_PAMU; i++) {

diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index dd27416..35409dc 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c

@@ -309,42 +309,42 @@
 	 */
 	switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
 	case 0x0: /* boot from PCIE1 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_1);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_1);
 		break;
 	case 0x1: /* boot from PCIE2 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_2);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_2);
 		break;
 	case 0x2: /* boot from PCIE3 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_3);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_3);
 		break;
 	case 0x8: /* boot from SRIO1 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_RIO_1);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_RIO_1);
 		break;
 	case 0x9: /* boot from SRIO2 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_RIO_2);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_RIO_2);
 		break;

diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
index d917e9d..caad667 100644
--- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c
+++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c

@@ -16,22 +16,22 @@
 	int j;
 
 	tbl->start_addr[i] =
-			(uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE);
+			(uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE);
 	tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED));
 	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
 
 	i++;
-#ifdef CONFIG_SYS_FLASH_BASE_PHYS
+#ifdef CFG_SYS_FLASH_BASE_PHYS
 	tbl->start_addr[i] =
-		(uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS);
+		(uint64_t)virt_to_phys((void *)CFG_SYS_FLASH_BASE_PHYS);
 	tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */
 	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
 
 	i++;
 #endif
-#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR))
+#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR))
 	tbl->start_addr[i] =
-		(uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR);
+		(uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR);
 	tbl->size[i] = 256 * 1024; /* 256K CPC flash */
 	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
 

diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c815d19..dc1bc0d 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c

@@ -240,8 +240,8 @@
 	devdisr = &gur->devdisr;
 #endif
 	if (is_serdes_configured(SRIO1)) {
-		set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
-				law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
+		set_next_law(CFG_SYS_SRIO1_MEM_PHYS,
+				law_size_bits(CFG_SYS_SRIO1_MEM_SIZE),
 				LAW_TRGT_IF_RIO_1);
 		srio1_used = 1;
 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
@@ -256,8 +256,8 @@
 
 #ifdef CONFIG_SRIO2
 	if (is_serdes_configured(SRIO2)) {
-		set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
-				law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
+		set_next_law(CFG_SYS_SRIO2_MEM_PHYS,
+				law_size_bits(CFG_SYS_SRIO2_MEM_SIZE),
 				LAW_TRGT_IF_RIO_2);
 		srio2_used = 1;
 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
@@ -301,44 +301,44 @@
 	/* configure inbound window for slave's u-boot image */
 	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
 			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
-			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
-			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
+			CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
+			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
+			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
 			SRIO_IB_ATMU_AR
-			| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
+			| atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
 
 	/* configure inbound window for slave's u-boot image */
 	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
 			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
-			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
-			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
+			CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
+			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
+			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
 			SRIO_IB_ATMU_AR
-			| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
+			| atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
 
 	/* configure inbound window for slave's ucode and ENV */
 	debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
 			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
-			(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
-			(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
-			CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
+			(u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
+			(u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
+			CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
-			CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
+			CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
-			CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
+			CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
 			SRIO_IB_ATMU_AR
-			| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
+			| atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
 }
 
 void srio_boot_master_release_slave(int port)
@@ -368,11 +368,11 @@
 			if (port - 1)
 				out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[1].rowbar,
-					CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
+					CFG_SYS_SRIO2_MEM_PHYS >> 12);
 			else
 				out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[1].rowbar,
-					CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
+					CFG_SYS_SRIO1_MEM_PHYS >> 12);
 			out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[1].rowar,
 					SRIO_OB_ATMU_AR_MAINT
@@ -390,12 +390,12 @@
 			if (port - 1)
 				out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[2].rowbar,
-					(CONFIG_SYS_SRIO2_MEM_PHYS
+					(CFG_SYS_SRIO2_MEM_PHYS
 					+ SRIO_MAINT_WIN_SIZE) >> 12);
 			else
 				out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[2].rowbar,
-					(CONFIG_SYS_SRIO1_MEM_PHYS
+					(CFG_SYS_SRIO1_MEM_PHYS
 					+ SRIO_MAINT_WIN_SIZE) >> 12);
 			out_be32((void *)&srio->atmu.port[port - 1]
 				.outbw[2].rowar,
@@ -407,10 +407,10 @@
 			 * by the maint-outbound window
 			 */
 			if (port - 1) {
-				out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+				out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
 					+ SRIO_LCSBA1CSR_OFFSET,
 					SRIO_LCSBA1CSR);
-				while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+				while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
 					+ SRIO_LCSBA1CSR_OFFSET)
 					!= SRIO_LCSBA1CSR)
 					;
@@ -418,15 +418,15 @@
 				 * And then set the BRR register
 				 * to release slave core
 				 */
-				out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+				out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
 					+ SRIO_MAINT_WIN_SIZE
-					+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
-					CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
+					+ CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
+					CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
 			} else {
-				out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+				out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
 					+ SRIO_LCSBA1CSR_OFFSET,
 					SRIO_LCSBA1CSR);
-				while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+				while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
 					+ SRIO_LCSBA1CSR_OFFSET)
 					!= SRIO_LCSBA1CSR)
 					;
@@ -434,10 +434,10 @@
 				 * And then set the BRR register
 				 * to release slave core
 				 */
-				out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+				out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
 					+ SRIO_MAINT_WIN_SIZE
-					+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
-					CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
+					+ CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
+					CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
 			}
 			debug("SRIOBOOT - MASTER: "
 					"Release slave successfully! Now the slave should start up!\n");

diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 79fe567..983c6f7 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h

@@ -32,14 +32,6 @@
 #define BPTR_VIRT_ADDR	0xfffff000
 #endif
 
-/* Since so many PPC SOCs have a semi-common LBC, define this here */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
-	defined(CONFIG_MPC83xx)
-#if !defined(CONFIG_FSL_IFC)
-#define CONFIG_FSL_LBC
-#endif
-#endif
-
 /* The TSEC driver uses the PHYLIB infrastructure */
 #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
 #include <config_phylib_all_drivers.h>
@@ -52,7 +44,7 @@
  * TODO: Convert this to a clock driver exists that can give us the UART
  * clock here.
  */
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CFG_SYS_NS16550_CLK		get_serial_clock()
 #endif
 
 #endif /* _ASM_CONFIG_H_ */

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 25d1b48..d9e5a7d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h

@@ -41,11 +41,11 @@
 #define QE_NUM_OF_SNUM			28
 
 #elif defined(CONFIG_ARCH_P1023)
-#define CONFIG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_NUM_FM1_DTSEC	2
-#define CONFIG_SYS_QMAN_NUM_PORTALS	3
-#define CONFIG_SYS_BMAN_NUM_PORTALS	3
-#define CONFIG_SYS_FM_MURAM_SIZE	0x10000
+#define CFG_SYS_NUM_FMAN		1
+#define CFG_SYS_NUM_FM1_DTSEC	2
+#define CFG_SYS_QMAN_NUM_PORTALS	3
+#define CFG_SYS_BMAN_NUM_PORTALS	3
+#define CFG_SYS_FM_MURAM_SIZE	0x10000
 
 /* P1024 is lower end variant of P1020 */
 #elif defined(CONFIG_ARCH_P1024)
@@ -65,32 +65,32 @@
 #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
-#define CONFIG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_NUM_FM1_DTSEC	5
-#define CONFIG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_NUM_FMAN		1
+#define CFG_SYS_NUM_FM1_DTSEC	5
+#define CFG_SYS_NUM_FM1_10GEC	1
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P3041)
-#define CONFIG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_NUM_FM1_DTSEC	5
-#define CONFIG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_NUM_FMAN		1
+#define CFG_SYS_NUM_FM1_DTSEC	5
+#define CFG_SYS_NUM_FM1_10GEC	1
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
-#define CONFIG_SYS_NUM_FMAN		2
-#define CONFIG_SYS_NUM_FM1_DTSEC	4
-#define CONFIG_SYS_NUM_FM2_DTSEC	4
-#define CONFIG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_NUM_FM2_10GEC	1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_NUM_FMAN		2
+#define CFG_SYS_NUM_FM1_DTSEC	4
+#define CFG_SYS_NUM_FM2_DTSEC	4
+#define CFG_SYS_NUM_FM1_10GEC	1
+#define CFG_SYS_NUM_FM2_10GEC	1
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -98,12 +98,12 @@
 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
 #elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_SYS_NUM_FMAN		2
-#define CONFIG_SYS_NUM_FM1_DTSEC	5
-#define CONFIG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_NUM_FM2_DTSEC	5
-#define CONFIG_SYS_NUM_FM2_10GEC	1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_NUM_FMAN		2
+#define CFG_SYS_NUM_FM1_DTSEC	5
+#define CFG_SYS_NUM_FM1_10GEC	1
+#define CFG_SYS_NUM_FM2_DTSEC	5
+#define CFG_SYS_NUM_FM2_10GEC	1
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_BSC9131)
@@ -119,26 +119,26 @@
 #elif defined(CONFIG_ARCH_T4240)
 #ifdef CONFIG_ARCH_T4240
 #define CFG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
-#define CONFIG_SYS_NUM_FM1_DTSEC	8
-#define CONFIG_SYS_NUM_FM1_10GEC	2
-#define CONFIG_SYS_NUM_FM2_DTSEC	8
-#define CONFIG_SYS_NUM_FM2_10GEC	2
+#define CFG_SYS_NUM_FM1_DTSEC	8
+#define CFG_SYS_NUM_FM1_10GEC	2
+#define CFG_SYS_NUM_FM2_DTSEC	8
+#define CFG_SYS_NUM_FM2_10GEC	2
 #else
-#define CONFIG_SYS_NUM_FM1_DTSEC	6
-#define CONFIG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_NUM_FM2_DTSEC	8
-#define CONFIG_SYS_NUM_FM2_10GEC	1
+#define CFG_SYS_NUM_FM1_DTSEC	6
+#define CFG_SYS_NUM_FM1_10GEC	1
+#define CFG_SYS_NUM_FM2_DTSEC	8
+#define CFG_SYS_NUM_FM2_10GEC	1
 #endif
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
 #define CFG_SYS_FSL_SRDS_3
 #define CFG_SYS_FSL_SRDS_4
-#define CONFIG_SYS_NUM_FMAN		2
-#define CONFIG_SYS_PME_CLK		0
+#define CFG_SYS_NUM_FMAN		2
+#define CFG_SYS_PME_CLK		0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_SYS_FM1_CLK		3
-#define CONFIG_SYS_FM2_CLK		3
-#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CFG_SYS_FM1_CLK		3
+#define CFG_SYS_FM2_CLK		3
+#define CFG_SYS_FM_MURAM_SIZE	0x60000
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -146,38 +146,38 @@
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_FM1_CLK		0
+#define CFG_SYS_NUM_FMAN		1
+#define CFG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
-#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CFG_SYS_FM_MURAM_SIZE	0x60000
 
 #ifdef CONFIG_ARCH_B4860
 #define CONFIG_MAX_DSP_CPUS		12
 #define CONFIG_NUM_DSP_CPUS		6
 #define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
-#define CONFIG_SYS_NUM_FM1_DTSEC	6
-#define CONFIG_SYS_NUM_FM1_10GEC	2
+#define CFG_SYS_NUM_FM1_DTSEC	6
+#define CFG_SYS_NUM_FM1_10GEC	2
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #else
 #define CONFIG_MAX_DSP_CPUS		2
 #define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
-#define CONFIG_SYS_NUM_FM1_DTSEC	4
-#define CONFIG_SYS_NUM_FM1_10GEC	0
+#define CFG_SYS_NUM_FM1_DTSEC	4
+#define CFG_SYS_NUM_FM1_10GEC	0
 #endif
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
 #define CFG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CFG_SYS_NUM_FMAN		1
+#define CFG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_PME_PLAT_CLK_DIV		2
-#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CFG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_FM_PLAT_CLK_DIV	1
-#define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
-#define CONFIG_SYS_FM_MURAM_SIZE	0x30000
+#define CFG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
+#define CFG_SYS_FM_MURAM_SIZE	0x30000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
@@ -186,36 +186,36 @@
 #elif defined(CONFIG_ARCH_T1024)
 #define CFG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_NUM_FM1_DTSEC	4
-#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CFG_SYS_NUM_FMAN		1
+#define CFG_SYS_NUM_FM1_DTSEC	4
+#define CFG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_SYS_FM1_CLK		0
+#define CFG_SYS_FM1_CLK		0
 #define CONFIG_QBMAN_CLK_DIV		1
-#define CONFIG_SYS_FM_MURAM_SIZE	0x30000
+#define CFG_SYS_FM_MURAM_SIZE	0x30000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 
 #elif defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_NUM_FMAN		1
+#define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CONFIG_SYS_FSL_SRDS_1
 #if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_NUM_FM1_DTSEC	8
-#define CONFIG_SYS_NUM_FM1_10GEC	4
+#define CFG_SYS_NUM_FM1_DTSEC	8
+#define CFG_SYS_NUM_FM1_10GEC	4
 #define CONFIG_SYS_FSL_SRDS_2
 #define CFG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #endif
 #define CONFIG_PME_PLAT_CLK_DIV		1
-#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FM1_CLK		0
+#define CFG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CFG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CFG_SYS_FM_MURAM_SIZE	0x28000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 
 

diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 5038cb9..a03f091 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h

@@ -469,7 +469,7 @@
 extern void init_early_memctl_regs(void);
 extern void upmconfig(uint upm, uint *table, uint size);
 
-#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
+#define LBC_BASE_ADDR ((fsl_lbc_t *)CFG_SYS_LBC_ADDR)
 #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
 #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
 #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))

diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index de85bcf..0af3d89 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h

@@ -18,15 +18,15 @@
 #define SET_SRIO_LIODN_1(port, idA) \
 	{ .id = { idA }, .num_ids = 1, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_2(port, idA, idB) \
 	{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
 	  .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
-		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_BASE(port, id_a) \
@@ -70,22 +70,22 @@
 	{ .compat[0] = name1, \
 	  .compat[1] = name2, \
 	  .id = { idA }, .num_ids = 1, \
-	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .reg_offset = off + CFG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 #define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
 	{ .compat = name, \
 	  .id = { idA }, .num_ids = 1, \
-	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .reg_offset = off + CFG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
 	{ .compat = name, \
 	  .id = { idA, idB }, .num_ids = 2, \
-	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	  .reg_offset = off + CFG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
 	}
 
 #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \

diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 06f9bfb..809ab1d 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h

@@ -193,35 +193,35 @@
 
 #define SET_STD_PCI_INFO(x, num) \
 {			\
-	x.regs = CONFIG_SYS_PCI##num##_ADDR;	\
-	x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
-	x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
-	x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
-	x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
-	x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
-	x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+	x.regs = CFG_SYS_PCI##num##_ADDR;	\
+	x.mem_bus = CFG_SYS_PCI##num##_MEM_BUS; \
+	x.mem_phys = CFG_SYS_PCI##num##_MEM_PHYS; \
+	x.mem_size = CFG_SYS_PCI##num##_MEM_SIZE; \
+	x.io_bus = CFG_SYS_PCI##num##_IO_BUS; \
+	x.io_phys = CFG_SYS_PCI##num##_IO_PHYS; \
+	x.io_size = CFG_SYS_PCI##num##_IO_SIZE; \
 	x.law = LAW_TRGT_IF_PCI_##num; \
 	x.pci_num = num; \
 }
 
 #define SET_STD_PCIE_INFO(x, num) \
 {			\
-	x.regs = CONFIG_SYS_PCIE##num##_ADDR;	\
-	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
-	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
-	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
-	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
-	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
-	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+	x.regs = CFG_SYS_PCIE##num##_ADDR;	\
+	x.mem_bus = CFG_SYS_PCIE##num##_MEM_BUS; \
+	x.mem_phys = CFG_SYS_PCIE##num##_MEM_PHYS; \
+	x.mem_size = CFG_SYS_PCIE##num##_MEM_SIZE; \
+	x.io_bus = CFG_SYS_PCIE##num##_IO_BUS; \
+	x.io_phys = CFG_SYS_PCIE##num##_IO_PHYS; \
+	x.io_size = CFG_SYS_PCIE##num##_IO_SIZE; \
 	x.law = LAW_TRGT_IF_PCIE_##num; \
 	x.pci_num = num; \
 }
 
 #define __FT_FSL_PCI_SETUP(blob, compat, num) \
-	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
+	ft_fsl_pci_setup(blob, compat, CFG_SYS_PCI##num##_ADDR)
 
 #define __FT_FSL_PCIE_SETUP(blob, compat, num) \
-	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
+	ft_fsl_pci_setup(blob, compat, CFG_SYS_PCIE##num##_ADDR)
 
 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)

diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index b1fd6bd..54ef4fb 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h

@@ -11,7 +11,7 @@
 	FSL_HW_PORTAL_SEC,
 #ifdef CONFIG_SYS_DPAA_FMAN
 	FSL_HW_PORTAL_FMAN1,
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	FSL_HW_PORTAL_FMAN2,
 #endif
 #endif

diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 3e70760..e8b2680 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h

@@ -9,11 +9,11 @@
 
 #ifdef CONFIG_NXP_ESBC
 #if defined(CONFIG_FSL_CORENET)
-#define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
+#define CFG_SYS_PBI_FLASH_BASE		0xc0000000
 #else
-#define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
+#define CFG_SYS_PBI_FLASH_BASE		0xce000000
 #endif
-#define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
+#define CFG_SYS_PBI_FLASH_WINDOW		0xcff80000
 
 #if defined(CONFIG_TARGET_T2080QDS) || \
 	defined(CONFIG_TARGET_T2080RDB) || \
@@ -21,18 +21,18 @@
 	defined(CONFIG_TARGET_T1042D4RDB) || \
 	defined(CONFIG_TARGET_T1042RDB_PI) || \
 	defined(CONFIG_ARCH_T1024)
-#undef CONFIG_SYS_INIT_L3_ADDR
-#define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
+#undef CFG_SYS_INIT_L3_ADDR
+#define CFG_SYS_INIT_L3_ADDR			0xbff00000
 #endif
 
 #if defined(CONFIG_RAMBOOT_PBL)
-#undef CONFIG_SYS_INIT_L3_ADDR
-#ifdef CONFIG_SYS_INIT_L3_VADDR
-#define CONFIG_SYS_INIT_L3_ADDR	\
-			(CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
+#undef CFG_SYS_INIT_L3_ADDR
+#ifdef CFG_SYS_INIT_L3_VADDR
+#define CFG_SYS_INIT_L3_ADDR	\
+			(CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
 					0xbff00000
 #else
-#define CONFIG_SYS_INIT_L3_ADDR		0xbff00000
+#define CFG_SYS_INIT_L3_ADDR		0xbff00000
 #endif
 #endif
 

diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 8e18202..19774f3 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h

@@ -871,11 +871,11 @@
 #define CFG_SYS_MPC83xx_ESDHC_ADDR \
 			(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
 
-#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
+#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
-#define CONFIG_SYS_TSEC1_OFFSET		0x24000
-#define CONFIG_SYS_MDIO1_OFFSET		0x24000
+#define CFG_SYS_TSEC1_OFFSET		0x24000
+#define CFG_SYS_MDIO1_OFFSET		0x24000
 
-#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 #endif				/* __IMMAP_83xx__ */

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index c9ced54..283fdf3 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h

@@ -2445,10 +2445,10 @@
 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0
 /* In SFPv3, OSPR register is now at offset 0x200.
  *  * So directly mapping sfp register map to this address */
-#define CONFIG_SYS_OSPR_OFFSET                  0x200
-#define CONFIG_SYS_SFP_OFFSET            (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#define CFG_SYS_OSPR_OFFSET                  0x200
+#define CFG_SYS_SFP_OFFSET            (0xE8000 + CFG_SYS_OSPR_OFFSET)
 #else
-#define CONFIG_SYS_SFP_OFFSET                   0xE8000
+#define CFG_SYS_SFP_OFFSET                   0xE8000
 #endif
 #define CFG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CFG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
@@ -2489,7 +2489,7 @@
 #define CFG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CFG_SYS_FSL_SEC_OFFSET		0x300000
 #define CFG_SYS_FSL_JR0_OFFSET		0x301000
-#define CONFIG_SYS_SEC_MON_OFFSET		0x314000
+#define CFG_SYS_SEC_MON_OFFSET		0x314000
 #define CFG_SYS_FSL_CORENET_PME_OFFSET	0x316000
 #define CFG_SYS_FSL_QMAN_OFFSET		0x318000
 #define CFG_SYS_FSL_BMAN_OFFSET		0x31a000
@@ -2542,13 +2542,13 @@
 #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
 #ifdef CONFIG_TSECV2
-#define CONFIG_SYS_TSEC1_OFFSET			0xB0000
+#define CFG_SYS_TSEC1_OFFSET			0xB0000
 #elif defined(CONFIG_TSECV2_1)
-#define CONFIG_SYS_TSEC1_OFFSET			0x10000
+#define CFG_SYS_TSEC1_OFFSET			0x10000
 #else
-#define CONFIG_SYS_TSEC1_OFFSET			0x24000
+#define CFG_SYS_TSEC1_OFFSET			0x24000
 #endif
-#define CONFIG_SYS_MDIO1_OFFSET			0x24000
+#define CFG_SYS_MDIO1_OFFSET			0x24000
 #define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_ARCH_C29X)
 #define CFG_SYS_FSL_SEC_OFFSET		0x80000
@@ -2559,8 +2559,8 @@
 #endif
 #define CFG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CFG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
-#define CONFIG_SYS_SEC_MON_OFFSET		0xE6000
-#define CONFIG_SYS_SFP_OFFSET			0xE7000
+#define CFG_SYS_SEC_MON_OFFSET		0xE6000
+#define CFG_SYS_SFP_OFFSET			0xE7000
 #define CFG_SYS_FSL_QMAN_OFFSET		0x88000
 #define CFG_SYS_FSL_BMAN_OFFSET		0x8a000
 #define CFG_SYS_FSL_FM1_OFFSET		0x100000
@@ -2574,9 +2574,9 @@
 #define CFG_SYS_FSL_SRIO_OFFSET		0xC0000
 
 #define CFG_SYS_FSL_CPC_ADDR	\
-	(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
+	(CFG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
 #define CFG_SYS_FSL_SCFG_ADDR	\
-	(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
+	(CFG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
 #define CFG_SYS_FSL_QMAN_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET)
 #define CFG_SYS_FSL_BMAN_ADDR \
@@ -2603,9 +2603,9 @@
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
 #define CFG_SYS_FSL_DDR3_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
-#define CONFIG_SYS_LBC_ADDR \
+#define CFG_SYS_LBC_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
-#define CONFIG_SYS_IFC_ADDR \
+#define CFG_SYS_IFC_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
 #define CFG_SYS_MPC85xx_ESPI_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
@@ -2659,30 +2659,22 @@
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET)
 #define CFG_SYS_FSL_SRIO_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET)
-#define CONFIG_SYS_PAMU_ADDR \
+#define CFG_SYS_PAMU_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
 
-#define CONFIG_SYS_PCI1_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
-#define CONFIG_SYS_PCI2_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET)
-#define CONFIG_SYS_PCIE1_ADDR \
+#define CFG_SYS_PCIE1_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
-#define CONFIG_SYS_PCIE2_ADDR \
+#define CFG_SYS_PCIE2_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
-#define CONFIG_SYS_PCIE3_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET)
-#define CONFIG_SYS_PCIE4_ADDR \
-	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET)
 
-#define CONFIG_SYS_SFP_ADDR  \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+#define CFG_SYS_SFP_ADDR  \
+	(CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET)
 
-#define CONFIG_SYS_SEC_MON_ADDR  \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+#define CFG_SYS_SEC_MON_ADDR  \
+	(CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET)
 
-#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 struct ccsr_cluster_l2 {
@@ -2743,7 +2735,7 @@
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
-#define	CONFIG_SYS_DCSR_DCFG_OFFSET	0X20000
+#define	CFG_SYS_DCSR_DCFG_OFFSET	0X20000
 struct dcsr_dcfg_regs {
 	u8  res_0[0x520];
 	u32 ecccr1;

diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 8ae8d8a..1df0822 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c

@@ -126,7 +126,7 @@
 
 #ifdef DEBUG
 	if (((u64)bootmap_base + bootm_size) >
-	    (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size))
+	    (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size))
 		puts("WARNING: bootm_low + bootm_size exceed total memory\n");
 	if ((bootmap_base + bootm_size) > get_effective_memsize())
 		puts("WARNING: bootm_low + bootm_size exceed eff. memory\n");

diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c
index d4a6057..b638ea7 100644
--- a/arch/powerpc/lib/spl.c
+++ b/arch/powerpc/lib/spl.c

@@ -23,7 +23,7 @@
 	image_entry_arg_t image_entry =
 		(image_entry_arg_t)spl_image->entry_point;
 
-	image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ,
+	image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CFG_SYS_BOOTMAPSZ,
 		    0, 0);
 }
 #endif /* CONFIG_SPL_OS_BOOT */

diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 96b3402..0ce77de 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig

@@ -47,6 +47,13 @@
 config HOST_64BIT
 	def_bool $(cc-define,_LP64)
 
+config HOST_HAS_SDL
+	def_bool $(success,sdl2-config --version)
+
+config SANDBOX_SDL
+	bool "Enable SDL2 support in sandbox"
+	default HOST_HAS_SDL
+
 config SANDBOX_CRASH_RESET
 	bool "Reset on crash"
 	help

diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 3e2c7f9..1284ef3 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk

@@ -8,9 +8,7 @@
 
 # Define this to avoid linking with SDL, which requires SDL libraries
 # This can solve 'sdl-config: Command not found' errors
-ifneq ($(NO_SDL),)
-PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL
-else
+ifeq ($(CONFIG_SANDBOX_SDL),y)
 PLATFORM_LIBS += $(shell $(SDL_CONFIG) --libs)
 PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags)
 endif

diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index a681e47..dd7978c 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c

@@ -448,7 +448,7 @@
 {
 	state = &main_state;
 
-	state->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	state->ram_size = CFG_SYS_SDRAM_SIZE;
 	state->ram_buf = os_malloc(state->ram_size);
 	if (!state->ram_buf) {
 		printf("Out of memory\n");

diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 2051207..88b57bf 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts

@@ -25,7 +25,7 @@
 	};
 
 	memory {
-		reg = <0 CONFIG_SYS_SDRAM_SIZE>;
+		reg = <0 CFG_SYS_SDRAM_SIZE>;
 	};
 
 	reserved-memory {

diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts
index 3eb0457..a9cd790 100644
--- a/arch/sandbox/dts/sandbox64.dts
+++ b/arch/sandbox/dts/sandbox64.dts

@@ -21,7 +21,7 @@
 	};
 
 	memory {
-		reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>;
+		reg = /bits/ 64 <0 CFG_SYS_SDRAM_SIZE>;
 	};
 
 	reserved-memory {

diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds
index 85ee547..d360eea 100644
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds

@@ -18,7 +18,7 @@
 
 MEMORY
 {
-	ram	: ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE
+	ram	: ORIGIN = CFG_SYS_SDRAM_BASE, LENGTH = CFG_SYS_SDRAM_SIZE
 }
 
 ENTRY(_start)

diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h
index 09a15da..03c196f 100644
--- a/arch/sh/include/asm/config.h
+++ b/arch/sh/include/asm/config.h

@@ -9,8 +9,7 @@
 #include <asm/processor.h>
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE		(get_board_sys_clk() / 4)
+#define CFG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
+#define CFG_SYS_TIMER_RATE		(get_board_sys_clk() / 4)
 
 #endif

diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
index 3fa093a..b31fa6d 100644
--- a/arch/sh/lib/board.c
+++ b/arch/sh/lib/board.c

@@ -11,8 +11,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 
 	return 0;
 }

diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c
index a5fad6c..b205e5e 100644
--- a/arch/sh/lib/bootm.c
+++ b/arch/sh/lib/bootm.c

@@ -88,7 +88,7 @@
 		set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200);
 		set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001);
 		set_sh_linux_param((unsigned long)param + INITRD_START,
-			GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE));
+			GET_INITRD_START(images->rd_start, CFG_SYS_SDRAM_BASE));
 		set_sh_linux_param((unsigned long)param + INITRD_SIZE,
 			images->rd_end - images->rd_start);
 	}

diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c
index c11101b..1eb97ac 100644
--- a/arch/x86/lib/physmem.c
+++ b/arch/x86/lib/physmem.c

@@ -144,7 +144,7 @@
 
 	/* Make sure the window is below U-Boot. */
 	assert(window + LARGE_PAGE_SIZE <
-	       gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_STACK_SIZE);
+	       gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE);
 	/* Map the page into the window and then memset the appropriate part. */
 	x86_phys_map_page(window, map_addr, 1);
 	memset((void *)(window + offset), c, size);

diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c
index a09e103..98d9753 100644
--- a/arch/xtensa/cpu/cpu.c
+++ b/arch/xtensa/cpu/cpu.c

@@ -45,7 +45,7 @@
 
 int arch_cpu_init(void)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 	return 0;
 }
 

diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h
index 3b27f93..920b5fd 100644
--- a/arch/xtensa/include/asm/addrspace.h
+++ b/arch/xtensa/include/asm/addrspace.h

@@ -22,8 +22,8 @@
  * The actual location of memory and IO is the board property.
  */
 
-#define IOADDR(x)		(CONFIG_SYS_IO_BASE + (x))
-#define MEMADDR(x)		(CONFIG_SYS_MEMORY_BASE + (x))
+#define IOADDR(x)		(CFG_SYS_IO_BASE + (x))
+#define MEMADDR(x)		(CFG_SYS_MEMORY_BASE + (x))
 #define PHYSADDR(x)		((x) - XCHAL_VECBASE_RESET_VADDR + \
 				 XCHAL_VECBASE_RESET_PADDR)
 

diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c
index c8dc186..36945bb 100644
--- a/board/BuR/brppt1/board.c
+++ b/board/BuR/brppt1/board.c

@@ -150,7 +150,7 @@
 #if defined(CONFIG_HW_WATCHDOG)
 	hw_watchdog_init();
 #endif
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c
index 2b08930..ea49c7a 100644
--- a/board/BuS/eb_cpu5282/eb_cpu5282.c
+++ b/board/BuS/eb_cpu5282/eb_cpu5282.c

@@ -26,7 +26,7 @@
 int checkboard (void)
 {
 	puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n");
-#if (CONFIG_TEXT_BASE ==  CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE ==  CFG_SYS_INT_FLASH_BASE)
 	puts("       Boot from Internal FLASH\n");
 #endif
 	return 0;
@@ -38,10 +38,10 @@
 
 	size = 0;
 	MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
-			MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
+			MCFSDRAMC_DCR_RC((15 * CFG_SYS_CLK / 1000000) >> 4);
 	asm (" nop");
-#ifdef CONFIG_SYS_SDRAM_BASE0
-	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)|
+#ifdef CFG_SYS_SDRAM_BASE0
+	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)|
 		MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
 		MCFSDRAMC_DACR_PS_32;
 	asm (" nop");
@@ -54,7 +54,7 @@
 	for (i = 0; i < 10; i++)
 		asm (" nop");
 
-	*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
+	*(unsigned long *)(CFG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
 	asm (" nop");
 	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
 	asm (" nop");
@@ -65,12 +65,12 @@
 	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
 	asm (" nop");
 	/* write SDRAM mode register */
-	*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
+	*(unsigned long *)(CFG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
 	asm (" nop");
-	size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024;
+	size += CFG_SYS_SDRAM_SIZE0 * 1024 * 1024;
 #endif
-#ifdef CONFIG_SYS_SDRAM_BASE1xx
-	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
+#ifdef CFG_SYS_SDRAM_BASE1xx
+	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SYS_SDRAM_BASE1)
 			| MCFSDRAMC_DACR_CASL (1)
 			| MCFSDRAMC_DACR_CBM (3)
 			| MCFSDRAMC_DACR_PS_16;
@@ -79,22 +79,22 @@
 
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
 
-	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
+	*(unsigned short *) (CFG_SYS_SDRAM_BASE1) = 0xA5A5;
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
 
 	for (i = 0; i < 2000; i++)
 		asm (" nop");
 
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
-	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
-	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
+	*(unsigned int *) (CFG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
+	size += CFG_SYS_SDRAM_SIZE1 * 1024 * 1024;
 #endif
 	gd->ram_size = size;
 
 	return 0;
 }
 
-#if defined(CONFIG_SYS_DRAM_TEST)
+#if defined(CFG_SYS_DRAM_TEST)
 int testdram(void)
 {
 	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;

diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index ff1c4cb..a52a032 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c

@@ -139,7 +139,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
index 695d6f6..9170913 100644
--- a/board/LaCie/net2big_v2/net2big_v2.c
+++ b/board/LaCie/net2big_v2/net2big_v2.c

@@ -88,7 +88,7 @@
 
 #if defined(CONFIG_MISC_INIT_R)
 
-#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
+#if defined(CONFIG_CMD_I2C) && defined(CFG_SYS_I2C_G762_ADDR)
 /*
  * Start I2C fan (GMT G762 controller)
  */
@@ -100,11 +100,11 @@
 
 	/* Enable open-loop and PWM modes */
 	data = 0x20;
-	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+	if (i2c_write(CFG_SYS_I2C_G762_ADDR,
 		      G762_REG_FAN_CMD1, 1, &data, 1) != 0)
 		goto err;
 	data = 0;
-	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+	if (i2c_write(CFG_SYS_I2C_G762_ADDR,
 		      G762_REG_SET_CNT, 1, &data, 1) != 0)
 		goto err;
 	/*
@@ -124,18 +124,18 @@
 	 * Start fan at low speed (2800 RPM):
 	 */
 	data = 0x08;
-	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+	if (i2c_write(CFG_SYS_I2C_G762_ADDR,
 		      G762_REG_SET_OUT, 1, &data, 1) != 0)
 		goto err;
 
 	return;
 err:
 	printf("Error: failed to start I2C fan @%02x\n",
-	       CONFIG_SYS_I2C_G762_ADDR);
+	       CFG_SYS_I2C_G762_ADDR);
 }
 #else
 static void init_fan(void) {}
-#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
+#endif /* CONFIG_CMD_I2C && CFG_SYS_I2C_G762_ADDR */
 
 #if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
 /*

diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
index 619cd6c..0c4f8e0 100644
--- a/board/Marvell/mvebu_alleycat-5/board.c
+++ b/board/Marvell/mvebu_alleycat-5/board.c

@@ -7,7 +7,7 @@
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index c6ecc32..45fe3e5 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c

@@ -80,7 +80,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c
index 77c7dd7..a8899af 100644
--- a/board/Marvell/mvebu_armada-8k/board.c
+++ b/board/Marvell/mvebu_armada-8k/board.c

@@ -150,7 +150,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/board/Marvell/octeontx/board.c b/board/Marvell/octeontx/board.c
index 059ebf8..2246535 100644
--- a/board/Marvell/octeontx/board.c
+++ b/board/Marvell/octeontx/board.c

@@ -63,7 +63,7 @@
 int dram_init(void)
 {
 	gd->ram_size = smc_dram_size(0);
-	gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size -= CFG_SYS_SDRAM_BASE;
 	mem_map_fill();
 
 	return 0;

diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c
index 63aa2d6..e7899f4 100644
--- a/board/Marvell/octeontx2/board.c
+++ b/board/Marvell/octeontx2/board.c

@@ -105,7 +105,7 @@
 int dram_init(void)
 {
 	gd->ram_size = smc_dram_size(0);
-	gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size -= CFG_SYS_SDRAM_BASE;
 
 	mem_map_fill();
 

diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
index 953e9db..3d20cfb 100644
--- a/board/Marvell/octeontx2_cn913x/board.c
+++ b/board/Marvell/octeontx2_cn913x/board.c

@@ -34,7 +34,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c
index 06f964f..a0bace7 100644
--- a/board/Synology/common/legacy.c
+++ b/board/Synology/common/legacy.c

@@ -56,8 +56,8 @@
 	t = (struct tag_mv_uboot *)&params->u;
 
 	t->uboot_version = VER_NUM | syno_board_id();
-	t->tclk = CONFIG_SYS_TCLK;
-	t->sysclk = CONFIG_SYS_TCLK * 2;
+	t->tclk = CFG_SYS_TCLK;
+	t->sysclk = CFG_SYS_TCLK * 2;
 	t->isusbhost = usb_port_modes();
 
 	for (i = 0; i < ETHADDR_MAX; i++) {

diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c
index 9e7f6ac..5c3f46e 100644
--- a/board/Synology/ds109/ds109.c
+++ b/board/Synology/ds109/ds109.c

@@ -101,17 +101,17 @@
 #include <ns16550.h>
 #define SOFTWARE_SHUTDOWN   0x31
 #define SOFTWARE_REBOOT     0x43
-#define CONFIG_SYS_NS16550_COM2		KW_UART1_BASE
+#define CFG_SYS_NS16550_COM2		KW_UART1_BASE
 void reset_misc(void)
 {
 	int b_d;
 	printf("Synology reset...");
 	udelay(50000);
 
-	b_d = ns16550_calc_divisor((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
-				   CONFIG_SYS_NS16550_CLK, 9600);
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM2, b_d);
-	ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
+	b_d = ns16550_calc_divisor((struct ns16550 *)CFG_SYS_NS16550_COM2,
+				   CFG_SYS_NS16550_CLK, 9600);
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM2, b_d);
+	ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM2,
 		     SOFTWARE_REBOOT);
 }
 

diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index 4959a7f..ad02cf1 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c

@@ -137,7 +137,7 @@
 
 int dram_init (void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 #ifdef CONFIG_CM_SPD_DETECT
 	{
 extern void dram_query(void);
@@ -160,12 +160,12 @@
 	 *
 	 */
 	sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
-	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+	gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
 				    REMAPPED_FLASH_SZ,
 				    0x01000000 << sdram_shift);
 	}
 #else
-	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+	gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
 				    REMAPPED_FLASH_SZ,
 				    PHYS_SDRAM_1_SIZE);
 #endif /* CM_SPD_DETECT */

diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c
index d220b87..9db5135 100644
--- a/board/armltd/integrator/timer.c
+++ b/board/armltd/integrator/timer.c

@@ -41,10 +41,10 @@
 static unsigned long long div_timer = 1; /* Divisor to convert timer reading
 					  * change to U-Boot ticks
 					  */
-/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
+/* CONFIG_SYS_HZ = CFG_SYS_HZ_CLOCK/(div_clock * div_timer) */
 static ulong timestamp;		/* U-Boot ticks since startup */
 
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
+#define READ_TIMER (*(volatile ulong *)(CFG_SYS_TIMERBASE+4))
 
 /* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
  *  - unless otherwise stated
@@ -55,7 +55,7 @@
 int timer_init (void)
 {
 	/* Load timer with initial value */
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
+	*(volatile ulong *)(CFG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
 #ifdef CONFIG_ARCH_CINTEGRATOR
 	/* Set timer to be
 	 *	enabled		 1
@@ -66,7 +66,7 @@
 	 *	32 bit		 1
 	 *	wrapping	 0
 	 */
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
+	*(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x000000C2;
 #else
 	/* Set timer to be
 	 *	enabled		 1
@@ -75,7 +75,7 @@
 	 *	divider 256	10
 	 *	XX		00
 	 */
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
+	*(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x00000088;
 #endif
 
 	/* init the timestamp */
@@ -85,7 +85,7 @@
 	/* start "advancing" time stamp from 0 */
 	timestamp = 0L;
 
-	div_timer = CONFIG_SYS_HZ_CLOCK;
+	div_timer = CFG_SYS_HZ_CLOCK;
 	do_div(div_timer, CONFIG_SYS_HZ);
 	do_div(div_timer, div_clock);
 
@@ -156,7 +156,7 @@
  */
 ulong get_tbclk(void)
 {
-	unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
+	unsigned long long tmp = CFG_SYS_HZ_CLOCK;
 
 	do_div(tmp, div_clock);
 

diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c
index 1c83019..763131c 100644
--- a/board/armltd/vexpress/vexpress_common.c
+++ b/board/armltd/vexpress/vexpress_common.c

@@ -73,7 +73,7 @@
 int dram_init(void)
 {
 	gd->ram_size =
-		get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
+		get_ram_size((long *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
 

diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index af326dc..4ca544f 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c

@@ -108,7 +108,7 @@
 #define JUNO_FLASH_SEC_SIZE	(256 * 1024)
 static phys_addr_t find_dtb_in_nor_flash(const char *partname)
 {
-	phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
+	phys_addr_t sector = CFG_SYS_FLASH_BASE;
 	int i;
 
 	for (i = 0;
@@ -140,7 +140,7 @@
 			imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
 			reg = readl(imginfo + 0x54);
 
-			return CONFIG_SYS_FLASH_BASE +
+			return CFG_SYS_FLASH_BASE +
 			       reg * JUNO_FLASH_SEC_SIZE;
 		}
 	}

diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c
index 3e2f79a..43563c4 100644
--- a/board/astro/mcf5373l/mcf5373l.c
+++ b/board/astro/mcf5373l/mcf5373l.c

@@ -39,12 +39,12 @@
 	 * GPIO configuration for bus should be set correctly from reset,
 	 * so we do not care! First, set up address space: at this point,
 	 * we should be running from internal SRAM;
-	 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
+	 * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM,
 	 * and do not care where it is
 	 */
-	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
+	__raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
 			&sdp->cs0);
-	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
+	__raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
 			&sdp->cs1);
 	/*
 	 * I am not sure from the data sheet, but it seems burst length
@@ -72,7 +72,7 @@
 	 */
 	__raw_writel(0x71462C00, &sdp->ctrl);
 	/* Dummy write to start SDRAM */
-	writel(0, CONFIG_SYS_SDRAM_BASE);
+	writel(0, CFG_SYS_SDRAM_BASE);
 #endif
 
 	/*
@@ -82,8 +82,8 @@
 	 * (Do not rely on the SDCS register(s) being set to 0x00000000
 	 * during reset as stated in the data sheet.)
 	 */
-	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-				0x80000000 - CONFIG_SYS_SDRAM_BASE);
+	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+				0x80000000 - CFG_SYS_SDRAM_BASE);
 
 	return 0;
 }

diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index a9ea9b5..b8e02f4 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c

@@ -56,10 +56,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 }
 #endif
@@ -81,7 +81,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	at91sam9260ek_nand_hw_init();
@@ -92,8 +92,8 @@
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size(
-		(void *)CONFIG_SYS_SDRAM_BASE,
-		CONFIG_SYS_SDRAM_SIZE);
+		(void *)CFG_SYS_SDRAM_BASE,
+		CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 0c53325..eab3a13 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c

@@ -78,10 +78,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
 	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
@@ -156,7 +156,7 @@
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 #endif
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	at91sam9261ek_nand_hw_init();
@@ -176,8 +176,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-		CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+		CFG_SYS_SDRAM_SIZE);
 
 	return 0;
 }

diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 3e232aa..15f20b6 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c

@@ -69,10 +69,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
@@ -95,7 +95,7 @@
 	/* arch number of AT91SAM9263EK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	at91sam9263ek_nand_hw_init();
@@ -108,8 +108,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-		CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+		CFG_SYS_SDRAM_SIZE);
 
 	return 0;
 }

diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 3af7097..f53c1cf 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

@@ -63,10 +63,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
@@ -168,7 +168,7 @@
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
 
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	at91sam9m10g45ek_nand_hw_init();
@@ -181,8 +181,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 5468519..a3e294c 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c

@@ -99,7 +99,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_NAND_ATMEL
 	at91sam9n12ek_nand_hw_init();
@@ -114,8 +114,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-					CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+					CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index f05ee322..11725f7 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c

@@ -64,10 +64,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOD);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_set_A_periph(AT91_PIN_PB4, 0);		/* NANDOE */
 	at91_set_A_periph(AT91_PIN_PB5, 0);		/* NANDWE */
@@ -93,7 +93,7 @@
 	/* arch number of AT91SAM9RLEK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	at91sam9rlek_nand_hw_init();
@@ -104,7 +104,7 @@
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size(
-		(void *)CONFIG_SYS_SDRAM_BASE,
-		CONFIG_SYS_SDRAM_SIZE);
+		(void *)CFG_SYS_SDRAM_BASE,
+		CFG_SYS_SDRAM_SIZE);
 	return 0;
 }

diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index b5af35b..ab666b6 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c

@@ -65,9 +65,9 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOCD);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
@@ -115,7 +115,7 @@
 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
 
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	at91sam9x5ek_nand_hw_init();
@@ -129,8 +129,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
-					CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
+					CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c
index 7035fab..a3e35f3 100644
--- a/board/atmel/sam9x60ek/sam9x60ek.c
+++ b/board/atmel/sam9x60ek/sam9x60ek.c

@@ -36,9 +36,9 @@
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0);	/* NAND ALE */
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0);	/* NAND CLE */
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
@@ -120,7 +120,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	sam9x60ek_nand_hw_init();
@@ -130,7 +130,7 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }

diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
index 6524867..6e41017 100644
--- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c

@@ -65,7 +65,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	rgb_leds_init();
 
@@ -84,8 +84,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c
index 0207770..fabe492 100644
--- a/board/atmel/sama5d2_icp/sama5d2_icp.c
+++ b/board/atmel/sama5d2_icp/sama5d2_icp.c

@@ -54,7 +54,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	rgb_leds_init();
 
@@ -63,8 +63,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
index 16e9183..854715e 100644
--- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
+++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c

@@ -115,7 +115,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	rgb_leds_init();
 
@@ -130,8 +130,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index a778f26..ce73a80 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c

@@ -94,7 +94,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_NAND_ATMEL
 	sama5d3_xplained_nand_hw_init();
@@ -110,8 +110,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 
 	return 0;
 }

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index 008f1db..660a6b9 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c

@@ -147,7 +147,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_NAND_ATMEL
 	sama5d3xek_nand_hw_init();
@@ -166,8 +166,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 4058594..780aba1 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c

@@ -121,7 +121,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_NAND_ATMEL
 	sama5d4_xplained_nand_hw_init();
@@ -135,8 +135,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index ef5a8a0..2226906 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c

@@ -107,7 +107,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_NAND_ATMEL
 	sama5d4ek_nand_hw_init();
@@ -121,8 +121,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c
index 7d83e76..295fd07 100644
--- a/board/atmel/sama7g5ek/sama7g5ek.c
+++ b/board/atmel/sama7g5ek/sama7g5ek.c

@@ -67,7 +67,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	board_leds_init();
 
@@ -76,7 +76,7 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }

diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
index f547ce3..9b42299 100644
--- a/board/bluewater/gurnard/gurnard.c
+++ b/board/bluewater/gurnard/gurnard.c

@@ -100,16 +100,16 @@
 	       AT91_SMC_MODE_TDF_CYCLE(3),
 	       &smc->cs[3].mode);
 
-	ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+	ret = gpio_request(CFG_SYS_NAND_READY_PIN, "nand_rdy");
 	if (ret)
 		return ret;
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+	ret = gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand_ce");
 	if (ret)
 		return ret;
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	return 0;
 }
@@ -307,7 +307,7 @@
 	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
 
 	/* Address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	ret = gurnard_nand_hw_init();
@@ -407,8 +407,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index bdf8d06..c31e2c8 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c

@@ -182,7 +182,7 @@
 	hw_watchdog_init();
 #endif
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_MTD_RAW_NAND
 	gpmc_init();

diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index a7a9775..e3a9c00 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c

@@ -449,7 +449,7 @@
 	if (read_eeprom() < 0)
 		puts("EEPROM Content Invalid.\n");
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
 	gpmc_init();
 #endif

diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
index 6064eb4..e91fa40 100644
--- a/board/broadcom/bcm_ep/board.c
+++ b/board/broadcom/bcm_ep/board.c

@@ -26,7 +26,7 @@
 	 * Address of boot parameters passed to kernel
 	 * Use default offset 0x100
 	 */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }
@@ -36,14 +36,14 @@
  */
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	return 0;

diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index ade7f9d..f38f556 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c

@@ -58,8 +58,8 @@
 	 * else non-zero (hang).
 	 */
 
-#ifdef CONFIG_SYS_FPGAREG_FREQ
-	return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
+#ifdef CFG_SYS_FPGAREG_FREQ
+	return (*(volatile unsigned long *)CFG_SYS_FPGAREG_FREQ);
 #else
 	/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
 	return 50000000;
@@ -90,7 +90,7 @@
 	if (s == 0) {
 		unsigned int x;
 		char s[] = __stringify(CONFIG_ETHBASE);
-		x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
+		x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW)
 			& FPGAREG_MAC_MASK;
 		sprintf(&s[15], "%02x", x);
 		env_set("ethaddr", s);
@@ -106,9 +106,9 @@
 
 static struct ethoc_eth_pdata ethoc_pdata = {
 	.eth_pdata = {
-		.iobase = CONFIG_SYS_ETHOC_BASE,
+		.iobase = CFG_SYS_ETHOC_BASE,
 	},
-	.packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
+	.packet_base = CFG_SYS_ETHOC_BUFFER_ADDR,
 };
 
 U_BOOT_DRVINFO(ethoc) = {

diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c
index c0a5c51..3d31776 100644
--- a/board/calao/usb_a9263/usb_a9263.c
+++ b/board/calao/usb_a9263/usb_a9263.c

@@ -54,12 +54,12 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
 
 	/* Configure RDY/BSY */
-	gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_request(CFG_SYS_NAND_READY_PIN, "NAND ready/busy");
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "NAND enable");
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
@@ -95,7 +95,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	usb_a9263_nand_hw_init();
@@ -111,8 +111,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c
index 1a039c5..37340fe 100644
--- a/board/cavium/thunderx/atf.c
+++ b/board/cavium/thunderx/atf.c

@@ -187,7 +187,7 @@
 	int ret;
 	char *ptype;
 
-	struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE;
+	struct storage_partition *part = (void *)CFG_SYS_LOWMEM_BASE;
 
 	pcount = atf_get_pcount();
 

diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index a8f8c78..ab20825 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c

@@ -20,7 +20,7 @@
 #include <dm/platform_data/serial_pl01x.h>
 
 static const struct pl01x_serial_plat serial0 = {
-	.base = CONFIG_SYS_SERIAL0,
+	.base = CFG_SYS_SERIAL0,
 	.type = TYPE_PL011,
 	.clock = 0,
 	.skip_init = true,
@@ -32,7 +32,7 @@
 };
 
 static const struct pl01x_serial_plat serial1 = {
-	.base = CONFIG_SYS_SERIAL1,
+	.base = CFG_SYS_SERIAL1,
 	.type = TYPE_PL011,
 	.clock = 0,
 	.skip_init = true,

diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c
index 3e24188..69a9df9 100644
--- a/board/cobra5272/cobra5272.c
+++ b/board/cobra5272/cobra5272.c

@@ -28,7 +28,7 @@
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *) 0) = 0;
 
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
 
 	return 0;
 };

diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
index 5d15ed4..8416af1 100644
--- a/board/cobra5272/flash.c
+++ b/board/cobra5272/flash.c

@@ -12,7 +12,7 @@
 #include <uuid.h>
 #include <linux/delay.h>
 
-#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+#define PHYS_FLASH_1 CFG_SYS_FLASH_BASE
 #define FLASH_BANK_SIZE 0x200000
 
 flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
@@ -102,8 +102,8 @@
 	}
 
 	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_FLASH_BASE,
-		      CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
+		      CFG_SYS_FLASH_BASE,
+		      CFG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
 
 	return size;
 }
@@ -117,8 +117,8 @@
 #define CMD_PROGRAM		0x00A0
 #define CMD_UNLOCK_BYPASS	0x0020
 
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x000002AA<<1)))
 
 #define BIT_ERASE_DONE		0x0080
 #define BIT_RDY_MASK		0x0080

diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c
index bcfe1bf..5df378a 100644
--- a/board/compulab/cm_t43/cm_t43.c
+++ b/board/compulab/cm_t43/cm_t43.c

@@ -45,7 +45,7 @@
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	gpmc_init();
 	set_i2c_pin_mux();
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c
index e67bf81..a6223a4 100644
--- a/board/compulab/cm_t43/spl.c
+++ b/board/compulab/cm_t43/spl.c

@@ -119,7 +119,7 @@
 	unsigned long ram_size;
 
 	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
-	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000);
 	if (ram_size == 0x80000000 ||
 	    ram_size == 0x40000000 ||
 	    ram_size == 0x20000000)
@@ -127,7 +127,7 @@
 
 	ddr3_emif_regs.sdram_config = 0x638453B2;
 	config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
-	ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000);
 	if (ram_size == 0x08000000)
 		return;
 

diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/board/cortina/presidio-asic/lowlevel_init.S
index cbf8134..8d8842e 100644
--- a/board/cortina/presidio-asic/lowlevel_init.S
+++ b/board/cortina/presidio-asic/lowlevel_init.S

@@ -27,7 +27,7 @@
 
 #if defined(CONFIG_SOC_CA8277B)
 	/* Enable CPU Timer */
-	ldr x0, =CONFIG_SYS_TIMER_BASE
+	ldr x0, =CFG_SYS_TIMER_BASE
 	mov x1, #1
 	str w1, [x0]
 #endif

diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c
index f344622..aae0a5d 100644
--- a/board/cortina/presidio-asic/presidio.c
+++ b/board/cortina/presidio-asic/presidio.c

@@ -84,7 +84,7 @@
 	unsigned int reg_data, jtag_id;
 
 	/* Enable timer */
-	writel(1, CONFIG_SYS_TIMER_BASE);
+	writel(1, CFG_SYS_TIMER_BASE);
 
 	/* Enable snoop in CCI400 slave port#4 */
 	writel(3, 0xF5595000);

diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c
index c20e871..e95e04a 100644
--- a/board/cssi/MCR3000/MCR3000.c
+++ b/board/cssi/MCR3000/MCR3000.c

@@ -114,7 +114,7 @@
 	out_be32(&memctl->memc_mcr, 0x80002038);
 	udelay(200);
 
-	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
 				    SDRAM_MAX_SIZE);
 
 	return 0;

diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 2436aab..e3a0f26 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c

@@ -371,20 +371,20 @@
 	/* Set polarity to non-inverted */
 	buf[0] = 0x0;
 	buf[1] = 0x0;
-	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
+	ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
 	if (ret) {
 		printf("\nExpander @ 0x%02x write FAILED!!!\n",
-				CONFIG_SYS_I2C_EXPANDER_ADDR);
+				CFG_SYS_I2C_EXPANDER_ADDR);
 		return ret;
 	}
 
 	/* Configure P07-P05 as outputs */
 	buf[0] = 0x1f;
 	buf[1] = 0xff;
-	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
+	ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
 	if (ret) {
 		printf("\nExpander @ 0x%02x write FAILED!!!\n",
-				CONFIG_SYS_I2C_EXPANDER_ADDR);
+				CFG_SYS_I2C_EXPANDER_ADDR);
 	}
 
 	/* For Ethernet RMII selection
@@ -392,16 +392,16 @@
 	 * P06(SelB)=1
 	 * P05(SelC)=1
 	 */
-	if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+	if (i2c_read(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
 		printf("\nExpander @ 0x%02x read FAILED!!!\n",
-				CONFIG_SYS_I2C_EXPANDER_ADDR);
+				CFG_SYS_I2C_EXPANDER_ADDR);
 	}
 
 	buf[0] &= 0x1f;
 	buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
-	if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+	if (i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
 		printf("\nExpander @ 0x%02x write FAILED!!!\n",
-				CONFIG_SYS_I2C_EXPANDER_ADDR);
+				CFG_SYS_I2C_EXPANDER_ADDR);
 	}
 
 	/* Set the output as high */

diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
index 72cf46c..2b03e48 100644
--- a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
+++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c

@@ -29,13 +29,13 @@
 int
 board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x2000;
 	return 0;
 }
 
 int
 dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_64M);
 	return 0;
 }

diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index 1054837..648d77f 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c

@@ -286,7 +286,7 @@
 	hw_watchdog_init();
 #endif
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	return 0;
 }
 

diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c
index f0f9e26..886fef6 100644
--- a/board/eets/pdu001/mux.c
+++ b/board/eets/pdu001/mux.c

@@ -92,22 +92,22 @@
 void enable_uart_pin_mux(u32 addr)
 {
 	switch (addr) {
-	case CONFIG_SYS_NS16550_COM1:
+	case CFG_SYS_NS16550_COM1:
 		enable_uart0_pin_mux();
 		break;
-	case CONFIG_SYS_NS16550_COM2:
+	case CFG_SYS_NS16550_COM2:
 		enable_uart1_pin_mux();
 		break;
-	case CONFIG_SYS_NS16550_COM3:
+	case CFG_SYS_NS16550_COM3:
 		enable_uart2_pin_mux();
 		break;
-	case CONFIG_SYS_NS16550_COM4:
+	case CFG_SYS_NS16550_COM4:
 		enable_uart3_pin_mux();
 		break;
-	case CONFIG_SYS_NS16550_COM5:
+	case CFG_SYS_NS16550_COM5:
 		enable_uart4_pin_mux();
 		break;
-	case CONFIG_SYS_NS16550_COM6:
+	case CFG_SYS_NS16550_COM6:
 		enable_uart5_pin_mux();
 		break;
 	}

diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c
index 559fdd2..ceb0d2c 100644
--- a/board/egnite/ethernut5/ethernut5.c
+++ b/board/egnite/ethernut5/ethernut5.c

@@ -85,8 +85,8 @@
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size(
-			(void *)CONFIG_SYS_SDRAM_BASE,
-			CONFIG_SYS_SDRAM_SIZE);
+			(void *)CFG_SYS_SDRAM_BASE,
+			CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 
@@ -117,11 +117,11 @@
 		AT91_SMC_MODE_TDF_CYCLE(2),
 		&smc->cs[3].mode);
 
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 	/* Ready pin is optional. */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_pio_input(CFG_SYS_NAND_READY_PIN, 1);
 #endif
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
@@ -135,7 +135,7 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Set adress of boot parameters. */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	/* Initialize UARTs and power management. */
 	ethernut5_power_init();
 #ifdef CONFIG_CMD_NAND
@@ -193,6 +193,6 @@
 
 int board_mmc_getcd(struct mmc *mmc)
 {
-	return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
+	return !at91_get_pio_value(CFG_SYS_MMC_CD_PIN);
 }
 #endif

diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c
index 16237e2..3df3e41 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c

@@ -126,7 +126,7 @@
 {
 	*err = 0;
 	/* QEMU loads a generated DTB for us at the start of RAM. */
-	return (void *)CONFIG_SYS_SDRAM_BASE;
+	return (void *)CFG_SYS_SDRAM_BASE;
 }
 
 void enable_caches(void)

diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c
index 99edaa3..a39bcb4 100644
--- a/board/emulation/qemu-ppce500/qemu-ppce500.c
+++ b/board/emulation/qemu-ppce500/qemu-ppce500.c

@@ -41,7 +41,7 @@
 	if (gd->flags & GD_FLG_RELOC)
 		return (void *)gd->fdt_blob;
 	else
-		return (void *)CONFIG_SYS_TMPVIRT;
+		return (void *)CFG_SYS_TMPVIRT;
 }
 
 static uint64_t get_fdt_phys(void)
@@ -163,7 +163,7 @@
 	 * U-Boot is relocated to RAM already, let's delete the temporary FDT
 	 * virtual-physical mapping that was used in the pre-relocation phase.
 	 */
-	disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1));
+	disable_tlb(find_tlb_idx((void *)CFG_SYS_TMPVIRT, 1));
 
 	/*
 	 * Detect the presence of the platform bus node, and
@@ -248,7 +248,7 @@
 	init_used_tlb_cams();
 
 	/* Create a dynamic AS=0 CCSRBAR mapping */
-	assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	assert(!tlb_map_range(CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 			      1024 * 1024, TLB_MAP_IO));
 
 	/* Create a RAM map that spans all accessible RAM */
@@ -343,7 +343,7 @@
 	return get_fdt_virt();
 }
 
-/* See CONFIG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */
+/* See CFG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */
 int get_serial_clock(void)
 {
 	return get_bus_freq(0);

diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index a3eee63..21f4ba9 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c

@@ -84,10 +84,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif /* CONFIG_CMD_NAND */
 
@@ -240,7 +240,7 @@
 	if (str && (strcmp(str, "4") == 0)) {
 		writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
 			AT91SAM9_PMC_MDIV_4, &pmc->mckr);
-		at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+		at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
 		serial_setbrg();
 		/* Notify the user that the clock is not default */
 		printf("Setting master clock to %s MHz\n",
@@ -264,7 +264,7 @@
 	meesc_ethercat_hw_init();
 
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	meesc_nand_hw_init();

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 377c6aa..cc13718 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile

@@ -61,7 +61,9 @@
 obj-$(CONFIG_TARGET_P5040DS)		+= ics307_clk.o
 obj-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
 obj-$(CONFIG_ZM7300)		+= zm7300.o
+ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
 obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
+endif
 obj-$(CONFIG_DM_PMIC_PFUZE100)	+= pfuze.o
 obj-$(CONFIG_POWER_MC34VR500)	+= mc34vr500.o
 ifneq (,$(filter $(SOC), imx8ulp imx9))

diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index f5bed6c..46ffd81 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c

@@ -61,7 +61,7 @@
 
 	/* get the address of ddr date from SPARECR3 */
 	src = (u64 *)in_le32(&scfg->sparecr[2]);
-	dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+	dst = (u64 *)CFG_SYS_SDRAM_BASE;
 
 	for (i = 0; i < DDR_BUFF_LEN / 8; i++)
 		*dst++ = *src++;

diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index d31ad02..9ca350e 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c

@@ -43,7 +43,7 @@
 int fsl_check_boot_mode_secure(void)
 {
 	uint32_t val;
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
 
 	val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;

diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 3424d49..285ed9a 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c

@@ -85,7 +85,7 @@
 {
 	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
-	u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
+	u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE);
 	u32 flash_addr, addr;
 	int found = 0;
 	int i = 0;
@@ -160,7 +160,7 @@
 	 */
 #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
 	sg_tbl = (struct fsl_secboot_sg_table *)
-		 (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+		 (((u32)hdr->psgtable & ~(CFG_SYS_PBI_FLASH_BASE)) +
 		  flash_base_addr);
 #else
 	sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
@@ -170,7 +170,7 @@
 	/* IE Key Table is the first entry in the SG Table */
 #if defined(CONFIG_MPC85xx)
 	*ie_addr = (uintptr_t)((sg_tbl->src_addr &
-			~(CONFIG_SYS_PBI_FLASH_BASE)) +
+			~(CFG_SYS_PBI_FLASH_BASE)) +
 			flash_base_addr);
 #else
 	*ie_addr = (uintptr_t)sg_tbl->src_addr;
@@ -203,7 +203,7 @@
 /* This function returns ospr's key_revoc values.*/
 static u32 get_key_revoc(void)
 {
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 	return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
 		OSPR_KEY_REVOC_SHIFT;
 }
@@ -342,7 +342,7 @@
  */
 static void fsl_secboot_header_verification_failure(void)
 {
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 
 	/* 29th bit of OSPR is ITS */
 	u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
@@ -367,7 +367,7 @@
  */
 static void fsl_secboot_image_verification_failure(void)
 {
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 
 	u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
 
@@ -871,7 +871,7 @@
 int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
 			uintptr_t *img_addr_ptr)
 {
-	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
 	ulong hash[SHA256_BYTES/sizeof(ulong)];
 	char hash_str[NUM_HEX_CHARS + 1];
 	struct fsl_secboot_img_priv *img;

diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index 71922aa..d3323b9 100644
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c

@@ -50,7 +50,7 @@
 
 	/* get the address of ddr date from SPARECR3 */
 	src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
-	dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
+	dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
 
 	for (i = 0; i < DDR_BUFF_LEN / 8; i++)
 		*dst-- = *src--;

diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index 603384a..1a1e934 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c

@@ -11,12 +11,12 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
 #endif
 #ifdef PIXIS_BASE_PHYS
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
@@ -24,12 +24,12 @@
 #ifdef CPLD_BASE_PHYS
 	SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
 };
 

diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index c0ab1a5..1a2d9cb 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c

@@ -11,20 +11,20 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 #ifdef CPLD_BASE
@@ -41,25 +41,25 @@
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 
 #if !defined(CONFIG_NXP_ESBC)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
 #else
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
-	 * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
+	 * the physical address of the SRAM is at CFG_SYS_INIT_L3_ADDR,
 	 * and virtual address is CONFIG_SYS_MONITOR_BASE
 	 */
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000,
-			CONFIG_SYS_INIT_L3_ADDR & 0xfff00000,
+			CFG_SYS_INIT_L3_ADDR & 0xfff00000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
 #endif
@@ -69,8 +69,8 @@
 	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
 	 * space is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
-			CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+			CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
 #else
@@ -80,68 +80,68 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+		      CFG_SYS_PCIE1_MEM_PHYS + 0x40000000,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+		      CFG_SYS_PCIE1_MEM_PHYS + 0x50000000,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x00100000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x00100000,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_1M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 11, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x00100000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x00100000,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_1M, 1),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_4M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 16, BOOKE_PAGESZ_1M, 1),
 #endif
@@ -150,8 +150,8 @@
 	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
 	 * fetching ucode and ENV from master
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
-		CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		0, 17, BOOKE_PAGESZ_1M, 1),
 #endif

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 2bb838c..da2c1de 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c

@@ -29,15 +29,15 @@
 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
 #endif
 
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#ifdef CFG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
 #if !CONFIG_IS_ENABLED(DM_I2C)
-	return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+	return i2c_reg_read(CFG_SYS_I2C_FPGA_ADDR, reg);
 #else
 	struct udevice *dev;
 
-	if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+	if (i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev))
 		return 0xff;
 
 	return dm_i2c_reg_read(dev, reg);
@@ -48,11 +48,11 @@
 {
 	u8 val = value;
 #if !CONFIG_IS_ENABLED(DM_I2C)
-	i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+	i2c_reg_write(CFG_SYS_I2C_FPGA_ADDR, reg, val);
 #else
 	struct udevice *dev;
 
-	if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+	if (!i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev))
 		dm_i2c_reg_write(dev, reg, val);
 #endif
 

diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index af76327..784046a 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h

@@ -100,12 +100,12 @@
 char *qixis_read_time(char *result);
 char *qixis_read_tag(char *buf);
 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#ifdef CFG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg);
 void qixis_write_i2c(unsigned int reg, u8 value);
 #endif
 
-#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CFG_SYS_I2C_FPGA_ADDR)
 #define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
 #define QIXIS_WRITE(reg, value) \
 	qixis_write_i2c(offsetof(struct qixis, reg), value)
@@ -114,7 +114,7 @@
 #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
 #endif
 
-#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#ifdef CFG_SYS_I2C_FPGA_ADDR
 #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
 #define QIXIS_WRITE_I2C(reg, value) \
 			qixis_write_i2c(offsetof(struct qixis, reg), value)

diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index bc37c55..f2b8750 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c

@@ -102,7 +102,7 @@
 		else
 			gd->ram_size = SYS_SDRAM_SIZE_512;
 #else
-		gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+		gd->ram_size = CFG_SYS_SDRAM_SIZE;
 #endif
 	}
 	return 0;
@@ -139,7 +139,7 @@
 		gd->ram_size = SYS_SDRAM_SIZE_512;
 	}
 #else
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 #endif
 	mmdc_init(&mparam);
 

diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 3f70fbc..194b5d2 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c

@@ -66,7 +66,7 @@
 {
 	gd->ram_size = tfa_get_dram_size();
 	if (!gd->ram_size)
-		gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+		gd->ram_size = CFG_SYS_SDRAM_SIZE;
 
 	return 0;
 }
@@ -90,7 +90,7 @@
 	};
 
 	mmdc_init(&mparam);
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();
@@ -117,7 +117,7 @@
 	struct udevice *dev;
 	int ret;
 
-	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
+	ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR,
 				      1, &dev);
 	if (ret) {
 		printf("%s: Cannot find udev for a bus %d\n", __func__,
@@ -128,7 +128,7 @@
 #else
 	i2c_set_bus_num(bus_num);
 
-	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+	i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
 #endif
 
 	return 0;

diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 456609d..62c935e 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c

@@ -113,7 +113,7 @@
 {
 	gd->ram_size = tfa_get_dram_size();
 	if (!gd->ram_size)
-		gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+		gd->ram_size = CFG_SYS_SDRAM_SIZE;
 
 	return 0;
 }
@@ -140,7 +140,7 @@
 	mmdc_init(&mparam);
 #endif
 
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();

diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 66fe151..4e70acc 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c

@@ -192,7 +192,7 @@
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	return 0;

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d0674d0..d5cb731 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c

@@ -196,7 +196,7 @@
 	porsr1 = in_be32(&gur->porsr1);
 	pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
 		 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
-	out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+	out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 		 pinctl);
 #endif
 

diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index 4325439..d144f25 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c

@@ -47,7 +47,7 @@
 	if (is_warm_boot()) {
 		out_be32(&ddr->sdram_cfg_2,
 			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
-		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
 		out_be32(&ddr->init_ext_addr, (1 << 31));
 
 		/* DRAM VRef will not be trained */

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 33027ad..4f58343 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c

@@ -98,7 +98,7 @@
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 static void cpld_show(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
 	       in_8(&cpld_data->cpld_ver) & VERSION_MASK,
@@ -162,7 +162,7 @@
 	if (is_warm_boot()) {
 		out_be32(&ddr->sdram_cfg_2,
 			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
-		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
 		out_be32(&ddr->init_ext_addr, (1 << 31));
 
 		/* DRAM VRef will not be trained */
@@ -248,7 +248,7 @@
 static void convert_serdes_mux(int type, int need_reset)
 {
 	char current_serdes;
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	current_serdes = cpld_data->serdes_mux;
 
@@ -322,7 +322,7 @@
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 int config_board_mux(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	int conflict_flag;
 
 	conflict_flag = 0;
@@ -610,7 +610,7 @@
 	&& !defined(CONFIG_SPL_BUILD)
 static void convert_flash_bank(char bank)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	printf("Now switch to boot from flash bank %d.\n", bank);
 	cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
@@ -644,7 +644,7 @@
 static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 			  char *const argv[])
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	if (argc > 2)
 		return CMD_RET_USAGE;
@@ -671,7 +671,7 @@
 static void print_serdes_mux(void)
 {
 	char current_serdes;
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	current_serdes = cpld_data->serdes_mux;
 

diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index 6783ebe..645c56c 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c

@@ -427,7 +427,7 @@
 		break;
 	}
 
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
 		idx = i - FM1_DTSEC1;
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index b02f649..841d8b5 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c

@@ -57,55 +57,55 @@
 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR,
-		CONFIG_SYS_NOR0_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR,
-		CONFIG_SYS_NOR1_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR1_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 	},
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
-		CONFIG_SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_AMASK,
+		CFG_SYS_FPGA_CSOR,
 		{
-			CONFIG_SYS_FPGA_FTIM0,
-			CONFIG_SYS_FPGA_FTIM1,
-			CONFIG_SYS_FPGA_FTIM2,
-			CONFIG_SYS_FPGA_FTIM3
+			CFG_SYS_FPGA_FTIM0,
+			CFG_SYS_FPGA_FTIM1,
+			CFG_SYS_FPGA_FTIM2,
+			CFG_SYS_FPGA_FTIM3
 		},
 	}
 };
@@ -113,54 +113,54 @@
 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR,
-		CONFIG_SYS_NOR0_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR,
-		CONFIG_SYS_NOR1_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR1_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
-		CONFIG_SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_AMASK,
+		CFG_SYS_FPGA_CSOR,
 		{
-			CONFIG_SYS_FPGA_FTIM0,
-			CONFIG_SYS_FPGA_FTIM1,
-			CONFIG_SYS_FPGA_FTIM2,
-			CONFIG_SYS_FPGA_FTIM3
+			CFG_SYS_FPGA_FTIM0,
+			CFG_SYS_FPGA_FTIM1,
+			CFG_SYS_FPGA_FTIM2,
+			CFG_SYS_FPGA_FTIM3
 		},
 	}
 };

diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
index 2320356..9db3aa5 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c

@@ -12,14 +12,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }

diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
index 00ff602..3cae2a0 100644
--- a/board/freescale/ls1043ardb/eth.c
+++ b/board/freescale/ls1043ardb/eth.c

@@ -62,7 +62,7 @@
 	}
 
 	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)
 		fm_info_set_mdio(i, dev);
 
 	/* 10GBase-R on lane A, MAC 9 */

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 799900e..741a4d6 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c

@@ -33,42 +33,42 @@
 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nor",
-		CONFIG_SYS_NOR_CSPR,
-		CONFIG_SYS_NOR_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR_CSPR,
+		CFG_SYS_NOR_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 
 	},
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
 		"cpld",
-		CONFIG_SYS_CPLD_CSPR,
-		CONFIG_SYS_CPLD_CSPR_EXT,
-		CONFIG_SYS_CPLD_AMASK,
-		CONFIG_SYS_CPLD_CSOR,
+		CFG_SYS_CPLD_CSPR,
+		CFG_SYS_CPLD_CSPR_EXT,
+		CFG_SYS_CPLD_AMASK,
+		CFG_SYS_CPLD_CSOR,
 		{
-			CONFIG_SYS_CPLD_FTIM0,
-			CONFIG_SYS_CPLD_FTIM1,
-			CONFIG_SYS_CPLD_FTIM2,
-			CONFIG_SYS_CPLD_FTIM3
+			CFG_SYS_CPLD_FTIM0,
+			CFG_SYS_CPLD_FTIM1,
+			CFG_SYS_CPLD_FTIM2,
+			CFG_SYS_CPLD_FTIM3
 		},
 	}
 };
@@ -76,41 +76,41 @@
 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
 		"nor",
-		CONFIG_SYS_NOR_CSPR,
-		CONFIG_SYS_NOR_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR_CSPR,
+		CFG_SYS_NOR_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 	},
 	{
 		"cpld",
-		CONFIG_SYS_CPLD_CSPR,
-		CONFIG_SYS_CPLD_CSPR_EXT,
-		CONFIG_SYS_CPLD_AMASK,
-		CONFIG_SYS_CPLD_CSOR,
+		CFG_SYS_CPLD_CSPR,
+		CFG_SYS_CPLD_CSPR_EXT,
+		CFG_SYS_CPLD_AMASK,
+		CFG_SYS_CPLD_CSOR,
 		{
-			CONFIG_SYS_CPLD_FTIM0,
-			CONFIG_SYS_CPLD_FTIM1,
-			CONFIG_SYS_CPLD_FTIM2,
-			CONFIG_SYS_CPLD_FTIM3
+			CFG_SYS_CPLD_FTIM0,
+			CFG_SYS_CPLD_FTIM1,
+			CFG_SYS_CPLD_FTIM2,
+			CFG_SYS_CPLD_FTIM3
 		},
 	}
 };
@@ -355,7 +355,7 @@
 		return;
 
     /* Change NAND Flash PGS/SPRZ configuration */
-	csor = CONFIG_SYS_NAND_CSOR;
+	csor = CFG_SYS_NAND_CSOR;
 	if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
 		csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
 

diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
index 88265a3..926bd74 100644
--- a/board/freescale/ls1046aqds/eth.c
+++ b/board/freescale/ls1046aqds/eth.c

@@ -349,7 +349,7 @@
 		/* SGMII on slot 4, MAC 2 */
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
 		idx = i - FM1_DTSEC1;
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {

diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index dfdc9f0..3d08816 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c

@@ -41,55 +41,55 @@
 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR,
-		CONFIG_SYS_NOR0_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR,
-		CONFIG_SYS_NOR1_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR1_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 	},
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
-		CONFIG_SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_AMASK,
+		CFG_SYS_FPGA_CSOR,
 		{
-			CONFIG_SYS_FPGA_FTIM0,
-			CONFIG_SYS_FPGA_FTIM1,
-			CONFIG_SYS_FPGA_FTIM2,
-			CONFIG_SYS_FPGA_FTIM3
+			CFG_SYS_FPGA_FTIM0,
+			CFG_SYS_FPGA_FTIM1,
+			CFG_SYS_FPGA_FTIM2,
+			CFG_SYS_FPGA_FTIM3
 		},
 	}
 };
@@ -97,54 +97,54 @@
 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR,
-		CONFIG_SYS_NOR0_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR,
-		CONFIG_SYS_NOR1_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR1_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
-		CONFIG_SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_AMASK,
+		CFG_SYS_FPGA_CSOR,
 		{
-			CONFIG_SYS_FPGA_FTIM0,
-			CONFIG_SYS_FPGA_FTIM1,
-			CONFIG_SYS_FPGA_FTIM2,
-			CONFIG_SYS_FPGA_FTIM3
+			CFG_SYS_FPGA_FTIM0,
+			CFG_SYS_FPGA_FTIM1,
+			CFG_SYS_FPGA_FTIM2,
+			CFG_SYS_FPGA_FTIM3
 		},
 	}
 };

diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c
index 548601a..ee19d4f 100644
--- a/board/freescale/ls1046ardb/cpld.c
+++ b/board/freescale/ls1046ardb/cpld.c

@@ -12,14 +12,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }

diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
index 04fa57f..af70d10 100644
--- a/board/freescale/ls1046ardb/eth.c
+++ b/board/freescale/ls1046ardb/eth.c

@@ -64,7 +64,7 @@
 	}
 
 	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)
 		fm_info_set_mdio(i, dev);
 
 	/* 10GBase-R on lane A, MAC 9 */

diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index ae81740..0d3f22c 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c

@@ -41,55 +41,55 @@
 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nor0",
-		CONFIG_SYS_NOR0_CSPR_EARLY,
-		CONFIG_SYS_NOR0_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR0_CSPR_EARLY,
+		CFG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR_AMASK,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 		0,
-		CONFIG_SYS_NOR0_CSPR,
+		CFG_SYS_NOR0_CSPR,
 		0,
 	},
 	{
 		"nor1",
-		CONFIG_SYS_NOR1_CSPR_EARLY,
-		CONFIG_SYS_NOR0_CSPR_EXT,
-		CONFIG_SYS_NOR_AMASK_EARLY,
-		CONFIG_SYS_NOR_CSOR,
+		CFG_SYS_NOR1_CSPR_EARLY,
+		CFG_SYS_NOR0_CSPR_EXT,
+		CFG_SYS_NOR_AMASK_EARLY,
+		CFG_SYS_NOR_CSOR,
 		{
-			CONFIG_SYS_NOR_FTIM0,
-			CONFIG_SYS_NOR_FTIM1,
-			CONFIG_SYS_NOR_FTIM2,
-			CONFIG_SYS_NOR_FTIM3
+			CFG_SYS_NOR_FTIM0,
+			CFG_SYS_NOR_FTIM1,
+			CFG_SYS_NOR_FTIM2,
+			CFG_SYS_NOR_FTIM3
 		},
 		0,
-		CONFIG_SYS_NOR1_CSPR,
-		CONFIG_SYS_NOR_AMASK,
+		CFG_SYS_NOR1_CSPR,
+		CFG_SYS_NOR_AMASK,
 	},
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
 		SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSOR,
 		{
 			SYS_FPGA_CS_FTIM0,
 			SYS_FPGA_CS_FTIM1,
@@ -105,15 +105,15 @@
 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"nand",
-		CONFIG_SYS_NAND_CSPR,
-		CONFIG_SYS_NAND_CSPR_EXT,
-		CONFIG_SYS_NAND_AMASK,
-		CONFIG_SYS_NAND_CSOR,
+		CFG_SYS_NAND_CSPR,
+		CFG_SYS_NAND_CSPR_EXT,
+		CFG_SYS_NAND_AMASK,
+		CFG_SYS_NAND_CSOR,
 		{
-			CONFIG_SYS_NAND_FTIM0,
-			CONFIG_SYS_NAND_FTIM1,
-			CONFIG_SYS_NAND_FTIM2,
-			CONFIG_SYS_NAND_FTIM3
+			CFG_SYS_NAND_FTIM0,
+			CFG_SYS_NAND_FTIM1,
+			CFG_SYS_NAND_FTIM2,
+			CFG_SYS_NAND_FTIM3
 		},
 	},
 	{
@@ -121,10 +121,10 @@
 	},
 	{
 		"fpga",
-		CONFIG_SYS_FPGA_CSPR,
-		CONFIG_SYS_FPGA_CSPR_EXT,
+		CFG_SYS_FPGA_CSPR,
+		CFG_SYS_FPGA_CSPR_EXT,
 		SYS_FPGA_AMASK,
-		CONFIG_SYS_FPGA_CSOR,
+		CFG_SYS_FPGA_CSOR,
 		{
 			SYS_FPGA_CS_FTIM0,
 			SYS_FPGA_CS_FTIM1,
@@ -746,12 +746,12 @@
 
 	/* Read the BRDCFG54 via CLPD */
 #if !CONFIG_IS_ENABLED(DM_I2C)
-	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
+	ret = i2c_read(CFG_SYS_I2C_FPGA_ADDR,
 		       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 #else
 	struct udevice *dev;
 
-	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
+	ret = i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev);
 	if (!ret)
 		ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 				  (void *)&brdcfg4, 1);
@@ -766,7 +766,7 @@
 
 	/* Write to the BRDCFG4 */
 #if !CONFIG_IS_ENABLED(DM_I2C)
-	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
+	ret = i2c_write(CFG_SYS_I2C_FPGA_ADDR,
 			QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 #else
 	ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,

diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 971633c..a4cb1a6 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README

@@ -118,10 +118,10 @@
 Environment Variables
 ---------------------
 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
-  the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+  the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
 
 - mcmemsize: MC DRAM block size. If this variable is not defined
-  the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+  the value CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
 
 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
 -------------------------------------------------------------------

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 5df8572..91db618 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c

@@ -217,7 +217,7 @@
 
 #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 #if CONFIG_IS_ENABLED(DM_I2C)
-	rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
+	rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR);
 #else
 	rtc_enable_32khz_output();
 #endif

diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 4376755..cf5b1ee 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c

@@ -57,9 +57,9 @@
 
 static struct pl01x_serial_plat serial0 = {
 #if CONFIG_CONS_INDEX == 0
-	.base = CONFIG_SYS_SERIAL0,
+	.base = CFG_SYS_SERIAL0,
 #elif CONFIG_CONS_INDEX == 1
-	.base = CONFIG_SYS_SERIAL1,
+	.base = CFG_SYS_SERIAL1,
 #else
 #error "Unsupported console index value."
 #endif
@@ -72,7 +72,7 @@
 };
 
 static struct pl01x_serial_plat serial1 = {
-	.base = CONFIG_SYS_SERIAL1,
+	.base = CFG_SYS_SERIAL1,
 	.type = TYPE_PL011,
 };
 

diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
index 7bfb455..6125c9e 100644
--- a/board/freescale/m5208evbe/m5208evbe.c
+++ b/board/freescale/m5208evbe/m5208evbe.c

@@ -29,7 +29,7 @@
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
-	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
 
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
@@ -37,35 +37,35 @@
 	}
 	i--;
 
-	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CONFIG_SYS_SDRAM_BASE1
-	out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+#ifdef CFG_SYS_SDRAM_BASE1
+	out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
 #endif
-	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
-	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+	out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
 
 	udelay(500);
 
 	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
 
 	/* Perform two refresh cycles */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
 	asm("nop");
 
 	/* Issue LEMR */
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
 	asm("nop");
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
 	asm("nop");
 
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
 
 	out_be32(&sdram->ctrl,
-		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+		(CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
 	asm("nop");
 
 	udelay(100);

diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index e7c7a94..44161a0 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c

@@ -44,7 +44,7 @@
 		GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
 		GPIO_PAR_SDRAM_SDCS(3));
 
-	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
 			break;
@@ -61,7 +61,7 @@
 
 		/* Initialize DACR0 */
 		out_be32(&sdram->dacr0,
-			SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+			SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) |
 			SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
 			SDRAMC_DARCn_PS_32);
 		asm("nop");
@@ -80,7 +80,7 @@
 		}
 
 		/* Write to this block to initiate precharge */
-		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+		*(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696;
 
 		/*  Set RE (bit 15) in DACR */
 		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
@@ -95,7 +95,7 @@
 		asm("nop");
 
 		/* Write to the SDRAM Mode Register */
-		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+		*(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
 
 	gd->ram_size = dramsize;

diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index 48c0079..d67db24 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c

@@ -26,7 +26,7 @@
 	/*
 	 * Set LED on
 	 */
-	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
+	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED;
 	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
 
 	return 0;
@@ -42,13 +42,13 @@
 	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
 	 */
 
-#ifdef CONFIG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
 	/*
 	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
 	 */
 	mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CONFIG_SYS_PLL_BYPASS
+#elif CFG_SYS_PLL_BYPASS
 	/*
 	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
@@ -86,7 +86,7 @@
 	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
 	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
 
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
 
 	return 0;
 };

diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index bff1ac5..fbd4835 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c

@@ -42,7 +42,7 @@
 	ulong size = 0;
 	ulong fbase = 0;
 
-	fbase = (ulong) CONFIG_SYS_FLASH_BASE;
+	fbase = (ulong) CFG_SYS_FLASH_BASE;
 	flash_get_size((FPWV *) fbase, &flash_info[0]);
 	flash_get_offsets((ulong) fbase, &flash_info[0]);
 	fbase += flash_info[0].size;
@@ -64,9 +64,9 @@
 
 		info->start[0] = base;
 		info->protect[0] = 0;
-		for (i = 1; i < CONFIG_SYS_SST_SECT; i++) {
+		for (i = 1; i < CFG_SYS_SST_SECT; i++) {
 			info->start[i] = info->start[i - 1]
-						+ CONFIG_SYS_SST_SECTSZ;
+						+ CFG_SYS_SST_SECTSZ;
 			info->protect[i] = 0;
 		}
 	}
@@ -162,8 +162,8 @@
 
 	info->sector_count = 0;
 	info->size = 0;
-	info->sector_count = CONFIG_SYS_SST_SECT;
-	info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ;
+	info->sector_count = CFG_SYS_SST_SECT;
+	info->size = CFG_SYS_SST_SECT * CFG_SYS_SST_SECTSZ;
 
 	/* reset ID mode */
 	*addr = (FPWV) 0x00F000F0;
@@ -222,7 +222,7 @@
 
 	start = get_timer(0);
 
-	if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
+	if ((s_last - s_first) == (CFG_SYS_SST_SECT - 1)) {
 		if (prot == 0) {
 			addr = (FPWV *) info->start[0];
 
@@ -259,7 +259,7 @@
 				enable_interrupts();
 
 			return 0;
-		} else if (prot == CONFIG_SYS_SST_SECT) {
+		} else if (prot == CFG_SYS_SST_SECT) {
 			return 1;
 		}
 	}
@@ -282,7 +282,7 @@
 
 					flag = disable_interrupts();
 
-					base = (FPWV *) (CONFIG_SYS_FLASH_BASE);	/* First sector */
+					base = (FPWV *) (CFG_SYS_FLASH_BASE);	/* First sector */
 
 					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
 					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
@@ -411,7 +411,7 @@
 		return (2);
 	}
 
-	base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+	base = (FPWV *) (CFG_SYS_FLASH_BASE);
 
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();

diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 85f5f0c..c1cff52 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c

@@ -36,7 +36,7 @@
 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
 		u32 RC, temp;
 
-		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
+		RC = (CFG_SYS_CLK / 1000000) >> 1;
 		RC = (RC * 15) >> 4;
 
 		/* Initialize DRAM Control Register: DCR */
@@ -47,7 +47,7 @@
 		__asm__("nop");
 
 		/* Initialize DMR0 */
-		dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
+		dramsize = (CFG_SYS_SDRAM_SIZE << 20);
 		temp = (dramsize - 1) & 0xFFFC0000;
 		mbar_writeLong(MCFSIM_DMR0, temp | 1);
 		__asm__("nop");
@@ -57,7 +57,7 @@
 		__asm__("nop");
 
 		/* Write to this block to initiate precharge */
-		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+		*(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
 		mb();
 		__asm__("nop");
 
@@ -74,7 +74,7 @@
 			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
 		__asm__("nop");
 
-		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+		*(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
 		mb();
 	}
 
@@ -113,7 +113,7 @@
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
 
 #define CALC_TIMING(t) (t + period - 1) / period
-		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
+		period = 1000000000 / (CFG_SYS_CLK / 2);	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
 		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));

diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index 9580cf2..3c20a23 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c

@@ -30,7 +30,7 @@
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)0) = 0;
 
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
 
 	return 0;
 	};

diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index 1c4fb72..00fa35c 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c

@@ -35,7 +35,7 @@
 	out_be16(&gpio_reg->par_sdram, 0x3FF);
 
 	/* Set up chip select */
-	out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+	out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE);
 	out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
 
 	/* Set up timing */
@@ -49,34 +49,34 @@
 	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
 
 	/* Dummy write to start SDRAM */
-	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Send LEMR */
 	setbits_be32(&sdp->sdmr,
 		MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
 		MCF_SDRAMC_SDMR_CMD);
-	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Send LMR */
 	out_be32(&sdp->sdmr, 0x058d0000);
-	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Stop sending commands */
 	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
 
 	/* Set precharge */
 	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
-	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Stop manual precharge, send 2 IREF */
 	clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
 	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
-	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
-	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 
 	out_be32(&sdp->sdmr, 0x018d0000);
-	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Stop sending commands */
 	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
@@ -91,7 +91,7 @@
 		| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
 		| MCF_SDRAMC_SDCR_DQS_OE(0x3));
 
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
 
 	return 0;
 };

diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index e1ea9b3..53e0f20 100644
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c

@@ -21,7 +21,7 @@
 {
 	u32 dramsize, i, dramclk;
 
-	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
 			break;
@@ -40,7 +40,7 @@
 
 		/* Initialize DACR0 */
 		MCFSDRAMC_DACR0 = (0
-			| MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
+			| MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE)
 			| MCFSDRAMC_DACR_CASL(1)
 			| MCFSDRAMC_DACR_CBM(3)
 			| MCFSDRAMC_DACR_PS_32);
@@ -62,7 +62,7 @@
 		}
 
 		/* Write to this block to initiate precharge */
-		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+		*(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696;
 		asm("nop");
 
 		/* Set RE (bit 15) in DACR */
@@ -79,7 +79,7 @@
 		asm("nop");
 
 		/* Write to the SDRAM Mode Register */
-		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+		*(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
 	gd->ram_size = dramsize;
 

diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README
index 8a7d8ca..34f05f3 100644
--- a/board/freescale/m53017evb/README
+++ b/board/freescale/m53017evb/README

@@ -68,7 +68,7 @@
 CONFIG_M53017EVB		-- define for M53017EVB board
 
 CONFIG_MCFUART			-- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CFG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
 CONFIG_BAUDRATE			-- define UART baudrate
 
 CONFIG_MCFRTC			-- define to use common CF RTC driver
@@ -96,17 +96,17 @@
 CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
 CONFIG_SYS_IMMR			-- define for MBAR offset
 
-CONFIG_SYS_MBAR			-- define MBAR offset
+CFG_SYS_MBAR			-- define MBAR offset
 
 CONFIG_MONITOR_IS_IN_RAM	-- Not support
 
-CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5301x internal SRAM
+CFG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5301x internal SRAM
 
 CONFIG_SYS_CSn_BASE		-- defines the Chip Select Base register
 CONFIG_SYS_CSn_MASK		-- defines the Chip Select Mask register
 CONFIG_SYS_CSn_CTRL		-- defines the Chip Select Control register
 
-CONFIG_SYS_SDRAM_BASE		-- defines the DRAM Base
+CFG_SYS_SDRAM_BASE		-- defines the DRAM Base
 
 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
 ===========================================

diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
index c9f8935..76ebc0a 100644
--- a/board/freescale/m53017evb/m53017evb.c
+++ b/board/freescale/m53017evb/m53017evb.c

@@ -29,7 +29,7 @@
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
-	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
 
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
@@ -37,35 +37,35 @@
 	}
 	i--;
 
-	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CONFIG_SYS_SDRAM_BASE1
-	out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+#ifdef CFG_SYS_SDRAM_BASE1
+	out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
 #endif
-	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
-	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+	out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
 
 	udelay(500);
 
 	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
 
 	/* Perform two refresh cycles */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
 	asm("nop");
 
 	/* Issue LEMR */
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
 	asm("nop");
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
 	asm("nop");
 
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
 
 	out_be32(&sdram->ctrl,
-		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+		(CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
 	asm("nop");
 
 	udelay(100);

diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index 7a75b04..b278dbf 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c

@@ -29,7 +29,7 @@
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
-	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
 
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
@@ -37,30 +37,30 @@
 	}
 	i--;
 
-	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
-	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+	out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
 
 	/* Issue LEMR */
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
 
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
 
 	out_be32(&sdram->ctrl,
-		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+		(CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
 
 	udelay(100);
 

diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index a10c365..d921eef 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c

@@ -23,7 +23,7 @@
 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd_to_nand(mtdinfo);
-	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+	volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;

diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README
index bba5420..7240648 100644
--- a/board/freescale/m5373evb/README
+++ b/board/freescale/m5373evb/README

@@ -67,7 +67,7 @@
 CONFIG_M5373EVB		-- define for M5373EVB board
 
 CONFIG_MCFUART		-- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CFG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
 CONFIG_BAUDRATE		-- define UART baudrate
 
 CONFIG_MCFRTC		-- define to use common CF RTC driver
@@ -95,17 +95,17 @@
 CONFIG_SYS_I2C_OFFSET		-- define for I2C base address offset
 CONFIG_SYS_IMMR		-- define for MBAR offset
 
-CONFIG_SYS_MBAR		-- define MBAR offset
+CFG_SYS_MBAR		-- define MBAR offset
 
 CONFIG_MONITOR_IS_IN_RAM -- Not support
 
-CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5373 internal SRAM
+CFG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF5373 internal SRAM
 
 CONFIG_SYS_CSn_BASE	-- defines the Chip Select Base register
 CONFIG_SYS_CSn_MASK	-- defines the Chip Select Mask register
 CONFIG_SYS_CSn_CTRL	-- defines the Chip Select Control register
 
-CONFIG_SYS_SDRAM_BASE	-- defines the DRAM Base
+CFG_SYS_SDRAM_BASE	-- defines the DRAM Base
 
 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
 ===========================================

diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index cfa5ca4..0e9eec3 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c

@@ -29,7 +29,7 @@
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
-	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
 
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
@@ -37,30 +37,30 @@
 	}
 	i--;
 
-	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
-	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+	out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
 
 	/* Issue LEMR */
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
 
-	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+	out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
 
 	out_be32(&sdram->ctrl,
-		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+		(CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
 
 	udelay(100);
 

diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index fdf3e0a..6d825a6 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c

@@ -23,7 +23,7 @@
 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd_to_nand(mtdinfo);
-	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+	volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;

diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 2650d30..4a14554 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c

@@ -22,7 +22,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SYS_DRAM_TEST)
+#if defined(CFG_SYS_DRAM_TEST)
 int
 testdram(void)
 {
@@ -97,37 +97,37 @@
 int fixed_sdram(void)
 {
 	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_SDRAM_SIZE;
+	u32 msize = CFG_SYS_SDRAM_SIZE;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+	im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
 	udelay(50000);
 
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+	im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
 	udelay(1000);
 
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG;
 	udelay(1000);
 
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CFG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL;
 	sync();
 	udelay(1000);
 
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 	udelay(2000);
-	return CONFIG_SYS_SDRAM_SIZE >> 20;
+	return CFG_SYS_SDRAM_SIZE >> 20;
 }
 #endif	/*!CONFIG_SYS_SPD_EEPROM */
 

diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig
index bd9153b..bb0a075 100644
--- a/board/freescale/mpc8548cds/Kconfig
+++ b/board/freescale/mpc8548cds/Kconfig

@@ -3,6 +3,12 @@
 config PCI1
 	def_bool y
 
+config FSL_CADMUS
+	def_bool y
+
+config INTERRUPTS
+	def_bool y
+
 config SYS_BOARD
 	default "mpc8548cds"
 

diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index d194388..7b6ef5b 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c

@@ -12,7 +12,7 @@
 
 struct law_entry law_table[] = {
 	/* LBC window - maps 256M */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index e4c951f..73e024e 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c

@@ -103,11 +103,11 @@
 
 	uint idx;
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;
 
 	puts("LBC SDRAM: ");
-	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+	print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
 		   "\n");
 
 	/*
@@ -115,17 +115,17 @@
 	 */
 	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
 	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->lbcr = CFG_SYS_LBC_LBCR;
 	asm("msync");
 
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	lbc->lsrt = CFG_SYS_LBC_LSRT;
+	lbc->mrtpr = CFG_SYS_LBC_MRTPR;
 	asm("msync");
 
 	/*
 	 * MPC8548 uses "new" 15-16 style addressing.
 	 */
-	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON;
 	lsdmr_common |= LSDMR_BSMA1516;
 
 	/*

diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index 8d1e5fe..994a32d 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c

@@ -11,16 +11,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -29,7 +29,7 @@
 	 * Entry 0:
 	 * FLASH(cover boot page)	16M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -37,7 +37,7 @@
 	 * Entry 1:
 	 * CCSRBAR	1M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1M, 1),
 
@@ -45,8 +45,8 @@
 	 * Entry 2:
 	 * LBC SDRAM	64M	Cacheable, non-guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
-		      CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE,
+		      CFG_SYS_LBC_SDRAM_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 2, BOOKE_PAGESZ_64M, 1),
 
@@ -62,7 +62,7 @@
 	 * Entry 4:
 	 * PCI and PCIe MEM	1G	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_1G, 1),
 
@@ -70,7 +70,7 @@
 	 * Entry 5:
 	 * PCI1 IO	1M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_1M, 1),
 
@@ -78,7 +78,7 @@
 	 * Entry 6:
 	 * PCIe IO	1M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_1M, 1),
 };

diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 46095ac..86364ac 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c

@@ -30,7 +30,7 @@
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
 				PHYS_SDRAM_1_SIZE);
 	return 0;
 }

diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index 4f27d3e..d447ad8 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c

@@ -42,7 +42,7 @@
 
 	int rev = readl(&fuse->gp[6]);
 
-	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
+	if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR))
 		rev = 0;
 
 	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
@@ -81,7 +81,7 @@
 	int ret;
 	struct pmic *p;
 
-	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+	if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) {
 		ret = pmic_dialog_init(I2C_PMIC);
 		if (ret)
 			return ret;

diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
index debf571..13fc2fa 100644
--- a/board/freescale/p1010rdb/law.c
+++ b/board/freescale/p1010rdb/law.c

@@ -8,9 +8,9 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index c39df46..0f01482 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c

@@ -83,7 +83,7 @@
 int board_early_init_f(void)
 {
 	ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
-	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 	/* Clock configuration to access CPLD using IFC(GPCM) */
 	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
 	/*
@@ -97,7 +97,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -118,12 +118,12 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel, BOOKE_PAGESZ_16M, 1);
 
 	set_tlb(1, flashbase + 0x1000000,
-			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+			CFG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
 	return 0;
@@ -138,7 +138,7 @@
 	struct udevice *dev;
 	int ret;
 #if defined(CONFIG_TARGET_P1010RDB_PA)
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
 				      I2C_PCA9557_ADDR1, 1, &dev);
@@ -254,7 +254,7 @@
 #endif
 #else
 #if defined(CONFIG_TARGET_P1010RDB_PA)
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 
 	switch (ctrl_type) {
 	case MUX_TYPE_IFC:
@@ -404,7 +404,7 @@
 int checkboard(void)
 {
 	struct cpu_type *cpu;
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	u8 val;
 
 	cpu = gd->arch.cpu;
@@ -587,7 +587,7 @@
 	int nodeoff;
 
 	nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
-					CONFIG_SYS_NS16550_COM2);
+					CFG_SYS_NS16550_COM2);
 
 	if (nodeoff > 0) {
 		fdt_status_disabled(blob, nodeoff);

diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 0db11f4..e450f62 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c

@@ -29,7 +29,7 @@
 {
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
-	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 
 	console_init_f();
 
@@ -45,7 +45,7 @@
 	plat_ratio >>= 1;
 	gd->bus_clk = get_board_sys_clk() * plat_ratio;
 
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
 		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
 
 #ifdef CONFIG_SPL_MMC_BOOT

diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index a262d5c..8f0dec4 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c

@@ -22,9 +22,9 @@
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
 #endif
 
 	/* initialize selected port with appropriate baud rate */
@@ -32,7 +32,7 @@
 	plat_ratio >>= 1;
 	gd->bus_clk = get_board_sys_clk() * plat_ratio;
 
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
 		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
 
 	puts("\nNAND boot... ");
@@ -54,9 +54,9 @@
 void putc(char c)
 {
 	if (c == '\n')
-		ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
+		ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r');
 
-	ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
+	ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c);
 }
 
 void puts(const char *str)

diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 7992666..265cde8 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c

@@ -8,19 +8,19 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -36,51 +36,51 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
 #ifndef CONFIG_SPL_BUILD
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 2, BOOKE_PAGESZ_16M, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
-			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE + 0x1000000,
+			CFG_SYS_FLASH_BASE_PHYS + 0x1000000,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 3, BOOKE_PAGESZ_16M, 1),
 
 #ifdef CONFIG_PCI
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 4, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 5, BOOKE_PAGESZ_256K, 1),
 #endif
 #endif
 
 	/* *I*G - Board CPLD  */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_256K, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_1M, 1),
 
 #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
 	/* *I*G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 11, BOOKE_PAGESZ_256K, 1)
 #endif

diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 038e673..5f16779 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c

@@ -201,7 +201,7 @@
 }
 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
 
-#ifdef CONFIG_SYS_DDR_CS0_BNDS
+#ifdef CFG_SYS_DDR_CS0_BNDS
 /* Fixed sdram init -- doesn't use serial presence detect. */
 phys_size_t fixed_sdram(void)
 {
@@ -209,46 +209,46 @@
 	char buf[32];
 	size_t ddr_size;
 	fsl_ddr_cfg_regs_t ddr_cfg_regs = {
-		.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-		.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-		.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+		.cs[0].bnds = CFG_SYS_DDR_CS0_BNDS,
+		.cs[0].config = CFG_SYS_DDR_CS0_CONFIG,
+		.cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2,
 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-		.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
-		.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
-		.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+		.cs[1].bnds = CFG_SYS_DDR_CS1_BNDS,
+		.cs[1].config = CFG_SYS_DDR_CS1_CONFIG,
+		.cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2,
 #endif
-		.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
-		.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
-		.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
-		.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
-		.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
-		.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
-		.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
-		.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
-		.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-		.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+		.timing_cfg_3 = CFG_SYS_DDR_TIMING_3,
+		.timing_cfg_0 = CFG_SYS_DDR_TIMING_0,
+		.timing_cfg_1 = CFG_SYS_DDR_TIMING_1,
+		.timing_cfg_2 = CFG_SYS_DDR_TIMING_2,
+		.ddr_sdram_cfg = CFG_SYS_DDR_CONTROL,
+		.ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2,
+		.ddr_sdram_mode = CFG_SYS_DDR_MODE_1,
+		.ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2,
+		.ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL,
+		.ddr_sdram_interval = CFG_SYS_DDR_INTERVAL,
 		.ddr_data_init = 0xdeadbeef, /* Poison value */
-		.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
-		.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-		.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-		.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-		.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-		.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
-		.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-		.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
-		.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-		.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+		.ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL,
+		.ddr_init_addr = CFG_SYS_DDR_INIT_ADDR,
+		.ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR,
+		.timing_cfg_4 = CFG_SYS_DDR_TIMING_4,
+		.timing_cfg_5 = CFG_SYS_DDR_TIMING_5,
+		.ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL,
+		.ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL,
+		.ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR,
+		.ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1,
+		.ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2
 	};
 
 	get_sys_info(&sysinfo);
 	printf("Configuring DDR for %s MT/s data rate\n",
 			strmhz(buf, sysinfo.freq_ddrbus));
 
-	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
 
 	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
-	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+	if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE,
 				ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
 		printf("ERROR setting Local Access Windows for DDR\n");
 		return 0;

diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 6bdfb35..6085984 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c

@@ -8,13 +8,13 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_VSC7385_ENET
-	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
 #endif
 };
 

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 2999c85..ab79724 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c

@@ -90,20 +90,20 @@
 	 * This ensures that external watchdog does not trigger
 	 * another reset or possible infinite reset loop.
 	 */
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
 	in_8(&cpld_data->wd_cfg); /* Read back to sync write */
 }
 
 void board_reset_last(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	out_8(&cpld_data->system_rst, 1);
 }
 
 void board_cpld_init(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg);
 
 	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
@@ -226,7 +226,7 @@
 
 int checkboard(void)
 {
-	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
 	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	u8 in, out, invert, io_config, val;
 	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
@@ -246,7 +246,7 @@
 	struct udevice *dev;
 	int ret;
 
-	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
+	ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_PCA9557_ADDR,
 				      1, &dev);
 	if (ret) {
 		printf("%s: Cannot find udev for a bus %d\n", __func__,
@@ -264,10 +264,10 @@
 	#else /* Non DM I2C support - will be removed */
 	i2c_set_bus_num(bus_num);
 
-	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
-	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
-	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
-	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
+	if (i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
+	    i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
+	    i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 ||
+	    i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
 		printf("Error reading i2c boot information!\n");
 		return 0; /* Don't want to hang() on this error */
 	}
@@ -319,7 +319,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 #ifdef CONFIG_VSC7385_ENET
 	unsigned int vscfw_addr;
@@ -344,7 +344,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
 		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
 

diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index e7d4428..6c3f828 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c

@@ -57,7 +57,7 @@
 	bus_clk = get_board_sys_clk() * plat_ratio;
 	gd->bus_clk = bus_clk;
 
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
 		     bus_clk / 16 / CONFIG_BAUDRATE);
 #ifdef CONFIG_SPL_MMC_BOOT
 	puts("\nSD boot...\n");

diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index e467c7a..f9e0b5b 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c

@@ -21,9 +21,9 @@
 	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
-	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
-	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
 #endif
 
 	/* initialize selected port with appropriate baud rate */
@@ -31,7 +31,7 @@
 	plat_ratio >>= 1;
 	gd->bus_clk = get_board_sys_clk() * plat_ratio;
 
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
 		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
 
 	puts("\nNAND boot... ");
@@ -52,9 +52,9 @@
 void putc(char c)
 {
 	if (c == '\n')
-		ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
+		ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r');
 
-	ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
+	ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c);
 }
 
 void puts(const char *str)

diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 65cedd4..9477396 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c

@@ -8,20 +8,20 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+			CFG_SYS_INIT_RAM_ADDR_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -32,71 +32,71 @@
 			0, 0, BOOKE_PAGESZ_4K, 1),
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
 #ifndef CONFIG_SPL_BUILD
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 2, BOOKE_PAGESZ_64M, 1),
 
 #ifdef CONFIG_PCI
 	/* *I*G* - PCI memory 1.5G */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI I/O effective: 192K  */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 4, BOOKE_PAGESZ_256K, 1),
 #endif
 
 #ifdef CONFIG_VSC7385_ENET
 	/* *I*G - VSC7385 Switch */
-	SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_VSC7385_BASE, CFG_SYS_VSC7385_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 5, BOOKE_PAGESZ_1M, 1),
 #endif
 #endif /* not SPL */
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_1M, 1),
 
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
 #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
 	/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
 	/* **M** - 2G DDR on P1020MBG, map the second 1G */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif /* RAMBOOT/SPL */
 
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
 	/* ***G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 11, BOOKE_PAGESZ_256K, 1),
 #if CONFIG_SYS_L2_SIZE >= (256 << 10)
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + 0x40000,
+		      CFG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 12, BOOKE_PAGESZ_256K, 1)
 #endif

diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 23fd619..3e12c81 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c

@@ -35,10 +35,10 @@
 };
 
 static int riser_phy_addr[] = {
-	CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
+	CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
+	CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
+	CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
+	CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
 };
 
 /*
@@ -101,12 +101,12 @@
 		slot = lane_to_slot[lane];
 		if (slot) {
 			sprintf(phy, "phy_sgmii_%x",
-					CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+					CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
 					+ (port - FM1_DTSEC1));
 			fdt_set_phy_handle(fdt, compat, addr, phy);
 		} else {
 			sprintf(phy, "phy_sgmii_%x",
-					CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
+					CFG_SYS_FM1_DTSEC1_PHY_ADDR
 					+ (port - FM1_DTSEC1));
 			fdt_set_phy_handle(fdt, compat, addr, phy);
 		}
@@ -158,11 +158,11 @@
 	 * is RGMII, we'll also override its PHY address later. We assume that
 	 * DTSEC4 and DTSEC5 are used for RGMII.
 	 */
-	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR);
 
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
 		int idx = i - FM1_DTSEC1;
 
 		switch (fm_info_get_enet_if(i)) {
@@ -180,8 +180,8 @@
 		case PHY_INTERFACE_MODE_RGMII_ID:
 			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
 			fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
-					CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
-					CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+					CFG_SYS_FM1_DTSEC5_PHY_ADDR :
+					CFG_SYS_FM1_DTSEC4_PHY_ADDR);
 			break;
 		default:
 			printf("Fman1: DTSEC%u set to unknown interface %i\n",
@@ -198,7 +198,7 @@
 		slot = lane_to_slot[lane];
 		if (slot)
 			fm_info_set_phy_address(FM1_10GEC1,
-					CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+					CFG_SYS_FM1_10GEC1_PHY_ADDR);
 	}
 
 	fm_info_set_mdio(FM1_10GEC1,

diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 1b12630..575259b 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c

@@ -119,7 +119,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -140,7 +140,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, flash_esel, BOOKE_PAGESZ_256M, 1);
 

diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c
index 47c3b16..17a6226 100644
--- a/board/freescale/t102xrdb/cpld.c
+++ b/board/freescale/t102xrdb/cpld.c

@@ -14,14 +14,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }

diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index 818c20c..1b41739 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c

@@ -222,7 +222,7 @@
 #if defined(CONFIG_DEEP_SLEEP)
 void board_mem_sleep_setup(void)
 {
-	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+	void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
 
 	/* does not provide HW signals for power management */
 	clrbits_8(cpld_base + 0x17, 0x40);

diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index be42efa..ed6b363 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c

@@ -85,7 +85,7 @@
 		break;
 	}
 
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
 		case PHY_INTERFACE_MODE_RGMII:
@@ -112,7 +112,7 @@
 		}
 	}
 
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);

diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c
index 04a4239..d636bef 100644
--- a/board/freescale/t102xrdb/law.c
+++ b/board/freescale/t102xrdb/law.c

@@ -9,22 +9,22 @@
 
 struct law_entry law_table[] = {
 #ifdef CONFIG_MTD_NOR_FLASH
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 #endif
 };
 

diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index 3ba94fe..9faf259 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c

@@ -73,7 +73,7 @@
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
 		     ccb_clk / 16 / CONFIG_BAUDRATE);
 
 #if defined(CONFIG_SPL_MMC_BOOT)

diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index f777f5a..baa5961 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c

@@ -130,8 +130,8 @@
 
 int board_early_init_r(void)
 {
-#ifdef CONFIG_SYS_FLASH_BASE
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+#ifdef CFG_SYS_FLASH_BASE
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 	/*
 	 * Remap Boot flash region to caching-inhibited
@@ -150,7 +150,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif

diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
index 97080eb..2519a9e 100644
--- a/board/freescale/t102xrdb/tlb.c
+++ b/board/freescale/t102xrdb/tlb.c

@@ -8,31 +8,31 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
 	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
 #else
@@ -42,69 +42,69 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 #ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 8, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 9, BOOKE_PAGESZ_4M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+#ifdef CFG_SYS_NAND_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 11, BOOKE_PAGESZ_256K, 1),
 #endif
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 12, BOOKE_PAGESZ_1G, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif

diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c
index ac34095..9ac57bb 100644
--- a/board/freescale/t104xrdb/cpld.c
+++ b/board/freescale/t104xrdb/cpld.c

@@ -7,7 +7,7 @@
  *
  * The following macros need to be defined:
  *
- * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
+ * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
  */
 
 #include <common.h>
@@ -18,14 +18,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }

diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 539a36d..02ddb66 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c

@@ -115,7 +115,7 @@
 #if defined(CONFIG_DEEP_SLEEP)
 void board_mem_sleep_setup(void)
 {
-	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+	void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE;
 
 	/* does not provide HW signals for power management */
 	clrbits_8(cpld_base + 0x17, 0x40);

diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index bb6641b..fe51d68 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c

@@ -39,7 +39,7 @@
 	/*
 	 * Program on board RGMII, SGMII PHY addresses.
 	 */
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
 		int idx = i - FM1_DTSEC1;
 
 		switch (fm_info_get_enet_if(i)) {
@@ -49,7 +49,7 @@
 			 * DTSEC3
 			 */
 			fm_info_set_phy_address(FM1_DTSEC3,
-						CONFIG_SYS_SGMII1_PHY_ADDR);
+						CFG_SYS_SGMII1_PHY_ADDR);
 			break;
 #endif
 #ifdef CONFIG_TARGET_T1042RDB
@@ -59,7 +59,7 @@
 				fm_info_set_phy_address(i, 0);
 			/* T1042RDB only supports SGMII on DTSEC3 */
 			fm_info_set_phy_address(FM1_DTSEC3,
-						CONFIG_SYS_SGMII1_PHY_ADDR);
+						CFG_SYS_SGMII1_PHY_ADDR);
 			break;
 #endif
 #ifdef CONFIG_TARGET_T1042D4RDB
@@ -68,11 +68,11 @@
 			 *  & DTSEC3
 			 */
 			if (FM1_DTSEC1 == i)
-				phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
+				phy_addr = CFG_SYS_SGMII1_PHY_ADDR;
 			if (FM1_DTSEC2 == i)
-				phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
+				phy_addr = CFG_SYS_SGMII2_PHY_ADDR;
 			if (FM1_DTSEC3 == i)
-				phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
+				phy_addr = CFG_SYS_SGMII3_PHY_ADDR;
 			fm_info_set_phy_address(i, phy_addr);
 			break;
 #endif
@@ -81,9 +81,9 @@
 		case PHY_INTERFACE_MODE_RGMII_RXID:
 		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (FM1_DTSEC4 == i)
-				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+				phy_addr = CFG_SYS_RGMII1_PHY_ADDR;
 			if (FM1_DTSEC5 == i)
-				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+				phy_addr = CFG_SYS_RGMII2_PHY_ADDR;
 			fm_info_set_phy_address(i, phy_addr);
 			break;
 		case PHY_INTERFACE_MODE_QSGMII:
@@ -112,7 +112,7 @@
 	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
 		for (i = 0; i < 4; i++) {
 			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-			phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+			phy_addr = CFG_SYS_FM1_QSGMII11_PHY_ADDR + i;
 			phy_int = PHY_INTERFACE_MODE_QSGMII;
 
 			vsc9953_port_info_set_mdio(i, bus);
@@ -124,7 +124,7 @@
 	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
 		for (i = 4; i < 8; i++) {
 			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-			phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+			phy_addr = CFG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
 			phy_int = PHY_INTERFACE_MODE_QSGMII;
 
 			vsc9953_port_info_set_mdio(i, bus);

diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
index 0f6b71a..a0d6eb5 100644
--- a/board/freescale/t104xrdb/law.c
+++ b/board/freescale/t104xrdb/law.c

@@ -9,22 +9,22 @@
 
 struct law_entry law_table[] = {
 #ifdef CONFIG_MTD_NOR_FLASH
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 #endif
 };
 

diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index c7fb427..dd8283f 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c

@@ -46,7 +46,7 @@
 		porsr1 = in_be32(&gur->porsr1);
 		pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
 			  | 0x24800000);
-		out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
+		out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000),
 			 pinctl);
 	}
 #endif
@@ -72,7 +72,7 @@
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	uart_clk = sys_clk * plat_ratio / 2;
 
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
 		     uart_clk / 16 / CONFIG_BAUDRATE);
 
 	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);

diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 7d3fd29..45ebdd3 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c

@@ -62,8 +62,8 @@
 
 int board_early_init_r(void)
 {
-#ifdef CONFIG_SYS_FLASH_BASE
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+#ifdef CFG_SYS_FLASH_BASE
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -84,7 +84,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif

diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 9dcba79..10be580 100644
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c

@@ -8,32 +8,32 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) && \
 	!defined(CONFIG_NXP_ESBC)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
 	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
 
@@ -44,8 +44,8 @@
 	 * and virtual address is 0xfffc0000
 	 */
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
-		      CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_VADDR,
+		      CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
 #else
@@ -55,74 +55,74 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 #ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 8, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 9, BOOKE_PAGESZ_4M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 11, BOOKE_PAGESZ_256K, 1),
 #endif
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 12, BOOKE_PAGESZ_1G, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif

diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 555985b..62261f5 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c

@@ -625,7 +625,7 @@
 		break;
 	}
 
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
 		idx = i - FM1_DTSEC1;
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
@@ -673,7 +673,7 @@
 		}
 	}
 
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
 		idx = i - FM1_10GEC1;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:

diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c
index 40fdcf6..3cdd493 100644
--- a/board/freescale/t208xqds/law.c
+++ b/board/freescale/t208xqds/law.c

@@ -11,22 +11,22 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
 #ifdef QIXIS_BASE_PHYS
 	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
 #endif
 };
 

diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index 8b68329..8866be5 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c

@@ -82,7 +82,7 @@
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
 		     ccb_clk / 16 / CONFIG_BAUDRATE);
 
 #if defined(CONFIG_SPL_MMC_BOOT)

diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 82710cf..8be55e5 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c

@@ -282,7 +282,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -303,7 +303,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 

diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
index 1e501da..3d220af 100644
--- a/board/freescale/t208xqds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c

@@ -11,31 +11,31 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_1M, 1),
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -43,8 +43,8 @@
 	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
 	 * space is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_1M, 1),
 #else
@@ -54,75 +54,75 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 #ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCIe 1, 0x80000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_512M, 1),
 
 	/* *I*G* - PCIe 2, 0xa0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCIe 3, 0xb0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_256M, 1),
 
 
 	/* *I*G* - PCIe 4, 0xc0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 11, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
@@ -136,14 +136,14 @@
 	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
 	 * fetching ucode and ENV from master
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif

diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c
index b9ba62a..933fa0d 100644
--- a/board/freescale/t208xrdb/cpld.c
+++ b/board/freescale/t208xrdb/cpld.c

@@ -11,14 +11,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }

diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c
index d3b263f..53a1369 100644
--- a/board/freescale/t208xrdb/law.c
+++ b/board/freescale/t208xrdb/law.c

@@ -11,22 +11,22 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
 #endif
 };
 

diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 3f9b1fa..130cb88 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c

@@ -42,7 +42,7 @@
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
 		     ccb_clk / 16 / CONFIG_BAUDRATE);
 
 #if defined(CONFIG_SPL_MMC_BOOT)

diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 1c8017b..04cb313 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c

@@ -77,7 +77,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 	/*
 	 * Remap Boot flash + PROMJET region to caching-inhibited
@@ -96,7 +96,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 

diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 542ab1e..688a208 100644
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c

@@ -11,31 +11,31 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_1M, 1),
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -43,8 +43,8 @@
 	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
 	 * space is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_1M, 1),
 #else
@@ -54,80 +54,80 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 #ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCIe 1, 0x80000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_512M, 1),
 
 	/* *I*G* - PCIe 2, 0xa0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCIe 3, 0xb0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_256M, 1),
 
 
 	/* *I*G* - PCIe 4, 0xc0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 11, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 17, BOOKE_PAGESZ_4K, 1),
 #endif
@@ -136,13 +136,13 @@
 	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
 	 * fetching ucode and ENV from master
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif

diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
index d484509..8b10120 100644
--- a/board/freescale/t4rdb/cpld.c
+++ b/board/freescale/t4rdb/cpld.c

@@ -9,7 +9,7 @@
  *
  * The following macros need to be defined:
  *
- * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CFG_SYS_CPLD_BASE - The virtual address of the base of the
  * CPLD register map
  *
  */
@@ -22,14 +22,14 @@
 
 u8 cpld_read(unsigned int reg)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	return in_8(p + reg);
 }
 
 void cpld_write(unsigned int reg, u8 value)
 {
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+	void *p = (void *)CFG_SYS_CPLD_BASE;
 
 	out_8(p + reg, value);
 }

diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 4041b3d..241ee5a 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c

@@ -81,7 +81,7 @@
 	fm_disable_port(FM1_DTSEC5);
 	fm_disable_port(FM1_DTSEC6);
 
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
 		case PHY_INTERFACE_MODE_SGMII:
@@ -93,7 +93,7 @@
 		}
 	}
 
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
@@ -104,7 +104,7 @@
 		}
 	}
 
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
 		/* SGMII && 10GBase-R */
 		fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
@@ -121,7 +121,7 @@
 
 	fm_disable_port(FM2_DTSEC5);
 	fm_disable_port(FM2_DTSEC6);
-	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) {
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
 		case PHY_INTERFACE_MODE_SGMII:
@@ -133,7 +133,7 @@
 		}
 	}
 
-	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+	for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) {
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
@@ -143,7 +143,7 @@
 			break;
 		}
 	}
-#endif /* CONFIG_SYS_NUM_FMAN */
+#endif /* CFG_SYS_NUM_FMAN */
 
 	cpu_eth_init(bis);
 #endif /* CONFIG_FMAN_ENET */

diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c
index 038f605..43eeb88 100644
--- a/board/freescale/t4rdb/law.c
+++ b/board/freescale/t4rdb/law.c

@@ -8,22 +8,22 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CFG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#ifdef CFG_SYS_NAND_BASE_PHYS
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 #endif
 };
 

diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 72d3b80..779457d 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c

@@ -51,7 +51,7 @@
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 
-	ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+	ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
 		     ccb_clk / 16 / CONFIG_BAUDRATE);
 
 	puts("\nSD boot...\n");

diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 20ce752..0bd0ba9 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c

@@ -54,7 +54,7 @@
 
 int board_early_init_r(void)
 {
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -75,7 +75,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 

diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h
index 06779f5..bb3ce21 100644
--- a/board/freescale/t4rdb/t4rdb.h
+++ b/board/freescale/t4rdb/t4rdb.h

@@ -6,10 +6,10 @@
 #ifndef __T4RDB_H__
 #define __T4RDB_H__
 
-#undef CONFIG_SYS_NUM_FM1_DTSEC
-#undef CONFIG_SYS_NUM_FM2_DTSEC
-#define CONFIG_SYS_NUM_FM1_DTSEC	4
-#define CONFIG_SYS_NUM_FM2_DTSEC	4
+#undef CFG_SYS_NUM_FM1_DTSEC
+#undef CFG_SYS_NUM_FM2_DTSEC
+#define CFG_SYS_NUM_FM1_DTSEC	4
+#define CFG_SYS_NUM_FM2_DTSEC	4
 
 #define CORTINA_FW_ADDR_IFCNOR				0xefe00000
 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK		0xebf00000

diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
index b927dd8..f5af893 100644
--- a/board/freescale/t4rdb/tlb.c
+++ b/board/freescale/t4rdb/tlb.c

@@ -8,29 +8,29 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 512K SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+	SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_512K, 1),
 #else
@@ -40,81 +40,81 @@
 #endif
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 #ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+		      CFG_SYS_PCIE1_MEM_PHYS + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+		      CFG_SYS_PCIE1_MEM_PHYS + 0x50000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 11, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
 
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
-#ifdef CONFIG_SYS_NAND_BASE
+#ifdef CFG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+	SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
 		      MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 17, BOOKE_PAGESZ_4K, 1),
 #endif
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 18, BOOKE_PAGESZ_2G, 1)
 #endif

diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c
index 70e4dfc..9541972 100644
--- a/board/friendlyarm/nanopi2/board.c
+++ b/board/friendlyarm/nanopi2/board.c

@@ -507,7 +507,7 @@
 /* u-boot dram initialize */
 int dram_init(void)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 	return 0;
 }
 
@@ -518,10 +518,10 @@
 	unsigned int reg_val = readl(SCR_USER_SIG6_READ);
 
 	/* set global data memory */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x00000100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;
 
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size  = CONFIG_SYS_SDRAM_SIZE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size  = CFG_SYS_SDRAM_SIZE;
 
 	/* Number of Row: 14 bits */
 	if ((reg_val >> 28) == 14)

diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c
index c6eb11e..d9dfb25 100644
--- a/board/gardena/smart-gateway-at91sam/board.c
+++ b/board/gardena/smart-gateway-at91sam/board.c

@@ -45,15 +45,15 @@
 int board_init(void)
 {
 	/* Address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 
 	return 0;
 }

diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c
index 3ab6760..2807c4e 100644
--- a/board/gardena/smart-gateway-at91sam/spl.c
+++ b/board/gardena/smart-gateway-at91sam/spl.c

@@ -53,10 +53,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOCD);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */

diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c
index 47b8804..4fac146 100644
--- a/board/gdsys/mpc8308/sdram.c
+++ b/board/gdsys/mpc8308/sdram.c

@@ -34,39 +34,39 @@
 static long fixed_sdram(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_SDRAM_SIZE;
+	u32 msize = CFG_SYS_SDRAM_SIZE;
 	u32 msize_log2 = __ilog2(msize);
 
 	out_be32(&im->sysconf.ddrlaw[0].bar,
-		 CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
+		 CFG_SYS_SDRAM_BASE  & 0xfffff000);
 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
-	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+	out_be32(&im->sysconf.ddrcdr, CFG_SYS_DDRCDR_VALUE);
 
 	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
-	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+	out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
 
 	/* Currently we use only one CS, so disable the other bank. */
 	out_be32(&im->ddr.cs_config[1], 0);
 
-	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
-	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
-	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
-	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
-	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+	out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
 
-	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
-	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
-	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
-	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+	out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
 
-	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
 	sync();
 
 	/* enable DDR controller */
 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 	sync();
 
-	return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+	return get_ram_size(CFG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
index 6423c1e..b472ca5 100644
--- a/board/grinn/chiliboard/board.c
+++ b/board/grinn/chiliboard/board.c

@@ -95,7 +95,7 @@
 	hw_watchdog_init();
 #endif
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	gpmc_init();
 
 	return 0;

diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
index 5b245cb..8532225 100644
--- a/board/imgtec/boston/ddr.c
+++ b/board/imgtec/boston/ddr.c

@@ -27,7 +27,7 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
+	if (gd->ram_top < CFG_SYS_SDRAM_BASE) {
 		/* 2GB wrapped around to 0 */
 		return CKSEG0ADDR(256 << 20);
 	}

diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index bed2497..aa910bf 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S

@@ -118,7 +118,7 @@
 	/* setup basic address decode */
 	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
 	li	t1, 0x0
-	li	t2, -CONFIG_SYS_SDRAM_SIZE
+	li	t2, -CFG_SYS_SDRAM_SIZE
 	sw	t1, MSC01_BIU_MCBAS1L_OFS(t0)
 	sw	t2, MSC01_BIU_MCMSK1L_OFS(t0)
 	sw	t1, MSC01_BIU_MCBAS2L_OFS(t0)
@@ -168,7 +168,7 @@
 	sw	t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
 
 	/* setup PCI_BAR0 memory window */
-	li	t1, -CONFIG_SYS_SDRAM_SIZE
+	li	t1, -CFG_SYS_SDRAM_SIZE
 	sw	t1, MSC01_PCI_BAR0_OFS(t0)
 
 	/* setup PCI to SysCon/CPU translation */

diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 9853a0b..4a72ab5 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c

@@ -94,7 +94,7 @@
 
 int dram_init(void)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 
 	return 0;
 }

diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c
index 6a83637..7122692 100644
--- a/board/imgtec/xilfpga/xilfpga.c
+++ b/board/imgtec/xilfpga/xilfpga.c

@@ -19,7 +19,7 @@
 {
 	/* MIG IP block is smart and doesn't need SW
 	 * to do any init */
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;	/* in bytes */
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;	/* in bytes */
 
 	return 0;
 }

diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c
index 7dbb3a9..f3a0de3 100644
--- a/board/inversepath/usbarmory/usbarmory.c
+++ b/board/inversepath/usbarmory/usbarmory.c

@@ -412,7 +412,7 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 1 << 30);
 	return 0;
 }
 

diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c
index 02ae7df..5462a3d 100644
--- a/board/isee/igep003x/board.c
+++ b/board/isee/igep003x/board.c

@@ -185,7 +185,7 @@
  */
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	gpmc_init();
 

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 6c5e6fb..f159930 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c

@@ -82,7 +82,7 @@
 {
 	if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
 		struct onenand_chip *this = mtd->priv;
-		this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+		this->base = (void *)CFG_SYS_ONENAND_BASE;
 		return 0;
 	}
 	return 1;

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index c8138dc..0252ada 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c

@@ -52,7 +52,7 @@
 	char envval[16];
 	char *p;
 
-	pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+	pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size -
 		CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
 	sprintf(envval, "0x%x", pnvramaddr);
 	env_set("pnvramaddr", envval);
@@ -65,7 +65,7 @@
 		CONFIG_KM_PNVRAM) / 0x400;
 	env_set_ulong("pram", pram);
 
-	varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+	varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size -
 		CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
 	env_set_hex("varaddr", varaddr);
 	sprintf(envval, "0x%x", varaddr);

diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c
index 5401bdd..b433f69 100644
--- a/board/keymile/common/qrio.c
+++ b/board/keymile/common/qrio.c

@@ -20,7 +20,7 @@
 
 void show_qrio(void)
 {
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 	u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
 
 	printf("QRIO: id = %u, revision = %u\n",
@@ -33,7 +33,7 @@
 {
 	u8 slftest;
 
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	slftest = in_8(qrio_base + SLFTEST_OFF);
 
@@ -46,7 +46,7 @@
 {
 	u8 pgy_pres;
 
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	pgy_pres = in_8(qrio_base + BPRTH_OFF);
 
@@ -57,7 +57,7 @@
 {
 	u32 gprt;
 
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	gprt = in_be32(qrio_base + port_off + GPRT_OFF);
 
@@ -68,7 +68,7 @@
 {
 	u32 gprt, mask;
 
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	mask = 1U << gpio_nr;
 
@@ -85,7 +85,7 @@
 {
 	u32 direct, mask;
 
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	mask = 1U << gpio_nr;
 
@@ -100,7 +100,7 @@
 {
 	u32 direct, mask;
 
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	mask = 1U << gpio_nr;
 
@@ -113,7 +113,7 @@
 {
 	u32 direct, mask;
 
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	mask = 1U << gpio_nr;
 
@@ -133,7 +133,7 @@
 void qrio_wdmask(u8 bit, bool wden)
 {
 	u16 wdmask;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	wdmask = in_be16(qrio_base + WDMASK_OFF);
 
@@ -150,7 +150,7 @@
 void qrio_prst(u8 bit, bool en, bool wden)
 {
 	u16 prst;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	qrio_wdmask(bit, wden);
 
@@ -170,7 +170,7 @@
 {
 	unsigned long prstcfg;
 	u8 i;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
 
@@ -191,7 +191,7 @@
 void qrio_set_leds(void)
 {
 	u8 ctrlh;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	/* set UNIT LED to RED and BOOT LED to ON */
 	ctrlh = in_8(qrio_base + CTRLH_OFF);
@@ -205,7 +205,7 @@
 void qrio_enable_app_buffer(void)
 {
 	u8 ctrll;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	/* enable application buffer */
 	ctrll = in_8(qrio_base + CTRLL_OFF);
@@ -219,7 +219,7 @@
 void qrio_cpuwd_flag(bool flag)
 {
 	u8 reason1;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	reason1 = in_8(qrio_base + REASON1_OFF);
 	if (flag)
@@ -246,7 +246,7 @@
 bool qrio_reason_unitrst(void)
 {
 	u16 reason;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	reason = in_be16(qrio_base + REASON1_OFF);
 
@@ -258,7 +258,7 @@
 void qrio_uprstreq(u8 mode)
 {
 	u32 rstcfg;
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 
 	rstcfg = in_8(qrio_base + RSTCFG_OFF);
 
@@ -277,7 +277,7 @@
 
 ulong early_bootcount_load(void)
 {
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 	u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
 	u8 id = (id_rev >> 8) & 0xff;
 	u8 rev = id_rev & 0xff;
@@ -295,7 +295,7 @@
 
 void early_bootcount_store(ulong ebootcount)
 {
-	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
 	u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
 	u8 id = (id_rev >> 8) & 0xff;
 	u8 rev = id_rev & 0xff;

diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 6a7b848..88afc76 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c

@@ -40,7 +40,7 @@
 static int piggy_present(void)
 {
 	struct km_bec_fpga __iomem *base =
-		(struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+		(struct km_bec_fpga __iomem *)CFG_SYS_KMBEC_FPGA_BASE;
 
 	return in_8(&base->bprth) & PIGGY_PRESENT;
 }
@@ -53,7 +53,7 @@
 int board_early_init_r(void)
 {
 	struct km_bec_fpga *base =
-		(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+		(struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
 
 #if defined(CONFIG_ARCH_MPC8360)
 	unsigned short	svid;
@@ -126,26 +126,26 @@
 	u32 ddr_size_log2;
 
 	out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
-	out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
-	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
-	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
-	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
-	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
-	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
-	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
-	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
-	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
-	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
-	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+	out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f);
+	out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
+	out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
+	out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
+	out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
+	out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL);
 	udelay(200);
 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 
 	disable_addr_trans();
-	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+	msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
 	enable_addr_trans();
 	msize /= (1024 * 1024);
-	if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) {
+	if (CFG_SYS_SDRAM_SIZE >> 20 != msize) {
 		for (ddr_size = msize << 20, ddr_size_log2 = 0;
 			(ddr_size > 1);
 			ddr_size = ddr_size >> 1, ddr_size_log2++)
@@ -169,7 +169,7 @@
 		return -ENXIO;
 
 	out_be32(&im->sysconf.ddrlaw[0].bar,
-		CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
+		CFG_SYS_SDRAM_BASE & LAWBAR_BAR);
 	msize = fixed_sdram();
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
@@ -215,7 +215,7 @@
 {
 	int testpin = 0;
 	struct km_bec_fpga *base =
-		(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+		(struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
 	int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
 	testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
 	debug("post_hotkeys_pressed: %d\n", !testpin);

diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c
index 6a17110..9f68c21 100644
--- a/board/keymile/kmcent2/kmcent2.c
+++ b/board/keymile/kmcent2/kmcent2.c

@@ -44,7 +44,7 @@
 
 int board_early_init_f(void)
 {
-	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
 	bool cpuwd_flag = false;
 
@@ -141,7 +141,7 @@
 {
 	int ret = 0;
 
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const unsigned int flashbase = CFG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
 	/*
@@ -162,7 +162,7 @@
 		disable_tlb(flash_esel);
 	}
 
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+	set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 

diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c
index aa0f29f..ec3bb8f 100644
--- a/board/keymile/kmcent2/law.c
+++ b/board/keymile/kmcent2/law.c

@@ -10,12 +10,12 @@
 #include <asm/fsl_law.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+	SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+	SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+	SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CFG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 	SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
 /* other application LAW are not used in u-boot */
 };

diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c
index dbd3b9b..41b24e3 100644
--- a/board/keymile/kmcent2/tlb.c
+++ b/board/keymile/kmcent2/tlb.c

@@ -11,20 +11,20 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -35,56 +35,56 @@
 		      0, 0, BOOKE_PAGESZ_4K, 1),
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
 		      0, 2, BOOKE_PAGESZ_128M, 1),
 
 	/* *I*G* - PCI1 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI1 I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 6, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 8, BOOKE_PAGESZ_16M, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 9, BOOKE_PAGESZ_4M, 1),
 
 	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 	/* QRIO */
-	SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_QRIO_BASE, CFG_SYS_QRIO_BASE_PHYS,
 		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 11, BOOKE_PAGESZ_64K, 1),
 	/* MRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
 		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 12, BOOKE_PAGESZ_128M, 1),
 	/* BFTIC */
@@ -96,7 +96,7 @@
 	 * in cpu_init_f, so do not use them here!!.
 	 */
 	/* PAXE */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
 		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 16, BOOKE_PAGESZ_128M, 1)
 };

diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c
index 4ec60f1..556d39d 100644
--- a/board/keymile/pg-wcom-ls102xa/ddr.c
+++ b/board/keymile/pg-wcom-ls102xa/ddr.c

@@ -84,7 +84,7 @@
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	return 0;

diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
index 3719bcf..e005ece 100644
--- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c

@@ -52,7 +52,7 @@
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
-	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+	struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
 
 	/* Disable unused MCK1 */
 	setbits_be32(&gur->ddrclkdr, 2);
@@ -184,7 +184,7 @@
 {
 	/* Define only 1MiB range for mem_regions at the middle of the RAM */
 	/* For 1GiB range mem_regions takes approx. 4min */
-	*vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
+	*vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
 	*size = 1 << 20;
 	return 0;
 }

diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
index d47c7b5..b3c176d 100644
--- a/board/l+g/vinco/vinco.c
+++ b/board/l+g/vinco/vinco.c

@@ -164,7 +164,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #if !CONFIG_IS_ENABLED(DM_SPI)
 	vinco_spi0_hw_init();
@@ -188,8 +188,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c
index 0504d61..ff233e9 100644
--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c

@@ -14,7 +14,7 @@
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	return 0;
 }
 

diff --git a/board/mediatek/mt7623/mt7623_rfb.c b/board/mediatek/mt7623/mt7623_rfb.c
index 755e879..ec10f77 100644
--- a/board/mediatek/mt7623/mt7623_rfb.c
+++ b/board/mediatek/mt7623/mt7623_rfb.c

@@ -12,7 +12,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/board/mediatek/mt7629/mt7629_rfb.c b/board/mediatek/mt7629/mt7629_rfb.c
index d1bca6d..55f7696 100644
--- a/board/mediatek/mt7629/mt7629_rfb.c
+++ b/board/mediatek/mt7629/mt7629_rfb.c

@@ -11,7 +11,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c
index fce5de6..2490b15 100644
--- a/board/mediatek/mt8518/mt8518_ap1.c
+++ b/board/mediatek/mt8518/mt8518_ap1.c

@@ -14,7 +14,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	debug("gd->fdt_blob is %p\n", gd->fdt_blob);
 	return 0;

diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
index 6abf08b..84b95be 100644
--- a/board/mscc/jr2/jr2.c
+++ b/board/mscc/jr2/jr2.c

@@ -28,7 +28,7 @@
 			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
 
 	/* Address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
 
 	return 0;
 }

diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
index 76e3f2e..48170b3 100644
--- a/board/mscc/luton/luton.c
+++ b/board/mscc/luton/luton.c

@@ -29,7 +29,7 @@
 	writel(0, BASE_CFG + ICPU_SW_MODE);
 
 	/* Address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
 
 	return 0;
 }

diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 2a75ec2..f261346 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c

@@ -77,7 +77,7 @@
 			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
 
 	/* Address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
 
 	return 0;
 }

diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c
index 87e7907..99d5f5b 100644
--- a/board/mscc/serval/serval.c
+++ b/board/mscc/serval/serval.c

@@ -22,7 +22,7 @@
 	writel(0, BASE_CFG + ICPU_SW_MODE);
 
 	/* Address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
 
 	return 0;
 }

diff --git a/board/mscc/servalt/servalt.c b/board/mscc/servalt/servalt.c
index bd8c7e8..4999316 100644
--- a/board/mscc/servalt/servalt.c
+++ b/board/mscc/servalt/servalt.c

@@ -22,7 +22,7 @@
 	writel(0, BASE_CFG + ICPU_SW_MODE);
 
 	/* Address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
 
 	return 0;
 }

diff --git a/board/nokia/rx51/Kconfig b/board/nokia/rx51/Kconfig
index 7cf0507..c884543 100644
--- a/board/nokia/rx51/Kconfig
+++ b/board/nokia/rx51/Kconfig

@@ -1,5 +1,35 @@
 if TARGET_NOKIA_RX51
 
+config USB_DEVICE
+	def_bool y
+	help
+	  Legacy UDC device support
+
+config USB_TTY
+	def_bool y
+	help
+	  Legacy tty type of device available to talk to the UDC device
+
+config USBD_VENDORID
+	hex
+	default 0x0421
+
+config USBD_PRODUCTID_CDCACM
+	hex
+	default 0x01c8
+
+config USBD_PRODUCTID_GSERIAL
+	hex
+	default 0x01c8
+
+config USBD_MANUFACTURER
+	string
+	default "Nokia"
+
+config USBD_PRODUCT_NAME
+	string
+	default "N900 (U-Boot)"
+
 config NR_DRAM_BANKS
 	default 2
 

diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index c1b4b91..238b963 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c

@@ -232,7 +232,7 @@
 	gpmc_init();
 #if defined(CONFIG_CMD_ONENAND)
 	enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0],
-			      CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M);
+			      CFG_SYS_ONENAND_BASE, GPMC_SIZE_256M);
 #endif
 	/* Enable the clks & power */
 	per_clocks_enable();
@@ -795,9 +795,9 @@
 };
 
 static const struct ns16550_plat rx51_serial = {
-	.base = CONFIG_SYS_NS16550_COM3,
+	.base = CFG_SYS_NS16550_COM3,
 	.reg_shift = 2,
-	.clock = CONFIG_SYS_NS16550_CLK,
+	.clock = CFG_SYS_NS16550_CLK,
 	.fcr = UART_FCR_DEFVAL,
 };
 

diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c
index d97ebd0..e84dd25 100644
--- a/board/phytec/phycore_am335x_r2/board.c
+++ b/board/phytec/phycore_am335x_r2/board.c

@@ -166,7 +166,7 @@
 		   0);
 
 	/* Detect memory physically present */
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
 
 	/* Reconfigure memory for actual detected size */
@@ -269,7 +269,7 @@
  */
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	return 0;
 }
 

diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c
index 4fbe1e5..75d2636 100644
--- a/board/phytium/pomelo/pomelo.c
+++ b/board/phytium/pomelo/pomelo.c

@@ -24,7 +24,7 @@
 	ddr_init();
 
 	gd->mem_clk = 0;
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000);
 
 	sec_init();
 	debug("PBF relocate done\n");

diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 3b60afc..85fbaf0 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c

@@ -70,7 +70,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	/* Force ethernet PHY out of reset */
 	gpio_request(ETHERNET_PHY_RESET, "phy_reset");

diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index a365269..ea09057 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c

@@ -312,7 +312,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }

diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 6197e54..2d1435a 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c

@@ -78,7 +78,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	/* Force ethernet PHY out of reset */
 	gpio_request(ETHERNET_PHY_RESET, "phy_reset");

diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c
index 199ec4a..f609e4f 100644
--- a/board/renesas/grpeach/grpeach.c
+++ b/board/renesas/grpeach/grpeach.c

@@ -20,7 +20,7 @@
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+	gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
 
 	return 0;
 }

diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index 87607df..c3ebcd3 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c

@@ -80,7 +80,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	/* Force ethernet PHY out of reset */
 	gpio_request(ETHERNET_PHY_RESET, "phy_reset");

diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 8e24ac0..1437875 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c

@@ -89,7 +89,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	/* Force ethernet PHY out of reset */
 	gpio_request(ETHERNET_PHY_RESET, "phy_reset");

diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c
index 1a3a4c1..db1fb4b 100644
--- a/board/renesas/porter/porter.c
+++ b/board/renesas/porter/porter.c

@@ -78,7 +78,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	/* Force ethernet PHY out of reset */
 	gpio_request(ETHERNET_PHY_RESET, "phy_reset");

diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
index 4558070..6ecebfe 100644
--- a/board/renesas/silk/silk.c
+++ b/board/renesas/silk/silk.c

@@ -71,7 +71,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	/* Force ethernet PHY out of reset */
 	gpio_request(ETHERNET_PHY_RESET, "phy_reset");

diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c
index 56bdb34..f069ecc 100644
--- a/board/renesas/stout/stout.c
+++ b/board/renesas/stout/stout.c

@@ -88,7 +88,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	cpld_init();
 

diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index fe52c7c..07febe6 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c

@@ -66,10 +66,10 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Configure RDY/BSY */
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
 	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */

diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 84926cd..76f62dd 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c

@@ -62,10 +62,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 

diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 8d5825c..c56582a 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c

@@ -65,13 +65,13 @@
 
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 	/* Configure RDY/BSY */
-	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+	gpio_direction_input(CFG_SYS_NAND_READY_PIN);
 #endif
 
 	/* Enable NandFlash */
-	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
@@ -126,7 +126,7 @@
 	/* arch number of AT91SAM9M10G45EK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_CMD_NAND
 	pm9g45_nand_hw_init();
@@ -141,15 +141,15 @@
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
 
 	return 0;
 }

diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 5320c1f..a992dc6 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c

@@ -46,7 +46,7 @@
 	u32 addr;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 	}
 	return 0;
@@ -64,7 +64,7 @@
 	u32 addr, size;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 
 		gd->bd->bi_dram[i].start = addr;

diff --git a/board/samsung/common/Kconfig b/board/samsung/common/Kconfig
new file mode 100644
index 0000000..849aeff
--- /dev/null
+++ b/board/samsung/common/Kconfig

@@ -0,0 +1,2 @@
+config MISC_COMMON
+	bool

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 943b498..16ce5cb 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c

@@ -122,7 +122,7 @@
 	unsigned long addr;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 	}
 	return 0;
@@ -134,7 +134,7 @@
 	unsigned long addr, size;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 
 		gd->bd->bi_dram[i].start = addr;

diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c
index 9f21795..c67c107 100644
--- a/board/samsung/goni/onenand.c
+++ b/board/samsung/goni/onenand.c

@@ -14,7 +14,7 @@
 {
 	struct onenand_chip *this = mtd->priv;
 
-	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+	this->base = (void *)CFG_SYS_ONENAND_BASE;
 	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
 	this->chip_probe = s5pc110_chip_probe;
 

diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c
index 37e911c..265a2cd 100644
--- a/board/samsung/universal_c210/onenand.c
+++ b/board/samsung/universal_c210/onenand.c

@@ -13,7 +13,7 @@
 {
 	struct onenand_chip *this = mtd->priv;
 
-	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+	this->base = (void *)CFG_SYS_ONENAND_BASE;
 	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
 	this->chip_probe = s5pc210_chip_probe;
 

diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index 4c655df..8b953f9 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c

@@ -115,7 +115,7 @@
 
 int dram_init(void)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 	return 0;
 }
 
@@ -173,7 +173,7 @@
 int init_addr_map(void)
 {
 	if (IS_ENABLED(CONFIG_ADDR_MAP))
-		addrmap_set_entry(0, 0, CONFIG_SYS_SDRAM_SIZE, 0);
+		addrmap_set_entry(0, 0, CFG_SYS_SDRAM_SIZE, 0);
 
 	return 0;
 }

diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 85025f2..2efede6 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c

@@ -85,7 +85,7 @@
 #ifdef CONFIG_MACH_TYPE
 	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
 #endif
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_FACTORYSET
 	factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR);

diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index 90fece7..569b86d 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c

@@ -40,8 +40,8 @@
 
 static void corvus_request_gpio(void)
 {
-	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
-	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
 	gpio_request(AT91_PIN_PD7, "d0");
 	gpio_request(AT91_PIN_PD8, "d1");
 	gpio_request(AT91_PIN_PA12, "d2");
@@ -110,8 +110,8 @@
 	at91_periph_clk_enable(ATMEL_ID_PIOA);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 }
 
 #if defined(CONFIG_SPL_BUILD)
@@ -262,7 +262,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	/* we have to request the gpios again after relocation */
 	corvus_request_gpio();
@@ -287,8 +287,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index b965ae9..8f4b0ea 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c

@@ -146,7 +146,7 @@
 	dram_init();
 
 	/* Bank 0 declares the memory available in the DDR low region */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 
 	/* Bank 1 declares the memory available in the DDR high region */

diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
index d500a62..15044c7 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c

@@ -42,8 +42,8 @@
 
 static void smartweb_request_gpio(void)
 {
-	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
-	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
 	gpio_request(AT91_PIN_PA26, "ena PHY");
 }
 
@@ -72,10 +72,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 
 static void smartweb_macb_hw_init(void)
@@ -167,7 +167,7 @@
 #endif
 
 	/* Adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	smartweb_nand_hw_init();
 	smartweb_macb_hw_init();
@@ -177,8 +177,8 @@
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size(
-		(void *)CONFIG_SYS_SDRAM_BASE,
-		CONFIG_SYS_SDRAM_SIZE);
+		(void *)CFG_SYS_SDRAM_BASE,
+		CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 
@@ -246,7 +246,7 @@
 
 	setting.cr = SDRAM_BASE_CONF;
 	setting.mdr = AT91_SDRAMC_MD_SDRAM;
-	setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+	setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
 
 	/*
 	 * I write here directly in this register, because this

diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 6c44afb..ad44a7c 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c

@@ -41,8 +41,8 @@
 
 static void taurus_request_gpio(void)
 {
-	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
-	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
 	gpio_request(AT91_PIN_PA25, "ena PHY");
 }
 
@@ -73,10 +73,10 @@
 	       &smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
 }
 
 #if defined(CONFIG_SPL_BUILD)
@@ -149,7 +149,7 @@
 		} else {
 			puts("erase spi flash sector 0\n");
 			spi_flash_erase(flash, 0,
-					CONFIG_SYS_NAND_U_BOOT_SIZE);
+					CFG_SYS_NAND_U_BOOT_SIZE);
 		}
 	}
 }
@@ -168,7 +168,7 @@
 	at91_sdram_hw_init();
 	setting.cr = SDRAM_BASE_CONF | mask;
 	setting.mdr = AT91_SDRAMC_MD_SDRAM;
-	setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+	setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
 
 	writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
 		AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
@@ -185,8 +185,8 @@
 	sdramc_configure(AT91_SDRAMC_NC_10);
 
 	/* Do memtest for 128MB */
-	ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				CONFIG_SYS_SDRAM_SIZE);
+	ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				CFG_SYS_SDRAM_SIZE);
 
 	/*
 	 * If 32MB or 16MB should be supported check also for
@@ -306,7 +306,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	taurus_request_gpio();
 #ifdef CONFIG_CMD_NAND
@@ -326,8 +326,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 	return 0;
 }
 

diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c
index a218278..79e492f 100644
--- a/board/sipeed/maix/maix.c
+++ b/board/sipeed/maix/maix.c

@@ -11,7 +11,7 @@
 
 phys_size_t get_effective_memsize(void)
 {
-	return CONFIG_SYS_SDRAM_SIZE;
+	return CFG_SYS_SDRAM_SIZE;
 }
 
 static int sram_init(void)

diff --git a/board/socrates/law.c b/board/socrates/law.c
index 840941b..e4427ec 100644
--- a/board/socrates/law.c
+++ b/board/socrates/law.c

@@ -30,12 +30,12 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#if defined(CONFIG_SYS_FPGA_BASE)
-	SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW(CFG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#if defined(CFG_SYS_FPGA_BASE)
+	SET_LAW(CFG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
-	SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 9b7ffee..b1e38c5 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 
-#if defined(CONFIG_SYS_NAND_BASE)
+#if defined(CFG_SYS_NAND_BASE)
 #include <nand.h>
 #include <linux/errno.h>
 #include <linux/mtd/rawnand.h>

diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 04527cf..61402a5 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c

@@ -34,35 +34,35 @@
 	ddr->cs0_config = 0;
 	ddr->sdram_cfg = 0;
 
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
+	ddr->cs0_bnds = CFG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_SYS_DDR_MODE;
+	ddr->sdram_interval = CFG_SYS_DDR_INTERVAL;
+	ddr->sdram_cfg_2 = CFG_SYS_DDR_CONFIG_2;
+	ddr->sdram_clk_cntl = CFG_SYS_DDR_CLK_CONTROL;
 
 	asm ("sync;isync;msync");
 	udelay(1000);
 
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
+	ddr->sdram_cfg = CFG_SYS_DDR_CONFIG;
 	asm ("sync; isync; msync");
 	udelay(1000);
 
-	if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
+	if (get_ram_size(0, CFG_SYS_SDRAM_SIZE<<20) == CFG_SYS_SDRAM_SIZE<<20) {
 		/*
 		 * OK, size detected -> all done
 		 */
-		return CONFIG_SYS_SDRAM_SIZE<<20;
+		return CFG_SYS_SDRAM_SIZE<<20;
 	}
 
 	return 0;				/* nothing found !		*/
 }
 #endif
 
-#if defined(CONFIG_SYS_DRAM_TEST)
+#if defined(CFG_SYS_DRAM_TEST)
 int testdram(void)
 {
 	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;

diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index eaba875..9c4dd18 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c

@@ -83,7 +83,7 @@
 	/*
 	 * Check if boot FLASH isn't max size
 	 */
-	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
+	if (gd->bd->bi_flashsize < (0 - CFG_SYS_FLASH0)) {
 		set_lbc_or(0, gd->bd->bi_flashstart |
 			   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
 		set_lbc_br(0, gd->bd->bi_flashstart |
@@ -98,7 +98,7 @@
 	/*
 	 * Check if only one FLASH bank is available
 	 */
-	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
+	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CFG_SYS_FLASH0)) {
 		set_lbc_or(1, 0);
 		set_lbc_br(1, 0);
 
@@ -143,7 +143,7 @@
 	sys_info_t sysinfo;
 	uint clkdiv;
 	uint lbc_mhz;
-	uint lcrr = CONFIG_SYS_LBC_LCRR;
+	uint lcrr = CFG_SYS_LBC_LCRR;
 
 	get_sys_info (&sysinfo);
 	clkdiv = lbc->lcrr & LCRR_CLKDIV;
@@ -204,8 +204,8 @@
 	/* Fixup FPGA mapping */
 	val[i++] = 3;				/* chip select number */
 	val[i++] = 0;				/* always 0 */
-	val[i++] = CONFIG_SYS_FPGA_BASE;
-	val[i++] = CONFIG_SYS_FPGA_SIZE;
+	val[i++] = CFG_SYS_FPGA_BASE;
+	val[i++] = CFG_SYS_FPGA_SIZE;
 
 	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
 				  val, i * sizeof(u32), 1);

diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index de80c3c..631f6c3 100644
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c

@@ -14,16 +14,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -33,7 +33,7 @@
 	 * 0xfc000000	64M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_64M, 1),
 
@@ -41,7 +41,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS, CFG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -49,16 +49,16 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, CFG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
-#if defined(CONFIG_SYS_FPGA_BASE)
+#if defined(CFG_SYS_FPGA_BASE)
 	/*
 	 * TLB 4:	1M	Non-cacheable, guarded
 	 * 0xc0000000	1M	FPGA and NAND
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_FPGA_BASE, CFG_SYS_FPGA_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_1M, 1),
 #endif
@@ -70,7 +70,7 @@
 	 * (0xcbfc0000	256K	LIME GDC MMIO)
 	 * MMIO is relocatable and could be at 0xcbfc0000
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_LIME_BASE, CFG_SYS_LIME_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -79,7 +79,7 @@
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe200_0000	16M	PCI1 IO
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -91,11 +91,11 @@
 	 * Make sure the TLB count at the top of this table is correct.
 	 * Likely it needs to be increased by two for these entries.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, CFG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 8, BOOKE_PAGESZ_256M, 1),
 #endif

diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c
index 2299227..b3f9550 100644
--- a/board/softing/vining_fpga/socfpga.c
+++ b/board/softing/vining_fpga/socfpga.c

@@ -30,7 +30,7 @@
 	status_led_set(2, CONFIG_LED_STATUS_ON);
 
 	/* Address of boot parameters for ATAG (if ATAG is used) */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 	ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
 	if (!ret)

diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 8e80ca6..7c44379 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c

@@ -107,7 +107,7 @@
 {
 	u32 max_size = imx_ddr_size();
 
-	gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size_stride_test((u32 *) CFG_SYS_SDRAM_BASE,
 						(u32)max_size);
 
 	return 0;
@@ -288,7 +288,7 @@
 	int ret = 0;
 
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_VIDEO_IPUV3
 	ret = setup_display();

diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
index beab4e9..429f886 100644
--- a/board/sysam/amcore/amcore.c
+++ b/board/sysam/amcore/amcore.c

@@ -77,7 +77,7 @@
 	 * DCR
 	 * set proper  RC as per specification
 	 */
-	RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
+	RC = (CFG_SYS_CPU_CLK / 1000000) >> 1;
 	RC = (RC * 15) >> 4;
 
 	/* 0x8000 is the faster option */
@@ -88,7 +88,7 @@
 	 */
 	out_be32(&dc->dacr0, 0x00003304);
 
-	dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
+	dramsize = ((CFG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
 	out_be32(&dc->dmr0,  dramsize|1);
 
 	/* issue a PRECHARGE ALL */
@@ -102,8 +102,8 @@
 	out_be32(&dc->dacr0, 0x0000b344);
 	out_be32((u32 *)0x00000c00, 0xbeaddeed);
 
-	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size(CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 
 	return 0;
 }

diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c
index d48da48..475e3ed 100644
--- a/board/sysam/stmark2/stmark2.c
+++ b/board/sysam/stmark2/stmark2.c

@@ -35,7 +35,7 @@
 	 * Serial Boot: The dram is already initialized in start.S
 	 * only require to return DRAM size
 	 */
-	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
 
 	gd->ram_size = dramsize;
 

diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index 3a447ca..8d9eedb 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c

@@ -144,7 +144,7 @@
 int board_init(void)
 {
 	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_VIDEO_IPUV3
 	setup_display();

diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c
index b7ddc3b..839a692 100644
--- a/board/tcl/sl50/board.c
+++ b/board/tcl/sl50/board.c

@@ -238,7 +238,7 @@
 	hw_watchdog_init();
 #endif
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	return 0;
 }
 

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index b97fedd..9e58281 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c

@@ -704,7 +704,7 @@
 	hw_watchdog_init();
 #endif
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
 	gpmc_init();
 #endif

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 529129e..d0b7a14 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c

@@ -639,7 +639,7 @@
 	u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 	    modena_init0_bw_integer, modena_init0_watermark_0;
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	gpmc_init();
 
 	/*

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index cfc825e..652c40f 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c

@@ -661,7 +661,7 @@
 int board_init(void)
 {
 	gpmc_init();
-	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+	gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
 
 	return 0;
 }

diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 34ec391..b266ccb 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c

@@ -75,13 +75,13 @@
 int dram_init_banksize(void)
 {
 	/* Bank 0 declares the memory available in the DDR low region */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = 0x80000000;
 	gd->ram_size = 0x80000000;
 
 #ifdef CONFIG_PHYS_64BIT
 	/* Bank 1 declares the memory available in the DDR high region */
-	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+	gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
 	gd->bd->bi_dram[1].size = 0x80000000;
 	gd->ram_size = 0x100000000;
 #endif

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index a854d61..1c00e25 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c

@@ -644,7 +644,7 @@
 
 	ram_size = board_ti_get_emif_size();
 
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
 	if (ram_size > CONFIG_MAX_MEM_MAPPED) {
 		gd->bd->bi_dram[1].start = 0x200000000;

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index d6e431e..d4e672a 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c

@@ -71,13 +71,13 @@
 int dram_init_banksize(void)
 {
 	/* Bank 0 declares the memory available in the DDR low region */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = 0x80000000;
 	gd->ram_size = 0x80000000;
 
 #ifdef CONFIG_PHYS_64BIT
 	/* Bank 1 declares the memory available in the DDR high region */
-	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+	gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
 	gd->bd->bi_dram[1].size = 0x80000000;
 	gd->ram_size = 0x100000000;
 #endif

diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index e09adc8..4d28582 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c

@@ -60,13 +60,13 @@
 int dram_init_banksize(void)
 {
 	/* Bank 0 declares the memory available in the DDR low region */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = 0x7fffffff;
 	gd->ram_size = 0x80000000;
 
 #ifdef CONFIG_PHYS_64BIT
 	/* Bank 1 declares the memory available in the DDR high region */
-	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+	gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
 	gd->bd->bi_dram[1].size = 0x37fffffff;
 	gd->ram_size = 0x400000000;
 #endif

diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 51e8de4..1683f78 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c

@@ -46,7 +46,7 @@
 
 	ddr3_size = ddr3_init();
 
-	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
 #if defined(CONFIG_TI_AEMIF)
 	if (!(board_is_k2g_ice() || board_is_k2g_i1()))
@@ -71,7 +71,7 @@
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 	return 0;
 }
 
@@ -120,8 +120,8 @@
 
 	/* adjust memory start address for LPAE */
 	if (lpae) {
-		start[0] -= CONFIG_SYS_SDRAM_BASE;
-		start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
+		start[0] -= CFG_SYS_SDRAM_BASE;
+		start[0] += CFG_SYS_LPAE_SDRAM_BASE;
 	}
 
 	if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
@@ -174,12 +174,12 @@
 					    "linux,initrd-end", NULL);
 			if (prop1 && prop2) {
 				initrd_start = __be64_to_cpu(*prop1);
-				initrd_start -= CONFIG_SYS_SDRAM_BASE;
-				initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
+				initrd_start -= CFG_SYS_SDRAM_BASE;
+				initrd_start += CFG_SYS_LPAE_SDRAM_BASE;
 				initrd_start = __cpu_to_be64(initrd_start);
 				initrd_end = __be64_to_cpu(*prop2);
-				initrd_end -= CONFIG_SYS_SDRAM_BASE;
-				initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
+				initrd_end -= CFG_SYS_SDRAM_BASE;
+				initrd_end += CFG_SYS_LPAE_SDRAM_BASE;
 				initrd_end = __cpu_to_be64(initrd_end);
 
 				err = fdt_delprop(blob, nodeoffset,
@@ -221,9 +221,9 @@
 			*reserve_start = __cpu_to_be64(*reserve_start);
 			size = __cpu_to_be64(*(reserve_start + 1));
 			if (size) {
-				*reserve_start -= CONFIG_SYS_SDRAM_BASE;
+				*reserve_start -= CFG_SYS_SDRAM_BASE;
 				*reserve_start +=
-					CONFIG_SYS_LPAE_SDRAM_BASE;
+					CFG_SYS_LPAE_SDRAM_BASE;
 				*reserve_start =
 					__cpu_to_be64(*reserve_start);
 			} else {

diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 929668e..09cbd6b 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c

@@ -146,7 +146,7 @@
 	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
 	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 
-	tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
+	tca642x_set_inital_state(CFG_SYS_I2C_TCA642X_ADDR, tca642x_init);
 
 	return 0;
 }

diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index 2d42af6..8c70835 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c

@@ -27,7 +27,7 @@
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 #if defined(CONFIG_MTD_RAW_NAND)
 	gpmc_init();
 #endif

diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
index 9d4ffb0..efef855 100644
--- a/board/timll/devkit3250/devkit3250.c
+++ b/board/timll/devkit3250/devkit3250.c

@@ -56,7 +56,7 @@
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params  = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params  = CFG_SYS_SDRAM_BASE + 0x100;
 
 #ifdef CONFIG_SYS_FLASH_CFI
 	/* Use 16-bit memory interface for NOR Flash */
@@ -76,8 +76,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 
 	return 0;
 }

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 96d0185..3c7cfa3 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c

@@ -79,7 +79,7 @@
 int dram_init(void)
 {
 	/* use the DDR controllers configured size */
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
 				    (ulong)imx_ddr_size());
 
 	return 0;

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 475250d..65e0e9a 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c

@@ -73,7 +73,7 @@
 int dram_init(void)
 {
 	/* use the DDR controllers configured size */
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
 				    (ulong)imx_ddr_size());
 
 	return 0;

diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index 07fe454..f335d5b 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c

@@ -266,7 +266,7 @@
 	hw_watchdog_init();
 #endif
 
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
 	gpmc_init();
 #endif

diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c
index 5d12f84..c8e791a 100644
--- a/board/work-microwave/work_92105/work_92105.c
+++ b/board/work-microwave/work_92105/work_92105.c

@@ -67,15 +67,15 @@
 {
 	reset_periph();
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params  = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gd->bd->bi_boot_params  = CFG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 
 	return 0;
 }

diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
index 9d92103..bc7e5c5 100644
--- a/board/xes/common/fsl_8xxx_misc.c
+++ b/board/xes/common/fsl_8xxx_misc.c

@@ -13,7 +13,7 @@
  */
 int board_flash_wp_on(void)
 {
-	if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+	if (pca953x_get_val(CFG_SYS_I2C_PCA953X_ADDR0) &
 			CONFIG_SYS_PCA953X_NVM_WP)
 		return 1;
 
@@ -30,7 +30,7 @@
 #if defined(CONFIG_MPC85xx)
        volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
 #elif defined(CONFIG_MPC86xx)
-       volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+       volatile immap_t *immap = (immap_t *)CFG_SYS_CCSRBAR;
        volatile ccsr_gur_t *gur = &immap->im_gur;
 #endif
 

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 17ee541..df4c457 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c

@@ -105,7 +105,7 @@
 	return board_late_init_xilinx();
 }
 
-#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
 int dram_init_banksize(void)
 {
 	return fdtdec_setup_memory_banksize();
@@ -123,8 +123,8 @@
 #else
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 
 	zynq_ddrc_init();
 

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 579708d..e3f70c4 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c

@@ -236,7 +236,7 @@
 	return ret;
 }
 
-#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
 int dram_init_banksize(void)
 {
 	int ret;
@@ -261,7 +261,7 @@
 #else
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
 
 	mem_map_fill();
@@ -271,8 +271,8 @@
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+				    CFG_SYS_SDRAM_SIZE);
 
 	return 0;
 }

diff --git a/boot/Kconfig b/boot/Kconfig
index 4a001bc..668270c 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig

@@ -654,7 +654,7 @@
 	default TEXT_BASE
 	help
 	  The physical start address of boot monitor code (which is the same as
-	  CONFIG_TEXT_BASE when linking) and the same as CONFIG_SYS_FLASH_BASE
+	  CONFIG_TEXT_BASE when linking) and the same as CFG_SYS_FLASH_BASE
 	  when booting from flash.
 
 config SPL_SYS_MONITOR_BASE

diff --git a/boot/image-board.c b/boot/image-board.c
index 34d1e5f..0fd6329 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c

@@ -116,8 +116,8 @@
 		return tmp;
 	}
 
-#if defined(CONFIG_SYS_SDRAM_BASE)
-	return CONFIG_SYS_SDRAM_BASE;
+#if defined(CFG_SYS_SDRAM_BASE)
+	return CFG_SYS_SDRAM_BASE;
 #elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV)
 	return gd->bd->bi_dram[0].start;
 #else
@@ -161,8 +161,8 @@
 		return tmp;
 	}
 
-#if defined(CONFIG_SYS_BOOTMAPSZ)
-	return CONFIG_SYS_BOOTMAPSZ;
+#if defined(CFG_SYS_BOOTMAPSZ)
+	return CFG_SYS_BOOTMAPSZ;
 #else
 	return env_get_bootm_size();
 #endif

diff --git a/cmd/date.c b/cmd/date.c
index 0e2dfbc..58505e6 100644
--- a/cmd/date.c
+++ b/cmd/date.c

@@ -51,10 +51,10 @@
 	}
 #elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 	old_bus = i2c_get_bus_num();
-	i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
+	i2c_set_bus_num(CFG_SYS_RTC_BUS_NUM);
 #else
 	old_bus = I2C_GET_BUS();
-	I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM);
+	I2C_SET_BUS(CFG_SYS_RTC_BUS_NUM);
 #endif
 
 	switch (argc) {

diff --git a/cmd/i2c.c b/cmd/i2c.c
index e196a73..da8b4c2 100644
--- a/cmd/i2c.c
+++ b/cmd/i2c.c

@@ -97,19 +97,19 @@
  * When multiple buses are present, the list is an array of bus-address
  * pairs.  The following macros take care of this */
 
-#if defined(CONFIG_SYS_I2C_NOPROBES)
+#if defined(CFG_SYS_I2C_NOPROBES)
 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
 static struct
 {
 	uchar	bus;
 	uchar	addr;
-} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
+} i2c_no_probes[] = CFG_SYS_I2C_NOPROBES;
 #define GET_BUS_NUM	i2c_get_bus_num()
 #define COMPARE_BUS(b,i)	(i2c_no_probes[(i)].bus == (b))
 #define COMPARE_ADDR(a,i)	(i2c_no_probes[(i)].addr == (a))
 #define NO_PROBE_ADDR(i)	i2c_no_probes[(i)].addr
 #else		/* single bus */
-static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
+static uchar i2c_no_probes[] = CFG_SYS_I2C_NOPROBES;
 #define GET_BUS_NUM	0
 #define COMPARE_BUS(b,i)	((b) == 0)	/* Make compiler happy */
 #define COMPARE_ADDR(a,i)	(i2c_no_probes[(i)] == (a))
@@ -912,7 +912,7 @@
 	int j;
 	int addr = -1;
 	int found = 0;
-#if defined(CONFIG_SYS_I2C_NOPROBES)
+#if defined(CFG_SYS_I2C_NOPROBES)
 	int k, skip;
 	unsigned int bus = GET_BUS_NUM;
 #endif	/* NOPROBES */
@@ -932,7 +932,7 @@
 		if ((0 <= addr) && (j != addr))
 			continue;
 
-#if defined(CONFIG_SYS_I2C_NOPROBES)
+#if defined(CFG_SYS_I2C_NOPROBES)
 		skip = 0;
 		for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
 			if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
@@ -955,7 +955,7 @@
 	}
 	putc ('\n');
 
-#if defined(CONFIG_SYS_I2C_NOPROBES)
+#if defined(CFG_SYS_I2C_NOPROBES)
 	puts ("Excluded chip addresses:");
 	for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
 		if (COMPARE_BUS(bus,k))
@@ -1697,12 +1697,12 @@
 #else
 		int i;
 
-		for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
+		for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) {
 			printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 			int j;
 
-			for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
+			for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
 				if (i2c_bus[i].next_hop[j].chip == 0)
 					break;
 				printf("->%s@0x%2x:%d",
@@ -1730,14 +1730,14 @@
 		}
 		show_bus(bus);
 #else
-		if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
+		if (i >= CFG_SYS_NUM_I2C_BUSES) {
 			printf("Invalid bus %d\n", i);
 			return -1;
 		}
 		printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
 			int j;
-			for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
+			for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
 				if (i2c_bus[i].next_hop[j].chip == 0)
 					break;
 				printf("->%s@0x%2x:%d",
@@ -1788,7 +1788,7 @@
 	} else {
 		bus_no = dectoul(argv[1], NULL);
 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
-		if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
+		if (bus_no >= CFG_SYS_NUM_I2C_BUSES) {
 			printf("Invalid bus %d\n", bus_no);
 			return -1;
 		}

diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c
index aaaedfe..bbd406f 100644
--- a/cmd/ti/ddr3.c
+++ b/cmd/ti/ddr3.c

@@ -20,7 +20,7 @@
 
 #ifdef CONFIG_ARCH_KEYSTONE
 #include <asm/arch/ddr3.h>
-#define DDR_MIN_ADDR		CONFIG_SYS_SDRAM_BASE
+#define DDR_MIN_ADDR		CFG_SYS_SDRAM_BASE
 #define STACKSIZE		(512 << 10)     /* 512 KiB */
 
 #define DDR_REMAP_ADDR		0x80000000
@@ -247,9 +247,9 @@
 	/* Check in ecc address range 1 */
 	if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) {
 		start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
-				+ CONFIG_SYS_SDRAM_BASE;
+				+ CFG_SYS_SDRAM_BASE;
 		end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
-				CONFIG_SYS_SDRAM_BASE;
+				CFG_SYS_SDRAM_BASE;
 		if ((addr >= start_addr) && (addr <= end_addr))
 			/* addr within ecc address range 1 */
 			return 1;
@@ -259,9 +259,9 @@
 	if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) {
 		range = readl(&emif->emif_ecc_address_range_2);
 		start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
-				+ CONFIG_SYS_SDRAM_BASE;
+				+ CFG_SYS_SDRAM_BASE;
 		end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
-				CONFIG_SYS_SDRAM_BASE;
+				CFG_SYS_SDRAM_BASE;
 		if ((addr >= start_addr) && (addr <= end_addr))
 			/* addr within ecc address range 2 */
 			return 1;
@@ -309,11 +309,11 @@
 	start_addr = hextoul(argv[2], NULL);
 	end_addr = hextoul(argv[3], NULL);
 
-	if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
-	    (start_addr > (CONFIG_SYS_SDRAM_BASE +
+	if ((start_addr < CFG_SYS_SDRAM_BASE) ||
+	    (start_addr > (CFG_SYS_SDRAM_BASE +
 	     get_effective_memsize() - 1)) ||
-	    (end_addr < CONFIG_SYS_SDRAM_BASE) ||
-	    (end_addr > (CONFIG_SYS_SDRAM_BASE +
+	    (end_addr < CFG_SYS_SDRAM_BASE) ||
+	    (end_addr > (CFG_SYS_SDRAM_BASE +
 	     get_effective_memsize() - 1)) || (start_addr >= end_addr)) {
 		puts("Invalid start or end address!\n");
 		return cmd_usage(cmdtp);

diff --git a/common/Kconfig b/common/Kconfig
index 21434c5..8c71d3c 100644
--- a/common/Kconfig
+++ b/common/Kconfig

@@ -676,6 +676,10 @@
 	bool "Call set_cpu_clk_info"
 	depends on ARM
 
+config HWCONFIG
+	bool "hwconfig infrastructure"
+	default y if PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+
 config SYS_FSL_CLK
 	bool
 	depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || \
@@ -1082,3 +1086,6 @@
 	  These functions can be used by board to indicate to the OS
 	  the presence of the simple frame buffer with associated reserved
 	  memory
+
+config IO_TRACE
+	bool

diff --git a/common/board_f.c b/common/board_f.c
index e6117a7..e027248 100644
--- a/common/board_f.c
+++ b/common/board_f.c

@@ -329,12 +329,12 @@
 /* Get the top of usable RAM */
 __weak phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
-#if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
+#if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0
 	/*
 	 * Detect whether we have so much RAM that it goes past the end of our
 	 * 32-bit address space. If so, clip the usable RAM so it doesn't.
 	 */
-	if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
+	if (gd->ram_top < CFG_SYS_SDRAM_BASE)
 		/*
 		 * Will wrap back to top of 32-bit space when reservations
 		 * are made.
@@ -369,8 +369,8 @@
 	 */
 	gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
 #endif
-#ifdef CONFIG_SYS_SDRAM_BASE
-	gd->ram_base = CONFIG_SYS_SDRAM_BASE;
+#ifdef CFG_SYS_SDRAM_BASE
+	gd->ram_base = CFG_SYS_SDRAM_BASE;
 #endif
 	gd->ram_top = gd->ram_base + get_effective_memsize();
 	gd->ram_top = board_get_usable_ram_top(gd->mon_len);
@@ -900,9 +900,9 @@
 	post_init_f,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_SYS_DRAM_TEST)
+#if defined(CFG_SYS_DRAM_TEST)
 	testdram,
-#endif /* CONFIG_SYS_DRAM_TEST */
+#endif /* CFG_SYS_DRAM_TEST */
 	INIT_FUNC_WATCHDOG_RESET
 
 #ifdef CONFIG_POST

diff --git a/common/board_r.c b/common/board_r.c
index f7fb7df..347bb7f 100644
--- a/common/board_r.c
+++ b/common/board_r.c

@@ -346,7 +346,7 @@
 	 * NOTE: Maybe we should add some schedule()? XXX
 	 */
 	if (env_get_yesno("flashchecksum") == 1) {
-		const uchar *flash_base = (const uchar *)CONFIG_SYS_FLASH_BASE;
+		const uchar *flash_base = (const uchar *)CFG_SYS_FLASH_BASE;
 
 		printf("  CRC: %08X", crc32(0,
 					    flash_base,
@@ -356,8 +356,8 @@
 	putc('\n');
 
 	/* update start of FLASH memory    */
-#ifdef CONFIG_SYS_FLASH_BASE
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#ifdef CFG_SYS_FLASH_BASE
+	bd->bi_flashstart = CFG_SYS_FLASH_BASE;
 #endif
 	/* size of FLASH memory (final value) */
 	bd->bi_flashsize = flash_size;
@@ -370,7 +370,7 @@
 #if defined(CONFIG_OXC) || defined(CONFIG_RMU)
 	/* flash mapped at end of memory map */
 	bd->bi_flashoffset = CONFIG_TEXT_BASE + flash_size;
-#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
+#elif CONFIG_SYS_MONITOR_BASE == CFG_SYS_FLASH_BASE
 	bd->bi_flashoffset = monitor_flash_len;	/* reserved area for monitor */
 #endif
 	return 0;

diff --git a/common/fdt_support.c b/common/fdt_support.c
index ebebffc..dbceec6 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c

@@ -739,7 +739,7 @@
 }
 
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_NR_INBOUND_WIN 4
+#define CFG_SYS_PCI_NR_INBOUND_WIN 4
 
 #define FDT_PCI_PREFETCH	(0x40000000)
 #define FDT_PCI_MEM32		(0x02000000)
@@ -751,7 +751,7 @@
 	int addrcell, sizecell, len, r;
 	u32 *dma_range;
 	/* sized based on pci addr cells, size-cells, & address-cells */
-	u32 dma_ranges[(3 + 2 + 2) * CONFIG_SYS_PCI_NR_INBOUND_WIN];
+	u32 dma_ranges[(3 + 2 + 2) * CFG_SYS_PCI_NR_INBOUND_WIN];
 
 	addrcell = fdt_getprop_u32_default(blob, "/", "#address-cells", 1);
 	sizecell = fdt_getprop_u32_default(blob, "/", "#size-cells", 1);

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index fef01bd..c6da4a4 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig

@@ -1232,6 +1232,11 @@
 	  expense and power consumption. This enables loading from SATA
 	  using a configured device.
 
+config SYS_SATA_FAT_BOOT_PARTITION
+	int "Partition on the SATA disk to load U-Boot from"
+	depends on SPL_SATA && SPL_FS_FAT
+	default 1
+
 config SPL_SATA_RAW_U_BOOT_USE_SECTOR
 	bool "SATA raw mode: by sector"
 	depends on SPL_SATA

diff --git a/common/spl/Kconfig.nxp b/common/spl/Kconfig.nxp
index 8da8553..fc696cf 100644
--- a/common/spl/Kconfig.nxp
+++ b/common/spl/Kconfig.nxp

@@ -26,7 +26,7 @@
 	bool "Ensures that CCSR is not relocated"
 	depends on PPC
 	help
-	  If this is defined, then CONFIG_SYS_CCSRBAR_PHYS will be forced to a
+	  If this is defined, then CFG_SYS_CCSRBAR_PHYS will be forced to a
 	  value that ensures that CCSR is not relocated.
 
 config TPL_SYS_CCSR_DO_NOT_RELOCATE
@@ -59,7 +59,7 @@
 config SPL_RELOC_STACK
 	hex "Address of the start of the stack SPL will use after relocation."
 	help
-	  If unspecified, this is equal to CONFIG_SYS_SPL_MALLOC_START.  Starting
+	  If unspecified, this is equal to CFG_SYS_SPL_MALLOC_START.  Starting
 	  address of the malloc pool used in SPL.  When this option is set the full
 	  malloc is used in SPL and it is set up by spl_init() and before that, the
 	  simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined.

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 22d2a06..1d2e8fd 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c

@@ -43,8 +43,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 DECLARE_BINMAN_MAGIC_SYM;
 
-#ifndef CONFIG_SYS_UBOOT_START
-#define CONFIG_SYS_UBOOT_START	CONFIG_TEXT_BASE
+#ifndef CFG_SYS_UBOOT_START
+#define CFG_SYS_UBOOT_START	CONFIG_TEXT_BASE
 #endif
 
 u32 *boot_params_ptr = NULL;
@@ -250,7 +250,7 @@
 		spl_image->entry_point = u_boot_pos;
 		spl_image->load_addr = u_boot_pos;
 	} else {
-		spl_image->entry_point = CONFIG_SYS_UBOOT_START;
+		spl_image->entry_point = CFG_SYS_UBOOT_START;
 		spl_image->load_addr = CONFIG_TEXT_BASE;
 	}
 	spl_image->os = IH_OS_U_BOOT;

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index c1ed31e..08da7fe 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c

@@ -828,7 +828,7 @@
 	}
 
 	/*
-	 * If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's
+	 * If a platform does not provide CFG_SYS_UBOOT_START, U-Boot's
 	 * Makefile will set it to 0 and it will end up as the entry point
 	 * here. What it actually means is: use the load address.
 	 */

diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 25a38be..dc45204 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c

@@ -26,12 +26,12 @@
 	nand_init();
 
 	printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n",
-	       CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
-	       CONFIG_SYS_NAND_U_BOOT_DST);
+	       CONFIG_SYS_NAND_U_BOOT_OFFS, CFG_SYS_NAND_U_BOOT_SIZE,
+	       CFG_SYS_NAND_U_BOOT_DST);
 
 	nand_spl_load_image(spl_nand_get_uboot_raw_page(),
-			    CONFIG_SYS_NAND_U_BOOT_SIZE,
-			    (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+			    CFG_SYS_NAND_U_BOOT_SIZE,
+			    (void *)CFG_SYS_NAND_U_BOOT_DST);
 	spl_set_header_raw_uboot(spl_image);
 	nand_deselect();
 

diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index eaa95fb..1ef5e41 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c

@@ -20,7 +20,7 @@
 
 unsigned long __weak spl_nor_get_uboot_base(void)
 {
-	return CONFIG_SYS_UBOOT_BASE;
+	return CFG_SYS_UBOOT_BASE;
 }
 
 static int spl_nor_load_image(struct spl_image_info *spl_image,

diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
index 9ae0273..12397f0 100644
--- a/common/spl/spl_sata.c
+++ b/common/spl/spl_sata.c

@@ -17,10 +17,6 @@
 #include <fat.h>
 #include <image.h>
 
-#ifndef CONFIG_SYS_SATA_FAT_BOOT_PARTITION
-#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
-#endif
-
 #ifndef CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR
 /* Dummy value to make the compiler happy */
 #define CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR 0x100

diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index da67424..2aff025 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c

@@ -31,7 +31,7 @@
 	int err;
 
 	/* Read for a header, parse or error out. */
-	spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(*header),
+	spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, sizeof(*header),
 		       (void *)header);
 
 	if (image_get_magic(header) != IH_MAGIC)
@@ -41,12 +41,12 @@
 	if (err)
 		return err;
 
-	spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS,
+	spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS,
 		       spl_image->size, (void *)spl_image->load_addr);
 
 	/* Read device tree. */
-	spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS,
-		       CONFIG_SYS_SPI_ARGS_SIZE,
+	spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
+		       CFG_SYS_SPI_ARGS_SIZE,
 		       (void *)CONFIG_SYS_SPL_ARGS_ADDR);
 
 	return 0;

diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c
index fb804f0..bcac25c 100644
--- a/common/spl/spl_ubi.c
+++ b/common/spl/spl_ubi.c

@@ -31,7 +31,7 @@
 #ifdef CONFIG_SPL_ONENAND_SUPPORT
 	case BOOT_DEVICE_ONENAND:
 		info.read = onenand_spl_read_block;
-		info.peb_size = CONFIG_SYS_ONENAND_BLOCK_SIZE;
+		info.peb_size = CFG_SYS_ONENAND_BLOCK_SIZE;
 		break;
 #endif
 	default:

diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c
index 1258d85..77c23ba 100644
--- a/common/spl/spl_xip.c
+++ b/common/spl/spl_xip.c

@@ -25,6 +25,6 @@
 	}
 #endif
 	return(spl_parse_image_header(spl_image, bootdev,
-	       (const struct legacy_img_hdr *)CONFIG_SYS_UBOOT_BASE));
+	       (const struct legacy_img_hdr *)CFG_SYS_UBOOT_BASE));
 }
 SPL_LOAD_IMAGE_METHOD("XIP", 0, BOOT_DEVICE_XIP, spl_xip);

diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index dd88d10..28966e0 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig

@@ -47,5 +47,6 @@
 CONFIG_ALTERA_TSE=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_TIMER=y
 CONFIG_ALTERA_TIMER=y

diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index 0e7d5e7..2f55845 100644
--- a/configs/CHIP_pro_defconfig
+++ b/configs/CHIP_pro_defconfig

@@ -25,6 +25,7 @@
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_SIZE=0x1000
 CONFIG_SYS_NAND_OOBSIZE=0x100
+CONFIG_SYS_NAND_MAX_ECCPOS=1664
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2

diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index fd219cb..680c2d4 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig

@@ -43,3 +43,4 @@
 CONFIG_MCFFEC=y
 CONFIG_MII=y
 CONFIG_MCFUART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=5000

diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index 1b7b156..c0087aa 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig

@@ -50,3 +50,4 @@
 CONFIG_MCFFEC=y
 CONFIG_MII=y
 CONFIG_MCFUART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=5000

diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index fffcddd..b099e98 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig

@@ -50,3 +50,4 @@
 CONFIG_MCFFEC=y
 CONFIG_MII=y
 CONFIG_MCFUART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=5000

diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 5e7d401..a321b1c 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig

@@ -62,3 +62,4 @@
 CONFIG_MCFFEC=y
 CONFIG_MII=y
 CONFIG_MCFUART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=10000

diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index 6586f04..32d1958 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig

@@ -49,3 +49,4 @@
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=5000

diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index bf1d70f..9f0b419 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig

@@ -48,3 +48,4 @@
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=5000

diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index b83b542..0538879 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig

@@ -50,3 +50,4 @@
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=5000

diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 181f79b..90d8321 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig

@@ -50,3 +50,4 @@
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=3360

diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index 6c41d7c..d8d6417 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig

@@ -29,6 +29,7 @@
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run flashboot"
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_AUTO_COMPLETE is not set

diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 675b2de..1a571cf 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig

@@ -147,6 +147,7 @@
 CONFIG_SPCR_TSECEP_3=y
 CONFIG_LCRR_DBYP_PLL_BYPASSED=y
 CONFIG_LCRR_CLKDIV_8=y
+CONFIG_FSL_SERDES=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -205,8 +206,10 @@
 CONFIG_DM_ETH_PHY=y
 CONFIG_RGMII=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_DS1374=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_FSL=y

diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index e5c45a1..517fd78 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig

@@ -8,6 +8,8 @@
 CONFIG_ENV_ADDR=0xFFF60000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -43,6 +45,7 @@
 CONFIG_BOOTFILE="8548cds/uImage.uboot"
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eTSEC0"
+CONFIG_SPD_EEPROM=y
 CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
@@ -85,5 +88,5 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_ADDR_MAP=y

diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 85ec76a..5c83e80 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig

@@ -8,6 +8,8 @@
 CONFIG_ENV_ADDR=0xFFF60000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -42,6 +44,7 @@
 CONFIG_BOOTFILE="8548cds/uImage.uboot"
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eTSEC0"
+CONFIG_SPD_EEPROM=y
 CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
@@ -84,4 +87,4 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y

diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 852ac9a..b354237 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig

@@ -8,6 +8,8 @@
 CONFIG_ENV_ADDR=0xFFF60000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -42,6 +44,7 @@
 CONFIG_BOOTFILE="8548cds/uImage.uboot"
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eTSEC0"
+CONFIG_SPD_EEPROM=y
 CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
@@ -84,4 +87,4 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y

diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig
index 94060ab..1b7a457 100644
--- a/configs/Nintendo_NES_Classic_Edition_defconfig
+++ b/configs/Nintendo_NES_Classic_Edition_defconfig

@@ -20,6 +20,7 @@
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_PAGE_SIZE=0x800
 CONFIG_SYS_NAND_OOBSIZE=0x40
+CONFIG_SYS_NAND_MAX_ECCPOS=1664
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_ELDO2_VOLT=1800
 CONFIG_CONS_INDEX=5

diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index e15ca5e..b32837c 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig

@@ -129,7 +129,9 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index dcf74f5..575d5bf 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig

@@ -93,7 +93,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 230c6d0..21c752d 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig

@@ -114,7 +114,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 982420d..a514d4b 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig

@@ -116,7 +116,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index b3af445..db71e9b 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig

@@ -128,7 +128,9 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 537d8bf..291c4a4 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig

@@ -92,7 +92,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index dd91209..8237da3 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig

@@ -113,7 +113,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index ff7cfa2..9cb53d6 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig

@@ -115,7 +115,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index a61f4d0..9574697 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig

@@ -132,7 +132,9 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 92a7e09..7b3919d 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig

@@ -95,7 +95,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 84e2d3c..3ad137d 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig

@@ -116,7 +116,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index b883b81..cde657c 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig

@@ -118,7 +118,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 7f7870d..1faeab2 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig

@@ -131,7 +131,9 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 3e16470..190d02f 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig

@@ -94,7 +94,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index e985f8c..5e32768 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig

@@ -115,7 +115,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 9f4ae14..bce763c 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig

@@ -117,7 +117,8 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 3f93b31..b9d52a7 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig

@@ -139,10 +139,13 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 3b3cf1e..f86bc55 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig

@@ -121,10 +121,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index aba5b9c..0b9e108 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig

@@ -123,10 +123,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index ce0ba0e..9f68ede 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig

@@ -101,10 +101,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index f3fc4c8..3dd2475 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig

@@ -138,10 +138,13 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 25eb5d5..bd64dcc 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig

@@ -120,10 +120,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 054320f..140d271 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig

@@ -122,10 +122,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index aae886b..3f65389 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig

@@ -100,10 +100,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index cc02fe6..abe064c 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig

@@ -141,10 +141,13 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index dc82da8..78a54dd 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig

@@ -123,10 +123,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 7b80ede..a8bdb5a 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig

@@ -125,10 +125,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 5fecb66..7a533ed 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig

@@ -103,10 +103,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 9162774..3abb9d7 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig

@@ -144,10 +144,13 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index fd143b6..551b5fc 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig

@@ -126,10 +126,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index edb8b99..493e2c9 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig

@@ -128,10 +128,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index b1dbca6..fc82fa8 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig

@@ -106,10 +106,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 1269d22..b6ae81d 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig

@@ -143,10 +143,13 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPL_NS16550_MIN_FUNCTIONS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index b5394d0..cfbb3c2 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig

@@ -125,10 +125,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 431ca31..36c6c7e 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig

@@ -127,10 +127,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 1ee46f9..691df7c 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig

@@ -105,10 +105,12 @@
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_VSC7385_ENET=y
 CONFIG_TSEC_ENET=y
 CONFIG_PCIE_FSL=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_PT7C4338=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 2ba5666..f495205 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig

@@ -6,6 +6,10 @@
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
@@ -98,7 +102,7 @@
 CONFIG_MII=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
@@ -108,3 +112,4 @@
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_POST=y

diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 9a2796f..23a7b66 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig

@@ -6,6 +6,10 @@
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
@@ -93,7 +97,7 @@
 CONFIG_MII=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
@@ -103,3 +107,4 @@
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_POST=y

diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 8cb00d5..7dfbde0 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig

@@ -7,6 +7,10 @@
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
@@ -95,7 +99,7 @@
 CONFIG_MII=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
@@ -105,3 +109,4 @@
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_POST=y

diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index c0bd16b..aea0b89 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig

@@ -7,6 +7,10 @@
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
@@ -90,7 +94,7 @@
 CONFIG_MII=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
@@ -100,3 +104,4 @@
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_POST=y

diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index 73ef73c..fa7c35b 100644
--- a/configs/SBx81LIFKW_defconfig
+++ b/configs/SBx81LIFKW_defconfig

@@ -63,7 +63,8 @@
 CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig
index 9fa0fda..1258713 100644
--- a/configs/SBx81LIFXCAT_defconfig
+++ b/configs/SBx81LIFXCAT_defconfig

@@ -61,7 +61,8 @@
 CONFIG_PHY_FIXED=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 2aada04..e51db83 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig

@@ -129,7 +129,8 @@
 CONFIG_SYS_QE_FW_ADDR=0x200000
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_DS1337=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index e5661b0..5472ccc 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig

@@ -123,7 +123,8 @@
 CONFIG_SYS_QE_FW_ADDR=0x124000
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_DS1337=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 320f22e..0dd7251 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig

@@ -126,7 +126,8 @@
 CONFIG_SYS_QE_FW_ADDR=0x130000
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_DS1337=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 1f571b6..8a2096c 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig

@@ -98,7 +98,8 @@
 CONFIG_SYS_QE_FW_ADDR=0xEFE00000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_DS1337=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 4088d40..cc6a804 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig

@@ -129,7 +129,8 @@
 CONFIG_SYS_QE_FW_ADDR=0x380000
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_DS1337=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 5a6f9a8..cb270ad 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig

@@ -123,7 +123,8 @@
 CONFIG_SYS_QE_FW_ADDR=0x124000
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_DS1337=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 2d03b4e..79530ea 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig

@@ -126,7 +126,8 @@
 CONFIG_SYS_QE_FW_ADDR=0x130000
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_DS1337=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 8f283fa..a671ae3 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig

@@ -98,7 +98,8 @@
 CONFIG_SYS_QE_FW_ADDR=0xEFF10000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_RTC_DS1337=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index beb0259..637842c 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig

@@ -11,6 +11,10 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
@@ -136,7 +140,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 7ee5fb4..35ab993 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig

@@ -12,6 +12,10 @@
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
@@ -130,7 +134,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index c050e31..93b02a5 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig

@@ -4,6 +4,10 @@
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
@@ -104,7 +108,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 0ff651a..7d25bbb 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig

@@ -14,6 +14,10 @@
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
@@ -133,7 +137,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 98065da..2846f63 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig

@@ -5,6 +5,10 @@
 CONFIG_ENV_ADDR=0xFFE20000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
@@ -93,7 +97,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 88e943d..a7dc88c 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig

@@ -6,6 +6,10 @@
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
@@ -105,7 +109,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 23f6ee6..a881488 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig

@@ -136,7 +136,7 @@
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index c2d95c1..562a799 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig

@@ -130,7 +130,7 @@
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 2194ff6..0001803 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig

@@ -133,7 +133,7 @@
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 7f57b00..0cb359d 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig

@@ -104,7 +104,7 @@
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index 5d4573a..cbe1bb4 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig

@@ -138,7 +138,7 @@
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index 7ca9a8b..80a2c00 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig

@@ -132,7 +132,7 @@
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index 39fcd2d..99bee8e 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig

@@ -135,7 +135,7 @@
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index 8d1011d..aa6a053 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig

@@ -106,7 +106,7 @@
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_DS1307=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 9b08267..b445b6b 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig

@@ -119,7 +119,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 662edc3..a807ac8 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig

@@ -94,7 +94,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y

diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index e4d6fc2..d28cdf4 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig

@@ -105,3 +105,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index bd23b71..9976cee 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig

@@ -79,6 +79,7 @@
 CONFIG_DM_MDIO=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 66b7fb6..442783a 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig

@@ -76,6 +76,7 @@
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_DM_PMIC is not set
 CONFIG_PMIC_TPS65217=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index f73123e..78e63c9 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig

@@ -102,6 +102,7 @@
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_DM_PMIC is not set
 CONFIG_PMIC_TPS65217=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 7f42201..335a43d 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig

@@ -93,6 +93,7 @@
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_DM_PMIC is not set
 CONFIG_PMIC_TPS65217=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 8d3a454..5dc9ba9 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig

@@ -80,6 +80,7 @@
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_DM_PMIC is not set
 CONFIG_PMIC_TPS65217=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index 7080b14..68513c1 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig

@@ -81,6 +81,7 @@
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_DM_PMIC is not set
 CONFIG_PMIC_TPS65217=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 65b2055..673824c 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig

@@ -75,6 +75,7 @@
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_PMIC_TPS65217=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 45332e2..0839d36 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig

@@ -81,6 +81,8 @@
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
 CONFIG_MII=y
 CONFIG_DRIVER_TI_EMAC=y
 CONFIG_DRIVER_TI_EMAC_USE_RMII=y

diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 2dfd936..2faf132 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig

@@ -88,6 +88,8 @@
 CONFIG_PHY=y
 CONFIG_SPL_PHY=y
 CONFIG_OMAP_USB2_PHY=y
+CONFIG_POWER_TPS65218=y
+CONFIG_POWER_TPS62362=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
 CONFIG_TI_QSPI=y

diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 0b759c8..9c90924 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig

@@ -53,7 +53,9 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SYS_NS16550=y
+CONFIG_POWER_TPS65218=y
+CONFIG_POWER_TPS62362=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y

diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index 357da19..4241070 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig

@@ -72,6 +72,8 @@
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
+CONFIG_POWER_TPS65218=y
+CONFIG_POWER_TPS62362=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
 CONFIG_TI_QSPI=y

diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 0e58221..91270d0 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig

@@ -91,6 +91,8 @@
 CONFIG_PHY=y
 CONFIG_SPL_PHY=y
 CONFIG_OMAP_USB2_PHY=y
+CONFIG_POWER_TPS65218=y
+CONFIG_POWER_TPS62362=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
 CONFIG_TI_QSPI=y

diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 2b5a7fb..b6b74af 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig

@@ -86,6 +86,8 @@
 CONFIG_PHY=y
 CONFIG_SPL_PHY=y
 CONFIG_OMAP_USB2_PHY=y
+CONFIG_POWER_TPS65218=y
+CONFIG_POWER_TPS62362=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y
 CONFIG_TI_QSPI=y

diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig
index 68a9651..03e46dd 100644
--- a/configs/am43xx_hs_evm_qspi_defconfig
+++ b/configs/am43xx_hs_evm_qspi_defconfig

@@ -55,7 +55,9 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SYS_NS16550=y
+CONFIG_POWER_TPS65218=y
+CONFIG_POWER_TPS62362=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y

diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
index 5ff2954..4c7ded9 100644
--- a/configs/aristainetos2c_defconfig
+++ b/configs/aristainetos2c_defconfig

@@ -118,6 +118,7 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig
index 0a20854..a23c77a 100644
--- a/configs/aristainetos2ccslb_defconfig
+++ b/configs/aristainetos2ccslb_defconfig

@@ -118,6 +118,7 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index afbcb86..9e5665a 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig

@@ -50,3 +50,4 @@
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y
 CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=3355

diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index a5436db..85a70c0 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig

@@ -56,6 +56,7 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 7fbec63..00d43e2 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig

@@ -56,6 +56,7 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 5f43f4c..90a734f 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig

@@ -59,6 +59,7 @@
 CONFIG_SYS_64BIT_LBA=y
 CONFIG_CPU=y
 CONFIG_E1000=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig
index 920e882..f8e0327 100644
--- a/configs/bcm7260_defconfig
+++ b/configs/bcm7260_defconfig

@@ -40,5 +40,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCMSTB=y
 CONFIG_MTD=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 # CONFIG_EFI_LOADER is not set

diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig
index b44eaba..81433b0 100644
--- a/configs/bcm7445_defconfig
+++ b/configs/bcm7445_defconfig

@@ -44,7 +44,8 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_BCMSTB_SPI=y

diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index cbcbc9b..0225717 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig

@@ -93,4 +93,5 @@
 # CONFIG_WATCHDOG is not set
 CONFIG_WDT=y
 CONFIG_WDT_CDNS=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
 # CONFIG_EFI_LOADER is not set

diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index bed7370..630a13f 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig

@@ -81,3 +81,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
index 06987ab..321121e 100644
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig

@@ -50,6 +50,7 @@
 CONFIG_SYS_64BIT_LBA=y
 CONFIG_CPU=y
 CONFIG_RTL8169=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index 59ae29a..2240988 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig

@@ -94,6 +94,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y

diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index 3d2f40f..d768e11 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig

@@ -92,6 +92,7 @@
 CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y

diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index 45905c6..a38b3b7 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig

@@ -102,6 +102,7 @@
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SOUND_DA7219=y
 CONFIG_SOUND_I8254=y

diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index ffa8070..150dba1 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig

@@ -97,6 +97,7 @@
 CONFIG_SPL_RAM=y
 CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_SOUND=y
 CONFIG_I2S=y

diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
index e8ec885..94d14d0 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig

@@ -93,6 +93,7 @@
 CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y

diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index b645cba..570c4e8 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig

@@ -79,6 +79,7 @@
 CONFIG_CROS_EC_LPC=y
 CONFIG_SPL_DM_RTC=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_TPM_TIS_LPC=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 541b7fa..43cf530 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig

@@ -68,6 +68,7 @@
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SOUND=y
 CONFIG_SPI=y
 CONFIG_TPM_TIS_LPC=y

diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index ca453ac..08e1e5b 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig

@@ -96,6 +96,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_I2S=y
 CONFIG_I2S_ROCKCHIP=y

diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 27bf046..aa3d6f2 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig

@@ -70,6 +70,7 @@
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
 CONFIG_SOUND_RT5677=y

diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
index e922264..7773573 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig

@@ -91,6 +91,7 @@
 # CONFIG_SPL_PINCTRL is not set
 # CONFIG_TPL_PINCTRL is not set
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
 CONFIG_SOUND_RT5677=y

diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 92018fb..d5aaee9 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig

@@ -95,6 +95,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y

diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index b78e98c..e83f2df 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig

@@ -59,6 +59,7 @@
 CONFIG_CROS_EC_LPC=y
 CONFIG_RTL8169=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_TPM_TIS_LPC=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index f3ee559..d1a044e 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig

@@ -74,6 +74,7 @@
 CONFIG_SPL_DM=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_CMD_PCA953X=y
+CONFIG_PCA953X=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MXC=y
@@ -95,6 +96,7 @@
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE3000=y
 CONFIG_DM_REGULATOR=y
 CONFIG_POWER_I2C=y
 CONFIG_MXC_UART=y

diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index ea75966..217752c 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig

@@ -116,6 +116,7 @@
 CONFIG_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SOURCE=y
 CONFIG_FDT_FIXUP_PARTITIONS=y

diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 0a5ce20..867ca30 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig

@@ -95,6 +95,7 @@
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_TPS65218=y
 CONFIG_POWER_I2C=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI=y

diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index 0d90467..31979f3 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig

@@ -69,6 +69,7 @@
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_E1000=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 6fed3f2..18d58be 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig

@@ -65,6 +65,7 @@
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_E1000=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
index 20c0c18..e4da59b 100644
--- a/configs/coreboot64_defconfig
+++ b/configs/coreboot64_defconfig

@@ -61,6 +61,7 @@
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 # CONFIG_PCI_PNP is not set
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
 CONFIG_CONSOLE_SCROLL_LINES=5

diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index d8c5be6..e297494 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig

@@ -55,6 +55,7 @@
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 # CONFIG_PCI_PNP is not set
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
 CONFIG_CONSOLE_SCROLL_LINES=5

diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 094b216..8b47f2d 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig

@@ -52,7 +52,9 @@
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 CONFIG_CPU=y
+CONFIG_SMSC_SIO1007=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 4521172..038cbbe 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig

@@ -56,7 +56,9 @@
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 CONFIG_CPU=y
+CONFIG_SMSC_LPC47M=y
 CONFIG_E1000=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
 CONFIG_SPI=y

diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index 5eea1ec..71c57ed 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig

@@ -66,7 +66,8 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index ec80edf..9b1b619 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig

@@ -35,6 +35,7 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_CLOCKS=y
+CONFIG_HWCONFIG=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_PAD_TO=0x8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index 01cdc4f..9332c8c 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig

@@ -29,6 +29,7 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_CLOCKS=y
+CONFIG_HWCONFIG=y
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PBSIZE=1050

diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 30454a3..f979c45 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig

@@ -33,6 +33,7 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_CLOCKS=y
+CONFIG_HWCONFIG=y
 CONFIG_SPL_PAD_TO=0x8000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xc0000000
@@ -86,7 +87,7 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
 CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
+CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800

diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index 16a866f..6c35f31 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig

@@ -59,7 +59,8 @@
 CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 6c805f4..a17d01f 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig

@@ -55,7 +55,8 @@
 CONFIG_PHY_MARVELL=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index 86fe069..6deb055 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig

@@ -62,7 +62,8 @@
 CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig
index 93aef47..9088fff 100644
--- a/configs/ds109_defconfig
+++ b/configs/ds109_defconfig

@@ -56,7 +56,8 @@
 CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig
index 5abdadf..c364c9e 100644
--- a/configs/eaidk-610-rk3399_defconfig
+++ b/configs/eaidk-610-rk3399_defconfig

@@ -51,6 +51,7 @@
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index f904bb3..a831c1c 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig

@@ -52,4 +52,5 @@
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_MCFFEC=y
 CONFIG_MII=y
+CONFIG_RTC_DS1338=y
 CONFIG_MCFUART=y

diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 2ce6ff9..6a673c9 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig

@@ -50,4 +50,5 @@
 CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_MCFFEC=y
 CONFIG_MII=y
+CONFIG_RTC_DS1338=y
 CONFIG_MCFUART=y

diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig
index 83f532d..8d1fc22 100644
--- a/configs/efi-x86_payload32_defconfig
+++ b/configs/efi-x86_payload32_defconfig

@@ -52,6 +52,7 @@
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 # CONFIG_PCI_PNP is not set
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 # CONFIG_GZIP is not set
 CONFIG_EFI=y
 CONFIG_EFI_STUB=y

diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig
index 28aaff6..89e6d1f 100644
--- a/configs/efi-x86_payload64_defconfig
+++ b/configs/efi-x86_payload64_defconfig

@@ -52,6 +52,7 @@
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 # CONFIG_PCI_PNP is not set
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 # CONFIG_GZIP is not set
 CONFIG_EFI=y
 CONFIG_EFI_STUB=y

diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig
index 1f4ca01..36f57d5 100644
--- a/configs/elgin-rv1108_defconfig
+++ b/configs/elgin-rv1108_defconfig

@@ -48,6 +48,7 @@
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 6bc777c..bb6f21b 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig

@@ -101,6 +101,7 @@
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
 CONFIG_DM_THERMAL=y

diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index f41c758..2e3bff8 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig

@@ -78,6 +78,7 @@
 CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_TINY_MEMSET=y

diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 8ef40d8..289f47f 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig

@@ -55,6 +55,7 @@
 CONFIG_PINCTRL=y
 # CONFIG_SPL_DM_SERIAL is not set
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 # CONFIG_SPL_SYSRESET is not set
 CONFIG_USB=y

diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
index ce10750..06a044b 100644
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig

@@ -46,6 +46,7 @@
 CONFIG_RAM=y
 CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index f8ca1f6..33202e4 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig

@@ -72,6 +72,7 @@
 CONFIG_TPL_RAM=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y

diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 7c0b856..8f8d34c 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig

@@ -81,6 +81,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index 8502fcc..0aeaf01 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig

@@ -74,6 +74,7 @@
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 9421845..8a6d19a 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig

@@ -88,6 +88,7 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set
 CONFIG_USB=y

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index e7da9c4..3050fd5 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig

@@ -61,6 +61,7 @@
 CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index db3acf5..7374ee4 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig

@@ -63,5 +63,6 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_ERRNO_STR=y

diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig
index 5de5de4..aab3223 100644
--- a/configs/evb-rv1108_defconfig
+++ b/configs/evb-rv1108_defconfig

@@ -42,6 +42,7 @@
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index d48dcc1..3aee6b6 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig

@@ -55,6 +55,7 @@
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 1f91118..2a6d2ed 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig

@@ -100,6 +100,7 @@
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
 CONFIG_DM_THERMAL=y

diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 63c53a0..26967a6 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig

@@ -78,6 +78,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index a378706..5475172 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig

@@ -61,6 +61,7 @@
 CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index 3974e3d..d294697 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig

@@ -131,6 +131,7 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_CBSIZE=1024

diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index 180a6a8..353942d 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig

@@ -133,6 +133,7 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=30000
 CONFIG_IMX_WATCHDOG=y
 CONFIG_BCH=y

diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index d9fbdbd..e35788f 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig

@@ -98,6 +98,8 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=8000
 CONFIG_IMX_WATCHDOG=y
 CONFIG_BCH=y

diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
index 1d7832b..c23d054 100644
--- a/configs/geekbox_defconfig
+++ b/configs/geekbox_defconfig

@@ -27,5 +27,6 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_ERRNO_STR=y

diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index 6fdb3ea..8ee1183 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig

@@ -62,7 +62,8 @@
 CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 55222eb..b918b13 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig

@@ -103,3 +103,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index 794cf4b..1889743 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig

@@ -61,7 +61,8 @@
 CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index cabe09e..f999b44 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig

@@ -39,6 +39,7 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HWCONFIG=y
 CONFIG_MISC_INIT_R=y
 CONFIG_PCI_INIT_R=y
 CONFIG_SPL_BOARD_INIT=y
@@ -119,6 +120,8 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_LTC3676=y
+CONFIG_POWER_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_POWER_I2C=y
@@ -160,6 +163,8 @@
 # CONFIG_PANEL is not set
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_HIDE_LOGO_VERSION=y

diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index f58abd9..4c6291f 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig

@@ -39,6 +39,7 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HWCONFIG=y
 CONFIG_MISC_INIT_R=y
 CONFIG_PCI_INIT_R=y
 CONFIG_SPL_BOARD_INIT=y
@@ -123,6 +124,8 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_LTC3676=y
+CONFIG_POWER_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_POWER_I2C=y
@@ -164,6 +167,8 @@
 # CONFIG_PANEL is not set
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_HIDE_LOGO_VERSION=y

diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index a41b3c4..4e062e4 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig

@@ -39,6 +39,7 @@
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HWCONFIG=y
 CONFIG_MISC_INIT_R=y
 CONFIG_PCI_INIT_R=y
 CONFIG_SPL_BOARD_INIT=y
@@ -129,6 +130,8 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_LTC3676=y
+CONFIG_POWER_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_POWER_I2C=y
@@ -170,6 +173,8 @@
 # CONFIG_PANEL is not set
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_HIDE_LOGO_VERSION=y

diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 9eec928..152459e 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig

@@ -30,9 +30,11 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_HIKEY_GPIO=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_K3=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_HI6553=y
 CONFIG_CONS_INDEX=4
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig
index 8c6ad5a..bba4067 100644
--- a/configs/hsdk_4xd_defconfig
+++ b/configs/hsdk_4xd_defconfig

@@ -60,6 +60,7 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig
index 9543c78..4715f9d9 100644
--- a/configs/hsdk_defconfig
+++ b/configs/hsdk_defconfig

@@ -59,6 +59,7 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index 9290cb7..beee589 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig

@@ -59,7 +59,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index ce5a089..f536dd3 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig

@@ -59,7 +59,8 @@
 CONFIG_MII=y
 CONFIG_PCI=y
 CONFIG_PCI_MVEBU=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index fe4866e..759bbf9 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig

@@ -74,6 +74,7 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index 2cb995e..c7d31d5 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig

@@ -75,6 +75,7 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index 9f6d29a..f5a7e96 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig

@@ -98,6 +98,7 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index 2cb995e..c7d31d5 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig

@@ -75,6 +75,7 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 274cdb9..79a27de 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig

@@ -88,6 +88,7 @@
 CONFIG_SPL_POWER_LEGACY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_POWER_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y

diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 42f812c..1fa1a5a 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig

@@ -66,7 +66,8 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 9bf2e86..96bcba6 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig

@@ -78,8 +78,8 @@
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
@@ -92,6 +92,7 @@
 CONFIG_KEYSTONE_USB_PHY=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DAVINCI_SPI=y

diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index afa4dc1..0d1c97d 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig

@@ -53,8 +53,8 @@
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
@@ -67,6 +67,7 @@
 CONFIG_KEYSTONE_USB_PHY=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DAVINCI_SPI=y

diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 6182101..bded097 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig

@@ -96,6 +96,7 @@
 CONFIG_REMOTEPROC_TI_POWER=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y

diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index fd169c3..a851d85 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig

@@ -70,6 +70,7 @@
 CONFIG_REMOTEPROC_TI_POWER=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y

diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index cbf948f..b0069fd 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig

@@ -78,8 +78,8 @@
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
@@ -92,6 +92,7 @@
 CONFIG_KEYSTONE_USB_PHY=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DAVINCI_SPI=y

diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 2480547..9ca26ae 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig

@@ -53,8 +53,8 @@
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
@@ -67,6 +67,7 @@
 CONFIG_KEYSTONE_USB_PHY=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DAVINCI_SPI=y

diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index f4c8c5e..153abb7 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig

@@ -78,8 +78,9 @@
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
+CONFIG_SYS_NAND_PAGE_4K=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
@@ -92,6 +93,7 @@
 CONFIG_KEYSTONE_USB_PHY=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DAVINCI_SPI=y

diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index 051cd23..2990a70 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig

@@ -56,8 +56,9 @@
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y
 CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
+CONFIG_SYS_NAND_PAGE_4K=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
@@ -70,6 +71,7 @@
 CONFIG_KEYSTONE_USB_PHY=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_DAVINCI_SPI=y

diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
index dff0522..754fd4e 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig

@@ -56,6 +56,7 @@
 CONFIG_RAM_RK3399_LPDDR4=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
index 5a8b69c..7518f7f 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig

@@ -55,6 +55,7 @@
 CONFIG_RAM_RK3399_LPDDR4=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
index f54a610..4c4301a 100644
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig

@@ -56,6 +56,7 @@
 CONFIG_RAM_RK3399_LPDDR4=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index 48ac85b..41b2628 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig

@@ -110,3 +110,4 @@
 CONFIG_BCH=y
 CONFIG_PANIC_HANG=y
 CONFIG_LZO=y
+CONFIG_POST=y

diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 298ff16..013277c 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig

@@ -167,6 +167,7 @@
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y
@@ -234,6 +235,7 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_KMETER1=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_QE_UEC=y
 # CONFIG_PCI is not set
@@ -241,3 +243,4 @@
 CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_BCH=y
+CONFIG_POST=y

diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 9386f2c..66ec936 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig

@@ -137,6 +137,7 @@
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y

diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index 1733066..3ba334c 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig

@@ -150,6 +150,7 @@
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y

diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index c281611..4a02e5e 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig

@@ -130,6 +130,7 @@
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y

diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index e099f74..5515886 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig

@@ -150,6 +150,7 @@
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y

diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index b4e6bae..24eff46 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig

@@ -103,3 +103,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig
index d2726b1..898a0b4 100644
--- a/configs/kontron_pitx_imx8m_defconfig
+++ b/configs/kontron_pitx_imx8m_defconfig

@@ -95,6 +95,7 @@
 CONFIG_SPL_POWER_LEGACY=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_POWER_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y

diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index f044334..9b90ed4 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig

@@ -39,6 +39,7 @@
 CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOARD_LATE_INIT=y
+# CONFIG_HWCONFIG is not set
 CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 1ad635d..646f008 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig

@@ -60,6 +60,7 @@
 CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_SPL_DM_SERIAL is not set
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 # CONFIG_SPL_SYSRESET is not set
 CONFIG_USB=y

diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 472d8da..56057e2 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig

@@ -105,3 +105,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index a8326f0..5a958ee 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig

@@ -51,6 +51,7 @@
 CONFIG_RAM_RK3399_LPDDR4=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index 98e37f1..90c1b94 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig

@@ -23,6 +23,7 @@
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_CLOCKS=y
+CONFIG_HWCONFIG=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_BOOTM_NETBSD is not set
 # CONFIG_BOOTM_PLAN9 is not set

diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 1ace7b7..ee401b7 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig

@@ -97,6 +97,7 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y

diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index dbb0ce0..b551f5b 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig

@@ -60,7 +60,7 @@
 CONFIG_FSL_PFE=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig
index a8b4ce2..21ccc55 100644
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig

@@ -58,7 +58,7 @@
 CONFIG_FSL_PFE=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 1a4fc99..f1c9169 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig

@@ -58,7 +58,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index 7e9076a..f40ede1 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig

@@ -56,7 +56,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index 7bfe1f7..ff5e323 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig

@@ -61,7 +61,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index 2327d89..3b07324 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig

@@ -64,7 +64,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index 250440a..238886d 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig

@@ -59,7 +59,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index f1600c4..ccd8fb9 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig

@@ -62,7 +62,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index e4a26dc..fcef5e5 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig

@@ -85,7 +85,7 @@
 CONFIG_RTC_PCF8563=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index c9fa109..c2996a1 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig

@@ -75,7 +75,7 @@
 CONFIG_RTC_PCF8563=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 773a3e6..a1709f4 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig

@@ -84,7 +84,7 @@
 CONFIG_RTC_PCF8563=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index c9f0635..3639b4d 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig

@@ -65,7 +65,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index c1c21cb..4fc7b38 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig

@@ -67,7 +67,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 503fe95..f162111 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig

@@ -63,7 +63,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index 727d10f..cc64046 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig

@@ -64,7 +64,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 72129a7..e6cd6a7 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig

@@ -68,7 +68,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index c67f329..d5d3354 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig

@@ -98,7 +98,7 @@
 CONFIG_U_QE=y
 CONFIG_SYS_QE_FW_ADDR=0xf40000
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 14aa19f..c3c6678 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig

@@ -130,7 +130,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y

diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 2f1b41f..40228ac 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig

@@ -96,7 +96,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y

diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 1c38d99..ebf6fdb 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig

@@ -84,7 +84,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 4a642f4..07d52c2 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig

@@ -127,7 +127,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y

diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 1b5d822..6834a69 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig

@@ -112,7 +112,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index 877a771..e5e732a 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig

@@ -69,7 +69,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 9695164..29dc23e 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig

@@ -96,7 +96,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 290d53f..8606080 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig

@@ -80,7 +80,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y

diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index b3a9317..ed7e91e 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig

@@ -77,7 +77,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index cb3d158..f84f4dd 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig

@@ -112,7 +112,7 @@
 CONFIG_U_QE=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
 CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y

diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index c53827c..40a0ea7 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig

@@ -111,7 +111,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y

diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 46ab9a2..621a023 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig

@@ -105,7 +105,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index 753583d..525c7df 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig

@@ -86,7 +86,7 @@
 CONFIG_RTC_PCF2127=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index b5e243b..dde204e 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig

@@ -92,7 +92,7 @@
 CONFIG_RTC_PCF2127=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index fad0786..b8df245 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig

@@ -80,7 +80,7 @@
 CONFIG_RTC_PCF2127=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 20354f7..5b1cf98 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig

@@ -86,7 +86,7 @@
 CONFIG_RTC_PCF2127=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 9b3c77f..a7e9583 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig

@@ -99,7 +99,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 29cbac3..774d413 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig

@@ -130,7 +130,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 21bb036..f759baf 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig

@@ -100,7 +100,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index fd7f3bb..e7dbf41 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig

@@ -89,7 +89,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 14931f7..627abc8 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig

@@ -127,7 +127,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 2284463..f4dcbd4 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig

@@ -115,7 +115,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index b75c752..307fbfc 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig

@@ -98,7 +98,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 21199b9..667fc21 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig

@@ -107,7 +107,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index df227d8..7d980c3 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig

@@ -86,7 +86,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 0e2fa02..b345d13 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig

@@ -89,7 +89,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x60940000
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 6b9971f..d454634 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig

@@ -110,7 +110,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 0aa046a..f0f8cbf 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig

@@ -117,7 +117,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index a6c33de..529cd93 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig

@@ -110,7 +110,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index ddf280a..bfe9260 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig

@@ -115,7 +115,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 7ca5457..391e95a 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig

@@ -84,7 +84,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 5fe6bae..2ebde25 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig

@@ -90,7 +90,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SYS_QE_FW_ADDR=0x940000
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
index 7d9f533..0df5b85 100644
--- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig

@@ -67,7 +67,7 @@
 CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index 03e944f..a095bbc 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig

@@ -76,7 +76,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
index e9cf20d..2bf8a94 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig

@@ -98,7 +98,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 0e2f409..5fe73bc 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig

@@ -101,7 +101,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index 75851ad..7c8a1e7 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig

@@ -130,7 +130,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index 552bb43..9375815 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig

@@ -91,7 +91,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index 3124644..4d3c058 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig

@@ -130,7 +130,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 344899e..480ab03 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig

@@ -118,7 +118,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 0a36353..a0d57b1 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig

@@ -99,7 +99,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 26fc459..e08af4d 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig

@@ -109,7 +109,7 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_PCIE_LAYERSCAPE_EP=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index d9c716e..1a09fda 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig

@@ -111,7 +111,7 @@
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index 61b7244..346a954 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig

@@ -86,7 +86,7 @@
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 05115ea..4361cd2 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig

@@ -90,7 +90,7 @@
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index ac2cede..5603626 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig

@@ -119,7 +119,7 @@
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 6074b6b..cdcfa63 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig

@@ -109,7 +109,7 @@
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 07b0777..e044239 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig

@@ -111,7 +111,7 @@
 CONFIG_POWER_I2C=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 2432154..da6c243 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig

@@ -79,7 +79,7 @@
 CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 0aa2792..f9aab31 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig

@@ -85,7 +85,7 @@
 CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
index 1e86590..aecd74d 100644
--- a/configs/ls1088aqds_defconfig
+++ b/configs/ls1088aqds_defconfig

@@ -83,6 +83,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
@@ -99,7 +101,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index cfe1540..8d1fc5f 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig

@@ -69,6 +69,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_EON=y
@@ -91,7 +93,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index 4e0e7c3..7c6e6b7 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig

@@ -72,6 +72,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_EON=y
@@ -94,7 +96,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index 0a7541d..64296dbe 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig

@@ -104,6 +104,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_PHYLIB=y
 CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
@@ -119,7 +121,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y

diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index d9f2781..2b4712e 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig

@@ -92,6 +92,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_EON=y
@@ -114,7 +116,7 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index cce2d9a..c8ab572 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig

@@ -91,6 +91,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_EON=y
@@ -116,7 +118,7 @@
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index 4c46384..18213e5c 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig

@@ -72,6 +72,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -87,7 +89,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 7962645..eb88cec 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig

@@ -75,6 +75,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -90,7 +92,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 504db13..33aedcf 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig

@@ -95,6 +95,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -109,7 +111,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 8053bc1..db28ae1 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig

@@ -95,6 +95,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -110,7 +112,7 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 7ba5940..0ec80be 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig

@@ -71,6 +71,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -88,7 +90,7 @@
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index ff5784b..27323be 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig

@@ -77,6 +77,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -94,7 +96,7 @@
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 8899fd9..d449b42 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig

@@ -74,6 +74,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -93,8 +95,9 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index a9f52ae..973537a 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig

@@ -77,6 +77,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -96,8 +98,9 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 0b70e7b..4fc4419 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig

@@ -91,6 +91,8 @@
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -109,8 +111,9 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 648a539..4cd1c85 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig

@@ -71,6 +71,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -89,8 +91,9 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 318822b..5256658 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig

@@ -85,6 +85,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -103,8 +105,9 @@
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 8ae8b52..15bc69e 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig

@@ -76,6 +76,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
@@ -90,9 +92,10 @@
 CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index d548bca..88b5d23 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig

@@ -79,6 +79,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
@@ -93,9 +95,10 @@
 CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index a49fe87..8339cf7 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig

@@ -100,6 +100,8 @@
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
@@ -112,9 +114,10 @@
 CONFIG_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y

diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index 58bae66..fc43c53 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig

@@ -86,7 +86,7 @@
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 4c1e742..a9faa15 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig

@@ -88,6 +88,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -109,8 +111,9 @@
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index 6e1fe90..d3a1133 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig

@@ -80,9 +80,10 @@
 CONFIG_NVME_PCI=y
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index 8441814..f94142d 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig

@@ -87,9 +87,10 @@
 CONFIG_NVME_PCI=y
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index 93be74d..1dd7c1d 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig

@@ -81,6 +81,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -96,9 +98,10 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index c2bf451..246ab40 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig

@@ -88,6 +88,8 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=256
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
 CONFIG_SPI_FLASH_SPANSION=y
@@ -104,9 +106,10 @@
 CONFIG_PCI=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
+CONFIG_RTC_DS3231=y
 CONFIG_DM_SCSI=y
 CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index b4ada56..e332de2 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig

@@ -80,6 +80,7 @@
 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_IIM=y
 CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
@@ -121,6 +122,7 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_SPLASH_SOURCE=y

diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index 054c5e6..b635c65 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig

@@ -45,3 +45,4 @@
 CONFIG_PCI_MSC01=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y

diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
index 55f624b..243213c 100644
--- a/configs/malta64el_defconfig
+++ b/configs/malta64el_defconfig

@@ -47,3 +47,4 @@
 CONFIG_PCI_MSC01=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y

diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index 53762a9..ed41e29 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig

@@ -44,3 +44,4 @@
 CONFIG_PCI_MSC01=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y

diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 8b86d74..63e5fcb 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig

@@ -46,3 +46,4 @@
 CONFIG_PCI_MSC01=y
 CONFIG_RTC_MC146818=y
 CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y

diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index a6cffa2..27c5ebe 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig

@@ -67,6 +67,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 # CONFIG_PANEL is not set
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 66f3036..52ed763 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig

@@ -65,6 +65,7 @@
 CONFIG_SYS_64BIT_LBA=y
 CONFIG_CPU=y
 CONFIG_RTL8169=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index 0811e70..9346caf 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig

@@ -75,6 +75,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index 403a84b..7ba8338 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig

@@ -99,6 +99,7 @@
 CONFIG_DM_RESET=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER=y

diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index 996dd5c..dad8839 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig

@@ -61,6 +61,7 @@
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RTC_MXS=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
 CONFIG_USB=y

diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index 89597c0..b173648 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig

@@ -40,6 +40,7 @@
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="FEC0"
 CONFIG_ARP_TIMEOUT=200
+CONFIG_FSL_IIM=y
 CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_PHYLIB=y
@@ -53,6 +54,9 @@
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_POWER_FSL=y
+CONFIG_POWER_SPI=y
+CONFIG_RTC_MC13XXX=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y

diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index b34f2e7..c20c6a4 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig

@@ -40,3 +40,4 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y

diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 193120f..08bcd35 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig

@@ -58,6 +58,7 @@
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_POWER_FSL=y
 CONFIG_POWER_I2C=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y

diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 328f546..d8cb654 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig

@@ -52,6 +52,7 @@
 CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_MISC=y
+CONFIG_FSL_IIM=y
 CONFIG_I2C_EEPROM=y
 CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
@@ -80,6 +81,7 @@
 CONFIG_VIDEO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
 CONFIG_WATCHDOG_TIMEOUT_MSECS=8000
 CONFIG_IMX_WATCHDOG=y
 CONFIG_BCH=y

diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 0904bd1..a9957ab 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig

@@ -84,6 +84,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 # CONFIG_PANEL is not set
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index becf36e..6869b90 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig

@@ -89,6 +89,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_VIDEO_BMP_GZIP=y

diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 2aa15ce..8e94a84 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig

@@ -95,6 +95,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_POWER_I2C=y
 CONFIG_MXC_UART=y
@@ -119,6 +120,8 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 766ce0e..9472e03 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig

@@ -102,6 +102,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_POWER_I2C=y
@@ -124,6 +125,8 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index 03fa857..8fad8c6 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig

@@ -55,6 +55,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig
index 67ca985..c5f13c0 100644
--- a/configs/nanopi-m4-2gb-rk3399_defconfig
+++ b/configs/nanopi-m4-2gb-rk3399_defconfig

@@ -51,6 +51,7 @@
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index afa51bc..b6a604b 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig

@@ -51,6 +51,7 @@
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig
index d02eb18..767befe 100644
--- a/configs/nanopi-m4b-rk3399_defconfig
+++ b/configs/nanopi-m4b-rk3399_defconfig

@@ -51,6 +51,7 @@
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index d2d9bf9..383ec1f 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig

@@ -51,6 +51,7 @@
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
index 82264de..40d3117 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig

@@ -91,6 +91,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSINFO=y
 CONFIG_SYSRESET=y
 # CONFIG_TPL_SYSRESET is not set

diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig
index 2185f87..40a45a0 100644
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig

@@ -52,6 +52,7 @@
 CONFIG_RAM_RK3399_LPDDR4=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index 9cebc70..0590fc9 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig

@@ -63,7 +63,8 @@
 CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index c10e1a5..b327814 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig

@@ -67,7 +67,8 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 75907e0..dfdb06b 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig

@@ -67,7 +67,8 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index db08ca5..995c0cc 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig

@@ -67,7 +67,8 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index dda3b6b..877a39c 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig

@@ -65,7 +65,8 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 21534c5..24f7d8b 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig

@@ -67,7 +67,8 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_KIRKWOOD_SPI=y

diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 3ec4df1..87ca848 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig

@@ -94,6 +94,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_VIDEO_BMP_GZIP=y

diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 6a6510e..1bdd2f0 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig

@@ -94,6 +94,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_VIDEO_BMP_GZIP=y

diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index e2acce8..dc010b0 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig

@@ -97,6 +97,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_VIDEO_BMP_GZIP=y

diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index ceb843f..fe3291d 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig

@@ -97,6 +97,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_VIDEO_BMP_GZIP=y

diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index bb0d6f5..b316524 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig

@@ -94,6 +94,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_VIDEO_BMP_GZIP=y

diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 0232d0c..eb11959 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig

@@ -94,6 +94,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_VIDEO_BMP_GZIP=y

diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index f6690b4..3999ae1 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig

@@ -79,6 +79,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE100=y
 CONFIG_POWER_I2C=y
 CONFIG_MXC_UART=y
 CONFIG_DM_THERMAL=y
@@ -98,5 +99,7 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index afa0cad..e7d6ffd 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig

@@ -53,7 +53,8 @@
 CONFIG_PHY_MARVELL=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_UBIFS_SILENCE_MSG=y

diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 4705f61..33adcc9 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig

@@ -104,6 +104,7 @@
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
 CONFIG_DM_THERMAL=y

diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 93daa46..84e267d 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig

@@ -80,6 +80,8 @@
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
 CONFIG_SMC911X=y
 CONFIG_SMC911X_32_BIT=y
 CONFIG_PINCTRL=y

diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index de33825..471e055 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig

@@ -88,6 +88,8 @@
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
 CONFIG_SMC911X=y
 CONFIG_SMC911X_32_BIT=y
 CONFIG_PINCTRL=y

diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index e2c6dfc..67db3af 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig

@@ -79,6 +79,8 @@
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
 CONFIG_SMC911X=y
 CONFIG_SMC911X_32_BIT=y
 CONFIG_PINCTRL=y

diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 3237c42..e18cbaa 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig

@@ -89,6 +89,8 @@
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_MAX_OOBFREE=2
+CONFIG_SYS_NAND_MAX_ECCPOS=56
 CONFIG_SMC911X=y
 CONFIG_SMC911X_32_BIT=y
 CONFIG_PINCTRL=y

diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 2c4e26c..79807f1 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig

@@ -45,8 +45,9 @@
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_TWL6030_POWER=y
 CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OMAP3=y

diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 2315a84..e2f1bc6 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig

@@ -42,8 +42,9 @@
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_TWL6030_POWER=y
 CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_OMAP3=y
 CONFIG_USB_GADGET=y

diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index bd0ede7..91878c1 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig

@@ -47,7 +47,7 @@
 CONFIG_SCSI_AHCI=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
-CONFIG_CMD_TCA642X=y
+CONFIG_TCA642X=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SUPPORT_EMMC_BOOT=y
@@ -56,7 +56,7 @@
 CONFIG_SCSI=y
 CONFIG_SCSI_AHCI_PLAT=y
 CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_DWC3=y

diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 51c78dc..ff3b5f0 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig

@@ -83,7 +83,7 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
 CONFIG_NAND_DAVINCI=y
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
+CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
 CONFIG_SYS_NAND_PAGE_COUNT=0x40
 CONFIG_SYS_NAND_PAGE_SIZE=0x800

diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index c2e879c..45bd307 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig

@@ -61,6 +61,7 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index 01bfaed..9c9f6c4 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig

@@ -62,6 +62,7 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index 7c64103..fbcdf4b 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig

@@ -62,6 +62,7 @@
 CONFIG_MTD_RAW_NAND=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
index 39245e8..0980d81 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig

@@ -51,6 +51,7 @@
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 373c609..3ed5591 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig

@@ -56,6 +56,7 @@
 CONFIG_PHY_SMSC=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig
index ed55f7b..d21e180 100644
--- a/configs/pg_wcom_expu1_defconfig
+++ b/configs/pg_wcom_expu1_defconfig

@@ -100,3 +100,4 @@
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_POST=y

diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig
index 64ddaf8..54773b0 100644
--- a/configs/pg_wcom_expu1_update_defconfig
+++ b/configs/pg_wcom_expu1_update_defconfig

@@ -98,3 +98,4 @@
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_POST=y

diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index ad08e35..8311b3a 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig

@@ -100,3 +100,4 @@
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_POST=y

diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig
index 01a6198..d6f4a05 100644
--- a/configs/pg_wcom_seli8_update_defconfig
+++ b/configs/pg_wcom_seli8_update_defconfig

@@ -98,3 +98,4 @@
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_POST=y

diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig
index b6b5274..1b31676 100644
--- a/configs/phycore-am335x-r2-regor_defconfig
+++ b/configs/phycore-am335x-r2-regor_defconfig

@@ -83,6 +83,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
index 5012049..c5ffb41 100644
--- a/configs/phycore-am335x-r2-wega_defconfig
+++ b/configs/phycore-am335x-r2-wega_defconfig

@@ -84,6 +84,7 @@
 CONFIG_DM_SPI_FLASH=y
 CONFIG_MII=y
 CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPL_POWER_TPS65910=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y

diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 8a27418..0632a92 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig

@@ -78,6 +78,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig
index 8213578..46777e0 100644
--- a/configs/pico-dwarf-imx7d_defconfig
+++ b/configs/pico-dwarf-imx7d_defconfig

@@ -81,6 +81,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE3000=y
 CONFIG_POWER_I2C=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y

diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index 759866c..fb354d1 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig

@@ -81,6 +81,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE3000=y
 CONFIG_POWER_I2C=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y

diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index 9b3f76d..a6ed013 100644
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig

@@ -99,6 +99,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 # CONFIG_PANEL is not set
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index 8631f81..35e6f1d 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig

@@ -77,6 +77,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE3000=y
 CONFIG_POWER_I2C=y
 CONFIG_CONS_INDEX=4
 CONFIG_MXC_UART=y

diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index a84954d..13cc97b 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig

@@ -81,6 +81,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE3000=y
 CONFIG_POWER_I2C=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y

diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig
index 8213578..46777e0 100644
--- a/configs/pico-nymph-imx7d_defconfig
+++ b/configs/pico-nymph-imx7d_defconfig

@@ -81,6 +81,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE3000=y
 CONFIG_POWER_I2C=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y

diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index dec4280..6e92366 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig

@@ -81,6 +81,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE3000=y
 CONFIG_POWER_I2C=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y

diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig
index 528b7bb..dfbf5e7 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig

@@ -80,6 +80,7 @@
 CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y

diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index d0071f3..116e5d0 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig

@@ -55,7 +55,8 @@
 CONFIG_PHY_MARVELL=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig
index 3b08cb7..018c2f5 100644
--- a/configs/pogo_v4_defconfig
+++ b/configs/pogo_v4_defconfig

@@ -74,7 +74,8 @@
 CONFIG_PCI_MVEBU=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PCI=y

diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index f6c49da..9112378 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig

@@ -75,6 +75,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 83cc54a..ca56008 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig

@@ -103,3 +103,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index c2b0b39..9a5be3e 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig

@@ -92,6 +92,7 @@
 CONFIG_DM_RTC=y
 CONFIG_RTC_ISL1208=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y

diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig
index 9175c7c..9c36750 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig

@@ -100,6 +100,7 @@
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
 CONFIG_DM_THERMAL=y

diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index 0aa7cca..db1ceaa 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig

@@ -100,6 +100,7 @@
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
 CONFIG_DM_THERMAL=y

diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index d731b96..d2cca48 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig

@@ -100,6 +100,7 @@
 # CONFIG_SPECIFY_CONSOLE_INDEX is not set
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SOUND=y
 CONFIG_SYSRESET=y
 CONFIG_DM_THERMAL=y

diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index d6ff4ac..cdad1b0 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig

@@ -52,6 +52,7 @@
 CONFIG_TSEC_ENET=y
 CONFIG_PCI_MPC85XX=y
 CONFIG_DM_RTC=y
+CONFIG_RTC_PT7C4338=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y

diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 8433b57..0f4811e 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig

@@ -70,6 +70,7 @@
 CONFIG_CPU=y
 CONFIG_NVME_PCI=y
 CONFIG_SPL_DM_RTC=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y

diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index f82f628..a822212 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig

@@ -50,6 +50,7 @@
 CONFIG_SYS_64BIT_LBA=y
 CONFIG_CPU=y
 CONFIG_NVME_PCI=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y

diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index cee9a1f..4217175 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig

@@ -57,4 +57,5 @@
 CONFIG_DM_SERIAL=y
 CONFIG_SERIAL_RX_BUFFER=y
 CONFIG_SCIF_CONSOLE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
 CONFIG_USE_PRIVATE_LIBGCC=y

diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 1bf4027..9f8fbc8 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig

@@ -84,6 +84,8 @@
 CONFIG_SYS_WHITE_ON_BLACK=y
 # CONFIG_PANEL is not set
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 670211e..0a029c4 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig

@@ -74,6 +74,7 @@
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 7f1259d..8172ed0 100644
--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig

@@ -95,6 +95,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y
 CONFIG_SYSRESET=y

diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
index 3cdcc72..6827c98 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig

@@ -71,6 +71,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y

diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index e03442a..cf4a58d 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig

@@ -68,6 +68,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y

diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index 83721ce..54a4004 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig

@@ -62,6 +62,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig
index ac9a3f9..e74ba07 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig

@@ -62,6 +62,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
index c0c1ebf..0ffb073 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig

@@ -96,6 +96,7 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y
 CONFIG_SYSRESET=y

diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig
index fcb3a68..2443f29 100644
--- a/configs/rock-pi-n10-rk3399pro_defconfig
+++ b/configs/rock-pi-n10-rk3399pro_defconfig

@@ -63,6 +63,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig
index 4ed98c0..18c6d1b 100644
--- a/configs/rock-pi-n8-rk3288_defconfig
+++ b/configs/rock-pi-n8-rk3288_defconfig

@@ -74,6 +74,7 @@
 CONFIG_SPL_RAM=y
 # CONFIG_RAM_ROCKCHIP_DEBUG is not set
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 38a5f3a..54d0145 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig

@@ -77,6 +77,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index e75011b..73a4f06 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig

@@ -92,6 +92,7 @@
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y

diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index 6ed5ef8..f2c914f 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig

@@ -65,6 +65,7 @@
 CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index bd6183b..2663840 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig

@@ -63,6 +63,7 @@
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER=y

diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index ba48d02..5b8d678 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig

@@ -79,6 +79,7 @@
 CONFIG_DM_SCSI=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y

diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 686a3c0..2375040 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig

@@ -50,6 +50,7 @@
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_TPS6586X_POWER=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
index 01f104a..40cd91c 100644
--- a/configs/sheep-rk3368_defconfig
+++ b/configs/sheep-rk3368_defconfig

@@ -29,5 +29,6 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_ERRNO_STR=y

diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index 52f5aba..79f36c0 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig

@@ -65,7 +65,8 @@
 CONFIG_MII=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 9ff9e23..5005e16 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig

@@ -105,3 +105,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig
index b6b9f88..f5d16f6 100644
--- a/configs/slimbootloader_defconfig
+++ b/configs/slimbootloader_defconfig

@@ -31,5 +31,6 @@
 CONFIG_LBA48=y
 CONFIG_SYS_64BIT_LBA=y
 # CONFIG_PCI_PNP is not set
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_CONSOLE_SCROLL_LINES=5
 # CONFIG_GZIP is not set

diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 601353c..ed0ed2c 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig

@@ -97,6 +97,7 @@
 CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0908
 CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
+CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y

diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index 6844092..9269ecc 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig

@@ -82,6 +82,7 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index de9ebd0..48fb067 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig

@@ -75,6 +75,7 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index 7642498..da4545e 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig

@@ -83,6 +83,7 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 08ae6c5..4e2dc0c 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig

@@ -62,6 +62,7 @@
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 2951574..67c6e74 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig

@@ -78,3 +78,4 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig
index 478efc5..00c4cf3 100644
--- a/configs/socfpga_chameleonv3_defconfig
+++ b/configs/socfpga_chameleonv3_defconfig

@@ -29,6 +29,7 @@
 CONFIG_SPL_FS_LOADER=y
 CONFIG_MMC_DW=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_DESIGNWARE_APB_TIMER=y

diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 9c3c0f6..ce1a349 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig

@@ -79,3 +79,4 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index b3ba9ff..01c29a2 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig

@@ -82,3 +82,4 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 5f5706f..905afb7 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig

@@ -75,3 +75,4 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index 1f835be..f2a53ba 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig

@@ -72,3 +72,4 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig
index 412b0da..dbf979e 100644
--- a/configs/socfpga_de10_standard_defconfig
+++ b/configs/socfpga_de10_standard_defconfig

@@ -72,3 +72,4 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 68a3689..613bf44 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig

@@ -60,4 +60,5 @@
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
 # CONFIG_EFI_LOADER is not set

diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 3a21bc7..32d7b74 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig

@@ -69,3 +69,4 @@
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 8be8b85..4d16ec3 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig

@@ -73,3 +73,4 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig
index 0feda3b..4d856d5 100644
--- a/configs/socfpga_n5x_atf_defconfig
+++ b/configs/socfpga_n5x_atf_defconfig

@@ -81,6 +81,7 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig
index fa19f55..1056932 100644
--- a/configs/socfpga_n5x_defconfig
+++ b/configs/socfpga_n5x_defconfig

@@ -72,6 +72,7 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig
index 12e8ebf..a6714b2 100644
--- a/configs/socfpga_n5x_vab_defconfig
+++ b/configs/socfpga_n5x_vab_defconfig

@@ -82,6 +82,7 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index debe22f..7a805df 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig

@@ -112,4 +112,5 @@
 CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
 CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
 # CONFIG_GZIP is not set

diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 31cc03a..b3de670 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig

@@ -79,3 +79,4 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 72a7037..80a9871 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig

@@ -80,3 +80,4 @@
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 44e9ba6..cbe37d2 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig

@@ -76,3 +76,4 @@
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 # CONFIG_SPL_WDT is not set
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index 5ee9f5f..e0e6b2d 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig

@@ -83,6 +83,7 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index f689105..9198632 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig

@@ -80,6 +80,7 @@
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y

diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 96c0ebb..cdad36b 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig

@@ -116,3 +116,4 @@
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index b89c348..f45f570 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig

@@ -23,6 +23,7 @@
 CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo"
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PBSIZE=276
 CONFIG_CMD_REGINFO=y
@@ -56,6 +57,7 @@
 CONFIG_ENV_ADDR_REDUND=0xFFF20000
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="TSEC0"
+CONFIG_SPD_EEPROM=y
 CONFIG_CHIP_SELECTS_PER_CTRL=2
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFE001001

diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
index 5d401e6..5b72469 100644
--- a/configs/som-db5800-som-6867_defconfig
+++ b/configs/som-db5800-som-6867_defconfig

@@ -60,6 +60,7 @@
 CONFIG_SYS_64BIT_LBA=y
 CONFIG_CPU=y
 CONFIG_E1000=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 231e22a..53dce6a 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig

@@ -104,3 +104,4 @@
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 179cb52..aa28a68 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig

@@ -78,3 +78,4 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index ef9e444..9a1dac7 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig

@@ -115,6 +115,7 @@
 CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0908
 CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
+CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y

diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 4c5b98b..0df8a68 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig

@@ -114,6 +114,8 @@
 CONFIG_VIDCONSOLE_AS_LCD=y
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_VIDEO_BMP_RLE8=y
 # CONFIG_GZIP is not set
 CONFIG_OF_LIBFDT_ASSUME_MASK=0xff

diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig
index 48b2ffc..0209f62 100644
--- a/configs/ten64_tfa_defconfig
+++ b/configs/ten64_tfa_defconfig

@@ -81,7 +81,7 @@
 CONFIG_DM_RTC=y
 CONFIG_RTC_RX8025=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
index 22544c0..440c170 100644
--- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig

@@ -65,6 +65,7 @@
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_E1000=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig
index 8741ecb..b91c3b1 100644
--- a/configs/theadorable-x86-conga-qa3-e3845_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig

@@ -64,6 +64,7 @@
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_E1000=y
+CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 47dbf34..bab7b29 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig

@@ -77,6 +77,6 @@
 CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
 CONFIG_MII=y
 CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
 CONFIG_SPI=y
 # CONFIG_USE_PRIVATE_LIBGCC is not set

diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 85d94a6..5976a84 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig

@@ -83,6 +83,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 7dfbad8..078f829 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig

@@ -83,6 +83,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index e3ed0b2..96aa62a 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig

@@ -78,3 +78,4 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index cb15656..41ba8a7 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig

@@ -78,3 +78,4 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 03d1887..763bd8c 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig

@@ -78,3 +78,4 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 3b8560f..894a79d 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig

@@ -130,6 +130,7 @@
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y

diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 04ce0b3..6e66e6c 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig

@@ -152,6 +152,7 @@
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_HWCONFIG is not set
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_HUSH_PARSER=y

diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index 95428e1..f62a585 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig

@@ -57,6 +57,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE3000=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_ANATOP=y

diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 510e215..ed2bcc6 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig

@@ -29,6 +29,7 @@
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_IIM=y
 CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_PINCTRL=y

diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 234686e..70ce13e 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig

@@ -54,3 +54,4 @@
 CONFIG_SMC911X_32_BIT=y
 CONFIG_BAUDRATE=38400
 CONFIG_CONS_INDEX=0
+CONFIG_SYS_TIMER_COUNTS_DOWN=y

diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 3b5658d..7f84209 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig

@@ -89,6 +89,7 @@
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
+CONFIG_POWER_PFUZE100=y
 CONFIG_POWER_I2C=y
 CONFIG_PWM_IMX=y
 CONFIG_DM_SERIAL=y

diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index cbae60f..0c9d61b 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig

@@ -83,6 +83,7 @@
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 525f55e..a6baff1 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig

@@ -83,6 +83,8 @@
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_VIDEO_SKIP=y
+CONFIG_IMX_HDMI=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y

diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 127bbf7..167a078 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig

@@ -72,6 +72,7 @@
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_SMSC=y
+CONFIG_RTC_DS1374=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_CONS_INDEX=5
 CONFIG_SYS_NS16550=y

diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 1db3a2c..a4c555d 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig

@@ -146,6 +146,7 @@
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
 CONFIG_SPL_GZIP=y
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y

diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig
index 3148329..c585146 100644
--- a/configs/xtfpga_defconfig
+++ b/configs/xtfpga_defconfig

@@ -45,6 +45,7 @@
 CONFIG_SYS_MAX_FLASH_SECT=1027
 CONFIG_PHYLIB=y
 CONFIG_ETHOC=y
-CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SYS_NS16550_REG_SIZE=-4
 CONFIG_SYSRESET=y
 CONFIG_OF_LIBFDT=y

diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 7ca7483..74c35f3 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig

@@ -78,5 +78,6 @@
 CONFIG_NAND_ZYNQ=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_ARM_DCC=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
 # CONFIG_GZIP is not set
 # CONFIG_LMB is not set

diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 28e9c45..f1c648a 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig

@@ -80,5 +80,6 @@
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_ARM_DCC=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
 # CONFIG_GZIP is not set
 # CONFIG_LMB is not set

diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 215d5ed..c623caf 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig

@@ -90,5 +90,6 @@
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_ARM_DCC=y
 CONFIG_ZYNQ_QSPI=y
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
 # CONFIG_GZIP is not set
 # CONFIG_LMB is not set

diff --git a/doc/README.POST b/doc/README.POST
index 1d1c25b..5d92f3f 100644
--- a/doc/README.POST
+++ b/doc/README.POST

@@ -242,11 +242,11 @@
 
 All POST-related code will be #ifdef'ed with the CONFIG_POST macro.
 This macro will be defined in the config_<board>.h file for those
-boards that need POST. The CONFIG_POST macro will contain the list of
+boards that need POST. The CFG_POST macro will contain the list of
 POST tests for the board. The macro will have the format of array
 composed of post_test structures:
 
-#define CONFIG_POST \
+#define CFG_POST \
 	{
 		"On-board peripherals test", "board", \
 		"  This test performs full check-up of the " \
@@ -257,7 +257,7 @@
 
 A new file, post.h, will be created in the include/ directory. This
 file will contain common POST declarations and will define a set of
-macros that will be reused for defining CONFIG_POST. As an example,
+macros that will be reused for defining CFG_POST. As an example,
 the following macro may be defined:
 
 #define POST_CACHE \

diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation
index 6bb4e17..69882a7 100644
--- a/doc/README.arm-relocation
+++ b/doc/README.arm-relocation

@@ -53,8 +53,8 @@
 d) this initialize CPU, RAM, ... and copy itself to RAM
    (this bin must fit in one page, so board_init_f()
     don;t fit in it ... )
-e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and
-   starts this image @ CONFIG_SYS_NAND_U_BOOT_START
+e) there it copy u-boot to CFG_SYS_NAND_U_BOOT_DST and
+   starts this image @ CFG_SYS_NAND_U_BOOT_START
 f) u-boot code steps through board_init_f() and calculates
    the relocation address and copy itself to it
 
@@ -86,8 +86,8 @@
 
 - The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c
   which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE	and loads
-  the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
-  @CONFIG_SYS_NAND_U_BOOT_START
+  the "real" u-boot to CFG_SYS_NAND_U_BOOT_DST and starts execution
+  @CFG_SYS_NAND_U_BOOT_START
 
 - This u-boot does no RAM init, nor CPU register setup. Just look
   where it has to copy and relocate itself to this address. If

diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci
index 00e64ba..0b6d2c5 100644
--- a/doc/README.atmel_mci
+++ b/doc/README.atmel_mci

@@ -60,7 +60,7 @@
 /* this is a weak define that we are overriding */
 int board_mmc_getcd(struct mmc *mmc)
 {
-	return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN);
+	return !at91_get_gpio_value(CFG_SYS_MMC_CD_PIN);
 }
 
 #endif
@@ -70,5 +70,5 @@
 /* SD/MMC card */
 #define CONFIG_GENERIC_ATMEL_MCI	1
 #define CONFIG_ATMEL_MCI_PORTB		1	/* Atmel XE-EK uses port B */
-#define CONFIG_SYS_MMC_CD_PIN		AT91_PIN_PC9
+#define CFG_SYS_MMC_CD_PIN		AT91_PIN_PC9
 #define CONFIG_CMD_MMC			1

diff --git a/doc/README.cfi b/doc/README.cfi
index ad52850..3818574 100644
--- a/doc/README.cfi
+++ b/doc/README.cfi

@@ -35,12 +35,12 @@
 void flash_cmd_reset(flash_info_t *info)
 {
 	/*
-	 * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
+	 * FLASH at address CFG_SYS_FLASH_BASE is a Spansion chip and
 	 * needs the Spansion type reset commands. The other flash chip
 	 * is located behind a FPGA (Xilinx DS617) and needs the Intel type
 	 * reset command.
 	 */
-	if (info->start[0] == CONFIG_SYS_FLASH_BASE)
+	if (info->start[0] == CFG_SYS_FLASH_BASE)
 		flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
 	else
 		flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);

diff --git a/doc/README.davinci b/doc/README.davinci
index 607531a..326efa0 100644
--- a/doc/README.davinci
+++ b/doc/README.davinci

@@ -75,7 +75,7 @@
 Davinci special defines
 =======================
 
-CONFIG_SYS_DV_NOR_BOOT_CFG:	AM18xx based boards, booting in NOR Boot mode
+CFG_SYS_DV_NOR_BOOT_CFG:	AM18xx based boards, booting in NOR Boot mode
 				need a "NOR Boot Configuration Word" stored
 				in the NOR Flash. This define adds this.
 				More Info about this, see:

diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index cec5d94..10e63f3 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr

@@ -137,7 +137,7 @@
 2. Memory test can be done with Power-On-Self-Test function, activated at
    compile time.
 
-   In order to enable the POST memory test, CONFIG_POST needs to be
+   In order to enable the POST memory test, CFG_POST needs to be
    defined in board configuraiton header file. By default, POST memory test
    performs a fast test. A slow test can be enabled by changing the flag at
    compiling time. To test memory bigger than 2GB, 36BIT support is needed.

diff --git a/doc/README.fsl_iim b/doc/README.fsl_iim
index e087f5e..78d3cb8 100644
--- a/doc/README.fsl_iim
+++ b/doc/README.fsl_iim

@@ -45,4 +45,4 @@
 Configuration:
 
    CONFIG_FSL_IIM
-      Define this to enable the fsl_iim driver.
+      Enable this to enable the fsl_iim driver.

diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci
index 82fea62..767614c 100644
--- a/doc/README.generic_usb_ohci
+++ b/doc/README.generic_usb_ohci

@@ -11,7 +11,7 @@
 
 	CONFIG_USB_OHCI_NEW: enable the new OHCI driver
 
-	CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI
+	CFG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI
 				registers
 
 	CONFIG_SYS_USB_OHCI_SLOT_NAME: slot name

diff --git a/doc/README.hwconfig b/doc/README.hwconfig
index b6ddb43..5408a22 100644
--- a/doc/README.hwconfig
+++ b/doc/README.hwconfig

@@ -1,6 +1,3 @@
-To enable this feature just define CONFIG_HWCONFIG in your board
-config file.
-
 This implements a simple hwconfig infrastructure: an
 interface for software knobs to control hardware.
 

diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx
index 3c6ebbd..bafffe6 100644
--- a/doc/README.mpc85xx
+++ b/doc/README.mpc85xx

@@ -59,13 +59,13 @@
    3) TLB entry for the stack during AS1
        Location	  : Lable "create_init_ram_area"
        TLB Entry  : 14
-       EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+       EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
        Properties : 16K, AS1, IPROT
 
    4) TLB entry for CCSRBAR during AS1 execution
        Location	  : cpu_init_early_f
        TLB Entry  : 13
-       EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+       EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
        Properties : 1M, AS1, I, G
 
    5) Invalidate unproctected TLB Entries
@@ -84,7 +84,7 @@
    8) Update Flash's TLB entry
        Location	  : Board_init_r
        TLB entry  : Search from TLB entries
-       EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+       EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
        Properties : Board specific size, AS0, I, G, IPROT
 
 
@@ -94,7 +94,7 @@
        Location	  : Label "_start"
        TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
 #if defined(CONFIG_NXP_ESBC)
-       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
        Properties : 1M, AS1, I, G, IPROT
 #else
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
@@ -105,7 +105,7 @@
        Location	  : Label "create_init_ram_area"
        TLB Entry  : 15
 #if defined(CONFIG_NXP_ESBC)
-       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
        Properties : 1M, AS1, I, G, IPROT
 #else
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
@@ -115,13 +115,13 @@
    3) TLB entry for the stack during AS1
        Location	  : Lable "create_init_ram_area"
        TLB Entry  : 14
-       EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+       EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
        Properties : 16K, AS1, IPROT
 
    4) TLB entry for CCSRBAR during AS1 execution
        Location	  : cpu_init_early_f
        TLB Entry  : 13
-       EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+       EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
        Properties : 1M, AS1, I, G
 
    5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
@@ -162,5 +162,5 @@
    12) Update Flash's TLB entry
        Location	  : Board_init_r
        TLB entry  : Search from TLB entries
-       EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+       EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
        Properties : Board specific size, AS0, I, G, IPROT

diff --git a/doc/README.nand b/doc/README.nand
index d1ce307..3765751 100644
--- a/doc/README.nand
+++ b/doc/README.nand

@@ -99,16 +99,6 @@
    CONFIG_CMD_NAND_TORTURE
       Enables the torture command (see description of this command below).
 
-   CONFIG_SYS_NAND_MAX_ECCPOS
-      If specified, overrides the maximum number of ECC bytes
-      supported.  Useful for reducing image size, especially with SPL.
-      This must be at least 48 if nand_base.c is used.
-
-   CONFIG_SYS_NAND_MAX_OOBFREE
-      If specified, overrides the maximum number of free OOB regions
-      supported.  Useful for reducing image size, especially with SPL.
-      This must be at least 2 if nand_base.c is used.
-
    CONFIG_SYS_NAND_MAX_CHIPS
       The maximum number of NAND chips per device to be supported.
 
@@ -144,7 +134,7 @@
 	chip.IO_ADDR_R = ...;
 	chip.IO_ADDR_W = ...;
 
-	if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
+	if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL))
 		error out
 
 	/*

diff --git a/doc/README.omap3 b/doc/README.omap3
index 208714a..3a1ac81 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3

@@ -146,11 +146,11 @@
 When you require the SPL to read with BCH8 there are two more configs to
 change:
 
- * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
+ * CFG_SYS_NAND_ECCPOS (must be the same as .eccpos in
    GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
    arch/arm/include/asm/arch-omap3/omap_gpmc.h)
- * CONFIG_SYS_NAND_ECCSIZE must be 512
- * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
+ * CFG_SYS_NAND_ECCSIZE must be 512
+ * CFG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
 
 Acknowledgements
 ================

diff --git a/doc/README.serial_multi b/doc/README.serial_multi
index c9049fd..0446fe9 100644
--- a/doc/README.serial_multi
+++ b/doc/README.serial_multi

@@ -35,7 +35,7 @@
 	setenv sout serial_scc; setenv baudrate 38400
 
 After that press 'enter' at the SCC console. Note that baudrates <38400
-are not allowed on LWMON with watchdog enabled (see CONFIG_SYS_BAUDRATE_TABLE in
+are not allowed on LWMON with watchdog enabled (see CFG_SYS_BAUDRATE_TABLE in
 include/configs/lwmon.h).
 
 

diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst
index 15806df..770327f 100644
--- a/doc/arch/m68k.rst
+++ b/doc/arch/m68k.rst

@@ -112,16 +112,16 @@
 Other options, generally set inside include/configs/<boardname>.h, they may
 apply to one or more cpu for the ColdFire family:
 
-CONFIG_SYS_MBAR:
+CFG_SYS_MBAR:
   defines the base address of the MCF5272 configuration registers
-CONFIG_SYS_SCR:
+CFG_SYS_SCR:
   defines the contents of the System Configuration Register
-CONFIG_SYS_SPR:
+CFG_SYS_SPR:
   defines the contents of the System Protection Register
-CONFIG_SYS_MFD:
+CFG_SYS_MFD:
   defines the PLL Multiplication Factor Divider
   (see table 9-4 of MCF user manual)
-CONFIG_SYS_RFD:
+CFG_SYS_RFD:
   defines the PLL Reduce Frequency Devider
   (see table 9-4 of MCF user manual)
 CONFIG_SYS_CSx_BASE:
@@ -136,33 +136,33 @@
   if set to 0 chip select x is read/write else chip select is read only
 CONFIG_SYS_CSx_WS:
   defines the number of wait states  of chip select x
-CONFIG_SYS_CACHE_ICACR:
+CFG_SYS_CACHE_ICACR:
   cache-related registers config
-CONFIG_SYS_CACHE_DCACR:
+CFG_SYS_CACHE_DCACR:
   cache-related registers config
 CONFIG_SYS_CACHE_ACRX:
   cache-related registers config
-CONFIG_SYS_SDRAM_BASE:
+CFG_SYS_SDRAM_BASE:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_SIZE:
+CFG_SYS_SDRAM_SIZE:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_BASEX:
+CFG_SYS_SDRAM_BASEX:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CFG1:
+CFG_SYS_SDRAM_CFG1:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CFG2:
+CFG_SYS_SDRAM_CFG2:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CTRL:
+CFG_SYS_SDRAM_CTRL:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_MODE:
+CFG_SYS_SDRAM_MODE:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_EMOD:
+CFG_SYS_SDRAM_EMOD:
   SDRAM config for SDRAM controller-specific registers, please
   see arch/m68k/cpu/<specific_cpu>/start.S files to see how
   these options are used.
 CONFIG_MCFUART:
   defines enabling of ColdFire UART driver
-CONFIG_SYS_UART_PORT:
+CFG_SYS_UART_PORT:
   defines the UART port to be used (only a single UART can be actually enabled)
-CONFIG_SYS_SBFHDR_SIZE:
+CFG_SYS_SBFHDR_SIZE:
   size of the prepended SBF header, if any

diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst
index 35defb0..34a75e7 100644
--- a/doc/arch/nios2.rst
+++ b/doc/arch/nios2.rst

@@ -96,8 +96,8 @@
 
 .. code-block:: c
 
-   #define CONFIG_SYS_SDRAM_BASE		0xc8000000
-   #define CONFIG_SYS_SDRAM_SIZE		0x08000000
+   #define CFG_SYS_SDRAM_BASE		0xc8000000
+   #define CFG_SYS_SDRAM_SIZE		0x08000000
 
 You will need to change the environment variables location and setting,
 too. You may change other configs to fit your board.

diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
index 34c4e06..e6d8403 100644
--- a/doc/arch/sandbox/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst

@@ -56,11 +56,8 @@
 
 Note: If you get errors about 'sdl-config: Command not found' you may need to
 install libsdl2.0-dev or similar to get SDL support. Alternatively you can
-build sandbox without SDL (i.e. no display/keyboard support) by removing
-the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using::
-
-   make sandbox_defconfig all NO_SDL=1
-   ./u-boot
+build sandbox without SDL (i.e. no display/keyboard support) by disabling
+CONFIG_SANDBOX_SDL in the .config file.
 
 U-Boot will start on your computer, showing a sandbox emulation of the serial
 console::
@@ -84,7 +81,7 @@
 Console / LCD support
 ---------------------
 
-Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the
+Assuming that CONFIG_SANDBOX_SDL is enabled when building, you can run the
 sandbox with LCD and keyboard emulation, using something like::
 
    ./u-boot -d u-boot.dtb -l

diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst
index a90f32d..0b230cf 100644
--- a/doc/board/ti/am335x_evm.rst
+++ b/doc/board/ti/am335x_evm.rst

@@ -54,7 +54,7 @@
 	CONFIG_SYS_NAND_PAGE_SIZE	number of main bytes in NAND page
 	CONFIG_SYS_NAND_OOBSIZE		number of OOB bytes in NAND page
 	CONFIG_SYS_NAND_BLOCK_SIZE	number of bytes in NAND erase-block
-	CONFIG_SYS_NAND_ECCPOS		ECC map for NAND page
+	CFG_SYS_NAND_ECCPOS		ECC map for NAND page
 	CONFIG_NAND_OMAP_ECCSCHEME	(refer doc/README.nand)
 
 Step-2: Flashing NAND via MMC/SD

diff --git a/doc/build/tools.rst b/doc/build/tools.rst
index c06f915..ec017229 100644
--- a/doc/build/tools.rst
+++ b/doc/build/tools.rst

@@ -44,4 +44,4 @@
 Launch the MSYS2 shell of the MSYS2 environment, and do the following::
 
    $ make tools-only_defconfig
-   $ make tools-only NO_SDL=1
+   $ make tools-only

diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst
index 43665de..fe1ae21 100644
--- a/doc/develop/driver-model/migration.rst
+++ b/doc/develop/driver-model/migration.rst

@@ -99,7 +99,7 @@
 Maintainers should submit patches switching over to using CONFIG_DM_I2C and
 other base driver model options in time for inclusion in the 2021.10 release.
 
-CONFIG_SYS_TIMER_RATE and CONFIG_SYS_TIMER_COUNTER
+CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER
 --------------------------------------------------
 Deadline: 2023.01
 

diff --git a/doc/device-tree-bindings/video/exynos-dp.txt b/doc/device-tree-bindings/video/exynos-dp.txt
index 464a853..273d8fc 100644
--- a/doc/device-tree-bindings/video/exynos-dp.txt
+++ b/doc/device-tree-bindings/video/exynos-dp.txt

@@ -30,9 +30,9 @@
 		8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32),
 		10(MOBILE_WHITEBAR_64)
 	samsung,h-sync-polarity: Horizontal Sync polarity
-			CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+			CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,v-sync-polarity: Vertical Sync polarity
-			CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+			CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,interlaced: Progressive if 0, else Interlaced
 	samsung,color-space: input video data format
 		COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2

diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt
index b022f61..bff0cecf 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt

@@ -23,15 +23,15 @@
 	samsung,vl-height: Height of display area in mm
 
 	samsung,vl-clkp: Clock polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,vl-oep: Output Enable polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,vl-hsp: Horizontal Sync polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,vl-vsp: Vertical Sync polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,vl-dp: Data polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 
 	samsung,vl-cmd-allow-len: Wait end of frame
 	samsung,winid: Window number on which data is to be displayed

diff --git a/doc/imx/common/imx5.txt b/doc/imx/common/imx5.txt
index ea0e144..6c8c2e5 100644
--- a/doc/imx/common/imx5.txt
+++ b/doc/imx/common/imx5.txt

@@ -16,7 +16,7 @@
     of frequency deviation), avoiding system failure, or at least decreasing
     the likelihood of system failure.
 
-1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+1.2 CFG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
     This option should be enabled for boards having a SYS_ON_OFF_CTL signal
     connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
     reference designs.

diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst
index 15897f6..83f210d 100644
--- a/doc/usage/environment.rst
+++ b/doc/usage/environment.rst

@@ -162,7 +162,7 @@
     for use by the bootm command. See also "bootm_size"
     environment variable. Address defined by "bootm_low" is
     also the base of the initial memory mapping for the Linux
-    kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
+    kernel -- see the description of CFG_SYS_BOOTMAPSZ and
     bootm_mapsize.
 
 bootm_mapsize
@@ -170,7 +170,7 @@
     This variable is given as a hexadecimal number and it
     defines the size of the memory region starting at base
     address bootm_low that is accessible by the Linux kernel
-    during early boot.  If unset, CONFIG_SYS_BOOTMAPSZ is used
+    during early boot.  If unset, CFG_SYS_BOOTMAPSZ is used
     as the default value if it is defined, and bootm_size is
     used otherwise.
 
@@ -228,7 +228,7 @@
     is usually what you want since it allows for
     maximum initrd size. If for some reason you want to
     make sure that the initrd image is loaded below the
-    CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
+    CFG_SYS_BOOTMAPSZ limit, you can set this environment
     variable to a value of "no" or "off" or "0".
     Alternatively, you can set it to a maximum upper
     address to use (U-Boot will still check that it

diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index 8d6424c..570252d 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig

@@ -83,7 +83,7 @@
 	bool "Boot counter on I2C device"
 	help
 	  Enable support for the bootcounter on an i2c (like RTC) device.
-	  CONFIG_SYS_I2C_RTC_ADDR = i2c chip address
+	  CFG_SYS_I2C_RTC_ADDR = i2c chip address
 	  CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
 	                              the bootcounter.
 

diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c
index 496741d..b3ac67e 100644
--- a/drivers/bootcount/bootcount_i2c.c
+++ b/drivers/bootcount/bootcount_i2c.c

@@ -17,7 +17,7 @@
 
 	buf[0] = BC_MAGIC;
 	buf[1] = (a & 0xff);
-	ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+	ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
 		  CONFIG_BOOTCOUNT_ALEN, buf, 2);
 	if (ret != 0)
 		puts("Error writing bootcount\n");
@@ -28,7 +28,7 @@
 	unsigned char buf[3];
 	int ret;
 
-	ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+	ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
 		       CONFIG_BOOTCOUNT_ALEN, buf, 2);
 	if (ret != 0) {
 		puts("Error loading bootcount\n");

diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c
index b2bfb52..2fdc2fb 100644
--- a/drivers/clk/at91/compat.c
+++ b/drivers/clk/at91/compat.c

@@ -150,7 +150,7 @@
 
 static ulong at91_slow_clk_get_rate(struct clk *clk)
 {
-	return CONFIG_SYS_AT91_SLOW_CLOCK;
+	return CFG_SYS_AT91_SLOW_CLOCK;
 }
 
 static struct clk_ops at91_slow_clk_ops = {

diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index b79e99b..8fde77c 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig

@@ -14,7 +14,7 @@
 	help
 	  Enable driver model in SPL. You will need to provide a
 	  suitable malloc() implementation. If you are not using the
-	  full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+	  full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
 	  consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. In that case you
 	  must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
 	  In most cases driver model will only allocate a few uclasses
@@ -27,7 +27,7 @@
 	help
 	  Enable driver model in TPL. You will need to provide a
 	  suitable malloc() implementation. If you are not using the
-	  full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+	  full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
 	  consider using CONFIG_TPL_SYS_MALLOC_SIMPLE. In that case you
 	  must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
 	  In most cases driver model will only allocate a few uclasses
@@ -42,7 +42,7 @@
 	help
 	  Enable driver model in VPL. You will need to provide a
 	  suitable malloc() implementation. If you are not using the
-	  full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+	  full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
 	  consider using CONFIG_SPL_SYS_MALLOC_SIMPLE.
 
 config DM_WARN

diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
index 738b788..fa873cc 100644
--- a/drivers/ddr/Kconfig
+++ b/drivers/ddr/Kconfig

@@ -37,3 +37,11 @@
 
 source "drivers/ddr/altera/Kconfig"
 source "drivers/ddr/imx/Kconfig"
+
+config SPD_EEPROM
+	bool "DDR controller makes use of an SPD EEPROM for JEDEC information"
+	depends on SYS_FSL_DDR || SYS_FSL_MMDC || CONFIG_ARMADA_XP
+	help
+	  Get DDR timing information from an I2C EEPROM. Common with pluggable
+	  memory modules such as SODIMMs. You must define SPD_EEPROM_ADDRESS
+	  to the I2C address of the SPD EEPROM.

diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 5e8fb7a..9dada5e 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c

@@ -130,7 +130,7 @@
 	if (is_warm_boot()) {
 		ddr_out32(&ddr->sdram_cfg_2,
 			  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
-		ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
 		ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 
 		/* DRAM VRef will not be trained */

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 3c1f7a1..f8d1468 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c

@@ -230,7 +230,7 @@
 	if (is_warm_boot()) {
 		ddr_out32(&ddr->sdram_cfg_2,
 			  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
-		ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
 		ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 
 		/* DRAM VRef will not be trained */

diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index fcff223..cd33271 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c

@@ -22,7 +22,7 @@
 
 /*
  * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
- * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
+ * of DDR controllers. It is the same as CFG_SYS_DDR_SDRAM_BASE for
  * all Power SoCs. But it could be different for ARM SoCs. For example,
  * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
  * 0x00_8000_0000 ~ 0x00_ffff_ffff
@@ -30,9 +30,9 @@
  */
 #ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
 #ifdef CONFIG_MPC83xx
-#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE
 #else
-#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE
 #endif
 #endif
 

diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 0f2dc24..1c4a1ca 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c

@@ -162,7 +162,7 @@
 	if (is_warm_boot()) {
 		out_be32(&ddr->sdram_cfg_2,
 			 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
-		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
 		out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 
 		/* DRAM VRef will not be trained */

diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h
index a14c766..c40cd76 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp.h

@@ -19,10 +19,10 @@
 #define FAR_END_DIMM_ADDR		0x50
 #define MAX_DIMM_ADDR			0x60
 
-#ifndef CONFIG_SYS_SDRAM_SIZE
+#ifndef CFG_SYS_SDRAM_SIZE
 #define SDRAM_CS_SIZE			0xFFFFFFF
 #else
-#define SDRAM_CS_SIZE			((CONFIG_SYS_SDRAM_SIZE >> 10) - 1)
+#define SDRAM_CS_SIZE			((CFG_SYS_SDRAM_SIZE >> 10) - 1)
 #endif
 #define SDRAM_CS_BASE			0x0
 #define SDRAM_DIMM_SIZE			0x80000000

diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c
index a1ff470..ca49ee4 100644
--- a/drivers/fpga/ACEX1K.c
+++ b/drivers/fpga/ACEX1K.c

@@ -24,8 +24,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10		/* 100 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10		/* 100 ms */
 #endif
 
 static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
@@ -138,7 +138,7 @@
 		ts = get_timer (0);		/* get current time */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for STATUS to go high.\n");
 				(*fn->abort) (cookie);
 				return FPGA_FAIL;

diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c
index f264ff8..3eed461 100644
--- a/drivers/fpga/cyclon2.c
+++ b/drivers/fpga/cyclon2.c

@@ -22,8 +22,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10		/* 100 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10		/* 100 ms */
 #endif
 
 static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
@@ -130,7 +130,7 @@
 		ts = get_timer(0);		/* get current time */
 		do {
 			CONFIG_FPGA_DELAY();
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 				/* check the time */
 				puts("** Timeout waiting for STATUS to go high.\n");
 				(*fn->abort) (cookie);

diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index f72dfde..57a4532 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c

@@ -21,8 +21,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
 static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -149,7 +149,7 @@
 		/* Now wait for INIT and BUSY to go high */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to clear.\n");
 				(*fn->abort) (cookie);	/* abort the burn */
 				return FPGA_FAIL;
@@ -182,7 +182,7 @@
 				CONFIG_FPGA_DELAY ();
 				(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-				if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+				if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 					puts ("** Timeout waiting for BUSY to clear.\n");
 					(*fn->abort) (cookie);	/* abort the burn */
 					return FPGA_FAIL;
@@ -214,7 +214,7 @@
 			CONFIG_FPGA_DELAY ();
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
 				(*fn->abort) (cookie);	/* abort the burn */
 				ret_val = FPGA_FAIL;
@@ -333,7 +333,7 @@
 		ts = get_timer (0);		/* get current time */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to start.\n");
 				return FPGA_FAIL;
 			}
@@ -347,7 +347,7 @@
 		/* Now wait for INIT to go high */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to clear.\n");
 				return FPGA_FAIL;
 			}
@@ -404,7 +404,7 @@
 
 			putc ('*');
 
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
 				ret_val = FPGA_FAIL;
 				break;

diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index b7a063a..fdec89b 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c

@@ -26,8 +26,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
 static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -154,7 +154,7 @@
 		/* Now wait for INIT and BUSY to go high */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to clear.\n");
 				(*fn->abort) (cookie);	/* abort the burn */
 				return FPGA_FAIL;
@@ -187,7 +187,7 @@
 				CONFIG_FPGA_DELAY ();
 				(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-				if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+				if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 					puts ("** Timeout waiting for BUSY to clear.\n");
 					(*fn->abort) (cookie);	/* abort the burn */
 					return FPGA_FAIL;
@@ -221,7 +221,7 @@
 			CONFIG_FPGA_DELAY ();
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
 				(*fn->abort) (cookie);	/* abort the burn */
 				ret_val = FPGA_FAIL;
@@ -340,7 +340,7 @@
 		ts = get_timer (0);		/* get current time */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to start.\n");
 				if (*fn->abort)
 					(*fn->abort) (cookie);
@@ -356,7 +356,7 @@
 		/* Now wait for INIT to go high */
 		do {
 			CONFIG_FPGA_DELAY ();
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for INIT to clear.\n");
 				if (*fn->abort)
 					(*fn->abort) (cookie);
@@ -423,7 +423,7 @@
 
 			putc ('*');
 
-			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");
 				ret_val = FPGA_FAIL;
 				break;

diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 0d536f0..8871dea 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c

@@ -49,8 +49,8 @@
  * which yields 11.44 mS.  So let's make it bigger in order to handle
  * an XC2V1000, if anyone can ever get ahold of one.
  */
-#ifndef CONFIG_SYS_FPGA_WAIT_INIT
-#define CONFIG_SYS_FPGA_WAIT_INIT	CONFIG_SYS_HZ / 2	/* 500 ms */
+#ifndef CFG_SYS_FPGA_WAIT_INIT
+#define CFG_SYS_FPGA_WAIT_INIT	CONFIG_SYS_HZ / 2	/* 500 ms */
 #endif
 
 /*
@@ -58,15 +58,15 @@
  * This is normally not necessary since for most reasonable configuration
  * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
  */
-#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
-#define CONFIG_SYS_FPGA_WAIT_BUSY	CONFIG_SYS_HZ / 200	/* 5 ms*/
+#ifndef CFG_SYS_FPGA_WAIT_BUSY
+#define CFG_SYS_FPGA_WAIT_BUSY	CONFIG_SYS_HZ / 200	/* 5 ms*/
 #endif
 
 /* Default timeout for waiting for FPGA to enter operational mode after
  * configuration data has been written.
  */
-#ifndef	CONFIG_SYS_FPGA_WAIT_CONFIG
-#define CONFIG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ / 5	/* 200 ms */
+#ifndef	CFG_SYS_FPGA_WAIT_CONFIG
+#define CFG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ / 5	/* 200 ms */
 #endif
 
 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -190,9 +190,9 @@
 	udelay(10);
 	ts = get_timer(0);
 	do {
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
 			printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
-			       __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+			       __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
 			(*fn->abort)(cookie);
 			return FPGA_FAIL;
 		}
@@ -209,9 +209,9 @@
 	ts = get_timer(0);
 	do {
 		CONFIG_FPGA_DELAY();
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
 			printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
-			       __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+			       __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
 			(*fn->abort)(cookie);
 			return FPGA_FAIL;
 		}
@@ -260,9 +260,9 @@
 				break;
 		}
 
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) {
 			printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
-			       __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
+			       __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG);
 			(*fn->abort)(cookie);
 			ret_val = FPGA_FAIL;
 			break;
@@ -350,10 +350,10 @@
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
 		ts = get_timer(0);
 		while ((*fn->busy)(cookie)) {
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) {
 				printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
 				       __func__, __LINE__,
-				       CONFIG_SYS_FPGA_WAIT_BUSY);
+				       CFG_SYS_FPGA_WAIT_BUSY);
 				(*fn->abort)(cookie);
 				return FPGA_FAIL;
 			}

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 0c83df4..53dd780 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c

@@ -36,8 +36,8 @@
 #define DEVCFG_MCTRL_RFIFO_FLUSH	0x00000002
 #define DEVCFG_MCTRL_WFIFO_FLUSH	0x00000001
 
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
 #ifndef CONFIG_SYS_FPGA_PROG_TIME
@@ -232,7 +232,7 @@
 		/* Polling the PCAP_INIT status for Reset */
 		ts = get_timer(0);
 		while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 				printf("%s: Timeout wait for INIT to clear\n",
 				       __func__);
 				return FPGA_FAIL;
@@ -246,7 +246,7 @@
 		ts = get_timer(0);
 		while (!(readl(&devcfg_base->status) &
 			DEVCFG_STATUS_PCFG_INIT)) {
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 				printf("%s: Timeout wait for INIT to set\n",
 				       __func__);
 				return FPGA_FAIL;
@@ -400,7 +400,7 @@
 	/* Check FPGA configuration completion */
 	ts = get_timer(0);
 	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 			printf("%s: Timeout wait for FPGA to config\n",
 			       __func__);
 			return FPGA_FAIL;
@@ -484,7 +484,7 @@
 	/* Check FPGA configuration completion */
 	ts = get_timer(0);
 	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
-		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+		if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 			printf("%s: Timeout wait for FPGA to config\n",
 			       __func__);
 			return FPGA_FAIL;
@@ -561,7 +561,7 @@
 		/* Check FPGA configuration completion */
 		ts = get_timer(0);
 		while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
-			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+			if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
 				printf("%s: Timeout wait for FPGA to config\n",
 				       __func__);
 				return FPGA_FAIL;

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index ff87fbf..365615a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig

@@ -169,6 +169,10 @@
 	  This driver supports the Fairchild FXL6408 device. FXL6408 is a
 	  fully configurable 8-bit I2C-controlled GPIO expander.
 
+config HIKEY_GPIO
+	bool "HI6220 GPIO driver"
+	depends on DM_GPIO
+
 config INTEL_BROADWELL_GPIO
 	bool "Intel Broadwell GPIO driver"
 	depends on DM
@@ -374,8 +378,13 @@
 	help
 	  This config enable the Xilinx GPIO driver for Microblaze.
 
+config TCA642X
+	bool "TCA642x legacy GPIO driver"
+
 config CMD_TCA642X
 	bool "tca642x - Command to access tca642x state"
+	depends on TCA642X
+	default y
 	help
 	  DEPRECATED - This needs conversion to driver model
 
@@ -511,6 +520,10 @@
 	  Now, max 24 bits chips and PCA953X compatible chips are
 	  supported
 
+config PCA953X
+	bool "NXP's PCA953X series I2C GPIO (legacy driver)"
+	depends on !DM_PCA953X
+
 config MPC8XXX_GPIO
 	bool "Freescale MPC8XXX GPIO driver"
 	depends on DM_GPIO
@@ -583,6 +596,11 @@
 	  are accessed using xilinx firmware. In modepin register, [3:0] bits
 	  set direction, [7:4] bits read IO, [11:8] bits set/clear IO.
 
+config SH_GPIO_PFC
+	bool "Pinmuxed GPIO support for SuperH"
+	depends on RCAR_GEN2 && !PINCTRL_PFC
+	default y
+
 config SL28CPLD_GPIO
 	bool "Kontron sl28cpld GPIO driver"
 	depends on DM_GPIO && SL28CPLD

diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 03471db..1dec4e3 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c

@@ -44,13 +44,13 @@
 	[0] = GPIO1_BASE_ADDR,
 	[1] = GPIO2_BASE_ADDR,
 	[2] = GPIO3_BASE_ADDR,
-#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
 		defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
 	[3] = GPIO4_BASE_ADDR,
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
 		defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
 	[4] = GPIO5_BASE_ADDR,
@@ -352,12 +352,12 @@
 	{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
 	{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
 	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
-#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
 #ifndef CONFIG_IMX8M
@@ -376,12 +376,12 @@
 	{ "gpio_mxc", &mxc_plat[0] },
 	{ "gpio_mxc", &mxc_plat[1] },
 	{ "gpio_mxc", &mxc_plat[2] },
-#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ "gpio_mxc", &mxc_plat[3] },
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ "gpio_mxc", &mxc_plat[4] },
 #ifndef CONFIG_IMX8M

diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index 2fd2996..b5ed352 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c

@@ -14,8 +14,8 @@
 #include <pca953x.h>
 
 /* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_PCA953X_ADDR
-#define CONFIG_SYS_I2C_PCA953X_ADDR	(~0)
+#ifndef CFG_SYS_I2C_PCA953X_ADDR
+#define CFG_SYS_I2C_PCA953X_ADDR	(~0)
 #endif
 
 enum {
@@ -26,14 +26,14 @@
 	PCA953X_CMD_INVERT,
 };
 
-#ifdef CONFIG_SYS_I2C_PCA953X_WIDTH
+#ifdef CFG_SYS_I2C_PCA953X_WIDTH
 struct pca953x_chip_ngpio {
 	uint8_t chip;
 	uint8_t ngpio;
 };
 
 static struct pca953x_chip_ngpio pca953x_chip_ngpios[] =
-    CONFIG_SYS_I2C_PCA953X_WIDTH;
+    CFG_SYS_I2C_PCA953X_WIDTH;
 
 /*
  * Determine the number of GPIO pins supported. If we don't know we assume
@@ -204,7 +204,7 @@
 static int do_pca953x(struct cmd_tbl *cmdtp, int flag, int argc,
 		      char *const argv[])
 {
-	static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
+	static uint8_t chip = CFG_SYS_I2C_PCA953X_ADDR;
 	int ret = CMD_RET_USAGE, val;
 	ulong ul_arg2 = 0;
 	ulong ul_arg3 = 0;

diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c
index 7f67f96..b07496e 100644
--- a/drivers/gpio/tca642x.c
+++ b/drivers/gpio/tca642x.c

@@ -52,7 +52,7 @@
 	int ret;
 
 	org_bus_num = i2c_get_bus_num();
-	i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+	i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM);
 
 	if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) {
 		printf("Could not read before writing\n");
@@ -76,7 +76,7 @@
 	int ret = 0;
 
 	org_bus_num = i2c_get_bus_num();
-	i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+	i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM);
 	if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) {
 		ret = -1;
 		goto error;
@@ -242,7 +242,7 @@
 static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc,
 		      char *const argv[])
 {
-	static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR;
+	static uchar chip = CFG_SYS_I2C_TCA642X_ADDR;
 	int ret = CMD_RET_USAGE, val;
 	int gpio_bank = 0;
 	uint8_t bank_shift;

diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c
index ae17722..25ef937 100644
--- a/drivers/i2c/davinci_i2c.c
+++ b/drivers/i2c/davinci_i2c.c

@@ -91,7 +91,7 @@
 
 	psc = 2;
 	/* SCLL + SCLH */
-	div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
+	div = (CFG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
 	REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
 	REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
 	REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index edbcd83..187db92 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c

@@ -41,7 +41,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_M68K
-#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_IMMR		CFG_SYS_MBAR
 #endif
 
 #if !CONFIG_IS_ENABLED(DM_I2C)

diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 09f91e6..7f65db2 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c

@@ -34,8 +34,8 @@
 }
 
 #if !defined(CONFIG_SYS_I2C_DIRECT_BUS)
-struct i2c_bus_hose i2c_bus[CONFIG_SYS_NUM_I2C_BUSES] =
-			CONFIG_SYS_I2C_BUSES;
+struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] =
+			CFG_SYS_I2C_BUSES;
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -114,7 +114,7 @@
 	/* Connect requested bus if behind muxes */
 	if (i2c_bus_tmp->next_hop[0].chip != 0) {
 		/* Set all muxes along the path to that bus */
-		for (i = 0; i < CONFIG_SYS_I2C_MAX_HOPS; i++) {
+		for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) {
 			int	ret;
 
 			if (i2c_bus_tmp->next_hop[i].chip == 0)
@@ -143,7 +143,7 @@
 	/* Disconnect current bus (turn off muxes if any) */
 	if ((i2c_bus_tmp->next_hop[0].chip != 0) &&
 	    (I2C_ADAP->init_done != 0)) {
-		i = CONFIG_SYS_I2C_MAX_HOPS;
+		i = CFG_SYS_I2C_MAX_HOPS;
 		do {
 			uint8_t	chip;
 			int ret;
@@ -173,7 +173,7 @@
  */
 static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr)
 {
-	if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES)
+	if (bus_no >= CFG_SYS_NUM_I2C_BUSES)
 		return;
 
 	I2C_ADAP->init(I2C_ADAP, speed, slaveaddr);
@@ -238,7 +238,7 @@
 		return 0;
 
 #ifndef CONFIG_SYS_I2C_DIRECT_BUS
-	if (bus >= CONFIG_SYS_NUM_I2C_BUSES)
+	if (bus >= CFG_SYS_NUM_I2C_BUSES)
 		return -1;
 #endif
 

diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c
index 4edcba2..b9b0ff1 100644
--- a/drivers/i2c/kona_i2c.c
+++ b/drivers/i2c/kona_i2c.c

@@ -129,7 +129,7 @@
 #define DEF_DEVICE(num) \
 {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
 
-static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
+static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = {
 #ifdef CONFIG_SYS_I2C_BASE0
 	DEF_DEVICE(0),
 #endif

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index f48a4f2..a9c7d6e 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c

@@ -42,7 +42,7 @@
 #endif /* CONFIG_DM_I2C */
 
 /*
- * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
+ * On SUNXI, we get CFG_SYS_TCLK from this include, so we want to
  * always have it.
  */
 #if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_ARCH_SUNXI)
@@ -427,9 +427,9 @@
 static uint twsi_calc_freq(const int n, const int m)
 {
 #ifdef CONFIG_ARCH_SUNXI
-	return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
+	return CFG_SYS_TCLK / (10 * (m + 1) * (1 << n));
 #else
-	return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
+	return CFG_SYS_TCLK / (10 * (m + 1) * (2 << n));
 #endif
 }
 

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index f80ff53..9a1599d 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c

@@ -39,8 +39,8 @@
 #define VF610_I2C_REGSHIFT	0
 
 #define I2C_EARLY_INIT_INDEX		0
-#ifdef CONFIG_SYS_I2C_IFDR_DIV
-#define I2C_IFDR_DIV_CONSERVATIVE	CONFIG_SYS_I2C_IFDR_DIV
+#ifdef CFG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE	CFG_SYS_I2C_IFDR_DIV
 #else
 #define I2C_IFDR_DIV_CONSERVATIVE	0x7e
 #endif

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index a6da6e2..b07261d 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig

@@ -112,6 +112,12 @@
 	  Enable support for reading and writing the eMemory OTP on the
 	  SiFive SoCs.
 
+config SMSC_LPC47M
+	bool "LPC47M SMSC driver"
+
+config SMSC_SIO1007
+	bool "SIO1007 SMSC driver"
+
 config VEXPRESS_CONFIG
 	bool "Enable support for Arm Versatile Express config bus"
 	depends on MISC
@@ -267,6 +273,10 @@
 	  and a configurable timer for the supervisor function. The device is
 	  connected over I2C.
 
+config FSL_IIM
+	bool "Enable FSL IC Identification Module (IIM) driver"
+	depends on ARCH_MX31 || ARCH_MX5
+
 config FSL_SEC_MON
 	bool "Enable FSL SEC_MON Driver"
 	help
@@ -326,6 +336,14 @@
 	  Programmable memory pages that are stored on the some
 	  Freescale i.MX processors.
 
+config MXS_OCOTP
+	bool "Enable MXS OCOTP Driver"
+	depends on ARCH_MX23 || ARCH_MX28
+	help
+	  If you say Y here, you will get support for the One Time
+	  Programmable memory pages that are stored on the
+	  Freescale i.MXS family of processors.
+
 config NPCM_HOST
 	bool "Enable support espi or LPC for Host"
 	depends on REGMAP && SYSCON

diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c
index 8fdaacd..58b0058 100644
--- a/drivers/misc/fsl_ifc.c
+++ b/drivers/misc/fsl_ifc.c

@@ -12,37 +12,37 @@
 struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 	{
 		"cs0",
-#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
-		CONFIG_SYS_CSPR0,
-#ifdef CONFIG_SYS_CSPR0_EXT
-		CONFIG_SYS_CSPR0_EXT,
+#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0)
+		CFG_SYS_CSPR0,
+#ifdef CFG_SYS_CSPR0_EXT
+		CFG_SYS_CSPR0_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK0
-		CONFIG_SYS_AMASK0,
+#ifdef CFG_SYS_AMASK0
+		CFG_SYS_AMASK0,
 #else
 		0,
 #endif
-		CONFIG_SYS_CSOR0,
+		CFG_SYS_CSOR0,
 		{
-			CONFIG_SYS_CS0_FTIM0,
-			CONFIG_SYS_CS0_FTIM1,
-			CONFIG_SYS_CS0_FTIM2,
-			CONFIG_SYS_CS0_FTIM3,
+			CFG_SYS_CS0_FTIM0,
+			CFG_SYS_CS0_FTIM1,
+			CFG_SYS_CS0_FTIM2,
+			CFG_SYS_CS0_FTIM3,
 		},
-#ifdef CONFIG_SYS_CSOR0_EXT
-		CONFIG_SYS_CSOR0_EXT,
+#ifdef CFG_SYS_CSOR0_EXT
+		CFG_SYS_CSOR0_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_CSPR0_FINAL
-		CONFIG_SYS_CSPR0_FINAL,
+#ifdef CFG_SYS_CSPR0_FINAL
+		CFG_SYS_CSPR0_FINAL,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK0_FINAL
-		CONFIG_SYS_AMASK0_FINAL,
+#ifdef CFG_SYS_AMASK0_FINAL
+		CFG_SYS_AMASK0_FINAL,
 #else
 		0,
 #endif
@@ -52,37 +52,37 @@
 #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2
 	{
 		"cs1",
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
-		CONFIG_SYS_CSPR1,
-#ifdef CONFIG_SYS_CSPR1_EXT
-		CONFIG_SYS_CSPR1_EXT,
+#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1)
+		CFG_SYS_CSPR1,
+#ifdef CFG_SYS_CSPR1_EXT
+		CFG_SYS_CSPR1_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK1
-		CONFIG_SYS_AMASK1,
+#ifdef CFG_SYS_AMASK1
+		CFG_SYS_AMASK1,
 #else
 		0,
 #endif
-		CONFIG_SYS_CSOR1,
+		CFG_SYS_CSOR1,
 		{
-			CONFIG_SYS_CS1_FTIM0,
-			CONFIG_SYS_CS1_FTIM1,
-			CONFIG_SYS_CS1_FTIM2,
-			CONFIG_SYS_CS1_FTIM3,
+			CFG_SYS_CS1_FTIM0,
+			CFG_SYS_CS1_FTIM1,
+			CFG_SYS_CS1_FTIM2,
+			CFG_SYS_CS1_FTIM3,
 		},
-#ifdef CONFIG_SYS_CSOR1_EXT
-		CONFIG_SYS_CSOR1_EXT,
+#ifdef CFG_SYS_CSOR1_EXT
+		CFG_SYS_CSOR1_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_CSPR1_FINAL
-		CONFIG_SYS_CSPR1_FINAL,
+#ifdef CFG_SYS_CSPR1_FINAL
+		CFG_SYS_CSPR1_FINAL,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK1_FINAL
-		CONFIG_SYS_AMASK1_FINAL,
+#ifdef CFG_SYS_AMASK1_FINAL
+		CFG_SYS_AMASK1_FINAL,
 #else
 		0,
 #endif
@@ -93,37 +93,37 @@
 #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3
 	{
 		"cs2",
-#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
-		CONFIG_SYS_CSPR2,
-#ifdef CONFIG_SYS_CSPR2_EXT
-		CONFIG_SYS_CSPR2_EXT,
+#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2)
+		CFG_SYS_CSPR2,
+#ifdef CFG_SYS_CSPR2_EXT
+		CFG_SYS_CSPR2_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK2
-		CONFIG_SYS_AMASK2,
+#ifdef CFG_SYS_AMASK2
+		CFG_SYS_AMASK2,
 #else
 		0,
 #endif
-		CONFIG_SYS_CSOR2,
+		CFG_SYS_CSOR2,
 		{
-			CONFIG_SYS_CS2_FTIM0,
-			CONFIG_SYS_CS2_FTIM1,
-			CONFIG_SYS_CS2_FTIM2,
-			CONFIG_SYS_CS2_FTIM3,
+			CFG_SYS_CS2_FTIM0,
+			CFG_SYS_CS2_FTIM1,
+			CFG_SYS_CS2_FTIM2,
+			CFG_SYS_CS2_FTIM3,
 		},
-#ifdef CONFIG_SYS_CSOR2_EXT
-		CONFIG_SYS_CSOR2_EXT,
+#ifdef CFG_SYS_CSOR2_EXT
+		CFG_SYS_CSOR2_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_CSPR2_FINAL
-		CONFIG_SYS_CSPR2_FINAL,
+#ifdef CFG_SYS_CSPR2_FINAL
+		CFG_SYS_CSPR2_FINAL,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK2_FINAL
-		CONFIG_SYS_AMASK2_FINAL,
+#ifdef CFG_SYS_AMASK2_FINAL
+		CFG_SYS_AMASK2_FINAL,
 #else
 		0,
 #endif
@@ -134,37 +134,37 @@
 #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4
 	{
 		"cs3",
-#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
-		CONFIG_SYS_CSPR3,
-#ifdef CONFIG_SYS_CSPR3_EXT
-		CONFIG_SYS_CSPR3_EXT,
+#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3)
+		CFG_SYS_CSPR3,
+#ifdef CFG_SYS_CSPR3_EXT
+		CFG_SYS_CSPR3_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK3
-		CONFIG_SYS_AMASK3,
+#ifdef CFG_SYS_AMASK3
+		CFG_SYS_AMASK3,
 #else
 		0,
 #endif
-		CONFIG_SYS_CSOR3,
+		CFG_SYS_CSOR3,
 		{
-			CONFIG_SYS_CS3_FTIM0,
-			CONFIG_SYS_CS3_FTIM1,
-			CONFIG_SYS_CS3_FTIM2,
-			CONFIG_SYS_CS3_FTIM3,
+			CFG_SYS_CS3_FTIM0,
+			CFG_SYS_CS3_FTIM1,
+			CFG_SYS_CS3_FTIM2,
+			CFG_SYS_CS3_FTIM3,
 		},
-#ifdef CONFIG_SYS_CSOR3_EXT
-		CONFIG_SYS_CSOR3_EXT,
+#ifdef CFG_SYS_CSOR3_EXT
+		CFG_SYS_CSOR3_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_CSPR3_FINAL
-		CONFIG_SYS_CSPR3_FINAL,
+#ifdef CFG_SYS_CSPR3_FINAL
+		CFG_SYS_CSPR3_FINAL,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK3_FINAL
-		CONFIG_SYS_AMASK3_FINAL,
+#ifdef CFG_SYS_AMASK3_FINAL
+		CFG_SYS_AMASK3_FINAL,
 #else
 		0,
 #endif
@@ -175,37 +175,37 @@
 #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5
 	{
 		"cs4",
-#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
-		CONFIG_SYS_CSPR4,
-#ifdef CONFIG_SYS_CSPR4_EXT
-		CONFIG_SYS_CSPR4_EXT,
+#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4)
+		CFG_SYS_CSPR4,
+#ifdef CFG_SYS_CSPR4_EXT
+		CFG_SYS_CSPR4_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK4
-		CONFIG_SYS_AMASK4,
+#ifdef CFG_SYS_AMASK4
+		CFG_SYS_AMASK4,
 #else
 		0,
 #endif
-		CONFIG_SYS_CSOR4,
+		CFG_SYS_CSOR4,
 		{
-			CONFIG_SYS_CS4_FTIM0,
-			CONFIG_SYS_CS4_FTIM1,
-			CONFIG_SYS_CS4_FTIM2,
-			CONFIG_SYS_CS4_FTIM3,
+			CFG_SYS_CS4_FTIM0,
+			CFG_SYS_CS4_FTIM1,
+			CFG_SYS_CS4_FTIM2,
+			CFG_SYS_CS4_FTIM3,
 		},
-#ifdef CONFIG_SYS_CSOR4_EXT
-		CONFIG_SYS_CSOR4_EXT,
+#ifdef CFG_SYS_CSOR4_EXT
+		CFG_SYS_CSOR4_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_CSPR4_FINAL
-		CONFIG_SYS_CSPR4_FINAL,
+#ifdef CFG_SYS_CSPR4_FINAL
+		CFG_SYS_CSPR4_FINAL,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK4_FINAL
-		CONFIG_SYS_AMASK4_FINAL,
+#ifdef CFG_SYS_AMASK4_FINAL
+		CFG_SYS_AMASK4_FINAL,
 #else
 		0,
 #endif
@@ -257,37 +257,37 @@
 #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7
 	{
 		"cs6",
-#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
-		CONFIG_SYS_CSPR6,
-#ifdef CONFIG_SYS_CSPR6_EXT
-		CONFIG_SYS_CSPR6_EXT,
+#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6)
+		CFG_SYS_CSPR6,
+#ifdef CFG_SYS_CSPR6_EXT
+		CFG_SYS_CSPR6_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK6
-		CONFIG_SYS_AMASK6,
+#ifdef CFG_SYS_AMASK6
+		CFG_SYS_AMASK6,
 #else
 		0,
 #endif
-		CONFIG_SYS_CSOR6,
+		CFG_SYS_CSOR6,
 		{
-			CONFIG_SYS_CS6_FTIM0,
-			CONFIG_SYS_CS6_FTIM1,
-			CONFIG_SYS_CS6_FTIM2,
-			CONFIG_SYS_CS6_FTIM3,
+			CFG_SYS_CS6_FTIM0,
+			CFG_SYS_CS6_FTIM1,
+			CFG_SYS_CS6_FTIM2,
+			CFG_SYS_CS6_FTIM3,
 		},
-#ifdef CONFIG_SYS_CSOR6_EXT
-		CONFIG_SYS_CSOR6_EXT,
+#ifdef CFG_SYS_CSOR6_EXT
+		CFG_SYS_CSOR6_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_CSPR6_FINAL
-		CONFIG_SYS_CSPR6_FINAL,
+#ifdef CFG_SYS_CSPR6_FINAL
+		CFG_SYS_CSPR6_FINAL,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK6_FINAL
-		CONFIG_SYS_AMASK6_FINAL,
+#ifdef CFG_SYS_AMASK6_FINAL
+		CFG_SYS_AMASK6_FINAL,
 #else
 		0,
 #endif
@@ -298,37 +298,37 @@
 #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8
 	{
 		"cs7",
-#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
-		CONFIG_SYS_CSPR7,
-#ifdef CONFIG_SYS_CSPR7_EXT
-		CONFIG_SYS_CSPR7_EXT,
+#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7)
+		CFG_SYS_CSPR7,
+#ifdef CFG_SYS_CSPR7_EXT
+		CFG_SYS_CSPR7_EXT,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK7
-		CONFIG_SYS_AMASK7,
+#ifdef CFG_SYS_AMASK7
+		CFG_SYS_AMASK7,
 #else
 		0,
 #endif
-		CONFIG_SYS_CSOR7,
-#ifdef CONFIG_SYS_CSOR7_EXT
-		CONFIG_SYS_CSOR7_EXT,
+		CFG_SYS_CSOR7,
+#ifdef CFG_SYS_CSOR7_EXT
+		CFG_SYS_CSOR7_EXT,
 #else
 		0,
 #endif
 		{
-			CONFIG_SYS_CS7_FTIM0,
-			CONFIG_SYS_CS7_FTIM1,
-			CONFIG_SYS_CS7_FTIM2,
-			CONFIG_SYS_CS7_FTIM3,
+			CFG_SYS_CS7_FTIM0,
+			CFG_SYS_CS7_FTIM1,
+			CFG_SYS_CS7_FTIM2,
+			CFG_SYS_CS7_FTIM3,
 		},
-#ifdef CONFIG_SYS_CSPR7_FINAL
-		CONFIG_SYS_CSPR7_FINAL,
+#ifdef CFG_SYS_CSPR7_FINAL
+		CFG_SYS_CSPR7_FINAL,
 #else
 		0,
 #endif
-#ifdef CONFIG_SYS_AMASK7_FINAL
-		CONFIG_SYS_AMASK7_FINAL,
+#ifdef CFG_SYS_AMASK7_FINAL
+		CFG_SYS_AMASK7_FINAL,
 #else
 		0,
 #endif
@@ -412,91 +412,91 @@
 #else
 void init_early_memctl_regs(void)
 {
-#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
-	set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
-	set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
-	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
-	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
+#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0)
+	set_ifc_ftim(IFC_CS0, IFC_FTIM0, CFG_SYS_CS0_FTIM0);
+	set_ifc_ftim(IFC_CS0, IFC_FTIM1, CFG_SYS_CS0_FTIM1);
+	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CFG_SYS_CS0_FTIM2);
+	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CFG_SYS_CS0_FTIM3);
 
 #ifndef CONFIG_A003399_NOR_WORKAROUND
-#ifdef CONFIG_SYS_CSPR0_EXT
-	set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
+#ifdef CFG_SYS_CSPR0_EXT
+	set_ifc_cspr_ext(IFC_CS0, CFG_SYS_CSPR0_EXT);
 #endif
-#ifdef CONFIG_SYS_CSOR0_EXT
-	set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+#ifdef CFG_SYS_CSOR0_EXT
+	set_ifc_csor_ext(IFC_CS0, CFG_SYS_CSOR0_EXT);
 #endif
-	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
-	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
-	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+	set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0);
+	set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0);
+	set_ifc_csor(IFC_CS0, CFG_SYS_CSOR0);
 #endif
 #endif
 
-#ifdef CONFIG_SYS_CSPR1_EXT
-	set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
+#ifdef CFG_SYS_CSPR1_EXT
+	set_ifc_cspr_ext(IFC_CS1, CFG_SYS_CSPR1_EXT);
 #endif
-#ifdef CONFIG_SYS_CSOR1_EXT
-	set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+#ifdef CFG_SYS_CSOR1_EXT
+	set_ifc_csor_ext(IFC_CS1, CFG_SYS_CSOR1_EXT);
 #endif
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
-	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
-	set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
-	set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
-	set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
+#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1)
+	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CFG_SYS_CS1_FTIM0);
+	set_ifc_ftim(IFC_CS1, IFC_FTIM1, CFG_SYS_CS1_FTIM1);
+	set_ifc_ftim(IFC_CS1, IFC_FTIM2, CFG_SYS_CS1_FTIM2);
+	set_ifc_ftim(IFC_CS1, IFC_FTIM3, CFG_SYS_CS1_FTIM3);
 
-	set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
-	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
-	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+	set_ifc_csor(IFC_CS1, CFG_SYS_CSOR1);
+	set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1);
+	set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1);
 #endif
 
-#ifdef CONFIG_SYS_CSPR2_EXT
-	set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
+#ifdef CFG_SYS_CSPR2_EXT
+	set_ifc_cspr_ext(IFC_CS2, CFG_SYS_CSPR2_EXT);
 #endif
-#ifdef CONFIG_SYS_CSOR2_EXT
-	set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
+#ifdef CFG_SYS_CSOR2_EXT
+	set_ifc_csor_ext(IFC_CS2, CFG_SYS_CSOR2_EXT);
 #endif
-#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
-	set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
-	set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
-	set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
-	set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
+#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2)
+	set_ifc_ftim(IFC_CS2, IFC_FTIM0, CFG_SYS_CS2_FTIM0);
+	set_ifc_ftim(IFC_CS2, IFC_FTIM1, CFG_SYS_CS2_FTIM1);
+	set_ifc_ftim(IFC_CS2, IFC_FTIM2, CFG_SYS_CS2_FTIM2);
+	set_ifc_ftim(IFC_CS2, IFC_FTIM3, CFG_SYS_CS2_FTIM3);
 
-	set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
-	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
-	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
+	set_ifc_csor(IFC_CS2, CFG_SYS_CSOR2);
+	set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2);
+	set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2);
 #endif
 
-#ifdef CONFIG_SYS_CSPR3_EXT
-	set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
+#ifdef CFG_SYS_CSPR3_EXT
+	set_ifc_cspr_ext(IFC_CS3, CFG_SYS_CSPR3_EXT);
 #endif
-#ifdef CONFIG_SYS_CSOR3_EXT
-	set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
+#ifdef CFG_SYS_CSOR3_EXT
+	set_ifc_csor_ext(IFC_CS3, CFG_SYS_CSOR3_EXT);
 #endif
-#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
-	set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
-	set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
-	set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
-	set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
+#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3)
+	set_ifc_ftim(IFC_CS3, IFC_FTIM0, CFG_SYS_CS3_FTIM0);
+	set_ifc_ftim(IFC_CS3, IFC_FTIM1, CFG_SYS_CS3_FTIM1);
+	set_ifc_ftim(IFC_CS3, IFC_FTIM2, CFG_SYS_CS3_FTIM2);
+	set_ifc_ftim(IFC_CS3, IFC_FTIM3, CFG_SYS_CS3_FTIM3);
 
-	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
-	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
-	set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
+	set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3);
+	set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3);
+	set_ifc_csor(IFC_CS3, CFG_SYS_CSOR3);
 #endif
 
-#ifdef CONFIG_SYS_CSPR4_EXT
-	set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#ifdef CFG_SYS_CSPR4_EXT
+	set_ifc_cspr_ext(IFC_CS4, CFG_SYS_CSPR4_EXT);
 #endif
-#ifdef CONFIG_SYS_CSOR4_EXT
-	set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
+#ifdef CFG_SYS_CSOR4_EXT
+	set_ifc_csor_ext(IFC_CS4, CFG_SYS_CSOR4_EXT);
 #endif
-#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
-	set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
-	set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
-	set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
-	set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4)
+	set_ifc_ftim(IFC_CS4, IFC_FTIM0, CFG_SYS_CS4_FTIM0);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM1, CFG_SYS_CS4_FTIM1);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM2, CFG_SYS_CS4_FTIM2);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM3, CFG_SYS_CS4_FTIM3);
 
-	set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
-	set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
-	set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+	set_ifc_cspr(IFC_CS4, CFG_SYS_CSPR4);
+	set_ifc_amask(IFC_CS4, CFG_SYS_AMASK4);
+	set_ifc_csor(IFC_CS4, CFG_SYS_CSOR4);
 #endif
 
 #ifdef CONFIG_SYS_CSPR5_EXT
@@ -516,66 +516,66 @@
 	set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
 #endif
 
-#ifdef CONFIG_SYS_CSPR6_EXT
-	set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#ifdef CFG_SYS_CSPR6_EXT
+	set_ifc_cspr_ext(IFC_CS6, CFG_SYS_CSPR6_EXT);
 #endif
-#ifdef CONFIG_SYS_CSOR6_EXT
-	set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
+#ifdef CFG_SYS_CSOR6_EXT
+	set_ifc_csor_ext(IFC_CS6, CFG_SYS_CSOR6_EXT);
 #endif
-#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
-	set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
-	set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
-	set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
-	set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6)
+	set_ifc_ftim(IFC_CS6, IFC_FTIM0, CFG_SYS_CS6_FTIM0);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM1, CFG_SYS_CS6_FTIM1);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM2, CFG_SYS_CS6_FTIM2);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM3, CFG_SYS_CS6_FTIM3);
 
-	set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
-	set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
-	set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+	set_ifc_cspr(IFC_CS6, CFG_SYS_CSPR6);
+	set_ifc_amask(IFC_CS6, CFG_SYS_AMASK6);
+	set_ifc_csor(IFC_CS6, CFG_SYS_CSOR6);
 #endif
 
-#ifdef CONFIG_SYS_CSPR7_EXT
-	set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#ifdef CFG_SYS_CSPR7_EXT
+	set_ifc_cspr_ext(IFC_CS7, CFG_SYS_CSPR7_EXT);
 #endif
-#ifdef CONFIG_SYS_CSOR7_EXT
-	set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
+#ifdef CFG_SYS_CSOR7_EXT
+	set_ifc_csor_ext(IFC_CS7, CFG_SYS_CSOR7_EXT);
 #endif
-#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
-	set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
-	set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
-	set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
-	set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7)
+	set_ifc_ftim(IFC_CS7, IFC_FTIM0, CFG_SYS_CS7_FTIM0);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM1, CFG_SYS_CS7_FTIM1);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM2, CFG_SYS_CS7_FTIM2);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM3, CFG_SYS_CS7_FTIM3);
 
-	set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
-	set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
-	set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+	set_ifc_cspr(IFC_CS7, CFG_SYS_CSPR7);
+	set_ifc_amask(IFC_CS7, CFG_SYS_AMASK7);
+	set_ifc_csor(IFC_CS7, CFG_SYS_CSOR7);
 #endif
 }
 
 void init_final_memctl_regs(void)
 {
-#ifdef CONFIG_SYS_CSPR0_FINAL
-	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
+#ifdef CFG_SYS_CSPR0_FINAL
+	set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0_FINAL);
 #endif
-#ifdef CONFIG_SYS_AMASK0_FINAL
-	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+#ifdef CFG_SYS_AMASK0_FINAL
+	set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0);
 #endif
-#ifdef CONFIG_SYS_CSPR1_FINAL
-	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
+#ifdef CFG_SYS_CSPR1_FINAL
+	set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1_FINAL);
 #endif
-#ifdef CONFIG_SYS_AMASK1_FINAL
-	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
+#ifdef CFG_SYS_AMASK1_FINAL
+	set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1_FINAL);
 #endif
-#ifdef CONFIG_SYS_CSPR2_FINAL
-	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
+#ifdef CFG_SYS_CSPR2_FINAL
+	set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2_FINAL);
 #endif
-#ifdef CONFIG_SYS_AMASK2_FINAL
-	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+#ifdef CFG_SYS_AMASK2_FINAL
+	set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2);
 #endif
-#ifdef CONFIG_SYS_CSPR3_FINAL
-	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
+#ifdef CFG_SYS_CSPR3_FINAL
+	set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3_FINAL);
 #endif
-#ifdef CONFIG_SYS_AMASK3_FINAL
-	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+#ifdef CFG_SYS_AMASK3_FINAL
+	set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3);
 #endif
 }
 #endif

diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 30a9409..6b83128 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c

@@ -20,25 +20,25 @@
 #endif
 #include <fsl_qbman.h>
 
-#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
-#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
+#define MAX_BPORTALS (CFG_SYS_BMAN_CINH_SIZE / CFG_SYS_BMAN_SP_CINH_SIZE)
+#define MAX_QPORTALS (CFG_SYS_QMAN_CINH_SIZE / CFG_SYS_QMAN_SP_CINH_SIZE)
 void setup_qbman_portals(void)
 {
-	void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
-				CONFIG_SYS_BMAN_SWP_ISDR_REG;
-	void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
-				CONFIG_SYS_QMAN_SWP_ISDR_REG;
+	void __iomem *bpaddr = (void *)CFG_SYS_BMAN_CINH_BASE +
+				CFG_SYS_BMAN_SWP_ISDR_REG;
+	void __iomem *qpaddr = (void *)CFG_SYS_QMAN_CINH_BASE +
+				CFG_SYS_QMAN_SWP_ISDR_REG;
 	struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
 
 	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
 #ifdef CONFIG_PHYS_64BIT
-	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+	out_be32(&qman->qcsp_bare, (u32)(CFG_SYS_QMAN_MEM_PHYS >> 32));
 #endif
-	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+	out_be32(&qman->qcsp_bar, (u32)CFG_SYS_QMAN_MEM_PHYS);
 #ifdef CONFIG_FSL_CORENET
 	int i;
 
-	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+	for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
 		u8 sdest = qp_info[i].sdest;
 		u16 fliodn = qp_info[i].fliodn;
 		u16 dliodn = qp_info[i].dliodn;
@@ -53,7 +53,7 @@
 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 	int i;
 
-	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+	for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
 		u8 sdest = qp_info[i].sdest;
 		u16 ficid = qp_info[i].ficid;
 		u16 dicid = qp_info[i].dicid;
@@ -68,10 +68,10 @@
 #endif
 
 	/* Change default state of BMan ISDR portals to all 1s */
-	inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
-			CONFIG_SYS_BMAN_SP_CINH_SIZE);
-	inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
-			CONFIG_SYS_QMAN_SP_CINH_SIZE);
+	inhibit_portals(bpaddr, CFG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
+			CFG_SYS_BMAN_SP_CINH_SIZE);
+	inhibit_portals(qpaddr, CFG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
+			CFG_SYS_QMAN_SP_CINH_SIZE);
 }
 
 void inhibit_portals(void __iomem *addr, int max_portals,
@@ -257,7 +257,7 @@
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+		for (j = 0; j < CFG_SYS_NUM_FMAN; j++) {
 			char name[] = "fman@0";
 
 			name[sizeof(name) - 2] = '0' + j;

diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c
index 321bd27..3597ee2 100644
--- a/drivers/misc/fsl_sec_mon.c
+++ b/drivers/misc/fsl_sec_mon.c

@@ -10,7 +10,7 @@
 static u32 get_sec_mon_state(void)
 {
 	struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
-						(CONFIG_SYS_SEC_MON_ADDR);
+						(CFG_SYS_SEC_MON_ADDR);
 	return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK;
 }
 
@@ -19,7 +19,7 @@
 	u32 sts;
 	int timeout = 10;
 	struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
-						(CONFIG_SYS_SEC_MON_ADDR);
+						(CFG_SYS_SEC_MON_ADDR);
 
 	sts = get_sec_mon_state();
 
@@ -120,7 +120,7 @@
 	u32 sts;
 	int timeout = 10;
 	struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
-						(CONFIG_SYS_SEC_MON_ADDR);
+						(CFG_SYS_SEC_MON_ADDR);
 
 	printf("SEC_MON state transitioning to Soft Fail.\n");
 	sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);

diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index aa00d7e..6d7c0cf 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c

@@ -9,7 +9,7 @@
 #include <mmc.h>
 #include <malloc.h>
 
-#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS
+#ifndef CFG_SYS_MMC_U_BOOT_OFFS
 extern uchar mmc_u_boot_offs[];
 #endif
 
@@ -97,7 +97,7 @@
 	}
 
 #ifdef CONFIG_FSL_CORENET
-	offset = CONFIG_SYS_MMC_U_BOOT_OFFS;
+	offset = CFG_SYS_MMC_U_BOOT_OFFS;
 #else
 	sector = 0;
 again:
@@ -153,16 +153,16 @@
 		val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i);
 		offset = (offset << 8) + val;
 	}
-#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS
+#ifndef CFG_SYS_MMC_U_BOOT_OFFS
 	offset += (ulong)&mmc_u_boot_offs - CONFIG_SPL_TEXT_BASE;
 #else
-	offset += CONFIG_SYS_MMC_U_BOOT_OFFS;
+	offset += CFG_SYS_MMC_U_BOOT_OFFS;
 #endif
 #endif
 	/*
 	* Load U-Boot image from mmc into RAM
 	*/
-	code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
+	code_len = CFG_SYS_MMC_U_BOOT_SIZE;
 	blk_start = offset / mmc->read_bl_len;
 	blk_off = offset % mmc->read_bl_len;
 	blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1;
@@ -176,7 +176,7 @@
 		blk_start++;
 	}
 	err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
-					(uchar *)CONFIG_SYS_MMC_U_BOOT_DST +
+					(uchar *)CFG_SYS_MMC_U_BOOT_DST +
 					(blk_off ? (mmc->read_bl_len - blk_off) : 0));
 	if (err != blk_cnt) {
 		puts("spl: mmc read failed!!\n");
@@ -189,18 +189,18 @@
 	 * after SDHC DMA transfer.
 	 */
 	if (blk_off)
-		memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST,
+		memcpy((uchar *)CFG_SYS_MMC_U_BOOT_DST,
 		       tmp_buf + blk_off, mmc->read_bl_len - blk_off);
 
 	/*
 	* Clean d-cache and invalidate i-cache, to
 	* make sure that no stale data is executed.
 	*/
-	flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE);
+	flush_cache(CFG_SYS_MMC_U_BOOT_DST, CFG_SYS_MMC_U_BOOT_SIZE);
 
 	/*
 	* Jump to U-Boot image
 	*/
-	uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START;
+	uboot = (void *)CFG_SYS_MMC_U_BOOT_START;
 	(*uboot)();
 }

diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 607a223..d91819a 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c

@@ -24,8 +24,8 @@
 #include <asm/arch/hardware.h>
 #include "atmel_mci.h"
 
-#ifndef CONFIG_SYS_MMC_CLK_OD
-# define CONFIG_SYS_MMC_CLK_OD	150000
+#ifndef CFG_SYS_MMC_CLK_OD
+# define CFG_SYS_MMC_CLK_OD	150000
 #endif
 
 #define MMC_DEFAULT_BLKLEN	512
@@ -448,9 +448,9 @@
 
 	/* Set default clocks and blocklen */
 #ifdef CONFIG_DM_MMC
-	mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+	mci_set_mode(dev, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
 #else
-	mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+	mci_set_mode(mmc, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
 #endif
 
 	return 0;

diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c
index b2d0fac..3ce7cbf 100644
--- a/drivers/mmc/sh_sdhi.c
+++ b/drivers/mmc/sh_sdhi.c

@@ -761,7 +761,7 @@
 	struct mmc *mmc;
 	struct sh_sdhi_host *host = NULL;
 
-	if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL)
+	if (ch >= CFG_SYS_SH_SDHI_NR_CHANNEL)
 		return -ENODEV;
 
 	host = malloc(sizeof(struct sh_sdhi_host));

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index fcdb450..d8e2dec 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig

@@ -212,6 +212,24 @@
 
 source "drivers/mtd/nand/Kconfig"
 
+config SYS_NAND_MAX_OOBFREE
+	int "Maximum number of free OOB regions supported"
+	depends on SAMSUNG_ONENAND || MTD_RAW_NAND
+	range 2 32
+	default 32
+	help
+	  Set the maximum number of free OOB regions supported.  Useful for
+	  reducing image size, especially with SPL.
+
+config SYS_NAND_MAX_ECCPOS
+	int "Maximum number of ECC bytes supported"
+	depends on SAMSUNG_ONENAND || MTD_RAW_NAND
+	range 48 2147483647
+	default 680
+	help
+	  Set the maximum number of ECC bytes supported.  Useful for reducing
+	  image size, especially with SPL.
+
 config SYS_NAND_MAX_CHIPS
 	int "NAND max chips"
 	depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \

diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index d34d8ee..c1cdd2c 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c

@@ -53,7 +53,7 @@
  * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
  *   Device IDs, Publication Number 25538 Revision A, November 8, 2001
  *
- * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
+ * Define CFG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
  * reading and writing ... (yes there is such a Hardware).
  */
 
@@ -119,14 +119,14 @@
 #else
 __weak phys_addr_t cfi_flash_bank_addr(int i)
 {
-	return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
+	return ((phys_addr_t [])CFG_SYS_FLASH_BANKS_LIST)[i];
 }
 #endif
 
 __weak unsigned long cfi_flash_bank_size(int i)
 {
-#ifdef CONFIG_SYS_FLASH_BANKS_SIZES
-	return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
+#ifdef CFG_SYS_FLASH_BANKS_SIZES
+	return ((unsigned long [])CFG_SYS_FLASH_BANKS_SIZES)[i];
 #else
 	return 0;
 #endif
@@ -178,7 +178,7 @@
  */
 #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \
 	(defined(CONFIG_SYS_MONITOR_BASE) && \
-	(CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE))
+	(CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE))
 static flash_info_t *flash_get_info(ulong base)
 {
 	int i;
@@ -227,7 +227,7 @@
 	int i;
 	int cword_offset;
 	int cp_offset;
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
 	u32 cmd_le = cpu_to_le32(cmd);
 #endif
 	uchar val;
@@ -235,7 +235,7 @@
 
 	for (i = info->portwidth; i > 0; i--) {
 		cword_offset = (info->portwidth - i) % info->chipwidth;
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
 		cp_offset = info->portwidth - i;
 		val = *((uchar *)&cmd_le + cword_offset);
 #else
@@ -292,7 +292,7 @@
 	uchar retval;
 
 	cp = flash_map(info, 0, offset);
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
 	retval = flash_read8(cp);
 #else
 	retval = flash_read8(cp + info->portwidth - 1);
@@ -335,7 +335,7 @@
 	for (x = 0; x < 4 * info->portwidth; x++)
 		debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
 #endif
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
 	retval = ((flash_read8(addr) << 16) |
 		  (flash_read8(addr + info->portwidth) << 24) |
 		  (flash_read8(addr + 2 * info->portwidth)) |
@@ -580,7 +580,7 @@
 #endif
 
 	/* Wait for command completion */
-#ifdef CONFIG_SYS_LOW_RES_TIMER
+#ifdef CFG_SYS_LOW_RES_TIMER
 	reset_timer();
 #endif
 	start = get_timer(0);
@@ -673,7 +673,7 @@
 #endif
 
 	/* Wait for command completion */
-#ifdef CONFIG_SYS_LOW_RES_TIMER
+#ifdef CFG_SYS_LOW_RES_TIMER
 	reset_timer();
 #endif
 	start = get_timer(0);
@@ -713,7 +713,7 @@
  */
 static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
 {
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
 	unsigned short	w;
 	unsigned int	l;
 	unsigned long long ll;
@@ -724,7 +724,7 @@
 		cword->w8 = c;
 		break;
 	case FLASH_CFI_16BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
 		w = c;
 		w <<= 8;
 		cword->w16 = (cword->w16 >> 8) | w;
@@ -733,7 +733,7 @@
 #endif
 		break;
 	case FLASH_CFI_32BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
 		l = c;
 		l <<= 24;
 		cword->w32 = (cword->w32 >> 8) | l;
@@ -742,7 +742,7 @@
 #endif
 		break;
 	case FLASH_CFI_64BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
 		ll = c;
 		ll <<= 56;
 		cword->w64 = (cword->w64 >> 8) | ll;
@@ -2359,7 +2359,7 @@
 
 	/* Monitor protection ON by default */
 #if defined(CONFIG_SYS_MONITOR_BASE) && \
-	(CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \
+	(CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE) && \
 	(!defined(CONFIG_MONITOR_IS_IN_RAM))
 	flash_protect(FLAG_PROTECT_SET,
 		      CONFIG_SYS_MONITOR_BASE,

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index da2c579..338a356 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig

@@ -41,6 +41,10 @@
 	help
 	  Enable the BBT (Bad Block Table) usage.
 
+config SYS_NAND_NO_SUBPAGE_WRITE
+	bool "Disable subpage write support"
+	depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD
+
 config NAND_ATMEL
 	bool "Support Atmel NAND controller"
 	select SYS_NAND_SELF_INIT
@@ -83,6 +87,18 @@
 	help
 	  Generate Programmable Multibit ECC (PMECC) header for SPL image.
 
+choice
+	prompt "NAND bus width (bits)"
+	default SYS_NAND_DBW_8
+
+config SYS_NAND_DBW_8
+	bool "NAND bus width is 8 bits"
+
+config SYS_NAND_DBW_16
+	bool "NAND bus width is 16 bits"
+
+endchoice
+
 endif
 
 config NAND_BRCMNAND
@@ -136,9 +152,34 @@
 	  Enable this driver for NAND flash controllers available in TI Davinci
 	  and Keystone2 platforms
 
+choice
+	prompt "Type of ECC used on NAND"
+	default SYS_NAND_4BIT_HW_ECC_OOBFIRST
+	depends on NAND_DAVINCI
+
+config SYS_NAND_HW_ECC
+	bool "Use 1-bit HW ECC"
+
 config SYS_NAND_4BIT_HW_ECC_OOBFIRST
 	bool "Use 4-bit HW ECC with OOB at the front"
+
+config SYS_NAND_SOFT_ECC
+	bool "Use software ECC"
+
+endchoice
+
+choice
+	prompt "NAND page size"
 	depends on NAND_DAVINCI
+	default SYS_NAND_PAGE_2K
+
+config SYS_NAND_PAGE_2K
+	bool "Page size is 2K"
+
+config SYS_NAND_PAGE_4K
+	bool "Page size is 4K"
+
+endchoice
 
 config KEYSTONE_RBL_NAND
 	depends on ARCH_KEYSTONE
@@ -184,6 +225,19 @@
 	help
 	  Enable the Freescale Integrated Flash Controller NAND driver.
 
+config NAND_KIRKWOOD
+	bool "Support for Kirkwood NAND controller"
+	depends on ARCH_KIRKWOOD
+	default y
+
+config NAND_ECC_BCH
+	bool
+
+config NAND_KMETER1
+	bool "Support KMETER1 NAND controller"
+	depends on VENDOR_KM
+	select NAND_ECC_BCH
+
 config NAND_LPC32XX_MLC
 	bool "Support LPC32XX_MLC controller"
 	select SYS_NAND_SELF_INIT
@@ -420,6 +474,11 @@
 	  This enables the NAND driver for the NAND flash controller on the
 	  i.MX27 / i.MX31 / i.MX5 processors.
 
+config SYS_NAND_SIZE
+	int "Size of NAND in kilobytes"
+	depends on NAND_MXC && SPL_NAND_SUPPORT
+	default 268435456
+
 config NAND_MXS
 	bool "MXS NAND support"
 	depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
@@ -700,6 +759,11 @@
 	help
 	  Support for NAND boot using simple NAND drivers that
 	  expose the cmd_ctrl() interface.
+
+config SYS_NAND_HW_ECC_OOBFIRST
+	bool "In SPL, read the OOB first and then the data from NAND"
+	depends on SPL_NAND_SIMPLE
+
 endif
 
 endif   # if NAND

diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c
index 83590a6..6ab3f1f 100644
--- a/drivers/mtd/nand/raw/am335x_spl_bch.c
+++ b/drivers/mtd/nand/raw/am335x_spl_bch.c

@@ -16,13 +16,13 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/rawnand.h>
 
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
 static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
-					CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL	(ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+					CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL	(ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
 
 
 /*
@@ -155,8 +155,8 @@
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
 	int i;
-	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
-	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsize = CFG_SYS_NAND_ECCSIZE;
+	int eccbytes = CFG_SYS_NAND_ECCBYTES;
 	int eccsteps = ECCSTEPS;
 	uint8_t *p = dst;
 	uint32_t data_pos = 0;
@@ -207,7 +207,7 @@
 	 */
 	mtd = nand_to_mtd(&nand_chip);
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
-		(void  __iomem *)CONFIG_SYS_NAND_BASE;
+		(void  __iomem *)CFG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
 
 	if (nand_chip.select_chip)

diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index 61bfd17..9fbb0b5 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c

@@ -1012,13 +1012,13 @@
 	unsigned int ecc_value;
 
 	/* get the first 2 ECC bytes */
-	ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
+	ecc_value = ecc_readl(ATMEL_BASE_ECC, PR);
 
 	ecc_code[0] = ecc_value & 0xFF;
 	ecc_code[1] = (ecc_value >> 8) & 0xFF;
 
 	/* get the last 2 ECC bytes */
-	ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
+	ecc_value = ecc_readl(ATMEL_BASE_ECC, NPR) & ATMEL_ECC_NPARITY;
 
 	ecc_code[2] = ecc_value & 0xFF;
 	ecc_code[3] = (ecc_value >> 8) & 0xFF;
@@ -1101,16 +1101,16 @@
 	unsigned int ecc_word, ecc_bit;
 
 	/* get the status from the Status Register */
-	ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
+	ecc_status = ecc_readl(ATMEL_BASE_ECC, SR);
 
 	/* if there's no error */
 	if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
 		return 0;
 
 	/* get error bit offset (4 bits) */
-	ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
+	ecc_bit = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_BITADDR;
 	/* get word address (12 bits) */
-	ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
+	ecc_word = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_WORDADDR;
 	ecc_word >>= 4;
 
 	/* if there are multiple errors */
@@ -1180,22 +1180,22 @@
 		switch (mtd->writesize) {
 		case 512:
 			nand->ecc.layout = &atmel_oobinfo_small;
-			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+			ecc_writel(ATMEL_BASE_ECC, MR,
 					ATMEL_ECC_PAGESIZE_528);
 			break;
 		case 1024:
 			nand->ecc.layout = &atmel_oobinfo_large;
-			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+			ecc_writel(ATMEL_BASE_ECC, MR,
 					ATMEL_ECC_PAGESIZE_1056);
 			break;
 		case 2048:
 			nand->ecc.layout = &atmel_oobinfo_large;
-			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+			ecc_writel(ATMEL_BASE_ECC, MR,
 					ATMEL_ECC_PAGESIZE_2112);
 			break;
 		case 4096:
 			nand->ecc.layout = &atmel_oobinfo_large;
-			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+			ecc_writel(ATMEL_BASE_ECC, MR,
 					ATMEL_ECC_PAGESIZE_4224);
 			break;
 		default:
@@ -1227,16 +1227,16 @@
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
-		IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
-			     | CONFIG_SYS_NAND_MASK_CLE);
+		IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE
+			     | CFG_SYS_NAND_MASK_CLE);
 
 		if (ctrl & NAND_CLE)
-			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
+			IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE;
 		if (ctrl & NAND_ALE)
-			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
+			IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE;
 
-#ifdef CONFIG_SYS_NAND_ENABLE_PIN
-		at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
+#ifdef CFG_SYS_NAND_ENABLE_PIN
+		at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN,
 				    !(ctrl & NAND_NCE));
 #endif
 		this->IO_ADDR_W = (void *) IO_ADDR_W;
@@ -1246,10 +1246,10 @@
 		writeb(cmd, this->IO_ADDR_W);
 }
 
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 static int at91_nand_ready(struct mtd_info *mtd)
 {
-	return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
+	return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN);
 }
 #endif
 
@@ -1314,10 +1314,10 @@
 }
 
 #ifdef CONFIG_SPL_NAND_ECC
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
-		  CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+		  CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
 
 static int nand_read_page(int block, int page, void *dst)
 {
@@ -1325,8 +1325,8 @@
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
-	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
-	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsize = CFG_SYS_NAND_ECCSIZE;
+	int eccbytes = CFG_SYS_NAND_ECCBYTES;
 	int eccsteps = ECCSTEPS;
 	int i;
 	uint8_t *p = dst;
@@ -1415,7 +1415,7 @@
 	nand->read_buf = nand_read_buf;
 #endif
 	nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 	nand->dev_ready = at91_nand_ready;
 #else
 	nand->dev_ready = at91_nand_wait_ready;
@@ -1439,8 +1439,8 @@
 	mtd = nand_to_mtd(&nand_chip);
 	mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
 	mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
-	nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
-	nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+	nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
 
 #ifdef CONFIG_SPL_NAND_ECC
@@ -1464,11 +1464,11 @@
 
 #else
 
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 #endif
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
 
 int atmel_nand_chip_init(int devnum, ulong base_addr)
 {
@@ -1487,7 +1487,7 @@
 	nand->options = NAND_BUSWIDTH_16;
 #endif
 	nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
 	nand->dev_ready = at91_nand_ready;
 #endif
 	nand->chip_delay = 75;

diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index 9158d94..e4e144b 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c

@@ -170,7 +170,7 @@
 	u_int32_t	ecc = 0;
 
 	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
-				CONFIG_SYS_NAND_CS - 2]));
+				CFG_SYS_NAND_CS - 2]));
 
 	return ecc;
 }
@@ -183,8 +183,8 @@
 	nand_davinci_readecc(mtd);
 
 	val = __raw_readl(&davinci_emif_regs->nandfcr);
-	val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
-	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+	val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS);
 	__raw_writel(val, &davinci_emif_regs->nandfcr);
 }
 
@@ -486,8 +486,8 @@
 		 */
 		val = __raw_readl(&davinci_emif_regs->nandfcr);
 		val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
-		val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
-		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
+		val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS);
 		val |= DAVINCI_NANDFCR_4BIT_ECC_START;
 		__raw_writel(val, &davinci_emif_regs->nandfcr);
 		break;
@@ -766,10 +766,7 @@
 	nand->ecc.calculate = nand_davinci_calculate_ecc;
 	nand->ecc.correct  = nand_davinci_correct_data;
 	nand->ecc.hwctl  = nand_davinci_enable_hwecc;
-#else
-	nand->ecc.mode = NAND_ECC_SOFT;
-#endif /* CONFIG_SYS_NAND_HW_ECC */
-#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#elif defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
 	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
 	nand->ecc.size = 512;
 	nand->ecc.bytes = 10;
@@ -778,6 +775,8 @@
 	nand->ecc.correct = nand_davinci_4bit_correct_data;
 	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
 	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
+#elif defined(CONFIG_SYS_NAND_SOFT_ECC)
+	nand->ecc.mode = NAND_ECC_SOFT;
 #endif
 	/* Set address of hardware control function */
 	nand->cmd_ctrl = nand_davinci_hwcontrol;
@@ -795,8 +794,8 @@
 	struct mtd_info *mtd = nand_to_mtd(nand);
 	int ret;
 
-	nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
-	nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+	nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
 
 	davinci_nand_init(nand);
 

diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c
index f721428..690279c 100644
--- a/drivers/mtd/nand/raw/denali_spl.c
+++ b/drivers/mtd/nand/raw/denali_spl.c

@@ -25,9 +25,9 @@
 #define BANK(x) ((x) << 24)
 
 static void __iomem *denali_flash_mem =
-			(void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+			(void __iomem *)CFG_SYS_NAND_DATA_BASE;
 static void __iomem *denali_flash_reg =
-			(void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+			(void __iomem *)CFG_SYS_NAND_REGS_BASE;
 
 static const int flash_bank;
 static int page_size, oob_size, pages_per_block;

diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index 4f0acd7..7853c3f 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c

@@ -819,12 +819,12 @@
 
 #ifndef CONFIG_NAND_FSL_ELBC_DT
 
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 #endif
 
 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
-	CONFIG_SYS_NAND_BASE_LIST;
+	CFG_SYS_NAND_BASE_LIST;
 
 void board_nand_init(void)
 {

diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c
index e55b40f..26aaab08 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c

@@ -46,8 +46,8 @@
 #endif
 {
 	fsl_lbc_t *regs = LBC_BASE_ADDR;
-	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
-	const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
+	uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
+	const int large = CFG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
 	const int block_shift = large ? 17 : 14;
 	const int block_size = 1 << block_shift;
 	const int page_size = large ? 2048 : 512;
@@ -143,8 +143,8 @@
 	 * Load U-Boot image from NAND into RAM
 	 */
 	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			    CONFIG_SYS_NAND_U_BOOT_SIZE,
-			    (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+			    CFG_SYS_NAND_U_BOOT_SIZE,
+			    (void *)CFG_SYS_NAND_U_BOOT_DST);
 
 #ifdef CONFIG_NAND_ENV_DST
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -161,13 +161,13 @@
 	 * Clean d-cache and invalidate i-cache, to
 	 * make sure that no stale data is executed.
 	 */
-	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+	flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
 #endif
 
 	puts("transfering control\n");
 	/*
 	 * Jump to U-Boot image
 	 */
-	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+	uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
 	(*uboot)();
 }

diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index e5ff937..18abd75 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c

@@ -780,10 +780,10 @@
 	ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
 	if (ver >= FSL_IFC_V2_0_0)
 		ifc_ctrl->regs.rregs =
-			(void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+			(void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
 	else
 		ifc_ctrl->regs.rregs =
-			(void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
+			(void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
 
 	/* clear event registers */
 	ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
@@ -1053,12 +1053,12 @@
 	return 0;
 }
 
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 #endif
 
 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
-	CONFIG_SYS_NAND_BASE_LIST;
+	CFG_SYS_NAND_BASE_LIST;
 
 void board_nand_init(void)
 {

diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index 4d11922..3b464ce 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c

@@ -54,14 +54,14 @@
 
 static inline struct fsl_ifc_runtime *runtime_regs_address(void)
 {
-	struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
+	struct fsl_ifc regs = {(void *)CFG_SYS_IFC_ADDR, NULL};
 	int ver = 0;
 
 	ver = ifc_in32(&regs.gregs->ifc_rev);
 	if (ver >= FSL_IFC_V2_0_0)
-		regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+		regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
 	else
-		regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
+		regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
 
 	return regs.rregs;
 }
@@ -108,9 +108,9 @@
 
 int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
 {
-	struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR;
 	struct fsl_ifc_runtime *ifc = NULL;
-	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
+	uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
 	int page_size;
 	int port_size;
 	int pages_per_blk;
@@ -129,8 +129,8 @@
 	ifc = runtime_regs_address();
 
 	/* Get NAND Flash configuration */
-	csor = CONFIG_SYS_NAND_CSOR;
-	cspr = CONFIG_SYS_NAND_CSPR;
+	csor = CFG_SYS_NAND_CSOR;
+	cspr = CFG_SYS_NAND_CSPR;
 
 	port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
 
@@ -250,8 +250,8 @@
 	 * Load U-Boot image from NAND into RAM
 	 */
 	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			    CONFIG_SYS_NAND_U_BOOT_SIZE,
-			    (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+			    CFG_SYS_NAND_U_BOOT_SIZE,
+			    (uchar *)CFG_SYS_NAND_U_BOOT_DST);
 
 #ifdef CONFIG_NAND_ENV_DST
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -270,7 +270,7 @@
 	 * Clean d-cache and invalidate i-cache, to
 	 * make sure that no stale data is executed.
 	 */
-	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+	flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
 #endif
 
 #ifdef CONFIG_CHAIN_OF_TRUST
@@ -279,11 +279,11 @@
 	 * calculate U-boot header address using U-boot header size.
 	 */
 #define CONFIG_U_BOOT_HDR_ADDR \
-		((CONFIG_SYS_NAND_U_BOOT_START + \
-		  CONFIG_SYS_NAND_U_BOOT_SIZE) - \
+		((CFG_SYS_NAND_U_BOOT_START + \
+		  CFG_SYS_NAND_U_BOOT_SIZE) - \
 		 CONFIG_U_BOOT_HDR_SIZE)
 	spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
-			   CONFIG_SYS_NAND_U_BOOT_START);
+			   CFG_SYS_NAND_U_BOOT_START);
 	/*
 	 * In case of failure in validation, spl_validate_uboot would
 	 * not return back in case of Production environment with ITS=1.
@@ -293,7 +293,7 @@
 	 */
 #endif
 
-	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+	uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
 	uboot();
 }
 

diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index a92c625..d795864 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c

@@ -427,7 +427,7 @@
 	nand->ecc.hwctl = fsmc_enable_hwecc;
 	nand->cmd_ctrl = fsmc_nand_hwcontrol;
 	nand->IO_ADDR_R = nand->IO_ADDR_W =
-		(void  __iomem *)CONFIG_SYS_NAND_BASE;
+		(void  __iomem *)CFG_SYS_NAND_BASE;
 	nand->badblockbits = 7;
 
 	mtd = nand_to_mtd(nand);

diff --git a/drivers/mtd/nand/raw/kmeter1_nand.c b/drivers/mtd/nand/raw/kmeter1_nand.c
index b838164..84564b2 100644
--- a/drivers/mtd/nand/raw/kmeter1_nand.c
+++ b/drivers/mtd/nand/raw/kmeter1_nand.c

@@ -10,8 +10,8 @@
 #include <linux/delay.h>
 #include <linux/mtd/rawnand.h>
 
-#define CONFIG_NAND_MODE_REG	(void *)(CONFIG_SYS_NAND_BASE + 0x20000)
-#define CONFIG_NAND_DATA_REG	(void *)(CONFIG_SYS_NAND_BASE + 0x30000)
+#define CONFIG_NAND_MODE_REG	(void *)(CFG_SYS_NAND_BASE + 0x20000)
+#define CONFIG_NAND_DATA_REG	(void *)(CFG_SYS_NAND_BASE + 0x30000)
 
 #define read_mode()	in_8(CONFIG_NAND_MODE_REG)
 #define write_mode(val)	out_8(CONFIG_NAND_MODE_REG, val)

diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index 5bc5301..a884c65 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c

@@ -84,8 +84,8 @@
 static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
 	= (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
 
-#if !defined(CONFIG_SYS_MAX_NAND_CHIPS)
-#define CONFIG_SYS_MAX_NAND_CHIPS	1
+#if !defined(CFG_SYS_MAX_NAND_CHIPS)
+#define CFG_SYS_MAX_NAND_CHIPS	1
 #endif
 
 #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
@@ -586,7 +586,7 @@
 	lpc32xx_nand_init();
 
 	/* identify chip */
-	ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
+	ret = nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL);
 	if (ret) {
 		pr_err("nand_scan_ident returned %i", ret);
 		return;

diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
index 3d6cb1d..f4f1b22 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c

@@ -84,7 +84,7 @@
 };
 
 #if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
-#define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE)
 
 /*
  * DMA Descriptors
@@ -187,7 +187,7 @@
 			DMAC_CHAN_DEST_AHB1;
 
 	/* CTRL descriptor entry for reading/writing Data */
-	ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
+	ctrl = (CFG_SYS_NAND_ECCSIZE / 4) |
 			DMAC_CHAN_SRC_BURST_4 |
 			DMAC_CHAN_DEST_BURST_4 |
 			DMAC_CHAN_SRC_WIDTH_32 |
@@ -241,7 +241,7 @@
 	 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
 	 */
 
-	for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
+	for (i = 0; i < size/CFG_SYS_NAND_ECCSIZE; i++) {
 		dmalist_cur = &dmalist[i * 2];
 		dmalist_cur_ecc = &dmalist[(i * 2) + 1];
 
@@ -337,9 +337,9 @@
 static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
 {
 	int i;
-	for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
-	     i += CONFIG_SYS_NAND_ECCBYTES) {
-		u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
+	for (i = 0; i < (count * CFG_SYS_NAND_ECCBYTES);
+	     i += CFG_SYS_NAND_ECCBYTES) {
+		u32 ce = ecc[i / CFG_SYS_NAND_ECCBYTES];
 		ce = ~(ce << 2) & 0xFFFFFF;
 		spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
 		spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
@@ -386,9 +386,9 @@
 	u16 data_offset = 0;
 
 	for (i = 0 ; i < ECCSTEPS ; i++) {
-		r += CONFIG_SYS_NAND_ECCBYTES;
-		c += CONFIG_SYS_NAND_ECCBYTES;
-		data_offset += CONFIG_SYS_NAND_ECCSIZE;
+		r += CFG_SYS_NAND_ECCBYTES;
+		c += CFG_SYS_NAND_ECCBYTES;
+		data_offset += CFG_SYS_NAND_ECCSIZE;
 
 		ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
 		if (ret1 < 0)
@@ -568,8 +568,8 @@
 	 * These values are predefined
 	 * for both small and large page NAND flash devices.
 	 */
-	lpc32xx_chip->ecc.size     = CONFIG_SYS_NAND_ECCSIZE;
-	lpc32xx_chip->ecc.bytes    = CONFIG_SYS_NAND_ECCBYTES;
+	lpc32xx_chip->ecc.size     = CFG_SYS_NAND_ECCSIZE;
+	lpc32xx_chip->ecc.bytes    = CFG_SYS_NAND_ECCBYTES;
 	lpc32xx_chip->ecc.strength = 1;
 
 	if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)

diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 2b8a132..8aa5f73 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c

@@ -12,8 +12,7 @@
 #include <linux/err.h>
 #include <linux/mtd/rawnand.h>
 #include <asm/io.h>
-#if defined(CONFIG_MX27) || \
-	defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #include <asm/arch/imx-regs.h>
 #endif
 #include "mxc_nand.h"
@@ -50,7 +49,7 @@
 
 /* OOB placement block for use with hardware ecc generation */
 #if defined(MXC_NFC_V1)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
 static struct nand_ecclayout nand_hw_eccoob = {
 	.eccbytes = 5,
 	.eccpos = {6, 7, 8, 9, 10},
@@ -69,7 +68,7 @@
 };
 #endif
 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
 static struct nand_ecclayout nand_hw_eccoob = {
 	.eccbytes = 9,
 	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
@@ -1219,7 +1218,7 @@
 	if (is_16bit_nand())
 		this->options |= NAND_BUSWIDTH_16;
 
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
+#ifdef CFG_SYS_NAND_LARGEPAGE
 	host->pagesize_2k = 1;
 	this->ecc.layout = &nand_hw_eccoob2k;
 #else

diff --git a/drivers/mtd/nand/raw/mxc_nand.h b/drivers/mtd/nand/raw/mxc_nand.h
index 771f61e..084fac7 100644
--- a/drivers/mtd/nand/raw/mxc_nand.h
+++ b/drivers/mtd/nand/raw/mxc_nand.h

@@ -24,7 +24,7 @@
  *	Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
  *	Also some of registers are moved and/or changed meaning as seen below.
  */
-#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
+#if defined(CONFIG_MX31)
 #define MXC_NFC_V1
 #define is_mxc_nfc_1()		1
 #define is_mxc_nfc_21()		0

diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c
index 0fea307..309e75d 100644
--- a/drivers/mtd/nand/raw/mxc_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxc_nand_spl.c

@@ -332,14 +332,14 @@
 	__attribute__((noreturn)) void (*uboot)(void);
 
 	/*
-	 * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
+	 * CONFIG_SYS_NAND_U_BOOT_OFFS and CFG_SYS_NAND_U_BOOT_SIZE must
 	 * be aligned to full pages
 	 */
 	if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			CONFIG_SYS_NAND_U_BOOT_SIZE,
-			(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+			CFG_SYS_NAND_U_BOOT_SIZE,
+			(uchar *)CFG_SYS_NAND_U_BOOT_DST)) {
 		/* Copy from NAND successful, start U-Boot */
-		uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+		uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
 		uboot();
 	} else {
 		/* Unrecoverable error when copying from NAND */

diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c
index 14bca12..eacd99c 100644
--- a/drivers/mtd/nand/raw/nand.c
+++ b/drivers/mtd/nand/raw/nand.c

@@ -11,8 +11,8 @@
 #include <linux/mtd/concat.h>
 #include <linux/mtd/rawnand.h>
 
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 #endif
 
 int nand_curr_device = -1;
@@ -21,7 +21,7 @@
 
 #if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
 #endif
 
 static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];

diff --git a/drivers/mtd/nand/raw/nand_spl_load.c b/drivers/mtd/nand/raw/nand_spl_load.c
index ecd373e..7ac9bf4 100644
--- a/drivers/mtd/nand/raw/nand_spl_load.c
+++ b/drivers/mtd/nand/raw/nand_spl_load.c

@@ -20,8 +20,8 @@
 	 * Load U-Boot image from NAND into RAM
 	 */
 	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			CONFIG_SYS_NAND_U_BOOT_SIZE,
-			(void *)CONFIG_SYS_NAND_U_BOOT_DST);
+			CFG_SYS_NAND_U_BOOT_SIZE,
+			(void *)CFG_SYS_NAND_U_BOOT_DST);
 
 #ifdef CONFIG_NAND_ENV_DST
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -36,6 +36,6 @@
 	/*
 	 * Jump to U-Boot image
 	 */
-	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+	uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
 	(*uboot)();
 }

diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c
index 727861c..2f3af9e 100644
--- a/drivers/mtd/nand/raw/nand_spl_simple.c
+++ b/drivers/mtd/nand/raw/nand_spl_simple.c

@@ -10,13 +10,13 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/rawnand.h>
 
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
 static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
-					CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL	(ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+					CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL	(ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
 
 
 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
@@ -139,8 +139,8 @@
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
 	int i;
-	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
-	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsize = CFG_SYS_NAND_ECCSIZE;
+	int eccbytes = CFG_SYS_NAND_ECCBYTES;
 	int eccsteps = ECCSTEPS;
 	uint8_t *p = dst;
 
@@ -170,8 +170,8 @@
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
 	int i;
-	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
-	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsize = CFG_SYS_NAND_ECCSIZE;
+	int eccbytes = CFG_SYS_NAND_ECCBYTES;
 	int eccsteps = ECCSTEPS;
 	uint8_t *p = dst;
 
@@ -212,7 +212,7 @@
 	 */
 	mtd = nand_to_mtd(&nand_chip);
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
-		(void  __iomem *)CONFIG_SYS_NAND_BASE;
+		(void  __iomem *)CFG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
 
 #ifdef CONFIG_SPL_NAND_SOFTECC

diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 8b9ff4d..b7d261d 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c

@@ -407,7 +407,7 @@
 		cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
 
 		for (i = 0; i < cnt / 4; i++) {
-			*buf++ = readl(CONFIG_SYS_NAND_BASE);
+			*buf++ = readl(CFG_SYS_NAND_BASE);
 			len -= 4;
 		}
 	} while (len);

diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index 13fd631..d4b40e8 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c

@@ -812,7 +812,7 @@
 		return;
 	}
 
-	nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE;
 	err = vf610_nfc_nand_init(nfc, 0);
 	if (err)
 		printf("VF610 NAND init failed (err %d)\n", err);

diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c
index ab6f1a8..2699958 100644
--- a/drivers/mtd/onenand/onenand_spl.c
+++ b/drivers/mtd/onenand/onenand_spl.c

@@ -49,12 +49,12 @@
 
 static inline uint16_t onenand_readw(uint32_t addr)
 {
-	return readw(CONFIG_SYS_ONENAND_BASE + addr);
+	return readw(CFG_SYS_ONENAND_BASE + addr);
 }
 
 static inline void onenand_writew(uint16_t value, uint32_t addr)
 {
-	writew(value, CONFIG_SYS_ONENAND_BASE + addr);
+	writew(value, CFG_SYS_ONENAND_BASE + addr);
 }
 
 static enum onenand_spl_pagesize onenand_spl_get_geometry(void)
@@ -82,7 +82,7 @@
 static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf,
 					enum onenand_spl_pagesize pagesize)
 {
-	const uint32_t addr = CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM;
+	const uint32_t addr = CFG_SYS_ONENAND_BASE + ONENAND_DATARAM;
 	uint32_t offset;
 
 	onenand_writew(onenand_block_address(block),

diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c
index 3a8c7b8..04791df 100644
--- a/drivers/mtd/onenand/onenand_uboot.c
+++ b/drivers/mtd/onenand/onenand_uboot.c

@@ -35,7 +35,7 @@
 	/* It's used for some board init required */
 	err = onenand_board_init(&onenand_mtd);
 #else
-	onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE;
+	onenand_chip.base = (void *) CFG_SYS_ONENAND_BASE;
 #endif
 
 	if (!err && !(onenand_scan(&onenand_mtd, 1))) {

diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index 5c41d75..dfc35d6 100644
--- a/drivers/mtd/spi/fsl_espi_spl.c
+++ b/drivers/mtd/spi/fsl_espi_spl.c

@@ -49,8 +49,8 @@
 	}
 
 #ifdef CONFIG_FSL_CORENET
-	offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
-	code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE;
+	offset = CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
+	code_len = CFG_SYS_SPI_FLASH_U_BOOT_SIZE;
 #else
 	/*
 	* Load U-Boot image from SPI flash into RAM
@@ -66,7 +66,7 @@
 		       flash->page_size, (void *)buf);
 	offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
 	/* Skip spl code */
-	offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+	offset += CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
 	/* Get the code size from offset 0x48 */
 	code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
 	/* Skip spl code */
@@ -76,7 +76,7 @@
 	printf("Loading second stage boot loader ");
 	while (copy_len <= code_len) {
 		spi_flash_read(flash, offset + copy_len, 0x2000,
-			       (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST
+			       (void *)(CFG_SYS_SPI_FLASH_U_BOOT_DST
 			       + copy_len));
 		copy_len = copy_len + 0x2000;
 		putc('.');
@@ -85,7 +85,7 @@
 	/*
 	* Jump to U-Boot image
 	*/
-	flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
-	uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START;
+	flush_cache(CFG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
+	uboot = (void *)CFG_SYS_SPI_FLASH_U_BOOT_START;
 	(*uboot)();
 }

diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c
index 95afa2d..4523344 100644
--- a/drivers/mtd/stm32_flash.c
+++ b/drivers/mtd/stm32_flash.c

@@ -39,7 +39,7 @@
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		flash_info[i].flash_id = FLASH_STM32;
 		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-		flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
+		flash_info[i].start[0] = CFG_SYS_FLASH_BASE + (i << 20);
 		flash_info[i].size = sect_sz_kb[0];
 		for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
 			flash_info[i].start[j] = flash_info[i].start[j - 1]

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 029bf38..13e434e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig

@@ -676,6 +676,12 @@
 	  rates from 10GE to 100GE. This could be present in some of the Xilinx
 	  Versal designs.
 
+config VSC7385_ENET
+	bool "Vitesse 7385 Switch Firmware Upload driver"
+
+config VSC9953
+	bool "Vitesse VSC9953 L2 Switch driver"
+
 config XILINX_EMACLITE
 	select PHYLIB
 	select MII

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index bbc4434..a61a1fc 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c

@@ -251,9 +251,6 @@
 	 * Wake up from sleep if necessary
 	 * Reset PHY, then delay 300ns
 	 */
-#ifdef CONFIG_MX27
-	fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
-#endif
 	fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
 	udelay(1000);
 

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index c23e0c0..c8381cc 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c

@@ -128,7 +128,7 @@
 	struct dtsec *regs = (struct dtsec *)CFG_SYS_FSL_FM1_DTSEC1_ADDR;
 
 	/* Assign a Physical address to the TBI */
-	out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
+	out_be32(&regs->tbipa, CFG_SYS_TBIPA_VALUE);
 #endif
 
 	if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||

diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 9b6dbe2..c476cb3 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c

@@ -26,7 +26,7 @@
 #include <asm/arch/cpu.h>
 #endif
 
-struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
+struct fm_muram muram[CFG_SYS_NUM_FMAN];
 
 void *fm_muram_base(int fm_idx)
 {
@@ -67,9 +67,9 @@
 	void *base = reg;
 
 	muram[fm_idx].base = base;
-	muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
+	muram[fm_idx].size = CFG_SYS_FM_MURAM_SIZE;
 	muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
-	muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
+	muram[fm_idx].top = base + CFG_SYS_FM_MURAM_SIZE;
 }
 
 /*

diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 2379b3a..3d9cc5c 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h

@@ -15,11 +15,11 @@
 #define OH_PORT_ID_BASE		0x01
 #define MAX_NUM_OH_PORT		7
 #define RX_PORT_1G_BASE		0x08
-#define MAX_NUM_RX_PORT_1G	CONFIG_SYS_NUM_FM1_DTSEC
+#define MAX_NUM_RX_PORT_1G	CFG_SYS_NUM_FM1_DTSEC
 #define RX_PORT_10G_BASE	0x10
 #define RX_PORT_10G_BASE2	0x08
 #define TX_PORT_1G_BASE		0x28
-#define MAX_NUM_TX_PORT_1G	CONFIG_SYS_NUM_FM1_DTSEC
+#define MAX_NUM_TX_PORT_1G	CFG_SYS_NUM_FM1_DTSEC
 #define TX_PORT_10G_BASE	0x30
 #define TX_PORT_10G_BASE2	0x28
 #define MIIM_TIMEOUT    0xFFFF

diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 34f3816..618c1bc 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c

@@ -19,70 +19,70 @@
 
 #ifndef CONFIG_DM_ETH
 struct fm_eth_info fm_info[] = {
-#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1)
+#if (CFG_SYS_NUM_FM1_DTSEC >= 1)
 	FM_DTSEC_INFO_INITIALIZER(1, 1),
 #endif
-#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2)
+#if (CFG_SYS_NUM_FM1_DTSEC >= 2)
 	FM_DTSEC_INFO_INITIALIZER(1, 2),
 #endif
-#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3)
+#if (CFG_SYS_NUM_FM1_DTSEC >= 3)
 	FM_DTSEC_INFO_INITIALIZER(1, 3),
 #endif
-#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4)
+#if (CFG_SYS_NUM_FM1_DTSEC >= 4)
 	FM_DTSEC_INFO_INITIALIZER(1, 4),
 #endif
-#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5)
+#if (CFG_SYS_NUM_FM1_DTSEC >= 5)
 	FM_DTSEC_INFO_INITIALIZER(1, 5),
 #endif
-#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6)
+#if (CFG_SYS_NUM_FM1_DTSEC >= 6)
 	FM_DTSEC_INFO_INITIALIZER(1, 6),
 #endif
-#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7)
+#if (CFG_SYS_NUM_FM1_DTSEC >= 7)
 	FM_DTSEC_INFO_INITIALIZER(1, 9),
 #endif
-#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8)
+#if (CFG_SYS_NUM_FM1_DTSEC >= 8)
 	FM_DTSEC_INFO_INITIALIZER(1, 10),
 #endif
-#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1)
+#if (CFG_SYS_NUM_FM2_DTSEC >= 1)
 	FM_DTSEC_INFO_INITIALIZER(2, 1),
 #endif
-#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2)
+#if (CFG_SYS_NUM_FM2_DTSEC >= 2)
 	FM_DTSEC_INFO_INITIALIZER(2, 2),
 #endif
-#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3)
+#if (CFG_SYS_NUM_FM2_DTSEC >= 3)
 	FM_DTSEC_INFO_INITIALIZER(2, 3),
 #endif
-#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
+#if (CFG_SYS_NUM_FM2_DTSEC >= 4)
 	FM_DTSEC_INFO_INITIALIZER(2, 4),
 #endif
-#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
+#if (CFG_SYS_NUM_FM2_DTSEC >= 5)
 	FM_DTSEC_INFO_INITIALIZER(2, 5),
 #endif
-#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6)
+#if (CFG_SYS_NUM_FM2_DTSEC >= 6)
 	FM_DTSEC_INFO_INITIALIZER(2, 6),
 #endif
-#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7)
+#if (CFG_SYS_NUM_FM2_DTSEC >= 7)
 	FM_DTSEC_INFO_INITIALIZER(2, 9),
 #endif
-#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8)
+#if (CFG_SYS_NUM_FM2_DTSEC >= 8)
 	FM_DTSEC_INFO_INITIALIZER(2, 10),
 #endif
-#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
+#if (CFG_SYS_NUM_FM1_10GEC >= 1)
 	FM_TGEC_INFO_INITIALIZER(1, 1),
 #endif
-#if (CONFIG_SYS_NUM_FM1_10GEC >= 2)
+#if (CFG_SYS_NUM_FM1_10GEC >= 2)
 	FM_TGEC_INFO_INITIALIZER(1, 2),
 #endif
-#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
+#if (CFG_SYS_NUM_FM1_10GEC >= 3)
 	FM_TGEC_INFO_INITIALIZER2(1, 3),
 #endif
-#if (CONFIG_SYS_NUM_FM1_10GEC >= 4)
+#if (CFG_SYS_NUM_FM1_10GEC >= 4)
 	FM_TGEC_INFO_INITIALIZER2(1, 4),
 #endif
-#if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
+#if (CFG_SYS_NUM_FM2_10GEC >= 1)
 	FM_TGEC_INFO_INITIALIZER(2, 1),
 #endif
-#if (CONFIG_SYS_NUM_FM2_10GEC >= 2)
+#if (CFG_SYS_NUM_FM2_10GEC >= 2)
 	FM_TGEC_INFO_INITIALIZER(2, 2),
 #endif
 };
@@ -101,7 +101,7 @@
 			fm_eth_initialize(reg, &fm_info[i]);
 	}
 
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 	reg = (void *)CFG_SYS_FSL_FM2_ADDR;
 	if (fm_init_common(1, reg))
 		return 0;
@@ -244,9 +244,9 @@
 {
 	int off;
 	uint32_t ph;
-	phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
+	phys_addr_t paddr = CFG_SYS_CCSRBAR_PHYS + info->compat_offset;
 #ifndef CONFIG_SYS_FMAN_V3
-	u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
+	u64 dtsec1_addr = (u64)CFG_SYS_CCSRBAR_PHYS +
 				CFG_SYS_FSL_FM1_DTSEC1_OFFSET;
 #endif
 
@@ -276,7 +276,7 @@
 	    ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
 	    ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1)))  ||
 	    ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2)))
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 										||
 	    ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1)))	||
 	    ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2)))	||

diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h
index 8be38e1..ff998d4 100644
--- a/drivers/net/fsl-mc/dpio/qbman_sys.h
+++ b/drivers/net/fsl-mc/dpio/qbman_sys.h

@@ -256,12 +256,12 @@
 
 	s->addr_cena = d->cena_bar;
 	s->addr_cinh = d->cinh_bar;
-	s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
+	s->cena = (void *)valloc(CFG_SYS_PAGE_SIZE);
 	if (!s->cena) {
 		printf("Could not allocate page for cena shadow\n");
 		return -1;
 	}
-	memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
+	memset((void *)s->cena, 0x00, CFG_SYS_PAGE_SIZE);
 
 #ifdef QBMAN_CHECKING
 	/* We should never be asked to initialise for a portal that isn't in

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 68833f9..69da465 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c

@@ -54,7 +54,7 @@
 static struct mc_version mc_ver_info;
 static int mc_boot_status = -1;
 static int mc_dpl_applied = -1;
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 static int mc_aiop_applied = -1;
 #endif
 struct fsl_mc_io *root_mc_io = NULL;
@@ -500,13 +500,13 @@
 	int dpc_size;
 #endif
 
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
-	BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
-		     CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
+#ifdef CFG_SYS_LS_MC_DRAM_DPC_OFFSET
+	BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
+		     CFG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
 
-	mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
+	mc_dpc_offset = CFG_SYS_LS_MC_DRAM_DPC_OFFSET;
 #else
-#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
+#error "CFG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
 #endif
 
 	/*
@@ -531,7 +531,7 @@
 	}
 
 	dpc_size = fdt_totalsize(dpc_fdt_hdr);
-	if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
+	if (dpc_size > CFG_SYS_LS_MC_DPC_MAX_LENGTH) {
 		printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
 		       dpc_size);
 		return -EINVAL;
@@ -576,13 +576,13 @@
 	int dpl_size;
 #endif
 
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
-	BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
-		     CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
+#ifdef CFG_SYS_LS_MC_DRAM_DPL_OFFSET
+	BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
+		     CFG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
 
-	mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
+	mc_dpl_offset = CFG_SYS_LS_MC_DRAM_DPL_OFFSET;
 #else
-#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
+#error "CFG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
 #endif
 
 	/*
@@ -603,7 +603,7 @@
 	}
 
 	dpl_size = fdt_totalsize(dpl_fdt_hdr);
-	if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
+	if (dpl_size > CFG_SYS_LS_MC_DPL_MAX_LENGTH) {
 		printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
 		       dpl_size);
 		return -EINVAL;
@@ -624,7 +624,7 @@
  */
 static unsigned long get_mc_boot_timeout_ms(void)
 {
-	unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+	unsigned long timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS;
 
 	char *timeout_ms_env_var = env_get(MC_BOOT_TIMEOUT_ENV_VAR);
 
@@ -636,14 +636,14 @@
 			       "\' environment variable: %lu\n",
 			       timeout_ms);
 
-			timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+			timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS;
 		}
 	}
 
 	return timeout_ms;
 }
 
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 
 __weak bool soc_has_aiop(void)
 {
@@ -666,12 +666,12 @@
 
 #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
 	printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
-	       CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+	       CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
 #else
 	aiop_img = (void *)aiop_fw_addr;
 	mc_copy_image("MC AIOP image",
-		      (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
-		      mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+		      (u64)aiop_img, CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
+		      mc_ram_addr + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
 #endif
 	mc_aiop_applied = 0;
 
@@ -896,7 +896,7 @@
 	return mc_boot_status;
 }
 
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 int get_aiop_apply_status(void)
 {
 	return mc_aiop_applied;
@@ -938,14 +938,14 @@
  */
 unsigned long mc_get_dram_block_size(void)
 {
-	unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+	unsigned long dram_block_size = CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
 
 	char *dram_block_size_env_var = env_get(MC_MEM_SIZE_ENV_VAR);
 
 	if (dram_block_size_env_var) {
 		dram_block_size = hextoul(dram_block_size_env_var, NULL);
 
-		if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
+		if (dram_block_size < CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
 			printf("fsl-mc: WARNING: Invalid value for \'"
 			       MC_MEM_SIZE_ENV_VAR
 			       "\' environment variable: %lu\n",
@@ -1838,7 +1838,7 @@
 	case 's': {
 			char sub_cmd;
 			u64 mc_fw_addr, mc_dpc_addr;
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 			u64 aiop_fw_addr;
 #endif
 			if (argc < 3)
@@ -1864,7 +1864,7 @@
 					err = mc_init_object();
 				break;
 
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 			case 'a':
 				if (argc < 4)
 					goto usage;

diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
index 6825f9e..cc61a10 100644
--- a/drivers/net/fsl_mcdmafec.c
+++ b/drivers/net/fsl_mcdmafec.c

@@ -43,11 +43,11 @@
 static void init_eth_info(struct fec_info_dma *info)
 {
 	/* setup Receive and Transmit buffer descriptor */
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+#ifdef CFG_SYS_FEC_BUF_USE_SRAM
 	static u32 tmp;
 
 	if (info->index == 0)
-		tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+		tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
 	else
 		info->rxbd = (cbd_t *)DBUF_LENGTH;
 
@@ -59,7 +59,7 @@
 	tmp = (u32)info->txbd;
 	info->txbuf =
 	    (char *)((u32)info->txbuf + tmp +
-	    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+	    (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
 	tmp = (u32)info->txbuf;
 #else
 	info->rxbd =
@@ -67,7 +67,7 @@
 			       (PKTBUFSRX * sizeof(cbd_t)));
 	info->txbd =
 	    (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
-			       (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+			       (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
 	info->txbuf =
 	    (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
 #endif
@@ -283,15 +283,15 @@
 
 	/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
 	 * Settings:    Last, Tx CRC */
-	for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
+	for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) {
 		info->txbd[i].cbd_sc = 0;
 		info->txbd[i].cbd_datlen = 0;
 		info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
 	}
-	info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
+	info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
 
 	info->used_tbd_idx = 0;
-	info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
+	info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER;
 
 	/* Set Rx FIFO alarm and granularity value */
 	fecp->rfcr = 0x0c000000;
@@ -352,7 +352,7 @@
 	miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
 
 	/* process all the consumed TBDs */
-	while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
+	while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) {
 		p_used_tbd = &info->txbd[info->used_tbd_idx];
 		if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
 #ifdef ET_DEBUG
@@ -363,7 +363,7 @@
 		}
 
 		/* clean this buffer descriptor */
-		if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
+		if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1))
 			p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
 		else
 			p_used_tbd->cbd_sc = 0;
@@ -371,7 +371,7 @@
 		/* update some indeces for a correct handling of TBD ring */
 		info->clean_tbd_num++;
 		info->used_tbd_idx = (info->used_tbd_idx + 1)
-			% CONFIG_SYS_TX_ETH_BUFFER;
+			% CFG_SYS_TX_ETH_BUFFER;
 	}
 
 	/* Check for valid length of data. */
@@ -389,7 +389,7 @@
 	p_tbd->cbd_datlen = length;
 	p_tbd->cbd_bufaddr = (u32)packet;
 	p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
-	info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
+	info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER;
 
 	/* Enable DMA transmit task */
 	MCD_continDma(info->tx_task);
@@ -524,8 +524,8 @@
 	if (val)
 		info->tx_init = fdt32_to_cpu(*val);
 
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
-	u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+#ifdef CFG_SYS_FEC_BUF_USE_SRAM
+	u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
 #endif
 	init_eth_info(info);
 

diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
index c30ace9..f710c27 100644
--- a/drivers/net/ftmac100.c
+++ b/drivers/net/ftmac100.c

@@ -17,10 +17,10 @@
 #include <linux/io.h>
 
 #include "ftmac100.h"
-#ifdef CONFIG_DM_ETH
 #include <dm.h>
+
 DECLARE_GLOBAL_DATA_PTR;
-#endif
+
 #define ETH_ZLEN	60
 
 struct ftmac100_data {
@@ -228,95 +228,9 @@
 
 	debug ("%s(): packet sent\n", __func__);
 
-	return 0;
-}
-
-#ifndef CONFIG_DM_ETH
-/*
- * disable transmitter, receiver
- */
-static void ftmac100_halt(struct eth_device *dev)
-{
-	struct ftmac100_data *priv = dev->priv;
-	return _ftmac100_halt(priv);
-}
-
-static int ftmac100_init(struct eth_device *dev, struct bd_info *bd)
-{
-	struct ftmac100_data *priv = dev->priv;
-	return _ftmac100_init(priv , dev->enetaddr);
-}
-
-static int _ftmac100_recv(struct ftmac100_data *priv)
-{
-	struct ftmac100_rxdes *curr_des;
-	unsigned short len;
-	curr_des = &priv->rxdes[priv->rx_index];
-	len = __ftmac100_recv(priv);
-	if (len) {
-		/* pass the packet up to the protocol layers. */
-		net_process_received_packet((void *)curr_des->rxdes2, len);
-		_ftmac100_free_pkt(priv);
-	}
-	return len ? 1 : 0;
-}
-
-/*
- * Get a data block via Ethernet
- */
-static int ftmac100_recv(struct eth_device *dev)
-{
-	struct ftmac100_data *priv = dev->priv;
-	return _ftmac100_recv(priv);
-}
-
-/*
- * Send a data block via Ethernet
- */
-static int ftmac100_send(struct eth_device *dev, void *packet, int length)
-{
-	struct ftmac100_data *priv = dev->priv;
-	return _ftmac100_send(priv , packet , length);
-}
-
-int ftmac100_initialize (struct bd_info *bd)
-{
-	struct eth_device *dev;
-	struct ftmac100_data *priv;
-	dev = malloc (sizeof *dev);
-	if (!dev) {
-		printf ("%s(): failed to allocate dev\n", __func__);
-		goto out;
-	}
-	/* Transmit and receive descriptors should align to 16 bytes */
-	priv = memalign (16, sizeof (struct ftmac100_data));
-	if (!priv) {
-		printf ("%s(): failed to allocate priv\n", __func__);
-		goto free_dev;
-	}
-	memset (dev, 0, sizeof (*dev));
-	memset (priv, 0, sizeof (*priv));
-
-	strcpy(dev->name, "FTMAC100");
-	dev->iobase	= CONFIG_FTMAC100_BASE;
-	dev->init	= ftmac100_init;
-	dev->halt	= ftmac100_halt;
-	dev->send	= ftmac100_send;
-	dev->recv	= ftmac100_recv;
-	dev->priv	= priv;
-	priv->iobase	= dev->iobase;
-	eth_register (dev);
-
-	return 1;
-
-free_dev:
-	free (dev);
-out:
 	return 0;
 }
-#endif
 
-#ifdef CONFIG_DM_ETH
 static int ftmac100_start(struct udevice *dev)
 {
 	struct eth_pdata *plat = dev_get_plat(dev);
@@ -445,4 +359,3 @@
 	.plat_auto	= sizeof(struct eth_pdata),
 	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
 };
-#endif

diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 4dd8489..ec1fae9 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c

@@ -39,11 +39,11 @@
 
 static void init_eth_info(struct fec_info_s *info)
 {
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+#ifdef CFG_SYS_FEC_BUF_USE_SRAM
 	static u32 tmp;
 
 	if (info->index == 0)
-		tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+		tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
 	else
 		info->rxbd = (cbd_t *)DBUF_LENGTH;
 
@@ -56,7 +56,7 @@
 	tmp = (u32)info->txbd;
 	info->txbuf =
 	    (char *)((u32)info->txbuf + tmp +
-	    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+	    (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
 	tmp = (u32)info->txbuf;
 #else
 	info->rxbd =
@@ -387,7 +387,7 @@
 	/* Activate transmit Buffer Descriptor polling */
 	fecp->tdar = 0x01000000;	/* Descriptor polling active    */
 
-#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
+#ifndef CFG_SYS_FEC_BUF_USE_SRAM
 	/*
 	 * FEC unable to initial transmit data packet.
 	 * A nop will ensure the descriptor polling active completed.

diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h
index 32b7d3e..551d706 100644
--- a/drivers/net/qe/uec.h
+++ b/drivers/net/qe/uec.h

@@ -605,10 +605,10 @@
 #define STD_UEC_INFO(num) \
 {			\
 	.uf_info		= {	\
-		.ucc_num	= CONFIG_SYS_UEC##num##_UCC_NUM,\
-		.rx_clock	= CONFIG_SYS_UEC##num##_RX_CLK,	\
-		.tx_clock	= CONFIG_SYS_UEC##num##_TX_CLK,	\
-		.eth_type	= CONFIG_SYS_UEC##num##_ETH_TYPE,\
+		.ucc_num	= CFG_SYS_UEC##num##_UCC_NUM,\
+		.rx_clock	= CFG_SYS_UEC##num##_RX_CLK,	\
+		.tx_clock	= CFG_SYS_UEC##num##_TX_CLK,	\
+		.eth_type	= CFG_SYS_UEC##num##_ETH_TYPE,\
 	},	\
 	.num_threads_tx		= UEC_NUM_OF_THREADS_1,	\
 	.num_threads_rx		= UEC_NUM_OF_THREADS_1,	\
@@ -616,9 +616,9 @@
 	.risc_rx		= QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
 	.tx_bd_ring_len		= 16,	\
 	.rx_bd_ring_len		= 16,	\
-	.phy_address		= CONFIG_SYS_UEC##num##_PHY_ADDR, \
-	.enet_interface_type	= CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
-	.speed			= CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
+	.phy_address		= CFG_SYS_UEC##num##_PHY_ADDR, \
+	.enet_interface_type	= CFG_SYS_UEC##num##_INTERFACE_TYPE, \
+	.speed			= CFG_SYS_UEC##num##_INTERFACE_SPEED, \
 }
 
 struct uec_inf {

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index d69a9ff..8b6f034 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c

@@ -764,7 +764,7 @@
 	priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
 
 	priv->phyaddr = tsec_info->phyaddr;
-	priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+	priv->tbiaddr = CFG_SYS_TBIPA_VALUE;
 	priv->flags = tsec_info->flags;
 
 	strcpy(dev->name, tsec_info->devname);
@@ -832,7 +832,7 @@
 	struct eth_pdata *pdata = dev_get_plat(dev);
 	struct tsec_private *priv = dev_get_priv(dev);
 	struct ofnode_phandle_args phandle_args;
-	u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+	u32 tbiaddr = CFG_SYS_TBIPA_VALUE;
 	struct tsec_data *data;
 	ofnode parent, child;
 	fdt_addr_t reg;

diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
index af8d99c..09883f0 100644
--- a/drivers/net/vsc7385.c
+++ b/drivers/net/vsc7385.c

@@ -39,13 +39,13 @@
 	u8 *fw = firmware;
 	unsigned int i;
 
-	u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050);
-	u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040);
-	u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044);
-	u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048);
-	u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070);
+	u32 *gloreset = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c050);
+	u32 *icpu_ctrl = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c040);
+	u32 *icpu_addr = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c044);
+	u32 *icpu_data = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c048);
+	u32 *icpu_rom_map = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c070);
 #ifdef DEBUG
-	u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060);
+	u32 *chipid = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c060);
 #endif
 
 	out_be32(gloreset, 3);

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 22f4995..a3b662f 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig

@@ -60,7 +60,7 @@
 	  instead of a physical address (e.g. on MIPS). The PCI core will then remap
 	  the virtual memory base address to a physical address when adding the PCI
 	  region of type PCI_REGION_SYS_MEMORY.
-	  This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still
+	  This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still
 	  being used as virtual address.
 
 config PCI_SRIOV

diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c
index dc11402..b81eb35 100644
--- a/drivers/pci/pci-rcar-gen2.c
+++ b/drivers/pci/pci-rcar-gen2.c

@@ -191,7 +191,7 @@
 
 	/* AHB-PCI Bridge Communication Registers */
 	writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG);
-	writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
+	writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
 	       priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG);
 	writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16,
 	       priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG);
@@ -204,7 +204,7 @@
 	/* PCI Configuration Registers for AHBPCI */
 	devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0);
 	writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0);
-	writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
+	writel(CFG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
 	writel(0xf0000000, devad + PCI_BASE_ADDRESS_2);
 	writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 	       PCI_COMMAND_PARITY | PCI_COMMAND_SERR,

diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index c796892..14fd3bb 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c

@@ -16,9 +16,9 @@
 #include <time.h>
 #include "pci_internal.h"
 
-/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
-#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8
+/* the user can define CFG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CFG_SYS_PCI_CACHE_LINE_SIZE
+#define CFG_SYS_PCI_CACHE_LINE_SIZE	8
 #endif
 
 static void dm_pciauto_setup_device(struct udevice *dev,
@@ -178,7 +178,7 @@
 
 	dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
 	dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
-			     CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+			     CFG_SYS_PCI_CACHE_LINE_SIZE);
 	dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
 }
 

diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c
index d514c04..c1be56c 100644
--- a/drivers/pci/pci_sh7751.c
+++ b/drivers/pci/pci_sh7751.c

@@ -158,9 +158,9 @@
 
 	/* Set up target memory mappings (for external DMA access) */
 	/* Map both P0 and P2 range to Area 3 RAM for ease of use */
-	p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
-	p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
-	p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
+	p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
+	p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
+	p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
 
 	p4_out(0, SH7751_PCILSR1);
 	p4_out(0, SH7751_PCILAR1);

diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 99891dc..a0b82c7 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c

@@ -459,9 +459,9 @@
 	}
 
 	/* Set the BAR base and size towards DDR */
-	bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
+	bar0 = CFG_SYS_SDRAM_BASE & ~0xf;
 	bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
-	writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
+	writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
 
 	reg = ((size >> 20) - 1) << 12;
 	writel(size, regs_base + RESIZABLE_BAR_CTL0);

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index a8f8c31..4600652 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c

@@ -343,8 +343,8 @@
 
 static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
 {
-	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
-	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
+	phys_addr_t phys_start = CFG_SYS_PCI_MEMORY_PHYS;
+	pci_addr_t bus_start = CFG_SYS_PCI_MEMORY_BUS;
 	u64 sz = min((u64)gd->ram_size, (1ull << 32));
 	pci_size_t pci_sz;
 	int idx;
@@ -367,8 +367,8 @@
 		sz = 2ull << __ilog2_u64(sz);
 
 	fsl_pcie_setup_inbound_win(pcie, idx--, true,
-				   CONFIG_SYS_PCI_MEMORY_PHYS,
-				   CONFIG_SYS_PCI_MEMORY_BUS, sz);
+				   CFG_SYS_PCI_MEMORY_PHYS,
+				   CFG_SYS_PCI_MEMORY_BUS, sz);
 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
 	/*
 	 * On 64-bit capable systems, set up a mapping for all of DRAM
@@ -380,12 +380,12 @@
 		pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
 
 	dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
-		(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
-		(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
+		(u64)CFG_SYS_PCI64_MEMORY_BUS,
+		(u64)CFG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
 
 	fsl_pcie_setup_inbound_win(pcie, idx--, true,
-				   CONFIG_SYS_PCI_MEMORY_PHYS,
-				   CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
+				   CFG_SYS_PCI_MEMORY_PHYS,
+				   CFG_SYS_PCI64_MEMORY_BUS, pci_sz);
 #endif
 
 	return 0;

diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index 70c5f4e..ba84a23 100644
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h

@@ -28,16 +28,16 @@
 
 #define DBI_RO_WR_EN			0x8bc
 
-#ifndef CONFIG_SYS_PCI_MEMORY_BUS
-#define CONFIG_SYS_PCI_MEMORY_BUS	0
+#ifndef CFG_SYS_PCI_MEMORY_BUS
+#define CFG_SYS_PCI_MEMORY_BUS	0
 #endif
 
-#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
-#define CONFIG_SYS_PCI_MEMORY_PHYS	0
+#ifndef CFG_SYS_PCI_MEMORY_PHYS
+#define CFG_SYS_PCI_MEMORY_PHYS	0
 #endif
 
-#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
-#define CONFIG_SYS_PCI64_MEMORY_BUS	(64ull * 1024 * 1024 * 1024)
+#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CFG_SYS_PCI64_MEMORY_BUS)
+#define CFG_SYS_PCI64_MEMORY_BUS	(64ull * 1024 * 1024 * 1024)
 #endif
 
 #define PEX_CSR0_LTSSM_MASK		0xFC

diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 8cdf516..b7f692f 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h

@@ -13,20 +13,20 @@
 #include <asm/arch-fsl-layerscape/svr.h>
 #include <asm/arch-ls102xa/svr.h>
 
-#ifndef CONFIG_SYS_PCI_MEMORY_BUS
-#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
+#ifndef CFG_SYS_PCI_MEMORY_BUS
+#define CFG_SYS_PCI_MEMORY_BUS CFG_SYS_SDRAM_BASE
 #endif
 
-#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
-#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
+#ifndef CFG_SYS_PCI_MEMORY_PHYS
+#define CFG_SYS_PCI_MEMORY_PHYS CFG_SYS_SDRAM_BASE
 #endif
 
-#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G
+#ifndef CFG_SYS_PCI_MEMORY_SIZE
+#define CFG_SYS_PCI_MEMORY_SIZE SZ_4G
 #endif
 
-#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
-#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
+#ifndef CFG_SYS_PCI_EP_MEMORY_BASE
+#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
 #endif
 
 #define PCIE_PHYS_SIZE			0x200000000

diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index f2813ae..ff26a5c 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c

@@ -72,7 +72,7 @@
 	u32 vf_flag = 0;
 	u64 phys = 0;
 
-	phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
+	phys = CFG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
 
 	phys = ALIGN(phys, PCIE_BAR0_SIZE);
 	/* ATU 0 : INBOUND : map BAR0 */
@@ -117,8 +117,8 @@
 	/* ATU: OUTBOUND : map MEM */
 	ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
 				 (u64)pcie_ep->addr_res.start +
-				 pf * CONFIG_SYS_PCI_MEMORY_SIZE,
-				 0, CONFIG_SYS_PCI_MEMORY_SIZE);
+				 pf * CFG_SYS_PCI_MEMORY_SIZE,
+				 0, CFG_SYS_PCI_MEMORY_SIZE);
 }
 
 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */

diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 6ecdd6a..021c975 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c

@@ -333,7 +333,7 @@
 	if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)
 		return;
 
-	phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
+	phys = CFG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
 	for (bar = 0; bar < PF_BAR_NUM; bar++) {
 		ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);
 		phys += PCIE_BAR_SIZE;
@@ -342,8 +342,8 @@
 	/* OUTBOUND: map MEM */
 	ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,
 				    pcie->cfg_res.start +
-				    CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
-				    CONFIG_SYS_PCI_MEMORY_SIZE);
+				    CFG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
+				    CFG_SYS_PCI_MEMORY_SIZE);
 
 	val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));
 	val &= ~FUNC_NUM_PCIE_MASK;

diff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h
index 483eb53..805c23a 100644
--- a/drivers/pci/pcie_layerscape_gen4.h
+++ b/drivers/pci/pcie_layerscape_gen4.h

@@ -11,12 +11,12 @@
 #include <pci.h>
 #include <linux/bitops.h>
 
-#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE		(4 * 1024 * 1024 * 1024ULL)
+#ifndef CFG_SYS_PCI_MEMORY_SIZE
+#define CFG_SYS_PCI_MEMORY_SIZE		(4 * 1024 * 1024 * 1024ULL)
 #endif
 
-#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
-#define CONFIG_SYS_PCI_EP_MEMORY_BASE		CONFIG_SYS_LOAD_ADDR
+#ifndef CFG_SYS_PCI_EP_MEMORY_BASE
+#define CFG_SYS_PCI_EP_MEMORY_BASE		CONFIG_SYS_LOAD_ADDR
 #endif
 
 #define PCIE_PF_NUM				2

diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index bc47cf1..7f3b990 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig

@@ -411,6 +411,9 @@
 	is typically used to power the VDD-CPU and should be 1200mV.
 	Values can range from 680mV till 1950mV.
 
+config TPS6586X_POWER
+	bool "Enable legacy driver for TI TPS6586x power management chip"
+
 config TWL4030_POWER
 	depends on OMAP34XX
 	bool "Enable driver for TI TWL4030 power management chip"
@@ -419,6 +422,10 @@
 	The TWL4030 in a combination audio CODEC/power management with
 	GPIO and it is commonly used with the OMAP3 family of processors
 
+config TWL6030_POWER
+	depends on OMAP44XX
+	bool "Enable driver for TI TWL6030 power management chip"
+
 config POWER_MT6323
 	bool "Poweroff driver for mediatek mt6323"
 	select CMD_POWEROFF
@@ -430,6 +437,10 @@
 	bool "Palmas power support"
 	depends on OMAP54XX
 
+config POWER_FSL
+	bool "Power control (legacy) for Freescale / NXP platforms"
+	depends on POWER_LEGACY
+
 config POWER_I2C
 	bool "I2C-based power control for legacy power"
 	depends on POWER_LEGACY
@@ -440,6 +451,10 @@
 	  Not to be used for new designs and existing ones should be moved to
 	  the new PMIC interface based on driver model.
 
+config POWER_SPI
+	bool "SPI-based power control for legacy power_fsl driver"
+	depends on POWER_FSL && !POWER_I2C
+
 config SPL_POWER_I2C
 	bool "I2C-based power control for legacy power"
 	depends on SPL_POWER_LEGACY
@@ -451,4 +466,17 @@
 	  Not to be used for new designs and existing ones should be moved to
 	  the new PMIC interface based on driver model.
 
+choice
+	prompt "PMIC chip"
+	default POWER_FSL_MC13892
+	depends on POWER_FSL && POWER_I2C
+
+config POWER_FSL_MC13892
+	bool "MC13892"
+
+config POWER_FSL_MC34704
+	bool "MC34704"
+
+endchoice
+
 endif

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 628d3a9..d94048d 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig

@@ -393,10 +393,40 @@
 	only, and you can enable the regulator/charger drivers separately if
 	required.
 
+config POWER_TPS65218
+	bool "Enable legacy driver for TPS65218 PMIC"
+
+config POWER_TPS62362
+	bool "Enable legacy driver for TPS62362 PMIC"
+
+config SPL_POWER_TPS62362
+	bool "Enable legacy driver for TPS62362 PMIC in SPL"
+	default y if POWER_TPS62362
+	depends on SPL
+
+config SPL_POWER_TPS65910
+	bool "Enable legacy driver for TPS65910 PMIC in SPL"
+	depends on SPL
+
+if POWER_LEGACY || SPL_POWER_LEGACY
+
+config POWER_HI6553
+	bool "Enable legacy driver for HI6553 PMIC"
+
+config POWER_LTC3676
+	bool "Enable legacy driver for LTC3676 PMIC"
+
+config POWER_PFUZE100
+	bool "Enable legacy driver for PFUZE100 PMIC"
+
+config POWER_PFUZE3000
+	bool "Enable legacy driver for PFUZE3000 PMIC"
+
 config POWER_MC34VR500
 	bool "Enable driver for Freescale MC34VR500 PMIC"
-	depends on !DM_PMIC
 	---help---
 	The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
 	SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed
 	via an I2C interface.
+
+endif

diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 58c6507..c3180c5 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile

@@ -30,17 +30,20 @@
 obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
 obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
 obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
+obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
+obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
+obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
+obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
 
+ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
 obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
 obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o
 obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
 obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
-obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
-obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
-obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
-obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
 obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o
 obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o
-obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
-obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
+endif
+
+obj-$(CONFIG_$(SPL_)POWER_TPS62362) += pmic_tps62362.o
+obj-$(CONFIG_SPL_POWER_TPS65910) += pmic_tps65910.o

diff --git a/drivers/power/power_dialog.c b/drivers/power/power_dialog.c
index e286dd1..ad7aaf3 100644
--- a/drivers/power/power_dialog.c
+++ b/drivers/power/power_dialog.c

@@ -24,7 +24,7 @@
 	p->number_of_regs = DIALOG_NUM_OF_REGS;
 
 	p->interface = PMIC_I2C;
-	p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR;
+	p->hw.i2c.addr = CFG_SYS_DIALOG_PMIC_I2C_ADDR;
 	p->hw.i2c.tx_num = 1;
 	p->bus = bus;
 

diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c
index 7180b51..9bb7e39 100644
--- a/drivers/power/power_fsl.c
+++ b/drivers/power/power_fsl.c

@@ -49,8 +49,6 @@
 	p->interface = PMIC_I2C;
 	p->hw.i2c.addr = CFG_SYS_FSL_PMIC_I2C_ADDR;
 	p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
-#else
-#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C"
 #endif
 
 	return 0;

diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 83461c0..63371e7 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h

@@ -605,10 +605,10 @@
 #define STD_UEC_INFO(num) \
 {			\
 	.uf_info		= {	\
-		.ucc_num	= CONFIG_SYS_UEC##num##_UCC_NUM,\
-		.rx_clock	= CONFIG_SYS_UEC##num##_RX_CLK,	\
-		.tx_clock	= CONFIG_SYS_UEC##num##_TX_CLK,	\
-		.eth_type	= CONFIG_SYS_UEC##num##_ETH_TYPE,\
+		.ucc_num	= CFG_SYS_UEC##num##_UCC_NUM,\
+		.rx_clock	= CFG_SYS_UEC##num##_RX_CLK,	\
+		.tx_clock	= CFG_SYS_UEC##num##_TX_CLK,	\
+		.eth_type	= CFG_SYS_UEC##num##_ETH_TYPE,\
 	},	\
 	.num_threads_tx		= UEC_NUM_OF_THREADS_1,	\
 	.num_threads_rx		= UEC_NUM_OF_THREADS_1,	\
@@ -616,9 +616,9 @@
 	.risc_rx		= QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
 	.tx_bd_ring_len		= 16,	\
 	.rx_bd_ring_len		= 16,	\
-	.phy_address		= CONFIG_SYS_UEC##num##_PHY_ADDR, \
-	.enet_interface_type	= CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
-	.speed			= CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
+	.phy_address		= CFG_SYS_UEC##num##_PHY_ADDR, \
+	.enet_interface_type	= CFG_SYS_UEC##num##_INTERFACE_TYPE, \
+	.speed			= CFG_SYS_UEC##num##_INTERFACE_SPEED, \
 }
 
 struct uec_inf {

diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 9d429c8..fcf06d1 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c

@@ -52,7 +52,7 @@
  *
  * Some boards do not have a PHY for each ethernet port. These ports are known
  * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
- * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
+ * CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
  * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
  * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
  * speed and duplex should be for the port.
@@ -61,10 +61,10 @@
  *     #define CONFIG_FIXED_PHY   0xFFFFFFFF
  *     #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
  *
- *     #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
- *     #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
- *     #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
- *     #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
+ *     #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ *     #define CFG_SYS_UEC2_PHY_ADDR 0x02
+ *     #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ *     #define CFG_SYS_UEC4_PHY_ADDR 0x04
  *
  *     #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
  *                 {name, speed, duplex},

diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c
index 141b19b..dc466a8 100644
--- a/drivers/ram/aspeed/sdram_ast2500.c
+++ b/drivers/ram/aspeed/sdram_ast2500.c

@@ -203,7 +203,7 @@
 	u32 test_pattern = 0xdeadbeef;
 	u32 cap_param = SDRAM_CONF_CAP_1024M;
 	u32 refresh_timing_param = DDR4_TRFC;
-	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
+	const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
 
 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
 	     ram_size >>= 1) {
@@ -231,7 +231,7 @@
 			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
 			 << SDRAM_AC_TRFC_SHIFT));
 
-	info->info.base = CONFIG_SYS_SDRAM_BASE;
+	info->info.base = CFG_SYS_SDRAM_BASE;
 	info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
 	clrsetbits_le32(&info->regs->config,
 			(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),

diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index 5d42608..a2d7ca8 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c

@@ -838,7 +838,7 @@
 	u32 test_pattern = 0xdeadbeef;
 	u32 cap_param = SDRAM_CONF_CAP_2048M;
 	u32 refresh_timing_param = DDR4_TRFC;
-	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
+	const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
 
 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
 	     ram_size >>= 1) {
@@ -866,7 +866,7 @@
 			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
 			 << SDRAM_AC_TRFC_SHIFT));
 
-	info->info.base = CONFIG_SYS_SDRAM_BASE;
+	info->info.base = CFG_SYS_SDRAM_BASE;
 	info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
 
 	clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK,
@@ -1015,7 +1015,7 @@
 		break;
 	}
 
-	info->info.base = CONFIG_SYS_SDRAM_BASE;
+	info->info.base = CFG_SYS_SDRAM_BASE;
 	info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
 
 	if (0 == (conf & SDRAM_CONF_ECC_SETUP))

diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c
index d12a3b4..1737fda 100644
--- a/drivers/ram/mediatek/ddr3-mt7629.c
+++ b/drivers/ram/mediatek/ddr3-mt7629.c

@@ -243,17 +243,17 @@
 	 * and it has maximum addressing region
 	 */
 
-	writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE);
+	writel(WALKING_PATTERN, CFG_SYS_SDRAM_BASE);
 
-	if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN)
+	if (readl(CFG_SYS_SDRAM_BASE) != WALKING_PATTERN)
 		return -EINVAL;
 
 	for (step = 0; step < 5; step++) {
-		writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE +
+		writel(~WALKING_PATTERN, CFG_SYS_SDRAM_BASE +
 		       (WALKING_STEP << step));
 
-		start = readl(CONFIG_SYS_SDRAM_BASE);
-		test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step));
+		start = readl(CFG_SYS_SDRAM_BASE);
+		test = readl(CFG_SYS_SDRAM_BASE + (WALKING_STEP << step));
 		if ((test != ~WALKING_PATTERN) || test == start)
 			break;
 	}
@@ -727,7 +727,7 @@
 	struct mtk_ddr3_priv *priv = dev_get_priv(dev);
 	u32 val = readl(priv->emi + EMI_CONA);
 
-	info->base = CONFIG_SYS_SDRAM_BASE;
+	info->base = CFG_SYS_SDRAM_BASE;
 
 	switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) {
 	case 0:

diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
index 42daf06..bb21078 100644
--- a/drivers/ram/octeon/octeon_ddr.c
+++ b/drivers/ram/octeon/octeon_ddr.c

@@ -2687,7 +2687,7 @@
 	if (!mem_mbytes)
 		return -ENODEV;
 
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size = MB(mem_mbytes);
 
 	/*

diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index 69c454a..6929a7e 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c

@@ -617,12 +617,12 @@
 
 	/* Detect col */
 	for (col = 11; col >= 9; col--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE +
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE +
 			(1 << (col + params->chan.bw - 1));
 		writel(test_pattern, addr);
 		if ((readl(addr) == test_pattern) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 
@@ -637,11 +637,11 @@
 
 	/* Detect row*/
 	for (row = 16; row >= 12; row--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
 		writel(test_pattern, addr);
 		if ((readl(addr) == test_pattern) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 

diff --git a/drivers/ram/rockchip/sdram_common.c b/drivers/ram/rockchip/sdram_common.c
index b3e7421..ec46ba5 100644
--- a/drivers/ram/rockchip/sdram_common.c
+++ b/drivers/ram/rockchip/sdram_common.c

@@ -220,12 +220,12 @@
 	u32 bw = cap_info->bw;
 
 	for (col = coltmp; col >= 9; col -= 1) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+		writel(0, CFG_SYS_SDRAM_BASE);
+		test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
 				(1ul << (col + bw - 1ul)));
 		writel(PATTERN, test_addr);
 		if ((readl(test_addr) == PATTERN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (col == 8) {
@@ -245,12 +245,12 @@
 	u32 bk;
 	u32 bw = cap_info->bw;
 
-	test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+	test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
 			(1ul << (coltmp + bktmp + bw - 1ul)));
-	writel(0, CONFIG_SYS_SDRAM_BASE);
+	writel(0, CFG_SYS_SDRAM_BASE);
 	writel(PATTERN, test_addr);
 	if ((readl(test_addr) == PATTERN) &&
-	    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+	    (readl(CFG_SYS_SDRAM_BASE) == 0))
 		bk = 3;
 	else
 		bk = 2;
@@ -268,12 +268,12 @@
 	u32 dbw;
 	u32 bw = cap_info->bw;
 
-	test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+	test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
 			(1ul << (coltmp + bw + 1ul)));
-	writel(0, CONFIG_SYS_SDRAM_BASE);
+	writel(0, CFG_SYS_SDRAM_BASE);
 	writel(PATTERN, test_addr);
 	if ((readl(test_addr) == PATTERN) &&
-	    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+	    (readl(CFG_SYS_SDRAM_BASE) == 0))
 		dbw = 0;
 	else
 		dbw = 1;
@@ -337,12 +337,12 @@
 	void __iomem *test_addr;
 
 	for (row = rowtmp; row > 12; row--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+		writel(0, CFG_SYS_SDRAM_BASE);
+		test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
 				(1ul << (row + bktmp + coltmp + bw - 1ul)));
 		writel(PATTERN, test_addr);
 		if ((readl(test_addr) == PATTERN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (row == 12) {
@@ -363,8 +363,8 @@
 	u32 row = cap_info->cs0_row;
 	void __iomem *test_addr, *test_addr1;
 
-	test_addr = CONFIG_SYS_SDRAM_BASE;
-	test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+	test_addr = CFG_SYS_SDRAM_BASE;
+	test_addr1 = (void __iomem *)(CFG_SYS_SDRAM_BASE +
 			(0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
 
 	writel(0, test_addr);
@@ -421,15 +421,15 @@
 
 		/* detect cs1 row */
 		for (row = cap_info->cs0_row; row > 12; row--) {
-			test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+			test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
 				    cs0_cap +
 				    (1ul << (row + bktmp + coltmp + bw - 1ul)));
-			writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap);
+			writel(0, CFG_SYS_SDRAM_BASE + cs0_cap);
 			writel(PATTERN, test_addr);
 
 			if (((readl(test_addr) & byte_mask) ==
 			     (PATTERN & byte_mask)) &&
-			    ((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) &
+			    ((readl(CFG_SYS_SDRAM_BASE + cs0_cap) &
 			      byte_mask) == 0)) {
 				break;
 			}

diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c
index c024a0c..98b2593 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c

@@ -726,7 +726,7 @@
 
 	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 	debug("%s: grf=%p\n", __func__, priv->pmugrf);
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size =
 		rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
 

diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c
index 832154e..a2425f2 100644
--- a/drivers/ram/rockchip/sdram_rk3066.c
+++ b/drivers/ram/rockchip/sdram_rk3066.c

@@ -616,12 +616,12 @@
 
 	/* Detect col. */
 	for (col = 11; col >= 9; col--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE +
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE +
 		       (1 << (col + sdram_params->ch[channel].bw - 1));
 		writel(TEST_PATTERN, addr);
 		if ((readl(addr) == TEST_PATTERN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (col == 8) {
@@ -638,11 +638,11 @@
 	rk3066_dmc_move_to_access_state(chan);
 	/* Detect row, max 15, min13 for rk3066 */
 	for (row = 16; row >= 13; row--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
 		writel(TEST_PATTERN, addr);
 		if ((readl(addr) == TEST_PATTERN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (row == 12) {
@@ -854,7 +854,7 @@
 		if (ret)
 			return ret;
 	} else {
-		priv->info.base = CONFIG_SYS_SDRAM_BASE;
+		priv->info.base = CFG_SYS_SDRAM_BASE;
 		priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]);
 	}
 

diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c
index 16cfbf9..ded6539 100644
--- a/drivers/ram/rockchip/sdram_rk3128.c
+++ b/drivers/ram/rockchip/sdram_rk3128.c

@@ -23,7 +23,7 @@
 
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 	debug("%s: grf=%p\n", __func__, priv->grf);
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size = rockchip_sdram_size(
 				(phys_addr_t)&priv->grf->os_reg[1]);
 

diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c
index be8ba44..272b1b2 100644
--- a/drivers/ram/rockchip/sdram_rk3188.c
+++ b/drivers/ram/rockchip/sdram_rk3188.c

@@ -638,12 +638,12 @@
 
 	/* Detect col */
 	for (col = 11; col >= 9; col--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE +
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE +
 			(1 << (col + sdram_params->ch[channel].bw - 1));
 		writel(TEST_PATTEN, addr);
 		if ((readl(addr) == TEST_PATTEN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (col == 8) {
@@ -660,11 +660,11 @@
 	move_to_access_state(chan);
 	/* Detect row, max 15,min13 in rk3188*/
 	for (row = 16; row >= 13; row--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
 		writel(TEST_PATTEN, addr);
 		if ((readl(addr) == TEST_PATTEN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (row == 12) {
@@ -919,7 +919,7 @@
 	if (ret)
 		return ret;
 #else
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size = rockchip_sdram_size(
 				(phys_addr_t)&priv->pmu->sys_reg[2]);
 #endif

diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c
index cd4234f..1b204fb 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c

@@ -636,12 +636,12 @@
 		writel(3, &axi_bus->ddrconf);
 	move_to_access_state(dram->chan[0].pctl);
 	for (col = 11; col >= 9; col--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE +
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE +
 			(1 << (col + bw - 1));
 		writel(TEST_PATTEN, addr);
 		if ((readl(addr) == TEST_PATTEN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (col == 8) {
@@ -656,11 +656,11 @@
 
 	/* Detect row*/
 	for (row = 16; row >= 12; row--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
 		writel(TEST_PATTEN, addr);
 		if ((readl(addr) == TEST_PATTEN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (row == 11) {
@@ -672,11 +672,11 @@
 		sdram_params->ch[0].cs0_row = row;
 	}
 	/* cs detect */
-	writel(0, CONFIG_SYS_SDRAM_BASE);
-	writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30));
-	writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4);
-	if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
-	    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+	writel(0, CFG_SYS_SDRAM_BASE);
+	writel(TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30));
+	writel(~TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30) + 4);
+	if ((readl(CFG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
+	    (readl(CFG_SYS_SDRAM_BASE) == 0))
 		sdram_params->ch[0].rank = 2;
 	else
 		sdram_params->ch[0].rank = 1;
@@ -813,7 +813,7 @@
 	if (ret)
 		return ret;
 #else
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size = rockchip_sdram_size(
 			(phys_addr_t)&priv->grf->os_reg[2]);
 #endif

diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
index 227a3cc..83778ad 100644
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c

@@ -684,12 +684,12 @@
 
 	/* Detect col */
 	for (col = 11; col >= 9; col--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE +
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE +
 			(1 << (col + sdram_params->ch[channel].bw - 1));
 		writel(TEST_PATTEN, addr);
 		if ((readl(addr) == TEST_PATTEN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (col == 8) {
@@ -705,11 +705,11 @@
 	move_to_access_state(chan);
 	/* Detect row*/
 	for (row = 16; row >= 12; row--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
 		writel(TEST_PATTEN, addr);
 		if ((readl(addr) == TEST_PATTEN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (row == 11) {
@@ -1087,7 +1087,7 @@
 	if (ret)
 		return ret;
 #else
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size = rockchip_sdram_size(
 			(phys_addr_t)&priv->pmu->sys_reg[2]);
 #endif

diff --git a/drivers/ram/rockchip/sdram_rk3308.c b/drivers/ram/rockchip/sdram_rk3308.c
index 44d7d8a..10828e8 100644
--- a/drivers/ram/rockchip/sdram_rk3308.c
+++ b/drivers/ram/rockchip/sdram_rk3308.c

@@ -21,7 +21,7 @@
 	struct dram_info *priv = dev_get_priv(dev);
 
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2);
 
 	return 0;

diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c
index 9c6798f..b511c6b 100644
--- a/drivers/ram/rockchip/sdram_rk3328.c
+++ b/drivers/ram/rockchip/sdram_rk3328.c

@@ -580,7 +580,7 @@
 
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 	debug("%s: grf=%p\n", __func__, priv->grf);
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size = rockchip_sdram_size(
 				(phys_addr_t)&priv->grf->os_reg[2]);
 #endif

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index cbf502b..136e4ed 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c

@@ -3151,7 +3151,7 @@
 
 	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 	debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size =
 		rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
 #endif

diff --git a/drivers/ram/rockchip/sdram_rk3568.c b/drivers/ram/rockchip/sdram_rk3568.c
index 0ac4b54..f661615 100644
--- a/drivers/ram/rockchip/sdram_rk3568.c
+++ b/drivers/ram/rockchip/sdram_rk3568.c

@@ -21,7 +21,7 @@
 	struct dram_info *priv = dev_get_priv(dev);
 
 	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size =
 		rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);
 

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 2396327..b698722 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig

@@ -68,9 +68,38 @@
 	bool "Enable DS1307 driver"
 	depends on DM_RTC
 	help
-	  Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and
+	  Support for Dallas Semiconductor (now Maxim) DS1307 and DS1339 and
 	  compatible Real Time Clock devices.
 
+config RTC_DS1337
+	bool "Enable DS1337 driver"
+	help
+	  Support for Dallas Semiconductor (now Maxim) DS1337/8/9 compatible
+	  Real Time Clock devices.
+
+config RTC_DS1337_NOOSC
+	bool "Enable support for no oscillator output in DS1337 driver"
+	depends on RTC_DS1337
+
+config RTC_DS1338
+	bool "Enable DS1338 driver"
+	help
+	  Support for Dallas Semiconductor (now Maxim) DS1338 and compatible
+	  Real Time Clock devices.
+
+config RTC_DS1374
+	bool "Enable DS1374 driver"
+	depends on !DM_RTC
+	help
+	  Support for Dallas Semiconductor (now Maxim) DS1374 and compatible
+	  Real Time Clock devices.
+
+config RTC_DS3231
+	bool "Enable DS3231 driver"
+	help
+	  Support for Dallas Semiconductor (now Maxim) DS3231 compatible
+	  Real Time Clock devices.
+
 config RTC_DS3232
 	bool "Enable DS3232 driver"
 	depends on DM_RTC
@@ -111,6 +140,9 @@
 	  If you say yes here you get support for the Philips PCF8563 RTC
 	  and compatible chips.
 
+config RTC_PT7C4338
+	bool "Enable Pericom Technology PT7C4338 RTC driver"
+
 config RTC_RV3028
 	bool "Enable RV3028 driver"
 	depends on DM_RTC
@@ -169,6 +201,10 @@
 	help
 	  Enable s35392a driver which provides rtc get and set function.
 
+config RTC_MC13XXX
+	bool "Enable MC13XXX RTC driver"
+	depends on !DM_RTC
+
 config RTC_MC146818
 	bool "Enable MC146818 driver"
 	help
@@ -185,6 +221,10 @@
 	hex "Base address for RTC in immap.h"
 	depends on MCFRTC
 
+config RTC_MXS
+	bool "Enable i.MXS RTC driver"
+	depends on ARCH_MX23 || ARCH_MX28
+
 config RTC_M41T62
 	bool "Enable M41T62 driver"
 	help

diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 009dd9d..2089086 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile

@@ -17,9 +17,6 @@
 obj-$(CONFIG_RTC_DS1337) += ds1337.o
 obj-$(CONFIG_RTC_DS1374) += ds1374.o
 obj-$(CONFIG_RTC_DS1388) += ds1337.o
-obj-$(CONFIG_RTC_DS1556) += ds1556.o
-obj-$(CONFIG_RTC_DS164x) += ds164x.o
-obj-$(CONFIG_RTC_DS174x) += ds174x.o
 obj-$(CONFIG_RTC_DS3231) += ds3231.o
 obj-$(CONFIG_RTC_DS3232) += ds3232.o
 obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o

diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c
index 40ca66b..0e9d3d2 100644
--- a/drivers/rtc/ds1307.c
+++ b/drivers/rtc/ds1307.c

@@ -80,8 +80,8 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#ifndef CFG_SYS_I2C_RTC_ADDR
+# define CFG_SYS_I2C_RTC_ADDR	0x68
 #endif
 
 #if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
@@ -212,13 +212,13 @@
 static
 uchar rtc_read (uchar reg)
 {
-	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+	return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
 }
 
 
 static void rtc_write (uchar reg, uchar val)
 {
-	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+	i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
 }
 
 #endif /* !CONFIG_DM_RTC */

diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c
index 486c01f..2c780ab 100644
--- a/drivers/rtc/ds1337.c
+++ b/drivers/rtc/ds1337.c

@@ -184,13 +184,13 @@
 static
 uchar rtc_read (uchar reg)
 {
-	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+	return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
 }
 
 
 static void rtc_write (uchar reg, uchar val)
 {
-	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+	i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
 }
 #else
 static uchar rtc_read(struct udevice *dev, uchar reg)

diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c
index 9f2647d..89442f9 100644
--- a/drivers/rtc/ds1374.c
+++ b/drivers/rtc/ds1374.c

@@ -29,8 +29,8 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#ifndef CFG_SYS_I2C_RTC_ADDR
+# define CFG_SYS_I2C_RTC_ADDR	0x68
 #endif
 
 #if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
@@ -194,21 +194,21 @@
  */
 static uchar rtc_read (uchar reg)
 {
-	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+	return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
 }
 
 static void rtc_write(uchar reg, uchar val, bool set)
 {
 	if (set == true) {
-		val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
-		i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+		val |= i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg);
+		i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
 	} else {
-		val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val;
-		i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+		val = i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg) & ~val;
+		i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
 	}
 }
 
 static void rtc_write_raw (uchar reg, uchar val)
 {
-		i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+		i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
 }

diff --git a/drivers/rtc/ds1556.c b/drivers/rtc/ds1556.c
deleted file mode 100644
index 687b329..0000000
--- a/drivers/rtc/ds1556.c
+++ /dev/null

@@ -1,179 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * ARIO Data Networks, Inc. dchiu@ariodata.com
- *
- * modified for DS1556:
- * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
- *
- * Based on MontaVista DS1743 code and U-Boot mc146818 code
- */
-
-/*
- * Date & Time support for the DS1556 RTC
- */
-
-/*#define	RTC_DEBUG */
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-static uchar rtc_read( unsigned int addr );
-static void  rtc_write( unsigned int addr, uchar val);
-
-#define RTC_BASE		( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR )
-
-#define RTC_YEAR		( RTC_BASE + 0xf )
-#define RTC_MONTH		( RTC_BASE + 0xe )
-#define RTC_DAY_OF_MONTH	( RTC_BASE + 0xd )
-#define RTC_DAY_OF_WEEK		( RTC_BASE + 0xc )
-#define RTC_HOURS		( RTC_BASE + 0xb )
-#define RTC_MINUTES		( RTC_BASE + 0xa )
-#define RTC_SECONDS		( RTC_BASE + 0x9 )
-#define RTC_CENTURY		( RTC_BASE + 0x8 )
-
-#define RTC_CONTROLA		RTC_CENTURY
-#define RTC_CONTROLB		RTC_SECONDS
-#define RTC_CONTROLC		RTC_BASE
-
-#define RTC_CA_WRITE		0x80
-#define RTC_CA_READ		0x40
-
-#define RTC_CB_OSC_DISABLE	0x80
-
-#define RTC_CC_BATTERY_FLAG	0x10
-#define RTC_CC_FREQ_TEST	0x40
-
-/* ------------------------------------------------------------------------- */
-
-int rtc_get( struct rtc_time *tmp )
-{
-	uchar sec, min, hour;
-	uchar mday, wday, mon, year;
-
-	int century;
-
-	uchar reg_a;
-
-	reg_a = rtc_read( RTC_CONTROLA );
-	/* lock clock registers for read */
-	rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
-
-	sec     = rtc_read( RTC_SECONDS );
-	min     = rtc_read( RTC_MINUTES );
-	hour    = rtc_read( RTC_HOURS );
-	mday    = rtc_read( RTC_DAY_OF_MONTH );
-	wday    = rtc_read( RTC_DAY_OF_WEEK );
-	mon     = rtc_read( RTC_MONTH );
-	year    = rtc_read( RTC_YEAR );
-	century = rtc_read( RTC_CENTURY );
-
-	/* unlock clock registers after read */
-	rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
-
-#ifdef RTC_DEBUG
-	printf( "Get RTC year: %02x mon/cent: %02x mon: %02x mday: %02x wday: %02x "
-		"hr: %02x min: %02x sec: %02x\n",
-		year, century, mon, mday, wday,
-		hour, min, sec );
-#endif
-	tmp->tm_sec  = bcd2bin( sec  & 0x7F );
-	tmp->tm_min  = bcd2bin( min  & 0x7F );
-	tmp->tm_hour = bcd2bin( hour & 0x3F );
-	tmp->tm_mday = bcd2bin( mday & 0x3F );
-	tmp->tm_mon  = bcd2bin( mon & 0x1F );
-	tmp->tm_wday = bcd2bin( wday & 0x07 );
-
-	/* glue year from century and year in century */
-	tmp->tm_year = bcd2bin( year ) +
-		( bcd2bin( century & 0x3F ) * 100 );
-
-	tmp->tm_yday = 0;
-	tmp->tm_isdst= 0;
-#ifdef RTC_DEBUG
-	printf( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
-#endif
-	return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
-	uchar reg_a;
-#ifdef RTC_DEBUG
-	printf( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
-	/* lock clock registers for write */
-	reg_a = rtc_read( RTC_CONTROLA );
-	rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
-
-	rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
-
-	rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
-	rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
-	rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
-	rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
-	rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
-
-	/* break year up into century and year in century */
-	rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
-	rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
-
-	/* unlock clock registers after read */
-	rtc_write( RTC_CONTROLA, ( reg_a  & ~RTC_CA_WRITE ));
-
-	return 0;
-}
-
-void rtc_reset (void)
-{
-	uchar reg_a, reg_b, reg_c;
-
-	reg_a = rtc_read( RTC_CONTROLA );
-	reg_b = rtc_read( RTC_CONTROLB );
-
-	if ( reg_b & RTC_CB_OSC_DISABLE )
-	{
-		printf( "real-time-clock was stopped. Now starting...\n" );
-		reg_a |= RTC_CA_WRITE;
-		reg_b &= ~RTC_CB_OSC_DISABLE;
-
-		rtc_write( RTC_CONTROLA, reg_a );
-		rtc_write( RTC_CONTROLB, reg_b );
-	}
-
-	/* make sure read/write clock register bits are cleared */
-	reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
-	rtc_write( RTC_CONTROLA, reg_a );
-
-	reg_c = rtc_read( RTC_CONTROLC );
-	if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
-		printf( "RTC battery low. Clock setting may not be reliable.\n" );
-}
-
-/* ------------------------------------------------------------------------- */
-
-static uchar rtc_read( unsigned int addr )
-{
-	uchar val = *(volatile unsigned char*)(addr);
-#ifdef RTC_DEBUG
-	printf( "rtc_read: %x:%x\n", addr, val );
-#endif
-	return( val );
-}
-
-static void rtc_write( unsigned int addr, uchar val )
-{
-#ifdef RTC_DEBUG
-	printf( "rtc_write: %x:%x\n", addr, val );
-#endif
-	*(volatile unsigned char*)(addr) = val;
-}
-
-#endif

diff --git a/drivers/rtc/ds164x.c b/drivers/rtc/ds164x.c
deleted file mode 100644
index f870789..0000000
--- a/drivers/rtc/ds164x.c
+++ /dev/null

@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * ARIO Data Networks, Inc. dchiu@ariodata.com
- *
- * modified for DS164x:
- * The LEOX team <team@leox.org>, http://www.leox.org
- *
- * Based on MontaVista DS1743 code and U-Boot mc146818 code
- */
-
-/*
- * Date & Time support for the DS164x RTC
- */
-
-/* #define	RTC_DEBUG */
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-
-static uchar    rtc_read(unsigned int addr );
-static void     rtc_write(unsigned int addr, uchar val);
-
-#define RTC_EPOCH                 2000	/* century */
-
-/*
- * DS164x registers layout
- */
-#define RTC_BASE		( CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE )
-
-#define RTC_YEAR		( RTC_BASE + 0x07 )
-#define RTC_MONTH		( RTC_BASE + 0x06 )
-#define RTC_DAY_OF_MONTH	( RTC_BASE + 0x05 )
-#define RTC_DAY_OF_WEEK		( RTC_BASE + 0x04 )
-#define RTC_HOURS		( RTC_BASE + 0x03 )
-#define RTC_MINUTES		( RTC_BASE + 0x02 )
-#define RTC_SECONDS		( RTC_BASE + 0x01 )
-#define RTC_CONTROL		( RTC_BASE + 0x00 )
-
-#define RTC_CONTROLA		RTC_CONTROL	/* W=bit6, R=bit5 */
-#define   RTC_CA_WRITE		  0x80
-#define   RTC_CA_READ		  0x40
-#define RTC_CONTROLB		RTC_SECONDS	/* OSC=bit7       */
-#define   RTC_CB_OSC_DISABLE	  0x80
-#define RTC_CONTROLC		RTC_DAY_OF_WEEK	/* FT=bit6        */
-#define   RTC_CC_FREQ_TEST	  0x40
-
-/* ------------------------------------------------------------------------- */
-
-int rtc_get( struct rtc_time *tmp )
-{
-	uchar sec, min, hour;
-	uchar mday, wday, mon, year;
-
-	uchar reg_a;
-
-	reg_a = rtc_read( RTC_CONTROLA );
-	/* lock clock registers for read */
-	rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
-
-	sec     = rtc_read( RTC_SECONDS );
-	min     = rtc_read( RTC_MINUTES );
-	hour    = rtc_read( RTC_HOURS );
-	mday    = rtc_read( RTC_DAY_OF_MONTH );
-	wday    = rtc_read( RTC_DAY_OF_WEEK );
-	mon     = rtc_read( RTC_MONTH );
-	year    = rtc_read( RTC_YEAR );
-
-	/* unlock clock registers after read */
-	rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
-
-#ifdef RTC_DEBUG
-	printf( "Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
-		"hr: %02x min: %02x sec: %02x\n",
-		year, mon, mday, wday,
-		hour, min, sec );
-#endif
-	tmp->tm_sec  = bcd2bin( sec  & 0x7F );
-	tmp->tm_min  = bcd2bin( min  & 0x7F );
-	tmp->tm_hour = bcd2bin( hour & 0x3F );
-	tmp->tm_mday = bcd2bin( mday & 0x3F );
-	tmp->tm_mon  = bcd2bin( mon  & 0x1F );
-	tmp->tm_wday = bcd2bin( wday & 0x07 );
-
-	/* glue year in century (2000) */
-	tmp->tm_year = bcd2bin( year ) + RTC_EPOCH;
-
-	tmp->tm_yday = 0;
-	tmp->tm_isdst= 0;
-#ifdef RTC_DEBUG
-	printf( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
-#endif
-
-	return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
-	uchar reg_a;
-
-#ifdef RTC_DEBUG
-	printf( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
-	/* lock clock registers for write */
-	reg_a = rtc_read( RTC_CONTROLA );
-	rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
-
-	rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
-
-	rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
-	rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
-	rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
-	rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
-	rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
-
-	/* break year in century */
-	rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
-
-	/* unlock clock registers after read */
-	rtc_write( RTC_CONTROLA, ( reg_a  & ~RTC_CA_WRITE ));
-
-	return 0;
-}
-
-void rtc_reset (void)
-{
-	uchar reg_a, reg_b;
-
-	reg_a = rtc_read( RTC_CONTROLA );
-	reg_b = rtc_read( RTC_CONTROLB );
-
-	if ( reg_b & RTC_CB_OSC_DISABLE )
-	{
-		printf( "real-time-clock was stopped. Now starting...\n" );
-		reg_a |= RTC_CA_WRITE;
-		reg_b &= ~RTC_CB_OSC_DISABLE;
-
-		rtc_write( RTC_CONTROLA, reg_a );
-		rtc_write( RTC_CONTROLB, reg_b );
-	}
-
-	/* make sure read/write clock register bits are cleared */
-	reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
-	rtc_write( RTC_CONTROLA, reg_a );
-}
-
-/* ------------------------------------------------------------------------- */
-
-static uchar rtc_read( unsigned int addr )
-{
-	uchar val = *(volatile unsigned char*)(addr);
-
-#ifdef RTC_DEBUG
-	printf( "rtc_read: %x:%x\n", addr, val );
-#endif
-	return( val );
-}
-
-static void rtc_write( unsigned int addr, uchar val )
-{
-#ifdef RTC_DEBUG
-	printf( "rtc_write: %x:%x\n", addr, val );
-#endif
-	*(volatile unsigned char*)(addr) = val;
-}

diff --git a/drivers/rtc/ds174x.c b/drivers/rtc/ds174x.c
deleted file mode 100644
index 94f943d..0000000
--- a/drivers/rtc/ds174x.c
+++ /dev/null

@@ -1,172 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2001
- * ARIO Data Networks, Inc. dchiu@ariodata.com
- *
- * Based on MontaVista DS1743 code and U-Boot mc146818 code
- */
-
-/*
- * Date & Time support for the DS174x RTC
- */
-
-/*#define	DEBUG*/
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-static uchar rtc_read( unsigned int addr );
-static void  rtc_write( unsigned int addr, uchar val);
-
-#define RTC_BASE		( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR )
-
-#define RTC_YEAR		( RTC_BASE + 7 )
-#define RTC_MONTH		( RTC_BASE + 6 )
-#define RTC_DAY_OF_MONTH	( RTC_BASE + 5 )
-#define RTC_DAY_OF_WEEK		( RTC_BASE + 4 )
-#define RTC_HOURS		( RTC_BASE + 3 )
-#define RTC_MINUTES		( RTC_BASE + 2 )
-#define RTC_SECONDS		( RTC_BASE + 1 )
-#define RTC_CENTURY		( RTC_BASE + 0 )
-
-#define RTC_CONTROLA		RTC_CENTURY
-#define RTC_CONTROLB		RTC_SECONDS
-#define RTC_CONTROLC		RTC_DAY_OF_WEEK
-
-#define RTC_CA_WRITE		0x80
-#define RTC_CA_READ		0x40
-
-#define RTC_CB_OSC_DISABLE	0x80
-
-#define RTC_CC_BATTERY_FLAG	0x80
-#define RTC_CC_FREQ_TEST	0x40
-
-/* ------------------------------------------------------------------------- */
-
-int rtc_get( struct rtc_time *tmp )
-{
-	uchar sec, min, hour;
-	uchar mday, wday, mon, year;
-
-	int century;
-
-	uchar reg_a;
-
-	reg_a = rtc_read( RTC_CONTROLA );
-	/* lock clock registers for read */
-	rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
-
-	sec     = rtc_read( RTC_SECONDS );
-	min     = rtc_read( RTC_MINUTES );
-	hour    = rtc_read( RTC_HOURS );
-	mday    = rtc_read( RTC_DAY_OF_MONTH );
-	wday    = rtc_read( RTC_DAY_OF_WEEK );
-	mon     = rtc_read( RTC_MONTH );
-	year    = rtc_read( RTC_YEAR );
-	century = rtc_read( RTC_CENTURY );
-
-	/* unlock clock registers after read */
-	rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
-
-#ifdef RTC_DEBUG
-	printf( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
-		"hr: %02x min: %02x sec: %02x\n",
-		year, mon_cent, mday, wday,
-		hour, min, sec );
-#endif
-	tmp->tm_sec  = bcd2bin( sec  & 0x7F );
-	tmp->tm_min  = bcd2bin( min  & 0x7F );
-	tmp->tm_hour = bcd2bin( hour & 0x3F );
-	tmp->tm_mday = bcd2bin( mday & 0x3F );
-	tmp->tm_mon  = bcd2bin( mon & 0x1F );
-	tmp->tm_wday = bcd2bin( wday & 0x07 );
-
-	/* glue year from century and year in century */
-	tmp->tm_year = bcd2bin( year ) +
-		( bcd2bin( century & 0x3F ) * 100 );
-
-	tmp->tm_yday = 0;
-	tmp->tm_isdst= 0;
-#ifdef RTC_DEBUG
-	printf( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
-#endif
-	return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
-	uchar reg_a;
-#ifdef RTC_DEBUG
-	printf( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
-	/* lock clock registers for write */
-	reg_a = rtc_read( RTC_CONTROLA );
-	rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
-
-	rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
-
-	rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
-	rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
-	rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
-	rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
-	rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
-
-	/* break year up into century and year in century */
-	rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
-	rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
-
-	/* unlock clock registers after read */
-	rtc_write( RTC_CONTROLA, ( reg_a  & ~RTC_CA_WRITE ));
-
-	return 0;
-}
-
-void rtc_reset (void)
-{
-	uchar reg_a, reg_b, reg_c;
-
-	reg_a = rtc_read( RTC_CONTROLA );
-	reg_b = rtc_read( RTC_CONTROLB );
-
-	if ( reg_b & RTC_CB_OSC_DISABLE )
-	{
-		printf( "real-time-clock was stopped. Now starting...\n" );
-		reg_a |= RTC_CA_WRITE;
-		reg_b &= ~RTC_CB_OSC_DISABLE;
-
-		rtc_write( RTC_CONTROLA, reg_a );
-		rtc_write( RTC_CONTROLB, reg_b );
-	}
-
-	/* make sure read/write clock register bits are cleared */
-	reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
-	rtc_write( RTC_CONTROLA, reg_a );
-
-	reg_c = rtc_read( RTC_CONTROLC );
-	if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
-		printf( "RTC battery low. Clock setting may not be reliable.\n" );
-}
-
-/* ------------------------------------------------------------------------- */
-
-static uchar rtc_read( unsigned int addr )
-{
-	uchar val = in8( addr );
-#ifdef RTC_DEBUG
-	printf( "rtc_read: %x:%x\n", addr, val );
-#endif
-	return( val );
-}
-
-static void rtc_write( unsigned int addr, uchar val )
-{
-#ifdef RTC_DEBUG
-	printf( "rtc_write: %x:%x\n", addr, val );
-#endif
-	out8( addr, val );
-}

diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c
index 5b72e86..bd32ed2 100644
--- a/drivers/rtc/ds3231.c
+++ b/drivers/rtc/ds3231.c

@@ -164,13 +164,13 @@
 static
 uchar rtc_read (uchar reg)
 {
-	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+	return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
 }
 
 
 static void rtc_write (uchar reg, uchar val)
 {
-	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+	i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
 }
 #else
 static int ds3231_rtc_get(struct udevice *dev, struct rtc_time *tmp)

diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c
index 8be532c..66a0faa 100644
--- a/drivers/rtc/m41t62.c
+++ b/drivers/rtc/m41t62.c

@@ -319,7 +319,7 @@
 {
 	u8 buf[M41T62_DATETIME_REG_SIZE];
 
-	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
+	i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
 	m41t62_update_rtc_time(tm, buf);
 
 	return 0;
@@ -329,10 +329,10 @@
 {
 	u8 buf[M41T62_DATETIME_REG_SIZE];
 
-	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
+	i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
 	m41t62_set_rtc_buf(tm, buf);
 
-	if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf,
+	if (i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf,
 		      M41T62_DATETIME_REG_SIZE)) {
 		printf("I2C write failed in %s()\n", __func__);
 		return -1;
@@ -349,8 +349,8 @@
 	 * M41T82: Make sure HT (Halt Update) bit is cleared.
 	 * This bit is 0 in M41T62 so its save to clear it always.
 	 */
-	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
+	i2c_read(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
 	val &= ~M41T80_ALHOUR_HT;
-	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
+	i2c_write(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
 }
 #endif /* CONFIG_DM_RTC */

diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c
index 1192883..e03a87f 100644
--- a/drivers/rtc/max6900.c
+++ b/drivers/rtc/max6900.c

@@ -16,20 +16,20 @@
 #include <i2c.h>
 #include <linux/delay.h>
 
-#ifndef	CONFIG_SYS_I2C_RTC_ADDR
-#define	CONFIG_SYS_I2C_RTC_ADDR	0x50
+#ifndef	CFG_SYS_I2C_RTC_ADDR
+#define	CFG_SYS_I2C_RTC_ADDR	0x50
 #endif
 
 /* ------------------------------------------------------------------------- */
 
 static uchar rtc_read (uchar reg)
 {
-	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+	return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
 }
 
 static void rtc_write (uchar reg, uchar val)
 {
-	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+	i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
 	udelay(2500);
 }
 

diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c
index 19faefb..91a4124 100644
--- a/drivers/rtc/pcf8563.c
+++ b/drivers/rtc/pcf8563.c

@@ -111,12 +111,12 @@
 
 static uchar rtc_read (uchar reg)
 {
-	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+	return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
 }
 
 static void rtc_write (uchar reg, uchar val)
 {
-	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+	i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
 }
 #else
 static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp)

diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c
index c987494..e0a7bd3 100644
--- a/drivers/rtc/pt7c4338.c
+++ b/drivers/rtc/pt7c4338.c

@@ -53,12 +53,12 @@
 /****** Helper functions ****************************************/
 static u8 rtc_read(u8 reg)
 {
-	return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg);
+	return i2c_reg_read(CFG_SYS_I2C_RTC_ADDR, reg);
 }
 
 static void rtc_write(u8 reg, u8 val)
 {
-	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+	i2c_reg_write(CFG_SYS_I2C_RTC_ADDR, reg, val);
 }
 /****************************************************************/
 

diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c
index 97ec001..6b1c23c 100644
--- a/drivers/rtc/rs5c372.c
+++ b/drivers/rtc/rs5c372.c

@@ -39,8 +39,8 @@
 #define rtc_debug 0	/* gcc will remove all the debug code for us */
 #endif
 
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#ifndef CFG_SYS_I2C_RTC_ADDR
+#define CFG_SYS_I2C_RTC_ADDR 0x32
 #endif
 
 #define RS5C372_RAM_SIZE 0x10
@@ -63,7 +63,7 @@
 {
 	int ret;
 
-	ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len);
+	ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len);
 	if (ret != 0) {
 		printf("%s: failed to read\n", __FUNCTION__);
 		return ret;
@@ -103,7 +103,7 @@
 	buf[14] = 0; /* reg. 13 */
 	buf[15] = 0; /* reg. 14 */
 	buf[16] = USE_24HOUR_MODE; /* reg. 15 */
-	ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1);
+	ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1);
 	if (ret != 0) {
 		printf("%s: failed\n", __FUNCTION__);
 		return;
@@ -204,7 +204,7 @@
 	memset(buf, 0, sizeof(buf));
 
 	/* only read register 15 */
-	ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1);
+	ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1);
 
 	if (ret == 0) {
 		/* need to save register 15 */
@@ -233,7 +233,7 @@
 			printf("WARNING: year should be between 1970 and 2069!\n");
 		buf[7] = bin2bcd(tmp->tm_year % 100);
 
-		ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8);
+		ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8);
 		if (ret != 0) {
 			printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret);
 			return -1;

diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c
index d513561..bf93b55 100644
--- a/drivers/rtc/rx8010sj.c
+++ b/drivers/rtc/rx8010sj.c

@@ -33,8 +33,8 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR	0x32
+#ifndef CFG_SYS_I2C_RTC_ADDR
+# define CFG_SYS_I2C_RTC_ADDR	0x32
 #endif
 
 /*
@@ -313,7 +313,7 @@
 int rtc_get(struct rtc_time *tm)
 {
 	struct ludevice dev = {
-			.chip = CONFIG_SYS_I2C_RTC_ADDR,
+			.chip = CFG_SYS_I2C_RTC_ADDR,
 	};
 
 	return rx8010sj_rtc_get(&dev, tm);
@@ -322,7 +322,7 @@
 int rtc_set(struct rtc_time *tm)
 {
 	struct ludevice dev = {
-			.chip = CONFIG_SYS_I2C_RTC_ADDR,
+			.chip = CFG_SYS_I2C_RTC_ADDR,
 	};
 
 	return rx8010sj_rtc_set(&dev, tm);
@@ -331,7 +331,7 @@
 void rtc_reset(void)
 {
 	struct ludevice dev = {
-			.chip = CONFIG_SYS_I2C_RTC_ADDR,
+			.chip = CFG_SYS_I2C_RTC_ADDR,
 	};
 
 	rx8010sj_rtc_reset(&dev);
@@ -340,7 +340,7 @@
 void rtc_init(void)
 {
 	struct ludevice dev = {
-			.chip = CONFIG_SYS_I2C_RTC_ADDR,
+			.chip = CFG_SYS_I2C_RTC_ADDR,
 	};
 
 	rx8010sj_rtc_init(&dev);

diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c
index ce23427..4a8d1c5 100644
--- a/drivers/rtc/x1205.c
+++ b/drivers/rtc/x1205.c

@@ -77,7 +77,7 @@
 
 static void rtc_write(int reg, u8 val)
 {
-	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
+	i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
 }
 
 /*
@@ -89,7 +89,7 @@
 {
 	u8 buf[8];
 
-	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
+	i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
 
 	debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
 	      "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index de02e08..14b0feb 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig

@@ -720,37 +720,75 @@
 	help
 	  Support for the UART found on Microchip PIC32 SoC's.
 
+config SYS_NS16550_SERIAL
+	bool "NS16550 UART or compatible legacy driver"
+	depends on !DM_SERIAL
+	select SYS_NS16550
+
+config SPL_SYS_NS16550_SERIAL
+	bool "NS16550 UART or compatible legacy driver in SPL"
+	depends on SPL && !SPL_DM_SERIAL
+	default y if SYS_NS16550_SERIAL || ARCH_SUNXI || ARCH_OMAP2PLUS
+	select SYS_NS16550
+
 config SYS_NS16550
 	bool "NS16550 UART or compatible"
 	help
 	  Support NS16550 UART or compatible. This can be enabled in the
 	  device tree with the correct input clock frequency. If the input
 	  clock frequency is not defined in the device tree, the macro
-	  CONFIG_SYS_NS16550_CLK defined in a legacy board header file will
+	  CFG_SYS_NS16550_CLK defined in a legacy board header file will
 	  be used. It can be a constant or a function to get clock, eg,
 	  get_serial_clock().
 
 config NS16550_DYNAMIC
 	bool "Allow NS16550 to be configured at runtime"
+	depends on SYS_NS16550
 	default y if SYS_COREBOOT || SYS_SLIMBOOTLOADER
 	help
 	  Enable this option to allow device-tree control of the driver.
 
 	  Normally this driver is controlled by the following options:
 
-	  CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for
-	     access. If not enabled, then the UART is memory-mapped.
-	  CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit
-	     access should be used (instead of 8-bit)
-	  CONFIG_SYS_NS16550_REG_SIZE - indicates register width and also
-	     endianness. If positive, big-endian access is used. If negative,
-	     little-endian is used.
-
 	  It is not a good practice for a driver to be statically configured,
 	  since it prevents the same driver being used for different types of
 	  UARTs in a system. This option avoids this problem at the cost of a
 	  slightly increased code size.
 
+config SYS_NS16550_MEM32
+	bool "If memory-mapped, 32bit access is needed for ns16550 register access"
+	depends on SYS_NS16550
+	help
+	  If enabled, if memory-mapped, indicates that 32-bit access should be
+	  used (instead of 8-bit) for register access.
+
+config SYS_NS16550_PORT_MAPPED
+	bool "Port I/O is used for ns16550 register access"
+	depends on SYS_NS16550
+	help
+	  If enabled, port I/O is used for ns16550 register access. If not
+	  enabled, then the UART is memory-mapped.
+
+config SYS_NS16550_REG_SIZE
+	int "ns16550 register width and endianness"
+	depends on SYS_NS16550_SERIAL || SPL_SYS_NS16550_SERIAL
+	range -4 4
+	default -4 if ARCH_OMAP2PLUS || ARCH_SUNXI
+	default 1
+	help
+	  Indicates register width and also endianness. If positive, big-endian
+	  access is used. If negative, little-endian is used.
+
+config SPL_NS16550_MIN_FUNCTIONS
+	bool "Only provide NS16550_init and NS16550_putc in SPL"
+	depends on SPL_SYS_NS16550_SERIAL && PPC
+	help
+	  Enable this if you desire to only have use of the NS16550_init and
+	  NS16550_putc functions for the serial driver located at
+	  drivers/serial/ns16550.c.  This option is useful for saving space for
+	  already greatly restricted images, including but not limited to
+	  NAND_SPL configurations.
+
 config INTEL_MID_SERIAL
 	bool "Intel MID platform UART support"
 	depends on DM_SERIAL && OF_CONTROL

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index eb7b8f2..33fa568 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile

@@ -25,7 +25,7 @@
 obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
 else
 obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
-obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
+obj-$(CONFIG_$(SPL_)SYS_NS16550_SERIAL) += serial_ns16550.o
 endif
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
@@ -38,7 +38,6 @@
 obj-$(CONFIG_CORTINA_UART) += serial_cortina.o
 obj-$(CONFIG_DEBUG_SBI_CONSOLE) += serial_sbi.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
-obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += serial_mcf.o
 obj-$(CONFIG_SYS_NS16550) += ns16550.o
 obj-$(CONFIG_S5P_SERIAL) += serial_s5p.o

diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c
deleted file mode 100644
index d39a3c0..0000000
--- a/drivers/serial/lpc32xx_hsuart.c
+++ /dev/null

@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <dm.h>
-#include <serial.h>
-#include <dm/platform_data/lpc32xx_hsuart.h>
-
-#include <asm/arch/uart.h>
-#include <linux/compiler.h>
-
-struct lpc32xx_hsuart_priv {
-	struct hsuart_regs *hsuart;
-};
-
-static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate)
-{
-	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
-	struct hsuart_regs *hsuart = priv->hsuart;
-	u32 div;
-
-	/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
-	div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1;
-	if (div > 255)
-		div = 255;
-
-	writel(div, &hsuart->rate);
-
-	return 0;
-}
-
-static int lpc32xx_serial_getc(struct udevice *dev)
-{
-	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
-	struct hsuart_regs *hsuart = priv->hsuart;
-
-	if (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
-		return -EAGAIN;
-
-	return readl(&hsuart->rx) & HSUART_RX_DATA;
-}
-
-static int lpc32xx_serial_putc(struct udevice *dev, const char c)
-{
-	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
-	struct hsuart_regs *hsuart = priv->hsuart;
-
-	/* Wait for empty FIFO */
-	if (readl(&hsuart->level) & HSUART_LEVEL_TX)
-		return -EAGAIN;
-
-	writel(c, &hsuart->tx);
-
-	return 0;
-}
-
-static int lpc32xx_serial_pending(struct udevice *dev, bool input)
-{
-	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
-	struct hsuart_regs *hsuart = priv->hsuart;
-
-	if (input) {
-		if (readl(&hsuart->level) & HSUART_LEVEL_RX)
-			return 1;
-	} else {
-		if (readl(&hsuart->level) & HSUART_LEVEL_TX)
-			return 1;
-	}
-
-	return 0;
-}
-
-static int lpc32xx_serial_init(struct hsuart_regs *hsuart)
-{
-	/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
-	writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
-	       HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
-	       &hsuart->ctrl);
-
-	return 0;
-}
-
-static int lpc32xx_hsuart_probe(struct udevice *dev)
-{
-	struct lpc32xx_hsuart_plat *plat = dev_get_plat(dev);
-	struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
-
-	priv->hsuart = (struct hsuart_regs *)plat->base;
-
-	lpc32xx_serial_init(priv->hsuart);
-
-	return 0;
-}
-
-static const struct dm_serial_ops lpc32xx_hsuart_ops = {
-	.setbrg	= lpc32xx_serial_setbrg,
-	.getc	= lpc32xx_serial_getc,
-	.putc	= lpc32xx_serial_putc,
-	.pending = lpc32xx_serial_pending,
-};
-
-U_BOOT_DRIVER(lpc32xx_hsuart) = {
-	.name	= "lpc32xx_hsuart",
-	.id	= UCLASS_SERIAL,
-	.probe	= lpc32xx_hsuart_probe,
-	.ops	= &lpc32xx_hsuart_ops,
-	.priv_auto	= sizeof(struct lpc32xx_hsuart_priv),
-	.flags	= DM_FLAG_PRE_RELOC,
-};

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 7592979..772dd6f 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c

@@ -92,8 +92,8 @@
 
 #if CONFIG_IS_ENABLED(DM_SERIAL)
 
-#ifndef CONFIG_SYS_NS16550_CLK
-#define CONFIG_SYS_NS16550_CLK  0
+#ifndef CFG_SYS_NS16550_CLK
+#define CFG_SYS_NS16550_CLK  0
 #endif
 
 /*
@@ -272,7 +272,7 @@
 #endif
 }
 
-#ifndef CONFIG_NS16550_MIN_FUNCTIONS
+#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
 void ns16550_reinit(struct ns16550 *com_port, int baud_divisor)
 {
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
@@ -281,7 +281,7 @@
 	serial_out(ns16550_getfcr(com_port), &com_port->fcr);
 	ns16550_setbrg(com_port, baud_divisor);
 }
-#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
+#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
 
 void ns16550_putc(struct ns16550 *com_port, char c)
 {
@@ -299,7 +299,7 @@
 		schedule();
 }
 
-#ifndef CONFIG_NS16550_MIN_FUNCTIONS
+#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
 char ns16550_getc(struct ns16550 *com_port)
 {
 	while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
@@ -317,7 +317,7 @@
 	return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
 }
 
-#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
+#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
 
 #ifdef CONFIG_DEBUG_UART_NS16550
 
@@ -567,9 +567,9 @@
 
 	if (!plat->clock)
 		plat->clock = dev_read_u32_default(dev, "clock-frequency",
-						   CONFIG_SYS_NS16550_CLK);
+						   CFG_SYS_NS16550_CLK);
 	if (!plat->clock)
-		plat->clock = CONFIG_SYS_NS16550_CLK;
+		plat->clock = CFG_SYS_NS16550_CLK;
 	if (!plat->clock) {
 		debug("ns16550 clock not defined\n");
 		return -EINVAL;

diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 83cda1f..c021067 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c

@@ -25,7 +25,7 @@
 /*
  * Table with supported baudrates (defined in config_xyz.h)
  */
-static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
 
 #if CONFIG_IS_ENABLED(SERIAL_PRESENT)
 static int serial_check_stdout(const void *blob, struct udevice **devp)
@@ -526,7 +526,7 @@
 		ops->getconfig += gd->reloc_off;
 	if (ops->setconfig)
 		ops->setconfig += gd->reloc_off;
-#if CONFIG_POST & CONFIG_SYS_POST_UART
+#if CFG_POST & CONFIG_SYS_POST_UART
 	if (ops->loop)
 		ops->loop += gd->reloc_off;
 #endif

diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 6cdbb89..369a8e3 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c

@@ -22,7 +22,7 @@
 /*
  * Table with supported baudrates (defined in config_xyz.h)
  */
-static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
 
 /**
  * serial_null() - Void registration routine of a serial driver
@@ -458,8 +458,8 @@
 		dev->putc(*s++);
 }
 
-#if CONFIG_POST & CONFIG_SYS_POST_UART
-static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE;
+#if CFG_POST & CONFIG_SYS_POST_UART
+static const int bauds[] = CFG_SYS_BAUDRATE_TABLE;
 
 /**
  * uart_post_test() - Test the currently selected serial port using POST

diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index 03b9e86..6fb4cb6 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c

@@ -284,8 +284,8 @@
 
 #define DECLARE_HSUART_PRIV(port) \
 	static struct mtk_serial_priv mtk_hsuart##port = { \
-	.regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
-	.fixed_clk_rate = CONFIG_SYS_NS16550_CLK \
+	.regs = (struct mtk_serial_regs *)CFG_SYS_NS16550_COM##port, \
+	.fixed_clk_rate = CFG_SYS_NS16550_CLK \
 };
 
 #define DECLARE_HSUART_FUNCTIONS(port) \
@@ -356,36 +356,36 @@
 #error	"Invalid console index value."
 #endif
 
-#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
+#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1)
 #error	"Console port 1 defined but not configured."
-#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
+#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2)
 #error	"Console port 2 defined but not configured."
-#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
+#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3)
 #error	"Console port 3 defined but not configured."
-#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
+#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4)
 #error	"Console port 4 defined but not configured."
-#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
+#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5)
 #error	"Console port 5 defined but not configured."
-#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
+#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6)
 #error	"Console port 6 defined but not configured."
 #endif
 
-#if defined(CONFIG_SYS_NS16550_COM1)
+#if defined(CFG_SYS_NS16550_COM1)
 DECLARE_HSUART(1, "mtk-hsuart0");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM2)
+#if defined(CFG_SYS_NS16550_COM2)
 DECLARE_HSUART(2, "mtk-hsuart1");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM3)
+#if defined(CFG_SYS_NS16550_COM3)
 DECLARE_HSUART(3, "mtk-hsuart2");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM4)
+#if defined(CFG_SYS_NS16550_COM4)
 DECLARE_HSUART(4, "mtk-hsuart3");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM5)
+#if defined(CFG_SYS_NS16550_COM5)
 DECLARE_HSUART(5, "mtk-hsuart4");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM6)
+#if defined(CFG_SYS_NS16550_COM6)
 DECLARE_HSUART(6, "mtk-hsuart5");
 #endif
 
@@ -410,22 +410,22 @@
 
 void mtk_serial_initialize(void)
 {
-#if defined(CONFIG_SYS_NS16550_COM1)
+#if defined(CFG_SYS_NS16550_COM1)
 	serial_register(&mtk_hsuart1_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM2)
+#if defined(CFG_SYS_NS16550_COM2)
 	serial_register(&mtk_hsuart2_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM3)
+#if defined(CFG_SYS_NS16550_COM3)
 	serial_register(&mtk_hsuart3_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM4)
+#if defined(CFG_SYS_NS16550_COM4)
 	serial_register(&mtk_hsuart4_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM5)
+#if defined(CFG_SYS_NS16550_COM5)
 	serial_register(&mtk_hsuart5_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM6)
+#if defined(CFG_SYS_NS16550_COM6)
 	serial_register(&mtk_hsuart6_device);
 #endif
 }

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 97b6a4f..4014f68 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c

@@ -11,7 +11,7 @@
 #include <asm/global_data.h>
 #include <linux/compiler.h>
 
-#ifndef CONFIG_NS16550_MIN_FUNCTIONS
+#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -20,17 +20,17 @@
 #error	"Invalid console index value."
 #endif
 
-#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
+#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1)
 #error	"Console port 1 defined but not configured."
-#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
+#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2)
 #error	"Console port 2 defined but not configured."
-#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
+#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3)
 #error	"Console port 3 defined but not configured."
-#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
+#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4)
 #error	"Console port 4 defined but not configured."
-#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
+#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5)
 #error	"Console port 5 defined but not configured."
-#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
+#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6)
 #error	"Console port 6 defined but not configured."
 #endif
 
@@ -38,33 +38,33 @@
  *	 the array is 0 based.
  */
 static struct ns16550 *serial_ports[6] = {
-#ifdef CONFIG_SYS_NS16550_COM1
-	(struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+#ifdef CFG_SYS_NS16550_COM1
+	(struct ns16550 *)CFG_SYS_NS16550_COM1,
 #else
 	NULL,
 #endif
-#ifdef CONFIG_SYS_NS16550_COM2
-	(struct ns16550 *)CONFIG_SYS_NS16550_COM2,
+#ifdef CFG_SYS_NS16550_COM2
+	(struct ns16550 *)CFG_SYS_NS16550_COM2,
 #else
 	NULL,
 #endif
-#ifdef CONFIG_SYS_NS16550_COM3
-	(struct ns16550 *)CONFIG_SYS_NS16550_COM3,
+#ifdef CFG_SYS_NS16550_COM3
+	(struct ns16550 *)CFG_SYS_NS16550_COM3,
 #else
 	NULL,
 #endif
-#ifdef CONFIG_SYS_NS16550_COM4
-	(struct ns16550 *)CONFIG_SYS_NS16550_COM4,
+#ifdef CFG_SYS_NS16550_COM4
+	(struct ns16550 *)CFG_SYS_NS16550_COM4,
 #else
 	NULL,
 #endif
-#ifdef CONFIG_SYS_NS16550_COM5
-	(struct ns16550 *)CONFIG_SYS_NS16550_COM5,
+#ifdef CFG_SYS_NS16550_COM5
+	(struct ns16550 *)CFG_SYS_NS16550_COM5,
 #else
 	NULL,
 #endif
-#ifdef CONFIG_SYS_NS16550_COM6
-	(struct ns16550 *)CONFIG_SYS_NS16550_COM6
+#ifdef CFG_SYS_NS16550_COM6
+	(struct ns16550 *)CFG_SYS_NS16550_COM6
 #else
 	NULL
 #endif
@@ -78,7 +78,7 @@
 	{ \
 		int clock_divisor; \
 		clock_divisor = ns16550_calc_divisor(serial_ports[port-1], \
-				CONFIG_SYS_NS16550_CLK, gd->baudrate); \
+				CFG_SYS_NS16550_CLK, gd->baudrate); \
 		ns16550_init(serial_ports[port - 1], clock_divisor); \
 		return 0 ; \
 	} \
@@ -144,7 +144,7 @@
 {
 	int clock_divisor;
 
-	clock_divisor = ns16550_calc_divisor(PORT, CONFIG_SYS_NS16550_CLK,
+	clock_divisor = ns16550_calc_divisor(PORT, CFG_SYS_NS16550_CLK,
 					     gd->baudrate);
 	ns16550_reinit(PORT, clock_divisor);
 }
@@ -179,32 +179,32 @@
 	_serial_setbrg(dev_index);
 }
 
-#if defined(CONFIG_SYS_NS16550_COM1)
+#if defined(CFG_SYS_NS16550_COM1)
 DECLARE_ESERIAL_FUNCTIONS(1);
 struct serial_device eserial1_device =
 	INIT_ESERIAL_STRUCTURE(1, "eserial0");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM2)
+#if defined(CFG_SYS_NS16550_COM2)
 DECLARE_ESERIAL_FUNCTIONS(2);
 struct serial_device eserial2_device =
 	INIT_ESERIAL_STRUCTURE(2, "eserial1");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM3)
+#if defined(CFG_SYS_NS16550_COM3)
 DECLARE_ESERIAL_FUNCTIONS(3);
 struct serial_device eserial3_device =
 	INIT_ESERIAL_STRUCTURE(3, "eserial2");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM4)
+#if defined(CFG_SYS_NS16550_COM4)
 DECLARE_ESERIAL_FUNCTIONS(4);
 struct serial_device eserial4_device =
 	INIT_ESERIAL_STRUCTURE(4, "eserial3");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM5)
+#if defined(CFG_SYS_NS16550_COM5)
 DECLARE_ESERIAL_FUNCTIONS(5);
 struct serial_device eserial5_device =
 	INIT_ESERIAL_STRUCTURE(5, "eserial4");
 #endif
-#if defined(CONFIG_SYS_NS16550_COM6)
+#if defined(CFG_SYS_NS16550_COM6)
 DECLARE_ESERIAL_FUNCTIONS(6);
 struct serial_device eserial6_device =
 	INIT_ESERIAL_STRUCTURE(6, "eserial5");
@@ -231,24 +231,24 @@
 
 void ns16550_serial_initialize(void)
 {
-#if defined(CONFIG_SYS_NS16550_COM1)
+#if defined(CFG_SYS_NS16550_COM1)
 	serial_register(&eserial1_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM2)
+#if defined(CFG_SYS_NS16550_COM2)
 	serial_register(&eserial2_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM3)
+#if defined(CFG_SYS_NS16550_COM3)
 	serial_register(&eserial3_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM4)
+#if defined(CFG_SYS_NS16550_COM4)
 	serial_register(&eserial4_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM5)
+#if defined(CFG_SYS_NS16550_COM5)
 	serial_register(&eserial5_device);
 #endif
-#if defined(CONFIG_SYS_NS16550_COM6)
+#if defined(CFG_SYS_NS16550_COM6)
 	serial_register(&eserial6_device);
 #endif
 }
 
-#endif /* !CONFIG_NS16550_MIN_FUNCTIONS */
+#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */

diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index e9ff61a..904f7d2 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c

@@ -15,8 +15,8 @@
 #include <clk.h>
 #include <linux/err.h>
 
-#ifndef CONFIG_SYS_NS16550_CLK
-#define CONFIG_SYS_NS16550_CLK  0
+#ifndef CFG_SYS_NS16550_CLK
+#define CFG_SYS_NS16550_CLK  0
 #endif
 
 #ifdef CONFIG_DEBUG_UART_OMAP
@@ -128,7 +128,7 @@
 
 	if (!plat->clock)
 		plat->clock = dev_read_u32_default(dev, "clock-frequency",
-						   CONFIG_SYS_NS16550_CLK);
+						   CFG_SYS_NS16550_CLK);
 	if (!plat->clock) {
 		debug("omap serial clock not defined\n");
 		return -EINVAL;

diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 0ee6171..9ebc4ed 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c

@@ -225,7 +225,7 @@
 		SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
 
 	/* setup format */
-	scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
+	scalar = ((CFG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
 
 	/*
 	 * Use following format:
@@ -314,7 +314,7 @@
 	struct davinci_spi_slave *ds = dev_get_priv(bus);
 
 	debug("%s speed %u\n", __func__, max_hz);
-	if (max_hz > CONFIG_SYS_SPI_CLK / 2)
+	if (max_hz > CFG_SYS_SPI_CLK / 2)
 		return -EINVAL;
 
 	ds->freq = max_hz;

diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index bc5da0a..2bb7390 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c

@@ -131,7 +131,7 @@
 	 * follows:
 	 * SPI actual frequency = core_clk / (SPR * (2 ^ SPPR))
 	 */
-	divider = DIV_ROUND_UP(CONFIG_SYS_TCLK, hz);
+	divider = DIV_ROUND_UP(CFG_SYS_TCLK, hz);
 	if (divider < 16) {
 		/* This is the easy case, divider is less than 16 */
 		spr = divider;
@@ -205,7 +205,7 @@
 	data = readl(&reg->timing1);
 	data &= ~KW_SPI_TMISO_SAMPLE_MASK;
 
-	if (CONFIG_SYS_TCLK == 250000000 &&
+	if (CFG_SYS_TCLK == 250000000 &&
 	    mode & SPI_CPOL &&
 	    mode & SPI_CPHA)
 		data |= KW_SPI_TMISO_SAMPLE_2;

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 5adfdf8..ea9cc3d 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c

@@ -91,14 +91,6 @@
 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
 #endif
 
-#ifdef CONFIG_MX27
-/* i.MX27 has a completely wrong register layout and register definitions in the
- * datasheet, the correct one is in the Freescale's Linux driver */
-
-#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
-"See linux mxc_spi driver from Freescale for details."
-#endif
-
 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
 {
 	return -1;

diff --git a/drivers/sysreset/sysreset_xtfpga.c b/drivers/sysreset/sysreset_xtfpga.c
index ad1781e..84fbc79 100644
--- a/drivers/sysreset/sysreset_xtfpga.c
+++ b/drivers/sysreset/sysreset_xtfpga.c

@@ -15,8 +15,8 @@
 {
 	switch (type) {
 	case SYSRESET_COLD:
-		writel(CONFIG_SYS_FPGAREG_RESET_CODE,
-		       CONFIG_SYS_FPGAREG_RESET);
+		writel(CFG_SYS_FPGAREG_RESET_CODE,
+		       CFG_SYS_FPGAREG_RESET);
 		break;
 	default:
 		return -EPROTONOSUPPORT;

diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c
index 065f10b..2e50d9f 100644
--- a/drivers/timer/arm_global_timer.c
+++ b/drivers/timer/arm_global_timer.c

@@ -59,7 +59,7 @@
 			return ret;
 		uc_priv->clock_rate = ret;
 	} else {
-		uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+		uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
 	}
 
 	/* init timer */

diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c
index 72be297..9c3b64a 100644
--- a/drivers/timer/imx-gpt-timer.c
+++ b/drivers/timer/imx-gpt-timer.c

@@ -28,9 +28,9 @@
 #define GPT_CLKSRC_IPG_CLK		(1 << 6)
 #define GPT_CLKSRC_IPG_CLK_24M		(5 << 6)
 
-/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
-#ifndef CONFIG_SYS_HZ_CLOCK
-#define CONFIG_SYS_HZ_CLOCK		3000000
+/* If CFG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
+#ifndef CFG_SYS_HZ_CLOCK
+#define CFG_SYS_HZ_CLOCK		3000000
 #endif
 
 struct imx_gpt_timer_regs {
@@ -60,7 +60,7 @@
 
 static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
 {
-	u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+	u32 prescaler = (rate / CFG_SYS_HZ_CLOCK) - 1;
 
 	/* Reset the timer */
 	setbits_le32(&regs->cr, GPT_CR_SWR);
@@ -138,7 +138,7 @@
 		return ret;
 	}
 
-	uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+	uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
 
 	return 0;
 }

diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c
index d0eab3c..d588f0c 100644
--- a/drivers/timer/orion-timer.c
+++ b/drivers/timer/orion-timer.c

@@ -72,7 +72,7 @@
 	if (IS_ENABLED(CONFIG_ARCH_MVEBU))
 		return MVEBU_TIMER_FIXED_RATE_25MHZ;
 	else
-		return CONFIG_SYS_TCLK;
+		return CFG_SYS_TCLK;
 }
 
 /**
@@ -117,7 +117,7 @@
 	if (type == INPUT_CLOCK_25MHZ)
 		uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ;
 	else
-		uc_priv->clock_rate = CONFIG_SYS_TCLK;
+		uc_priv->clock_rate = CFG_SYS_TCLK;
 	orion_timer_init(priv->base, type);
 
 	return 0;

diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c
index f07251e..1213a14 100644
--- a/drivers/timer/stm32_timer.c
+++ b/drivers/timer/stm32_timer.c

@@ -97,11 +97,11 @@
 	rate = clk_get_rate(&clk);
 
 	/* we set timer prescaler to obtain a 1MHz timer counter frequency */
-	psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+	psc = (rate / CFG_SYS_HZ_CLOCK) - 1;
 	writel(psc, &regs->psc);
 
 	/* Set timer frequency to 1MHz */
-	uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+	uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
 
 	/* Configure timer for auto-reload */
 	setbits_le32(&regs->cr1, CR1_ARPE);

diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index e8da73c..e120efe 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig

@@ -82,6 +82,10 @@
 	help
 	  Enable the Broadcom UDC OTG physical device interface.
 
+config USB_GADGET_AT91
+	bool "Atmel AT91 USB Gadget Controller"
+	depends on ARCH_AT91
+
 config USB_GADGET_DWC2_OTG
 	bool "DesignWare USB2.0 HS OTG controller (gadget mode)"
 	select USB_GADGET_DUALSPEED

diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c
index 130b73d..60525f2 100644
--- a/drivers/usb/host/ehci-rmobile.c
+++ b/drivers/usb/host/ehci-rmobile.c

@@ -90,7 +90,7 @@
 
 	/* AHB-PCI Bridge Communication Registers */
 	writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
-	writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
+	writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
 	       &ahbcom_pci->pciahb_win1_ctr);
 	writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
 	       &ahbcom_pci->pciahb_win2_ctr);
@@ -103,7 +103,7 @@
 	writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
 	       &ahbcom_pci->ahbpci_win1_ctr);
 	writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
-	writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
+	writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
 	writel(0xf0000000, &ahbconf_pci->win2_basead);
 	writel(SERREN | PERREN | MASTEREN | MEMEN,
 	       &ahbconf_pci->cmnd_sts);

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 9acef5e..3f44181 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c

@@ -1993,7 +1993,7 @@
 	gohci.disabled = 1;
 	gohci.sleeping = 0;
 	gohci.irq = -1;
-	gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
+	gohci.regs = (struct ohci_regs *)CFG_SYS_USB_OHCI_REGS_BASE;
 
 	gohci.flags = 0;
 	gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index c841b99..f539977 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig

@@ -622,7 +622,7 @@
 
 config VIDEO_SANDBOX_SDL
 	bool "Enable sandbox video console using SDL"
-	depends on SANDBOX
+	depends on SANDBOX_SDL
 	help
 	  When using sandbox you can enable an emulated LCD display which
 	  appears as an SDL (Simple DirectMedia Layer) window. This is a

diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig
index afe950b..34e8b64 100644
--- a/drivers/video/imx/Kconfig
+++ b/drivers/video/imx/Kconfig

@@ -6,3 +6,10 @@
 	  This enables framebuffer driver for i.MX processors working
 	  on the IPUv3(Image Processing Unit) internal graphic processor.
 
+config IMX_VIDEO_SKIP
+	bool "Enable calling board_video_skip function"
+	depends on VIDEO_IPUV3
+
+config IMX_HDMI
+	bool "Enable HDMI support in IPUv3"
+	depends on VIDEO_IPUV3

diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c
index 54d1efc..b0a99c9 100644
--- a/drivers/video/imx/ipu_common.c
+++ b/drivers/video/imx/ipu_common.c

@@ -221,13 +221,13 @@
 	.usecount = 0,
 };
 
-#if !defined CONFIG_SYS_LDB_CLOCK
-#define CONFIG_SYS_LDB_CLOCK 65000000
+#if !defined CFG_SYS_LDB_CLOCK
+#define CFG_SYS_LDB_CLOCK 65000000
 #endif
 
 static struct clk ldb_clk = {
 	.name = "ldb_clk",
-	.rate = CONFIG_SYS_LDB_CLOCK,
+	.rate = CFG_SYS_LDB_CLOCK,
 	.usecount = 0,
 };
 

diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
index 2ee6212..9110a48 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c

@@ -385,7 +385,7 @@
 		(struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
 
 	setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS);
-	writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
+	writel(CFG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
 	writel(mode->xres * 4, &de_fe->ch0_stride);
 	writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt);
 	writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt);
@@ -1222,7 +1222,7 @@
 			   EFI_RESERVED_MEMORY_TYPE);
 #endif
 
-	fb_dma_addr = sunxi_display->fb_addr - CONFIG_SYS_SDRAM_BASE;
+	fb_dma_addr = sunxi_display->fb_addr - CFG_SYS_SDRAM_BASE;
 	if (overscan_offset) {
 		fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
 		sunxi_display->fb_addr += ALIGN(overscan_offset, 0x1000);

diff --git a/env/Kconfig b/env/Kconfig
index 24111df..4e506ae 100644
--- a/env/Kconfig
+++ b/env/Kconfig

@@ -140,7 +140,7 @@
 	   type flash chips the second sector can be used: the offset
 	   for this sector is given here.
 
-	   CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
+	   CONFIG_ENV_OFFSET is used relative to CFG_SYS_FLASH_BASE.
 
 	  CONFIG_ENV_ADDR:
 

diff --git a/env/embedded.c b/env/embedded.c
index 9f26e6c..27fb45b 100644
--- a/env/embedded.c
+++ b/env/embedded.c

@@ -92,6 +92,6 @@
 /*
  * Add in absolutes.
  */
-GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE));
+GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE));
 
 #endif /* ENV_IS_EMBEDDED */

diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index 17c76bc..d60f494 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h

@@ -17,8 +17,8 @@
 #endif
 #endif
 
-#ifndef CONFIG_SYS_BAUDRATE_TABLE
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#ifndef CFG_SYS_BAUDRATE_TABLE
+#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 #endif
 
 #endif	/* __CONFIG_FALLBACKS_H */

diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index afd7cc8..3a4fbc6 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h

@@ -15,7 +15,6 @@
 /*
  * SERIAL
  */
-#define CONFIG_SYS_NS16550_MEM32
 
 /*
  * Flash
@@ -31,8 +30,8 @@
  * -The heap is placed below the monitor
  * -The stack is placed below the heap (&grows down).
  */
-#define CONFIG_SYS_SDRAM_BASE		0xc8000000
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CFG_SYS_SDRAM_BASE		0xc8000000
+#define CFG_SYS_SDRAM_SIZE		0x08000000
 #define CONFIG_MONITOR_IS_IN_RAM
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index ad7bd13..ab88918 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h

@@ -26,8 +26,8 @@
  * -The heap is placed below the monitor
  * -The stack is placed below the heap (&grows down).
  */
-#define CONFIG_SYS_SDRAM_BASE		0xD0000000
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CFG_SYS_SDRAM_BASE		0xD0000000
+#define CFG_SYS_SDRAM_SIZE		0x08000000
 #define CONFIG_MONITOR_IS_IN_RAM
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 25c3f22..b360238 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h

@@ -13,9 +13,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_SYS_UART_PORT		(0)
-
-#define CONFIG_WATCHDOG_TIMEOUT		5000
+#define CFG_SYS_UART_PORT		(0)
 
 /* I2C */
 
@@ -41,11 +39,11 @@
 
 #define CONFIG_PRAM		512	/* 512 KB */
 
-#define CONFIG_SYS_CLK		166666666	/* CPU Core Clock */
-#define CONFIG_SYS_PLL_ODR	0x36
-#define CONFIG_SYS_PLL_FDR	0x7D
+#define CFG_SYS_CLK		166666666	/* CPU Core Clock */
+#define CFG_SYS_PLL_ODR	0x36
+#define CFG_SYS_PLL_FDR	0x7D
 
-#define CONFIG_SYS_MBAR		0xFC000000
+#define CFG_SYS_MBAR		0xFC000000
 
 /*
  * Low Level Configuration Settings
@@ -53,36 +51,36 @@
  * You should know what you are doing if you make changes here.
  */
 /* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CFG_SYS_INIT_RAM_ADDR	0x80000000
+#define CFG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL	0x221
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1		0x43711630
-#define CONFIG_SYS_SDRAM_CFG2		0x56670000
-#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
-#define CONFIG_SYS_SDRAM_EMOD		0x80010000
-#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1		0x43711630
+#define CFG_SYS_SDRAM_CFG2		0x56670000
+#define CFG_SYS_SDRAM_CTRL		0xE1002000
+#define CFG_SYS_SDRAM_EMOD		0x80010000
+#define CFG_SYS_SDRAM_MODE		0x00CD0000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
 #ifdef CONFIG_SYS_FLASH_CFI
-#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CFG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
 #endif
 
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE
 
 /*
  * Configuration for environment
@@ -95,15 +93,15 @@
 
 /* Cache Configuration */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
 					 CF_CACR_DISD | CF_CACR_INVI | \
 					 CF_CACR_CEIB | CF_CACR_DCM | \
 					 CF_CACR_EUSP)
@@ -117,8 +115,8 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CONFIG_SYS_CS0_BASE		0
-#define CONFIG_SYS_CS0_MASK		0x007F0001
-#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#define CFG_SYS_CS0_BASE		0
+#define CFG_SYS_CS0_MASK		0x007F0001
+#define CFG_SYS_CS0_CTRL		0x00001FA0
 
 #endif				/* _M5208EVBE_H */

diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index f200d70..ed45ecc 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h

@@ -18,14 +18,12 @@
  * (easy to change)
  */
 
-#define CONFIG_SYS_UART_PORT		(0)
-
-#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+#define CFG_SYS_UART_PORT		(0)
 
 /* I2C */
-#define CONFIG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
-#define CONFIG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
-#define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
+#define CFG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
+#define CFG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CFG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
 
 /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
 #ifdef CONFIG_MCFFEC
@@ -50,10 +48,10 @@
 
 #define CONFIG_PRAM		512	/* 512 KB */
 
-#define CONFIG_SYS_CLK			75000000
-#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
+#define CFG_SYS_CLK			75000000
+#define CFG_SYS_CPU_CLK		CFG_SYS_CLK * 2
 
-#define CONFIG_SYS_MBAR		0x40000000
+#define CFG_SYS_MBAR		0x40000000
 
 /*
  * Low Level Configuration Settings
@@ -63,17 +61,17 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL	0x21
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
 
 /*
  * For booting Linux, the board info and command line data
@@ -81,16 +79,16 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #ifdef CONFIG_SYS_FLASH_CFI
-#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CFG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
 #endif
 
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#define CFG_SYS_FLASH_BASE		(CFG_SYS_CS0_BASE)
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -104,15 +102,15 @@
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
 					 CF_CACR_CEIB | CF_CACR_DCM | \
 					 CF_CACR_EUSP)
 
@@ -130,13 +128,13 @@
  * CS7 - Available
  */
 #ifdef CONFIG_NORFLASH_PS32BIT
-#	define CONFIG_SYS_CS0_BASE	0xFFC00000
-#	define CONFIG_SYS_CS0_MASK	0x003f0001
-#	define CONFIG_SYS_CS0_CTRL	0x00001D00
+#	define CFG_SYS_CS0_BASE	0xFFC00000
+#	define CFG_SYS_CS0_MASK	0x003f0001
+#	define CFG_SYS_CS0_CTRL	0x00001D00
 #else
-#	define CONFIG_SYS_CS0_BASE	0xFFE00000
-#	define CONFIG_SYS_CS0_MASK	0x001f0001
-#	define CONFIG_SYS_CS0_CTRL	0x00001D80
+#	define CFG_SYS_CS0_BASE	0xFFE00000
+#	define CFG_SYS_CS0_MASK	0x001f0001
+#	define CFG_SYS_CS0_CTRL	0x00001D80
 #endif
 
 #endif				/* _M5329EVB_H */

diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 9ff66d7..0e38eeb 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h

@@ -18,7 +18,7 @@
  * (easy to change)
  */
 
-#define CONFIG_SYS_UART_PORT		(0)
+#define CFG_SYS_UART_PORT		(0)
 
 #undef CONFIG_MONITOR_IS_IN_RAM		/* no pre-loader required!!! ;-) */
 
@@ -26,9 +26,9 @@
  * Clock configuration: enable only one of the following options
  */
 
-#undef  CONFIG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
-#define CONFIG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
-#define	CONFIG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */
+#undef  CFG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
+#define CFG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
+#define	CFG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */
 
 /*
  * Low Level Configuration Settings
@@ -36,14 +36,14 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
-#define	CONFIG_SYS_MBAR2		0x80000000
+#define CFG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define	CFG_SYS_MBAR2		0x80000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
 
 #define LDS_BOARD_TEXT \
 	. = DEFINED(env_offset) ? env_offset : .; \
@@ -52,11 +52,11 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CFG_SYS_FLASH_BASE		(CFG_SYS_CS0_BASE)
 
 #if 0 /* test-only */
 #define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -67,33 +67,33 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #ifdef CONFIG_SYS_FLASH_CFI
 
-#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
-#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#	define CFG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE }
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_FLASH_BASE | \
 					 CF_ADDRMASK(2) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CFG_SYS_CACHE_ACR1		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
 					 CF_CACR_DBWE)
 
 /*-----------------------------------------------------------------------
@@ -101,25 +101,25 @@
  */
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CONFIG_SYS_CS0_BASE		0xffe00000
-#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
+#define	CFG_SYS_CS0_BASE		0xffe00000
+#define	CFG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CFG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
 
 /* CS1 - FPGA, address 0xe0000000 */
-#define	CONFIG_SYS_CS1_BASE		0xe0000000
-#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
-#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CFG_SYS_CS1_BASE		0xe0000000
+#define	CFG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CFG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define	CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
-#define	CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
-#define	CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
-#define	CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
-#define	CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
-#define	CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led                     */
+#define	CFG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
+#define	CFG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CFG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
+#define	CFG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
+#define	CFG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define	CFG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CFG_SYS_GPIO1_LED		0x00400000	/* user led                     */
 
 #endif	/* M5249 */

diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index f7bfe59..7e37c6d 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h

@@ -8,7 +8,7 @@
 
 #include <linux/stringify.h>
 
-#define CONFIG_SYS_UART_PORT		(0)
+#define CFG_SYS_UART_PORT		(0)
 
 
 /* Configuration for environment
@@ -20,7 +20,7 @@
 	env/embedded.o(.text*);
 
 #ifdef CONFIG_DRIVER_DM9000
-#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
+#	define CONFIG_DM9000_BASE	(CFG_SYS_CS1_BASE | 0x300)
 #	define DM9000_IO		CONFIG_DM9000_BASE
 #	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
 #	undef CONFIG_DM9000_DEBUG
@@ -45,18 +45,18 @@
 #define CONFIG_HOSTNAME		"M5253DEMO"
 
 /* I2C */
-#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
-#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
-#define CONFIG_SYS_I2C_PINMUX_SET	(0)
+#define CFG_SYS_I2C_PINMUX_REG	(*(u32 *) (CFG_SYS_MBAR+0x19C))
+#define CFG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
+#define CFG_SYS_I2C_PINMUX_SET	(0)
 
-#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
-#define CONFIG_SYS_FAST_CLK
-#ifdef CONFIG_SYS_FAST_CLK
-#	define CONFIG_SYS_PLLCR	0x1243E054
-#	define CONFIG_SYS_CLK		140000000
+#undef CFG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CFG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
+#	define CFG_SYS_PLLCR	0x1243E054
+#	define CFG_SYS_CLK		140000000
 #else
-#	define CONFIG_SYS_PLLCR	0x135a4140
-#	define CONFIG_SYS_CLK		70000000
+#	define CFG_SYS_PLLCR	0x135a4140
+#	define CFG_SYS_CLK		70000000
 #endif
 
 /*
@@ -65,32 +65,32 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
-#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */
+#define CFG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CFG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */
 
 /*
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#define CFG_SYS_FLASH_BASE		(CFG_SYS_CS0_BASE)
 
 #define FLASH_SST6401B		0x200
 #define SST_ID_xF6401B		0x236D236D
@@ -101,45 +101,45 @@
  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
  * 0x30 is block erase in SST
  */
-#	define CONFIG_SYS_FLASH_SIZE		0x800000
+#	define CFG_SYS_FLASH_SIZE		0x800000
 #else
-#	define CONFIG_SYS_SST_SECT		2048
-#	define CONFIG_SYS_SST_SECTSZ		0x1000
+#	define CFG_SYS_SST_SECT		2048
+#	define CFG_SYS_SST_SECTSZ		0x1000
 #endif
 
 /* Cache Configuration */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_FLASH_BASE | \
 					 CF_ADDRMASK(8) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CFG_SYS_CACHE_ACR1		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
 					 CF_CACR_DBWE)
 
-#define CONFIG_SYS_CS0_BASE		0xFF800000
-#define CONFIG_SYS_CS0_MASK		0x007F0021
-#define CONFIG_SYS_CS0_CTRL		0x00001D80
+#define CFG_SYS_CS0_BASE		0xFF800000
+#define CFG_SYS_CS0_MASK		0x007F0021
+#define CFG_SYS_CS0_CTRL		0x00001D80
 
-#define CONFIG_SYS_CS1_BASE		0xE0000000
-#define CONFIG_SYS_CS1_MASK		0x00000001
-#define CONFIG_SYS_CS1_CTRL		0x00003DD8
+#define CFG_SYS_CS1_BASE		0xE0000000
+#define CFG_SYS_CS1_MASK		0x00000001
+#define CFG_SYS_CS1_CTRL		0x00003DD8
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
-#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
-#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
-#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
-#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */
+#define CFG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CFG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CFG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CFG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CFG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CFG_SYS_GPIO1_LED		0x00400000	/* user led */
 
 #endif				/* _M5253DEMO_H */

diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index dcd8365..a9339e5 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h

@@ -17,9 +17,7 @@
  * (easy to change)
  */
 
-#define CONFIG_SYS_UART_PORT		(0)
-
-#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
+#define CFG_SYS_UART_PORT		(0)
 
 #undef CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
 
@@ -51,59 +49,59 @@
 	"save\0"				\
 	""
 
-#define CONFIG_SYS_CLK			66000000
+#define CFG_SYS_CLK			66000000
 
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
-#define CONFIG_SYS_SCR			0x0003
-#define CONFIG_SYS_SPR			0xffff
+#define CFG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CFG_SYS_SCR			0x0003
+#define CFG_SYS_SPR			0xffff
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		4	/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_SIZE		4	/* SDRAM size in MB */
+#define CFG_SYS_FLASH_BASE		0xffe00000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /*
  * FLASH organization
  */
 #ifdef CONFIG_SYS_FLASH_CFI
-#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CFG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
 					 CF_CACR_DISD | CF_CACR_INVI | \
 					 CF_CACR_CEIB | CF_CACR_DCM | \
 					 CF_CACR_EUSP)
@@ -111,11 +109,11 @@
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CONFIG_SYS_PACNT		0x00000000
-#define CONFIG_SYS_PADDR		0x0000
-#define CONFIG_SYS_PADAT		0x0000
-#define CONFIG_SYS_PBCNT		0x55554155	/* Ethernet/UART configuration */
-#define CONFIG_SYS_PBDDR		0x0000
-#define CONFIG_SYS_PBDAT		0x0000
-#define CONFIG_SYS_PDCNT		0x00000000
+#define CFG_SYS_PACNT		0x00000000
+#define CFG_SYS_PADDR		0x0000
+#define CFG_SYS_PADAT		0x0000
+#define CFG_SYS_PBCNT		0x55554155	/* Ethernet/UART configuration */
+#define CFG_SYS_PBDDR		0x0000
+#define CFG_SYS_PBDAT		0x0000
+#define CFG_SYS_PDCNT		0x00000000
 #endif				/* _M5272C3_H */

diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 9012794..ff9f853 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h

@@ -21,7 +21,7 @@
  * (easy to change)
  */
 
-#define CONFIG_SYS_UART_PORT		(0)
+#define CFG_SYS_UART_PORT		(0)
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -34,9 +34,9 @@
 /* Available command configuration */
 
 /* I2C */
-#define CONFIG_SYS_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
-#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFF0)
-#define CONFIG_SYS_I2C_PINMUX_SET	(0x000F)
+#define CFG_SYS_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
+#define CFG_SYS_I2C_PINMUX_CLR	(0xFFF0)
+#define CFG_SYS_I2C_PINMUX_SET	(0x000F)
 
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_OVERWRITE_ETHADDR_ONCE
@@ -54,7 +54,7 @@
 	"save\0"				\
 	""
 
-#define CONFIG_SYS_CLK			150000000
+#define CFG_SYS_CLK			150000000
 
 /*
  * Low Level Configuration Settings
@@ -62,49 +62,49 @@
  * You should know what you are doing if you make changes here.
  */
 
-#define CONFIG_SYS_MBAR		0x40000000
+#define CFG_SYS_MBAR		0x40000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 
-#define CONFIG_SYS_FLASH_SIZE		0x200000
+#define CFG_SYS_FLASH_SIZE		0x200000
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
 					 CF_CACR_DISD | CF_CACR_INVI | \
 					 CF_CACR_CEIB | CF_CACR_DCM | \
 					 CF_CACR_EUSP)
@@ -112,12 +112,12 @@
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CONFIG_SYS_CS0_BASE		0xffe00000
-#define CONFIG_SYS_CS0_CTRL		0x00001980
-#define CONFIG_SYS_CS0_MASK		0x001F0001
+#define CFG_SYS_CS0_BASE		0xffe00000
+#define CFG_SYS_CS0_CTRL		0x00001980
+#define CFG_SYS_CS0_MASK		0x001F0001
 
-#define CONFIG_SYS_CS1_BASE		0x30000000
-#define CONFIG_SYS_CS1_CTRL		0x00001900
-#define CONFIG_SYS_CS1_MASK		0x00070001
+#define CFG_SYS_CS1_BASE		0x30000000
+#define CFG_SYS_CS1_CTRL		0x00001900
+#define CFG_SYS_CS1_MASK		0x00070001
 
 #endif	/* _M5275EVB_H */

diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index e191dc6..bde9e77 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h

@@ -17,7 +17,7 @@
  * (easy to change)
  */
 
-#define CONFIG_SYS_UART_PORT		(0)
+#define CFG_SYS_UART_PORT		(0)
 
 #undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
 
@@ -49,98 +49,92 @@
 	"save\0"				\
 	""
 
-#define	CONFIG_SYS_CLK			64000000
+#define	CFG_SYS_CLK			64000000
 
 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 
-#define CONFIG_SYS_MFD			0x02	/* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */
+#define CFG_SYS_MFD			0x02	/* PLL Multiplication Factor Devider */
+#define CFG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */
 
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
-#define	CONFIG_SYS_MBAR		0x40000000
+#define	CFG_SYS_MBAR		0x40000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM    */
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM    */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define	CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
-#define	CONFIG_SYS_INT_FLASH_BASE	0xf0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define	CFG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE
+#define	CFG_SYS_INT_FLASH_BASE	0xf0000000
+#define CFG_SYS_INT_FLASH_ENABLE	0x21
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #ifdef CONFIG_SYS_FLASH_CFI
 
-#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
-#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#	define CFG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE }
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
 					 CF_CACR_CEIB | CF_CACR_DBWE | \
 					 CF_CACR_EUSP)
 
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CONFIG_SYS_CS0_BASE		0xFFE00000
-#define CONFIG_SYS_CS0_CTRL		0x00001980
-#define CONFIG_SYS_CS0_MASK		0x001F0001
+#define CFG_SYS_CS0_BASE		0xFFE00000
+#define CFG_SYS_CS0_CTRL		0x00001980
+#define CFG_SYS_CS0_MASK		0x001F0001
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
-#define CONFIG_SYS_PADDR		0x0000000
-#define CONFIG_SYS_PADAT		0x0000000
+#define CFG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
+#define CFG_SYS_PADDR		0x0000000
+#define CFG_SYS_PADAT		0x0000000
 
-#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
-#define CONFIG_SYS_PBDDR		0x0000000
-#define CONFIG_SYS_PBDAT		0x0000000
+#define CFG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CFG_SYS_PBDDR		0x0000000
+#define CFG_SYS_PBDAT		0x0000000
 
-#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
-#define CONFIG_SYS_PCDDR		0x0000000
-#define CONFIG_SYS_PCDAT		0x0000000
-
-#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
-#define CONFIG_SYS_PCDDR		0x0000000
-#define CONFIG_SYS_PCDAT		0x0000000
+#define CFG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
 
-#define CONFIG_SYS_PEHLPAR		0xC0
-#define CONFIG_SYS_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
-#define CONFIG_SYS_DDRUA		0x05
-#define CONFIG_SYS_PJPAR		0xFF
+#define CFG_SYS_PEHLPAR		0xC0
+#define CFG_SYS_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
+#define CFG_SYS_DDRUA		0x05
+#define CFG_SYS_PJPAR		0xFF
 
 #endif				/* _CONFIG_M5282EVB_H */

diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 79a4e61..42b74ae 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h

@@ -18,17 +18,15 @@
  * (easy to change)
  */
 
-#define CONFIG_SYS_UART_PORT		(0)
-
-#define CONFIG_WATCHDOG_TIMEOUT		5000
+#define CFG_SYS_UART_PORT		(0)
 
 #ifdef CONFIG_MCFFEC
-#	define CONFIG_SYS_TX_ETH_BUFFER	8
-#	define CONFIG_SYS_FEC_BUF_USE_SRAM
+#	define CFG_SYS_TX_ETH_BUFFER	8
+#	define CFG_SYS_FEC_BUF_USE_SRAM
 #endif
 
-#define CONFIG_SYS_RTC_CNT		(0x8000)
-#define CONFIG_SYS_RTC_SETUP		(RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
+#define CFG_SYS_RTC_CNT		(0x8000)
+#define CFG_SYS_RTC_SETUP		(RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
 
 /* I2C */
 
@@ -54,10 +52,10 @@
 
 #define CONFIG_PRAM		512	/* 512 KB */
 
-#define CONFIG_SYS_CLK		80000000
-#define CONFIG_SYS_CPU_CLK	CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK		80000000
+#define CFG_SYS_CPU_CLK	CFG_SYS_CLK * 3
 
-#define CONFIG_SYS_MBAR		0xFC000000
+#define CFG_SYS_MBAR		0xFC000000
 
 /*
  * Low Level Configuration Settings
@@ -67,39 +65,39 @@
 /*
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE		0x20000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CFG_SYS_INIT_RAM_ADDR	0x80000000
+#define CFG_SYS_INIT_RAM_SIZE		0x20000	/* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL	0x221
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1		0x43711630
-#define CONFIG_SYS_SDRAM_CFG2		0x56670000
-#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD		0x80010000
-#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1		0x43711630
+#define CFG_SYS_SDRAM_CFG2		0x56670000
+#define CFG_SYS_SDRAM_CTRL		0xE1092000
+#define CFG_SYS_SDRAM_EMOD		0x80010000
+#define CFG_SYS_SDRAM_MODE		0x00CD0000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #ifdef CONFIG_SYS_FLASH_CFI
 #	define CONFIG_FLASH_SPANSION_S29WS_N	1
-#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CFG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
 #endif
 
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -113,15 +111,15 @@
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
 					 CF_CACR_DCM_P)
 
 /*-----------------------------------------------------------------------
@@ -135,12 +133,12 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CONFIG_SYS_CS0_BASE		0
-#define CONFIG_SYS_CS0_MASK		0x00FF0001
-#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#define CFG_SYS_CS0_BASE		0
+#define CFG_SYS_CS0_MASK		0x00FF0001
+#define CFG_SYS_CS0_CTRL		0x00001FA0
 
-#define CONFIG_SYS_CS1_BASE		0xC0000000
-#define CONFIG_SYS_CS1_MASK		0x00070001
-#define CONFIG_SYS_CS1_CTRL		0x00001FA0
+#define CFG_SYS_CS1_BASE		0xC0000000
+#define CFG_SYS_CS1_MASK		0x00070001
+#define CFG_SYS_CS1_CTRL		0x00001FA0
 
 #endif				/* _M53017EVB_H */

diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 47ea51c..72f0c63 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h

@@ -18,9 +18,7 @@
  * (easy to change)
  */
 
-#define CONFIG_SYS_UART_PORT		(0)
-
-#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+#define CFG_SYS_UART_PORT		(0)
 
 /* I2C */
 
@@ -46,12 +44,12 @@
 
 #define CONFIG_PRAM		512	/* 512 KB */
 
-#define CONFIG_SYS_CLK			80000000
-#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK			80000000
+#define CFG_SYS_CPU_CLK		CFG_SYS_CLK * 3
 
-#define CONFIG_SYS_MBAR		0xFC000000
+#define CFG_SYS_MBAR		0xFC000000
 
-#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)
+#define CFG_SYS_LATCH_ADDR		(CFG_SYS_CS1_BASE + 0x80000)
 
 /*
  * Low Level Configuration Settings
@@ -61,45 +59,44 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CFG_SYS_INIT_RAM_ADDR	0x80000000
+#define CFG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL	0x221
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1		0x53722730
-#define CONFIG_SYS_SDRAM_CFG2		0x56670000
-#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD		0x40010000
-#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1		0x53722730
+#define CFG_SYS_SDRAM_CFG2		0x56670000
+#define CFG_SYS_SDRAM_CTRL		0xE1092000
+#define CFG_SYS_SDRAM_EMOD		0x40010000
+#define CFG_SYS_SDRAM_MODE		0x018D0000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #ifdef CONFIG_SYS_FLASH_CFI
-#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CFG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
 #endif
 
 #ifdef CONFIG_CMD_NAND
-#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
-#	define CONFIG_SYS_NAND_SIZE		1
-#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#	define CFG_SYS_NAND_BASE		CFG_SYS_CS2_BASE
+#	define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #	define NAND_ALLOW_ERASE_ALL	1
 #endif
 
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -113,15 +110,15 @@
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
 					 CF_CACR_DCM_P)
 
 /*-----------------------------------------------------------------------
@@ -135,18 +132,18 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CONFIG_SYS_CS0_BASE		0
-#define CONFIG_SYS_CS0_MASK		0x007f0001
-#define CONFIG_SYS_CS0_CTRL		0x00001fa0
+#define CFG_SYS_CS0_BASE		0
+#define CFG_SYS_CS0_MASK		0x007f0001
+#define CFG_SYS_CS0_CTRL		0x00001fa0
 
-#define CONFIG_SYS_CS1_BASE		0x10000000
-#define CONFIG_SYS_CS1_MASK		0x001f0001
-#define CONFIG_SYS_CS1_CTRL		0x002A3780
+#define CFG_SYS_CS1_BASE		0x10000000
+#define CFG_SYS_CS1_MASK		0x001f0001
+#define CFG_SYS_CS1_CTRL		0x002A3780
 
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_CS2_BASE		0x20000000
-#define CONFIG_SYS_CS2_MASK		(16 << 20)
-#define CONFIG_SYS_CS2_CTRL		0x00001f60
+#define CFG_SYS_CS2_BASE		0x20000000
+#define CFG_SYS_CS2_MASK		(16 << 20)
+#define CFG_SYS_CS2_CTRL		0x00001f60
 #endif
 
 #endif				/* _M5329EVB_H */

diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index a2e36cc..4e8b54e 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h

@@ -20,9 +20,7 @@
  * (easy to change)
  */
 
-#define CONFIG_SYS_UART_PORT		(0)
-
-#define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */
+#define CFG_SYS_UART_PORT		(0)
 
 /* I2C */
 
@@ -48,12 +46,12 @@
 
 #define CONFIG_PRAM		512	/* 512 KB */
 
-#define CONFIG_SYS_CLK			80000000
-#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK			80000000
+#define CFG_SYS_CPU_CLK		CFG_SYS_CLK * 3
 
-#define CONFIG_SYS_MBAR		0xFC000000
+#define CFG_SYS_MBAR		0xFC000000
 
-#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)
+#define CFG_SYS_LATCH_ADDR		(CFG_SYS_CS1_BASE + 0x80000)
 
 /*
  * Low Level Configuration Settings
@@ -63,43 +61,42 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CFG_SYS_INIT_RAM_ADDR	0x80000000
+#define CFG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL	0x221
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1		0x53722730
-#define CONFIG_SYS_SDRAM_CFG2		0x56670000
-#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD		0x40010000
-#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1		0x53722730
+#define CFG_SYS_SDRAM_CFG2		0x56670000
+#define CFG_SYS_SDRAM_CTRL		0xE1092000
+#define CFG_SYS_SDRAM_EMOD		0x40010000
+#define CFG_SYS_SDRAM_MODE		0x018D0000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #ifdef CONFIG_SYS_FLASH_CFI
-#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CFG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
 #endif
 
-#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
-#	define CONFIG_SYS_NAND_SIZE		1
-#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#	define CFG_SYS_NAND_BASE		CFG_SYS_CS2_BASE
+#	define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #	define NAND_ALLOW_ERASE_ALL	1
 
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -113,15 +110,15 @@
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
 					 CF_CACR_DCM_P)
 
 /*-----------------------------------------------------------------------
@@ -135,16 +132,16 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CONFIG_SYS_CS0_BASE		0
-#define CONFIG_SYS_CS0_MASK		0x007f0001
-#define CONFIG_SYS_CS0_CTRL		0x00001fa0
+#define CFG_SYS_CS0_BASE		0
+#define CFG_SYS_CS0_MASK		0x007f0001
+#define CFG_SYS_CS0_CTRL		0x00001fa0
 
-#define CONFIG_SYS_CS1_BASE		0x10000000
-#define CONFIG_SYS_CS1_MASK		0x001f0001
-#define CONFIG_SYS_CS1_CTRL		0x002A3780
+#define CFG_SYS_CS1_BASE		0x10000000
+#define CFG_SYS_CS1_MASK		0x001f0001
+#define CFG_SYS_CS1_CTRL		0x002A3780
 
-#define CONFIG_SYS_CS2_BASE		0x20000000
-#define CONFIG_SYS_CS2_MASK		(16 << 20)
-#define CONFIG_SYS_CS2_CTRL		0x00001f60
+#define CFG_SYS_CS2_BASE		0x20000000
+#define CFG_SYS_CS2_MASK		(16 << 20)
+#define CFG_SYS_CS2_CTRL		0x00001f60
 
 #endif				/* _M5373EVB_H */

diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
index b080933..232cf9e 100644
--- a/include/configs/MCR3000.h
+++ b/include/configs/MCR3000.h

@@ -59,21 +59,21 @@
 /* Miscellaneous configurable options */
 
 /* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x2800)
-#define	CONFIG_SYS_INIT_RAM_SIZE	(0x2e00 - 0x2800)
+#define CFG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x2800)
+#define	CFG_SYS_INIT_RAM_SIZE	(0x2e00 - 0x2800)
 
-/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
+#define	CFG_SYS_SDRAM_BASE		0x00000000
 
 /* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_FLASH_BASE		CONFIG_TEXT_BASE
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+#define	CFG_SYS_BOOTMAPSZ		(8 << 20)
 
 /* Environment Configuration */
 
@@ -82,6 +82,6 @@
 /* Ethernet configuration part */
 
 /* NAND configuration part */
-#define CONFIG_SYS_NAND_BASE		0x0C000000
+#define CFG_SYS_NAND_BASE		0x0C000000
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index bb93c28..95a9019 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h

@@ -14,31 +14,24 @@
  * High Level Configuration Options
  */
 
-#define CONFIG_HWCONFIG
-
-/*
- * On-board devices
- */
-#define CONFIG_VSC7385_ENET
-
 /* System performance - define the value i.e. CONFIG_SYS_XXX
 */
 
 /* System Clock Configuration Register */
-#define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
+#define CFG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
+#define CFG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
+#define CFG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
 
 /*
  * System IO Config
  */
-#define CONFIG_SYS_SICRH		0x08200000
-#define CONFIG_SYS_SICRL		0x00000000
+#define CFG_SYS_SICRH		0x08200000
+#define CFG_SYS_SICRL		0x00000000
 
 /*
  * Output Buffer Impedance
  */
-#define CONFIG_SYS_OBIR		0x30100000
+#define CFG_SYS_OBIR		0x30100000
 
 /*
  * Device configurations
@@ -59,25 +52,25 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
+#define CFG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CFG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
 
-#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
+#define CFG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 
 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */
 
 /*
  * Manually set up DDR parameters
  */
-#define CONFIG_SYS_SDRAM_SIZE		0x10000000 /* 256 MiB */
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+#define CFG_SYS_SDRAM_SIZE		0x10000000 /* 256 MiB */
+#define CFG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CFG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
 					| CSCONFIG_ODT_WR_ONLY_CURRENT \
 					| CSCONFIG_ROW_BIT_13 \
 					| CSCONFIG_COL_BIT_10)
 
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+#define CFG_SYS_DDR_TIMING_3	0x00000000
+#define CFG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
 				| (0 << TIMING_CFG0_WRT_SHIFT) \
 				| (0 << TIMING_CFG0_RRT_SHIFT) \
 				| (0 << TIMING_CFG0_WWT_SHIFT) \
@@ -86,7 +79,7 @@
 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 				/* 0x00260802 */ /* DDR400 */
-#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+#define CFG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
@@ -95,7 +88,7 @@
 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
 				/* 0x3937d322 */
-#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+#define CFG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 				| (5 << TIMING_CFG2_CPO_SHIFT) \
 				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
@@ -104,23 +97,23 @@
 				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 				/* 0x02984cc8 */
 
-#define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
+#define CFG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 				/* 0x06090100 */
 
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+#define CFG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
 					| SDRAM_CFG_SDRAM_TYPE_DDR2)
 					/* 0x43000000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
+#define CFG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
+#define CFG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 					| (0x0442 << SDRAM_MODE_SD_SHIFT))
 					/* 0x04400442 */ /* DDR400 */
-#define CONFIG_SYS_DDR_MODE2		0x00000000
+#define CFG_SYS_DDR_MODE2		0x00000000
 
 /*
  * Memory test
  */
-#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#undef CFG_SYS_DRAM_TEST		/* memory test, takes time */
 
 /*
  * The reserved memory
@@ -129,65 +122,61 @@
 /*
  * Initial RAM Base Address Setup
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
 
 /*
  * FLASH on the Local Bus
  */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
+#define CFG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CFG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
 
 /*
  * NAND Flash on the Local Bus
  */
-#define CONFIG_SYS_NAND_BASE	0xE0600000
+#define CFG_SYS_NAND_BASE	0xE0600000
 
 
 /* Vitesse 7385 */
 
-#define CONFIG_SYS_VSC7385_BASE	0xF0000000
+#define CFG_SYS_VSC7385_BASE	0xF0000000
 
 /*
  * Serial Port
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CFG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+#define CFG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CFG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 /* SERDES */
-#define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1	0xe3000
 #define CONFIG_FSL_SERDES2	0xe3100
 
 /* I2C */
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+#define CFG_SYS_I2C_NOPROBES		{ {0, 0x51} }
 
 /*
  * Config on-board RTC
  */
-#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+#define CFG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
 
 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
+#define CFG_SYS_PCIE1_CFG_BASE	0xA0000000
+#define CFG_SYS_PCIE1_CFG_SIZE	0x08000000
+#define CFG_SYS_PCIE1_MEM_PHYS	0xA8000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xB8000000
 
-#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
+#define CFG_SYS_PCIE2_CFG_BASE	0xC0000000
+#define CFG_SYS_PCIE2_CFG_SIZE	0x08000000
+#define CFG_SYS_PCIE2_MEM_PHYS	0xC8000000
+#define CFG_SYS_PCIE2_IO_PHYS	0xD8000000
 
 /*
  * TSEC
@@ -200,7 +189,7 @@
 
 #ifdef CONFIG_TSEC1
 #define CONFIG_TSEC1_NAME		"TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET		0x24000
+#define CFG_SYS_TSEC1_OFFSET		0x24000
 #define TSEC1_PHY_ADDR			2
 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX			0
@@ -228,7 +217,7 @@
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
 
 /*
  * Environment Configuration

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index b241939..780ee5a 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h

@@ -13,11 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-
-#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
-
 #ifndef __ASSEMBLY__
 #include <linux/stringify.h>
 #endif
@@ -31,16 +26,15 @@
  * Only possible on E500 Version 2 or newer cores.
  */
 
-#define CONFIG_SYS_CCSRBAR		0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR		0xe0000000
+#define CFG_SYS_CCSRBAR_PHYS_LOW	CFG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
@@ -115,32 +109,30 @@
  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
  */
 
-#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CFG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS	0xfff000000ull
+#define CFG_SYS_FLASH_BASE_PHYS	0xfff000000ull
 #else
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_FLASH_BANKS_LIST \
-	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_HWCONFIG			/* enable hwconfig */
+#define CFG_SYS_FLASH_BANKS_LIST \
+	{CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
 
 /*
  * SDRAM on the Local Bus
  */
-#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
 #else
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	CONFIG_SYS_LBC_SDRAM_BASE
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS	CFG_SYS_LBC_SDRAM_BASE
 #endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CFG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -152,12 +144,12 @@
  * 0	4    8	  12   16   20	 24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
 /*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -170,10 +162,10 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
-#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
+#define CFG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CFG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
+#define CFG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CFG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
 /*
  * Common settings for all Local Bus SDRAM commands.
@@ -181,7 +173,7 @@
  *		    or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+#define CFG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
 				| LSDMR_PRETOACT7	\
 				| LSDMR_ACTTORW7	\
 				| LSDMR_BL8		\
@@ -220,8 +212,6 @@
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
-#define CONFIG_FSL_CADMUS
-
 #define CADMUS_BASE_ADDR 0xf8000000
 #ifdef CONFIG_PHYS_64BIT
 #define CADMUS_BASE_ADDR_PHYS	0xff8000000ull
@@ -229,76 +219,69 @@
 #define CADMUS_BASE_ADDR_PHYS	CADMUS_BASE_ADDR
 #endif
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CFG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x4600)
 
 /*
  * I2C
  */
 #if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+#define CFG_SYS_I2C_NOPROBES		{ {0, 0x69} }
 #endif
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CFG_SYS_PCI1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS		0xe0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCI1_MEM_PHYS	0xc00000000ull
 #else
-#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CFG_SYS_PCI1_MEM_PHYS	0x80000000
 #endif
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CFG_SYS_PCI1_IO_VIRT	0xe2000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
+#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull
 #else
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CFG_SYS_PCI1_IO_PHYS	0xe2000000
 #endif
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CFG_SYS_PCIE1_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
+#define CFG_SYS_PCIE1_IO_VIRT	0xe3000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
+#define CFG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 #else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xe3000000
 #endif
 #endif
 
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xc0000000
+#define CFG_SYS_SRIO1_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
+#define CFG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
 #else
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc0000000
+#define CFG_SYS_SRIO1_MEM_PHYS	0xc0000000
 #endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
 #if defined(CONFIG_TSEC_ENET)
 
@@ -336,7 +319,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Environment Configuration

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index addb306..b1d6b15 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h

@@ -16,10 +16,10 @@
 #include <asm/config_mpc85xx.h>
 
 #ifdef CONFIG_SDCARD
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CFG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
 #endif
 
 #ifdef CONFIG_SPIFLASH
@@ -27,27 +27,27 @@
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #else
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
 #endif
 #endif
 
 #ifdef CONFIG_MTD_RAW_NAND
 #ifdef CONFIG_NXP_ESBC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CFG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CFG_SYS_NAND_U_BOOT_START	0x00200000
 #else
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CFG_SYS_NAND_U_BOOT_START	(0x11000000)
 #elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0xD0000000
-#define CONFIG_SYS_NAND_U_BOOT_START	0xD0000000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0xD0000000
+#define CFG_SYS_NAND_U_BOOT_START	0xD0000000
 #endif
 #endif
 #endif
@@ -68,35 +68,34 @@
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CFG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS	0x80000000
 #endif
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CFG_SYS_PCIE1_IO_VIRT	0xffc00000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+#define CFG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
 #else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#define CFG_SYS_PCIE1_IO_PHYS	0xffc00000
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CFG_SYS_PCIE2_IO_VIRT	0xffc10000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#define CFG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
 #else
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CFG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
 #endif
 
-#define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
@@ -110,12 +109,12 @@
 #ifndef __ASSEMBLY__
 extern unsigned long get_sdram_size(void);
 #endif
-#define CONFIG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_CCSRBAR			0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW		CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR			0xffe00000
+#define CFG_SYS_CCSRBAR_PHYS_LOW		CFG_SYS_CCSRBAR
 
 /*
  * Memory map
@@ -136,54 +135,52 @@
  */
 /* NOR Flash on IFC */
 
-#define CONFIG_SYS_FLASH_BASE		0xee000000
+#define CFG_SYS_FLASH_BASE		0xee000000
 
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)
 #else
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(32*1024*1024)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(7)
+#define CFG_SYS_NOR_AMASK	IFC_AMASK(32*1024*1024)
+#define CFG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(7)
 /* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_FTIM0	FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_FTIM0	FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5)
-#define CONFIG_SYS_NOR_FTIM1	FTIM1_NOR_TACO(0x1e) | \
+#define CFG_SYS_NOR_FTIM1	FTIM1_NOR_TACO(0x1e) | \
 				FTIM1_NOR_TRAD_NOR(0x0f)
-#define CONFIG_SYS_NOR_FTIM2	FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2	FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWP(0x1c)
-#define CONFIG_SYS_NOR_FTIM3	0x0
+#define CFG_SYS_NOR_FTIM3	0x0
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
 
 /* CFI for NOR Flash */
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#define CFG_SYS_NAND_BASE_PHYS	0xfff800000ull
 #else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 #endif
 
-#define CONFIG_MTD_PARTITION
-
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
 #if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_2	/* RAL = 2 Bytes */ \
@@ -192,7 +189,7 @@
 				| CSOR_NAND_PB(32))	/* 32 Pages Per Block */
 
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
@@ -201,141 +198,134 @@
 				| CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
 #endif
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_TARGET_P1010RDB_PA)
 /* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
+#define CFG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
 					FTIM0_NAND_TWP(0x0C)   | \
 					FTIM0_NAND_TWCHT(0x04) | \
 					FTIM0_NAND_TWH(0x05)
-#define CONFIG_SYS_NAND_FTIM1		FTIM1_NAND_TADLE(0x1d) | \
+#define CFG_SYS_NAND_FTIM1		FTIM1_NAND_TADLE(0x1d) | \
 					FTIM1_NAND_TWBE(0x1d)  | \
 					FTIM1_NAND_TRR(0x07)   | \
 					FTIM1_NAND_TRP(0x0c)
-#define CONFIG_SYS_NAND_FTIM2		FTIM2_NAND_TRAD(0x0c) | \
+#define CFG_SYS_NAND_FTIM2		FTIM2_NAND_TRAD(0x0c) | \
 					FTIM2_NAND_TREH(0x05) | \
 					FTIM2_NAND_TWHRE(0x0f)
-#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+#define CFG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
 
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
+#define CFG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
+#define CFG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a)  | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3	0x0
+#define CFG_SYS_NAND_FTIM3	0x0
 #endif
 
-#define CONFIG_SYS_NAND_DDR_LAW		11
-
 /* Set up IFC registers for boot location NOR/NAND */
 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1		CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
 #else
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0		CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
 /* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE		0xffb00000
+#define CFG_SYS_CPLD_BASE		0xffb00000
 
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CPLD_BASE_PHYS	0xfffb00000ull
+#define CFG_SYS_CPLD_BASE_PHYS	0xfffb00000ull
 #else
-#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE_PHYS	CFG_SYS_CPLD_BASE
 #endif
 
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CSPR3	(CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
-#define CONFIG_SYS_AMASK3		IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3		0x0
+#define CFG_SYS_AMASK3		IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3		0x0
 /* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3		0x0
+#define CFG_SYS_CS3_FTIM3		0x0
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* End of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
+#define CFG_SYS_INIT_RAM_SIZE	0x00004000 /* End of used area in RAM */
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Config the L2 Cache as L2 SRAM
  */
 #if defined(CONFIG_SPL_BUILD)
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR		0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS	CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END	(CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR		0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS	CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END	(CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #else
-#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR		0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS	CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END	(CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #endif
 #endif
 #endif
 
 /* Serial Port */
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
+#define CFG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x4600)
 
 /* I2C */
 #define I2C_PCA9557_ADDR1		0x18
@@ -349,8 +339,7 @@
 /* enable read and write access to EEPROM */
 
 /* RTC */
-#define CONFIG_RTC_PT7C4338
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CFG_SYS_I2C_RTC_ADDR	0x68
 
 /*
  * SPI interface will not be available in case of NAND boot SPI CS0 will be
@@ -400,7 +389,7 @@
  */
 #if defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR		(CFG_SYS_INIT_L2_ADDR + (160 << 10))
 #endif
 #endif
 
@@ -417,7 +406,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
 
 /*
  * Environment Configuration

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 08c1bcc..8b901ca 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h

@@ -18,9 +18,9 @@
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 
@@ -30,13 +30,7 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CFG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 #ifndef __ASSEMBLY__
 #include <linux/stringify.h>
@@ -45,53 +39,53 @@
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0		L2CSR0_L2E
 
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#define CFG_POST CFG_SYS_POST_MEMORY	/* test POST memory test */
 
 /*
  *  Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#define CFG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
+#define CFG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
 		CONFIG_RAMBOOT_TEXT_BASE)
 #else
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
+#define CFG_SYS_INIT_L3_ADDR_PHYS	CFG_SYS_INIT_L3_ADDR
 #endif
 
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#define CFG_SYS_DCSRBAR		0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS		0xf00000000ull
 #endif
 
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 #define SPD_EEPROM_ADDRESS	0x52
-#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 
 /*
  * Local Bus Definitions
  */
 
 /* Set the local bus clock 1/8 of platform clock */
-#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
+#define CFG_SYS_LBC_LCRR		LCRR_CLKDIV_8
 
 /*
  * This board doesn't have a promjet connector.
  * However, it uses commone corenet board LAW and TLB.
  * It is necessary to use the same start address with proper offset.
  */
-#define CONFIG_SYS_FLASH_BASE		0xe0000000
+#define CFG_SYS_FLASH_BASE		0xe0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#define CFG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
 #else
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
 #endif
 
 #define CONFIG_FSL_CPLD
@@ -111,22 +105,22 @@
 
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CFG_SYS_NAND_BASE		0xffa00000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#define CFG_SYS_NAND_BASE_PHYS	0xfffa00000ull
 #else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 #endif
 
-#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CFG_SYS_NAND_BASE_LIST     {CFG_SYS_NAND_BASE}
 
 /* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 			       | BR_PS_8	       /* Port Size = 8 bit */ \
 			       | BR_MS_FCM	       /* MSEL = FCM */ \
 			       | BR_V)		       /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+#define CFG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
 			       | OR_FCM_PGS	       /* Large Page*/ \
 			       | OR_FCM_CSCT \
 			       | OR_FCM_CST \
@@ -136,44 +130,40 @@
 			       | OR_FCM_EHTR)
 #endif /* CONFIG_NAND_FSL_ELBC */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
-
-#define CONFIG_HWCONFIG
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS	CFG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
 #endif
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CFG_SYS_INIT_RAM_SIZE	0x00004000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3	(CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4	(CFG_SYS_CCSRBAR+0x11D600)
 
 /* I2C */
 
@@ -181,49 +171,49 @@
 /*
  * RapidIO
  */
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CFG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#define CFG_SYS_SRIO1_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
 
-#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CFG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CFG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #else
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
+#define CFG_SYS_SRIO2_MEM_PHYS	0xb0000000
 #endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
 
 /* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 
 /*
  * SRIO_PCIE_BOOT - SLAVE
  */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 
 /*
@@ -236,75 +226,68 @@
  */
 
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CFG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#define CFG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
 
 /* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS	10
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CFG_SYS_BMAN_NUM_PORTALS	10
+#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #else
-#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_MEM_PHYS	CFG_SYS_BMAN_MEM_BASE
 #endif
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	10
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#define CFG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS	10
+#define CFG_SYS_QMAN_MEM_BASE	0xf4200000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#define CFG_SYS_QMAN_MEM_PHYS	0xff4200000ull
 #else
-#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_PHYS	CFG_SYS_QMAN_MEM_BASE
 #endif
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
+#define CFG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08
 
 #ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x2
-#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x3
-#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x4
-#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x0
+#define CFG_SYS_FM1_DTSEC1_PHY_ADDR	0x2
+#define CFG_SYS_FM1_DTSEC2_PHY_ADDR	0x3
+#define CFG_SYS_FM1_DTSEC3_PHY_ADDR	0x4
+#define CFG_SYS_FM1_DTSEC4_PHY_ADDR	0x1
+#define CFG_SYS_FM1_DTSEC5_PHY_ADDR	0x0
 
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR	0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR	0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR	0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR	0x1f
+#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR	0x1c
+#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR	0x1d
+#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR	0x1e
+#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR	0x1f
 
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	0
+#define CFG_SYS_FM1_10GEC1_PHY_ADDR	0
 
-#define CONFIG_SYS_TBIPA_VALUE	8
+#define CFG_SYS_TBIPA_VALUE	8
 #endif
 
 #ifdef CONFIG_MMC
@@ -320,7 +303,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
 
 /*
  * Environment Configuration

diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
index 9629d73..bad34d9 100644
--- a/include/configs/SBx81LIFKW.h
+++ b/include/configs/SBx81LIFKW.h

@@ -7,15 +7,13 @@
 #define _CONFIG_SBX81LIFKW_H
 
 /* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE	0x00000000
 
 /*
  * NS16550 Configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+#define CFG_SYS_NS16550_CLK		CFG_SYS_TCLK
+#define CFG_SYS_NS16550_COM1		KW_UART0_BASE
 
 /*
  * Serial Port configuration
@@ -34,7 +32,7 @@
  * U-Boot bootcode configuration
  */
 
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+#define CFG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
 
 /* size in bytes reserved for initial data */
 

diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h
index 67e42b9..9a9663b 100644
--- a/include/configs/SBx81LIFXCAT.h
+++ b/include/configs/SBx81LIFXCAT.h

@@ -7,15 +7,13 @@
 #define _CONFIG_SBX81LIFXCAT_H
 
 /* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE	0x00000000
 
 /*
  * NS16550 Configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+#define CFG_SYS_NS16550_CLK		CFG_SYS_TCLK
+#define CFG_SYS_NS16550_COM1		KW_UART0_BASE
 
 /*
  * Serial Port configuration
@@ -39,7 +37,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+#define CFG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
 
 /* size in bytes reserved for initial data */
 

diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 62c4177..623d4cf 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h

@@ -15,32 +15,32 @@
 
 /* High Level Configuration Options */
 
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CFG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 #ifdef CONFIG_RAMBOOT_PBL
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0x30000000
+#define CFG_SYS_NAND_U_BOOT_START	0x30000000
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
 #endif
 
 #ifdef CONFIG_SDCARD
 #define CONFIG_RESET_VECTOR_ADDRESS	0x30000FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST	(0x30000000)
+#define CFG_SYS_MMC_U_BOOT_START	(0x30000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #endif
 
 #endif /* CONFIG_RAMBOOT_PBL */
@@ -49,53 +49,51 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-/* PCIe Boot - Master */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 #else
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 #endif
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS	 0x3ffe00000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS	 0x3ffe00000ull
 #else
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 #endif
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE	0x40000 /* 256K */
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE	0x40000 /* 256K */
 /* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET	0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK	0x00000001 /* release core 0 */
+#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET	0xe00e4
+#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK	0x00000001 /* release core 0 */
 
 /* PCIe Boot - Slave */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 /* Set 1M boot space for PCIe boot */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS	\
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS	\
+		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
@@ -103,107 +101,107 @@
 /*
  *  Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#define CFG_SYS_DCSRBAR		0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS		0xf00000000ull
 #endif
 
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 #if defined(CONFIG_TARGET_T1024RDB)
 #define SPD_EEPROM_ADDRESS	0x51
-#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 #elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_SDRAM_SIZE   2048
+#define CFG_SYS_SDRAM_SIZE   2048
 #endif
 
 /*
  * IFC Definitions
  */
-#define CONFIG_SYS_FLASH_BASE	0xe8000000
+#define CFG_SYS_FLASH_BASE	0xe8000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)
 #else
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 
 /* NOR Flash Timing Params */
 #if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CFG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 #elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
+#define CFG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 				CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 #endif
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x0
+#define CFG_SYS_NOR_FTIM3	0x0
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS}
 
 #ifdef CONFIG_TARGET_T1024RDB
 /* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE		0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT		(0xf)
-#define CONFIG_SYS_CSPR2		(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+#define CFG_SYS_CPLD_BASE		0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT		(0xf)
+#define CFG_SYS_CSPR2		(CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
 						| CSPR_PORT_SIZE_8 \
 						| CSPR_MSEL_GPCM \
 						| CSPR_V)
-#define CONFIG_SYS_AMASK2		IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2		0x0
+#define CFG_SYS_AMASK2		IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2		0x0
 
 /* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 						FTIM0_GPCM_TEADC(0x0e) | \
 						FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 						FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 						FTIM2_GPCM_TCH(0x8) | \
 						FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3		0x0
+#define CFG_SYS_CS2_FTIM3		0x0
 #endif
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 #else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 #endif
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
 #if defined(CONFIG_TARGET_T1024RDB)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -211,7 +209,7 @@
 				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 #elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL 3Bytes */ \
@@ -221,91 +219,86 @@
 #endif
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_DDR_LAW		11
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
-#define CONFIG_HWCONFIG
-
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
 #endif
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+#define CFG_SYS_INIT_RAM_SIZE		0x00004000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3	(CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4	(CFG_SYS_CCSRBAR+0x11D600)
 
 /* I2C */
 
@@ -318,9 +311,7 @@
 /*
  * RTC configuration
  */
-#define RTC
-#define CONFIG_RTC_DS1337	1
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CFG_SYS_I2C_RTC_ADDR	0x68
 
 /*
  * eSPI - Enhanced SPI
@@ -334,26 +325,24 @@
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
-#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define	CFG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CFG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CFG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #endif
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CFG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
 #endif
 #endif	/* CONFIG_PCI */
 
@@ -370,40 +359,37 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS	10
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CFG_SYS_BMAN_NUM_PORTALS	10
+#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
 #else
-#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_MEM_PHYS	CFG_SYS_BMAN_MEM_BASE
 #endif
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	10
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CFG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS	10
+#define CFG_SYS_QMAN_MEM_BASE	0xf6000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CFG_SYS_QMAN_MEM_PHYS	0xff6000000ull
 #else
-#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#define CFG_SYS_QMAN_MEM_PHYS	CFG_SYS_QMAN_MEM_BASE
 #endif
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+#define CFG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08
 
-#define CONFIG_SYS_DPAA_FMAN
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -432,7 +418,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 
 /*
  * Environment Configuration

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index ad8037e..b693805 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h

@@ -25,29 +25,29 @@
  * HDR would be appended at end of image and copied to DDR along
  * with U-Boot image.
  */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + \
+#define CFG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + \
 					 CONFIG_U_BOOT_HDR_SIZE)
 #else
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #endif
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
+#define CFG_SYS_NAND_U_BOOT_DST	0x30000000
+#define CFG_SYS_NAND_U_BOOT_START	0x30000000
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
 #endif
 
 #ifdef CONFIG_SDCARD
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST	(0x30000000)
+#define CFG_SYS_MMC_U_BOOT_START	(0x30000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #endif
 
 #endif
@@ -58,12 +58,12 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CFG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
@@ -71,41 +71,41 @@
 /*
  *  Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR		0xFFFC0000
 /*
- * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
- * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
- * (CONFIG_SYS_INIT_L3_VADDR) will be different.
+ * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence
+ * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address
+ * (CFG_SYS_INIT_L3_VADDR) will be different.
  */
-#define CONFIG_SYS_INIT_L3_VADDR	0xFFFC0000
+#define CFG_SYS_INIT_L3_VADDR	0xFFFC0000
 #define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#define CFG_SYS_DCSRBAR		0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS		0xf00000000ull
 
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 #define SPD_EEPROM_ADDRESS	0x51
 
-#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 
 /*
  * IFC Definitions
  */
-#define CONFIG_SYS_FLASH_BASE	0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE	0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)
 
-#define CONFIG_SYS_NOR_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+#define CFG_SYS_NOR_CSPR_EXT	(0xf)
+#define CFG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 
 /*
  * TDM Definition
@@ -113,22 +113,22 @@
 #define T1040_TDM_QUIRK_CCSR_BASE	0xfe000000
 
 /* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x0
+#define CFG_SYS_NOR_FTIM3	0x0
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS}
 
 /* CPLD on IFC */
 #define CPLD_LBMAP_MASK			0x3F
@@ -157,38 +157,38 @@
 #define CPLD_INT_MASK_TDMR2		0x01
 #endif
 
-#define CONFIG_SYS_CPLD_BASE	0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT	(0xf)
-#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CPLD_BASE	0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT	(0xf)
+#define CFG_SYS_CSPR2	(CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
-#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2	0x0
+#define CFG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2	0x0
 /* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3		0x0
+#define CFG_SYS_CS2_FTIM3		0x0
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -197,88 +197,83 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_DDR_LAW		11
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
-#define CONFIG_HWCONFIG
-
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE		0x00004000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3	(CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4	(CFG_SYS_CCSRBAR+0x11D600)
 
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
@@ -290,9 +285,7 @@
 /*
  * RTC configuration
  */
-#define RTC
-#define CONFIG_RTC_DS1337               1
-#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CFG_SYS_I2C_RTC_ADDR         0x68
 
 /*DVI encoder*/
 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
@@ -310,34 +303,30 @@
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
-#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define	CFG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CFG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CFG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #endif
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CFG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
 #endif
 
 /* controller 4, Base address 203000 */
 #ifdef CONFIG_PCIE4
-#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CFG_SYS_PCIE4_MEM_VIRT	0xb0000000
+#define CFG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
 #endif
 #endif	/* CONFIG_PCI */
 
@@ -351,63 +340,57 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS	10
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	10
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
+#define CFG_SYS_BMAN_NUM_PORTALS	10
+#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS	10
+#define CFG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_FMAN_ENET
 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
+#define CFG_SYS_SGMII1_PHY_ADDR             0x03
 #elif defined(CONFIG_TARGET_T1040D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
+#define CFG_SYS_SGMII1_PHY_ADDR             0x01
 #elif defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
-#define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
-#define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
+#define CFG_SYS_SGMII1_PHY_ADDR             0x02
+#define CFG_SYS_SGMII2_PHY_ADDR             0x03
+#define CFG_SYS_SGMII3_PHY_ADDR             0x01
 #endif
 
 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
-#define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
+#define CFG_SYS_RGMII1_PHY_ADDR             0x04
+#define CFG_SYS_RGMII2_PHY_ADDR             0x05
 #else
-#define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
-#define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
+#define CFG_SYS_RGMII1_PHY_ADDR             0x01
+#define CFG_SYS_RGMII2_PHY_ADDR             0x02
 #endif
 
 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
-#define CONFIG_VSC9953
 #ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x04
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x08
+#define CFG_SYS_FM1_QSGMII11_PHY_ADDR	0x04
+#define CFG_SYS_FM1_QSGMII21_PHY_ADDR	0x08
 #else
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x08
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x0c
+#define CFG_SYS_FM1_QSGMII11_PHY_ADDR	0x08
+#define CFG_SYS_FM1_QSGMII21_PHY_ADDR	0x0c
 #endif
 #endif
 #endif
@@ -421,7 +404,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 
 /*
  * Dynamic MTD Partition support with mtdparts

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 2dcaeda..a93e05d 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h

@@ -14,50 +14,44 @@
 #include <linux/stringify.h>
 
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
-#define CONFIG_SRIO1		/* SRIO port 1 */
-#define CONFIG_SRIO2		/* SRIO port 2 */
-#endif
 
 /* High Level Configuration Options */
 
-#define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
+#define CFG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
 
 #ifdef CONFIG_RAMBOOT_PBL
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CFG_SYS_NAND_U_BOOT_START	0x00200000
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
 #endif
 
 #ifdef CONFIG_SDCARD
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST	(0x00200000)
+#define CFG_SYS_MMC_U_BOOT_START	(0x00200000)
+#define CFG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #endif
 
 #endif /* CONFIG_RAMBOOT_PBL */
 
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 
@@ -75,19 +69,19 @@
 /*
  * Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 
-#define CONFIG_SYS_DCSRBAR	0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+#define CFG_SYS_DCSRBAR	0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS	0xf00000000ull
 
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
@@ -96,39 +90,39 @@
 /*
  * IFC Definitions
  */
-#define CONFIG_SYS_FLASH_BASE		0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_FLASH_BASE		0xe0000000
+#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)
+#define CFG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CFG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CFG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x0
+#define CFG_SYS_NOR_FTIM3	0x0
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
-					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
 
 #define QIXIS_BASE			0xffdf0000
 #define QIXIS_LBMAP_SWITCH		6
@@ -147,36 +141,36 @@
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 
-#define CONFIG_SYS_CSPR3_EXT	(0xf)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_EXT	(0xf)
+#define CFG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
-#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3	0x0
+#define CFG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3	0x0
 /* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3		0x0
+#define CFG_SYS_CS3_FTIM3		0x0
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
@@ -185,100 +179,95 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)    | \
 					FTIM0_NAND_TWCHT(0x07)  | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)   | \
 					FTIM1_NAND_TRR(0x0e)    | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
 					FTIM2_NAND_TREH(0x0a)   | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_DDR_LAW		11
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
-#define CONFIG_HWCONFIG
-
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+			((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE	0x00004000
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Serial Port
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
 
 /*
  * I2C
@@ -304,39 +293,39 @@
 /*
  * RapidIO
  */
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+#define CFG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CFG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CFG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CFG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CFG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
 
 /* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 
 /*
  * SRIO_PCIE_BOOT - SLAVE
  */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 
 /*
@@ -348,60 +337,49 @@
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CFG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CFG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
 
 /* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CFG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS	18
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	18
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CFG_SYS_BMAN_NUM_PORTALS	18
+#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG    0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS	18
+#define CFG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -438,7 +416,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 
 /*
  * Environment Configuration

diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 223c8567..cf65a0d 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h

@@ -17,42 +17,41 @@
 
 /* High Level Configuration Options */
 
-#define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
+#define CFG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
 
 #ifdef CONFIG_RAMBOOT_PBL
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CFG_SYS_NAND_U_BOOT_START	0x00200000
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
 #endif
 
 #ifdef CONFIG_SDCARD
 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST      (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_START    (0x00200000)
+#define CFG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
 #endif
 
 #endif /* CONFIG_RAMBOOT_PBL */
 
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 
@@ -70,19 +69,19 @@
 /*
  * Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 
-#define CONFIG_SYS_DCSRBAR	0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+#define CFG_SYS_DCSRBAR	0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS	0xf00000000ull
 
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
@@ -91,68 +90,68 @@
 /*
  * IFC Definitions
  */
-#define CONFIG_SYS_FLASH_BASE		0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_FLASH_BASE		0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)
+#define CFG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 
 /* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CFG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x0
+#define CFG_SYS_NOR_FTIM3	0x0
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS }
 
 /* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE	0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT	(0xf)
-#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+#define CFG_SYS_CPLD_BASE	0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT	(0xf)
+#define CFG_SYS_CSPR2	(CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
-#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2	0x0
+#define CFG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2	0x0
 
 /* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3		0x0
+#define CFG_SYS_CS2_FTIM3		0x0
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
@@ -161,84 +160,79 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)    | \
 					FTIM0_NAND_TWCHT(0x07)  | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)   | \
 					FTIM1_NAND_TRR(0x0e)    | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
 					FTIM2_NAND_TREH(0x0a)   | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_DDR_LAW		11
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
-#define CONFIG_HWCONFIG
-
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+			((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE	0x00004000
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Serial Port
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
 
 /*
  * I2C
@@ -258,39 +252,39 @@
 /*
  * RapidIO
  */
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+#define CFG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CFG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CFG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CFG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CFG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 /*
  * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
 
 /* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 
 /*
  * SRIO_PCIE_BOOT - SLAVE
  */
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 
 /*
@@ -302,60 +296,49 @@
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CFG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CFG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
 
 /* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CFG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS	18
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	18
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CFG_SYS_BMAN_NUM_PORTALS	18
+#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS	18
+#define CFG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -399,7 +382,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 
 /*
  * Environment Configuration

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 12edfdd..b517622 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h

@@ -24,10 +24,10 @@
 
 #ifdef	CONFIG_SDCARD
 #define CONFIG_RESET_VECTOR_ADDRESS	0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_START	0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST	0x00200000
+#define CFG_SYS_MMC_U_BOOT_START	0x00200000
+#define CFG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #endif
 
 #endif
@@ -39,7 +39,7 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CFG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -51,55 +51,51 @@
 /*
  *  Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#define CFG_SYS_DCSRBAR		0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS		0xf00000000ull
 
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 /*
  * IFC Definitions
  */
-#define CONFIG_SYS_FLASH_BASE	0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#define CONFIG_HWCONFIG
+#define CFG_SYS_FLASH_BASE	0xe0000000
+#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)
 
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE		0x00004000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3	(CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4	(CFG_SYS_CCSRBAR+0x11D600)
 
 /* I2C */
 
@@ -109,27 +105,24 @@
  */
 
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CFG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#define CFG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
 
 /* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CFG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CFG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
 
 /*
  * Miscellaneous configurable options
@@ -140,7 +133,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 
 /*
  * Environment Configuration
@@ -159,57 +152,55 @@
 #define SPD_EEPROM_ADDRESS2	0x54
 #define SPD_EEPROM_ADDRESS3	0x56
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 
 /*
  * IFC Definitions
  */
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CFG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 /* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CFG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
 
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x0
+#define CFG_SYS_NOR_FTIM3	0x0
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
-					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
 
 /* NAND Flash on IFC */
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0xf)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
@@ -218,88 +209,87 @@
 				| CSOR_NAND_PB(128))	/*Page Per Block = 128*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_DDR_LAW		11
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
 
 /* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE	0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR3_EXT	(0xf)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CPLD_BASE	0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR3_EXT	(0xf)
+#define CFG_SYS_CSPR3	(CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 
-#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3	0x0
+#define CFG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3	0x0
 
 /* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3		0x0
+#define CFG_SYS_CS3_FTIM3		0x0
 
 /* I2C */
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
@@ -326,36 +316,28 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS	50
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	50
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN
+#define CFG_SYS_BMAN_NUM_PORTALS	50
+#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG    0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS	50
+#define CFG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 8eefaf2..755f7fa 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h

@@ -158,20 +158,17 @@
 #endif
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
-#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
-#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
-#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
-#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
-
-/* PMIC support */
-#define CONFIG_POWER_TPS65910
+#define CFG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CFG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CFG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CFG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CFG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
 
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -179,8 +176,8 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 #endif /* !CONFIG_MTD_RAW_NAND */
 
 /* USB Device Firmware Update support */
@@ -205,8 +202,8 @@
  * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
  */
 #if defined(CONFIG_NOR)
-#define CONFIG_SYS_FLASH_BASE		(0x08000000)
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CFG_SYS_FLASH_BASE		(0x08000000)
+#define CFG_SYS_FLASH_SIZE		0x01000000
 #endif  /* NOR support */
 
 #endif	/* ! __CONFIG_AM335X_EVM_H */

diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h
index 7fa1847..7c5e7ce 100644
--- a/include/configs/am335x_guardian.h
+++ b/include/configs/am335x_guardian.h

@@ -83,15 +83,15 @@
 #define CONSOLE_COLOR_RED 0x001F
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
-#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
-#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
-#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
-#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
-#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+#define CFG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CFG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CFG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CFG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CFG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CFG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS  {   2,   3,   4,   5,   6,   7,   8,   9, \
+#define CFG_SYS_NAND_ECCPOS  {   2,   3,   4,   5,   6,   7,   8,   9, \
 			 10,  11,  12,  13,  14,  15,  16,  17,  18,  19, \
 			 20,  21,  22,  23,  24,  25,  26,  27,  28,  29, \
 			 30,  31,  32,  33,  34,  35,  36,  37,  38,  39, \
@@ -113,8 +113,8 @@
 			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
 			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
 			}
-#define CONFIG_SYS_NAND_ECCSIZE         512
-#define CONFIG_SYS_NAND_ECCBYTES        26
+#define CFG_SYS_NAND_ECCSIZE         512
+#define CFG_SYS_NAND_ECCBYTES        26
 #define MTDIDS_DEFAULT                  "nand0=nand.0"
 
 #endif /* CONFIG_MTD_RAW_NAND */

diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
index 3952783..abd868c 100644
--- a/include/configs/am335x_igep003x.h
+++ b/include/configs/am335x_igep003x.h

@@ -88,14 +88,14 @@
 			"echo WARNING: Could not determine device tree to use; fi; \0"
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CFG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
 
 /* Ethernet support */
 
 /* NAND support */
 
 /* NAND config */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -103,7 +103,7 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 #endif	/* ! __CONFIG_IGEP003X_H */

diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index 08bae9b..452887d 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h

@@ -136,11 +136,11 @@
 #endif /* Regular Boot */
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
-#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
-#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
-#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
-#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
-#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+#define CFG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CFG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CFG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CFG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CFG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CFG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
 
 #endif	/* ! __CONFIG_AM335X_SHC_H */

diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index 7df5f14..342a068 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h

@@ -36,18 +36,11 @@
 	BOOTENV
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
-#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
-#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
-#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
-#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
-
-/* PMIC support */
-#define CONFIG_POWER_TPS65910
-
-/* SPL */
-
-/* Network. */
+#define CFG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CFG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CFG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CFG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CFG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
 
 #endif	/* ! __CONFIG_AM335X_SL50_H */

diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index e0f5f2b..c57a0dd 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h

@@ -16,18 +16,16 @@
 
 /* Board NAND Info. */
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, 10, \
+#define CFG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, 10, \
 					 11, 12, 13, 14, 16, 17, 18, 19, 20, \
 					 21, 22, 23, 24, 25, 26, 27, 28, 30, \
 					 31, 32, 33, 34, 35, 36, 37, 38, 39, \
 					 40, 41, 42, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56 }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	13
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-#define CONFIG_SYS_NAND_MAX_ECCPOS	56
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	13
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 /* NAND block size is 128 KiB.  Synchronize these values with
  * corresponding Device Tree entries in Linux:
  *  MLO(SPL)             4 * NAND_BLOCK_SIZE = 512 KiB  @ 0x000000
@@ -91,7 +89,7 @@
 						/* on one chip */
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#define CFG_SYS_FLASH_BASE		NAND_BASE
 #endif
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index fc82a8c..7659c1c 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h

@@ -9,27 +9,15 @@
 #define __CONFIG_AM43XX_EVM_H
 
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
-#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
 #include <asm/arch/omap.h>
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_CLK		48000000
-#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_REG_SIZE    (-4)
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-/* I2C Configuration */
-
-/* Power */
-#define CONFIG_POWER_TPS65218
-#define CONFIG_POWER_TPS62362
-
-/* SPL defines. */
+#define CFG_SYS_NS16550_CLK		48000000
 
 /* Enabling L2 Cache */
-#define CONFIG_SYS_PL310_BASE	0x48242000
+#define CFG_SYS_PL310_BASE	0x48242000
 
 /*
  * When building U-Boot such that there is no previous loader
@@ -45,7 +33,7 @@
 #define V_SCLK				(V_OSCK)
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
 
 #ifndef CONFIG_SPL_BUILD
 /* USB Device Firmware Update support */
@@ -120,7 +108,7 @@
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
 				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
 				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
 				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@@ -142,8 +130,8 @@
 			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
 			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
 			}
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	26
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	26
 #define NANDARGS \
 	"nandargs=setenv bootargs console=${console} " \
 		"${optargs} " \

diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index d8b0531..dacfd41 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h

@@ -14,13 +14,9 @@
 #include <environment/ti/dfu.h>
 #include <linux/sizes.h>
 
-#define CONFIG_IODELAY_RECALIBRATION
-
-#define CONFIG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2		UART2_BASE	/* UART2 */
-#define CONFIG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
-
-#define CONFIG_SYS_OMAP_ABE_SYSCK
+#define CFG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2		UART2_BASE	/* UART2 */
+#define CFG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
 
 #ifndef CONFIG_SPL_BUILD
 #define DFUARGS \
@@ -55,9 +51,9 @@
  * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
  * 0x9E0000 - 0x2000000 : USERLAND
  */
-#define CONFIG_SYS_SPI_KERNEL_OFFS      0x1E0000
-#define CONFIG_SYS_SPI_ARGS_OFFS        0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE        0x80000
+#define CFG_SYS_SPI_KERNEL_OFFS      0x1E0000
+#define CFG_SYS_SPI_ARGS_OFFS        0x140000
+#define CFG_SYS_SPI_ARGS_SIZE        0x80000
 
 /* SPI SPL */
 

diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h
index 78201ad..57f3f37 100644
--- a/include/configs/am62x_evm.h
+++ b/include/configs/am62x_evm.h

@@ -13,7 +13,7 @@
 #include <environment/ti/mmc.h>
 
 /* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1		0x880000000
+#define CFG_SYS_SDRAM_BASE1		0x880000000
 
 #define PARTS_DEFAULT \
 	/* Linux partitions */ \

diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 1409407..25c71f0 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h

@@ -16,7 +16,7 @@
 #include <environment/ti/k3_dfu.h>
 
 /* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1		0x880000000
+#define CFG_SYS_SDRAM_BASE1		0x880000000
 
 #define PARTS_DEFAULT \
 	/* Linux partitions */ \

diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 0345160..0307426 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h

@@ -15,7 +15,7 @@
 #include <environment/ti/k3_dfu.h>
 
 /* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1		0x880000000
+#define CFG_SYS_SDRAM_BASE1		0x880000000
 
 #define PARTS_DEFAULT \
 	/* Linux partitions */ \

diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 2bda66f..ee0be97 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h

@@ -10,7 +10,7 @@
 
 #define CONFIG_HOSTNAME			"AMCORE"
 
-#define CONFIG_SYS_UART_PORT		0
+#define CFG_SYS_UART_PORT		0
 
 #define CONFIG_EXTRA_ENV_SETTINGS				\
 	"upgrade_uboot=loady; "					\
@@ -24,21 +24,21 @@
 		"erase 0xfff00000 0xffffffff; "			\
 		"cp.b 0x20000 0xfff00000 ${filesize}\0"
 
-#define CONFIG_SYS_CLK			45000000
-#define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 2)
+#define CFG_SYS_CLK			45000000
+#define CFG_SYS_CPU_CLK		(CFG_SYS_CLK * 2)
 /* Register Base Addrs */
-#define CONFIG_SYS_MBAR			0x10000000
+#define CFG_SYS_MBAR			0x10000000
 /* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
 /* size of internal SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CFG_SYS_INIT_RAM_SIZE	0x1000
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		0x1000000
-#define CONFIG_SYS_FLASH_BASE		0xffc00000
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_SIZE		0x1000000
+#define CFG_SYS_FLASH_BASE		0xffc00000
 
 /* amcore design has flash data bytes wired swapped */
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
 /* reserve 128-4KB */
 
 #define LDS_BOARD_TEXT \
@@ -46,7 +46,7 @@
 	env/embedded.o(.text*);
 
 /* memory map space for linux boot data */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+#define CFG_SYS_BOOTMAPSZ		(8 << 20)
 
 /*
  * Cache Configuration
@@ -56,25 +56,25 @@
  * sdram - single region - no masks
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0		(CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV           (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0		(CF_ACR_CM_WT | CF_ACR_SM_ALL | \
 					 CF_ACR_EN)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_DCM_P | CF_CACR_ESB | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_DCM_P | CF_CACR_ESB | \
 					 CF_CACR_EC)
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CONFIG_SYS_CS0_BASE		(CONFIG_SYS_FLASH_BASE>>16)
+#define	CFG_SYS_CS0_BASE		(CFG_SYS_FLASH_BASE>>16)
 /* 4MB, AA=0,V=1  C/I BIT for errata */
-#define	CONFIG_SYS_CS0_MASK		0x003f0001
+#define	CFG_SYS_CS0_MASK		0x003f0001
 /* WS=10, AA=1, PS=16bit (10) */
-#define	CONFIG_SYS_CS0_CTRL		0x1980
+#define	CFG_SYS_CS0_CTRL		0x1980
 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
-#define CONFIG_SYS_CS1_BASE		0x3000
-#define CONFIG_SYS_CS1_MASK		0x00070001
-#define CONFIG_SYS_CS1_CTRL		0x0100
+#define CFG_SYS_CS1_BASE		0x3000
+#define CFG_SYS_CS1_MASK		0x00070001
+#define CFG_SYS_CS1_CTRL		0x0100
 
 #endif  /* __AMCORE_CONFIG_H */

diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 650140b..9c6f763 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h

@@ -6,10 +6,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CFG_SYS_SDRAM_BASE           0x80000000
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x8000
+#define CFG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE        0x8000
 
 /* Miscellaneous configurable options */
 

diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 0eed8db..034cd7a 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h

@@ -6,15 +6,15 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CFG_SYS_SDRAM_BASE           0x80000000
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x2000
+#define CFG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE        0x2000
 
 /*
  * Serial Port
  */
-#define CONFIG_SYS_NS16550_CLK          25000000
+#define CFG_SYS_NS16550_CLK          25000000
 
 /* Miscellaneous configurable options */
 

diff --git a/include/configs/ap152.h b/include/configs/ap152.h
index 7124711..c56b351 100644
--- a/include/configs/ap152.h
+++ b/include/configs/ap152.h

@@ -6,15 +6,15 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CFG_SYS_SDRAM_BASE           0x80000000
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x2000
+#define CFG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE        0x2000
 
 /*
  * Serial Port
  */
-#define CONFIG_SYS_NS16550_CLK          25000000
+#define CFG_SYS_NS16550_CLK          25000000
 
 /* Miscellaneous configurable options */
 

diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index e2e491b..cf23837 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h

@@ -63,7 +63,7 @@
 /* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
 #define CFG_SYS_FSL_USDHC_NUM	3
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #define PHYS_SDRAM_1_SIZE		SZ_2G		/* 2 GB */

diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 6a4092a..f0a02ae 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h

@@ -14,7 +14,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define FDT_MODULE			"apalis-v1.2"
 #define FDT_MODULE_V1_0			"apalis"

diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 192c9cf..a3c8654 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h

@@ -15,10 +15,6 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/mach-imx/gpio.h>
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* MMC Configs */
@@ -36,8 +32,6 @@
 #define CONFIG_USBD_HS
 
 /* Framebuffer and LCD */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
 
 /* Command definition */
 
@@ -110,8 +104,8 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #endif	/* __CONFIG_H */

diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 84bd88f..4f00b3b 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h

@@ -21,7 +21,7 @@
  * Apalis UART4: NVIDIA UARTC
  */
 #define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define UBOOT_UPDATE \
 	"uboot_hwpart=1\0" \

diff --git a/include/configs/arbel.h b/include/configs/arbel.h
index f7deba4..60758b0 100644
--- a/include/configs/arbel.h
+++ b/include/configs/arbel.h

@@ -6,10 +6,10 @@
 #ifndef __CONFIG_ARBEL_H
 #define __CONFIG_ARBEL_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x0
-#define CONFIG_SYS_BOOTMAPSZ		(20 << 20)
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE	0x8000
+#define CFG_SYS_SDRAM_BASE		0x0
+#define CFG_SYS_BOOTMAPSZ		(20 << 20)
+#define CFG_SYS_INIT_RAM_ADDR	CFG_SYS_SDRAM_BASE
+#define CFG_SYS_INIT_RAM_SIZE	0x8000
 
 /* Default environemnt variables */
 #define CONFIG_EXTRA_ENV_SETTINGS   "uimage_flash_addr=80200000\0"   \

diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 1f2b3b5..6faf544 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h

@@ -20,7 +20,7 @@
 #endif
 
 /* Framebuffer */
-#define CONFIG_SYS_LDB_CLOCK	28341000
+#define CFG_SYS_LDB_CLOCK	28341000
 
 #include "mx6_common.h"
 
@@ -30,8 +30,6 @@
 
 #define CONFIG_FEC_MXC_PHYADDR		0
 
-#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-
 #ifdef CONFIG_IMX_HAB
 #define HAB_EXTRA_SETTINGS \
 	"hab_check_addr=" \
@@ -408,9 +406,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #define CFG_SYS_FSL_USDHC_NUM	2
 
@@ -422,12 +420,6 @@
 
 /* UBI support */
 
-/* Framebuffer */
-/* check this console not needed, after test remove it */
-#define CONFIG_IMX_VIDEO_SKIP
-
-#define CONFIG_IMX6_PWM_PER_CLK	66000000
-
 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \
 		"sysnum:dw,panel:sw,ipaddr:iw,serverip:iw"
 

diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
index 5c90058..bb1bd50 100644
--- a/include/configs/aspeed-common.h
+++ b/include/configs/aspeed-common.h

@@ -14,14 +14,14 @@
 
 /* Misc CPU related */
 
-#define CONFIG_SYS_SDRAM_BASE		ASPEED_DRAM_BASE
+#define CFG_SYS_SDRAM_BASE		ASPEED_DRAM_BASE
 
 #ifdef CONFIG_PRE_CON_BUF_SZ
-#define CONFIG_SYS_INIT_RAM_ADDR	(ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
-#define CONFIG_SYS_INIT_RAM_SIZE	(ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
+#define CFG_SYS_INIT_RAM_ADDR	(ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
+#define CFG_SYS_INIT_RAM_SIZE	(ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
 #else
-#define CONFIG_SYS_INIT_RAM_ADDR	(ASPEED_SRAM_BASE)
-#define CONFIG_SYS_INIT_RAM_SIZE	(ASPEED_SRAM_SIZE)
+#define CFG_SYS_INIT_RAM_ADDR	(ASPEED_SRAM_BASE)
+#define CFG_SYS_INIT_RAM_SIZE	(ASPEED_SRAM_SIZE)
 #endif
 
 /*

diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 58635df..62aa993 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h

@@ -55,31 +55,21 @@
  * interface etc.
  */
 
-#define CONFIG_SYS_CLK			80000000
-#define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 3)
-#define CONFIG_SYS_SDRAM_SIZE		32		/* SDRAM size in MB */
+#define CFG_SYS_CLK			80000000
+#define CFG_SYS_CPU_CLK		(CFG_SYS_CLK * 3)
+#define CFG_SYS_SDRAM_SIZE		32		/* SDRAM size in MB */
 
 /*
  * Define baudrate for UART1 (console output, tftp, ...)
  * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
- * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
+ * CFG_SYS_BAUDRATE_TABLE defines values that can be selected
  * in u-boot command interface
  */
 
-#define CONFIG_SYS_UART_PORT		(2)
-#define CONFIG_SYS_UART2_ALT3_GPIO
+#define CFG_SYS_UART_PORT		(2)
+#define CFG_SYS_UART2_ALT3_GPIO
 
 /*
- * Watchdog configuration; Watchdog is disabled for running from RAM
- * and set to highest possible value else. Beware there is no check
- * in the watchdog code to validate the timeout value set here!
- */
-
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_WATCHDOG_TIMEOUT 3355	/* timeout in milliseconds */
-#endif
-
-/*
  * Configuration for environment
  * Environment is located in the last sector of the flash
  */
@@ -125,7 +115,7 @@
  * it needs non-blocking CFI routines.
  */
 
-#define CONFIG_SYS_FPGA_WAIT		1000
+#define CFG_SYS_FPGA_WAIT		1000
 
 /* End of user parameters to be customized */
 
@@ -139,26 +129,26 @@
 
 /* Base register address */
 
-#define CONFIG_SYS_MBAR		0xFC000000	/* Register Base Addrs */
+#define CFG_SYS_MBAR		0xFC000000	/* Register Base Addrs */
 
 /* System Conf. Reg. & System Protection Reg. */
 
-#define CONFIG_SYS_SCR		0x0003;
-#define CONFIG_SYS_SPR		0xffff;
+#define CFG_SYS_SCR		0x0003;
+#define CFG_SYS_SPR		0xffff;
 
 /*
  * Definitions for initial stack pointer and data area (in internal SRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE		0x8000
-#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CFG_SYS_INIT_RAM_ADDR	0x80000000
+#define CFG_SYS_INIT_RAM_SIZE		0x8000
+#define CFG_SYS_INIT_RAM_CTRL	0x221
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
  */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 /*
  * Chipselect bank definitions
@@ -170,23 +160,23 @@
  * CS4 - unused
  * CS5 - unused
  */
-#define CONFIG_SYS_CS0_BASE		0
-#define CONFIG_SYS_CS0_MASK		0x00ff0001
-#define CONFIG_SYS_CS0_CTRL		0x00001fc0
+#define CFG_SYS_CS0_BASE		0
+#define CFG_SYS_CS0_MASK		0x00ff0001
+#define CFG_SYS_CS0_CTRL		0x00001fc0
 
-#define CONFIG_SYS_CS1_BASE		0x01000000
-#define CONFIG_SYS_CS1_MASK		0x00ff0001
-#define CONFIG_SYS_CS1_CTRL		0x00001fc0
+#define CFG_SYS_CS1_BASE		0x01000000
+#define CFG_SYS_CS1_MASK		0x00ff0001
+#define CFG_SYS_CS1_CTRL		0x00001fc0
 
-#define CONFIG_SYS_CS2_BASE		0x20000000
-#define CONFIG_SYS_CS2_MASK		0x00ff0001
-#define CONFIG_SYS_CS2_CTRL		0x0000fec0
+#define CFG_SYS_CS2_BASE		0x20000000
+#define CFG_SYS_CS2_MASK		0x00ff0001
+#define CFG_SYS_CS2_CTRL		0x0000fec0
 
-#define CONFIG_SYS_CS3_BASE		0x21000000
-#define CONFIG_SYS_CS3_MASK		0x00ff0001
-#define CONFIG_SYS_CS3_CTRL		0x0000fec0
+#define CFG_SYS_CS3_BASE		0x21000000
+#define CFG_SYS_CS3_MASK		0x00ff0001
+#define CFG_SYS_CS3_CTRL		0x0000fec0
 
-#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CFG_SYS_FLASH_BASE		0x00000000
 
 /* Reserve 256 kB for Monitor */
 
@@ -195,12 +185,12 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + \
-						(CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + \
+						(CFG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
 
-#define CONFIG_SYS_FLASH_SIZE		0x2000000
+#define CFG_SYS_FLASH_SIZE		0x2000000
 
 #define LDS_BOARD_TEXT \
 	. = DEFINED(env_offset) ? env_offset : .; \
@@ -208,15 +198,15 @@
 
 /* Cache Configuration */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
 					 CF_CACR_DCM_P)
 
 #endif	/* _CONFIG_ASTRO_MCF5373L_H */

diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 4631acf..4aa876a 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h

@@ -12,7 +12,7 @@
 #include <linux/kconfig.h>
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK      32768
+#define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
 
 #endif

diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index d51da9d..b9cc7ba 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h

@@ -24,34 +24,33 @@
  */
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
 
 /*
  * SDRAM: 1 bank, min 32, max 128 MB
  * Initialized before u-boot gets started.
  */
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+#define CFG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE		0x04000000
 
-#define CONFIG_SYS_INIT_RAM_SIZE	(16 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE	(16 * 1024)
 #ifdef CONFIG_AT91SAM9XE
-# define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM
+# define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM
 #else
-# define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
+# define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
 #endif
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PC13
 #endif
 
 /* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
 
 #endif

diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 5dc8f21..56247e3 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h

@@ -11,27 +11,26 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */
 
 #include <asm/hardware.h>
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x04000000
-#define CONFIG_SYS_INIT_RAM_SIZE	(16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x04000000
+#define CFG_SYS_INIT_RAM_SIZE	(16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			0x40000000
-#define CONFIG_SYS_NAND_DBW_8
+#define CFG_SYS_NAND_BASE			0x40000000
 /* our ALE is AD22 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC15
+#define CFG_SYS_NAND_MASK_CLE		(1 << 21)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PC15
 
 #endif
 
@@ -43,6 +42,6 @@
 #define CONFIG_DM9000_NO_SROM
 
 /* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
 
 #endif

diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index d31a774..afdb747 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h

@@ -19,20 +19,20 @@
 #include <asm/hardware.h>
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CFG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+#define CFG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE		0x04000000
 
-#define CONFIG_SYS_INIT_RAM_SIZE	(16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE	(16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
 
 /* NOR flash, if populated */
 #ifdef CONFIG_SYS_USE_NORFLASH
 #define PHYS_FLASH_1				0x10000000
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE			PHYS_FLASH_1
 
 /* Address and size of Primary Environment Sector */
 
@@ -50,9 +50,9 @@
 #define MASTER_PLL_OUT		3
 
 /* clocks */
-#define CONFIG_SYS_MOR_VAL						\
+#define CFG_SYS_MOR_VAL						\
 		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
-#define CONFIG_SYS_PLLAR_VAL					\
+#define CFG_SYS_PLLAR_VAL					\
 	(AT91_PMC_PLLAR_29 |					\
 	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
 	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
@@ -60,31 +60,31 @@
 	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
 
 /* PCK/2 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR1_VAL		\
+#define	CFG_SYS_MCKR1_VAL		\
 	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
 	 AT91_PMC_MCKR_MDIV_2)
 
 /* PCK/2 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR2_VAL		\
+#define	CFG_SYS_MCKR2_VAL		\
 	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |	\
 	AT91_PMC_MCKR_MDIV_2)
 
 /* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+#define CFG_SYS_PIOD_PDR_VAL1	0xFFFF0000
 /* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+#define CFG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL					\
+#define CFG_SYS_MATRIX_EBICSA_VAL					\
 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
 	 AT91_MATRIX_CSA_EBI_CS1A)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1		0
+#define CFG_SYS_SDRC_MR_VAL1		0
 /* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
+#define CFG_SYS_SDRC_TR_VAL1		0x13C
 /* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL							\
+#define CFG_SYS_SDRC_CR_VAL							\
 		(AT91_SDRAMC_NC_9 |						\
 		 AT91_SDRAMC_NR_13 |						\
 		 AT91_SDRAMC_NB_4 |						\
@@ -98,47 +98,47 @@
 		 (1 << 28))		/* Exit Self Refresh to Active Delay */
 
 /* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CFG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
 
 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL				\
+#define CFG_SYS_SMC0_SETUP0_VAL				\
 	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
 	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL				\
+#define CFG_SYS_SMC0_PULSE0_VAL				\
 	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
 	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+#define CFG_SYS_SMC0_CYCLE0_VAL	\
 	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL				\
+#define CFG_SYS_SMC0_MODE0_VAL				\
 	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
 	 AT91_SMC_MODE_DBW_16 |					\
 	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
 
 /* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL			\
+#define CFG_SYS_RSTC_RMR_VAL			\
 		(AT91_RSTC_KEY |		\
 		AT91_RSTC_MR_URSTEN |		\
 		AT91_RSTC_MR_ERSTL(15))
 
 /* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL				\
+#define CFG_SYS_WDTC_WDMR_VAL				\
 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
 		 AT91_WDT_MR_WDV(0xfff) |			\
 		 AT91_WDT_MR_WDDIS |				\
@@ -150,17 +150,16 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8			1
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PA22
 #endif
 
 /* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
 
 #endif

diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 0108547..2ceb806 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h

@@ -11,40 +11,39 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK      32768
+#define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           0x70000000
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CFG_SYS_SDRAM_BASE           0x70000000
+#define CFG_SYS_SDRAM_SIZE		0x08000000
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PC8
 
 #endif
 
 #ifdef CONFIG_SD_BOOT
 #elif CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x80000
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 #endif
 
-#define CONFIG_SYS_MASTER_CLOCK		132096000
-#define CONFIG_SYS_AT91_PLLA		0x20c73f03
-#define CONFIG_SYS_MCKR			0x1301
-#define CONFIG_SYS_MCKR_CSS		0x1302
+#define CFG_SYS_MASTER_CLOCK		132096000
+#define CFG_SYS_AT91_PLLA		0x20c73f03
+#define CFG_SYS_MCKR			0x1301
+#define CFG_SYS_MCKR_CSS		0x1302
 
 #endif

diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 00f5774..0f9e2cf 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h

@@ -10,22 +10,22 @@
 #define __AT91SAM9N12_CONFIG_H_
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000	/* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	16000000	/* main clock xtal */
 
 /* Misc CPU related */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x08000000
 
 /* DataFlash */
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(4)
-#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
+#define CFG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(4)
+#define CFG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
 #endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
@@ -35,9 +35,9 @@
 
 /* SPL */
 
-#define CONFIG_SYS_MASTER_CLOCK		132096000
-#define CONFIG_SYS_AT91_PLLA		0x20953f03
-#define CONFIG_SYS_MCKR			0x1301
-#define CONFIG_SYS_MCKR_CSS		0x1302
+#define CFG_SYS_MASTER_CLOCK		132096000
+#define CFG_SYS_AT91_PLLA		0x20953f03
+#define CFG_SYS_MCKR			0x1301
+#define CFG_SYS_MCKR_CSS		0x1302
 
 #endif

diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index c60c248..cad00f6 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h

@@ -13,26 +13,25 @@
 #include <asm/hardware.h>
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	12000000	/* main clock xtal */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+#define CFG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE		0x04000000
 
-#define CONFIG_SYS_INIT_RAM_SIZE	(16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM
+#define CFG_SYS_INIT_RAM_SIZE	(16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8			1
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PB6
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PD17
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PB6
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PD17
 
 #endif
 

diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 71a2863..509c458 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h

@@ -9,8 +9,8 @@
 #define __CONFIG_H__
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768
+#define CFG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
 
 /* general purpose I/O */
 
@@ -20,28 +20,27 @@
  */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */
 
 /* DataFlash */
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8		1
+#define CFG_SYS_NAND_BASE		0x40000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PD5
 #endif
 
 /* SPL */
 
-#define CONFIG_SYS_MASTER_CLOCK		132096000
-#define CONFIG_SYS_AT91_PLLA		0x20c73f03
-#define CONFIG_SYS_MCKR			0x1301
-#define CONFIG_SYS_MCKR_CSS		0x1302
+#define CFG_SYS_MASTER_CLOCK		132096000
+#define CFG_SYS_AT91_PLLA		0x20c73f03
+#define CFG_SYS_MCKR			0x1301
+#define CFG_SYS_MCKR_CSS		0x1302
 
 #endif

diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index cf5125f..03e04e6 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h

@@ -28,30 +28,26 @@
 	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
 #define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_0
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM_0
 
 /*
  * Serial console configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#endif
-#define CONFIG_SYS_NS16550_CLK		19660800
+#define CFG_SYS_NS16550_CLK		19660800
 
 /* Init Stack Pointer */
 
 /* support JEDEC */
 #define PHYS_FLASH_1			0x88000000	/* BANK 0 */
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CFG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CFG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
 
 /* max number of memory banks */
 /*
  * There are 4 banks supported for this Controller,
  * but we have only 1 bank connected to flash on board
 */
-#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
+#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000}
 
 /* max number of sectors on one chip */
 #define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
@@ -67,7 +63,7 @@
  */
 
 /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)
 /* Increase max gunzip size */
 
 /* Support autoboot from RAM (kernel image is loaded via debug port) */

diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h
index f2357b5..04dc50b 100644
--- a/include/configs/axs10x.h
+++ b/include/configs/axs10x.h

@@ -19,16 +19,14 @@
  * Memory configuration
  */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE		SZ_512M
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE		SZ_512M
 
 /*
  * UART configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		33333333
-#define CONFIG_SYS_NS16550_MEM32
+#define CFG_SYS_NS16550_CLK		33333333
 
 /*
  * Ethernet PHY configuration

diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index f4161d7..6f6552e 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h

@@ -181,21 +181,18 @@
 	/*DFUARGS*/
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
-#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
-#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
-#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
-#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
-
-/* PMIC support */
-#define CONFIG_POWER_TPS65910
+#define CFG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CFG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CFG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CFG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CFG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
 
 /* SPL */
 #ifndef CONFIG_NOR_BOOT
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -203,9 +200,9 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 #endif
 #endif
 

diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h
index 1bae49e..43edc91 100644
--- a/include/configs/bcm7260.h
+++ b/include/configs/bcm7260.h

@@ -10,9 +10,9 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_NS16550_COM1	0xf040c000
+#define CFG_SYS_NS16550_COM1	0xf040c000
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x10200000
+#define CFG_SYS_INIT_RAM_ADDR	0x10200000
 
 #include "bcmstb.h"
 

diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h
index 4b41dc2..1143372 100644
--- a/include/configs/bcm7445.h
+++ b/include/configs/bcm7445.h

@@ -10,9 +10,9 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_NS16550_COM1	0xf040ab00
+#define CFG_SYS_NS16550_COM1	0xf040ab00
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80200000
+#define CFG_SYS_INIT_RAM_ADDR	0x80200000
 
 #include "bcmstb.h"
 

diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h
index d0c46a2..b02ed1b 100644
--- a/include/configs/bcm947622.h
+++ b/include/configs/bcm947622.h

@@ -6,7 +6,7 @@
 #ifndef __BCM947622_H
 #define __BCM947622_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #define COUNTER_FREQUENCY		50000000
 #endif

diff --git a/include/configs/bcm94908.h b/include/configs/bcm94908.h
index 1346ace..246feb6 100644
--- a/include/configs/bcm94908.h
+++ b/include/configs/bcm94908.h

@@ -6,6 +6,6 @@
 #ifndef __BCM94908_H
 #define __BCM94908_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm94912.h b/include/configs/bcm94912.h
index f3d17dd..c428b1a 100644
--- a/include/configs/bcm94912.h
+++ b/include/configs/bcm94912.h

@@ -6,6 +6,6 @@
 #ifndef __BCM94912_H
 #define __BCM94912_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h
index 361569a..c61acf6 100644
--- a/include/configs/bcm963138.h
+++ b/include/configs/bcm963138.h

@@ -6,7 +6,7 @@
 #ifndef __BCM963138_H
 #define __BCM963138_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_HZ_CLOCK		500000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_HZ_CLOCK		500000000
 
 #endif

diff --git a/include/configs/bcm963146.h b/include/configs/bcm963146.h
index edbdfc3..90dfa98 100644
--- a/include/configs/bcm963146.h
+++ b/include/configs/bcm963146.h

@@ -6,6 +6,6 @@
 #ifndef __BCM963146_H
 #define __BCM963146_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm963148.h b/include/configs/bcm963148.h
index 5a24ccc..54f6750 100644
--- a/include/configs/bcm963148.h
+++ b/include/configs/bcm963148.h

@@ -6,6 +6,6 @@
 #ifndef __BCM963148_H
 #define __BCM963148_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm963158.h b/include/configs/bcm963158.h
index b15c411..2fdd22d 100644
--- a/include/configs/bcm963158.h
+++ b/include/configs/bcm963158.h

@@ -6,6 +6,6 @@
 #ifndef __BCM963158_H
 #define __BCM963158_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm963178.h b/include/configs/bcm963178.h
index b25f6a1..32fc4a5 100644
--- a/include/configs/bcm963178.h
+++ b/include/configs/bcm963178.h

@@ -6,6 +6,6 @@
 #ifndef __BCM963178_H
 #define __BCM963178_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm96756.h b/include/configs/bcm96756.h
index c8f3267..c69d177 100644
--- a/include/configs/bcm96756.h
+++ b/include/configs/bcm96756.h

@@ -6,6 +6,6 @@
 #ifndef __BCM96756_H
 #define __BCM96756_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm96813.h b/include/configs/bcm96813.h
index 5d9e87b..37d2d91 100644
--- a/include/configs/bcm96813.h
+++ b/include/configs/bcm96813.h

@@ -6,6 +6,6 @@
 #ifndef __BCM96813_H
 #define __BCM96813_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm96846.h b/include/configs/bcm96846.h
index 1d6d5d6..581fd55 100644
--- a/include/configs/bcm96846.h
+++ b/include/configs/bcm96846.h

@@ -6,6 +6,6 @@
 #ifndef __BCM96846_H
 #define __BCM96846_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h
index 6e420f2..3fb1ab9 100644
--- a/include/configs/bcm96855.h
+++ b/include/configs/bcm96855.h

@@ -6,6 +6,6 @@
 #ifndef __BCM96855_H
 #define __BCM96855_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm96856.h b/include/configs/bcm96856.h
index a7ae71e..5f5af32 100644
--- a/include/configs/bcm96856.h
+++ b/include/configs/bcm96856.h

@@ -6,6 +6,6 @@
 #ifndef __BCM96856_H
 #define __BCM96856_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h
index 4e584b4..9a0d89a 100644
--- a/include/configs/bcm96858.h
+++ b/include/configs/bcm96858.h

@@ -6,6 +6,6 @@
 #ifndef __BCM96858_H
 #define __BCM96858_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm96878.h b/include/configs/bcm96878.h
index 3e23e94..7702d1f 100644
--- a/include/configs/bcm96878.h
+++ b/include/configs/bcm96878.h

@@ -6,6 +6,6 @@
 #ifndef __BCM96878_H
 #define __BCM96878_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #endif

diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h
index 795de46..b546988 100644
--- a/include/configs/bcm_ns3.h
+++ b/include/configs/bcm_ns3.h

@@ -15,7 +15,7 @@
 #define V2M_BASE			0x80000000
 #define PHYS_SDRAM_1			V2M_BASE
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 /*
  * Initial SP before reloaction is placed at end of first DRAM bank,
@@ -26,7 +26,7 @@
 /* 12MB Malloc size */
 
 /* console configuration */
-#define CONFIG_SYS_NS16550_CLK		25000000
+#define CFG_SYS_NS16550_CLK		25000000
 
 /*
  * Increase max uncompressed/gunzip size, keeping size same as EMMC linux

diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h
index 5aa720d..57360b6 100644
--- a/include/configs/bcmstb.h
+++ b/include/configs/bcmstb.h

@@ -81,8 +81,8 @@
  * MiB.  However, BOLT can be configured to allow loading larger
  * initramfs images, in which case this limitation is eliminated.
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x100000
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_INIT_RAM_SIZE	0x100000
 
 /*
  * CONFIG_SYS_LOAD_ADDR - 1 MiB.
@@ -97,14 +97,12 @@
  */
 #define V_NS16550_CLK			81000000
 
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CFG_SYS_NS16550_CLK		V_NS16550_CLK
 
 /*
  * Serial console configuration.
  */
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
 					 115200}
 
 /*

diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index 1d51bb4..6b5f650 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h

@@ -18,7 +18,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 /* SPI */
 #define CONFIG_TEGRA_SLINK_CTRLS       6

diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h
index 829e816..556bfa0 100644
--- a/include/configs/bitmain_antminer_s9.h
+++ b/include/configs/bitmain_antminer_s9.h

@@ -6,8 +6,8 @@
 #ifndef __CONFIG_BITMAIN_ANTMINER_S9_H
 #define __CONFIG_BITMAIN_ANTMINER_S9_H
 
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_SIZE	0x40000000
+#define CFG_SYS_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_SIZE	0x40000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"pxefile_addr_r=0x2000000\0" \

diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index ca2bc19..0842a4a 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h

@@ -199,8 +199,8 @@
 #define PHYS_SDRAM			(0x80000000)
 #define PHYS_SDRAM_SIZE		(SZ_512M)
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/blanche.h b/include/configs/blanche.h
index 0b1fc91..cb28ae2 100644
--- a/include/configs/blanche.h
+++ b/include/configs/blanche.h

@@ -26,10 +26,10 @@
 #define CONFIG_SH_QSPI_BASE	0xE6B10000
 #else
 #define CONFIG_FLASH_SHOW_PROGRESS	45
-#define CONFIG_SYS_FLASH_BASE		0x00000000
-#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+#define CFG_SYS_FLASH_BASE		0x00000000
+#define CFG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CFG_SYS_FLASH_BANKS_LIST	{ (CFG_SYS_FLASH_BASE) }
+#define CFG_SYS_FLASH_BANKS_SIZES	{ (CFG_SYS_FLASH_SIZE) }
 #endif
 
 /* Board Clock */

diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h
index c328f41..0d254cd 100644
--- a/include/configs/bmips_bcm3380.h
+++ b/include/configs/bmips_bcm3380.h

@@ -9,12 +9,12 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
 #endif /* __CONFIG_BMIPS_BCM3380_H */

diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h
index d16d50e..7865b9c 100644
--- a/include/configs/bmips_bcm6318.h
+++ b/include/configs/bmips_bcm6318.h

@@ -9,12 +9,12 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
 #endif /* __CONFIG_BMIPS_BCM6318_H */

diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
index f69c46b..93426d2 100644
--- a/include/configs/bmips_bcm63268.h
+++ b/include/configs/bmips_bcm63268.h

@@ -9,12 +9,12 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
 #endif /* __CONFIG_BMIPS_BCM63268_H */

diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
index acd021e..e992fe6 100644
--- a/include/configs/bmips_bcm6328.h
+++ b/include/configs/bmips_bcm6328.h

@@ -9,12 +9,12 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
 #endif /* __CONFIG_BMIPS_BCM6328_H */

diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h
index fa9e5f0..224b697 100644
--- a/include/configs/bmips_bcm6338.h
+++ b/include/configs/bmips_bcm6338.h

@@ -9,14 +9,14 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
-#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CFG_SYS_FLASH_BASE			0xbfc00000
 
 #endif /* __CONFIG_BMIPS_BCM6338_H */

diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
index bcf5c87..3211d23 100644
--- a/include/configs/bmips_bcm6348.h
+++ b/include/configs/bmips_bcm6348.h

@@ -9,14 +9,14 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
-#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CFG_SYS_FLASH_BASE			0xbfc00000
 
 #endif /* __CONFIG_BMIPS_BCM6348_H */

diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h
index e31b8bc..7e2449c 100644
--- a/include/configs/bmips_bcm6358.h
+++ b/include/configs/bmips_bcm6358.h

@@ -9,14 +9,14 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
-#define CONFIG_SYS_FLASH_BASE			0xbe000000
+#define CFG_SYS_FLASH_BASE			0xbe000000
 
 #endif /* __CONFIG_BMIPS_BCM6358_H */

diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h
index 6e707d3..443ee47 100644
--- a/include/configs/bmips_bcm6362.h
+++ b/include/configs/bmips_bcm6362.h

@@ -9,12 +9,12 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
 #endif /* __CONFIG_BMIPS_BCM6362_H */

diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h
index bb72c8c..c550f97 100644
--- a/include/configs/bmips_bcm6368.h
+++ b/include/configs/bmips_bcm6368.h

@@ -9,14 +9,14 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
-#define CONFIG_SYS_FLASH_BASE			0xb8000000
+#define CFG_SYS_FLASH_BASE			0xb8000000
 
 #endif /* __CONFIG_BMIPS_BCM6368_H */

diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h
index a1c992b..f212914 100644
--- a/include/configs/bmips_bcm6838.h
+++ b/include/configs/bmips_bcm6838.h

@@ -9,12 +9,12 @@
 #include <linux/sizes.h>
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* U-Boot */
 
 #if defined(CONFIG_BMIPS_BOOT_RAM)
-#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#define CFG_SYS_INIT_SP_OFFSET	SZ_8K
 #endif
 
 #endif /* __CONFIG_BMIPS_BCM6838_H */

diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h
index 7e358a6..3cdd0e4 100644
--- a/include/configs/bmips_common.h
+++ b/include/configs/bmips_common.h

@@ -9,7 +9,7 @@
 #include <linux/sizes.h>
 
 /* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
 					  230400, 500000, 1500000 }
 
 #endif /* __CONFIG_BMIPS_COMMON_H */

diff --git a/include/configs/boston.h b/include/configs/boston.h
index a09e831..14ce8a4 100644
--- a/include/configs/boston.h
+++ b/include/configs/boston.h

@@ -22,12 +22,12 @@
  * Memory map
  */
 #ifdef CONFIG_64BIT
-# define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
+# define CFG_SYS_SDRAM_BASE		0xffffffff80000000
 #else
-# define CONFIG_SYS_SDRAM_BASE		0x80000000
+# define CFG_SYS_SDRAM_BASE		0x80000000
 #endif
 
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CFG_SYS_INIT_SP_OFFSET	0x400000
 
 /*
  * Console

diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h
index 0c7fe5f..d35c7c4 100644
--- a/include/configs/brppt2.h
+++ b/include/configs/brppt2.h

@@ -13,7 +13,7 @@
 
 /* -- i.mx6 specifica -- */
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE		L2_PL310_BASE
+#define CFG_SYS_PL310_BASE		L2_PL310_BASE
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
 
 #define CONFIG_MXC_GPT_HCLK
@@ -76,9 +76,9 @@
 
 /* RAM */
 #define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Ethernet */
 #define CONFIG_FEC_FIXED_SPEED		_1000BASET
@@ -86,9 +86,4 @@
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 
-/* SPL */
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-
-#endif	/* CONFIG_SPL */
 #endif	/* __CONFIG_BRPP2_IMX6_H */

diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index a6de28a..3e0b425 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h

@@ -14,17 +14,15 @@
 
 /* legacy #defines for non DM bur-board */
 #ifndef CONFIG_DM
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		(48000000)
-#define CONFIG_SYS_NS16550_COM1		0x44e09000
+#define CFG_SYS_NS16550_CLK		(48000000)
+#define CFG_SYS_NS16550_COM1		0x44e09000
 
 #endif /* CONFIG_DM */
 
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 
 /* Timer information */
-#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
 #include <asm/arch/omap.h>
 
@@ -47,7 +45,7 @@
  * always, even when we have more.  We always start at 0x80000000,
  * and we place the initial stack pointer in our SRAM.
  */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /*
  * Our platforms make use of SPL to initalize the hardware (primarily

diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h
index c4110f8..474ad69 100644
--- a/include/configs/capricorn-common.h
+++ b/include/configs/capricorn-common.h

@@ -92,7 +92,7 @@
 
 /* On CCP board, USDHC1 is for eMMC */
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 /* DDR3 board total DDR is 1 GB */

diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index f3416b5..35c5a4f 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h

@@ -22,7 +22,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 /* SPI */
 #define CONFIG_TEGRA_SLINK_CTRLS       6

diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h
index 0672b7d..55e2d74 100644
--- a/include/configs/cei-tk1-som.h
+++ b/include/configs/cei-tk1-som.h

@@ -20,7 +20,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* SPI */
 #define CONFIG_SPI_FLASH_SIZE		(4 << 20)

diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index c395384..6f3396b 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h

@@ -19,7 +19,7 @@
 
 /* Flat Device Tree Definitions */
 
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+#define CFG_SYS_BOOTMAPSZ		(256 << 20)
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 #define USDHC1_BASE_ADDR		0x5B010000
 #define USDHC2_BASE_ADDR		0x5B020000
@@ -111,7 +111,7 @@
 
 #define CFG_SYS_FSL_USDHC_NUM	3
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */

diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index fdbcbf5..1e5154a 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h

@@ -97,18 +97,18 @@
 	NANDARGS
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
-#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
-#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
-#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
-#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
-#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+#define CFG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CFG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CFG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CFG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CFG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CFG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
 
 /* SPL */
 
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -116,7 +116,7 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 #endif	/* ! __CONFIG_CHILIBOARD_H */

diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h
index 0eeea80..d14c1d4 100644
--- a/include/configs/chromebook_coral.h
+++ b/include/configs/chromebook_coral.h

@@ -18,7 +18,4 @@
 					"stdout=vidconsole,serial\0" \
 					"stderr=vidconsole,serial\0"
 
-#define CONFIG_SYS_NS16550_MEM32
-#undef CONFIG_SYS_NS16550_PORT_MAPPED
-
 #endif	/* __CONFIG_H */

diff --git a/include/configs/ci20.h b/include/configs/ci20.h
index 63dac1d..3329c24 100644
--- a/include/configs/ci20.h
+++ b/include/configs/ci20.h

@@ -11,11 +11,11 @@
 
 /* Memory configuration */
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* cached (KSEG0) address */
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CFG_SYS_SDRAM_BASE		0x80000000 /* cached (KSEG0) address */
+#define CFG_SYS_INIT_SP_OFFSET	0x400000
 
 /* NS16550-ish UARTs */
-#define CONFIG_SYS_NS16550_CLK		48000000
+#define CFG_SYS_NS16550_CLK		48000000
 
 /* Ethernet: davicom DM9000 */
 #define CONFIG_DM9000_BASE		0xb6000000

diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index cbf8534..5c9004c 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h

@@ -19,12 +19,10 @@
 #define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
 
 /* PMIC */
-#define CONFIG_POWER_PFUZE3000
 #define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
 
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR	0x20
-#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x20, 16} }
+#define CFG_SYS_I2C_PCA953X_ADDR	0x20
+#define CFG_SYS_I2C_PCA953X_WIDTH	{ {0x20, 16} }
 
 #undef CONFIG_EXTRA_ENV_SETTINGS
 
@@ -82,9 +80,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* SPI Flash support */
 
@@ -101,7 +99,4 @@
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS   0
 
-/* SPL */
-#include "imx7_spl.h"
-
 #endif	/* __CONFIG_H */

diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 874c0eb..9df8baa 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h

@@ -21,9 +21,9 @@
 /* RAM */
 #define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
 #define PHYS_SDRAM_2			MMDC1_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Serial console */
 #define CONFIG_MXC_UART_BASE		UART4_BASE
@@ -128,7 +128,7 @@
 #include <config_distro_bootcmd.h>
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 /* APBH DMA is required for NAND support */
 
 /* Ethernet */
@@ -139,16 +139,10 @@
 #define CONFIG_MXC_USB_FLAGS		0
 
 /* Boot */
-#define CONFIG_SYS_BOOTMAPSZ	        (8 << 20)
+#define CFG_SYS_BOOTMAPSZ	        (8 << 20)
 
 /* misc */
 
-/* SPL */
-#include "imx6_spl.h"
-
-/* Display */
-#define CONFIG_IMX_HDMI
-
 /* EEPROM */
 
 #endif	/* __CONFIG_CM_FX6_H */

diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index f0fbbe2..fcc17fc 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h

@@ -9,22 +9,18 @@
 #define __CONFIG_CM_T43_H
 
 #define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2GB */
-#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
 #include <asm/arch/omap.h>
 
 /* Serial support */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		48000000
-#define CONFIG_SYS_NS16550_COM1		0x44e09000
-#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#endif
+#define CFG_SYS_NS16550_CLK		48000000
+#define CFG_SYS_NS16550_COM1		0x44e09000
 
 /* NAND support */
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -32,11 +28,8 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-/* Power */
-#define CONFIG_POWER_TPS65218
-
 /* Enabling L2 Cache */
-#define CONFIG_SYS_PL310_BASE		0x48242000
+#define CFG_SYS_PL310_BASE		0x48242000
 
 /*
  * Since SPL did pll and ddr initialization for us,

diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 52000b5..6d6e2fc 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h

@@ -29,32 +29,20 @@
  * ---
  */
 
-#define CONFIG_SYS_CLK			66000000
-#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CFG_SYS_CLK			66000000
+#define CFG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
 
 /* ---
  * Define baudrate for UART1 (console output, tftp, ...)
  * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
- * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
+ * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
  * interface
  * ---
  */
 
-#define CONFIG_SYS_UART_PORT		(0)
+#define CFG_SYS_UART_PORT		(0)
 
 /* ---
- * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
- * timeout acc. to your needs
- * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
- * for 10 sec
- * ---
- */
-
-#if 0
-#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
-#endif
-
-/* ---
  * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
  * bootloader residing in flash ('chainloading'); if you want to use
  * chainloading or want to compile a u-boot binary that can be loaded into
@@ -133,28 +121,28 @@
  * ---
  */
 
-#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CFG_SYS_MBAR		0x10000000	/* Register Base Addrs */
 
 /* ---
  * System Conf. Reg. & System Protection Reg.
  * ---
  */
 
-#define CONFIG_SYS_SCR			0x0003
-#define CONFIG_SYS_SPR			0xffff
+#define CFG_SYS_SCR			0x0003
+#define CFG_SYS_SPR			0xffff
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in internal SRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 /*
  *-------------------------------------------------------------------------
@@ -162,34 +150,34 @@
  *-----------------------------------------------------------------------
  */
 
-/* #define CONFIG_SYS_SDRAM_SIZE		16 */
+/* #define CFG_SYS_SDRAM_SIZE		16 */
 
 /*
  *-----------------------------------------------------------------------
  */
 
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CFG_SYS_FLASH_BASE		0xffe00000
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
 					 CF_CACR_DISD | CF_CACR_INVI | \
 					 CF_CACR_CEIB | CF_CACR_DCM | \
 					 CF_CACR_EUSP)
@@ -209,15 +197,15 @@
 /*-----------------------------------------------------------------------
  * Port configuration (GPIO)
  */
-#define CONFIG_SYS_PACNT		0x00000000		/* PortA control reg.: All pins are external
+#define CFG_SYS_PACNT		0x00000000		/* PortA control reg.: All pins are external
 GPIO*/
-#define CONFIG_SYS_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
+#define CFG_SYS_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
 (1^=output, 0^=input) */
-#define CONFIG_SYS_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
-#define CONFIG_SYS_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
+#define CFG_SYS_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
+#define CFG_SYS_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
 configuration */
-#define CONFIG_SYS_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
-#define CONFIG_SYS_PBDAT		0x0000			/* PortB value reg. */
-#define CONFIG_SYS_PDCNT		0x00000000		/* PortD control reg. */
+#define CFG_SYS_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
+#define CFG_SYS_PBDAT		0x0000			/* PortB value reg. */
+#define CFG_SYS_PDCNT		0x00000000		/* PortD control reg. */
 
 #endif	/* _CONFIG_COBRA5272_H */

diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index d7e181b..c0c3b4e 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h

@@ -11,7 +11,6 @@
 #define __COLIBRI_IMX6ULL_CONFIG_H
 
 #include "mx6_common.h"
-#define CONFIG_IOMUX_LPSR
 
 #define PHYS_SDRAM_SIZE			SZ_1G
 
@@ -116,14 +115,14 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
 /* NAND stuff */
-/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
-#define CONFIG_SYS_NAND_BASE		-1
+/* used to initialize CFG_SYS_NAND_BASE_LIST which is unused */
+#define CFG_SYS_NAND_BASE		-1
 #endif
 
 /* USB Configs */

diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
index d641fbf..6002d8d 100644
--- a/include/configs/colibri-imx8x.h
+++ b/include/configs/colibri-imx8x.h

@@ -96,7 +96,7 @@
 /* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
 #define CFG_SYS_FSL_USDHC_NUM	2
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #define PHYS_SDRAM_1_SIZE		SZ_2G		/* 2 GB */

diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 14fdf5b..60a3862 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h

@@ -15,10 +15,6 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/mach-imx/gpio.h>
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* MMC Configs */
@@ -32,10 +28,6 @@
 /* Client */
 #define CONFIG_USBD_HS
 
-/* Framebuffer and LCD */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
 /* Command definition */
 
 #undef CONFIG_IPADDR
@@ -104,8 +96,8 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #endif	/* __CONFIG_H */

diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 7380440..32a79b0 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h

@@ -160,14 +160,13 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
+#define CFG_SYS_NAND_BASE		0x40000000
 #endif
 
 /* USB Configs */

diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index b758086..2ba3c3b 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h

@@ -13,7 +13,7 @@
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
 #define CONFIG_TEGRA_UARTA_SDIO1
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 /* NAND support */
 

diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index c9d384e..ffed71a 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h

@@ -22,7 +22,7 @@
  * Colibri UART-C: NVIDIA UARTB
  */
 #define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 #define UBOOT_UPDATE \
 	"uboot_hwpart=1\0" \

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 0f6f99d..fa778ec 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h

@@ -85,9 +85,9 @@
 #define PHYS_SDRAM			(0x80000000)
 #define PHYS_SDRAM_SIZE			(256 * SZ_1M)
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* USB Host Support */
 

diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
index 8e0230c..8aec52d 100644
--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h

@@ -22,7 +22,7 @@
 #define PHYS_SDRAM_1		(V2M_BASE)
 #define PHYS_SDRAM_1_SIZE	0x80000000
 
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM_1
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(USB, usb, 0)

diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 0596afb..8a61086 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h

@@ -24,27 +24,26 @@
  */
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK      32768
+#define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
 
 /* serial console */
 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
 #define CONFIG_USART_ID			ATMEL_ID_SYS
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CFG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
+#define CFG_SYS_SDRAM_SIZE		0x08000000
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PC8
 #endif
 
 /* DFU class support */
@@ -54,20 +53,20 @@
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 
-#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CFG_SYS_MASTER_CLOCK		132096000
 #define AT91_PLL_LOCK_TIMEOUT		1000000
-#define CONFIG_SYS_AT91_PLLA		0x20c73f03
-#define CONFIG_SYS_MCKR			0x1301
-#define CONFIG_SYS_MCKR_CSS		0x1302
+#define CFG_SYS_AT91_PLLA		0x20c73f03
+#define CFG_SYS_MCKR			0x1301
+#define CFG_SYS_MCKR_CSS		0x1302
 
 #endif

diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
index efd0b77..b64c7df 100644
--- a/include/configs/cougarcanyon2.h
+++ b/include/configs/cougarcanyon2.h

@@ -8,8 +8,6 @@
 
 #include <configs/x86-common.h>
 
-#define CONFIG_SMSC_SIO1007
-
 #define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
 					"stdout=serial,vga\0" \
 					"stderr=serial,vga\0"

diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index e8a8af7..ff74deb 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h

@@ -12,8 +12,6 @@
 
 #include <configs/x86-common.h>
 
-#define CONFIG_SMSC_LPC47M
-
 #define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
 					"stdout=serial,vidconsole\0" \
 					"stderr=serial,vidconsole\0"

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 281cbe3..a818a4b 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h

@@ -17,13 +17,13 @@
 /*
  * SoC Configuration
  */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_OSCIN_FREQ		24000000
-#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_OSCIN_FREQ		24000000
+#define CFG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
+#define CFG_SYS_DV_NOR_BOOT_CFG	(0x11)
 #endif
 
 /*
@@ -36,7 +36,7 @@
 
 /* memtest will be run on 16MB */
 
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+#define CFG_SYS_DA850_SYSCFG_SUSPSRC (	\
 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
 	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
@@ -47,17 +47,17 @@
  * PLL configuration
  */
 
-#define CONFIG_SYS_DA850_PLL0_PLLM     24
-#define CONFIG_SYS_DA850_PLL1_PLLM     21
+#define CFG_SYS_DA850_PLL0_PLLM     24
+#define CFG_SYS_DA850_PLL1_PLLM     21
 
 /*
  * DDR2 memory configuration
  */
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
 					DV_DDR_PHY_EXT_STRBEN | \
 					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
+#define CFG_SYS_DA850_DDR2_SDBCR (		\
 	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
 	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
 	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
@@ -67,9 +67,9 @@
 	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 
 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+#define CFG_SYS_DA850_DDR2_SDBCR2 0
 
-#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
+#define CFG_SYS_DA850_DDR2_SDTIMR (		\
 	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
 	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
 	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
@@ -79,7 +79,7 @@
 	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
 	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
+#define CFG_SYS_DA850_DDR2_SDTIMR2 (		\
 	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
 	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
 	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
@@ -88,51 +88,44 @@
 	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
 	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
-#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+#define CFG_SYS_DA850_DDR2_SDRCR    0x00000494
+#define CFG_SYS_DA850_DDR2_PBBPR    0x30
 
 /*
  * Serial Driver info
  */
-#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CFG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
 
-#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+#define CFG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
 
 /*
  * I2C Configuration
  */
-#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
+#define CFG_SYS_I2C_EXPANDER_ADDR   0x20
 
 /*
  * Flash & Environment
  */
 #ifdef CONFIG_MTD_RAW_NAND
-#define	CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_CS		3
-#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE		0x10
-#define CONFIG_SYS_NAND_MASK_ALE		0x8
-#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x40000
-#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
-					CONFIG_SYS_NAND_U_BOOT_SIZE - \
-					CONFIG_SYS_MALLOC_LEN -       \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS		{				\
+#define CFG_SYS_NAND_CS		3
+#define CFG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_SYS_NAND_MASK_CLE		0x10
+#define CFG_SYS_NAND_MASK_ALE		0x8
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x40000
+#define CFG_SYS_NAND_U_BOOT_DST	0xc1080000
+#define CFG_SYS_NAND_U_BOOT_START	CFG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_ECCPOS		{				\
 				24, 25, 26, 27, 28, \
 				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 				59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	10
 #endif
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define CFG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 #define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
 #endif
 
@@ -144,7 +137,6 @@
  * Linux Information
  */
 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
-#define CONFIG_HWCONFIG		/* enable hwconfig */
 
 #define DEFAULT_LINUX_BOOT_ENV \
 	"loadaddr=0xc0700000\0" \
@@ -173,7 +165,7 @@
 /* Load U-Boot Image From MMC */
 
 /* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CFG_SYS_SDRAM_BASE		0xc0000000
 
 #include <asm/arch/hardware.h>
 

diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index e03a24a..24cf554 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h

@@ -15,7 +15,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 

diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
index 6079596..4b31bbf 100644
--- a/include/configs/dart_6ul.h
+++ b/include/configs/dart_6ul.h

@@ -10,9 +10,6 @@
 #include <linux/stringify.h>
 #include "mx6_common.h"
 
-/* SPL options */
-#include "imx6_spl.h"
-
 /* NAND pin conflicts with usdhc2 */
 #ifdef CONFIG_CMD_NAND
 #define CFG_SYS_FSL_USDHC_NUM        1
@@ -45,9 +42,9 @@
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 #define PHYS_SDRAM_SIZE			SZ_512M
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 7b30595..bf8b351 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h

@@ -45,7 +45,4 @@
 /* SPL */
 /* Defines for SPL */
 
-/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SPD_EEPROM		0x4e
-
 #endif /* _CONFIG_DB_MV7846MP_GP_H */

diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 4236612..66aa6d5 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h

@@ -15,8 +15,8 @@
 /*
  * Memory configurations
  */
-#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE		SZ_64M
+#define CFG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_SIZE		SZ_64M
 
 /*
  * DMA
@@ -29,14 +29,14 @@
 /*
  * NOR Flash
  */
-#define CONFIG_SYS_FLASH_BASE		EMC_CS0_BASE
-#define CONFIG_SYS_FLASH_SIZE		SZ_4M
+#define CFG_SYS_FLASH_BASE		EMC_CS0_BASE
+#define CFG_SYS_FLASH_SIZE		SZ_4M
 
 /*
  * NAND controller
  */
-#define CONFIG_SYS_NAND_BASE		SLC_NAND_BASE
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE		SLC_NAND_BASE
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 /*
  * NAND chip timings
@@ -79,10 +79,10 @@
  */
 
 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x60000
 
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
 /* See common/spl/spl.c  spl_set_header_raw_uboot() */
 

diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index d45115b..4641059 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h

@@ -100,12 +100,12 @@
 /* Defines for SPL */
 
 /* NAND boot config */
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
 						10, 11, 12, 13}
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	3
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x200000
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h
index 4297047..52f2d50 100644
--- a/include/configs/dfi-bt700.h
+++ b/include/configs/dfi-bt700.h

@@ -14,7 +14,6 @@
 
 #ifndef CONFIG_INTERNAL_UART
 /* Use BayTrail internal HS UART which is memory-mapped */
-#undef  CONFIG_SYS_NS16550_PORT_MAPPED
 #endif
 
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \

diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 54b2192..f9b3d19 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h

@@ -21,9 +21,6 @@
  * 0x12_0000-0x1f_ffff ... UNUSED
  */
 
-/* SPL */
-#include "imx6_spl.h"			/* common IMX6 SPL configuration */
-
 /* Miscellaneous configurable options */
 
 /* MMC Configs */
@@ -75,9 +72,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment */
 

diff --git a/include/configs/display5.h b/include/configs/display5.h
index eb65f17..7636d28 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h

@@ -30,11 +30,9 @@
  */
 
 /* Below values are "dummy" - only to avoid build break */
-#define CONFIG_SYS_SPI_KERNEL_OFFS      0x150000
-#define CONFIG_SYS_SPI_ARGS_OFFS        0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE        0x10000
-
-#include "imx6_spl.h"
+#define CFG_SYS_SPI_KERNEL_OFFS      0x150000
+#define CFG_SYS_SPI_ARGS_OFFS        0x140000
+#define CFG_SYS_SPI_ARGS_SIZE        0x10000
 
 #define CONFIG_MXC_UART_BASE		UART5_BASE
 
@@ -285,10 +283,10 @@
 
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
 
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* ENV config */
 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 6cf716e..ac3fcac 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h

@@ -13,8 +13,6 @@
 
 #include <environment/ti/dfu.h>
 
-#define CONFIG_IODELAY_RECALIBRATION
-
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_MAX_MEM_MAPPED		0x80000000
 
@@ -27,11 +25,9 @@
 #elif (CONFIG_CONS_INDEX == 3)
 #define CONSOLEDEV			"ttyS2"
 #endif
-#define CONFIG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2		UART2_BASE	/* UART2 */
-#define CONFIG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
-
-#define CONFIG_SYS_OMAP_ABE_SYSCK
+#define CFG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2		UART2_BASE	/* UART2 */
+#define CFG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
 
 #ifndef CONFIG_SPL_BUILD
 #define DFUARGS \
@@ -65,9 +61,9 @@
  * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
  * 0x9E0000 - 0x2000000 : USERLAND
  */
-#define CONFIG_SYS_SPI_KERNEL_OFFS	0x1E0000
-#define CONFIG_SYS_SPI_ARGS_OFFS	0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE	0x80000
+#define CFG_SYS_SPI_KERNEL_OFFS	0x1E0000
+#define CFG_SYS_SPI_ARGS_OFFS	0x140000
+#define CFG_SYS_SPI_ARGS_SIZE	0x80000
 
 /* SPI SPL */
 
@@ -75,22 +71,22 @@
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
 					 34, 35, 36, 37, 38, 39, 40, 41, \
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 #endif /* !CONFIG_MTD_RAW_NAND */
 
 /* Parallel NOR Support */
 #if defined(CONFIG_NOR)
 /* NOR: device related configs */
-#define CONFIG_SYS_FLASH_SIZE		(64 * 1024 * 1024) /* 64 MB */
-#define CONFIG_SYS_FLASH_BASE		(0x08000000)
+#define CFG_SYS_FLASH_SIZE		(64 * 1024 * 1024) /* 64 MB */
+#define CFG_SYS_FLASH_BASE		(0x08000000)
 /* Reduce SPL size by removing unlikey targets */
 #endif  /* NOR support */
 

diff --git a/include/configs/draak.h b/include/configs/draak.h
index 8bfba78..8140bc4 100644
--- a/include/configs/draak.h
+++ b/include/configs/draak.h

@@ -14,7 +14,7 @@
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
 
 #endif /* __DRAAK_H */

diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index c37b4c6..daf7ecd 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h

@@ -17,7 +17,7 @@
 #define PHYS_SDRAM_1			0x80000000
 /* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */
 #define PHYS_SDRAM_1_SIZE		SZ_1G
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 /* Environment */
 #define BOOT_TARGET_DEVICES(func) \

diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h
index 1fa5d05..31cd853 100644
--- a/include/configs/dragonboard820c.h
+++ b/include/configs/dragonboard820c.h

@@ -19,7 +19,7 @@
 #define PHYS_SDRAM_2			0x100000000
 #define PHYS_SDRAM_2_SIZE		0x5ea4ffff
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 #include <config_distro_bootcmd.h>
 

diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h
index 677a485..bd88c42 100644
--- a/include/configs/dragonboard845c.h
+++ b/include/configs/dragonboard845c.h

@@ -11,7 +11,7 @@
 #include <linux/sizes.h>
 #include <asm/arch/sysmap-sdm845.h>
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
+#define CFG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootm_size=0x5000000\0"	\

diff --git a/include/configs/durian.h b/include/configs/durian.h
index 8f0e8be..001596c 100644
--- a/include/configs/durian.h
+++ b/include/configs/durian.h

@@ -11,7 +11,7 @@
 /* Sdram Bank #1 Address */
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_1_SIZE		0x7B000000
-#define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE   PHYS_SDRAM_1
 
 /* BOOT */
 

diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h
index 1d65529..fc1c2ae 100644
--- a/include/configs/ea-lpc3250devkitv2.h
+++ b/include/configs/ea-lpc3250devkitv2.h

@@ -13,7 +13,7 @@
 /*
  * RAM
  */
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
 
 /*
  * cmd

diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index aaa2ef0..21eab9b 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h

@@ -12,7 +12,7 @@
  * High Level Configuration Options (easy to change)                    *
  *----------------------------------------------------------------------*/
 
-#define CONFIG_SYS_UART_PORT		(0)
+#define CFG_SYS_UART_PORT		(0)
 
 #undef	CONFIG_MONITOR_IS_IN_RAM		/* starts uboot direct */
 
@@ -27,18 +27,18 @@
  * Environment is in the second sector of the first 256k of flash	*
  *----------------------------------------------------------------------*/
 
-/*#define CONFIG_SYS_DRAM_TEST		1 */
-#undef CONFIG_SYS_DRAM_TEST
+/*#define CFG_SYS_DRAM_TEST		1 */
+#undef CFG_SYS_DRAM_TEST
 
 /*----------------------------------------------------------------------*
  * Clock and PLL Configuration						*
  *----------------------------------------------------------------------*/
-#define	CONFIG_SYS_CLK			80000000      /* 8MHz * 8 */
+#define	CFG_SYS_CLK			80000000      /* 8MHz * 8 */
 
 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
 
-#define CONFIG_SYS_MFD		0x02	/* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD		0x00	/* PLL Reduce Frecuency Devider */
+#define CFG_SYS_MFD		0x02	/* PLL Multiplication Factor Devider */
+#define CFG_SYS_RFD		0x00	/* PLL Reduce Frecuency Devider */
 
 /*----------------------------------------------------------------------*
  * Network								*
@@ -54,59 +54,59 @@
  * You should know what you are doing if you make changes here.
  *-----------------------------------------------------------------------*/
 
-#define	CONFIG_SYS_MBAR			0x40000000
+#define	CFG_SYS_MBAR			0x40000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  *-----------------------------------------------------------------------*/
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CFG_SYS_INIT_RAM_ADDR	0x20000000
+#define CFG_SYS_INIT_RAM_SIZE	0x10000
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE0		0x00000000
-#define	CONFIG_SYS_SDRAM_SIZE0		16	/* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE0		0x00000000
+#define	CFG_SYS_SDRAM_SIZE0		16	/* SDRAM size in MB */
 
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_SDRAM_BASE0
-#define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE0
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_SDRAM_BASE0
+#define	CFG_SYS_SDRAM_SIZE		CFG_SYS_SDRAM_SIZE0
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define	CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+#define	CFG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define CONFIG_FLASH_SHOW_PROGRESS	45
 
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
-#define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
+#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE
+#define	CFG_SYS_INT_FLASH_BASE	0xF0000000
+#define CFG_SYS_INT_FLASH_ENABLE	0x21
 
-#define CONFIG_SYS_FLASH_SIZE		16*1024*1024
+#define CFG_SYS_FLASH_SIZE		16*1024*1024
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE }
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
 					 CF_CACR_CEIB | CF_CACR_DBWE | \
 					 CF_CACR_EUSP)
 
@@ -114,75 +114,44 @@
  * Memory bank definitions
  */
 
-#define CONFIG_SYS_CS0_BASE		0xFF000000
-#define CONFIG_SYS_CS0_CTRL		0x00001980
-#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CFG_SYS_CS0_BASE		0xFF000000
+#define CFG_SYS_CS0_CTRL		0x00001980
+#define CFG_SYS_CS0_MASK		0x00FF0001
 
-#define CONFIG_SYS_CS2_BASE		0xE0000000
-#define CONFIG_SYS_CS2_CTRL		0x00001980
-#define CONFIG_SYS_CS2_MASK		0x000F0001
+#define CFG_SYS_CS2_BASE		0xE0000000
+#define CFG_SYS_CS2_CTRL		0x00001980
+#define CFG_SYS_CS2_MASK		0x000F0001
 
-#define CONFIG_SYS_CS3_BASE		0xE0100000
-#define CONFIG_SYS_CS3_CTRL		0x00001980
-#define CONFIG_SYS_CS3_MASK		0x000F0001
+#define CFG_SYS_CS3_BASE		0xE0100000
+#define CFG_SYS_CS3_CTRL		0x00001980
+#define CFG_SYS_CS3_MASK		0x000F0001
 
 /*-----------------------------------------------------------------------
  * Port configuration
  */
-#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
-#define CONFIG_SYS_PADDR		0x0000000
-#define CONFIG_SYS_PADAT		0x0000000
+#define CFG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
+#define CFG_SYS_PADDR		0x0000000
+#define CFG_SYS_PADAT		0x0000000
 
-#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
-#define CONFIG_SYS_PBDDR		0x0000000
-#define CONFIG_SYS_PBDAT		0x0000000
+#define CFG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CFG_SYS_PBDDR		0x0000000
+#define CFG_SYS_PBDAT		0x0000000
 
-#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
-#define CONFIG_SYS_PCDDR		0x0000000
-#define CONFIG_SYS_PCDAT		0x0000000
+#define CFG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
 
-#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
-#define CONFIG_SYS_PCDDR		0x0000000
-#define CONFIG_SYS_PCDAT		0x0000000
-
-#define CONFIG_SYS_PASPAR		0x0F0F
-#define CONFIG_SYS_PEHLPAR		0xC0
-#define CONFIG_SYS_PUAPAR		0x0F
-#define CONFIG_SYS_DDRUA		0x05
-#define CONFIG_SYS_PJPAR		0xFF
+#define CFG_SYS_PASPAR		0x0F0F
+#define CFG_SYS_PEHLPAR		0xC0
+#define CFG_SYS_PUAPAR		0x0F
+#define CFG_SYS_DDRUA		0x05
+#define CFG_SYS_PJPAR		0xFF
 
 /*-----------------------------------------------------------------------
  * I2C
  */
 
 #ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1338
 #define CONFIG_I2C_RTC_ADDR		0x68
 #endif
 
-/*-----------------------------------------------------------------------
- * VIDEO configuration
- */
-
-#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	2
-#define	CONFIG_SYS_VCXK_DOUBLEBUFFERED		1
-#define CONFIG_SYS_VCXK_BASE			CONFIG_SYS_CS2_BASE
-
-#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	MCFGPTB_GPTPORT
-#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		MCFGPTB_GPTDDR
-#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		0x0001
-
-#define CONFIG_SYS_VCXK_ENABLE_PORT		MCFGPTB_GPTPORT
-#define CONFIG_SYS_VCXK_ENABLE_DDR		MCFGPTB_GPTDDR
-#define CONFIG_SYS_VCXK_ENABLE_PIN		0x0002
-
-#define CONFIG_SYS_VCXK_REQUEST_PORT		MCFGPTB_GPTPORT
-#define CONFIG_SYS_VCXK_REQUEST_DDR		MCFGPTB_GPTDDR
-#define CONFIG_SYS_VCXK_REQUEST_PIN		0x0004
-
-#define CONFIG_SYS_VCXK_INVERT_PORT		MCFGPIO_PORTE
-#define CONFIG_SYS_VCXK_INVERT_DDR		MCFGPIO_DDRE
-#define CONFIG_SYS_VCXK_INVERT_PIN		MCFGPIO_PORT2
-
 #endif	/* _CONFIG_M5282EVB_H */
 /*---------------------------------------------------------------------*/

diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h
index 597efd6..d1882a9 100644
--- a/include/configs/ebisu.h
+++ b/include/configs/ebisu.h

@@ -16,7 +16,7 @@
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
 
 #endif /* __EBISU_H */

diff --git a/include/configs/edison.h b/include/configs/edison.h
index b05141a..455a889 100644
--- a/include/configs/edison.h
+++ b/include/configs/edison.h

@@ -10,6 +10,6 @@
 
 /* Miscellaneous configurable options */
 
-#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
+#define CFG_SYS_STACK_SIZE			(32 * 1024)
 
 #endif

diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index affe20a..89e071c 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h

@@ -12,16 +12,11 @@
 
 #include "mx6_common.h"
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 /* MMC Configs */
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 #define CFG_SYS_FSL_USDHC_NUM	2
 
 /* PMIC */
-#define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* Commands */
@@ -54,9 +49,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* environment organization */
 

diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 555239b..22e0fa5 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h

@@ -27,9 +27,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* Environment organization */
 
@@ -43,18 +43,8 @@
 #define CFG_SYS_FSL_USDHC_NUM	2
 #endif
 
-/* Framebuffer */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
 #include "mx6_common.h"
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-/* RiOTboard */
-
-#endif
-
 /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
  * 1M script, 1M pxe and the ramdisk at the end */
 #define MEM_LAYOUT_ENV_SETTINGS \

diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h
index 60fab04..c2b921e 100644
--- a/include/configs/emsdp.h
+++ b/include/configs/emsdp.h

@@ -8,8 +8,8 @@
 
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_SDRAM_BASE		0x10000000
-#define CONFIG_SYS_SDRAM_SIZE		SZ_16M
+#define CFG_SYS_SDRAM_BASE		0x10000000
+#define CFG_SYS_SDRAM_SIZE		SZ_16M
 
 /*
  * Environment

diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
index 2f067a4..b4f14a9 100644
--- a/include/configs/espresso7420.h
+++ b/include/configs/espresso7420.h

@@ -10,7 +10,7 @@
 
 #include <configs/exynos7420-common.h>
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 /* DRAM Memory Banks */
 #define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */

diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index 75322a3..6647148 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h

@@ -14,10 +14,10 @@
 
 #include "siemens-am33x-common.h"
 /* NAND specific changes for etamin due to different page size */
-#undef CONFIG_SYS_NAND_ECCPOS
+#undef CFG_SYS_NAND_ECCPOS
 
-#define CONFIG_SYS_ENV_SECT_SIZE       (512 << 10)     /* 512 KiB */
-#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_ENV_SECT_SIZE       (512 << 10)     /* 512 KiB */
+#define CFG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
 				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
 				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
 				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@@ -40,14 +40,14 @@
 			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
 			}
 
-#undef CONFIG_SYS_NAND_ECCSIZE
-#undef CONFIG_SYS_NAND_ECCBYTES
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
+#undef CFG_SYS_NAND_ECCSIZE
+#undef CFG_SYS_NAND_ECCBYTES
+#define CFG_SYS_NAND_ECCSIZE 512
+#define CFG_SYS_NAND_ECCBYTES 26
 
-#define CONFIG_SYS_NAND_BASE2           (0x18000000)    /* physical address */
-#define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
-					CONFIG_SYS_NAND_BASE2}
+#define CFG_SYS_NAND_BASE2           (0x18000000)    /* physical address */
+#define CFG_SYS_NAND_BASE_LIST       {CFG_SYS_NAND_BASE, \
+					CFG_SYS_NAND_BASE2}
 
 #define DDR_PLL_FREQ	303
 

diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 22647ab..52eb0be 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h

@@ -18,32 +18,31 @@
 /* CPU information */
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */
 
 /* 32kB internal SRAM */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x00300000 /*AT91SAM9XE_SRAM_BASE */
-#define CONFIG_SYS_INIT_RAM_SIZE	(32 << 10)
+#define CFG_SYS_INIT_RAM_ADDR	0x00300000 /*AT91SAM9XE_SRAM_BASE */
+#define CFG_SYS_INIT_RAM_SIZE	(32 << 10)
 
 /* 128MB SDRAM in 1 bank */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		(128 << 20)
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		(128 << 20)
 
 /* 512kB on-chip NOR flash */
-# define CONFIG_SYS_FLASH_BASE		0x00200000 /* AT91SAM9XE_FLASH_BASE */
+# define CFG_SYS_FLASH_BASE		0x00200000 /* AT91SAM9XE_FLASH_BASE */
 
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8
+#define CFG_SYS_NAND_BASE		0x40000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
 #endif
 
 /* JFFS2 */
@@ -54,16 +53,16 @@
 
 /* MMC */
 #ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_CD_PIN		AT91_PIO_PORTC, 8
+#define CFG_SYS_MMC_CD_PIN		AT91_PIO_PORTC, 8
 #endif
 
 /* RTC */
 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+#define CFG_SYS_I2C_RTC_ADDR		0x51
 #endif
 
 /* I2C */
-#define CONFIG_SYS_MAX_I2C_BUS	1
+#define CFG_SYS_MAX_I2C_BUS	1
 
 #define I2C_SOFT_DECLARATIONS
 

diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h
index cd6cb06..bec1660 100644
--- a/include/configs/evb_ast2500.h
+++ b/include/configs/evb_ast2500.h

@@ -11,7 +11,7 @@
 
 #include <configs/aspeed-common.h>
 
-#define CONFIG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
 
 /* Misc */
 #define CONFIG_EXTRA_ENV_SETTINGS \

diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h
index ecd05fe..c9c988b 100644
--- a/include/configs/evb_ast2600.h
+++ b/include/configs/evb_ast2600.h

@@ -8,7 +8,7 @@
 
 #include <configs/aspeed-common.h>
 
-#define CONFIG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
 
 /* Misc */
 #define STR_HELPER(s)	#s

diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 44f5cb1..dd322c2 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h

@@ -29,21 +29,21 @@
 
 #define CONFIG_RD_LVL
 
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1		CFG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2		(CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3		(CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4		(CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5		(CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6		(CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7		(CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8		(CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
 
 /* SPI */

diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h
index a94f5a1..c9e0c13 100644
--- a/include/configs/exynos5-dt-common.h
+++ b/include/configs/exynos5-dt-common.h

@@ -15,7 +15,7 @@
 		"stdout=serial,vidconsole\0" \
 		"stderr=serial,vidconsole\0"
 
-#define CONFIG_SYS_SPI_BASE	0x12D30000
+#define CFG_SYS_SPI_BASE	0x12D30000
 #define FLASH_SIZE		(4 << 20)
 #define CONFIG_SPI_BOOTING
 

diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h
index 8e2f135..cc0cf5e 100644
--- a/include/configs/exynos5250-common.h
+++ b/include/configs/exynos5250-common.h

@@ -9,7 +9,7 @@
 #ifndef __CONFIG_5250_H
 #define __CONFIG_5250_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 /* DRAM Memory Banks */
 #define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */

diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
index a8bef86..cff910c 100644
--- a/include/configs/exynos7420-common.h
+++ b/include/configs/exynos7420-common.h

@@ -23,21 +23,21 @@
 
 /* select serial console configuration */
 
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1		CFG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2		(CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3		(CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4		(CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5		(CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6		(CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7		(CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8		(CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
 
 /* Configuration of ENV Blocks */

diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h
index b05846d..8672b9e 100644
--- a/include/configs/exynos78x0-common.h
+++ b/include/configs/exynos78x0-common.h

@@ -18,35 +18,35 @@
 
 #define CPU_RELEASE_ADDR		secondary_boot_addr
 
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
 	{9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 /* DRAM Memory Banks */
 #define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1		CFG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2		(CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3		(CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4		(CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5		(CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6		(CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7		(CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8		(CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_9		(CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_9		(CFG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_9_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_10		(CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_10		(CFG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_10_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_11		(CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_11		(CFG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_11_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_12		(CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_12		(CFG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_12_SIZE	SDRAM_BANK_SIZE
 
 #ifndef MEM_LAYOUT_ENV_SETTINGS

diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 545408a..472f236 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h

@@ -13,7 +13,6 @@
 #include <configs/x86-common.h>
 
 /* ns16550 UART is memory-mapped in Quark SoC */
-#undef  CONFIG_SYS_NS16550_PORT_MAPPED
 
 #define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial\0" \
 					"stdout=serial\0" \

diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index 52b9fe2..89e5316 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h

@@ -14,32 +14,31 @@
 #endif
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768
+#define CFG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */
 
 /* NAND flash */
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8		1
+#define CFG_SYS_NAND_BASE		0x40000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
+#define CFG_SYS_NAND_MASK_ALE	BIT(21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+#define CFG_SYS_NAND_MASK_CLE	BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PD5
 
 /* SPL */
 
-#define CONFIG_SYS_MASTER_CLOCK		132096000
-#define CONFIG_SYS_AT91_PLLA		0x20c73f03
-#define CONFIG_SYS_MCKR			0x1301
-#define CONFIG_SYS_MCKR_CSS		0x1302
+#define CFG_SYS_MASTER_CLOCK		132096000
+#define CFG_SYS_AT91_PLLA		0x20c73f03
+#define CFG_SYS_MCKR			0x1301
+#define CFG_SYS_MCKR_CSS		0x1302
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0xa0000
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	0xa0000
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
 #endif

diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h
index 965fa87..0ba4efe 100644
--- a/include/configs/gardena-smart-gateway-mt7688.h
+++ b/include/configs/gardena-smart-gateway-mt7688.h

@@ -7,27 +7,25 @@
 #define __CONFIG_GARDENA_SMART_GATEWAY_H
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CFG_SYS_INIT_SP_OFFSET	0x400000
 
 /* SPL */
 
-#define CONFIG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 
 /* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE		0
+#define CFG_SYS_UBOOT_BASE		0
 
 /* Serial SPL */
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_CLK		40000000
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM1		0xb0000c00
+#define CFG_SYS_NS16550_CLK		40000000
+#define CFG_SYS_NS16550_COM1		0xb0000c00
 #endif
 
 /* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 921600 }
 
 /* RAM */

diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h
index fa6f0e6..36dcee8 100644
--- a/include/configs/gazerbeam.h
+++ b/include/configs/gazerbeam.h

@@ -12,9 +12,9 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+/* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */
+#define CFG_SYS_DDR_SDRAM_BASE	CFG_SYS_SDRAM_BASE
 
 /*
  * Memory test
@@ -28,16 +28,16 @@
 /*
  * Initial RAM Base Address Setup
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
 
 /*
  * FLASH on the Local Bus
  */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
+#define CFG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CFG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
 
-#define CONFIG_SYS_BAUDRATE_TABLE  \
+#define CFG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*
@@ -49,7 +49,7 @@
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
 
 /*
  * Environment Configuration

diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h
index 176f80b..1458b18 100644
--- a/include/configs/ge_b1x5v2.h
+++ b/include/configs/ge_b1x5v2.h

@@ -12,11 +12,6 @@
 
 #include "mx6_common.h"
 
-#include "imx6_spl.h"
-
-/* PWM */
-#define CONFIG_IMX6_PWM_PER_CLK		66000000
-
 /* UART */
 #define CONFIG_MXC_UART_BASE		UART3_BASE
 
@@ -33,15 +28,12 @@
 #define CONFIG_MXC_USB_FLAGS		0
 #define CONFIG_USBD_HS
 
-/* Video */
-#define CONFIG_IMX_VIDEO_SKIP
-
 /* Memory */
 #define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* Command definition */
 #define CONFIG_EXTRA_ENV_SETTINGS \

diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index d519384..f62b8f1 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h

@@ -92,20 +92,14 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)     /* 256M */
+#define CFG_SYS_BOOTMAPSZ (256 << 20)     /* 256M */
 
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* environment organization */
 
 #define CFG_SYS_FSL_USDHC_NUM	3
 
-/* Framebuffer */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
-#define CONFIG_IMX6_PWM_PER_CLK	66000000
-
 #endif	/* __GE_BX50V3_CONFIG_H */

diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index d2138c2..dd6b22d 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h

@@ -13,8 +13,8 @@
 /* Miscellaneous */
 
 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		(10 * 1024 * 1024)
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		(10 * 1024 * 1024)
 
 /* Network interface */
 #define CONFIG_SH_ETHER_USE_PORT	0

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index a9ef35e..4d0a78c 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h

@@ -13,7 +13,6 @@
 
 /* Falcon Mode - MMC support: args@1MB kernel@2MB */
 
-#include "imx6_spl.h"                  /* common IMX6 SPL configuration */
 #include "mx6_common.h"
 
 /* Serial */
@@ -31,9 +30,7 @@
 /*
  * PMIC
  */
-#define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
-#define CONFIG_POWER_LTC3676
 #define CONFIG_POWER_LTC3676_I2C_ADDR  0x3c
 
 /* Various command support */
@@ -43,20 +40,15 @@
 #define CONFIG_MXC_USB_FLAGS      0
 #define CONFIG_USBD_HS
 
-/* Framebuffer and LCD */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
 /* Miscellaneous configurable options */
-#define CONFIG_HWCONFIG
 
 /* Memory configuration */
 
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /*
  * MTD Command for mtdparts

diff --git a/include/configs/gxp.h b/include/configs/gxp.h
index e3c97b2..2b0b048 100644
--- a/include/configs/gxp.h
+++ b/include/configs/gxp.h

@@ -10,6 +10,6 @@
 #ifndef _GXP_H_
 #define _GXP_H_
 
-#define CONFIG_SYS_SDRAM_BASE   0x40000000
+#define CFG_SYS_SDRAM_BASE   0x40000000
 
 #endif

diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index fe4b02c..211dab4 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h

@@ -17,10 +17,10 @@
 #define CONFIG_TEGRA_ENABLE_UARTD
 
 /* UARTD: keyboard satellite board UART, default */
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 #ifdef CONFIG_TEGRA_ENABLE_UARTA
 /* UARTA: debug board UART */
-#define CONFIG_SYS_NS16550_COM2		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM2		NV_PA_APB_UARTA_BASE
 #endif
 
 /* NAND support */

diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 5e2b50b..4aef0b4 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h

@@ -6,7 +6,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
+#define CFG_SYS_BOOTMAPSZ		(16 << 20)
 
 #define CONFIG_PL011_CLOCK		150000000
 
@@ -14,12 +14,7 @@
  * Miscellaneous configurable options
  */
 
-/* Environment data setup
-*/
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfff88000	/* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE		0x8000		/* NVRAM size */
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_SDRAM_BASE		0x00000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS				\
 	"fdt_high=0x20000000\0"					\

diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 18c1e83..d4280de 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h

@@ -13,8 +13,6 @@
 
 #include <linux/sizes.h>
 
-#define CONFIG_POWER_HI6553
-
 /* Physical Memory Map */
 
 /* CONFIG_TEXT_BASE needs to align with where ATF loads bl33.bin */
@@ -24,16 +22,14 @@
 /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/
 #define PHYS_SDRAM_1_SIZE		0x3EFFFFFF
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CFG_SYS_INIT_RAM_SIZE	0x1000
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE			0xf6801000
 #define GICC_BASE			0xf6802000
 
-#define CONFIG_HIKEY_GPIO
-
 /* Initial environment variables */
 
 /*

diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h
index 973df8e..fad1f98 100644
--- a/include/configs/hikey960.h
+++ b/include/configs/hikey960.h

@@ -16,9 +16,9 @@
 #define PHYS_SDRAM_1			0x00000000
 #define PHYS_SDRAM_1_SIZE		0xC0000000
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CFG_SYS_INIT_RAM_SIZE	0x1000
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE			0xe82b1000

diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h
index 4af845e..59ea896 100644
--- a/include/configs/hsdk-4xd.h
+++ b/include/configs/hsdk-4xd.h

@@ -21,16 +21,14 @@
  * Memory configuration
  */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE		SZ_1G
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE		SZ_1G
 
 /*
  * UART configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		33330000
-#define CONFIG_SYS_NS16550_MEM32
+#define CFG_SYS_NS16550_CLK		33330000
 
 /*
  * Ethernet PHY configuration

diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h
index 0ce65e7..fbfcded 100644
--- a/include/configs/hsdk.h
+++ b/include/configs/hsdk.h

@@ -20,16 +20,14 @@
  * Memory configuration
  */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE		SZ_1G
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE		SZ_1G
 
 /*
  * UART configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		33330000
-#define CONFIG_SYS_NS16550_MEM32
+#define CFG_SYS_NS16550_CLK		33330000
 
 /*
  * Ethernet PHY configuration

diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h
index 1fc45f9..f1ca28b 100644
--- a/include/configs/imgtec_xilfpga.h
+++ b/include/configs/imgtec_xilfpga.h

@@ -21,8 +21,8 @@
  */
 
 /* SDRAM Configuration (for final code, data, stack, heap) */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 Mbytes */
+#define CFG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_SIZE		0x08000000	/* 128 Mbytes */
 
 /*----------------------------------------------------------------------
  * Commands

diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
deleted file mode 100644
index 232f786..0000000
--- a/include/configs/imx27lite-common.h
+++ /dev/null

@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
- *
- * based on:
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- */
-
-#ifndef __IMX27LITE_COMMON_CONFIG_H
-#define __IMX27LITE_COMMON_CONFIG_H
-
-/*
- * SoC Configuration
- */
-#define CONFIG_MX27
-#define CONFIG_MX27_CLK32	32768		/* OSC32K frequency */
-
-/*
- * Lowlevel configuration
- */
-#define SDRAM_ESDCFG_REGISTER_VAL(cas)	\
-		(ESDCFG_TRC(10) |	\
-		ESDCFG_TRCD(3) |	\
-		ESDCFG_TCAS(cas) |	\
-		ESDCFG_TRRD(1) |	\
-		ESDCFG_TRAS(5) |	\
-		ESDCFG_TWR |		\
-		ESDCFG_TMRD(2) |	\
-		ESDCFG_TRP(2) |		\
-		ESDCFG_TXP(3))
-
-#define SDRAM_ESDCTL_REGISTER_VAL	\
-		(ESDCTL_PRCT(0) |	\
-		 ESDCTL_BL |		\
-		 ESDCTL_PWDT(0) |	\
-		 ESDCTL_SREFR(3) |	\
-		 ESDCTL_DSIZ_32 |	\
-		 ESDCTL_COL10 |		\
-		 ESDCTL_ROW13 |		\
-		 ESDCTL_SDE)
-
-#define SDRAM_ALL_VAL		0xf00
-
-#define SDRAM_MODE_REGISTER_VAL	0x33	/* BL: 8, CAS: 3 */
-#define SDRAM_EXT_MODE_REGISTER_VAL	0x1000000
-
-#define MPCTL0_VAL	0x1ef15d5
-
-#define SPCTL0_VAL	0x043a1c09
-
-#define CSCR_VAL	0x33f08107
-
-#define PCDR0_VAL	0x120470c3
-#define PCDR1_VAL	0x03030303
-#define PCCR0_VAL	0xffffffff
-#define PCCR1_VAL	0xfffffffc
-
-#define AIPI1_PSR0_VAL	0x20040304
-#define AIPI1_PSR1_VAL	0xdffbfcfb
-#define AIPI2_PSR0_VAL	0x07ffc200
-#define AIPI2_PSR1_VAL	0xffffffff
-
-/*
- * Memory Info
- */
-/* memtest start address */
-#define PHYS_SDRAM_1		0xA0000000	/* DDR Start */
-#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
-
-/*
- * Serial Driver info
- */
-#define CONFIG_MXC_UART_BASE	UART_BASE_ADDR(1)
-
-/*
- * Flash & Environment
- */
-/* Use buffered writes (~10x faster) */
-/* Use hardware sector protection */
-/* CS2 Base address */
-#define PHYS_FLASH_1			0xc0000000
-/* Flash Base for U-Boot */
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-/* Address and size of Redundant Environment Sector	*/
-
-/*
- * Ethernet
- */
-#define CONFIG_FEC_MXC_PHYADDR		0x1f
-
-/*
- * MTD
- */
-
-/*
- * NAND
- */
-#define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
-#define CONFIG_SYS_NAND_BASE		0xd8000000
-#define CONFIG_MXC_NAND_HWECC
-
-/*
- * U-Boot general configuration
- */
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs}"				\
-		" console=ttymxc0,${baudrate}\0"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"addmisc=setenv bootargs ${bootargs}\0"				\
-	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"		\
-	"kernel_addr_r=a0800000\0"					\
-	"bootfile=" CONFIG_HOSTNAME "/uImage\0"		\
-	"rootpath=/opt/eldk-4.2-arm/arm\0"				\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"run nfsargs addip addtty addmtd addmisc;"		\
-		"bootm\0"						\
-	"bootcmd=run net_nfs\0"						\
-	"load=tftp ${loadaddr} ${u-boot}\0"				\
-	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
-		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
-		" +${filesize};cp.b ${fileaddr} "			\
-		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
-	"upd=run load update\0"						\
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#endif /* __IMX27LITE_COMMON_CONFIG_H */

diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h
index f52367c..36b6b95 100644
--- a/include/configs/imx6-engicam.h
+++ b/include/configs/imx6-engicam.h

@@ -109,9 +109,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* UART */
 #ifdef CONFIG_MXC_UART
@@ -126,25 +126,10 @@
 
 /* NAND */
 #ifdef CONFIG_NAND_MXS
-# define CONFIG_SYS_NAND_BASE		0x40000000
-# define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+# define CFG_SYS_NAND_BASE		0x40000000
+# define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 /* MTD device */
 #endif
 
-/* Falcon Mode */
-#ifdef CONFIG_SPL_OS_BOOT
-/* MMC support: args@1MB kernel@2MB */
-#endif
-
-/* Framebuffer */
-#ifdef CONFIG_VIDEO_IPUV3
-# define CONFIG_IMX_VIDEO_SKIP
-#endif
-
-/* SPL */
-#ifdef CONFIG_SPL
-# include "imx6_spl.h"
-#endif
-
 #endif /* __IMX6_ENGICAM_CONFIG_H */

diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 008fc07..4e23f1a 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h

@@ -11,10 +11,6 @@
 #define CONFIG_MXC_UART_BASE   UART1_BASE
 #define CONSOLE_DEV            "ttymxc0"
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 #include "mx6_common.h"
 
 /* MMC Configs */
@@ -109,15 +105,15 @@
 
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* Environment organization */
 
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE           0x40000000
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_BASE           0x40000000
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 /* USB Configs */
 #ifdef CONFIG_CMD_USB

diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
deleted file mode 100644
index 3afe418..0000000
--- a/include/configs/imx6_spl.h
+++ /dev/null

@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Gateworks Corporation
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-#ifndef __IMX6_SPL_CONFIG_H
-#define __IMX6_SPL_CONFIG_H
-
-#ifdef CONFIG_SPL
-
-/* MMC support */
-
-/* SATA support */
-#if defined(CONFIG_SPL_SATA)
-#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
-#endif
-
-#endif
-
-#endif

diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h
index 909453c..402f83c 100644
--- a/include/configs/imx6dl-mamoj.h
+++ b/include/configs/imx6dl-mamoj.h

@@ -55,11 +55,8 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
-
-/* SPL */
-#include "imx6_spl.h"
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #endif /* __IMX6DL_MAMOJ_CONFIG_H */

diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
index 5025ad9..99da081 100644
--- a/include/configs/imx6q-bosch-acc.h
+++ b/include/configs/imx6q-bosch-acc.h

@@ -85,13 +85,12 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM                      MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE           PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE        IRAM_SIZE
 
 /* SPL */
 #ifdef CONFIG_SPL
-#include "imx6_spl.h"
 
 #ifdef CONFIG_SPL_BUILD
 #define CFG_SYS_FSL_USDHC_NUM 2

diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h
index 46a96f1..2d9d3c3 100644
--- a/include/configs/imx6ulz_smm_m2.h
+++ b/include/configs/imx6ulz_smm_m2.h

@@ -12,9 +12,6 @@
 #include <linux/sizes.h>
 #include <linux/stringify.h>
 
-/* SPL options */
-#include "imx6_spl.h"
-
 #define CONFIG_MXC_UART_BASE		UART4_BASE
 
 #ifndef CONFIG_SPL_BUILD
@@ -66,12 +63,12 @@
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 #define PHYS_SDRAM_SIZE			SZ_128M
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* NAND */
 
-#define CONFIG_SYS_NAND_BASE		0x20000000
+#define CFG_SYS_NAND_BASE		0x20000000
 
 #endif

diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
index caa6a11..76771fd 100644
--- a/include/configs/imx7-cm.h
+++ b/include/configs/imx7-cm.h

@@ -69,9 +69,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM					MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* MMC Config*/
 #define CFG_SYS_FSL_ESDHC_ADDR       USDHC1_BASE_ADDR
@@ -83,7 +83,4 @@
 
 #define CONFIG_USBD_HS
 
-/* SPL */
-#include "imx7_spl.h"
-
 #endif	/* __CONFIG_H */

diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h
deleted file mode 100644
index 362b980..0000000
--- a/include/configs/imx7_spl.h
+++ /dev/null

@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * SPL definitions for the i.MX7 SPL
- *
- * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#ifndef __IMX7_SPL_CONFIG_H
-#define __IMX7_SPL_CONFIG_H
-
-#ifdef CONFIG_SPL
-
-/* MMC support */
-
-#endif /* CONFIG_SPL */
-
-#endif /* __IMX7_SPL_CONFIG_H */

diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
index 917d567..c228cf7 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h

@@ -11,7 +11,7 @@
 #include <asm/arch/imx-regs.h>
 #include <config_distro_bootcmd.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
@@ -123,11 +123,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x80000
 
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
 

diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index 8e08899..03325e6 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h

@@ -9,7 +9,7 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
@@ -71,10 +71,10 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        0x200000
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE		0x80000000 /* 2GB DDR */
 

diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index dd9f93f..80321cf 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h

@@ -18,10 +18,10 @@
 #endif
 
 /* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x200000
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x200000
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x40000000 /* Minimum 1 GiB DDR */
 

diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index f1d1c1c..8a694c8 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h

@@ -15,10 +15,10 @@
 #define UBOOT_ITB_OFFSET_FSPI  \
 	(UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE)
 #ifdef CONFIG_FSPI_CONF_HEADER
-#define CONFIG_SYS_UBOOT_BASE  \
+#define CFG_SYS_UBOOT_BASE  \
 	(QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI)
 #else
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 #endif
 
@@ -53,11 +53,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        0x200000
 
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
 

diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h
index 9cdba70..41ab930 100644
--- a/include/configs/imx8mm_icore_mx8mm.h
+++ b/include/configs/imx8mm_icore_mx8mm.h

@@ -10,7 +10,7 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
@@ -38,10 +38,10 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 
 /* SDRAM configuration */
 #define PHYS_SDRAM                      0x40000000

diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index 0653563..28ce834 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h

@@ -9,7 +9,7 @@
 #include <asm/arch/imx-regs.h>
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
@@ -29,10 +29,10 @@
 	"splblk=0x42\0" \
 	BOOTENV
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 
 /* SDRAM configuration */
 #define PHYS_SDRAM                      0x40000000

diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 0ae3da1..85fd5e2 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h

@@ -9,7 +9,7 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 /* Initial environment variables */
@@ -75,10 +75,10 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        0x200000
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR)
 #define PHYS_SDRAM_SIZE		0x80000000 /* 2GB DDR */

diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h
index a2323bd..a768ff3 100644
--- a/include/configs/imx8mn_bsh_smm_s2.h
+++ b/include/configs/imx8mn_bsh_smm_s2.h

@@ -44,6 +44,6 @@
 
 /* NAND */
 
-#define CONFIG_SYS_NAND_BASE		0x20000000
+#define CFG_SYS_NAND_BASE		0x20000000
 
 #endif /* __IMX8MN_BSH_SMM_S2_H */

diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h
index d6959ac..204fc4b 100644
--- a/include/configs/imx8mn_bsh_smm_s2_common.h
+++ b/include/configs/imx8mn_bsh_smm_s2_common.h

@@ -10,7 +10,7 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #define MEM_LAYOUT_ENV_SETTINGS \
@@ -23,10 +23,10 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	SZ_512K
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 
 #endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */

diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index 9c75e3e..024b86c 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h

@@ -10,7 +10,7 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #define BOOT_TARGET_DEVICES(func) \
@@ -45,11 +45,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        0x200000
 
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
 

diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h
index a484d91..4633843 100644
--- a/include/configs/imx8mn_var_som.h
+++ b/include/configs/imx8mn_var_som.h

@@ -10,7 +10,7 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #define BOOT_TARGET_DEVICES(func) \
@@ -43,10 +43,10 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	SZ_512K
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			SZ_1G /* 1GB DDR */
 

diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h
index d5252ab..a585cbf 100644
--- a/include/configs/imx8mn_venice.h
+++ b/include/configs/imx8mn_venice.h

@@ -9,7 +9,7 @@
 #include <asm/arch/imx-regs.h>
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 /* Enable Distro Boot */
@@ -23,10 +23,10 @@
 	"splblk=0x40\0" \
 	BOOTENV
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 
 /* SDRAM configuration */
 #define PHYS_SDRAM                      0x40000000

diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h
index bf87825..5443022 100644
--- a/include/configs/imx8mp_dhcom_pdk2.h
+++ b/include/configs/imx8mp_dhcom_pdk2.h

@@ -11,10 +11,10 @@
 #include <asm/arch/imx-regs.h>
 
 /* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x200000
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x200000
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x20000000 /* Minimum 512 MiB DDR */
 

diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 1b533e2..738677f 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h

@@ -10,7 +10,7 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
@@ -50,12 +50,12 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x80000
 
 
 /* Totally 2GB DDR */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000
 

diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h
index 7986d20..d67bad8 100644
--- a/include/configs/imx8mp_icore_mx8mp.h
+++ b/include/configs/imx8mp_icore_mx8mp.h

@@ -11,7 +11,7 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
@@ -52,11 +52,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x80000
 
 /* Totally 2GB DDR */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000
 

diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index 5be4609..58f7dc6 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h

@@ -12,7 +12,7 @@
 #include <asm/arch/imx-regs.h>
 #include <config_distro_bootcmd.h>
 
-#define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 /* GUIDs for capsule updatable firmware images */
 #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \
@@ -131,12 +131,12 @@
 		"fi;\0"
 
 /* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x80000
 
 
 /* Totally 6GB or 4G DDR */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
 #define PHYS_SDRAM_SIZE			0xC0000000	/* 3 GB */
@@ -166,7 +166,7 @@
 #ifdef CONFIG_NAND_MXS
 
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CFG_SYS_NAND_BASE           0x20000000
 #endif /* CONFIG_NAND_MXS */
 
 #endif /* __IMX8MP_RSB3720_H */

diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h
index b1c213c..e79aa57 100644
--- a/include/configs/imx8mp_venice.h
+++ b/include/configs/imx8mp_venice.h

@@ -9,7 +9,7 @@
 #include <asm/arch/imx-regs.h>
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 /* Enable Distro Boot */
@@ -23,10 +23,10 @@
 	"splblk=0x40\0" \
 	BOOTENV
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 
 /* SDRAM configuration */
 #define PHYS_SDRAM                      0x40000000

diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h
index 4b2107e..4df98e3 100644
--- a/include/configs/imx8mq_cm.h
+++ b/include/configs/imx8mq_cm.h

@@ -46,11 +46,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        0x80000
 
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE					0x40000000 /* 1 GB DDR */
 

diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 2d4c8d7..688c0bf 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h

@@ -18,7 +18,6 @@
 #define CONFIG_MALLOC_F_ADDR		0x182000
 /* For RAW image gives a error info not panic */
 
-#define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
 #endif
 
@@ -52,11 +51,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        0x80000
 
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0xC0000000 /* 3GB DDR */
 

diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
index 1905e53..3b4cd65 100644
--- a/include/configs/imx8mq_phanbell.h
+++ b/include/configs/imx8mq_phanbell.h

@@ -84,11 +84,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        0x80000
 
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0x40000000 /* 1GB DDR */
 

diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index 7f6d59d..f1f907f 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h

@@ -103,7 +103,7 @@
 
 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */

diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h
index 67f19bc..2e2e5ed 100644
--- a/include/configs/imx8qm_rom7720.h
+++ b/include/configs/imx8qm_rom7720.h

@@ -10,7 +10,7 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+#define CFG_SYS_BOOTMAPSZ		(256 << 20)
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 #define USDHC1_BASE_ADDR		0x5B010000
 #define USDHC2_BASE_ADDR		0x5B020000
@@ -108,7 +108,7 @@
  */
 #define CFG_SYS_FSL_USDHC_NUM	3
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */

diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index 567351f..d75b8bf 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h

@@ -103,17 +103,13 @@
 
 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
 /* LPDDR4 board total DDR is 3GB */
 #define PHYS_SDRAM_2_SIZE		0x40000000	/* 1 GB */
 
-#ifndef CONFIG_DM_PCA953X
-#define CONFIG_PCA953X
-#endif
-
 /* Misc configuration */
 
 #endif /* __IMX8QXP_MEK_H */

diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h
index 7bf0ce7..d313bdc 100644
--- a/include/configs/imx8ulp_evk.h
+++ b/include/configs/imx8ulp_evk.h

@@ -9,7 +9,7 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_MALLOC_F_ADDR		0x22040000
@@ -50,11 +50,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
+#define CFG_SYS_INIT_RAM_ADDR	0x80000000
+#define CFG_SYS_INIT_RAM_SIZE	0x80000
 
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM			0x80000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
 

diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index b281466..895c50f 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h

@@ -10,7 +10,7 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
@@ -124,10 +124,10 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CFG_SYS_INIT_RAM_ADDR        0x80000000
+#define CFG_SYS_INIT_RAM_SIZE        0x200000
 
-#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CFG_SYS_SDRAM_BASE           0x80000000
 #define PHYS_SDRAM                      0x80000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
 

diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h
index a2c0048..e180387 100644
--- a/include/configs/imxrt1020-evk.h
+++ b/include/configs/imxrt1020-evk.h

@@ -22,6 +22,6 @@
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_UBOOT_START		0x800023FD
+#define CFG_SYS_UBOOT_START		0x800023FD
 
 #endif /* __IMXRT1020_EVK_H */

diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
index d1a7dab..8422867 100644
--- a/include/configs/imxrt1050-evk.h
+++ b/include/configs/imxrt1050-evk.h

@@ -29,6 +29,6 @@
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_UBOOT_START		0x800023FD
+#define CFG_SYS_UBOOT_START		0x800023FD
 
 #endif /* __IMXRT1050_EVK_H */

diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h
index 2459fe2..f834290 100644
--- a/include/configs/imxrt1170-evk.h
+++ b/include/configs/imxrt1170-evk.h

@@ -23,7 +23,7 @@
 #define DMAMEM_BASE			(PHYS_SDRAM + PHYS_SDRAM_SIZE - \
 					 DMAMEM_SZ_ALL)
 /* For SPL */
-#define CONFIG_SYS_UBOOT_START		0x202403FD
+#define CFG_SYS_UBOOT_START		0x202403FD
 /* For SPL ends */
 
 #endif /* __IMXRT1170_EVK_H */

diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 512e0e6..7a55c6a 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h

@@ -6,7 +6,7 @@
  * Common ARM Integrator configuration settings
  */
 
-#define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1 */
+#define CFG_SYS_TIMERBASE		0x13000100	/* Timer1 */
 
 /*
  * The ARM boot monitor initializes the board.
@@ -30,7 +30,7 @@
  */
 #define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM_1
 
 /*
  * FLASH and environment organization
@@ -41,6 +41,6 @@
  * - SIB block
  * - U-Boot environment
  */
-#define CONFIG_SYS_FLASH_BASE		0x24000000
+#define CFG_SYS_FLASH_BASE		0x24000000
 
 /* Timeout values in ticks */

diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index c8457d9..6bee098 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h

@@ -17,10 +17,10 @@
 #include "integrator-common.h"
 
 /* Integrator/AP-specific configuration */
-#define CONFIG_SYS_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
+#define CFG_SYS_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
 
 /* Flash settings */
-#define CONFIG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */
+#define CFG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */
 
 /*-----------------------------------------------------------------------
  * PCI definitions

diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index bf09510..25bb41e 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h

@@ -17,7 +17,7 @@
 #include "integrator-common.h"
 
 /* Integrator CP-specific configuration */
-#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
+#define CFG_SYS_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
 
 #define CONFIG_SERVERIP 192.168.1.100
 #define CONFIG_IPADDR 192.168.1.104

diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h
index a2e50c3..5a769e0 100644
--- a/include/configs/iot_devkit.h
+++ b/include/configs/iot_devkit.h

@@ -32,12 +32,12 @@
  *   :           :
  *   :          Specified explicitly by CONFIG_CUSTOM_SYS_INIT_SP_ADDR
  *   :
- *  Specified explicitly by CONFIG_SYS_SDRAM_BASE
+ *  Specified explicitly by CFG_SYS_SDRAM_BASE
  *
  *  NOTES:
  *    - Stack starts from CONFIG_CUSTOM_SYS_INIT_SP_ADDR and grows down,
- *      i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing
- *      that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on
+ *      i.e. towards CFG_SYS_SDRAM_BASE but nothing stops it from crossing
+ *      that CFG_SYS_SDRAM_BASE in which case data won't be really saved on
  *      stack any longer and values popped from stack will contain garbage
  *      leading to unexpected behavior, typically but not limited to:
  *        - "Returning" back to bogus caller function
@@ -50,16 +50,16 @@
 #define DCCM_BASE			0x80000000
 #define DCCM_SIZE			SZ_128K
 
-#define CONFIG_SYS_SDRAM_BASE		DCCM_BASE
-#define CONFIG_SYS_SDRAM_SIZE		DCCM_SIZE
+#define CFG_SYS_SDRAM_BASE		DCCM_BASE
+#define CFG_SYS_SDRAM_SIZE		DCCM_SIZE
 
 #define ROM_BASE			CONFIG_SYS_MONITOR_BASE
 #define ROM_SIZE			SZ_256K
 
 #define RAM_DATA_BASE			SYS_INIT_SP_ADDR
-#define RAM_DATA_SIZE			CONFIG_SYS_SDRAM_SIZE - \
+#define RAM_DATA_SIZE			CFG_SYS_SDRAM_SIZE - \
 					(SYS_INIT_SP_ADDR - \
-					CONFIG_SYS_SDRAM_BASE) - \
+					CFG_SYS_SDRAM_BASE) - \
 					CONFIG_SYS_MALLOC_LEN - \
 					CONFIG_ENV_SIZE
 #endif /* _CONFIG_IOT_DEVKIT_H_ */

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 9f54f25..e66f994 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h

@@ -16,16 +16,16 @@
 #include <environment/ti/k3_dfu.h>
 
 /* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1		0x880000000
+#define CFG_SYS_SDRAM_BASE1		0x880000000
 /* FLASH Configuration */
-#define CONFIG_SYS_FLASH_BASE		0x000000000
+#define CFG_SYS_FLASH_BASE		0x000000000
 
 /* SPL Loader Configuration */
 #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
-#define CONFIG_SYS_UBOOT_BASE		0x50280000
+#define CFG_SYS_UBOOT_BASE		0x50280000
 /* Image load address in RAM for DFU boot*/
 #else
-#define CONFIG_SYS_UBOOT_BASE		0x50080000
+#define CFG_SYS_UBOOT_BASE		0x50080000
 #endif
 
 /* HyperFlash related configuration */

diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index 932d7d3..ab204c6 100644
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h

@@ -17,14 +17,14 @@
 #include <environment/ti/k3_dfu.h>
 
 /* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1		0x880000000
+#define CFG_SYS_SDRAM_BASE1		0x880000000
 
 /* SPL Loader Configuration */
 #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
-#define CONFIG_SYS_UBOOT_BASE		0x50280000
+#define CFG_SYS_UBOOT_BASE		0x50280000
 /* Image load address in RAM for DFU boot*/
 #else
-#define CONFIG_SYS_UBOOT_BASE		0x50080000
+#define CFG_SYS_UBOOT_BASE		0x50080000
 #endif
 
 /* U-Boot general configuration */

diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index 69aa55f..b846889 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h

@@ -16,7 +16,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 

diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 9b25c34..bbc58be 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h

@@ -36,9 +36,6 @@
 
 #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
 
-/* NAND Configuration */
-#define CONFIG_SYS_NAND_PAGE_2K
-
 /* Network */
 #define CONFIG_KSNET_NETCP_V1_5
 #define CONFIG_KSNET_CPSW_NUM_PORTS	9

diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 887fda9..bb91751 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h

@@ -50,9 +50,6 @@
 	"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
 	"name_fs=arago-base-tisdk-image-k2g-evm.cpio\0"
 
-/* NAND Configuration */
-#define CONFIG_SYS_NAND_PAGE_2K
-
 /* Network */
 #define CONFIG_KSNET_NETCP_V1_5
 #define CONFIG_KSNET_CPSW_NUM_PORTS	2

diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index cfc34c7..68cbe98 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h

@@ -36,9 +36,6 @@
 
 #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
 
-/* NAND Configuration */
-#define CONFIG_SYS_NAND_PAGE_2K
-
 /* Network */
 #define CONFIG_KSNET_NETCP_V1_0
 #define CONFIG_KSNET_CPSW_NUM_PORTS	5

diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 65988ff..a18158a 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h

@@ -36,9 +36,6 @@
 
 #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
 
-/* NAND Configuration */
-#define CONFIG_SYS_NAND_PAGE_4K
-
 /* Network */
 #define CONFIG_KSNET_NETCP_V1_5
 #define CONFIG_KSNET_CPSW_NUM_PORTS	5

diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 35cf27a..cc5ec21 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h

@@ -13,7 +13,7 @@
  * Miscellaneous configurable options
  */
 
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
 #define CONFIG_KM_DEF_ENV_BOOTPARAMS \

diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h
index 888bb29..f64c0ee 100644
--- a/include/configs/km/km-mpc832x.h
+++ b/include/configs/km/km-mpc832x.h

@@ -1,34 +1,34 @@
 /*
  * System IO Config
  */
-#define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
+#define CFG_SYS_SICRL	SICRL_IRQ_CKS
 
-#define CONFIG_SYS_DDRCDR (\
+#define CFG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_PZ_MAXZ | \
 	DDRCDR_NZ_MAXZ | \
 	DDRCDR_M_ODR)
 
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+#define CFG_SYS_DDR_CS0_BNDS		0x0000007f
+#define CFG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 					 SDRAM_CFG_32_BE | \
 					 SDRAM_CFG_SREN | \
 					 SDRAM_CFG_HSE)
 
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+#define CFG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CFG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CFG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+#define CFG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
 					 CSCONFIG_ODT_WR_CFG | \
 					 CSCONFIG_ROW_BIT_13 | \
 					 CSCONFIG_COL_BIT_10)
 
-#define CONFIG_SYS_DDR_MODE	0x47860242
-#define CONFIG_SYS_DDR_MODE2	0x8080c000
+#define CFG_SYS_DDR_MODE	0x47860242
+#define CFG_SYS_DDR_MODE2	0x8080c000
 
-#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+#define CFG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
@@ -37,7 +37,7 @@
 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
 				 (0 << TIMING_CFG0_RWT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
+#define CFG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
 				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
@@ -46,7 +46,7 @@
 				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+#define CFG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
@@ -54,7 +54,7 @@
 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 				 (5 << TIMING_CFG2_CPO_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CFG_SYS_DDR_TIMING_3	0x00000000
 
-#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+#define CFG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CFG_SYS_KMBEC_FPGA_SIZE	128

diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h
index 92e046d..5c9f912 100644
--- a/include/configs/km/km-mpc8360.h
+++ b/include/configs/km/km-mpc8360.h

@@ -1,6 +1,6 @@
 /* KMBEC FPGA (PRIO) */
-#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE	64
+#define CFG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CFG_SYS_KMBEC_FPGA_SIZE	64
 
 /*
  * High Level Configuration Options
@@ -9,34 +9,34 @@
 /*
  * System IO Setup
  */
-#define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
+#define CFG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
 
 /**
  * DDR RAM settings
  */
-#define CONFIG_SYS_DDR_SDRAM_CFG (\
+#define CFG_SYS_DDR_SDRAM_CFG (\
 	SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 	SDRAM_CFG_SREN | \
 	SDRAM_CFG_HSE)
 
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CFG_SYS_DDR_SDRAM_CFG2	0x00401000
 
-#define CONFIG_SYS_DDR_CLK_CNTL (\
+#define CFG_SYS_DDR_CLK_CNTL (\
 	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 
-#define CONFIG_SYS_DDR_INTERVAL (\
+#define CFG_SYS_DDR_INTERVAL (\
 	(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 	(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
 
-#define CONFIG_SYS_DDR_CS0_BNDS			0x0000007f
+#define CFG_SYS_DDR_CS0_BNDS			0x0000007f
 
-#define CONFIG_SYS_DDRCDR (\
+#define CFG_SYS_DDRCDR (\
 	DDRCDR_EN | \
 	DDRCDR_Q_DRN)
-#define CONFIG_SYS_DDR_MODE		0x47860452
-#define CONFIG_SYS_DDR_MODE2		0x8080c000
+#define CFG_SYS_DDR_MODE		0x47860452
+#define CFG_SYS_DDR_MODE2		0x8080c000
 
-#define CONFIG_SYS_DDR_TIMING_0 (\
+#define CFG_SYS_DDR_TIMING_0 (\
 	(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 	(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
@@ -46,7 +46,7 @@
 	(0 << TIMING_CFG0_WRT_SHIFT) | \
 	(0 << TIMING_CFG0_RWT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
+#define CFG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
 				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
@@ -55,7 +55,7 @@
 				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_2 (\
+#define CFG_SYS_DDR_TIMING_2 (\
 	(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 	(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
@@ -64,12 +64,11 @@
 	(5 << TIMING_CFG2_CPO_SHIFT) | \
 	(0 << TIMING_CFG2_ADD_LAT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_3			0x00000000
+#define CFG_SYS_DDR_TIMING_3			0x00000000
 
 /* EEprom support */
 
 /*
  * PAXE on the local bus CS3
  */
-#define CONFIG_SYS_PAXE_BASE		0xA0000000
-#define CONFIG_SYS_PAXE_SIZE		256
+#define CFG_SYS_PAXE_BASE		0xA0000000

diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index 181ed1b..840a4d5 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h

@@ -7,10 +7,9 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
+#define CFG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+#define CFG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 
 #define CFG_83XX_DDR_USES_CS0
@@ -18,20 +17,20 @@
 /*
  * Manually set up DDR parameters
  */
-#define CONFIG_SYS_SDRAM_SIZE		0x80000000 /* 2048 MiB */
+#define CFG_SYS_SDRAM_SIZE		0x80000000 /* 2048 MiB */
 
 /*
  * The reserved memory
  */
-#define CONFIG_SYS_FLASH_BASE		0xF0000000
+#define CFG_SYS_FLASH_BASE		0xF0000000
 
 /* Reserve 768 kB for Mon */
 
 /*
  * Initial RAM Base Address Setup
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
 /*
  * Init Local Bus Memory Controller:
  *
@@ -45,21 +44,20 @@
 /*
  * FLASH on the Local Bus
  */
-#define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
+#define CFG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
 
 /* I2C */
-#define CONFIG_SYS_NUM_I2C_BUSES	4
-#define CONFIG_SYS_I2C_MAX_HOPS		1
-#define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
+#define CFG_SYS_NUM_I2C_BUSES	4
+#define CFG_SYS_I2C_MAX_HOPS		1
+#define CFG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
 		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 		{1, {I2C_NULL_HOP} } }
 
 #if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
+#define CFG_SYS_NAND_BASE		CFG_SYS_KMBEC_FPGA_BASE
 #endif
 
 /*
@@ -67,7 +65,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+#define CFG_SYS_BOOTMAPSZ		(8 << 20)
 
 /*
  * Environment

diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index 0613b77..dfa81c0 100644
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h

@@ -9,8 +9,8 @@
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"
 
-#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
 #define CONFIG_PRAM			((CONFIG_KM_PNVRAM + \
 					  CONFIG_KM_PHRAM + \
@@ -19,75 +19,75 @@
 #define PHYS_SDRAM			0x80000000
 #define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 #define SPD_EEPROM_ADDRESS		0x54
 
 /* POST memory regions test */
-#define CONFIG_POST			(CONFIG_SYS_POST_MEM_REGIONS)
-#define CONFIG_POST_EXTERNAL_WORD_FUNCS
+#define CFG_POST			(CFG_SYS_POST_MEM_REGIONS)
+#define CFG_POST_EXTERNAL_WORD_FUNCS
 
 /*
  * IFC Definitions
  */
 /* NOR Flash Definitions */
-#define CONFIG_SYS_FLASH_BASE		0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE		0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
 
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_TE | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(64 * 1024 * 1024)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(64 * 1024 * 1024)
 
-#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_AVD_TGL_PGM_EN | \
+#define CFG_SYS_NOR_CSOR		(CSOR_NOR_AVD_TGL_PGM_EN | \
 					CSOR_NOR_ADM_SHIFT(0x4) | \
 					CSOR_NOR_NOR_MODE_ASYNC_NOR | \
 					CSOR_NOR_TRHZ_20 | \
 					CSOR_NOR_BCTLD)
-#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x1) | \
+#define CFG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x1) | \
 					FTIM0_NOR_TEADC(0x7) | \
 					FTIM0_NOR_TAVDS(0x0) | \
 					FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x1) | \
+#define CFG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x1) | \
 					FTIM1_NOR_TRAD_NOR(0x21) | \
 					FTIM1_NOR_TSEQRAD_NOR(0x21))
-#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x1) | \
+#define CFG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x1) | \
 					FTIM2_NOR_TCH(0x1) | \
 					FTIM2_NOR_TWPH(0x6) | \
 					FTIM2_NOR_TWP(0xb))
-#define CONFIG_SYS_NOR_FTIM3		0
+#define CFG_SYS_NOR_FTIM3		0
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE_PHYS }
 
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
 
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
 
 /* NAND Flash Definitions */
-#define CONFIG_SYS_NAND_BASE		0x68000000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x68000000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
 				CSPR_PORT_SIZE_8 | \
 				CSPR_TE | \
 				CSPR_MSEL_NAND | \
 				CSPR_V)
-#define CONFIG_SYS_NAND_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR		(CSOR_NAND_ECC_ENC_EN \
+#define CFG_SYS_NAND_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR		(CSOR_NAND_ECC_ENC_EN \
 					| CSOR_NAND_ECC_DEC_EN \
 					| CSOR_NAND_ECC_MODE_4 \
 					| CSOR_NAND_RAL_3 \
@@ -97,87 +97,78 @@
 					| CSOR_NAND_TRHZ_40 \
 					| CSOR_NAND_BCTLD)
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x3) | \
 					FTIM0_NAND_TWP(0x8) | \
 					FTIM0_NAND_TWCHT(0x3) | \
 					FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1e) | \
 					FTIM1_NAND_TWBE(0x1e) | \
 					FTIM1_NAND_TRR(0x6) | \
 					FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x9) | \
 					FTIM2_NAND_TREH(0x5) | \
 					FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3		(FTIM3_NAND_TWW(0x1e))
+#define CFG_SYS_NAND_FTIM3		(FTIM3_NAND_TWW(0x1e))
 
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 /* QRIO FPGA Definitions */
-#define CONFIG_SYS_QRIO_BASE		0x70000000
-#define CONFIG_SYS_QRIO_BASE_PHYS	CONFIG_SYS_QRIO_BASE
+#define CFG_SYS_QRIO_BASE		0x70000000
+#define CFG_SYS_QRIO_BASE_PHYS	CFG_SYS_QRIO_BASE
 
-#define CONFIG_SYS_CSPR2_EXT		(0x00)
-#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+#define CFG_SYS_CSPR2_EXT		(0x00)
+#define CFG_SYS_CSPR2	(CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_TE | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_AMASK2		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR2		(CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK2		IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR2		(CSOR_GPCM_ADM_SHIFT(0x4) | \
 					CSOR_GPCM_TRHZ_20 | \
 					CSOR_GPCM_BCTLD)
-#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x2) | \
+#define CFG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x2) | \
 					FTIM0_GPCM_TEADC(0x8) | \
 					FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x2) | \
 					FTIM1_GPCM_TRAD(0x6))
-#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x1) | \
+#define CFG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x1) | \
 					FTIM2_GPCM_TCH(0x1) | \
 					FTIM2_GPCM_TWP(0x7))
-#define CONFIG_SYS_CS2_FTIM3		0x04000000
+#define CFG_SYS_CS2_FTIM3		0x04000000
 
 /*
  * Serial Port
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CFG_SYS_NS16550_CLK		get_serial_clock()
 
 /*
  * I2C
  */
 
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_MAX_HOPS		1
-#define CONFIG_SYS_NUM_I2C_BUSES	3
+#define CFG_SYS_I2C_MAX_HOPS		1
+#define CFG_SYS_NUM_I2C_BUSES	3
 #define I2C_MUX_PCA_ADDR		0x70
 #define I2C_MUX_CH_DEFAULT		0x0
-#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+#define CFG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 					{1, {I2C_NULL_HOP}                 }, \
 				}
 
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
-#define CONFIG_FSL_DEVICE_DISABLE
 
 /*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_LS102XA_STREAM_ID
-
-/*
  * Environment
  */
 
@@ -206,12 +197,12 @@
 		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && "	\
 		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
 		" +${filesize}\0"					\
-	"update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	"update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE)	\
 		" +${filesize} && "					\
-		"erase " __stringify(CONFIG_SYS_FLASH_BASE)		\
+		"erase " __stringify(CFG_SYS_FLASH_BASE)		\
 		" +${filesize} && "					\
 		"cp.b ${load_addr_r} "					\
-		__stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "	\
+		__stringify(CFG_SYS_FLASH_BASE) " ${filesize} && "	\
 		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
 		" +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0"		\
 	"set_fdthigh=true\0"			\
@@ -239,6 +230,6 @@
 	"ethrotate=no\0"						\
 	""
 
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Increase map for Linux */
+#define CFG_SYS_BOOTMAPSZ	(256 << 20) /* Increase map for Linux */
 
 #endif

diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 2e1459e..527f038 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h

@@ -25,10 +25,10 @@
 #define SYS_LAWAPP_BASE_PHYS	(0xf00000000ull | SYS_LAWAPP_BASE)
 
 /* Application IFC CS4 MRAM */
-#define CONFIG_SYS_MRAM_BASE		SYS_LAWAPP_BASE
+#define CFG_SYS_MRAM_BASE		SYS_LAWAPP_BASE
 #define SYS_MRAM_BASE_PHYS	SYS_LAWAPP_BASE_PHYS
 #define SYS_MRAM_CSPR_EXT	(0x0f)
-#define SYS_MRAM_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
+#define SYS_MRAM_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \
 				CSPR_PORT_SIZE_8 | /* 8 bit */		\
 				CSPR_MSEL_GPCM   | /* msel = gpcm */	\
 				CSPR_V /* bank is valid */)
@@ -44,14 +44,14 @@
 			FTIM2_GPCM_TCH(0x2)  | \
 			FTIM2_GPCM_TWP(0x8))
 #define SYS_MRAM_FTIM3	0x04000000
-#define CONFIG_SYS_CSPR4_EXT	SYS_MRAM_CSPR_EXT
-#define CONFIG_SYS_CSPR4	SYS_MRAM_CSPR
-#define CONFIG_SYS_AMASK4	SYS_MRAM_AMASK
-#define CONFIG_SYS_CSOR4	SYS_MRAM_CSOR
-#define CONFIG_SYS_CS4_FTIM0	SYS_MRAM_FTIM0
-#define CONFIG_SYS_CS4_FTIM1	SYS_MRAM_FTIM1
-#define CONFIG_SYS_CS4_FTIM2	SYS_MRAM_FTIM2
-#define CONFIG_SYS_CS4_FTIM3	SYS_MRAM_FTIM3
+#define CFG_SYS_CSPR4_EXT	SYS_MRAM_CSPR_EXT
+#define CFG_SYS_CSPR4	SYS_MRAM_CSPR
+#define CFG_SYS_AMASK4	SYS_MRAM_AMASK
+#define CFG_SYS_CSOR4	SYS_MRAM_CSOR
+#define CFG_SYS_CS4_FTIM0	SYS_MRAM_FTIM0
+#define CFG_SYS_CS4_FTIM1	SYS_MRAM_FTIM1
+#define CFG_SYS_CS4_FTIM2	SYS_MRAM_FTIM2
+#define CFG_SYS_CS4_FTIM3	SYS_MRAM_FTIM3
 
 /* Application IFC CS6: BFTIC */
 #define SYS_BFTIC_BASE		0xd0000000
@@ -73,20 +73,20 @@
 				FTIM2_GPCM_TCH(0x1) | \
 				FTIM2_GPCM_TWP(0x12))
 #define SYS_BFTIC_FTIM3	0x04000000
-#define CONFIG_SYS_CSPR6_EXT	SYS_BFTIC_CSPR_EXT
-#define CONFIG_SYS_CSPR6	SYS_BFTIC_CSPR
-#define CONFIG_SYS_AMASK6	SYS_BFTIC_AMASK
-#define CONFIG_SYS_CSOR6	SYS_BFTIC_CSOR
-#define CONFIG_SYS_CS6_FTIM0	SYS_BFTIC_FTIM0
-#define CONFIG_SYS_CS6_FTIM1	SYS_BFTIC_FTIM1
-#define CONFIG_SYS_CS6_FTIM2	SYS_BFTIC_FTIM2
-#define CONFIG_SYS_CS6_FTIM3	SYS_BFTIC_FTIM3
+#define CFG_SYS_CSPR6_EXT	SYS_BFTIC_CSPR_EXT
+#define CFG_SYS_CSPR6	SYS_BFTIC_CSPR
+#define CFG_SYS_AMASK6	SYS_BFTIC_AMASK
+#define CFG_SYS_CSOR6	SYS_BFTIC_CSOR
+#define CFG_SYS_CS6_FTIM0	SYS_BFTIC_FTIM0
+#define CFG_SYS_CS6_FTIM1	SYS_BFTIC_FTIM1
+#define CFG_SYS_CS6_FTIM2	SYS_BFTIC_FTIM2
+#define CFG_SYS_CS6_FTIM3	SYS_BFTIC_FTIM3
 
 /* Application IFC CS7 PAXE */
-#define CONFIG_SYS_PAXE_BASE		0xd8000000
-#define SYS_PAXE_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_PAXE_BASE)
+#define CFG_SYS_PAXE_BASE		0xd8000000
+#define SYS_PAXE_BASE_PHYS	(0xf00000000ull | CFG_SYS_PAXE_BASE)
 #define SYS_PAXE_CSPR_EXT	(0x0f)
-#define SYS_PAXE_CSPR  (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
+#define SYS_PAXE_CSPR  (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \
 				CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
 				CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
 				CSPR_V)            /* valid */
@@ -102,14 +102,14 @@
 			FTIM2_GPCM_TCH(0x1) | \
 			FTIM2_GPCM_TWP(0x12))
 #define SYS_PAXE_FTIM3	0x04000000
-#define CONFIG_SYS_CSPR7_EXT	SYS_PAXE_CSPR_EXT
-#define CONFIG_SYS_CSPR7	SYS_PAXE_CSPR
-#define CONFIG_SYS_AMASK7	SYS_PAXE_AMASK
-#define CONFIG_SYS_CSOR7	SYS_PAXE_CSOR
-#define CONFIG_SYS_CS7_FTIM0	SYS_PAXE_FTIM0
-#define CONFIG_SYS_CS7_FTIM1	SYS_PAXE_FTIM1
-#define CONFIG_SYS_CS7_FTIM2	SYS_PAXE_FTIM2
-#define CONFIG_SYS_CS7_FTIM3	SYS_PAXE_FTIM3
+#define CFG_SYS_CSPR7_EXT	SYS_PAXE_CSPR_EXT
+#define CFG_SYS_CSPR7	SYS_PAXE_CSPR
+#define CFG_SYS_AMASK7	SYS_PAXE_AMASK
+#define CFG_SYS_CSOR7	SYS_PAXE_CSOR
+#define CFG_SYS_CS7_FTIM0	SYS_PAXE_FTIM0
+#define CFG_SYS_CS7_FTIM1	SYS_PAXE_FTIM1
+#define CFG_SYS_CS7_FTIM2	SYS_PAXE_FTIM2
+#define CFG_SYS_CS7_FTIM3	SYS_PAXE_FTIM3
 
 /* PRST */
 #define KM_BFTIC4_RST		0
@@ -136,7 +136,7 @@
 
 #define CONFIG_RESET_VECTOR_ADDRESS	0xebfffffc
 
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CFG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 
 /* Environment in parallel NOR-Flash */
 #define CONFIG_ENV_TOTAL_SIZE		0x040000
@@ -145,28 +145,28 @@
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0		L2CSR0_L2E
 
 /* POST memory regions test */
-#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
+#define CFG_POST CFG_SYS_POST_MEM_REGIONS
 
 /*
  *  Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR		0xFFFC0000
 
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#define CFG_SYS_DCSRBAR		0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS		0xf00000000ull
 
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 #define SPD_EEPROM_ADDRESS	0x54
-#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
 
 /******************************************************************************
  * (PRAM usage)
@@ -189,60 +189,60 @@
  * IFC Definitions
  */
 /* NOR flash on IFC CS0 */
-#define CONFIG_SYS_FLASH_BASE		0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | \
-					CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE		0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | \
+					CFG_SYS_FLASH_BASE)
 
-#define CONFIG_SYS_NOR_CSPR_EXT	(0x0f)
-#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+#define CFG_SYS_NOR_CSPR_EXT	(0x0f)
+#define CFG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
 				CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
 				0x00000010 |	    /* drive TE high */\
 				CSPR_MSEL_NOR |	    /* MSEL = NOR */\
 				CSPR_V)		    /* valid */
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64 * 1024 * 1024) /* 64MB */
-#define CONFIG_SYS_NOR_CSOR	(CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
+#define CFG_SYS_NOR_AMASK	IFC_AMASK(64 * 1024 * 1024) /* 64MB */
+#define CFG_SYS_NOR_CSOR	(CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
 				CSOR_NOR_TRHZ_20 | \
 				CSOR_NOR_BCTLD)
 
 /* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
 				FTIM0_NOR_TEADC(0x7) | \
 				FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
 				FTIM1_NOR_TRAD_NOR(0x21) | \
 				FTIM1_NOR_TSEQRAD_NOR(0x21))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCH(0x1) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCH(0x1) | \
 				FTIM2_NOR_TCS(0x1) | \
 				FTIM2_NOR_TWP(0xb) | \
 				FTIM2_NOR_TWPH(0x6))
-#define CONFIG_SYS_NOR_FTIM3	0x0
+#define CFG_SYS_NOR_FTIM3	0x0
 
-#define CONFIG_SYS_CSPR0_EXT	CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0	CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0	CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0	CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0	CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1	CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2	CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3	CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT	CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0	CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0	CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0	CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0	CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1	CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2	CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3	CFG_SYS_NOR_FTIM3
 
 /* More NOR Flash params */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS}
 
 /* NAND Flash on IFC CS1*/
-#define CONFIG_SYS_NAND_BASE		0xfa000000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#define CFG_SYS_NAND_BASE		0xfa000000
+#define CFG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CFG_SYS_NAND_BASE)
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0f)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0f)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
 				CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
 				0x00000010 |	   /* drive TE high */\
 				CSPR_MSEL_NAND |   /* MSEL = NAND */\
 				CSPR_V)		   /* valid */
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024) /* 64kB */
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024) /* 64kB */
 
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
 				CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */   \
 				CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */        \
 				CSOR_NAND_RAL_3      | /* RAL = 3Bytes */     \
@@ -253,36 +253,36 @@
 				CSOR_NAND_BCTLD)       /**/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x3) | \
 				FTIM0_NAND_TWP(0x8) | \
 				FTIM0_NAND_TWCHT(0x3) | \
 				FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x1e) | \
 				FTIM1_NAND_TWBE(0x1e) | \
 				FTIM1_NAND_TRR(0x6) | \
 				FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x9) | \
 				FTIM2_NAND_TREH(0x5) | \
 				FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x1e))
+#define CFG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x1e))
 
-#define CONFIG_SYS_CSPR1_EXT	CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1	CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1	CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1	CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0	CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1	CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2	CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3	CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT	CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1	CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1	CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1	CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0	CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1	CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2	CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3	CFG_SYS_NAND_FTIM3
 
 /* More NAND Flash Params */
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 /* QRIO on IFC CS2 */
-#define CONFIG_SYS_QRIO_BASE		0xfb000000
-#define CONFIG_SYS_QRIO_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_QRIO_BASE)
+#define CFG_SYS_QRIO_BASE		0xfb000000
+#define CFG_SYS_QRIO_BASE_PHYS	(0xf00000000ull | CFG_SYS_QRIO_BASE)
 #define SYS_QRIO_CSPR_EXT	(0x0f)
-#define SYS_QRIO_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+#define SYS_QRIO_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
 				CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
 				0x00000010 |	   /* drive TE high */\
 				CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
@@ -300,28 +300,26 @@
 			FTIM2_GPCM_TCH(0x1) | \
 			FTIM2_GPCM_TWP(0x7))
 #define SYS_QRIO_FTIM3	0x04000000
-#define CONFIG_SYS_CSPR2_EXT	SYS_QRIO_CSPR_EXT
-#define CONFIG_SYS_CSPR2	SYS_QRIO_CSPR
-#define CONFIG_SYS_AMASK2	SYS_QRIO_AMASK
-#define CONFIG_SYS_CSOR2	SYS_QRIO_CSOR
-#define CONFIG_SYS_CS2_FTIM0	SYS_QRIO_FTIM0
-#define CONFIG_SYS_CS2_FTIM1	SYS_QRIO_FTIM1
-#define CONFIG_SYS_CS2_FTIM2	SYS_QRIO_FTIM2
-#define CONFIG_SYS_CS2_FTIM3	SYS_QRIO_FTIM3
-
-#define CONFIG_HWCONFIG
+#define CFG_SYS_CSPR2_EXT	SYS_QRIO_CSPR_EXT
+#define CFG_SYS_CSPR2	SYS_QRIO_CSPR
+#define CFG_SYS_AMASK2	SYS_QRIO_AMASK
+#define CFG_SYS_CSOR2	SYS_QRIO_CSOR
+#define CFG_SYS_CS2_FTIM0	SYS_QRIO_FTIM0
+#define CFG_SYS_CS2_FTIM1	SYS_QRIO_FTIM1
+#define CFG_SYS_CS2_FTIM2	SYS_QRIO_FTIM2
+#define CFG_SYS_CS2_FTIM3	SYS_QRIO_FTIM3
 
 /* define to use L1 as initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE		0x00004000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Serial Port - controlled on board with jumper J8
@@ -330,10 +328,8 @@
  * Retain non-DM serial port for debug purposes.
  */
 #if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0) / 2)
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x11C500)
+#define CFG_SYS_NS16550_CLK		(get_bus_freq(0) / 2)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR + 0x11C500)
 #endif
 
 #ifndef __ASSEMBLY__
@@ -348,38 +344,35 @@
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1 */
-#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define	CFG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 
-#define CONFIG_SYS_BMAN_NUM_PORTALS	10
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	10
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
+#define CFG_SYS_BMAN_NUM_PORTALS	10
+#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS	10
+#define CFG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08
 
 /* Qman / Bman */
 /* RGMII (FM1@DTESC5) is local managemant interface */
-#define CONFIG_SYS_RGMII2_PHY_ADDR             0x11
+#define CFG_SYS_RGMII2_PHY_ADDR             0x11
 
 /*
  * Hardware Watchdog
@@ -392,7 +385,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 
 /*
  * Environment Configuration
@@ -417,12 +410,12 @@
 		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && "	\
 		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
 		" +${filesize}\0"					\
-	"update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	"update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE)	\
 		" +${filesize} && "					\
-		"erase " __stringify(CONFIG_SYS_FLASH_BASE)		\
+		"erase " __stringify(CFG_SYS_FLASH_BASE)		\
 		" +${filesize} && "					\
 		"cp.b ${load_addr_r} "					\
-		__stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "	\
+		__stringify(CFG_SYS_FLASH_BASE) " ${filesize} && "	\
 		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
 		" +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0"		\
 	"set_fdthigh=true\0"						\

diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index d6b60d8..6b30fb4 100644
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h

@@ -9,10 +9,8 @@
 #define __CONFIG_H
 
 #define CONFIG_HOSTNAME		"kmcoge5ne"
-#define CONFIG_NAND_ECC_BCH
-#define CONFIG_NAND_KMETER1
 #define NAND_MAX_CHIPS				1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 
 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
 #define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
@@ -26,7 +24,7 @@
 /**
  * KMCOGE5NE has 512 MB RAM
  */
-#define CONFIG_SYS_DDR_CS0_CONFIG (\
+#define CFG_SYS_DDR_CS0_CONFIG (\
 	CSCONFIG_EN | \
 	CSCONFIG_AP | \
 	CSCONFIG_ODT_WR_ONLY_CURRENT | \
@@ -35,8 +33,8 @@
 	CSCONFIG_COL_BIT_10)
 
 /* enable POST tests */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
-#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
+#define CFG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS)
+#define CFG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
 #define CPM_POST_WORD_ADDR  CONFIG_SYS_MEMTEST_END
 #define CONFIG_TESTPIN_REG  gprt3	/* for kmcoge5ne */
 #define CONFIG_TESTPIN_MASK 0x20	/* for kmcoge5ne */

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 4245875..910fc1b 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h

@@ -16,7 +16,7 @@
 #include "km/km-mpc83xx.h"
 #include "km/km-mpc8360.h"
 
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+#define CFG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
 					 CSCONFIG_ROW_BIT_13 | \
 					 CSCONFIG_COL_BIT_10 | \
 					 CSCONFIG_ODT_WR_ONLY_CURRENT)

diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h
index d3447a8..6fcacdb 100644
--- a/include/configs/kontron-sl-mx6ul.h
+++ b/include/configs/kontron-sl-mx6ul.h

@@ -11,18 +11,15 @@
 #include <linux/sizes.h>
 
 #include "mx6_common.h"
-#ifdef CONFIG_SPL_BUILD
-#include "imx6_spl.h"
-#endif
 
 /* RAM */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
 
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
-#define CONFIG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
 
 /* Board and environment settings */
 #define CONFIG_MXC_UART_BASE		UART4_BASE

diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h
index a2aedef..80a3230 100644
--- a/include/configs/kontron-sl-mx8mm.h
+++ b/include/configs/kontron-sl-mx8mm.h

@@ -17,10 +17,10 @@
 /* RAM */
 #define PHYS_SDRAM			DDR_CSD1_BASE_ADDR
 #define PHYS_SDRAM_SIZE			(SZ_4G)
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x200000
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x200000
 
 /* Board and environment settings */
 #define CONFIG_HOSTNAME			"kontron-mx8mm"

diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h
index 6acd2f7..17c63d8 100644
--- a/include/configs/kontron_pitx_imx8m.h
+++ b/include/configs/kontron_pitx_imx8m.h

@@ -20,7 +20,6 @@
 /* For RAW image gives a error info not panic */
 
 
-#define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR  0x08
 #endif
 
@@ -61,10 +60,10 @@
 	BOOTENV
 
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        0x80000
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0xC0000000 /* 3GB DDR */
 

diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index 38860bf..9c3174d 100644
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h

@@ -12,17 +12,17 @@
 
 /* we don't have secure memory unless we have a BL31 */
 #ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
-#undef CONFIG_SYS_MEM_RESERVE_SECURE
+#undef CFG_SYS_MEM_RESERVE_SECURE
 #endif
 
 /* DDR */
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000
 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE	0x2080000000ULL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE	0x2080000000ULL
 
 /* early stack pointer */
 
@@ -35,7 +35,7 @@
 #define CONFIG_MALLOC_F_ADDR		CFG_SYS_FSL_OCRAM_BASE
 
 /* serial port */
-#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
+#define CFG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
 
 /* SPL */
 

diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
index c401fd3..c551585 100644
--- a/include/configs/kp_imx53.h
+++ b/include/configs/kp_imx53.h

@@ -67,9 +67,9 @@
 #define PHYS_SDRAM_1_SIZE		(512 * SZ_1M)
 #define PHYS_SDRAM_SIZE		(PHYS_SDRAM_1_SIZE)
 
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+#define CFG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CFG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
 
 /* environment organization */
 

diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index 1823a79..136e228 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h

@@ -12,9 +12,6 @@
 
 #include "mx6_common.h"
 
-/* SPL */
-#include "imx6_spl.h"			/* common IMX6 SPL configuration */
-
 /* Miscellaneous configurable options */
 
 /* FEC ethernet */
@@ -89,9 +86,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment */
 

diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 9b70eed..828f910 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h

@@ -31,7 +31,7 @@
 #ifdef CONFIG_CMD_I2C
 /* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
 #if defined(CONFIG_NET2BIG_V2)
-#define CONFIG_SYS_I2C_G762_ADDR		0x3e
+#define CFG_SYS_I2C_G762_ADDR		0x3e
 #endif
 #endif /* CONFIG_CMD_I2C */
 

diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index f0ae924..abe470f 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h

@@ -17,10 +17,10 @@
 /*
  * SoC Configuration
  */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_OSCIN_FREQ		24000000
-#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_OSCIN_FREQ		24000000
+#define CFG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 
 /*
  * Memory Info
@@ -36,10 +36,9 @@
 /*
  * Serial Driver info
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CFG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
 
-#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI0_CLKID)
+#define CFG_SYS_SPI_CLK		clk_get(DAVINCI_SPI0_CLKID)
 
 /*
  * U-Boot general configuration
@@ -49,7 +48,6 @@
  * Linux Information
  */
 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
-#define CONFIG_HWCONFIG		/* enable hwconfig */
 #define CONFIG_SETUP_INITRD_TAG
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootenvfile=uEnv.txt\0" \
@@ -86,7 +84,7 @@
 	"bootscript=source ${bootscraddr}\0"
 
 /* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CFG_SYS_SDRAM_BASE		0xc0000000
 
 #include <asm/arch/hardware.h>
 

diff --git a/include/configs/librem5.h b/include/configs/librem5.h
index dbd7d10..11b3fa6 100644
--- a/include/configs/librem5.h
+++ b/include/configs/librem5.h

@@ -79,10 +79,10 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        0x80000
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			0xc0000000 /* 3GB LPDDR4 one Rank */
 

diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h
index 9eedd47..f16c7e9 100644
--- a/include/configs/linkit-smart-7688.h
+++ b/include/configs/linkit-smart-7688.h

@@ -7,28 +7,26 @@
 #define __CONFIG_LINKIT_SMART_7688_H
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CFG_SYS_INIT_SP_OFFSET	0x400000
 
 /* SPL */
 
-#define CONFIG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 
 /* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE		0
+#define CFG_SYS_UBOOT_BASE		0
 
 /* Serial SPL */
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_CLK		40000000
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM3		0xb0000e00
+#define CFG_SYS_NS16550_CLK		40000000
+#define CFG_SYS_NS16550_COM3		0xb0000e00
 
 #endif
 
 /* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 921600 }
 
 /* RAM */

diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index a784002..721da81 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h

@@ -13,9 +13,6 @@
 #include <linux/stringify.h>
 #include "mx6_common.h"
 
-/* SPL options */
-#include "imx6_spl.h"
-
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* MMC Configs */
@@ -90,9 +87,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* FLASH and environment organization */
 

diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index f0248e6..f0a9e9a 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h

@@ -9,11 +9,7 @@
 #include "ls1012a_common.h"
 
 /* DDR */
-#define CONFIG_SYS_SDRAM_SIZE		0x40000000
-
-/* SATA */
-
-#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+#define CFG_SYS_SDRAM_SIZE		0x40000000
 
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 77f84e1..9e4f949 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h

@@ -10,27 +10,20 @@
 #include <asm/arch/stream_id_lsch2.h>
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000
 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE     0x880000000ULL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE     0x880000000ULL
 
 /*SPI device */
 #define CFG_SYS_FSL_QSPI_BASE	0x40000000
 
-/* SATA */
-
-#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
-
 /* I2C */
 
 /* GPIO */
 
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE     1
-#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
+#define CFG_SYS_NS16550_CLK          (get_serial_clock())
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
 #define BOOT_TARGET_DEVICES(func) \

diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index 674bcbe..c19ed2f 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h

@@ -10,7 +10,7 @@
 #include "ls1012a_common.h"
 
 /* DDR */
-#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x20000000
 
 #undef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \

diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 9ad3a12..495bb39 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h

@@ -10,14 +10,14 @@
 #include "ls1012a_common.h"
 
 /* DDR */
-#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CFG_SYS_SDRAM_SIZE		0x40000000
 
 /*
  * QIXIS Definitions
  */
 
 #ifdef CONFIG_FSL_QIXIS
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_BRDCFG_REG		0x04
 #define QIXIS_LBMAP_SWITCH		6
 #define QIXIS_LBMAP_MASK		0x08
@@ -46,8 +46,7 @@
 /*
 * RTC configuration
 */
-#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 
 
 /* Voltage monitor on channel 2*/

diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 4f77acd..d74936d 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h

@@ -10,7 +10,7 @@
 #include "ls1012a_common.h"
 
 /* DDR */
-#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CFG_SYS_SDRAM_SIZE		0x40000000
 
 /*
  * I2C IO expander

diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 885774f..024a718 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h

@@ -7,8 +7,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
 /*
  * DDR: 800 MHz ( 1600 MT/s data rate )
@@ -41,15 +41,13 @@
 #define SDRAM_CFG2_FRC_SR		0x80000000
 #define SDRAM_CFG_BI			0x00000001
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 /*
  * Serial Port
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CFG_SYS_NS16550_CLK		get_serial_clock()
 
 /*
  * I2C
@@ -94,11 +92,8 @@
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
 
-#define CONFIG_FSL_DEVICE_DISABLE
-
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 "initrd_high=0xffffffff\0"
@@ -106,9 +101,7 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
-
-#define CONFIG_LS102XA_STREAM_ID
+#define CFG_SYS_BOOTMAPSZ		(256 << 20)
 
 #include <asm/fsl_secure_boot.h>
 

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 926c858..5a91cc3 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h

@@ -7,20 +7,20 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 #endif
 
 #define SPD_EEPROM_ADDRESS		0x51
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
@@ -30,57 +30,57 @@
  * IFC Definitions
  */
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FLASH_BASE		0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE		0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
 
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
 
-#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_TRHZ_80)
-#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
 					FTIM0_NOR_TEADC(0x5) | \
 					FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
 					FTIM1_NOR_TRAD_NOR(0x1a) | \
 					FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
 					FTIM2_NOR_TCH(0x4) | \
 					FTIM2_NOR_TWPH(0xe) | \
 					FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3		0
+#define CFG_SYS_NOR_FTIM3		0
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
-					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS, \
+					CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
 /*
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
 
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -88,20 +88,20 @@
 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3           0x0
+#define CFG_SYS_NAND_FTIM3           0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #endif
 
 /*
@@ -111,7 +111,7 @@
 #ifdef CONFIG_FSL_QIXIS
 #define QIXIS_BASE			0x7fb00000
 #define QIXIS_BASE_PHYS			QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_SWITCH		6
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
@@ -131,107 +131,103 @@
 #define QIXIS_PWR_CTL2			0x21
 #define QIXIS_PWR_CTL2_PCTL		0x2
 
-#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_NOR_MODE_AVD_NOR | \
 					CSOR_NOR_TRHZ_80)
 
 /*
  * QIXIS Timing parameters for IFC GPCM
  */
-#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xe) | \
+#define CFG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xe) | \
 					FTIM0_GPCM_TEADC(0xe) | \
 					FTIM0_GPCM_TEAHC(0xe))
-#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xe) | \
+#define CFG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xe) | \
 					FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xe) | \
+#define CFG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xe) | \
 					FTIM2_GPCM_TCH(0xe) | \
 					FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3		0x0
+#define CFG_SYS_FPGA_FTIM3		0x0
 #endif
 
 #if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1		CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2		CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3		CFG_SYS_FPGA_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1		CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2		CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3		CFG_SYS_FPGA_FTIM3
 #endif
 
 /*
  * Serial Port
  */
 #ifndef CONFIG_LPUART
-#define CONFIG_SYS_NS16550_SERIAL
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#endif
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CFG_SYS_NS16550_CLK		get_serial_clock()
 #endif
 
 /*
@@ -280,11 +276,8 @@
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
 
-#define CONFIG_FSL_DEVICE_DISABLE
-
 #ifdef CONFIG_LPUART
 #define CONFIG_EXTRA_ENV_SETTINGS       \
 	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
@@ -300,9 +293,7 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
-
-#define CONFIG_LS102XA_STREAM_ID
+#define CFG_SYS_BOOTMAPSZ		(256 << 20)
 
 /*
  * Environment

diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
index fce9119..5612c60 100644
--- a/include/configs/ls1021atsn.h
+++ b/include/configs/ls1021atsn.h

@@ -6,8 +6,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
 /* XHCI Support - enabled by default */
 
@@ -56,26 +56,19 @@
 #define PHYS_SDRAM			0x80000000
 #define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#endif
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CFG_SYS_NS16550_CLK		get_serial_clock()
 
 /* I2C */
 
 /* PCIe */
 #define FSL_PCIE_COMPAT			"fsl,ls1021a-pcie"
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
 
-#define CONFIG_FSL_DEVICE_DISABLE
-
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	func(USB, usb, 0) \
@@ -145,9 +138,7 @@
 		"bootm $load_addr#$board\0"
 
 /* Miscellaneous configurable options */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
-
-#define CONFIG_LS102XA_STREAM_ID
+#define CFG_SYS_BOOTMAPSZ		(256 << 20)
 
 /* Environment */
 

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 2c96b6f..3c4c207 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h

@@ -7,8 +7,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
 #define DDR_SDRAM_CFG			0x470c0008
 #define DDR_CS0_BNDS			0x008000bf
@@ -59,97 +59,93 @@
 #define PHYS_SDRAM			0x80000000
 #define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE      0x80000000UL
+#define CFG_SYS_SDRAM_BASE          CFG_SYS_DDR_SDRAM_BASE
 
 /*
  * IFC Definitions
  */
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FLASH_BASE		0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE		0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
 
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
 
 /* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_TRHZ_80)
-#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
 					FTIM0_NOR_TEADC(0x5) | \
 					FTIM0_NOR_TAVDS(0x0) | \
 					FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
 					FTIM1_NOR_TRAD_NOR(0x1A) | \
 					FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
 					FTIM2_NOR_TCH(0x4) | \
 					FTIM2_NOR_TWP(0x1c) | \
 					FTIM2_NOR_TWPH(0x0e))
-#define CONFIG_SYS_NOR_FTIM3		0
+#define CFG_SYS_NOR_FTIM3		0
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE_PHYS }
 
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
 #endif
 
 /* CPLD */
 
-#define CONFIG_SYS_CPLD_BASE	0x7fb00000
-#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE	0x7fb00000
+#define CPLD_BASE_PHYS		CFG_SYS_CPLD_BASE
 
-#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT        (0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_NOR_MODE_AVD_NOR | \
 					CSOR_NOR_TRHZ_80)
 
 /* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
+#define CFG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
 					FTIM0_GPCM_TEADC(0xf) | \
 					FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
 					FTIM2_GPCM_TCH(0xf) | \
 					FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_FPGA_FTIM3           0x0
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_FPGA_FTIM3           0x0
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_FPGA_FTIM3
 
 /*
  * Serial Port
  */
 #ifndef CONFIG_LPUART
-#define CONFIG_SYS_NS16550_SERIAL
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#endif
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CFG_SYS_NS16550_CLK		get_serial_clock()
 #endif
 
 /*
@@ -161,11 +157,8 @@
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
 
-#define CONFIG_FSL_DEVICE_DISABLE
-
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	func(USB, usb, 0) \
@@ -302,9 +295,7 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
-
-#define CONFIG_LS102XA_STREAM_ID
+#define CFG_SYS_BOOTMAPSZ		(256 << 20)
 
 /*
  * Environment

diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 43dbeea..b190bfe 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h

@@ -13,10 +13,10 @@
 /* Link Definitions */
 
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE	0x2080000000ULL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE	0x2080000000ULL
 
 /*
  * SMP Definitinos
@@ -28,15 +28,12 @@
 /* I2C */
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE     1
-#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
+#define CFG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
 
 /* Miscellaneous configurable options */
 
 /* Physical Memory Map */
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
 #define BOOT_TARGET_DEVICES(func) \

diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index 2539115..228fb12 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h

@@ -17,7 +17,7 @@
 #ifdef CONFIG_FSL_QIXIS
 #define QIXIS_BASE			0x7fb00000
 #define QIXIS_BASE_PHYS			QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_SWITCH		1
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		5
@@ -35,19 +35,19 @@
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define QIXIS_RST_FORCE_MEM		0x01
 
-#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_NOR_MODE_AVD_NOR | \
 					CSOR_NOR_TRHZ_80)
 #endif
 
 /* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM         1
+#define CFG_SYS_RTC_BUS_NUM         1
 #define I2C_MUX_CH_RTC                 0xB
 
 /* Store environment at top of flash */

diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h
index e7b2543..5c13461 100644
--- a/include/configs/ls1028ardb.h
+++ b/include/configs/ls1028ardb.h

@@ -10,7 +10,7 @@
 
 #define COUNTER_FREQUENCY_REAL		(get_board_sys_clk() / 4)
 
-#define CONFIG_SYS_RTC_BUS_NUM         0
+#define CFG_SYS_RTC_BUS_NUM         0
 
 /* Store environment at top of flash */
 
@@ -21,7 +21,7 @@
 #ifdef CONFIG_FSL_QIXIS
 #define QIXIS_BASE			0x7fb00000
 #define QIXIS_BASE_PHYS			QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_SWITCH		2
 #define QIXIS_LBMAP_MASK		0xe0
 #define QIXIS_LBMAP_SHIFT		0x5
@@ -39,12 +39,12 @@
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define QIXIS_RST_FORCE_MEM		0x01
 
-#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_NOR_MODE_AVD_NOR | \
 					CSOR_NOR_TRHZ_80)
 #endif

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 8c19468..a3fa92d 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h

@@ -32,17 +32,15 @@
 /* Link Definitions */
 
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000
 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
 
 #define CPU_RELEASE_ADDR               secondary_boot_addr
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
+#define CFG_SYS_NS16550_CLK          (get_serial_clock())
 
 /* SD boot SPL */
 #ifdef CONFIG_SD_BOOT
@@ -59,8 +57,8 @@
 
 /* NAND SPL */
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 #ifdef CONFIG_NXP_ESBC
 #define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
@@ -84,14 +82,14 @@
 #if defined(CONFIG_TFABOOT) || \
 	(!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
 /*
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  * CONFIG_TEXT_BASE is linked to 0x60000000 for booting
  */
-#define CONFIG_SYS_FLASH_BASE			0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+#define CFG_SYS_FLASH_BASE			0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS		CFG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
@@ -105,15 +103,13 @@
 
 /* FMan ucode */
 #ifndef SPL_NO_FMAN
-#define CONFIG_SYS_DPAA_FMAN
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CFG_SYS_FM_MURAM_SIZE	0x60000
 #endif
 #endif
 
 /* Miscellaneous configurable options */
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
 #ifndef SPL_NO_MISC

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index d207e47..dab5738 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h

@@ -35,61 +35,57 @@
 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
 #endif
 
-/* SATA */
-
-#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
-
 /*
  * IFC Definitions
  */
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
 
-#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_TRHZ_80)
-#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
 					FTIM0_NOR_TEADC(0x5) | \
 					FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
 					FTIM1_NOR_TRAD_NOR(0x1a) | \
 					FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
 					FTIM2_NOR_TCH(0x4) | \
 					FTIM2_NOR_TWPH(0xe) | \
 					FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3		0
+#define CFG_SYS_NOR_FTIM3		0
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
-					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS, \
+					CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
 
 /*
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
 
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -97,25 +93,25 @@
 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3           0x0
+#define CFG_SYS_NAND_FTIM3           0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #endif
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
 #endif
 
 #if defined(CONFIG_TFABOOT) || \
@@ -129,7 +125,7 @@
 #ifdef CONFIG_FSL_QIXIS
 #define QIXIS_BASE			0x7fb00000
 #define QIXIS_BASE_PHYS			QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_SWITCH		6
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
@@ -147,130 +143,130 @@
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 
-#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_NOR_MODE_AVD_NOR | \
 					CSOR_NOR_TRHZ_80)
 
 /*
  * QIXIS Timing parameters for IFC GPCM
  */
-#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
+#define CFG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
 					FTIM0_GPCM_TEADC(0x20) | \
 					FTIM0_GPCM_TEAHC(0x10))
-#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
+#define CFG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
 					FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
+#define CFG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3		0x0
+#define CFG_SYS_FPGA_FTIM3		0x0
 #endif
 
 #ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1		CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2		CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3		CFG_SYS_FPGA_FTIM3
 #else
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1		CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2		CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3		CFG_SYS_FPGA_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1		CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2		CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3		CFG_SYS_FPGA_FTIM3
 #endif
 #endif
 

diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 206de7e..12c4853 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h

@@ -18,49 +18,49 @@
 /*
  * NOR Flash Definitions
  */
-#define CONFIG_SYS_NOR_CSPR_EXT		(0x0)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+#define CFG_SYS_NOR_CSPR_EXT		(0x0)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
 
 /* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_TRHZ_80)
-#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x1) | \
+#define CFG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x1) | \
 					FTIM0_NOR_TEADC(0x1) | \
 					FTIM0_NOR_TAVDS(0x0) | \
 					FTIM0_NOR_TEAHC(0xc))
-#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x1c) | \
+#define CFG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x1c) | \
 					FTIM1_NOR_TRAD_NOR(0xb) | \
 					FTIM1_NOR_TSEQRAD_NOR(0x9))
-#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x1) | \
+#define CFG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x1) | \
 					FTIM2_NOR_TCH(0x4) | \
 					FTIM2_NOR_TWPH(0x8) | \
 					FTIM2_NOR_TWP(0x10))
-#define CONFIG_SYS_NOR_FTIM3		0
-#define CONFIG_SYS_IFC_CCR		0x01000000
+#define CFG_SYS_NOR_FTIM3		0
+#define CFG_SYS_IFC_CCR		0x01000000
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE_PHYS }
 
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
 
 /*
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -68,120 +68,120 @@
 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(1024 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(1024 << 10)
 #endif
 
 /*
  * CPLD
  */
-#define CONFIG_SYS_CPLD_BASE		0x7fb00000
-#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE		0x7fb00000
+#define CPLD_BASE_PHYS			CFG_SYS_CPLD_BASE
 
-#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
-#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_CPLD_CSPR_EXT	(0x0)
+#define CFG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_CPLD_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_NOR_MODE_AVD_NOR | \
 					CSOR_NOR_TRHZ_80)
 
 /* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
+#define CFG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
 					FTIM0_GPCM_TEADC(0xf) | \
 					FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
 					FTIM2_GPCM_TCH(0xf) | \
 					FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_CPLD_FTIM3		0x0
+#define CFG_SYS_CPLD_FTIM3		0x0
 
 /* IFC Timing Params */
 #ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
 
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #else
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
 
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 #endif
 
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_CPLD_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_CPLD_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_CPLD_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_CPLD_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_CPLD_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_CPLD_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_CPLD_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_CPLD_FTIM3
 
 /*
  * Environment

diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 7e1a724..4ed5481 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h

@@ -32,17 +32,15 @@
 /* Link Definitions */
 
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000
 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
 
 #define CPU_RELEASE_ADDR               secondary_boot_addr
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
+#define CFG_SYS_NS16550_CLK          (get_serial_clock())
 
 /* SD boot SPL */
 #ifdef CONFIG_SD_BOOT
@@ -59,30 +57,23 @@
 
 /* NAND SPL */
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 #endif
 
 /* GPIO */
 
 /* I2C */
 
-/* SATA */
-#ifndef SPL_NO_SATA
-#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
-#endif
-
 /* FMan ucode */
 #ifndef SPL_NO_FMAN
-#define CONFIG_SYS_DPAA_FMAN
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CFG_SYS_FM_MURAM_SIZE	0x60000
 #endif
 #endif
 
 /* Miscellaneous configurable options */
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
 #define BOOT_TARGET_DEVICES(func) \

diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 48408f2..1759d25 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h

@@ -8,22 +8,22 @@
 
 #include "ls1046a_common.h"
 
-#define CONFIG_SYS_UBOOT_BASE		0x40100000
+#define CFG_SYS_UBOOT_BASE		0x40100000
 
 /*
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -31,31 +31,31 @@
 				| CSOR_NAND_SPRZ_128	/* Spare size = 128 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 /* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
 /* EEPROM */
 #define I2C_RETIMER_ADDR			0x18
@@ -66,9 +66,8 @@
 #define I2C_MUX_CH_RTC				0x1 /* Channel 0*/
 
 /* RTC */
-#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51  /* Channel 0 I2C bus 0*/
-#define CONFIG_SYS_RTC_BUS_NUM			0
+#define CFG_SYS_I2C_RTC_ADDR		0x51  /* Channel 0 I2C bus 0*/
+#define CFG_SYS_RTC_BUS_NUM			0
 
 /*
  * Environment

diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 037d462..553ae84 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h

@@ -33,14 +33,14 @@
 /* IFC */
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 /*
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  * CONFIG_TEXT_BASE is linked to 0x60000000 for booting
  */
-#define CONFIG_SYS_FLASH_BASE			0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+#define CFG_SYS_FLASH_BASE			0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS		CFG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
@@ -58,54 +58,54 @@
  * IFC Definitions
  */
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+#define CFG_SYS_NOR1_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
 				+ 0x8000000) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
 
-#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_TRHZ_80)
-#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
 					FTIM0_NOR_TEADC(0x5) | \
 					FTIM0_NOR_TAVDS(0x6) | \
 					FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
 					FTIM1_NOR_TRAD_NOR(0x1a) | \
 					FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x8) | \
+#define CFG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x8) | \
 					FTIM2_NOR_TCH(0x8) | \
 					FTIM2_NOR_TWPH(0xe) | \
 					FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3		0
+#define CFG_SYS_NOR_FTIM3		0
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
-					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS, \
+					CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
 
 /*
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
 
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -113,25 +113,25 @@
 				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3           0x0
+#define CFG_SYS_NAND_FTIM3           0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #endif
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #endif
 
 #if defined(CONFIG_TFABOOT) || \
@@ -145,7 +145,7 @@
 #ifdef CONFIG_FSL_QIXIS
 #define QIXIS_BASE			0x7fb00000
 #define QIXIS_BASE_PHYS			QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_SWITCH		6
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		0
@@ -163,130 +163,130 @@
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 
-#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_NOR_MODE_AVD_NOR | \
 					CSOR_NOR_TRHZ_80)
 
 /*
  * QIXIS Timing parameters for IFC GPCM
  */
-#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
+#define CFG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
 					FTIM0_GPCM_TEADC(0x20) | \
 					FTIM0_GPCM_TEAHC(0x10))
-#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
+#define CFG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
 					FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
+#define CFG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0xf0))
-#define CONFIG_SYS_FPGA_FTIM3		0x0
+#define CFG_SYS_FPGA_FTIM3		0x0
 #endif
 
 #ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1		CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2		CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3		CFG_SYS_FPGA_FTIM3
 #else
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1		CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2		CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3		CFG_SYS_FPGA_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR1_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK3		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS3_FTIM1		CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS3_FTIM2		CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS3_FTIM3		CFG_SYS_FPGA_FTIM3
 #endif
 #endif
 

diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 7693493..f3904e7 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h

@@ -16,19 +16,19 @@
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 
 #if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_UBOOT_BASE		0x40100000
+#define CFG_SYS_UBOOT_BASE		0x40100000
 #endif
 
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8	\
 				| CSPR_MSEL_NAND	\
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
@@ -36,65 +36,65 @@
 				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x7) | \
 					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0xe)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
 					FTIM2_NAND_TREH(0xa) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 /*
  * CPLD
  */
-#define CONFIG_SYS_CPLD_BASE		0x7fb00000
-#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE		0x7fb00000
+#define CPLD_BASE_PHYS			CFG_SYS_CPLD_BASE
 
-#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
-#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+#define CFG_SYS_CPLD_CSPR_EXT	(0x0)
+#define CFG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR		CSOR_NOR_ADM_SHIFT(16)
+#define CFG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_CPLD_CSOR		CSOR_NOR_ADM_SHIFT(16)
 
 /* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
 					FTIM2_GPCM_TCH(0xf) | \
 					FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CPLD_FTIM3		0x0
+#define CFG_SYS_CPLD_FTIM3		0x0
 
 /* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_CPLD_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_CPLD_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_CPLD_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_CPLD_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_CPLD_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_CPLD_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_CPLD_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_CPLD_FTIM3
 
 /* EEPROM */
 #define I2C_RETIMER_ADDR			0x18

diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 73e4ac3..57429d4 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h

@@ -30,10 +30,10 @@
 #define CFG_SYS_FSL_QSPI_BASE	0x20000000
 
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
 /*
  * SMP Definitinos
  */
@@ -45,9 +45,7 @@
 
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE     1
-#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
+#define CFG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
 
 /*
  * During booting, IFC is mapped at the region of 0x30000000.
@@ -66,18 +64,18 @@
  * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
  *
  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  * CONFIG_TEXT_BASE is linked to 0x30000000 for booting
  */
 
-#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
-#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+#define CFG_SYS_FLASH_BASE			0x580000000ULL
+#define CFG_SYS_FLASH_BASE_PHYS		0x80000000
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
 
-#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
+#define CFG_SYS_FLASH1_BASE_PHYS		0xC0000000
+#define CFG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
 
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
@@ -88,18 +86,18 @@
 #define QIXIS_BASE_PHYS_EARLY			0xC000000
 
 
-#define CONFIG_SYS_NAND_BASE			0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
+#define CFG_SYS_NAND_BASE			0x530000000ULL
+#define CFG_SYS_NAND_BASE_PHYS		0x30000000
 
 
 /* MC firmware */
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
-#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
-#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
+#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
 
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
@@ -109,14 +107,13 @@
  */
 
 #if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(128UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(128UL * 1024 * 1024)
 #endif
 
 /* Miscellaneous configurable options */
 
 /* Physical Memory Map */
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
 #ifndef SPL_NO_ENV

diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index d50b76b..a35045d 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h

@@ -22,64 +22,61 @@
  * IFC Definitions
  */
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
 
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+#define CFG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+#define CFG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)	| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
+#define CFG_SYS_NOR1_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
+#define CFG_SYS_NOR1_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TAVDS(0x6) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1a) | \
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x8) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x8) | \
 				FTIM2_NOR_TCH(0x8) | \
 				FTIM2_NOR_TWPH(0xe) | \
 				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
+#define CFG_SYS_NOR_FTIM3	0x04000000
+#define CFG_SYS_IFC_CCR	0x01000000
 
 #ifndef SYS_NO_FLASH
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
-					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE,\
+					 CFG_SYS_FLASH_BASE + 0x40000000}
 #endif
 #endif
 
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -88,23 +85,23 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_SWITCH		6
 #define QIXIS_QMAP_MASK			0xe0
 #define QIXIS_QMAP_SHIFT		5
@@ -130,8 +127,8 @@
 #define QIXIS_SDID_MASK			0x07
 #define QIXIS_ESDHC_NO_ADAPTER		0x7
 
-#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 					| CSPR_PORT_SIZE_8 \
 					| CSPR_MSEL_GPCM \
 					| CSPR_V)
@@ -142,9 +139,9 @@
 
 #define SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
+#define CFG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
 #else
-#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(12)
 #endif
 /* QIXIS Timing parameters*/
 #define SYS_FPGA_CS_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
@@ -158,102 +155,102 @@
 #define SYS_FPGA_CS_FTIM3	0x0
 
 #ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3		SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK3		SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
 #else
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2		SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK2		SYS_FPGA_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3		SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR3_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR3		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK3		SYS_FPGA_AMASK
+#define CFG_SYS_CSOR3		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
 #endif
 #endif
 
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 /*
  * I2C bus multiplexer
@@ -283,8 +280,7 @@
 /*
 * RTC configuration
 */
-#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 
 #ifdef CONFIG_FSL_DSPI
 #if !defined(CONFIG_TFABOOT) && \

diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 4edf40b..7bc4fc6 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h

@@ -20,50 +20,47 @@
 
 
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
-#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64 * 1024 * 1024)
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+#define CFG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64 * 1024 * 1024)
 
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+#define CFG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+#define CFG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)	| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(6)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+#define CFG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(6)
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
 				FTIM0_NOR_TEADC(0x1) | \
 				FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
 				FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
 				FTIM2_NOR_TCH(0x0) | \
 				FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
+#define CFG_SYS_NOR_FTIM3	0x04000000
+#define CFG_SYS_IFC_CCR	0x01000000
 
 #ifndef SYS_NO_FLASH
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE }
 #endif
 #endif
 
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -72,23 +69,23 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_BRDCFG4_OFFSET            0x54
 #define QIXIS_LBMAP_SWITCH		2
 #define QIXIS_QMAP_MASK			0xe0
@@ -110,8 +107,8 @@
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define	QIXIS_RST_FORCE_MEM		0x01
 
-#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 					| CSPR_PORT_SIZE_8 \
 					| CSPR_MSEL_GPCM \
 					| CSPR_V)
@@ -120,8 +117,8 @@
 					| CSPR_MSEL_GPCM \
 					| CSPR_V)
 
-#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64*1024)
-#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
+#define CFG_SYS_FPGA_AMASK		IFC_AMASK(64*1024)
+#define CFG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
 /* QIXIS Timing parameters*/
 #define SYS_FPGA_CS_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
@@ -135,36 +132,36 @@
 
 #if defined(CONFIG_TFABOOT) || \
 	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_FPGA_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_FPGA_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_FPGA_CSPR
+#define CFG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
+#define CFG_SYS_AMASK2		CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
+#define CFG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
+#define CFG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
+#define CFG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
 #endif
 
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 #define I2C_MUX_CH_VOL_MONITOR         0xA
 /* Voltage monitor on channel 2*/
@@ -189,13 +186,10 @@
 #define I2C_MUX_CH_DEFAULT		0x8
 #define I2C_MUX_CH5			0xD
 
-#ifndef SPL_NO_RTC
 /*
 * RTC configuration
 */
-#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
-#endif
+#define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 
 #ifndef SPL_NO_ENV
 /* Initial environment variables */

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 53a3af1..e82456f 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h

@@ -17,10 +17,10 @@
 /* Link Definitions */
 
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
 
 /*
  * SMP Definitinos
@@ -37,9 +37,7 @@
 /* I2C */
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE     1
-#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
+#define CFG_SYS_NS16550_CLK          (get_serial_clock())
 
 /*
  * During booting, IFC is mapped at the region of 0x30000000.
@@ -58,18 +56,18 @@
  * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
  *
  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  * CONFIG_TEXT_BASE is linked to 0x30000000 for booting
  */
 
-#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
-#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+#define CFG_SYS_FLASH_BASE			0x580000000ULL
+#define CFG_SYS_FLASH_BASE_PHYS		0x80000000
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
 
-#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
+#define CFG_SYS_FLASH1_BASE_PHYS		0xC0000000
+#define CFG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
 
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
@@ -81,18 +79,18 @@
 #define QIXIS_SDID_MASK				0x07
 #define QIXIS_ESDHC_NO_ADAPTER			0x7
 
-#define CONFIG_SYS_NAND_BASE			0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
+#define CFG_SYS_NAND_BASE			0x530000000ULL
+#define CFG_SYS_NAND_BASE_PHYS		0x30000000
 
 /* MC firmware */
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 /* For LS2085A */
-#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
-#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
+#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
+#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
 
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
@@ -101,7 +99,7 @@
  * 512MB aligned, so the min size to hide is 512MB.
  */
 #ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(128UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(128UL * 1024 * 1024)
 #endif
 
 /* Miscellaneous configurable options */
@@ -109,7 +107,6 @@
 /* Physical Memory Map */
 /* fixme: these need to be checked against the board */
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
 /* Initial environment variables */
@@ -129,8 +126,8 @@
 	" 0x580e00000 \0"
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_U_BOOT_DST	0x80400000
+#define CFG_SYS_NAND_U_BOOT_START	CFG_SYS_NAND_U_BOOT_DST
 #endif
 
 #include <asm/arch/soc.h>

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 1fa4aa3..924d405 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h

@@ -10,10 +10,10 @@
 #include "ls2080a_common.h"
 
 #ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_I2C_IFDR_DIV		0x7e
+#define CFG_SYS_I2C_IFDR_DIV		0x7e
 #endif
 
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define COUNTER_FREQUENCY_REAL		(get_board_sys_clk()/4)
 
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
@@ -25,62 +25,59 @@
 #define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
 
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
 
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+#define CFG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+#define CFG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)	| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
+#define CFG_SYS_NOR1_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
+#define CFG_SYS_NOR1_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1a) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
+#define CFG_SYS_NOR_FTIM3	0x04000000
+#define CFG_SYS_IFC_CCR	0x01000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
-					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE,\
+					 CFG_SYS_FLASH_BASE + 0x40000000}
 #endif
 
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -89,20 +86,20 @@
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
 					FTIM0_NAND_TWP(0x18)   | \
 					FTIM0_NAND_TWCHT(0x07) | \
 					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
 					FTIM1_NAND_TWBE(0x39)  | \
 					FTIM1_NAND_TRR(0x0e)   | \
 					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
 					FTIM2_NAND_TREH(0x0a) | \
 					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define QIXIS_LBMAP_SWITCH		0x06
@@ -122,92 +119,92 @@
 #define QIXIS_RCW_SRC_QSPI		0x62
 #define	QIXIS_RST_FORCE_MEM		0x01
 
-#define CONFIG_SYS_CSPR3_EXT	(0x0)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_CSPR3_EXT	(0x0)
+#define CFG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
-#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 
-#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
 /* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
 					FTIM2_GPCM_TCH(0xf) | \
 					FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CS3_FTIM3		0x0
+#define CFG_SYS_CS3_FTIM3		0x0
 
 #if defined(CONFIG_SPL)
 #if defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK2_FINAL		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR2_FINAL		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK2_FINAL		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
 #endif
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR1_CSPR_EARLY
+#define CFG_SYS_CSPR1_FINAL		CFG_SYS_NOR1_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK_EARLY
+#define CFG_SYS_AMASK1_FINAL		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 /*
  * I2C
@@ -230,9 +227,7 @@
 /*
  * RTC configuration
  */
-#define RTC
-#define CONFIG_RTC_DS3231               1
-#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CFG_SYS_I2C_RTC_ADDR         0x68
 
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index e1c66c5..c50b603 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h

@@ -32,52 +32,49 @@
 
 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
 
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
 
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+#define CFG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+#define CFG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)	| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1a) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
+#define CFG_SYS_NOR_FTIM3	0x04000000
+#define CFG_SYS_IFC_CCR	0x01000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
-					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE,\
+					 CFG_SYS_FLASH_BASE + 0x40000000}
 #endif
 
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -86,20 +83,20 @@
 				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
 					FTIM0_NAND_TWP(0x30)   | \
 					FTIM0_NAND_TWCHT(0x0e) | \
 					FTIM0_NAND_TWH(0x14))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
 					FTIM1_NAND_TWBE(0xab)  | \
 					FTIM1_NAND_TRR(0x1c)   | \
 					FTIM1_NAND_TRP(0x30))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
 					FTIM2_NAND_TREH(0x14) | \
 					FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define QIXIS_LBMAP_SWITCH		0x06
@@ -116,70 +113,70 @@
 #define QIXIS_RCW_SRC_NAND		0x119
 #define	QIXIS_RST_FORCE_MEM		0x01
 
-#define CONFIG_SYS_CSPR3_EXT	(0x0)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_CSPR3_EXT	(0x0)
+#define CFG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
-#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 
-#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
 /* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
 					FTIM2_GPCM_TCH(0xf) | \
 					FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CS3_FTIM3		0x0
+#define CFG_SYS_CS3_FTIM3		0x0
 
 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR2_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
 
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 #endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 #ifdef CONFIG_TARGET_LS2081ARDB
 #define QIXIS_QMAP_MASK			0x07
@@ -200,7 +197,7 @@
  * I2C
  */
 #ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #endif
 #define I2C_MUX_PCA_ADDR		0x75
 #define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/
@@ -213,12 +210,10 @@
 /*
  * RTC configuration
  */
-#define RTC
 #ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SYS_I2C_RTC_ADDR         0x51
+#define CFG_SYS_I2C_RTC_ADDR         0x51
 #else
-#define CONFIG_RTC_DS3231               1
-#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CFG_SYS_I2C_RTC_ADDR         0x68
 #endif
 
 #define BOOT_TARGET_DEVICES(func) \

diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 8b2b747..a469c83 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h

@@ -10,15 +10,15 @@
 #include <asm/arch/config.h>
 #include <asm/arch/soc.h>
 
-#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CFG_SYS_FLASH_BASE		0x20000000
 
 /* DDR */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE		0x80000000UL
+#define CFG_SYS_DDR_SDRAM_BASE		0x80000000UL
 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_DDR_BLOCK2_BASE		0x2080000000ULL
-#define CONFIG_SYS_SDRAM_SIZE			0x200000000UL
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE		0x2080000000ULL
+#define CFG_SYS_SDRAM_SIZE			0x200000000UL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #define SPD_EEPROM_ADDRESS1		0x51
 #define SPD_EEPROM_ADDRESS2		0x52
@@ -42,22 +42,22 @@
 
 /* Serial Port */
 #define CONFIG_PL011_CLOCK		(get_bus_freq(0) / 4)
-#define CONFIG_SYS_SERIAL0		0x21c0000
-#define CONFIG_SYS_SERIAL1		0x21d0000
-#define CONFIG_SYS_SERIAL2		0x21e0000
-#define CONFIG_SYS_SERIAL3		0x21f0000
+#define CFG_SYS_SERIAL0		0x21c0000
+#define CFG_SYS_SERIAL1		0x21d0000
+#define CFG_SYS_SERIAL2		0x21e0000
+#define CFG_SYS_SERIAL3		0x21f0000
 /*below might needs to be removed*/
-#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
-					(void *)CONFIG_SYS_SERIAL1, \
-					(void *)CONFIG_SYS_SERIAL2, \
-					(void *)CONFIG_SYS_SERIAL3 }
+#define CONFIG_PL01x_PORTS		{(void *)CFG_SYS_SERIAL0, \
+					(void *)CFG_SYS_SERIAL1, \
+					(void *)CFG_SYS_SERIAL2, \
+					(void *)CFG_SYS_SERIAL3 }
 
 /* MC firmware */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH		0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET	0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH		0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET	0x00F20000
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS	5000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH		0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET	0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH		0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET	0x00F20000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS	5000
 
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
@@ -66,7 +66,7 @@
  * 512MB aligned, so the min size to hide is 512MB.
  */
 #ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(256UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(256UL * 1024 * 1024)
 #endif
 
 /* I2C bus multiplexer */
@@ -74,17 +74,15 @@
 #define I2C_MUX_CH_DEFAULT		0x8
 
 /* RTC */
-#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51  /* Channel 3*/
+#define CFG_SYS_I2C_RTC_ADDR		0x51  /* Channel 3*/
 
 /* Qixis */
-#define CONFIG_SYS_I2C_FPGA_ADDR		0x66
+#define CFG_SYS_I2C_FPGA_ADDR		0x66
 
 /* USB */
 
 #define COUNTER_FREQUENCY_REAL		(get_board_sys_clk() / 4)
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
 /* Initial environment variables */

diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 4e8a904..9f89106 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h

@@ -9,7 +9,7 @@
 #include "lx2160a_common.h"
 
 /* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM		0
+#define CFG_SYS_RTC_BUS_NUM		0
 
 /* MAC/PHY configuration */
 

diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index bb9239c..58c0ff3 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h

@@ -9,7 +9,7 @@
 #include "lx2160a_common.h"
 
 /* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM		4
+#define CFG_SYS_RTC_BUS_NUM		4
 
 /* EMC2305 */
 #define I2C_MUX_CH_EMC2305		0x09

diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h
index b70abb0..157688e 100644
--- a/include/configs/lx2162aqds.h
+++ b/include/configs/lx2162aqds.h

@@ -11,7 +11,7 @@
 /* USB */
 
 /* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM		0
+#define CFG_SYS_RTC_BUS_NUM		0
 
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\

diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index a20b41b..6659139 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h

@@ -20,9 +20,9 @@
 #define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
 #define PHYS_SDRAM_SIZE			(gd->ram_size)
 
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+#define CFG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CFG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
 
 /*
  * U-Boot general configurations
@@ -44,10 +44,10 @@
  * NAND
  */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
+#define CFG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
 #define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
 #define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_LARGEPAGE
+#define CFG_SYS_NAND_LARGEPAGE
 #define CONFIG_MXC_NAND_HWECC
 #endif
 
@@ -58,13 +58,13 @@
 #define CONFIG_FEC_MXC_PHYADDR		0x0
 #endif
 
-#define CONFIG_SYS_RTC_BUS_NUM		1 /* I2C2 */
+#define CFG_SYS_RTC_BUS_NUM		1 /* I2C2 */
 
 /*
  * RTC
  */
 #ifdef CONFIG_CMD_DATE
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CFG_SYS_I2C_RTC_ADDR		0x68
 #endif
 
 /*
@@ -77,21 +77,11 @@
 #endif
 
 /* LVDS display */
-#define CONFIG_SYS_LDB_CLOCK			33260000
-#define CONFIG_IMX_VIDEO_SKIP
-
-/* IIM Fuses */
-#define CONFIG_FSL_IIM
+#define CFG_SYS_LDB_CLOCK			33260000
 
 /* Watchdog */
 
 /*
- * NAND SPL
- */
-
-#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
-
-/*
  * Extra Environments
  */
 #define CONFIG_HOSTNAME		"m53menlo"

diff --git a/include/configs/malta.h b/include/configs/malta.h
index 30c2e41..65f4b05 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h

@@ -22,26 +22,25 @@
  */
 
 #ifdef CONFIG_64BIT
-# define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
+# define CFG_SYS_SDRAM_BASE		0xffffffff80000000
 #else
-# define CONFIG_SYS_SDRAM_BASE		0x80000000
+# define CFG_SYS_SDRAM_BASE		0x80000000
 #endif
-#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 MiB */
+#define CFG_SYS_SDRAM_SIZE		0x10000000	/* 256 MiB */
 
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CFG_SYS_INIT_SP_OFFSET	0x400000
 
 /*
  * Serial driver
  */
-#define CONFIG_SYS_NS16550_PORT_MAPPED
 
 /*
  * Flash configuration
  */
 #ifdef CONFIG_64BIT
-# define CONFIG_SYS_FLASH_BASE		0xffffffffbe000000
+# define CFG_SYS_FLASH_BASE		0xffffffffbe000000
 #else
-# define CONFIG_SYS_FLASH_BASE		0xbe000000
+# define CFG_SYS_FLASH_BASE		0xbe000000
 #endif
 
 /*

diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index db84302..5ad945b 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h

@@ -47,6 +47,6 @@
  */
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_SDRAM_SIZE		SZ_1G
+#define CFG_SYS_SDRAM_SIZE		SZ_1G
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */

diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 69ca7c5..7c401a2 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h

@@ -9,9 +9,7 @@
 
 #include "mx6_common.h"
 
-#include "imx6_spl.h"
-
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
+#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + 0x80000)
 
 /*
  * Below defines are set but NOT really used since we by
@@ -26,12 +24,12 @@
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 
 /* NOR 16-bit mode */
-#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
+#define CFG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
 #define CONFIG_FLASH_VERIFY
 
 /* NOR Flash MTD */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES	{ (32 * SZ_1M) }
+#define CFG_SYS_FLASH_BANKS_LIST	{ (CFG_SYS_FLASH_BASE) }
+#define CFG_SYS_FLASH_BANKS_SIZES	{ (32 * SZ_1M) }
 
 /* Ethernet Configuration */
 #define CONFIG_FEC_MXC_PHYADDR		1
@@ -118,7 +116,7 @@
 	"nor_img_addr=0x11000000\0" \
 	"nor_img_file=core-image-lwn-mccmon6.nor\0" \
 	"emmc_img_file=core-image-lwn-mccmon6.ext4\0" \
-	"nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
+	"nor_bank_start=" __stringify(CFG_SYS_FLASH_BASE) "\0" \
 	"nor_img_size=0x02000000\0" \
 	"factory_script_file=factory.scr\0" \
 	"factory_load_script=" \
@@ -216,9 +214,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment organization */
 

diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index b90a84d..a8d8d8b 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h

@@ -16,7 +16,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* NAND support */
 

diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h
index c6ce883..9e480fe 100644
--- a/include/configs/meerkat96.h
+++ b/include/configs/meerkat96.h

@@ -17,9 +17,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment configs */
 

diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 9f913fa..d190e4b 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h

@@ -28,8 +28,8 @@
  */
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* 32.768 kHz crystal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768	/* 32.768 kHz crystal */
+#define CFG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */
 
 /* Misc CPU related */
 
@@ -44,20 +44,19 @@
 #define PHYS_SDRAM					ATMEL_BASE_CS1 /* 0x20000000 */
 #define PHYS_SDRAM_SIZE				0x02000000     /* 32 MByte */
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_SDRAM_SIZE		PHYS_SDRAM_SIZE
 
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM0
-#define CONFIG_SYS_INIT_RAM_SIZE	(16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM0
+#define CFG_SYS_INIT_RAM_SIZE	(16 * 1024)
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3 /* 0x40000000 */
-# define CONFIG_SYS_NAND_DBW_8
-# define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
-# define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
-# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+# define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3 /* 0x40000000 */
+# define CFG_SYS_NAND_MASK_ALE		(1 << 21)
+# define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+# define CFG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CFG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* hw-controller addresses */

diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 726f33c..6331b76 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h

@@ -36,7 +36,7 @@
 #define STDIN_CFG "serial"
 #endif
 
-#define CONFIG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_BASE		0
 
 /* ROM USB boot support, auto-execute boot.scr at scriptaddr */
 #define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 139b5bc..edd2466 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h

@@ -13,7 +13,7 @@
 
 /* uart */
 /* The following table includes the supported baudrates */
-# define CONFIG_SYS_BAUDRATE_TABLE \
+# define CFG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 #define	CONFIG_HOSTNAME		"microblaze-generic"
@@ -95,6 +95,6 @@
 
 /* SPL part */
 
-#define CONFIG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
 
 #endif	/* __CONFIG_H */

diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h
index 4c7cfac..3def93d 100644
--- a/include/configs/microchip_mpfs_icicle.h
+++ b/include/configs/microchip_mpfs_icicle.h

@@ -9,7 +9,7 @@
 
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_SDRAM_BASE       0x80000000
+#define CFG_SYS_SDRAM_BASE       0x80000000
 
 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
 

diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h
index bd35378..cfe926c 100644
--- a/include/configs/msc_sm2s_imx8mp.h
+++ b/include/configs/msc_sm2s_imx8mp.h

@@ -14,7 +14,7 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR          1
@@ -46,10 +46,10 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x80000
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
 #define PHYS_SDRAM_2			0xc0000000

diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h
index c76e1fc..d5bd492 100644
--- a/include/configs/mt7620.h
+++ b/include/configs/mt7620.h

@@ -8,15 +8,15 @@
 #ifndef __CONFIG_MT7620_H
 #define __CONFIG_MT7620_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CFG_SYS_INIT_SP_OFFSET	0x400000
 
 /* SPL */
 
-#define CONFIG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 
 /* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE		0
+#define CFG_SYS_UBOOT_BASE		0
 
 #endif /* __CONFIG_MT7620_H */

diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h
index 9b1ba36..7c8c67f 100644
--- a/include/configs/mt7621.h
+++ b/include/configs/mt7621.h

@@ -8,12 +8,12 @@
 #ifndef __CONFIG_MT7621_H
 #define __CONFIG_MT7621_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_MAX_MEM_MAPPED		0x1c000000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	0x800000
+#define CFG_SYS_INIT_SP_OFFSET	0x800000
 
 /* MMC */
 #define MMC_SUPPORTS_TUNING
@@ -22,17 +22,15 @@
 
 /* Serial SPL */
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_CLK		50000000
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM1		0xbe000c00
+#define CFG_SYS_NS16550_CLK		50000000
+#define CFG_SYS_NS16550_COM1		0xbe000c00
 #endif
 
 /* Serial common */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 921600 }
 
 /* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE		0
+#define CFG_SYS_UBOOT_BASE		0
 
 #endif /* __CONFIG_MT7621_H */

diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h
index fd8e30a..8c29726 100644
--- a/include/configs/mt7622.h
+++ b/include/configs/mt7622.h

@@ -10,12 +10,12 @@
 #define __MT7622_H
 
 /* Uboot definition */
-#define CONFIG_SYS_UBOOT_BASE                   CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE                   CONFIG_TEXT_BASE
 
 /* SPL -> Uboot */
-#define CONFIG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 /* DRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 /* Ethernet */
 #define CONFIG_IPADDR			192.168.1.1

diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h
index 73093f9..39a7ba7 100644
--- a/include/configs/mt7623.h
+++ b/include/configs/mt7623.h

@@ -21,7 +21,7 @@
 #define MMC_SUPPORTS_TUNING
 
 /* DRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* This is needed for kernel booting */
 #define FDT_HIGH			"0xac000000"

diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h
index 4352701..9df2715 100644
--- a/include/configs/mt7628.h
+++ b/include/configs/mt7628.h

@@ -8,27 +8,25 @@
 #ifndef __CONFIG_MT7628_H
 #define __CONFIG_MT7628_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	0x80000
+#define CFG_SYS_INIT_SP_OFFSET	0x80000
 
 /* Serial SPL */
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_CLK		40000000
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM1		0xb0000c00
+#define CFG_SYS_NS16550_CLK		40000000
+#define CFG_SYS_NS16550_COM1		0xb0000c00
 #endif
 
 /* Serial common */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 921600 }
 
 /* SPL */
 
-#define CONFIG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 
 /* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE		0
+#define CFG_SYS_UBOOT_BASE		0
 
 #endif /* __CONFIG_MT7628_H */

diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h
index 668dc3c..bfa44aa 100644
--- a/include/configs/mt7629.h
+++ b/include/configs/mt7629.h

@@ -18,14 +18,14 @@
 /* Defines for SPL */
 
 #define CONFIG_SPI_ADDR			0x30000000
-#define CONFIG_SYS_UBOOT_BASE		(CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
+#define CFG_SYS_UBOOT_BASE		(CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
 
 /* SPL -> Uboot */
 
 /* UBoot -> Kernel */
 
 /* DRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 /* Ethernet */
 #define CONFIG_IPADDR			192.168.1.1

diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h
index 9f26b0b..14c885e 100644
--- a/include/configs/mt7981.h
+++ b/include/configs/mt7981.h

@@ -10,12 +10,12 @@
 #define __MT7981_H
 
 /* Uboot definition */
-#define CONFIG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
 
 /* SPL -> Uboot */
-#define CONFIG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 
 /* DRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 #endif

diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h
index 4fbd57a..0c41af1 100644
--- a/include/configs/mt7986.h
+++ b/include/configs/mt7986.h

@@ -10,12 +10,12 @@
 #define __MT7986_H
 
 /* Uboot definition */
-#define CONFIG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
 
 /* SPL -> Uboot */
-#define CONFIG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 
 /* DRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 #endif

diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h
index c93d70d..3da7619 100644
--- a/include/configs/mt8183.h
+++ b/include/configs/mt8183.h

@@ -12,11 +12,8 @@
 #include <linux/sizes.h>
 
 
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_COM1		0x11005200
-#define CONFIG_SYS_NS16550_CLK		26000000
+#define CFG_SYS_NS16550_COM1		0x11005200
+#define CFG_SYS_NS16550_CLK		26000000
 
 /* Environment settings */
 #include <config_distro_bootcmd.h>

diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h
index d159416..3a35527 100644
--- a/include/configs/mt8512.h
+++ b/include/configs/mt8512.h

@@ -10,7 +10,7 @@
 #define __MT8512_H
 
 /* Uboot definition */
-#define CONFIG_SYS_UBOOT_START			CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START			CONFIG_TEXT_BASE
 
 #define ENV_BOOT_READ_IMAGE \
 	"boot_rd_img=mmc dev 0" \

diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h
index 7228f3e..0f7981a 100644
--- a/include/configs/mt8516.h
+++ b/include/configs/mt8516.h

@@ -12,11 +12,8 @@
 #include <linux/sizes.h>
 
 
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_COM1		0x11005000
-#define CONFIG_SYS_NS16550_CLK		26000000
+#define CFG_SYS_NS16550_COM1		0x11005000
+#define CFG_SYS_NS16550_CLK		26000000
 
 /* Environment settings */
 #include <config_distro_bootcmd.h>

diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h
index 7cabbef..8a8bc85 100644
--- a/include/configs/mt8518.h
+++ b/include/configs/mt8518.h

@@ -10,8 +10,8 @@
 #define __MT8518_H
 
 /* DRAM definition */
-#define CONFIG_SYS_SDRAM_BASE			0x40000000
-#define CONFIG_SYS_SDRAM_SIZE			0x20000000
+#define CFG_SYS_SDRAM_BASE			0x40000000
+#define CFG_SYS_SDRAM_SIZE			0x20000000
 
 /* Uboot definition */
 

diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 6d4fff3..fa275d6 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h

@@ -27,20 +27,18 @@
  */
 
 /* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE	0x00000000
 
 /*
  * NS16550 Configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK		CFG_SYS_TCLK
 #if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_COM1		MV_UART_CONSOLE_BASE
+#define CFG_SYS_NS16550_COM1		MV_UART_CONSOLE_BASE
 #endif
 
-#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE)
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 300, 600, 1200, 1800, 2400, 4800, \
+#if defined(CONFIG_ARMADA_38X) && !defined(CFG_SYS_BAUDRATE_TABLE)
+#define CFG_SYS_BAUDRATE_TABLE	{ 300, 600, 1200, 1800, 2400, 4800, \
 					  9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 500000, 576000, \
 					  921600, 1000000, 1152000, 1500000, \

diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
index 41bdfae..5c96203 100644
--- a/include/configs/mvebu_alleycat-5.h
+++ b/include/configs/mvebu_alleycat-5.h

@@ -9,9 +9,9 @@
 #include <asm/arch/soc.h>
 
 /* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE   0x200000000
+#define CFG_SYS_SDRAM_BASE   0x200000000
 
-#define CONFIG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE   { 9600, 19200, 38400, 57600, \
 				      115200, 230400, 460800, 921600 }
 
 /* Default Env vars */
@@ -37,6 +37,6 @@
 /*
  * High Level Configuration Options (easy to change)
  */
-#define CONFIG_SYS_TCLK     325000000
+#define CFG_SYS_TCLK     325000000
 
 #endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */

diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
index 6d3cb99..9bfc48c 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h

@@ -13,9 +13,9 @@
  */
 
 /* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE	0x00000000
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 300, 600, 1200, 1800, 2400, 4800, \
+#define CFG_SYS_BAUDRATE_TABLE	{ 300, 600, 1200, 1800, 2400, 4800, \
 					  9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 500000, 576000, \
 					  921600, 1000000, 1152000, 1500000, \

diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index 5debd91..beac3ae 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h

@@ -9,14 +9,14 @@
 /*
  * High Level Configuration Options (easy to change)
  */
-#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+#define CFG_SYS_TCLK		250000000	/* 250MHz */
 
 /* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE	0x00000000
 
 /* auto boot */
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
 					  115200, 230400, 460800, 921600 }
 
 /*

diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index dd303a1..aa3d7a1 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h

@@ -10,7 +10,7 @@
 /* Memory configuration */
 #define PHYS_SDRAM_1			0x40000000	/* Base address */
 #define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 /* Status LED */
 

diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index 4c05312..f597cdb 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h

@@ -13,7 +13,7 @@
 /* Memory configuration */
 #define PHYS_SDRAM_1			0x40000000	/* Base address */
 #define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 /* Extra Environments */
 #define CONFIG_EXTRA_ENV_SETTINGS \

diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 140f5e9..c740d85 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h

@@ -13,15 +13,10 @@
 /* Memory configuration */
 #define PHYS_SDRAM_1			0x40000000	/* Base address */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 /* UBI and NAND partitioning */
 
-/* RTC */
-#ifdef	CONFIG_CMD_DATE
-#define	CONFIG_RTC_MXS
-#endif
-
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"ubifs_file=filesystem.ubifs\0" \

diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 95afb35..ddd37b3 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h

@@ -17,19 +17,15 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_FSL_IIM
 
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 
 /* PMIC Controller */
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
 #define CONFIG_FSL_PMIC_BUS	0
 #define CONFIG_FSL_PMIC_CS	0
 #define CONFIG_FSL_PMIC_CLK	2500000
 #define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
 #define CONFIG_FSL_PMIC_BITLEN	32
-#define CONFIG_RTC_MC13XXX
 
 /*
  * MMC Configs
@@ -112,13 +108,13 @@
 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
 #define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
 
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+#define CFG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CFG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
 
-#define CONFIG_SYS_DDR_CLKSEL	0
-#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
-#define CONFIG_SYS_MAIN_PWR_ON
+#define CFG_SYS_DDR_CLKSEL	0
+#define CFG_SYS_CLKTL_CBCDR	0x59E35100
+#define CFG_SYS_MAIN_PWR_ON
 
 /*-----------------------------------------------------------------------
  * environment organization

diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index 7783563..cd806cb 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h

@@ -60,13 +60,10 @@
 #define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
 #define PHYS_SDRAM_SIZE			(gd->ram_size)
 
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+#define CFG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CFG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
 
 /* environment organization */
 
-/* Framebuffer and LCD */
-#define CONFIG_IMX_VIDEO_SKIP
-
 #endif /* __CONFIG_H */

diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 3c9b2ad..d0107fc 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h

@@ -22,9 +22,7 @@
 #define CONFIG_MXC_USB_FLAGS	0
 
 /* PMIC Controller */
-#define CONFIG_POWER_FSL
-#define CONFIG_POWER_FSL_MC13892
-#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
+#define CFG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
 #define CFG_SYS_FSL_PMIC_I2C_ADDR	0x8
 
 /* Command definition */
@@ -95,9 +93,9 @@
 #define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
 #define PHYS_SDRAM_SIZE			(gd->ram_size)
 
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+#define CFG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CFG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
 
 /* Framebuffer and LCD */
 

diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index b26613a..9464d6e 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h

@@ -87,7 +87,7 @@
 
 /* Miscellaneous configurable options */
 
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)     /* 256M */
+#define CFG_SYS_BOOTMAPSZ (256 << 20)     /* 256M */
 
 /* Physical Memory Map */
 #define PHYS_SDRAM_1			CSD0_BASE_ADDR
@@ -96,17 +96,10 @@
 #define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
 #define PHYS_SDRAM_SIZE			(gd->ram_size)
 
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+#define CFG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CFG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
 
 /* FLASH and environment organization */
 
-#define CONFIG_FSL_IIM
-
-/* Backlight Control */
-#define CONFIG_IMX6_PWM_PER_CLK 66666000
-
-#define CONFIG_IMX_VIDEO_SKIP
-
 #endif				/* __CONFIG_H */

diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 4314556..245530a 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h

@@ -12,7 +12,7 @@
 #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
 #else
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE	L2_PL310_BASE
+#define CFG_SYS_PL310_BASE	L2_PL310_BASE
 #endif
 
 #endif

diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index bc90b95..f7f209c 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h

@@ -11,15 +11,9 @@
 
 #include "mx6_common.h"
 
-#include "imx6_spl.h"
-
 /* MMC Configs */
 #define CFG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
 
-/* Framebuffer */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
 /* USB */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 
@@ -87,9 +81,9 @@
 #include <config_distro_bootcmd.h>
 
 /* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE          MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE          MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* Environment organization */
 

diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h
index ad53f17..f6d3b2e 100644
--- a/include/configs/mx6memcal.h
+++ b/include/configs/mx6memcal.h

@@ -11,7 +11,6 @@
 /* SPL */
 
 #include "mx6_common.h"
-#include "imx6_spl.h"
 
 #ifdef CONFIG_SERIAL_CONSOLE_UART1
 #if defined(CONFIG_MX6SL)
@@ -28,9 +27,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 #define CONFIG_MXC_USB_PORTSC	PORT_PTS_UTMI
 

diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index bc9fab1..6294fd1 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h

@@ -139,16 +139,12 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* Environment organization */
 
-/* Framebuffer */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
 #define CONFIG_USBD_HS
 
 #endif                         /* __MX6QSABRE_COMMON_CONFIG_H */

diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
index 61570b7..888da7c 100644
--- a/include/configs/mx6sabreauto.h
+++ b/include/configs/mx6sabreauto.h

@@ -8,10 +8,6 @@
 #ifndef __MX6SABREAUTO_CONFIG_H
 #define __MX6SABREAUTO_CONFIG_H
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 #define CONFIG_MXC_UART_BASE	UART4_BASE
 #define CONSOLE_DEV		"ttymxc3"
 
@@ -19,8 +15,7 @@
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x30, 8}, {0x32, 8}, {0x34, 8} }
+#define CFG_SYS_I2C_PCA953X_WIDTH	{ {0x30, 8}, {0x32, 8}, {0x34, 8} }
 
 #include "mx6sabre_common.h"
 
@@ -30,18 +25,17 @@
 #endif
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
+#define CFG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
 #endif
 
 #define CFG_SYS_FSL_USDHC_NUM	2
 
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CFG_SYS_NAND_BASE           0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
 
 /* PMIC */
-#define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 #endif                         /* __MX6SABREAUTO_CONFIG_H */

diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 49cd151..78a554d 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h

@@ -8,10 +8,6 @@
 #ifndef __MX6SABRESD_CONFIG_H
 #define __MX6SABRESD_CONFIG_H
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONSOLE_DEV		"ttymxc0"
 
@@ -29,7 +25,6 @@
 #endif
 
 /* PMIC */
-#define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* USB Configs */

diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 26b97bd3..358d9f4 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h

@@ -10,10 +10,6 @@
 
 #include "mx6_common.h"
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 #define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
 
 /* MMC Configs */
@@ -86,9 +82,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment organization */
 

diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
index 44a5eef..8731f6a 100644
--- a/include/configs/mx6sllevk.h
+++ b/include/configs/mx6sllevk.h

@@ -82,9 +82,9 @@
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 #define PHYS_SDRAM_SIZE			SZ_2G
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment organization */
 
@@ -92,8 +92,6 @@
 #define CFG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
 #define CFG_SYS_FSL_USDHC_NUM	3
 
-#define CONFIG_IOMUX_LPSR
-
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)

diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 0d9764e..0dd4056 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h

@@ -78,15 +78,15 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* MMC Configuration */
 #define CFG_SYS_FSL_ESDHC_ADDR	USDHC3_BASE_ADDR
 
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CFG_SYS_NAND_BASE           0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
 

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 83779f0..6f5dffe 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h

@@ -12,10 +12,6 @@
 
 #include "mx6_common.h"
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 #ifdef CONFIG_IMX_BOOTAUX
@@ -110,9 +106,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* MMC Configuration */
 #define CFG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR

diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index d0e3d3f..cb1019b 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h

@@ -15,9 +15,6 @@
 
 #define is_mx6ul_9x9_evk()	CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
 
-/* SPL options */
-#include "imx6_spl.h"
-
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* MMC Configs */
@@ -111,9 +108,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* environment organization */
 

diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index 604923e..0e98609 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h

@@ -102,14 +102,12 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* environment organization */
 
-#define CONFIG_IOMUX_LPSR
-
 #ifdef CONFIG_CMD_NET
 #define CONFIG_FEC_ENET_DEV		1
 #endif

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 4704276..d5af699 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h

@@ -17,9 +17,6 @@
 #define CONFIG_MXC_GPT_HCLK
 #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
 
-/* Enable iomux-lpsr support */
-#define CONFIG_IOMUX_LPSR
-
 /* Miscellaneous configurable options */
 
 /* UART */

diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 2a97d2f..6c16552 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h

@@ -81,9 +81,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* environment organization */
 
@@ -93,7 +93,7 @@
  */
 #ifdef CONFIG_NAND_MXS
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
 #endif

diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h
index 62e8e62..85922fa 100644
--- a/include/configs/mx7ulp_com.h
+++ b/include/configs/mx7ulp_com.h

@@ -18,7 +18,7 @@
 /* Using ULP WDOG for reset */
 #define WDOG_BASE_ADDR			WDG1_RBASE
 
-#define CONFIG_SYS_HZ_CLOCK		1000000 /* Fixed at 1MHz from TSTMR */
+#define CFG_SYS_HZ_CLOCK		1000000 /* Fixed at 1MHz from TSTMR */
 
 /* UART */
 #define LPUART_BASE			LPUART4_RBASE
@@ -26,7 +26,7 @@
 /* Physical Memory Map */
 
 #define PHYS_SDRAM			0x60000000
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"image=zImage\0" \
@@ -48,8 +48,8 @@
 			"bootz ${loadaddr} - ${fdt_addr}; " \
 		"fi;\0" \
 
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	SZ_256K
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	SZ_256K
 
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #endif	/* __CONFIG_H */

diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index e938249..99e0189 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h

@@ -15,7 +15,7 @@
 /* Using ULP WDOG for reset */
 #define WDOG_BASE_ADDR			WDG1_RBASE
 
-#define CONFIG_SYS_HZ_CLOCK		1000000 /* Fixed at 1Mhz from TSTMR */
+#define CFG_SYS_HZ_CLOCK		1000000 /* Fixed at 1Mhz from TSTMR */
 
 /* UART */
 #define LPUART_BASE			LPUART4_RBASE
@@ -26,7 +26,7 @@
 
 #define PHYS_SDRAM			0x60000000
 #define PHYS_SDRAM_SIZE			SZ_1G
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
@@ -92,7 +92,7 @@
 			"bootz; " \
 		"fi;\0" \
 
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	SZ_256K
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	SZ_256K
 
 #endif	/* __CONFIG_H */

diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index e861038..30f27e7 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h

@@ -46,11 +46,11 @@
 /* Memory sizes */
 
 /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
+#define CFG_SYS_INIT_RAM_ADDR	0x00000000
 #if defined(CONFIG_MX23)
-#define CONFIG_SYS_INIT_RAM_SIZE	(32 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE	(32 * 1024)
 #elif defined(CONFIG_MX28)
-#define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE	(128 * 1024)
 #endif
 
 /* Point initial SP in SRAM so SPL can use it too. */
@@ -83,12 +83,7 @@
 
 /* NAND */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x60000000
-#endif
-
-/* OCOTP */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXS_OCOTP
+#define CFG_SYS_NAND_BASE		0x60000000
 #endif
 
 /* SPI */

diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h
index a777305..a32fcd5 100644
--- a/include/configs/mys_6ulx.h
+++ b/include/configs/mys_6ulx.h

@@ -10,9 +10,6 @@
 #include <linux/sizes.h>
 #include "mx6_common.h"
 
-/* SPL options */
-#include "imx6_spl.h"
-
 #define CFG_SYS_FSL_USDHC_NUM	1
 
 /* Console configs */
@@ -25,12 +22,12 @@
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 #define PHYS_SDRAM_SIZE			SZ_256M
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)

diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index ec5339d..5020b3b 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h

@@ -26,10 +26,6 @@
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
-/* Framebuffer and LCD */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
 #ifdef CONFIG_CMD_MMC
 #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
 #else
@@ -90,9 +86,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* Environment organization */
 

diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 99a020c..caaa9ed 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h

@@ -40,24 +40,14 @@
  */
 #define V_NS16550_CLK		48000000		/* 48MHz (APLL96/2) */
 
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CFG_SYS_NS16550_CLK		V_NS16550_CLK
 
 /*
  * select serial console configuration
  */
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CFG_SYS_NS16550_COM3		OMAP34XX_UART3
 
-#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE
-#define CONFIG_USB_TTY
-#define CONFIG_USBD_VENDORID		0x0421
-#define CONFIG_USBD_PRODUCTID_CDCACM	0x01c8
-#define CONFIG_USBD_PRODUCTID_GSERIAL	0x01c8
-#define CONFIG_USBD_MANUFACTURER	"Nokia"
-#define CONFIG_USBD_PRODUCT_NAME	"N900 (U-Boot)"
+#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
 
 #define GPIO_SLIDE			71
 
@@ -65,7 +55,7 @@
  * Board ONENAND Info.
  */
 
-#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+#define CFG_SYS_ONENAND_BASE		ONENAND_MAP
 
 /* Environment information */
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -151,7 +141,7 @@
  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  * This rate is divided by a local divisor.
  */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CFG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 
 /*
  * Physical Memory Map
@@ -162,16 +152,16 @@
  * FLASH and environment organization
  */
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CFG_SYS_INIT_RAM_SIZE	0x800
 
 /*
  * Attached kernel image
  */
 
 #define SDRAM_SIZE			0x10000000	/* 256 MB */
-#define SDRAM_END			(CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE)
+#define SDRAM_END			(CFG_SYS_SDRAM_BASE + SDRAM_SIZE)
 
 #define IMAGE_MAXSIZE			0x1FF800	/* 2 MB - 2 kB */
 #define KERNEL_OFFSET			0x40000		/* 256 kB */

diff --git a/include/configs/novena.h b/include/configs/novena.h
index f2a04ca..4e46dfc 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h

@@ -30,12 +30,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
-
-/* SPL */
-#include "imx6_spl.h"			/* common IMX6 SPL configuration */
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* I2C */
 #define CONFIG_I2C_MULTI_BUS
@@ -53,7 +50,6 @@
 #endif
 
 /* PMIC */
-#define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* UART */
@@ -67,10 +63,6 @@
 #define CONFIG_USBD_HS
 #endif
 
-/* Video output */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
 /* Extra U-Boot environment. */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"fdt_high=0xffffffff\0"						\

diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h
index ccc203f..09c4ddb 100644
--- a/include/configs/npi_imx6ull.h
+++ b/include/configs/npi_imx6ull.h

@@ -10,9 +10,6 @@
 #include <linux/sizes.h>
 #include "mx6_common.h"
 
-/* SPL options */
-#include "imx6_spl.h"
-
 #define CFG_SYS_FSL_USDHC_NUM	1
 
 /* Console configs */
@@ -26,12 +23,12 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)

diff --git a/include/configs/nsim.h b/include/configs/nsim.h
index d469ef8..013a349 100644
--- a/include/configs/nsim.h
+++ b/include/configs/nsim.h

@@ -12,9 +12,9 @@
  * Memory configuration
  */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE		SZ_256M
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE		SZ_256M
 
 /*
  * Console configuration

diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index c59e103..baa4521 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h

@@ -16,7 +16,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 /* SPI */
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)

diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h
index 00f7d87..ea1edab 100644
--- a/include/configs/o4-imx6ull-nano.h
+++ b/include/configs/o4-imx6ull-nano.h

@@ -7,9 +7,9 @@
 #include "mx6_common.h"
 
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #if IS_ENABLED(CONFIG_CMD_USB)
 #	define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)

diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h
index 0fa7490..c0ea9e8 100644
--- a/include/configs/octeon_common.h
+++ b/include/configs/octeon_common.h

@@ -8,12 +8,12 @@
 #define __OCTEON_COMMON_H__
 
 #if defined(CONFIG_RAM_OCTEON)
-#define CONFIG_SYS_INIT_SP_OFFSET	0x20180000
+#define CFG_SYS_INIT_SP_OFFSET	0x20180000
 #else
 /* No DDR init -> run in L2 cache with limited resources */
-#define CONFIG_SYS_INIT_SP_OFFSET	0x00180000
+#define CFG_SYS_INIT_SP_OFFSET	0x00180000
 #endif
 
-#define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
+#define CFG_SYS_SDRAM_BASE		0xffffffff80000000
 
 #endif /* __OCTEON_COMMON_H__ */

diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h
index ab1eb78..03d1a8e 100644
--- a/include/configs/octeontx2_common.h
+++ b/include/configs/octeontx2_common.h

@@ -10,7 +10,7 @@
 /** Maximum size of image supported for bootm (and bootable FIT images) */
 
 /** Memory base address */
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_SDRAM_BASE		CONFIG_TEXT_BASE
 
 /** Stack starting address */
 

diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h
index 38f99ab..58275cc 100644
--- a/include/configs/octeontx_common.h
+++ b/include/configs/octeontx_common.h

@@ -36,7 +36,7 @@
 /** Maximum size of image supported for bootm (and bootable FIT images) */
 
 /** Memory base address */
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_SDRAM_BASE		CONFIG_TEXT_BASE
 
 /** Stack starting address */
 

diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index babd3ca..f252b34 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h

@@ -14,12 +14,12 @@
 #include <configs/exynos4-common.h>
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE	0x10502000
+#define CFG_SYS_PL310_BASE	0x10502000
 #endif
 
-#define CONFIG_SYS_SDRAM_BASE	0x40000000
+#define CFG_SYS_SDRAM_BASE	0x40000000
 #define SDRAM_BANK_SIZE		(256 << 20)	/* 256 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1		CFG_SYS_SDRAM_BASE
 
 #include <linux/sizes.h>
 
@@ -143,10 +143,4 @@
 	"kernel_addr_r=0x41000000\0" \
 	BOOTENV
 
-/*
- * Supported Odroid boards: X3, U3
- * TODO: Add Odroid X support
- */
-#define CONFIG_MISC_COMMON
-
 #endif	/* __CONFIG_H */

diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 1564629..5bbe7aa 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h

@@ -10,7 +10,7 @@
 #include <configs/exynos5420-common.h>
 #include <configs/exynos5-common.h>
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 #define TZPC_BASE_OFFSET		0x10000
 
@@ -57,7 +57,6 @@
 	"params.bin raw 0x1880 0x20\0"
 
 /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */
-#define CONFIG_MISC_COMMON
 #define CONFIG_SET_DFU_ALT_BUF_LEN	(SZ_1K)
 
 /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index d46ca33..f4e23bb 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h

@@ -20,11 +20,11 @@
 
 /* NAND */
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FLASH_BASE		NAND_BASE
-#define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_FLASH_BASE		NAND_BASE
+#define CFG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
                                          10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE         512
-#define CONFIG_SYS_NAND_ECCBYTES        3
+#define CFG_SYS_NAND_ECCSIZE         512
+#define CFG_SYS_NAND_ECCBYTES        3
 /* NAND: SPL falcon mode configs */
 #endif /* CONFIG_MTD_RAW_NAND */
 

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 77629d7..8bb8521 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h

@@ -25,11 +25,11 @@
 
 /* NAND */
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FLASH_BASE		NAND_BASE
-#define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
+#define CFG_SYS_FLASH_BASE		NAND_BASE
+#define CFG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
                                          10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE         512
-#define CONFIG_SYS_NAND_ECCBYTES        3
+#define CFG_SYS_NAND_ECCSIZE         512
+#define CFG_SYS_NAND_ECCBYTES        3
 #endif /* CONFIG_MTD_RAW_NAND */
 
 #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \

diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 97f47ea..a6b5e55 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h

@@ -66,18 +66,18 @@
 	BOOTENV
 
 /* OneNAND config */
-#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
-#define CONFIG_SYS_ONENAND_BLOCK_SIZE	(128*1024)
+#define CFG_SYS_ONENAND_BASE		ONENAND_MAP
+#define CFG_SYS_ONENAND_BLOCK_SIZE	(128*1024)
 
 /* NAND config */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
 					 34, 35, 36, 37, 38, 39, 40, 41, \
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 #endif /* __IGEP00X0_H */

diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 442a3ca..3895537 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h

@@ -17,17 +17,15 @@
 /* Board NAND Info. */
 #ifdef CONFIG_MTD_RAW_NAND
 						  /* NAND devices */
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+#define CFG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
 					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
 					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
 					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
 					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
 					 52, 53, 54, 55, 56}
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	13
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	13
 #endif
 
 /* Environment information */
@@ -146,9 +144,9 @@
 
 /* **** PISMO SUPPORT *** */
 #if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CFG_SYS_FLASH_BASE		0x10000000
 #endif
 
-#define CONFIG_SYS_FLASH_SIZE		0x4000000
+#define CFG_SYS_FLASH_SIZE		0x4000000
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index cce5556..d7fa2d4 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h

@@ -28,7 +28,7 @@
 
 #include <configs/ti_omap5_common.h>
 
-#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+#define CFG_SYS_NS16550_COM3		UART3_BASE
 
 /* MMC ENV related defines */
 
@@ -36,9 +36,8 @@
 #define CONFIG_HSMMC2_8BIT
 
 /* Required support for the TCA642X GPIO we have on the uEVM */
-#define CONFIG_TCA642X
-#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
-#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
+#define CFG_SYS_I2C_TCA642X_BUS_NUM 4
+#define CFG_SYS_I2C_TCA642X_ADDR 0x22
 
 /* Enabled commands */
 

diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 4103930..788a111 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h

@@ -17,9 +17,9 @@
 /*
  * SoC Configuration
  */
-#define CONFIG_SYS_OSCIN_FREQ		24000000
-#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_OSCIN_FREQ		24000000
+#define CFG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 
 /*
  * Memory Info
@@ -32,7 +32,7 @@
 
 /* memtest will be run on 16MB */
 
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+#define CFG_SYS_DA850_SYSCFG_SUSPSRC (	\
 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
 	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
@@ -44,17 +44,17 @@
  */
 
 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
-#define CONFIG_SYS_DA850_PLL0_PLLM     18
-#define CONFIG_SYS_DA850_PLL1_PLLM     21
+#define CFG_SYS_DA850_PLL0_PLLM     18
+#define CFG_SYS_DA850_PLL1_PLLM     21
 
 /*
  * DDR2 memory configuration
  */
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
 					DV_DDR_PHY_EXT_STRBEN | \
 					(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDBCR (		  \
+#define CFG_SYS_DA850_DDR2_SDBCR (		  \
 	(1 << DV_DDR_SDCR_DDR2EN_SHIFT)		| \
 	(1 << DV_DDR_SDCR_DDREN_SHIFT)		| \
 	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
@@ -64,9 +64,9 @@
 	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 
 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+#define CFG_SYS_DA850_DDR2_SDBCR2 0
 
-#define CONFIG_SYS_DA850_DDR2_SDTIMR (		  \
+#define CFG_SYS_DA850_DDR2_SDTIMR (		  \
 	(19 << DV_DDR_SDTMR1_RFC_SHIFT)		| \
 	(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
 	(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
@@ -76,7 +76,7 @@
 	(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
 	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		  \
+#define CFG_SYS_DA850_DDR2_SDTIMR2 (		  \
 	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)	| \
 	(2 << DV_DDR_SDTMR2_XP_SHIFT)		| \
 	(0 << DV_DDR_SDTMR2_ODT_SHIFT)		| \
@@ -85,48 +85,41 @@
 	(1 << DV_DDR_SDTMR2_RTP_SHIFT)		| \
 	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
-#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+#define CFG_SYS_DA850_DDR2_SDRCR    0x00000492
+#define CFG_SYS_DA850_DDR2_PBBPR    0x30
 
 /*
  * Serial Driver info
  */
-#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CFG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
 
-#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
-#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+#define CFG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CFG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
 
 /*
  * I2C Configuration
  */
-#define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20
+#define CFG_SYS_I2C_EXPANDER_ADDR	0x20
 
 /*
  * Flash & Environment
  */
 #ifdef CONFIG_MTD_RAW_NAND
-#define	CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_CS		3
-#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE	0x10
-#define CONFIG_SYS_NAND_MASK_ALE	0x8
-#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CFG_SYS_NAND_CS		3
+#define CFG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_SYS_NAND_MASK_CLE	0x10
+#define CFG_SYS_NAND_MASK_ALE	0x8
 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
-					CONFIG_SYS_NAND_U_BOOT_SIZE - \
-					CONFIG_SYS_MALLOC_LEN -       \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS		{				\
+#define CFG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define CFG_SYS_NAND_U_BOOT_DST	0xc1080000
+#define CFG_SYS_NAND_U_BOOT_START	CFG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_ECCPOS		{				\
 				6, 7, 8, 9, 10, 11, 12, 13, 14, 15,	\
 				22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
 				38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
 				54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	10
 #endif
 
 /*
@@ -161,7 +154,7 @@
 /* defines for SPL */
 
 /* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CFG_SYS_SDRAM_BASE		0xc0000000
 
 #include <asm/arch/hardware.h>
 

diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h
index 3ff8187..5b097e9 100644
--- a/include/configs/openpiton-riscv64.h
+++ b/include/configs/openpiton-riscv64.h

@@ -14,7 +14,7 @@
 #include <linux/sizes.h>
 
 /* Environment options */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
 
 /* ---------------------------------------------------------------------
  * Board boot configuration

diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h
index 3e551e1..e42a736 100644
--- a/include/configs/opos6uldev.h
+++ b/include/configs/opos6uldev.h

@@ -10,17 +10,13 @@
 
 #include "mx6_common.h"
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 /* Miscellaneous configurable options */
 #define CONFIG_STANDALONE_LOAD_ADDR	CONFIG_SYS_LOAD_ADDR
 
 /* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE		MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* USB */
 #ifdef CONFIG_USB_EHCI_MX6

diff --git a/include/configs/origen.h b/include/configs/origen.h
index 36aaa7c..6633d54 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h

@@ -11,8 +11,8 @@
 #include <configs/exynos4-common.h>
 
 /* ORIGEN has 4 bank of DRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CFG_SYS_SDRAM_BASE
 #define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
 /* Power Down Modes */

diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h
index b0233b9..8d0311c 100644
--- a/include/configs/owl-common.h
+++ b/include/configs/owl-common.h

@@ -11,7 +11,7 @@
 #define _OWL_COMMON_CONFIG_H_
 
 /* SDRAM Definitions */
-#define CONFIG_SYS_SDRAM_BASE		0x0
+#define CFG_SYS_SDRAM_BASE		0x0
 
 /* Some commands use this as the default load address */
 

diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h
index d155e55..c96deda 100644
--- a/include/configs/p1_p2_bootsrc.h
+++ b/include/configs/p1_p2_bootsrc.h

@@ -7,11 +7,11 @@
 
 #include <linux/stringify.h>
 
-#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR)
-#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required"
+#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CFG_SYS_I2C_PCA9557_ADDR)
+#error "CONFIG_SYS_SPD_BUS_NUM and CFG_SYS_I2C_PCA9557_ADDR are required"
 #endif
 
-#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1
+#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CFG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CFG_SYS_I2C_PCA9557_ADDR 3 msk 1
 
 #define __VAR_CMD(var, cmd) __stringify(var=cmd\0)
 #define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 778bf51..9738e9f 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h

@@ -13,7 +13,6 @@
 #include <linux/stringify.h>
 
 #if defined(CONFIG_TARGET_P1020RDB_PC)
-#define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK		0x03
 #define __SW_BOOT_NOR		0x5c
@@ -43,7 +42,6 @@
  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  */
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK		0x03
 #define __SW_BOOT_NOR		0x64
@@ -63,7 +61,6 @@
 #endif
 
 #if defined(CONFIG_TARGET_P2020RDB)
-#define CONFIG_VSC7385_ENET
 #define __SW_BOOT_MASK		0x03
 #define __SW_BOOT_NOR		0xc8
 #define __SW_BOOT_SPI		0x28
@@ -83,28 +80,28 @@
 #endif
 
 #ifdef CONFIG_SDCARD
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	CONFIG_TEXT_BASE
-#define CONFIG_SYS_MMC_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_MMC_U_BOOT_START	CONFIG_TEXT_BASE
 #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
+#define CFG_SYS_MMC_U_BOOT_OFFS	(CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
 #else
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CFG_SYS_MMC_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
 #endif
 #elif defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		CONFIG_TEXT_BASE
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST		CONFIG_TEXT_BASE
+#define CFG_SYS_SPI_FLASH_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
 #elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CFG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CFG_SYS_NAND_U_BOOT_START	(0x11000000)
 #elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CFG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CFG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CFG_SYS_NAND_U_BOOT_START	0xf8f80000
 #endif /* not CONFIG_TPL_BUILD */
 #endif
 
@@ -112,58 +109,57 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE
 
-#define CONFIG_SYS_CCSRBAR		0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR		0xffe00000
+#define CFG_SYS_CCSRBAR_PHYS_LOW	CFG_SYS_CCSRBAR
 
 /* DDR Setup */
 #define SPD_EEPROM_ADDRESS 0x52
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
+#define CFG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
 #else
-#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
+#define CFG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
 #endif
-#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE		(1u << (CFG_SYS_SDRAM_SIZE_LAW - 19))
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 /* Default settings for DDR3 */
 #ifndef CONFIG_TARGET_P2020RDB
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
-#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
-#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
+#define CFG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CFG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CFG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CFG_SYS_DDR_CS1_BNDS		0x0040007f
+#define CFG_SYS_DDR_CS1_CONFIG	0x80014302
+#define CFG_SYS_DDR_CS1_CONFIG_2	0x00000000
 
-#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CFG_SYS_DDR_INIT_ADDR	0x00000000
+#define CFG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CFG_SYS_DDR_MODE_CONTROL	0x00000000
 
-#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
-#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
-#define CONFIG_SYS_DDR_RCW_1		0x00000000
-#define CONFIG_SYS_DDR_RCW_2		0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
-#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
-#define CONFIG_SYS_DDR_TIMING_4		0x00220001
-#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+#define CFG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CFG_SYS_DDR_WRLVL_CONTROL	0x8655A608
+#define CFG_SYS_DDR_SR_CNTR		0x00000000
+#define CFG_SYS_DDR_RCW_1		0x00000000
+#define CFG_SYS_DDR_RCW_2		0x00000000
+#define CFG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
+#define CFG_SYS_DDR_CONTROL_2	0x04401050
+#define CFG_SYS_DDR_TIMING_4		0x00220001
+#define CFG_SYS_DDR_TIMING_5		0x03402400
 
-#define CONFIG_SYS_DDR_TIMING_3		0x00020000
-#define CONFIG_SYS_DDR_TIMING_0		0x00330004
-#define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
-#define CONFIG_SYS_DDR_MODE_1		0x40461520
-#define CONFIG_SYS_DDR_MODE_2		0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL		0x0C300000
+#define CFG_SYS_DDR_TIMING_3		0x00020000
+#define CFG_SYS_DDR_TIMING_0		0x00330004
+#define CFG_SYS_DDR_TIMING_1		0x6f6B4846
+#define CFG_SYS_DDR_TIMING_2		0x0FA8C8CF
+#define CFG_SYS_DDR_CLK_CTRL		0x03000000
+#define CFG_SYS_DDR_MODE_1		0x40461520
+#define CFG_SYS_DDR_MODE_2		0x8000c000
+#define CFG_SYS_DDR_INTERVAL		0x0C300000
 #endif
 
 /*
@@ -186,43 +182,43 @@
  * Local Bus Definitions
  */
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_FLASH_BASE		0xec000000
+#define CFG_SYS_FLASH_BASE		0xec000000
 #else
-#define CONFIG_SYS_FLASH_BASE		0xef000000
+#define CFG_SYS_FLASH_BASE		0xef000000
 #endif
 
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)
 #else
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \
 	| BR_PS_16 | BR_V)
 
 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
 
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CFG_SYS_NAND_BASE		0xff800000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#define CFG_SYS_NAND_BASE_PHYS	0xfff800000ull
 #else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE_PHYS	CFG_SYS_NAND_BASE
 #endif
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 	| BR_PS_8	/* Port Size = 8 bit */ \
 	| BR_MS_FCM	/* MSEL = FCM */ \
 	| BR_V)	/* valid */
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
+#define CFG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
 	| OR_FCM_PGS	/* Large Page*/ \
 	| OR_FCM_CSCT \
 	| OR_FCM_CST \
@@ -231,7 +227,7 @@
 	| OR_FCM_TRLX \
 	| OR_FCM_EHTR)
 #else
-#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
+#define CFG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
 	| OR_FCM_CSCT \
 	| OR_FCM_CST \
 	| OR_FCM_CHT \
@@ -241,50 +237,44 @@
 #endif
 #endif /* CONFIG_NAND_FSL_ELBC */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
+#define CFG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#define CFG_SYS_INIT_RAM_ADDR_PHYS	CFG_SYS_INIT_RAM_ADDR
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
 #endif
 /* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CFG_SYS_INIT_RAM_SIZE	0x00004000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_SYS_CPLD_BASE	0xffa00000
+#define CFG_SYS_CPLD_BASE	0xffa00000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
+#define CFG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
 #else
-#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE_PHYS	CFG_SYS_CPLD_BASE
 #endif
 /* CPLD config size: 1Mb */
 
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
 #define __VSCFW_ADDR			"vscfw_addr=ef000000\0"
-#define CONFIG_SYS_VSC7385_BASE		0xffb00000
+#define CFG_SYS_VSC7385_BASE		0xffb00000
 
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
+#define CFG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
 #else
-#define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
+#define CFG_SYS_VSC7385_BASE_PHYS	CFG_SYS_VSC7385_BASE
 #endif
 
-#define CONFIG_SYS_VSC7385_BR_PRELIM	\
-	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
-			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
-			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
-
 /* The size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE_SIZE	8192
 #endif
@@ -298,18 +288,18 @@
 */
 #if defined(CONFIG_SPL_BUILD)
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CFG_SYS_INIT_L2_ADDR_PHYS	CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END	(CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CFG_SYS_INIT_L2_ADDR_PHYS	CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END	(CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #else
-#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CFG_SYS_INIT_L2_ADDR_PHYS	CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END	(CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 #endif /* CONFIG_TPL_BUILD */
 #endif
 #endif
@@ -319,31 +309,25 @@
  * shorted - index 1
  */
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
+#define CFG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x4600)
 
 /* I2C */
 #if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#define CFG_SYS_I2C_NOPROBES		{ {0, 0x29} }
 #endif
 
 /*
  * I2C2 EEPROM
  */
 
-#define CONFIG_RTC_PT7C4338
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68
-#define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
+#define CFG_SYS_I2C_RTC_ADDR		0x68
+#define CFG_SYS_I2C_PCA9557_ADDR	0x18
 
 /* enable read and write access to EEPROM */
 
@@ -354,31 +338,31 @@
  */
 
 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CFG_SYS_PCIE2_IO_VIRT	0xffc10000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#define CFG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
 #else
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CFG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
 
 /* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CFG_SYS_PCIE1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS	0x80000000
 #endif
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CFG_SYS_PCIE1_IO_VIRT	0xffc00000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+#define CFG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
 #else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#define CFG_SYS_PCIE1_IO_PHYS	0xffc00000
 #endif
 #endif /* CONFIG_PCI */
 
@@ -408,7 +392,7 @@
  */
 #if defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR		(CFG_SYS_INIT_L2_ADDR + (160 << 10))
 #endif
 #endif
 
@@ -429,7 +413,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
 
 /*
  * Environment Configuration

diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index c12f4d0..a945f4e 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h

@@ -17,7 +17,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 

diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index dea8712..2a1660b 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h

@@ -11,9 +11,6 @@
 #include <linux/sizes.h>
 #include "mx6_common.h"
 
-/* SPL options */
-#include "imx6_spl.h"
-
 /*
  * There is a bug in some i.MX6UL processors that results in the initial
  * portion of OCRAM being unavailable when booting from (at least) an SD
@@ -37,12 +34,12 @@
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 #define PHYS_SDRAM_SIZE			SZ_256M
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)

diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index 2bdae8a..4421e74 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h

@@ -13,9 +13,6 @@
 #include <linux/stringify.h>
 #include "mx6_common.h"
 
-/* SPL options */
-#include "imx6_spl.h"
-
 #define CFG_SYS_FSL_USDHC_NUM	2
 
 /* Environment settings */
@@ -39,12 +36,12 @@
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 #define PHYS_SDRAM_SIZE			SZ_256M
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* NAND */
-#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_BASE		0x40000000
 
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)

diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index a04a03a..5c2ff5d 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h

@@ -118,9 +118,9 @@
 #define PHYS_SDRAM			(0x80000000)
 #define PHYS_SDRAM_SIZE			(CONFIG_PCM052_DDR_SIZE * SZ_1M)
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* environment organization */
 

diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
index 0119090..3674e4c 100644
--- a/include/configs/pcm058.h
+++ b/include/configs/pcm058.h

@@ -6,10 +6,6 @@
 #ifndef __PCM058_CONFIG_H
 #define __PCM058_CONFIG_H
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 #include "mx6_common.h"
 
 #define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
@@ -19,9 +15,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
 /* Environment organization */
 #define ENV_MMC \

diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h
index ed3201a..7180783 100644
--- a/include/configs/pdu001.h
+++ b/include/configs/pdu001.h

@@ -50,11 +50,11 @@
 	"\0"
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1	UART0_BASE
-#define CONFIG_SYS_NS16550_COM2	UART1_BASE
-#define CONFIG_SYS_NS16550_COM3	UART2_BASE
-#define CONFIG_SYS_NS16550_COM4	UART3_BASE
-#define CONFIG_SYS_NS16550_COM5	UART4_BASE
-#define CONFIG_SYS_NS16550_COM6	UART5_BASE
+#define CFG_SYS_NS16550_COM1	UART0_BASE
+#define CFG_SYS_NS16550_COM2	UART1_BASE
+#define CFG_SYS_NS16550_COM3	UART2_BASE
+#define CFG_SYS_NS16550_COM4	UART3_BASE
+#define CFG_SYS_NS16550_COM5	UART4_BASE
+#define CFG_SYS_NS16550_COM6	UART5_BASE
 
 #endif	/* ! __CONFIG_PDU001_H */

diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h
index 7a8d3c6..fb6eb57 100644
--- a/include/configs/peach-pi.h
+++ b/include/configs/peach-pi.h

@@ -20,9 +20,7 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
-#define CONFIG_SYS_SDRAM_BASE	0x20000000
-
-#define CONFIG_POWER_TPS65090_EC
+#define CFG_SYS_SDRAM_BASE	0x20000000
 
 /* DRAM Memory Banks */
 #define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */

diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 2c749ac..09c6b4f 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h

@@ -20,7 +20,7 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
-#define CONFIG_SYS_SDRAM_BASE	0x20000000
+#define CFG_SYS_SDRAM_BASE	0x20000000
 
 /* DRAM Memory Banks */
 #define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */

diff --git a/include/configs/pg-wcom-expu1.h b/include/configs/pg-wcom-expu1.h
index e08d941..1b72739 100644
--- a/include/configs/pg-wcom-expu1.h
+++ b/include/configs/pg-wcom-expu1.h

@@ -13,23 +13,23 @@
 #define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
 
 /* CLIPS FPGA Definitions */
-#define CONFIG_SYS_CSPR3_EXT	(0x00)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
+#define CFG_SYS_CSPR3_EXT	(0x00)
+#define CFG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
 				CSPR_PORT_SIZE_8 | \
 				CSPR_MSEL_GPCM | \
 				CSPR_V)
-#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3	(CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3	(CSOR_GPCM_ADM_SHIFT(0x4) | \
 				CSOR_GPCM_TRHZ_40)
-#define CONFIG_SYS_CS3_FTIM0	(FTIM0_GPCM_TACSE(0x6) | \
+#define CFG_SYS_CS3_FTIM0	(FTIM0_GPCM_TACSE(0x6) | \
 				FTIM0_GPCM_TEADC(0x7) | \
 				FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS3_FTIM1	(FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS3_FTIM1	(FTIM1_GPCM_TACO(0x2) | \
 				FTIM1_GPCM_TRAD(0x12))
-#define CONFIG_SYS_CS3_FTIM2	(FTIM2_GPCM_TCS(0x3) | \
+#define CFG_SYS_CS3_FTIM2	(FTIM2_GPCM_TCS(0x3) | \
 				FTIM2_GPCM_TCH(0x1) | \
 				FTIM2_GPCM_TWP(0x12))
-#define CONFIG_SYS_CS3_FTIM3	0x04000000
+#define CFG_SYS_CS3_FTIM3	0x04000000
 
 /* PRST */
 #define WCOM_CLIPS_RST		0

diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h
index 9a7669c..e4bcae5 100644
--- a/include/configs/pg-wcom-seli8.h
+++ b/include/configs/pg-wcom-seli8.h

@@ -12,23 +12,23 @@
 #define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
 
 /* PAXK FPGA Definitions */
-#define CONFIG_SYS_CSPR3_EXT	(0x00)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
+#define CFG_SYS_CSPR3_EXT	(0x00)
+#define CFG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \
 				CSPR_PORT_SIZE_8 | \
 				CSPR_MSEL_GPCM | \
 				CSPR_V)
-#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3	(CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR3	(CSOR_GPCM_ADM_SHIFT(0x4) | \
 				CSOR_GPCM_TRHZ_40)
-#define CONFIG_SYS_CS3_FTIM0	(FTIM0_GPCM_TACSE(0x6) | \
+#define CFG_SYS_CS3_FTIM0	(FTIM0_GPCM_TACSE(0x6) | \
 				FTIM0_GPCM_TEADC(0x7) | \
 				FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS3_FTIM1	(FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS3_FTIM1	(FTIM1_GPCM_TACO(0x2) | \
 				FTIM1_GPCM_TRAD(0x12))
-#define CONFIG_SYS_CS3_FTIM2	(FTIM2_GPCM_TCS(0x3) | \
+#define CFG_SYS_CS3_FTIM2	(FTIM2_GPCM_TCS(0x3) | \
 				FTIM2_GPCM_TCH(0x1) | \
 				FTIM2_GPCM_TWP(0x12))
-#define CONFIG_SYS_CS3_FTIM3	0x04000000
+#define CFG_SYS_CS3_FTIM3	0x04000000
 
 /* PRST */
 #define KM_LIU_RST		0

diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
index f69d8ad..f922491 100644
--- a/include/configs/phycore_am335x_r2.h
+++ b/include/configs/phycore_am335x_r2.h

@@ -79,12 +79,10 @@
 #define V_OSCK				25000000  /* Clock output from T2 */
 #define V_SCLK				V_OSCK
 
-#define CONFIG_POWER_TPS65910
-
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -92,15 +90,9 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 #endif /* !CONFIG_MTD_RAW_NAND */
 
-/* CPU */
-
-#ifdef CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
-#endif
-
 #endif	/* ! __CONFIG_PHYCORE_AM335x_R2_H */

diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index c98393b..7f73117 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h

@@ -11,7 +11,7 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
 		(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
@@ -60,11 +60,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	SZ_512K
 
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE                 SZ_2G /* 2GB DDR */

diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 49cd9d4..11a833b 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h

@@ -10,7 +10,7 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-#define CONFIG_SYS_UBOOT_BASE \
+#define CFG_SYS_UBOOT_BASE \
 		(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
@@ -59,11 +59,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	SZ_512K
 
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000

diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 4ea16d6..3cc2a69 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h

@@ -18,12 +18,12 @@
  * Memory Layout
  */
 /* Initial RAM for temporary stack, global data */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
-#define CONFIG_SYS_INIT_RAM_ADDR	\
-	(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE)
+#define CFG_SYS_INIT_RAM_SIZE	0x10000
+#define CFG_SYS_INIT_RAM_ADDR	\
+	(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE)
 
 /* SDRAM Configuration (for final code, data, stack, heap) */
-#define CONFIG_SYS_SDRAM_BASE		0x88000000
+#define CFG_SYS_SDRAM_BASE		0x88000000
 
 /* Memory Test */
 

diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index 687133b..6d7873d 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h

@@ -10,14 +10,6 @@
 
 #include "mx6_common.h"
 
-#include "imx6_spl.h"
-
-#ifdef CONFIG_SPL_OS_BOOT
-/* Falcon Mode */
-
-/* Falcon Mode - MMC support: args@1MB kernel@2MB */
-#endif
-
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* MMC Configuration */
@@ -99,17 +91,13 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment organization */
 
 /* Ethernet Configuration */
 #define CONFIG_FEC_MXC_PHYADDR		1
 
-/* Framebuffer */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
 #endif			       /* __CONFIG_H * */

diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index d4f58b6..8af8883 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h

@@ -12,13 +12,6 @@
 #include <linux/sizes.h>
 #include "mx6_common.h"
 #include <asm/mach-imx/gpio.h>
-#include "imx6_spl.h"
-
-#ifdef CONFIG_SPL_OS_BOOT
-/* Falcon Mode */
-
-/* Falcon Mode - MMC support: args@1MB kernel@2MB */
-#endif
 
 /* Network support */
 
@@ -98,9 +91,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #ifdef CONFIG_VIDEO
 #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR

diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 159bf4c..83907b0 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h

@@ -10,14 +10,6 @@
 
 #include "mx7_common.h"
 
-#include "imx7_spl.h"
-
-#ifdef CONFIG_SPL_OS_BOOT
-/* Falcon Mode */
-
-/* Falcon Mode - MMC support: args@1MB kernel@2MB */
-#endif
-
 #define CONFIG_MXC_UART_BASE		UART5_IPS_BASE_ADDR
 
 /* MMC Config */
@@ -101,12 +93,11 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* PMIC */
-#define CONFIG_POWER_PFUZE3000
 #define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
 
 /* FLASH and environment organization */

diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h
index 17af19d..f9301a5 100644
--- a/include/configs/pico-imx8mq.h
+++ b/include/configs/pico-imx8mq.h

@@ -63,11 +63,11 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x80000
 
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0x80000000	/* 2 GiB DDR */
 

diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 09f0ed9..99db59c 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h

@@ -16,7 +16,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* NAND support */
 

diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 278f1b5..a233fb8 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h

@@ -22,47 +22,47 @@
 #define MASTER_PLL_DIV		15
 #define MASTER_PLL_MUL		162
 #define MAIN_PLL_DIV		2
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
+#define CFG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	18432000
 
 /* clocks */
 /* CKGR_MOR - enable main osc. */
-#define CONFIG_SYS_MOR_VAL						\
+#define CFG_SYS_MOR_VAL						\
 		(AT91_PMC_MOR_MOSCEN |					\
 		 (255 << 8))		/* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL						\
+#define CFG_SYS_PLLAR_VAL						\
 		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
 		 AT91_PMC_PLLXR_OUT(3) |						\
 		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
 
 /* PCK/2 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR1_VAL		\
+#define	CFG_SYS_MCKR1_VAL		\
 		(AT91_PMC_MCKR_CSS_SLOW |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
 		 AT91_PMC_MCKR_MDIV_2)
 
 /* PCK/2 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR2_VAL		\
+#define	CFG_SYS_MCKR2_VAL		\
 		(AT91_PMC_MCKR_CSS_PLLA |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
 		 AT91_PMC_MCKR_MDIV_2)
 
 /* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
+#define CFG_SYS_PIOC_PDR_VAL1	0xFFFF0000
 /* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOC_PPUDR_VAL	0xFFFF0000
+#define CFG_SYS_PIOC_PPUDR_VAL	0xFFFF0000
 
 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL		\
+#define CFG_SYS_MATRIX_EBICSA_VAL		\
 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
 /* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
+#define CFG_SYS_SDRC_TR_VAL1		0x13C
 /* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL							\
+#define CFG_SYS_SDRC_CR_VAL							\
 		(AT91_SDRAMC_NC_9 |						\
 		 AT91_SDRAMC_NR_13 |						\
 		 AT91_SDRAMC_NB_4 |						\
@@ -76,49 +76,49 @@
 		 (1 << 28))		/* Exit Self Refresh to Active Delay */
 
 /* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CFG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
 
 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+#define CFG_SYS_SMC0_SETUP0_VAL					\
 		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
 		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+#define CFG_SYS_SMC0_PULSE0_VAL					\
 		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
 		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+#define CFG_SYS_SMC0_CYCLE0_VAL	\
 		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL				\
+#define CFG_SYS_SMC0_MODE0_VAL				\
 		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
 		 AT91_SMC_MODE_DBW_16 |				\
 		 AT91_SMC_MODE_TDF |				\
 		 AT91_SMC_MODE_TDF_CYCLE(6))
 
 /* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL			\
+#define CFG_SYS_RSTC_RMR_VAL			\
 		(AT91_RSTC_KEY |		\
 		AT91_RSTC_CR_PROCRST |		\
 		AT91_RSTC_MR_ERSTL(1) |	\
 		AT91_RSTC_MR_ERSTL(2))
 
 /* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL				\
+#define CFG_SYS_WDTC_WDMR_VAL				\
 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
 		 AT91_WDT_MR_WDV(0xfff) |					\
 		 AT91_WDT_MR_WDDIS |				\
@@ -129,21 +129,20 @@
 #define PHYS_SDRAM_SIZE				0x04000000	/* 64 megs */
 
 /* NAND flash */
-#define CONFIG_SYS_NAND_BASE			0x40000000
-#define CONFIG_SYS_NAND_DBW_8			1
+#define CFG_SYS_NAND_BASE			0x40000000
 /* our ALE is AD22 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
-#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
+#define CFG_SYS_NAND_MASK_CLE		(1 << 21)
+#define CFG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
 
 /* NOR flash */
 #define PHYS_FLASH_1				0x10000000
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE			PHYS_FLASH_1
 
 /* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
+#define CFG_SYS_USB_OHCI_REGS_BASE		0x00500000
 
 #define CONFIG_EXTRA_ENV_SETTINGS				\
 	"partition=nand0,0\0"					\
@@ -161,6 +160,6 @@
 	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
 	""
 
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM
 
 #endif

diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 7c23206..9fd8979 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h

@@ -22,14 +22,14 @@
 #define MASTER_PLL_DIV		6
 #define MASTER_PLL_MUL		65
 #define MAIN_PLL_DIV		2	/* 2 or 4 */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	18432000
+#define CFG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 
 /* clocks */
-#define CONFIG_SYS_MOR_VAL						\
+#define CFG_SYS_MOR_VAL						\
 		(AT91_PMC_MOR_MOSCEN |					\
 		 (255 << 8))		/* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL						\
+#define CFG_SYS_PLLAR_VAL						\
 		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
 		 AT91_PMC_PLLXR_OUT(3) |				\
 		 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |	/* PLL Counter */\
@@ -38,43 +38,43 @@
 
 #if (MAIN_PLL_DIV == 2)
 /* PCK/2 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR1_VAL		\
+#define	CFG_SYS_MCKR1_VAL		\
 		(AT91_PMC_MCKR_CSS_SLOW |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
 		 AT91_PMC_MCKR_MDIV_2)
 /* PCK/2 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR2_VAL		\
+#define	CFG_SYS_MCKR2_VAL		\
 		(AT91_PMC_MCKR_CSS_PLLA |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
 		 AT91_PMC_MCKR_MDIV_2)
 #else
 /* PCK/4 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR1_VAL			\
+#define	CFG_SYS_MCKR1_VAL			\
 		(AT91_PMC_MCKR_CSS_SLOW |		\
 		 AT91_PMC_MCKR_PRES_1 |		\
 		 AT91_PMC_MCKR_MDIV_4)
 /* PCK/4 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR2_VAL			\
+#define	CFG_SYS_MCKR2_VAL			\
 		(AT91_PMC_MCKR_CSS_PLLA |		\
 		 AT91_PMC_MCKR_PRES_1 |		\
 		 AT91_PMC_MCKR_MDIV_4)
 #endif
 /* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+#define CFG_SYS_PIOD_PDR_VAL1	0xFFFF0000
 /* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+#define CFG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
+#define CFG_SYS_MATRIX_EBI0CSA_VAL					\
 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
 	 AT91_MATRIX_CSA_EBI_CS1A)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1		0
+#define CFG_SYS_SDRC_MR_VAL1		0
 /* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1		0x3AA
+#define CFG_SYS_SDRC_TR_VAL1		0x3AA
 /* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL							\
+#define CFG_SYS_SDRC_CR_VAL							\
 		(AT91_SDRAMC_NC_9 |						\
 		 AT91_SDRAMC_NR_13 |						\
 		 AT91_SDRAMC_NB_4 |						\
@@ -88,49 +88,49 @@
 		 (8 << 28))	/* tXSR - Exit Self Refresh to Active Delay */
 
 /* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CFG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CFG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
 
 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+#define CFG_SYS_SMC0_SETUP0_VAL					\
 		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
 		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+#define CFG_SYS_SMC0_PULSE0_VAL					\
 		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
 		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+#define CFG_SYS_SMC0_CYCLE0_VAL	\
 		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL				\
+#define CFG_SYS_SMC0_MODE0_VAL				\
 		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
 		 AT91_SMC_MODE_DBW_16 |				\
 		 AT91_SMC_MODE_TDF |				\
 		 AT91_SMC_MODE_TDF_CYCLE(6))
 
 /* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL			\
+#define CFG_SYS_RSTC_RMR_VAL			\
 		(AT91_RSTC_KEY |		\
 		AT91_RSTC_CR_PROCRST |		\
 		AT91_RSTC_MR_ERSTL(1) |	\
 		AT91_RSTC_MR_ERSTL(2))
 
 /* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL				\
+#define CFG_SYS_WDTC_WDMR_VAL				\
 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
 		 AT91_WDT_MR_WDV(0xfff) |					\
 		 AT91_WDT_MR_WDDIS |				\
@@ -142,18 +142,17 @@
 
 /* NOR flash, if populated */
 #define PHYS_FLASH_1			0x10000000
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8		1
+#define CFG_SYS_NAND_BASE		0x40000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CFG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
 
 #endif
 
@@ -167,7 +166,7 @@
 					 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
 
 /* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
 
 #define CONFIG_EXTRA_ENV_SETTINGS				\
 	"partition=nand0,0\0"					\
@@ -185,6 +184,6 @@
 	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
 	""
 
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM
 
 #endif

diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 35fd525..686411e 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h

@@ -16,23 +16,22 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK      32768
+#define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           0x70000000
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CFG_SYS_SDRAM_BASE           0x70000000
+#define CFG_SYS_SDRAM_SIZE		0x08000000
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		BIT(21)
+#define CFG_SYS_NAND_MASK_ALE		BIT(21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PD3
+#define CFG_SYS_NAND_MASK_CLE		BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PD3
 #endif
 
 #ifdef CONFIG_NAND_BOOT
@@ -45,18 +44,18 @@
 
 #ifdef CONFIG_SD_BOOT
 #elif CONFIG_NAND_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x80000
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 #endif
 
-#define CONFIG_SYS_MASTER_CLOCK		132096000
-#define CONFIG_SYS_AT91_PLLA		0x20c73f03
-#define CONFIG_SYS_MCKR			0x1301
-#define CONFIG_SYS_MCKR_CSS		0x1302
+#define CFG_SYS_MASTER_CLOCK		132096000
+#define CFG_SYS_AT91_PLLA		0x20c73f03
+#define CFG_SYS_MCKR			0x1301
+#define CFG_SYS_MCKR_CSS		0x1302
 
 #endif

diff --git a/include/configs/poleg.h b/include/configs/poleg.h
index 05253d5..518d7a3 100644
--- a/include/configs/poleg.h
+++ b/include/configs/poleg.h

@@ -7,11 +7,11 @@
 #define __CONFIG_POLEG_H
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE	0xF03FC000       /* L2 - Cache Regs Base (4k Space)*/
+#define CFG_SYS_PL310_BASE	0xF03FC000       /* L2 - Cache Regs Base (4k Space)*/
 #endif
 
-#define CONFIG_SYS_BOOTMAPSZ            (0x30 << 20)
-#define CONFIG_SYS_SDRAM_BASE           0x0
+#define CFG_SYS_BOOTMAPSZ            (0x30 << 20)
+#define CFG_SYS_SDRAM_BASE           0x0
 
 /* Default environemnt variables */
 #define CONFIG_SERVERIP                 192.168.0.1

diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h
index 2e20654..1c11685 100644
--- a/include/configs/pomelo.h
+++ b/include/configs/pomelo.h

@@ -9,7 +9,7 @@
 #define __POMELO_CONFIG_H__
 
 /* SDRAM Bank #1 start address */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* SIZE of malloc pool */
 

diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
index ebf5467..2b25c31 100644
--- a/include/configs/presidio_asic.h
+++ b/include/configs/presidio_asic.h

@@ -9,8 +9,8 @@
 #define __PRESIDIO_ASIC_H
 
 /* Generic Timer Definitions */
-#define CONFIG_SYS_TIMER_RATE		25000000
-#define CONFIG_SYS_TIMER_COUNTER	0xf4321008
+#define CFG_SYS_TIMER_RATE		25000000
+#define CFG_SYS_TIMER_COUNTER	0xf4321008
 
 /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
  * does not yet support DT. Thus define it here.
@@ -18,7 +18,7 @@
 #define GICD_BASE			0xf7011000
 #define GICC_BASE			0xf7012000
 
-#define CONFIG_SYS_TIMER_BASE		0xf4321000
+#define CFG_SYS_TIMER_BASE		0xf4321000
 
 /* Use external clock source */
 #define PRESIDIO_APB_CLK		125000000
@@ -26,17 +26,17 @@
 
 /* Cortina Serial Configuration */
 #define CORTINA_UART_CLOCK		(PRESIDIO_APB_CLK)
-#define CORTINA_SERIAL_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
-					 (void *)CONFIG_SYS_SERIAL1}
+#define CORTINA_SERIAL_PORTS		{(void *)CFG_SYS_SERIAL0, \
+					 (void *)CFG_SYS_SERIAL1}
 
-#define CONFIG_SYS_SERIAL0		PER_UART0_CFG
-#define CONFIG_SYS_SERIAL1		PER_UART1_CFG
+#define CFG_SYS_SERIAL0		PER_UART0_CFG
+#define CFG_SYS_SERIAL1		PER_UART1_CFG
 
 /* SDRAM Bank #1 */
 #define DDR_BASE			0x00000000
 #define PHYS_SDRAM_1			DDR_BASE
 #define PHYS_SDRAM_1_SIZE		0x80000000 /* 2GB */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 /* Console I/O Buffer Size */
 
@@ -58,8 +58,8 @@
 
 /* nand driver parameters */
 #ifdef CONFIG_TARGET_PRESIDIO_ASIC
-	#define CONFIG_SYS_NAND_BASE            CONFIG_SYS_FLASH_BASE
-	#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
+	#define CFG_SYS_NAND_BASE            CFG_SYS_FLASH_BASE
+	#define CFG_SYS_NAND_BASE_LIST       { CFG_SYS_NAND_BASE }
 #endif
 
 #endif /* __PRESIDIO_ASIC_H */

diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h
index 49d1878..9937615 100644
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h

@@ -8,15 +8,13 @@
 
 #include "rockchip-common.h"
 
-#define CONFIG_SYS_NS16550_MEM32
-
 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
 #define CONFIG_IRAM_BASE		0xff020000
 
 #define GICD_BASE			0xff131000
 #define GICC_BASE			0xff132000
 
-#define CONFIG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xff000000
 #define SDRAM_BANK_SIZE			(2UL << 30)
 

diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h
index 58020ae..c41bb34 100644
--- a/include/configs/qcs404-evb.h
+++ b/include/configs/qcs404-evb.h

@@ -11,7 +11,7 @@
 #include <linux/sizes.h>
 #include <asm/arch/sysmap-qcs404.h>
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
+#define CFG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootm_size=0x5000000\0"	\

diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h
index 535762e..a67af73 100644
--- a/include/configs/qemu-arm.h
+++ b/include/configs/qemu-arm.h

@@ -10,7 +10,7 @@
 
 /* Physical memory map */
 
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 /* GUIDs for capsule updatable firmware images */
 #define QEMU_ARM_UBOOT_IMAGE_GUID \

diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 9fc51fd..30a9eae 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h

@@ -12,42 +12,37 @@
 /* Needed to fill the ccsrbar pointer */
 
 /* Virtual address to CCSRBAR */
-#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CFG_SYS_CCSRBAR		0xe0000000
 /* Physical address should be a function call */
 #ifndef __ASSEMBLY__
 extern unsigned long long get_phys_ccsrbar_addr_early(void);
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
+#define CFG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
+#define CFG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
 #else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
 #endif
 
 /* Virtual address to a temporary map if we need it (max 128MB) */
-#define CONFIG_SYS_TMPVIRT		0xe8000000
+#define CFG_SYS_TMPVIRT		0xe8000000
 
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_HWCONFIG
-
-#define CONFIG_SYS_INIT_RAM_ADDR		0x00100000
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0x0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0x00100000
+#define CFG_SYS_INIT_RAM_ADDR		0x00100000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0x0
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0x00100000
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE		0x00004000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/* RTC */
-#define CONFIG_RTC_PT7C4338
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Miscellaneous configurable options
@@ -58,7 +53,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 
 /*
  * Environment Configuration

diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index d81e5d6..72f35cc 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h

@@ -8,7 +8,7 @@
 
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
 

diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index ac39e11..bad74cc 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h

@@ -6,21 +6,16 @@
 /* SCIF */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x8C000000
-#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+#define CFG_SYS_SDRAM_BASE		0x8C000000
+#define CFG_SYS_SDRAM_SIZE		0x04000000
 
 /* Address of u-boot image in Flash */
-#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CFG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /*
  * NOR Flash ( Spantion S29GL256P )
  */
-#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-/*
- * SuperH Clock setting
- */
-#define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */
+#define CFG_SYS_FLASH_BASE		(0xA0000000)
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE }
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 3a38e06..291c2a4 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h

@@ -10,20 +10,14 @@
 
 #include <asm/arch/rmobile.h>
 
-#ifndef CONFIG_PINCTRL_PFC
-#define CONFIG_SH_GPIO_PFC
-#endif
-
 /* console */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+#define CFG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
 
-#define CONFIG_SYS_SDRAM_BASE		(RCAR_GEN2_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE		(RCAR_GEN2_UBOOT_SDRAM_SIZE)
+#define CFG_SYS_SDRAM_BASE		(RCAR_GEN2_SDRAM_BASE)
+#define CFG_SYS_SDRAM_SIZE		(RCAR_GEN2_UBOOT_SDRAM_SIZE)
 
 /* Timer */
-#define CONFIG_TMU_TIMER
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE		(get_board_sys_clk() / 8)
+#define CFG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
+#define CFG_SYS_TIMER_RATE		(get_board_sys_clk() / 8)
 
 #endif	/* __RCAR_GEN2_COMMON_H */

diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 7432cff..e9cbd25 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h

@@ -18,7 +18,7 @@
 #define GICC_BASE	0xF1020000
 
 /* console */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 38400 }
+#define CFG_SYS_BAUDRATE_TABLE	{ 115200, 38400 }
 
 /* PHY needs a longer autoneg timeout */
 #define PHY_ANEG_TIMEOUT		20000
@@ -26,8 +26,8 @@
 /* MEMORY */
 
 #define DRAM_RSV_SIZE			0x08000000
-#define CONFIG_SYS_SDRAM_BASE		(0x40000000 + DRAM_RSV_SIZE)
-#define CONFIG_SYS_SDRAM_SIZE		(0x80000000u - DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_BASE		(0x40000000 + DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_SIZE		(0x80000000u - DRAM_RSV_SIZE)
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_MAX_MEM_MAPPED		(0x80000000u - DRAM_RSV_SIZE)
 

diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 6616396..a4cae69 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h

@@ -8,9 +8,9 @@
 #include <asm/arch-rockchip/hardware.h>
 #include "rockchip-common.h"
 
-#define CONFIG_SYS_HZ_CLOCK		24000000
+#define CFG_SYS_HZ_CLOCK		24000000
 
-#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CFG_SYS_SDRAM_BASE		0x60000000
 #define SDRAM_BANK_SIZE			(512UL << 20UL)
 #define SDRAM_MAX_SIZE                  (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
 

diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
index 9297184..99c86ed 100644
--- a/include/configs/rk3066_common.h
+++ b/include/configs/rk3066_common.h

@@ -11,7 +11,7 @@
 
 #define CONFIG_IRAM_BASE		0x10080000
 
-#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CFG_SYS_SDRAM_BASE		0x60000000
 #define SDRAM_BANK_SIZE			(1024UL << 20UL)
 #define SDRAM_MAX_SIZE			CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE
 

diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index 12d4bc6..3025466 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h

@@ -8,13 +8,13 @@
 
 #include "rockchip-common.h"
 
-#define CONFIG_SYS_HZ_CLOCK		24000000
+#define CFG_SYS_HZ_CLOCK		24000000
 
 #define CONFIG_IRAM_BASE		0x10080000
 
 /* RAW SD card / eMMC locations. */
 
-#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CFG_SYS_SDRAM_BASE		0x60000000
 #define SDRAM_MAX_SIZE			0x80000000
 
 /* usb mass storage */

diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 6fe1b2d..334fb3a 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h

@@ -13,7 +13,7 @@
 
 /* spl size 32kb sram - 2kb bootrom */
 
-#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CFG_SYS_SDRAM_BASE		0x60000000
 #define SDRAM_BANK_SIZE			(2UL << 30)
 #define SDRAM_MAX_SIZE			0x80000000
 

diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 4fb86b6..58ad62a 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h

@@ -8,11 +8,11 @@
 #include <asm/arch-rockchip/hardware.h>
 #include "rockchip-common.h"
 
-#define CONFIG_SYS_HZ_CLOCK		24000000
+#define CFG_SYS_HZ_CLOCK		24000000
 
 #define CONFIG_IRAM_BASE		0x10080000
 
-#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CFG_SYS_SDRAM_BASE		0x60000000
 #define SDRAM_BANK_SIZE			(512UL << 20UL)
 #define SDRAM_MAX_SIZE			0x80000000
 

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 81f16ed..6b55c57 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h

@@ -9,13 +9,13 @@
 #include <asm/arch-rockchip/hardware.h>
 #include "rockchip-common.h"
 
-#define CONFIG_SYS_HZ_CLOCK		24000000
+#define CFG_SYS_HZ_CLOCK		24000000
 
 #define CONFIG_IRAM_BASE		0xff700000
 
 /* RAW SD card / eMMC locations. */
 
-#define CONFIG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_BANK_SIZE			(2UL << 30)
 #define SDRAM_MAX_SIZE			0xfe000000
 

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 200b34b..4b510b1 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h

@@ -8,11 +8,9 @@
 
 #include "rockchip-common.h"
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_IRAM_BASE		0xfff80000
 
-#define CONFIG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xff000000
 #define SDRAM_BANK_SIZE			(2UL << 30)
 

diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 1e214e4..132b7d0 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h

@@ -11,7 +11,7 @@
 #define CONFIG_IRAM_BASE		0xff090000
 
 /* FAT sd card locations. */
-#define CONFIG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xff000000
 
 #define ENV_MEM_LAYOUT_SETTINGS \

diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 37e0c1d..92cdc1a 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h

@@ -11,7 +11,7 @@
 #include <asm/arch-rockchip/hardware.h>
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xff000000
 
 #define CONFIG_IRAM_BASE		0xff8c0000

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 2f9aee5..78f624d 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h

@@ -21,7 +21,7 @@
 /* RAW SD card / eMMC locations. */
 
 /* FAT sd card locations. */
-#define CONFIG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xf8000000
 
 #ifndef CONFIG_SPL_BUILD

diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
index 15e8152..d43dc25 100644
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h

@@ -10,7 +10,7 @@
 
 #define CONFIG_IRAM_BASE		0xfdcc0000
 
-#define CONFIG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xf0000000
 
 #define ENV_MEM_LAYOUT_SETTINGS		\

diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 4c964cc..1f6b82f 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h

@@ -7,8 +7,6 @@
 #define _ROCKCHIP_COMMON_H_
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_NS16550_MEM32
-
 /* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */
 
 #ifndef CONFIG_SPL_BUILD

diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index cd8fe8b..e354927 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h

@@ -17,21 +17,21 @@
 
 /* Use SoC timer for AArch32, but architected timer for AArch64 */
 #ifndef CONFIG_ARM64
-#define CONFIG_SYS_TIMER_RATE		1000000
-#define CONFIG_SYS_TIMER_COUNTER	\
+#define CFG_SYS_TIMER_RATE		1000000
+#define CFG_SYS_TIMER_COUNTER	\
 	(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
 #endif
 
 /* Memory layout */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
 /*
  * The board really has 256M. However, the VC (VideoCore co-processor) shares
  * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
  * smaller amount of RAM is present in order to avoid stomping on the area
  * the VC uses.
  */
-#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
+#define CFG_SYS_SDRAM_SIZE		SZ_128M
 
 /* Devices */
 /* LCD */

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 83c3167..84a5ae6 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h

@@ -10,12 +10,12 @@
 
 #define CONFIG_IRAM_BASE		0x10080000
 
-#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
+#define CFG_SYS_TIMER_RATE		(24 * 1000 * 1000)
 /* TIMER1,initialized by ddr initialize code */
-#define CONFIG_SYS_TIMER_BASE		0x10350020
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
+#define CFG_SYS_TIMER_BASE		0x10350020
+#define CFG_SYS_TIMER_COUNTER	(CFG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CFG_SYS_SDRAM_BASE		0x60000000
 
 /* rockchip ohci host driver */
 

diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h
index ae94f0e..e071d4d 100644
--- a/include/configs/s5p4418_nanopi2.h
+++ b/include/configs/s5p4418_nanopi2.h

@@ -18,7 +18,7 @@
 /*-----------------------------------------------------------------------
  *  System memory Configuration
  */
-#define CONFIG_SYS_SDRAM_BASE		0x71000000
+#define CFG_SYS_SDRAM_BASE		0x71000000
 
 /*
  * "(0x40000000 - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in
@@ -55,7 +55,7 @@
  *        Starting kernel ...
  *        ...
  */
-#define CONFIG_SYS_SDRAM_SIZE		(0xb0000000 - CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_SDRAM_SIZE		(0xb0000000 - CFG_SYS_SDRAM_BASE)
 
 #define BMP_LOAD_ADDR			0x78000000
 

diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index de4510a..fdade1e 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h

@@ -14,7 +14,7 @@
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 
 /* DRAM Base */
-#define CONFIG_SYS_SDRAM_BASE		0x30000000
+#define CFG_SYS_SDRAM_BASE		0x30000000
 
 /* Text Base */
 
@@ -61,8 +61,6 @@
 
 #define COMMON_BOOT	"${console} ${meminfo} ${mtdparts}"
 
-#define CONFIG_MISC_COMMON
-
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"updateb=" \
 		"onenand erase 0x0 0x100000;" \
@@ -114,7 +112,7 @@
 	"dfu_alt_info=" CONFIG_DFU_ALT "\0"
 
 /* Goni has 3 banks of DRAM, but swap the bank */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* OneDRAM Bank #0 */
+#define PHYS_SDRAM_1		CFG_SYS_SDRAM_BASE	/* OneDRAM Bank #0 */
 #define PHYS_SDRAM_1_SIZE	(80 << 20)		/* 80 MB in Bank #0 */
 #define PHYS_SDRAM_2		0x40000000		/* mDDR DMC1 Bank #1 */
 #define PHYS_SDRAM_2_SIZE	(256 << 20)		/* 256 MB in Bank #1 */
@@ -124,6 +122,6 @@
 /* FLASH and environment organization */
 #define CONFIG_MMC_DEFAULT_DEV	0
 
-#define CONFIG_SYS_ONENAND_BASE		0xB0000000
+#define CFG_SYS_ONENAND_BASE		0xB0000000
 
 #endif	/* __CONFIG_H */

diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 668b526..80d3fc9 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h

@@ -14,8 +14,8 @@
 /* Keep L2 Cache Disabled */
 
 /* Universal has 2 banks of DRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CFG_SYS_SDRAM_BASE
 
 #define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
@@ -87,7 +87,7 @@
 	"mmcrootpart=3\0" \
 	"opts=always_resume=1"
 
-#define CONFIG_SYS_ONENAND_BASE		0x0C000000
+#define CFG_SYS_ONENAND_BASE		0x0C000000
 
 #ifndef	__ASSEMBLY__
 void universal_spi_scl(int bit);
@@ -95,9 +95,6 @@
 int universal_spi_read(void);
 #endif
 
-/* Common misc for Samsung */
-#define CONFIG_MISC_COMMON
-
 /* Download menu - definitions for check keys */
 #ifndef __ASSEMBLY__
 

diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
index 41e5254..2e422cd 100644
--- a/include/configs/salvator-x.h
+++ b/include/configs/salvator-x.h

@@ -14,7 +14,7 @@
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
 
 #endif /* __SALVATOR_X_H */

diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h
index afb1e3d..f44ce90 100644
--- a/include/configs/sam9x60_curiosity.h
+++ b/include/configs/sam9x60_curiosity.h

@@ -10,14 +10,14 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK	24000000	/* 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768
+#define CFG_SYS_AT91_MAIN_CLOCK	24000000	/* 24 MHz crystal */
 
 #define CONFIG_USART_BASE   ATMEL_BASE_DBGU
 #define CONFIG_USART_ID     0 /* ignored in arm */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x8000000	/* 128 MB */
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x8000000	/* 128 MB */
 
 #endif

diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index 70c6ec5..27b39eb 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h

@@ -11,8 +11,8 @@
 #define __CONFIG_H__
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK	24000000	/* 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768
+#define CFG_SYS_AT91_MAIN_CLOCK	24000000	/* 24 MHz crystal */
 
 #define CONFIG_USART_BASE   ATMEL_BASE_DBGU
 #define CONFIG_USART_ID     0 /* ignored in arm */
@@ -23,16 +23,16 @@
  */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 megs */
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x10000000	/* 256 megs */
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
-#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+#define CFG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_MASK_ALE	BIT(21)
+#define CFG_SYS_NAND_MASK_CLE	BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PD5
 #endif
 
 #endif

diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h
index 79f354d..d62146e 100644
--- a/include/configs/sama5d27_som1_ek.h
+++ b/include/configs/sama5d27_som1_ek.h

@@ -11,8 +11,8 @@
 
 #include "at91-sama5_common.h"
 
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
 
 /* SPL */
 

diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h
index de6c92e..1979cb3 100644
--- a/include/configs/sama5d27_wlsom1_ek.h
+++ b/include/configs/sama5d27_wlsom1_ek.h

@@ -12,12 +12,12 @@
 
 #include "at91-sama5_common.h"
 
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x10000000
 
 /* SPL */
 

diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h
index ebdb392..a072b21 100644
--- a/include/configs/sama5d2_icp.h
+++ b/include/configs/sama5d2_icp.h

@@ -11,12 +11,12 @@
 
 #include "at91-sama5_common.h"
 
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x20000000
 
 #ifdef CONFIG_SD_BOOT
 /* u-boot env in sd/mmc card */

diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h
index 9281c7c..bf3c92b 100644
--- a/include/configs/sama5d2_ptc_ek.h
+++ b/include/configs/sama5d2_ptc_ek.h

@@ -12,20 +12,20 @@
 
 #include "at91-sama5_common.h"
 
-#undef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
+#undef CFG_SYS_AT91_MAIN_CLOCK
+#define CFG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x20000000
 
 /* NAND Flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
+#define CFG_SYS_NAND_MASK_ALE	BIT(21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
+#define CFG_SYS_NAND_MASK_CLE	BIT(22)
 #endif
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index eed688d..4b13a10 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h

@@ -24,16 +24,16 @@
 #define ATMEL_PMC_UHP			(1 <<  6)
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+#define CFG_SYS_SDRAM_BASE           0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x10000000
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x60000000
+#define CFG_SYS_NAND_BASE		0x60000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
 #endif
 
 /* SPL */

diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index b05fa59..4f579ad 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h

@@ -27,22 +27,22 @@
 
 /* NOR flash */
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CFG_SYS_FLASH_BASE		0x10000000
 #endif
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CFG_SYS_SDRAM_BASE           0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x20000000
 
 /* SerialFlash */
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x60000000
+#define CFG_SYS_NAND_BASE		0x60000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
 #endif
 
 /* SPL */

diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index c4552c2..084cb4d 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h

@@ -12,16 +12,16 @@
 #include "at91-sama5_common.h"
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CFG_SYS_SDRAM_BASE           0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x20000000
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x80000000
+#define CFG_SYS_NAND_BASE		0x80000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
 #endif
 
 /* SPL */

diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index d719992..cbc1c0f 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h

@@ -12,16 +12,16 @@
 #include "at91-sama5_common.h"
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CFG_SYS_SDRAM_BASE           0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x20000000
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		0x80000000
+#define CFG_SYS_NAND_BASE		0x80000000
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
 #endif
 
 /* SPL */

diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h
index 3f905bf..59f13ed 100644
--- a/include/configs/sama7g5ek.h
+++ b/include/configs/sama7g5ek.h

@@ -9,10 +9,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK      32768
+#define CFG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x60000000
-#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CFG_SYS_SDRAM_BASE		0x60000000
+#define CFG_SYS_SDRAM_SIZE		0x20000000
 
 #endif

diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 0dcb2eb..8d9af7f 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h

@@ -6,22 +6,16 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_IO_TRACE
-
 #define CONFIG_MALLOC_F_ADDR		0x0010000
 
 /* Size of our emulated memory */
 #define SB_CONCAT(x, y) x ## y
 #define SB_TO_UL(s) SB_CONCAT(s, UL)
-#define CONFIG_SYS_SDRAM_BASE		0
-#define CONFIG_SYS_SDRAM_SIZE \
+#define CFG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_SIZE \
 		(SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+#define CFG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 
-#ifndef SANDBOX_NO_SDL
-#define CONFIG_SANDBOX_SDL
-#endif
-
 #endif

diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h
index af5fe27..f7cdd5a 100644
--- a/include/configs/sdm845.h
+++ b/include/configs/sdm845.h

@@ -11,7 +11,7 @@
 #include <linux/sizes.h>
 #include <asm/arch/sysmap-sdm845.h>
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
+#define CFG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootm_size=0x4000000\0"	\

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index c7f03a1..f272fe9 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h

@@ -9,12 +9,6 @@
 
 #include <linux/sizes.h>
 
-/* LP0 suspend / resume */
-#define CONFIG_TEGRA_LP0
-#define CONFIG_TEGRA_PMU
-#define CONFIG_TPS6586X_POWER
-#define CONFIG_TEGRA_CLOCK_SCALING
-
 #include "tegra20-common.h"
 
 /* High-level configuration options */
@@ -22,7 +16,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 

diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 87da5e4..5a00171 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h

@@ -33,22 +33,21 @@
  /* Physical Memory Map */
 #define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_DRAM_1
  /* Platform/Board specific defs */
-#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		(48000000)
-#define CONFIG_SYS_NS16550_COM1		0x44e09000
-#define CONFIG_SYS_NS16550_COM4		0x481a6000
+#define CFG_SYS_NS16550_CLK		(48000000)
+#define CFG_SYS_NS16550_COM1		0x44e09000
+#define CFG_SYS_NS16550_COM4		0x481a6000
 
 
 /* I2C Configuration */
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -56,14 +55,10 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
-#define CONFIG_SYS_NAND_ECCSTEPS	4
-#define	CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
-						CONFIG_SYS_NAND_ECCSTEPS)
-
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 
 /*
  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
@@ -365,7 +360,7 @@
 
  */
 
-#define CONFIG_SYS_NAND_BASE		(0x08000000)	/* physical address */
+#define CFG_SYS_NAND_BASE		(0x08000000)	/* physical address */
 							/* to access nand at */
 							/* CS0 */
 #endif

diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index 2e5592c..5ad2124 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h

@@ -11,7 +11,7 @@
 
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
 

diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 85fab92..f4b1a16 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h

@@ -11,7 +11,7 @@
 
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
 

diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
index 7159fc3..974531e 100644
--- a/include/configs/sipeed-maix.h
+++ b/include/configs/sipeed-maix.h

@@ -8,8 +8,8 @@
 
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_SIZE SZ_8M
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_SIZE SZ_8M
 
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \

diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index a77215d..b988b96 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h

@@ -36,8 +36,8 @@
  */
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432MHz crystal */
 
 /* misc settings */
 
@@ -45,8 +45,8 @@
  * SDRAM: 1 bank, 64 MB, base address 0x20000000
  * Already initialized before u-boot gets started.
  */
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE		(64 * SZ_1M)
+#define CFG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE		(64 * SZ_1M)
 
 /*
  * Perform a SDRAM Memtest from the start of SDRAM
@@ -54,21 +54,16 @@
  */
 
 /* NAND flash settings */
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PC13
 
 /* serial console */
 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
 #define CONFIG_USART_ID			ATMEL_ID_SYS
 
-/* USB DFU support */
-
-#define CONFIG_USB_GADGET_AT91
-
 /* DFU class support */
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
@@ -88,28 +83,26 @@
  * leaving the correct space for initial global data structure above that
  * address while providing maximum stack area below.
  */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE	0x1000
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_NAND_ENABLE_PIN_SPL	(2*32 + 14)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
-#define CONFIG_SYS_NAND_SIZE		(SZ_256M)
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 
-#define CONFIG_SYS_MASTER_CLOCK		(198656000/2)
+#define CFG_SYS_MASTER_CLOCK		(198656000/2)
 #define AT91_PLL_LOCK_TIMEOUT		1000000
-#define CONFIG_SYS_AT91_PLLA		0x2060bf09
-#define CONFIG_SYS_MCKR			0x100
-#define CONFIG_SYS_MCKR_CSS		(0x02 | CONFIG_SYS_MCKR)
-#define CONFIG_SYS_AT91_PLLB		0x10483f0e
+#define CFG_SYS_AT91_PLLA		0x2060bf09
+#define CFG_SYS_MCKR			0x100
+#define CFG_SYS_MCKR_CSS		(0x02 | CFG_SYS_MCKR)
+#define CFG_SYS_AT91_PLLB		0x10483f0e
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 12c2e1f..0392530 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h

@@ -14,7 +14,7 @@
 
 #define CONFIG_SMDK5420			/* which is in a SMDK5420 */
 
-#define CONFIG_SYS_SDRAM_BASE	0x20000000
+#define CFG_SYS_SDRAM_BASE	0x20000000
 
 /* DRAM Memory Banks */
 #define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */

diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index ba562b2..ffa1a1f 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h

@@ -16,7 +16,7 @@
 /* input clock of PLL: SMDKC100 has 12MHz input clock */
 
 /* DRAM Base */
-#define CONFIG_SYS_SDRAM_BASE		0x30000000
+#define CFG_SYS_SDRAM_BASE		0x30000000
 
 /* Text Base */
 
@@ -77,7 +77,7 @@
  */
 
 /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1		CFG_SYS_SDRAM_BASE	/* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	(128 << 20)	/* 0x8000000, 128 MB Bank #1 */
 
 /*-----------------------------------------------------------------------
@@ -88,7 +88,7 @@
  * Boot configuration
  */
 
-#define CONFIG_SYS_ONENAND_BASE		0xE7100000
+#define CFG_SYS_ONENAND_BASE		0xE7100000
 
 /*
  * Ethernet Contoller driver

diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 0b1f0c5..af0c820 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h

@@ -11,7 +11,7 @@
 #include "exynos4-common.h"
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 
 /* Handling Sleep Mode*/
 #define S5P_CHECK_SLEEP			0x00000BAD
@@ -23,13 +23,13 @@
 
 /* SMDKV310 has 4 bank of DRAM */
 #define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1		CFG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2		(CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3		(CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4		(CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
 
 /* FLASH and environment organization */

diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index faa13c6..14f9cf5 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h

@@ -38,8 +38,8 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #endif

diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index c56fb37..b7aa49c 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h

@@ -15,27 +15,25 @@
 #include <linux/sizes.h>
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768
 
 /* CPU */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS6
-#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024) /* 64MB */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM
+#define CFG_SYS_SDRAM_BASE		ATMEL_BASE_CS6
+#define CFG_SYS_SDRAM_SIZE		(128 * 1024 * 1024) /* 64MB */
+#define CFG_SYS_INIT_RAM_SIZE	0x1000
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM
 
 /* Mem test settings */
 
 /* NAND Flash */
-#define CONFIG_SYS_NAND_ECC_BASE	ATMEL_BASE_ECC
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC8
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PC8
 
 /* UARTs/Serial console */
 

diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 0187fca..afca7e1 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h

@@ -15,7 +15,7 @@
  * Clocks
  */
 
-#define CONFIG_SYS_TIMERBASE	OMAP34XX_GPT2
+#define CFG_SYS_TIMERBASE	OMAP34XX_GPT2
 
 #define V_NS16550_CLK		48000000
 #define V_OSCK			26000000
@@ -32,7 +32,7 @@
  * Memory
  */
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /*
  * I2C
@@ -52,15 +52,10 @@
  * Serial
  */
 
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#endif
-
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CFG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CFG_SYS_NS16550_COM3		OMAP34XX_UART3
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, \
+#define CFG_SYS_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, \
 					  115200 }
 
 /*

diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
index f712928..35c777b 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h

@@ -18,8 +18,7 @@
 /*
  * Serial / UART configurations
  */
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
 
 /*
  * L4 OSC1 Timer 0

diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h
index 261ae56..29b4b22 100644
--- a/include/configs/socfpga_arria5_secu1.h
+++ b/include/configs/socfpga_arria5_secu1.h

@@ -10,7 +10,7 @@
 #include <linux/stringify.h>
 
 /* Eternal oscillator */
-#define CONFIG_SYS_TIMER_RATE	40000000
+#define CFG_SYS_TIMER_RATE	40000000
 
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512MiB on SECU1 */
@@ -21,7 +21,7 @@
  * the last two bytes of the 128 bytes large NVRAM in the
  * RTC which begin at address 0x20
  */
-#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CFG_SYS_I2C_RTC_ADDR         0x68
 
 /* Environment settings */
 

diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h
index 75d2081..aa13878 100644
--- a/include/configs/socfpga_chameleonv3.h
+++ b/include/configs/socfpga_chameleonv3.h

@@ -17,8 +17,7 @@
 /*
  * Serial / UART configurations
  */
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"autoload=no\0" \

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 704a714..bbbdea6 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h

@@ -12,12 +12,12 @@
  */
 #define PHYS_SDRAM_1			0x0
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE	SOCFPGA_PHYS_OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE	SOCFPGA_PHYS_OCRAM_SIZE
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
+#define CFG_SYS_INIT_RAM_ADDR	0xFFE00000
 /* SPL memory allocation configuration, this is for FAT implementation */
-#define CONFIG_SYS_INIT_RAM_SIZE	(SOCFPGA_PHYS_OCRAM_SIZE - \
+#define CFG_SYS_INIT_RAM_SIZE	(SOCFPGA_PHYS_OCRAM_SIZE - \
 					 CONFIG_SYS_SPL_MALLOC_SIZE)
 #endif
 
@@ -27,9 +27,9 @@
  * at this address to not overwrite the bootcounter by checking, if the
  * bootcounter address is located in the internal SRAM.
  */
-#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) &&	\
-     (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR +	\
-				   CONFIG_SYS_INIT_RAM_SIZE)))
+#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) &&	\
+     (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR +	\
+				   CFG_SYS_INIT_RAM_SIZE)))
 #endif
 
 /*
@@ -38,7 +38,7 @@
  * in U-Boot pre-reloc is higher than in SPL.
  */
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 /*
  * U-Boot general configurations
@@ -48,17 +48,16 @@
 /*
  * Cache
  */
-#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
+#define CFG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 
 /*
  * L4 OSC1 Timer 0
  */
 #ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
-#ifndef CONFIG_SYS_TIMER_RATE
-#define CONFIG_SYS_TIMER_RATE		25000000
+#define CFG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+#define CFG_SYS_TIMER_COUNTER	(CFG_SYS_TIMERBASE + 0x4)
+#ifndef CFG_SYS_TIMER_RATE
+#define CFG_SYS_TIMER_RATE		25000000
 #endif
 #endif
 
@@ -71,8 +70,8 @@
  * NAND Support
  */
 #ifdef CONFIG_NAND_DENALI
-#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
-#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
+#define CFG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
+#define CFG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
 #endif
 
 /*

diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 86cc377..47089f3 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h

@@ -26,8 +26,8 @@
 /*
  * U-Boot run time memory configurations
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x40000
+#define CFG_SYS_INIT_RAM_ADDR	0xFFE00000
+#define CFG_SYS_INIT_RAM_SIZE	0x40000
 
 /*
  * U-Boot environment configurations
@@ -70,13 +70,12 @@
  */
 #define PHYS_SDRAM_1			0x0
 #define PHYS_SDRAM_1_SIZE		(1 * 1024 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE		0
+#define CFG_SYS_SDRAM_BASE		0
 
 /*
  * Serial / UART configurations
  */
-#define CONFIG_SYS_NS16550_CLK		100000000
-#define CONFIG_SYS_NS16550_MEM32
+#define CFG_SYS_NS16550_CLK		100000000
 
 /*
  * SDMMC configurations

diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 3c978f5..95393d3 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h

@@ -42,20 +42,19 @@
  */
 #define CONFIG_L2_CACHE			/* toggle L2 cache		*/
 
-#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
+#define CFG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
 
-#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time	*/
+#undef	CFG_SYS_DRAM_TEST			/* memory test, takes time	*/
 
-#define CONFIG_SYS_CCSRBAR		0xE0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR		0xE0000000
+#define CFG_SYS_CCSRBAR_PHYS_LOW	CFG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 /* I2C addresses of SPD EEPROMs */
@@ -63,58 +62,54 @@
 
 
 /* Hardcoded values, to use instead of SPD */
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG		0x80010102
-#define CONFIG_SYS_DDR_TIMING_0		0x00260802
-#define CONFIG_SYS_DDR_TIMING_1		0x3935D322
-#define CONFIG_SYS_DDR_TIMING_2		0x14904CC8
-#define CONFIG_SYS_DDR_MODE			0x00480432
-#define CONFIG_SYS_DDR_INTERVAL		0x030C0100
-#define CONFIG_SYS_DDR_CONFIG_2		0x04400000
-#define CONFIG_SYS_DDR_CONFIG			0xC3008000
-#define CONFIG_SYS_DDR_CLK_CONTROL		0x03800000
-#define CONFIG_SYS_SDRAM_SIZE			256 /* in Megs */
+#define CFG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CFG_SYS_DDR_CS0_CONFIG		0x80010102
+#define CFG_SYS_DDR_TIMING_0		0x00260802
+#define CFG_SYS_DDR_TIMING_1		0x3935D322
+#define CFG_SYS_DDR_TIMING_2		0x14904CC8
+#define CFG_SYS_DDR_MODE			0x00480432
+#define CFG_SYS_DDR_INTERVAL		0x030C0100
+#define CFG_SYS_DDR_CONFIG_2		0x04400000
+#define CFG_SYS_DDR_CONFIG			0xC3008000
+#define CFG_SYS_DDR_CLK_CONTROL		0x03800000
+#define CFG_SYS_SDRAM_SIZE			256 /* in Megs */
 
 /*
  * Flash on the LocalBus
  */
-#define CONFIG_SYS_FLASH0		0xFE000000
-#define CONFIG_SYS_FLASH1		0xFC000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
+#define CFG_SYS_FLASH0		0xFE000000
+#define CFG_SYS_FLASH1		0xFC000000
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH1, CFG_SYS_FLASH0 }
 
-#define CONFIG_SYS_LBC_FLASH_BASE	CONFIG_SYS_FLASH1	/* Localbus flash start	*/
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH	*/
+#define CFG_SYS_LBC_FLASH_BASE	CFG_SYS_FLASH1	/* Localbus flash start	*/
+#define CFG_SYS_FLASH_BASE		CFG_SYS_LBC_FLASH_BASE /* start of FLASH	*/
 
-#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
-#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg		*/
-#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
-#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
+#define CFG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
+#define CFG_SYS_LBC_LBCR		0x00000000    /* LB config reg		*/
+#define CFG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
+#define CFG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size used area in RAM*/
+#define CFG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
+#define CFG_SYS_INIT_RAM_SIZE	0x4000		/* Size used area in RAM*/
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* FPGA and NAND */
-#define CONFIG_SYS_FPGA_BASE		0xc0000000
-#define CONFIG_SYS_FPGA_SIZE		0x00100000	/* 1 MB		*/
+#define CFG_SYS_FPGA_BASE		0xc0000000
+#define CFG_SYS_FPGA_SIZE		0x00100000	/* 1 MB		*/
 
-#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_FPGA_BASE + 0x70)
+#define CFG_SYS_NAND_BASE		(CFG_SYS_FPGA_BASE + 0x70)
 
 /* LIME GDC */
-#define CONFIG_SYS_LIME_BASE		0xc8000000
+#define CFG_SYS_LIME_BASE		0xc8000000
 
 /*
  * General PCI
  * Memory space is mapped 1-1.
  */
 
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
-#define CONFIG_SYS_PCI1_IO_BASE	0xE2000000
-#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
-#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M			*/
+#define CFG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CFG_SYS_PCI1_IO_PHYS	0xE2000000
 
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"TSEC0"
@@ -141,7 +136,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
+#define CFG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
 
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\

diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h
index 49672df..de0f48b 100644
--- a/include/configs/somlabs_visionsom_6ull.h
+++ b/include/configs/somlabs_visionsom_6ull.h

@@ -13,10 +13,6 @@
 #include "mx6_common.h"
 #include <asm/mach-imx/gpio.h>
 
-/* SPL options */
-#include "imx6_spl.h"
-
-
 /* MMC Configs */
 #ifdef CONFIG_FSL_USDHC
 #define CFG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
@@ -57,9 +53,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* environment organization */
 

diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h
index 3c70856..a5987c5 100644
--- a/include/configs/stemmy.h
+++ b/include/configs/stemmy.h

@@ -15,7 +15,7 @@
  */
 
 /* FIXME: This should be loaded from device tree... */
-#define CONFIG_SYS_PL310_BASE		0xa0412000
+#define CFG_SYS_PL310_BASE		0xa0412000
 
 /* Linux does not boot if FDT / initrd is loaded to end of RAM */
 #define BOOT_ENV \

diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h
index 1e966a2..9294d57 100644
--- a/include/configs/stih410-b2260.h
+++ b/include/configs/stih410-b2260.h

@@ -11,10 +11,10 @@
 
 /* ram memory-related information */
 #define PHYS_SDRAM_1			0x40000000
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define PHYS_SDRAM_1_SIZE		0x3E000000
 
-#define CONFIG_SYS_HZ_CLOCK		750000000	/* 750 MHz */
+#define CFG_SYS_HZ_CLOCK		750000000	/* 750 MHz */
 
 /* Environment */
 
@@ -22,7 +22,7 @@
  * For booting Linux, use the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		SZ_256M
+#define CFG_SYS_BOOTMAPSZ		SZ_256M
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \

diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 51f6901..afd7d50 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h

@@ -7,13 +7,13 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CFG_SYS_FLASH_BASE		0x08000000
 
 /*
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \

diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h
index 221b7ab..c8aad47 100644
--- a/include/configs/stm32f429-evaluation.h
+++ b/include/configs/stm32f429-evaluation.h

@@ -10,15 +10,15 @@
 #include <linux/sizes.h>
 
 /* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ		SZ_16M
+#define CFG_SYS_BOOTMAPSZ		SZ_16M
 
-#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CFG_SYS_FLASH_BASE		0x08000000
 
 /*
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0)

diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h
index 55e70ce..573a6b1 100644
--- a/include/configs/stm32f469-discovery.h
+++ b/include/configs/stm32f469-discovery.h

@@ -10,15 +10,15 @@
 #include <linux/sizes.h>
 
 /* For booting Linux, use the first 12MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ		SZ_8M + SZ_4M
+#define CFG_SYS_BOOTMAPSZ		SZ_8M + SZ_4M
 
-#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CFG_SYS_FLASH_BASE		0x08000000
 
 /*
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0)

diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index c7d6d93..14e883a 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h

@@ -10,15 +10,15 @@
 #include <linux/sizes.h>
 
 /* For booting Linux, use the first 6MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ		SZ_4M + SZ_2M
+#define CFG_SYS_BOOTMAPSZ		SZ_4M + SZ_2M
 
-#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CFG_SYS_FLASH_BASE		0x08000000
 
 /*
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+#define CFG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0)
@@ -33,7 +33,7 @@
 			"ramdisk_addr_r=0xC0438000\0"		\
 			BOOTENV
 
-#define CONFIG_SYS_UBOOT_BASE		(CONFIG_SYS_FLASH_BASE + \
+#define CFG_SYS_UBOOT_BASE		(CFG_SYS_FLASH_BASE + \
 					 CONFIG_SPL_PAD_TO)
 
 /* For splashcreen */

diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h
index f959fcf..67e6a3a 100644
--- a/include/configs/stm32h743-disco.h
+++ b/include/configs/stm32h743-disco.h

@@ -11,11 +11,11 @@
 #include <linux/sizes.h>
 
 /* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ		SZ_16M
+#define CFG_SYS_BOOTMAPSZ		SZ_16M
 
-#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CFG_SYS_FLASH_BASE		0x08000000
 
-#define CONFIG_SYS_HZ_CLOCK		1000000
+#define CFG_SYS_HZ_CLOCK		1000000
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0)

diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h
index c8688e9..4786eb0 100644
--- a/include/configs/stm32h743-eval.h
+++ b/include/configs/stm32h743-eval.h

@@ -11,11 +11,11 @@
 #include <linux/sizes.h>
 
 /* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ		SZ_16M
+#define CFG_SYS_BOOTMAPSZ		SZ_16M
 
-#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CFG_SYS_FLASH_BASE		0x08000000
 
-#define CONFIG_SYS_HZ_CLOCK		1000000
+#define CFG_SYS_HZ_CLOCK		1000000
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0)

diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h
index f7fa8c5..e667fe6 100644
--- a/include/configs/stm32h750-art-pi.h
+++ b/include/configs/stm32h750-art-pi.h

@@ -11,11 +11,11 @@
 #include <linux/sizes.h>
 
 /* For booting Linux, use the first 16MB of memory */
-#define CONFIG_SYS_BOOTMAPSZ		(SZ_16M + SZ_8M)
+#define CFG_SYS_BOOTMAPSZ		(SZ_16M + SZ_8M)
 
-#define CONFIG_SYS_FLASH_BASE		0x90000000
+#define CFG_SYS_FLASH_BASE		0x90000000
 
-#define CONFIG_SYS_HZ_CLOCK		1000000
+#define CFG_SYS_HZ_CLOCK		1000000
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0)

diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h
index 07a5bfc..c259a61 100644
--- a/include/configs/stm32mp13_common.h
+++ b/include/configs/stm32mp13_common.h

@@ -13,13 +13,13 @@
 /*
  * Configuration of the external SRAM memory used by U-Boot
  */
-#define CONFIG_SYS_SDRAM_BASE		STM32_DDR_BASE
+#define CFG_SYS_SDRAM_BASE		STM32_DDR_BASE
 
 /*
  * For booting Linux, use the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		SZ_256M
+#define CFG_SYS_BOOTMAPSZ		SZ_256M
 
 /* NAND support */
 

diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h
index c51022b..ad8126f 100644
--- a/include/configs/stm32mp13_st_common.h
+++ b/include/configs/stm32mp13_st_common.h

@@ -15,7 +15,7 @@
 #include <configs/stm32mp13_common.h>
 
 /* uart with on-board st-link */
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, \
 					 230400, 460800, 921600, \
 					 1000000, 2000000, 4000000}
 

diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h
index b809f93..c9cfadd 100644
--- a/include/configs/stm32mp15_common.h
+++ b/include/configs/stm32mp15_common.h

@@ -13,13 +13,13 @@
 /*
  * Configuration of the external SRAM memory used by U-Boot
  */
-#define CONFIG_SYS_SDRAM_BASE			STM32_DDR_BASE
+#define CFG_SYS_SDRAM_BASE			STM32_DDR_BASE
 
 /*
  * For booting Linux, use the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		SZ_256M
+#define CFG_SYS_BOOTMAPSZ		SZ_256M
 
 /* NAND support */
 

diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h
index 6bdc286..38b5aa7 100644
--- a/include/configs/stm32mp15_st_common.h
+++ b/include/configs/stm32mp15_st_common.h

@@ -14,7 +14,7 @@
 #include <configs/stm32mp15_common.h>
 
 /* uart with on-board st-link */
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, \
+#define CFG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, \
 					 230400, 460800, 921600, \
 					 1000000, 2000000 }
 

diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index ba49075..faff8d6 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h

@@ -10,7 +10,7 @@
 
 #define CONFIG_HOSTNAME			"stmark2"
 
-#define CONFIG_SYS_UART_PORT		0
+#define CFG_SYS_UART_PORT		0
 
 #define LDS_BOARD_TEXT						\
 	board/sysam/stmark2/sbf_dram_init.o (.text*)
@@ -34,34 +34,34 @@
 		"sf write ${loadaddr} 0x00800000 ${filesize}\0"	\
 	""
 
-#define CONFIG_SYS_SBFHDR_SIZE		0x7
+#define CFG_SYS_SBFHDR_SIZE		0x7
 
 /* Input, PCI, Flexbus, and VCO */
 
 #define CONFIG_PRAM			2048	/* 2048 KB */
 
-#define CONFIG_SYS_MBAR			0xFC000000
+#define CFG_SYS_MBAR			0xFC000000
 
 /*
  * Definitions for initial stack pointer and data area (in internal SRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CFG_SYS_INIT_RAM_ADDR	0x80000000
 /* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
-#define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_INIT_SP_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - \
+#define CFG_SYS_INIT_RAM_SIZE	0x10000
+#define CFG_SYS_INIT_RAM_CTRL	0x221
+#define CFG_SYS_INIT_SP_OFFSET	((CFG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+#define CFG_SYS_SBFHDR_DATA_OFFSET	(CFG_SYS_INIT_RAM_SIZE - 32)
 
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
 
-#define CONFIG_SYS_DRAM_TEST
+#define CFG_SYS_DRAM_TEST
 
 #if defined(CONFIG_CF_SBF)
 #define CONFIG_SERIAL_BOOT
@@ -75,30 +75,30 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + \
-					(CONFIG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + \
+					(CFG_SYS_SDRAM_SIZE << 20))
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
  */
 
 /* Cache Configuration */
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CFG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CFG_SYS_CACHE_ACR2		(CFG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
 					 CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+#define CFG_SYS_CACHE_DCACR		((CFG_SYS_CACHE_ICACR | \
 					 CF_CACR_DEC | CF_CACR_DDCM_P | \
 					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 
-#define CACR_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					CONFIG_SYS_INIT_RAM_SIZE - 12)
+#define CACR_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					CFG_SYS_INIT_RAM_SIZE - 12)
 
 #endif /* __STMARK2_CONFIG_H */

diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 567aa1f..7eadb6d 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h

@@ -6,18 +6,18 @@
 
 #ifndef __CONFIG_STV0991_H
 #define __CONFIG_STV0991_H
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CFG_SYS_EXCEPTION_VECTORS_HIGH
 
 /* ram memory-related information */
 #define PHYS_SDRAM_1				0x00000000
-#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE			PHYS_SDRAM_1
 #define PHYS_SDRAM_1_SIZE			0x00198000
 
 /* user interface */
 
 /* MISC */
-#define CONFIG_SYS_INIT_RAM_SIZE		0x8000
-#define CONFIG_SYS_INIT_RAM_ADDR		0x00190000
+#define CFG_SYS_INIT_RAM_SIZE		0x8000
+#define CFG_SYS_INIT_RAM_ADDR		0x00190000
 /* U-Boot Load Address */
 
 /* Misc configuration */

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 7207686..1677aaf 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h

@@ -16,21 +16,19 @@
 #include <linux/stringify.h>
 
 /* Serial & console */
-#define CONFIG_SYS_NS16550_SERIAL
 /* ns16550 reg in the low bits of cpu reg */
 #ifdef CONFIG_MACH_SUNIV
 /* suniv doesn't have apb2 and uart is connected to apb1 */
-#define CONFIG_SYS_NS16550_CLK		100000000
+#define CFG_SYS_NS16550_CLK		100000000
 #else
-#define CONFIG_SYS_NS16550_CLK		24000000
+#define CFG_SYS_NS16550_CLK		24000000
 #endif
 #ifndef CONFIG_DM_SERIAL
-# define CONFIG_SYS_NS16550_REG_SIZE	-4
-# define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
-# define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
-# define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
-# define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
-# define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
+# define CFG_SYS_NS16550_COM1		SUNXI_UART0_BASE
+# define CFG_SYS_NS16550_COM2		SUNXI_UART1_BASE
+# define CFG_SYS_NS16550_COM3		SUNXI_UART2_BASE
+# define CFG_SYS_NS16550_COM4		SUNXI_UART3_BASE
+# define CFG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
 #endif
 
 /* CPU */
@@ -44,13 +42,13 @@
  */
 #ifdef CONFIG_MACH_SUN9I
 #define SDRAM_OFFSET(x) 0x2##x
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_BASE		0x20000000
 #elif defined(CONFIG_MACH_SUNIV)
 #define SDRAM_OFFSET(x) 0x8##x
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #else
 #define SDRAM_OFFSET(x) 0x4##x
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 /* V3s do not have enough memory to place code at 0x4a000000 */
 #endif
 
@@ -64,17 +62,13 @@
  * is known yet.
  * H6 has SRAM A1 at 0x00020000.
  */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SUNXI_SRAM_ADDRESS
+#define CFG_SYS_INIT_RAM_ADDR	CONFIG_SUNXI_SRAM_ADDRESS
 /* FIXME: this may be larger on some SoCs */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x8000 /* 32 KiB */
+#define CFG_SYS_INIT_RAM_SIZE	0x8000 /* 32 KiB */
 
-#define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_0			CFG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
 
-#ifdef CONFIG_NAND_SUNXI
-#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
-#endif
-
 /* mmc config */
 #define CONFIG_MMC_SUNXI_SLOT		0
 

diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
index 63d897d..6992689 100644
--- a/include/configs/synquacer.h
+++ b/include/configs/synquacer.h

@@ -6,12 +6,12 @@
 #define __CONFIG_H
 
 /* Timers for fasp(TIMCLK) */
-#define CONFIG_SYS_TIMERBASE		0x31080000	/* AP Timer 1 (ARM-SP804) */
+#define CFG_SYS_TIMERBASE		0x31080000	/* AP Timer 1 (ARM-SP804) */
 
 /*
  * SDRAM (for initialize)
  */
-#define CONFIG_SYS_SDRAM_BASE		(0x80000000)	/* Start address of DDR3 */
+#define CFG_SYS_SDRAM_BASE		(0x80000000)	/* Start address of DDR3 */
 #define PHYS_SDRAM_SIZE			(0x7c000000)	/* Default size (2GB - Secure memory) */
 
 #define CONFIG_VERY_BIG_RAM				/* SynQuacer supports up to 64GB */
@@ -28,7 +28,7 @@
  */
 
 /* RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+#define CFG_SYS_I2C_RTC_ADDR		0x51
 
 /* Serial (pl011)       */
 #define UART_CLK			(62500000)
@@ -36,8 +36,8 @@
 #define CONFIG_PL01x_PORTS		{(void *)(0x2a400000)}
 
 /* Support MTD */
-#define CONFIG_SYS_FLASH_BASE		(0x08000000)
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CFG_SYS_FLASH_BASE		(0x08000000)
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE}
 
 /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
 

diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 45780d9..30f8425 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h

@@ -29,8 +29,8 @@
  */
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
 
 /* Misc CPU related */
 
@@ -41,32 +41,27 @@
  * SDRAM: 1 bank, min 32, max 128 MB
  * Initialized before u-boot gets started.
  */
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE		(128 * SZ_1M)
+#define CFG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE		(128 * SZ_1M)
 
 /*
  * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
  * leaving the correct space for initial global data structure above
  * that address while providing maximum stack area below.
  */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE	0x1000
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CFG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PC13
 #endif
 
 #if defined(CONFIG_BOARD_TAURUS)
-/* USB DFU support */
-
-#define CONFIG_USB_GADGET_AT91
-
 /* DFU class support */
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 #endif
@@ -127,23 +122,21 @@
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_NAND_ENABLE_PIN_SPL	(2*32 + 14)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
-#define CONFIG_SYS_NAND_SIZE		(256 * SZ_1M)
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 
-#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CFG_SYS_MASTER_CLOCK		132096000
 #define AT91_PLL_LOCK_TIMEOUT		1000000
-#define CONFIG_SYS_AT91_PLLA		0x202A3F01
-#define CONFIG_SYS_MCKR			0x1300
-#define CONFIG_SYS_MCKR_CSS		(0x02 | CONFIG_SYS_MCKR)
-#define CONFIG_SYS_AT91_PLLB		0x10193F05
+#define CFG_SYS_AT91_PLLA		0x202A3F01
+#define CFG_SYS_MCKR			0x1300
+#define CFG_SYS_MCKR_CSS		(0x02 | CFG_SYS_MCKR)
+#define CFG_SYS_AT91_PLLB		0x10193F05
 
 #endif

diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 16bdc39b..1318f5e 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h

@@ -12,15 +12,14 @@
  * Memory configuration
  */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE		SZ_128M
 
 /*
  * UART configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		166666666
+#define CFG_SYS_NS16550_CLK		166666666
 
 /*
  * Even though the board houses Realtek RTL8211E PHY

diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 7f19785..fcc9674 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h

@@ -13,16 +13,12 @@
 /* General configuration */
 
 /* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE		MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_SDRAM_BASE		MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
-
-#define CONFIG_SYS_BOOTMAPSZ		0x10000000
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
-/* Framebuffer */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
+#define CFG_SYS_BOOTMAPSZ		0x10000000
 
 /* PCI */
 #ifdef CONFIG_CMD_PCI

diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
index f8e741a..0987966 100644
--- a/include/configs/tec-ng.h
+++ b/include/configs/tec-ng.h

@@ -14,7 +14,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 

diff --git a/include/configs/tec.h b/include/configs/tec.h
index 2377b47..ddf753d 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h

@@ -16,7 +16,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* NAND support */
 

diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 2915db7..66cf7ae 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h

@@ -17,8 +17,8 @@
 
 /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
 #ifndef CONFIG_ARM64
-#define CONFIG_SYS_TIMER_RATE		1000000
-#define CONFIG_SYS_TIMER_COUNTER	NV_PA_TMRUS_BASE
+#define CFG_SYS_TIMER_RATE		1000000
+#define CFG_SYS_TIMER_COUNTER	NV_PA_TMRUS_BASE
 #endif
 
 /* Environment */
@@ -26,7 +26,7 @@
 /*
  * NS16550 Configuration
  */
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CFG_SYS_NS16550_CLK		V_NS16550_CLK
 
 #ifdef CONFIG_ARM64
 #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
@@ -40,13 +40,13 @@
 #define PHYS_SDRAM_1		NV_PA_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
 
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM_1
 
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* 256M */
+#define CFG_SYS_BOOTMAPSZ	(256 << 20)	/* 256M */
 
 #ifndef CONFIG_ARM64
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CFG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
+#define CFG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
 
 /* Defines for SPL */
 #endif

diff --git a/include/configs/ten64.h b/include/configs/ten64.h
index 04772c9..5772471 100644
--- a/include/configs/ten64.h
+++ b/include/configs/ten64.h

@@ -10,7 +10,7 @@
 #include "ls1088a_common.h"
 
 
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 #define QSPI_NOR_BOOTCOMMAND	"run distro_bootcmd"
 #define SD_BOOTCOMMAND		"run distro_bootcmd"

diff --git a/include/configs/theadorable-x86-dfi-bt700.h b/include/configs/theadorable-x86-dfi-bt700.h
index bb3186e..663a49e 100644
--- a/include/configs/theadorable-x86-dfi-bt700.h
+++ b/include/configs/theadorable-x86-dfi-bt700.h

@@ -13,7 +13,6 @@
 #include <configs/x86-common.h>
 
 /* Use BayTrail internal HS UART which is memory-mapped */
-#undef  CONFIG_SYS_NS16550_PORT_MAPPED
 
 /* Set the board specific parameters */
 #define DEF_ENV_TFTPDIR		"theadorable-x86-dfi"

diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 655fcb0..76b4963 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h

@@ -68,6 +68,6 @@
 /* Defines for SPL */
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_SDRAM_SIZE		SZ_2G
+#define CFG_SYS_SDRAM_SIZE		SZ_2G
 
 #endif /* _CONFIG_THEADORABLE_H */

diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index cf2efdb..7becf1e 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h

@@ -8,12 +8,12 @@
 
 #define MEM_BASE			0x00500000
 
-#define CONFIG_SYS_LOWMEM_BASE		MEM_BASE
+#define CFG_SYS_LOWMEM_BASE		MEM_BASE
 
 /* Link Definitions */
 
 /* SMP Spin Table Definitions */
-#define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CPU_RELEASE_ADDR		(CFG_SYS_SDRAM_BASE + 0x7fff0)
 
 /* PL011 Serial Configuration */
 
@@ -22,15 +22,15 @@
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE			(0x801000000000)
 #define GICR_BASE			(0x801000002000)
-#define CONFIG_SYS_SERIAL0		0x87e024000000
-#define CONFIG_SYS_SERIAL1		0x87e025000000
+#define CFG_SYS_SERIAL0		0x87e024000000
+#define CFG_SYS_SERIAL1		0x87e025000000
 
 /* Miscellaneous configurable options */
 
 /* Physical Memory Map */
 #define PHYS_SDRAM_1			(MEM_BASE)	  /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE		(0x80000000-MEM_BASE)	/* 2048 MB */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 /* Initial environment variables */
 #define UBOOT_IMG_HEAD_SIZE		0x40

diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 97166e0..03849ad 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h

@@ -69,25 +69,21 @@
 #define PHYS_DRAM_1_SIZE		0x20000000	/* 512MB */
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1024MB */
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /**
  * Platform/Board specific defs
  */
-#define CONFIG_SYS_TIMERBASE		0x4802E000
+#define CFG_SYS_TIMERBASE		0x4802E000
 
 /* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		(48000000)
-#define CONFIG_SYS_NS16550_COM1		0x48020000	/* Base EVM has UART0 */
+#define CFG_SYS_NS16550_CLK		(48000000)
+#define CFG_SYS_NS16550_COM1		0x48020000	/* Base EVM has UART0 */
 
 /* CPU */
 
 /* Defines for SPL */
 
-#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
-
 /*
  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  * 64 bytes before this address should be set aside for u-boot.img's

diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 82add65..7b04292 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h

@@ -20,20 +20,18 @@
 #define V_SCLK          (V_OSCK >> 1)
 
 #define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /**
  * Platform/Board specific defs
  */
-#define CONFIG_SYS_TIMERBASE    0x4802E000
+#define CFG_SYS_TIMERBASE    0x4802E000
 
 /*
  * NS16550 Configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK      (48000000)
-#define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
+#define CFG_SYS_NS16550_CLK      (48000000)
+#define CFG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
 
 /* allow overwriting serial config and ethaddr */
 
@@ -42,13 +40,13 @@
  * GPMC NAND block.  We support 1 device and the physical address to
  * access CS0 at is 0x8000000.
  */
-#define CONFIG_SYS_NAND_BASE		0x8000000
+#define CFG_SYS_NAND_BASE		0x8000000
 
 /* NAND: SPL related configs */
 
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
 					 10, 11, 12, 13, 14, 15, 16, 17, \
 					 18, 19, 20, 21, 22, 23, 24, 25, \
 					 26, 27, 28, 29, 30, 31, 32, 33, \
@@ -56,8 +54,8 @@
 					 42, 43, 44, 45, 46, 47, 48, 49, \
 					 50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CFG_SYS_NAND_ECCSIZE		512
+#define CFG_SYS_NAND_ECCBYTES	14
 
 /* SPL */
 /* Defines for SPL */

diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 5d5df6b..ed17b42 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h

@@ -12,18 +12,12 @@
 #define __CONFIG_TI_AM335X_COMMON_H__
 
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
-#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CFG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
 #include <asm/arch/omap.h>
 
 /* NS16550 Configuration */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_NS16550_SERIAL
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#endif
-#endif
-#define CONFIG_SYS_NS16550_CLK		48000000
+#define CFG_SYS_NS16550_CLK		48000000
 
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the

diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 05536c3..d54c208 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h

@@ -64,7 +64,7 @@
  * initial stack pointer in our SRAM. Otherwise, we can define
  * CONFIG_NR_DRAM_BANKS before including this file.
  */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
 /* If DM_I2C, enable non-DM I2C support */
 
@@ -123,7 +123,7 @@
 /* General parts of the framework, required. */
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
 #endif
 #endif /* !CONFIG_NOR_BOOT */
 

diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 6c01ab8..ea45bba 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h

@@ -14,7 +14,7 @@
 /* SoC Configuration */
 
 /* Memory Configuration */
-#define CONFIG_SYS_LPAE_SDRAM_BASE	0x800000000
+#define CFG_SYS_LPAE_SDRAM_BASE	0x800000000
 #define CONFIG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
 
 #ifdef CONFIG_SYS_MALLOC_F_LEN
@@ -34,23 +34,17 @@
 #define KEYSTONE_SRAM_SCRATCH_SPACE_END		(TI_SRAM_SCRATCH_BOARD_EEPROM_END)
 
 /* UART Configuration */
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_COM1		KS2_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2		KS2_UART1_BASE
+#define CFG_SYS_NS16550_COM1		KS2_UART0_BASE
+#define CFG_SYS_NS16550_COM2		KS2_UART1_BASE
 
 #ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_NS16550_CLK		ks_clk_get_rate(KS2_CLK1_6)
+#define CFG_SYS_NS16550_CLK		ks_clk_get_rate(KS2_CLK1_6)
 #else
-#define CONFIG_SYS_NS16550_CLK		ks_clk_get_rate(uart_pll_clk) / 2
+#define CFG_SYS_NS16550_CLK		ks_clk_get_rate(uart_pll_clk) / 2
 #endif
 
 /* SPI Configuration */
-#define CONFIG_SYS_SPI_CLK		ks_clk_get_rate(KS2_CLK1_6)
-
-/* Network Configuration */
-#define CONFIG_SYS_SGMII_REFCLK_MHZ	312
-#define CONFIG_SYS_SGMII_LINERATE_MHZ	1250
-#define CONFIG_SYS_SGMII_RATESCALE	2
+#define CFG_SYS_SPI_CLK		ks_clk_get_rate(KS2_CLK1_6)
 
 /* Keystone net */
 #define CONFIG_KSNET_MAC_ID_BASE		KS2_MAC_ID_BASE_ADDR
@@ -62,13 +56,12 @@
 /* EEPROM definitions */
 
 /* NAND Configuration */
-#define CONFIG_SYS_NAND_MASK_CLE		0x4000
-#define CONFIG_SYS_NAND_MASK_ALE		0x2000
-#define CONFIG_SYS_NAND_CS			2
+#define CFG_SYS_NAND_MASK_CLE		0x4000
+#define CFG_SYS_NAND_MASK_ALE		0x2000
+#define CFG_SYS_NAND_CS			2
 
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST		{ 0x30000000, }
-#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+#define CFG_SYS_NAND_LARGEPAGE
+#define CFG_SYS_NAND_BASE_LIST		{ 0x30000000, }
 
 #define DFU_ALT_INFO_MMC \
 	"dfu_alt_info_mmc=" \
@@ -183,9 +176,9 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
 #ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_HZ_CLOCK		ks_clk_get_rate(KS2_CLK1_6)
+#define CFG_SYS_HZ_CLOCK		ks_clk_get_rate(KS2_CLK1_6)
 #else
-#define CONFIG_SYS_HZ_CLOCK		get_external_clk(sys_clk)
+#define CFG_SYS_HZ_CLOCK		get_external_clk(sys_clk)
 #endif
 
 #endif /* __CONFIG_KS2_EVM_H */

diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
index 44706c7..d34042a 100644
--- a/include/configs/ti_armv7_omap.h
+++ b/include/configs/ti_armv7_omap.h

@@ -16,8 +16,8 @@
  * access CS0 at is 0x8000000.
  */
 #ifdef CONFIG_MTD_RAW_NAND
-#ifndef CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_BASE		0x8000000
+#ifndef CFG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE		0x8000000
 #endif
 #endif
 

diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 47f3c81..36a05b6 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h

@@ -26,19 +26,15 @@
 
 /* NS16550 Configuration */
 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-#if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#endif /* !CONFIG_DM_SERIAL */
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+#define CFG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CFG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
 					115200}
 
 /* Select serial console configuration */
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
-#define CONFIG_SYS_NS16550_COM2		OMAP34XX_UART2
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CFG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CFG_SYS_NS16550_COM2		OMAP34XX_UART2
+#define CFG_SYS_NS16550_COM3		OMAP34XX_UART3
 #endif
 
 /* Physical Memory Map */
@@ -50,12 +46,12 @@
  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  * This rate is divided by a local divisor.
  */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CFG_SYS_TIMERBASE		(OMAP34XX_GPT2)
 
 /* SPL */
 
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_BASE		0x30000000
+#define CFG_SYS_NAND_BASE		0x30000000
 #endif
 
 /* Now bring in the rest of the common code. */

diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 0568946..64ec59d 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h

@@ -12,7 +12,7 @@
 #define __CONFIG_TI_OMAP4_COMMON_H
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE	0x48242000
+#define CFG_SYS_PL310_BASE	0x48242000
 #endif
 
 /* Get CPU defs */
@@ -20,23 +20,18 @@
 #include <asm/arch/omap.h>
 
 /* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+#define CFG_SYS_TIMERBASE		GPT2_BASE
 
 #include <configs/ti_armv7_omap.h>
 
 /*
  * Hardware drivers
  */
-#define CONFIG_SYS_NS16550_CLK		48000000
+#define CFG_SYS_NS16550_CLK		48000000
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+#define CFG_SYS_NS16550_COM3		UART3_BASE
 #endif
 
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER		1
-
 /*
  * Environment setup
  */

diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 24bbf9e..37ab2e4 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h

@@ -17,7 +17,7 @@
 #define __CONFIG_TI_OMAP5_COMMON_H
 
 /* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+#define CFG_SYS_TIMERBASE		GPT2_BASE
 
 #include <linux/stringify.h>
 
@@ -29,11 +29,7 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_SYS_NS16550_CLK		48000000
-#if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#endif
+#define CFG_SYS_NS16550_CLK		48000000
 
 /*
  * Environment setup

diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h
index ab6cd06..0f28690 100644
--- a/include/configs/total_compute.h
+++ b/include/configs/total_compute.h

@@ -23,7 +23,7 @@
 /* Top 48MB reserved for secure world use */
 #define DRAM_SEC_SIZE		0x03000000
 #define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM_1
 
 #define PHYS_SDRAM_2		0x8080000000
 #define PHYS_SDRAM_2_SIZE	0x180000000
@@ -41,6 +41,6 @@
  * Else boot FIT image.
  */
 
-#define CONFIG_SYS_FLASH_BASE		0x0C000000
+#define CFG_SYS_FLASH_BASE		0x0C000000
 
 #endif /* __TOTAL_COMPUTE_H */

diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index b14726a..24943c8 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h

@@ -6,15 +6,15 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_SDRAM_BASE		0xa0000000
+#define CFG_SYS_SDRAM_BASE		0xa0000000
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0xbd000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x8000
+#define CFG_SYS_INIT_RAM_ADDR	0xbd000000
+#define CFG_SYS_INIT_RAM_SIZE	0x8000
 
 /*
  * Serial Port
  */
-#define CONFIG_SYS_NS16550_CLK		40000000
+#define CFG_SYS_NS16550_CLK		40000000
 
 /*
  * Command

diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 2c58915..7a1ad95 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h

@@ -11,13 +11,6 @@
 #include <linux/kconfig.h>
 #include <linux/stringify.h>
 
-/* SPL */
-/* #if defined(CONFIG_SPL_BUILD) */
-/* common IMX6 SPL configuration */
-#include "imx6_spl.h"
-
-/* #endif */
-
 /* place code in last 4 MiB of RAM */
 
 #include "mx6_common.h"
@@ -38,7 +31,6 @@
 #define CONFIG_I2C_MULTI_BUS
 
 #if !defined(CONFIG_DM_PMIC)
-#define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 #define TQMA6_PFUZE100_I2C_BUS		2
 #endif
@@ -275,9 +267,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /*
  * All the defines above are for the TQMa6 SoM

diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
index 9991306..4d8839b 100644
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h

@@ -16,11 +16,9 @@
 /* Watchdog */
 
 /* Config on-board RTC */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_RTC_BUS_NUM		2
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CFG_SYS_RTC_BUS_NUM		2
+#define CFG_SYS_I2C_RTC_ADDR		0x68
 /* Turn off RTC square-wave output to save battery */
-#define CONFIG_RTC_DS1337_NOOSC
 
 /* LED */
 

diff --git a/include/configs/trats.h b/include/configs/trats.h
index ca31868..ec18842 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h

@@ -12,12 +12,12 @@
 #include <configs/exynos4-common.h>
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE	0x10502000
+#define CFG_SYS_PL310_BASE	0x10502000
 #endif
 
 /* TRATS has 4 banks of DRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CFG_SYS_SDRAM_BASE
 #define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
 /* Tizen - partitions definitions */
@@ -125,9 +125,6 @@
 
 /* GPT */
 
-/* Common misc for Samsung */
-#define CONFIG_MISC_COMMON
-
 /* Download menu - definitions for check keys */
 #ifndef __ASSEMBLY__
 

diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index f324ea7..0aa331e 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h

@@ -13,12 +13,12 @@
 #include <configs/exynos4-common.h>
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
-#define CONFIG_SYS_PL310_BASE	0x10502000
+#define CFG_SYS_PL310_BASE	0x10502000
 #endif
 
 /* TRATS2 has 4 banks of DRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CFG_SYS_SDRAM_BASE
 #define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
 /* Tizen - partitions definitions */
@@ -115,9 +115,6 @@
 
 /* GPT */
 
-/* Common misc for Samsung */
-#define CONFIG_MISC_COMMON
-
 /* Download menu - definitions for check keys */
 #ifndef __ASSEMBLY__
 

diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index b562d44..e4cbc7d 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h

@@ -16,7 +16,7 @@
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
 #define CONFIG_TEGRA_UARTA_GPU
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 /* SPI */
 

diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h
index f549f9f..fdb420e 100644
--- a/include/configs/turris_mox.h
+++ b/include/configs/turris_mox.h

@@ -8,8 +8,8 @@
 #ifndef _CONFIG_TURRIS_MOX_H
 #define _CONFIG_TURRIS_MOX_H
 
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 300, 600, 1200, 1800, 2400, 4800, \
+#define CFG_SYS_SDRAM_BASE		0x00000000
+#define CFG_SYS_BAUDRATE_TABLE	{ 300, 600, 1200, 1800, 2400, 4800, \
 					  9600, 19200, 38400, 57600, 115200, \
 					  230400, 460800, 500000, 576000, \
 					  921600, 1000000, 1152000, 1500000, \

diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 8af5151..fac8c1e 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h

@@ -10,8 +10,6 @@
 
 #include "mx6_common.h"
 
-#include "imx6_spl.h"
-
 #define CONFIG_MXC_UART_BASE		UART2_BASE
 
 /* MMC Configuration */
@@ -51,9 +49,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment organization */
 

diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index 093e2e8..d4c9223 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h

@@ -12,8 +12,6 @@
 
 #include "mx6_common.h"
 
-#include "imx6_spl.h"
-
 /* MMC Configuration */
 #define CFG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
 
@@ -59,12 +57,11 @@
 
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* PMIC */
-#define CONFIG_POWER_PFUZE3000
 #define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
 #define PFUZE3000_I2C_BUS	0
 

diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h
index a977271..ab199bc 100644
--- a/include/configs/ulcb.h
+++ b/include/configs/ulcb.h

@@ -14,7 +14,7 @@
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
 
 #endif /* __ULCB_H */

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 32b47db..8cd81f1 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h

@@ -37,11 +37,11 @@
 
 #if !defined(CONFIG_ARM64)
 /* Time clock 1MHz */
-#define CONFIG_SYS_TIMER_RATE			1000000
+#define CFG_SYS_TIMER_RATE			1000000
 #endif
 
-#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
-#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
+#define CFG_SYS_NAND_REGS_BASE			0x68100000
+#define CFG_SYS_NAND_DATA_BASE			0x68000000
 
 /*
  * Network Configuration
@@ -162,11 +162,11 @@
 	LINUXBOOT_ENV_SETTINGS \
 	BOOTENV
 
-#define CONFIG_SYS_BOOTMAPSZ			0x20000000
+#define CFG_SYS_BOOTMAPSZ			0x20000000
 
 /* only for SPL */
 
 /* subtract sizeof(struct legacy_img_hdr) */
-#define CONFIG_SYS_UBOOT_BASE			(0x130000 - 0x40)
+#define CFG_SYS_UBOOT_BASE			(0x130000 - 0x40)
 
 #endif /* __CONFIG_UNIPHIER_H__ */

diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 44eaeda..657dbad 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h

@@ -17,29 +17,29 @@
 #include <asm/hardware.h>
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CFG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768
 
 /*
  * Hardware drivers
  */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+#define CFG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE		0x04000000
 
-#define CONFIG_SYS_INIT_RAM_SIZE	(16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE	(16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+#define CFG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */

diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index c381934..a2bc3cd 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h

@@ -27,9 +27,6 @@
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
-/* Fuse */
-#define CONFIG_FSL_IIM
-
 /* Linux boot */
 #define CONFIG_HOSTNAME		"usbarmory"
 
@@ -60,8 +57,8 @@
 #define PHYS_SDRAM			CSD0_BASE_ADDR
 #define PHYS_SDRAM_SIZE			(gd->ram_size)
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #endif				/* __CONFIG_H */

diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
index 02ddc6f..b031598 100644
--- a/include/configs/vcoreiii.h
+++ b/include/configs/vcoreiii.h

@@ -10,17 +10,17 @@
 
 /* Onboard devices */
 
-#define CONFIG_SYS_INIT_SP_OFFSET       0x400000
+#define CFG_SYS_INIT_SP_OFFSET       0x400000
 
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_MIPS_TIMER_FREQ
+#define CFG_SYS_NS16550_CLK		CONFIG_SYS_MIPS_TIMER_FREQ
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
-#define CONFIG_SYS_SDRAM_SIZE		(128 * SZ_1M)
+#define CFG_SYS_SDRAM_SIZE		(128 * SZ_1M)
 #elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
-#define CONFIG_SYS_SDRAM_SIZE		(256 * SZ_1M)
+#define CFG_SYS_SDRAM_SIZE		(256 * SZ_1M)
 #elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
-#define CONFIG_SYS_SDRAM_SIZE		(512 * SZ_1M)
+#define CFG_SYS_SDRAM_SIZE		(512 * SZ_1M)
 #else
 #error Unknown DDR size - please add!
 #endif

diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index 03aa7ad..b2dc04a 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h

@@ -16,7 +16,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 

diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 0bd5a1e..f7a5077 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h

@@ -15,7 +15,7 @@
 
 /* Board-specific serial config */
 #define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 

diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index f513dad..18ac6b2 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h

@@ -9,7 +9,7 @@
 #include <asm/arch/imx-regs.h>
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
@@ -53,14 +53,14 @@
 		"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \
 		"${blkcnt}; fi\0"
 
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
+#define CFG_SYS_INIT_RAM_ADDR        0x40000000
+#define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
 #if defined(CONFIG_ENV_IS_IN_MMC)
 /* Environment in eMMC, before config block at the end of 1st "boot sector" */
 #endif
 
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CFG_SYS_SDRAM_BASE           0x40000000
 
 /* SDRAM configuration */
 #define PHYS_SDRAM                      0x40000000

diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h
index fea4329..88839a6 100644
--- a/include/configs/verdin-imx8mp.h
+++ b/include/configs/verdin-imx8mp.h

@@ -9,7 +9,7 @@
 #include <asm/arch/imx-regs.h>
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_UBOOT_BASE	\
+#define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
@@ -65,11 +65,11 @@
 		"${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \
 		"${blkcnt}; fi\0"
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE	SZ_512K
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	SZ_512K
 
 /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CFG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			(SZ_2G + SZ_1G)
 #define PHYS_SDRAM_2			0x100000000

diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h
index 0c11b6b..30c1f50 100644
--- a/include/configs/vexpress_aemv8.h
+++ b/include/configs/vexpress_aemv8.h

@@ -96,7 +96,7 @@
 /* Top 16MB reserved for secure world use */
 #define DRAM_SEC_SIZE		0x01000000
 #define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE	PHYS_SDRAM_1
 
 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 #define PHYS_SDRAM_2			(0x880000000)
@@ -254,9 +254,9 @@
 		BOOTENV
 
 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CFG_SYS_FLASH_BASE		0x08000000
 #else
-#define CONFIG_SYS_FLASH_BASE		(V2M_PA_BASE + 0x0C000000)
+#define CFG_SYS_FLASH_BASE		(V2M_PA_BASE + 0x0C000000)
 #endif
 
 #endif /* __VEXPRESS_AEMV8_H */

diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 5d77306..e8b6acf 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h

@@ -112,17 +112,16 @@
 #define SCTL_BASE			V2M_SYSCTL
 #define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
 
-#define CONFIG_SYS_TIMER_RATE		1000000
-#define CONFIG_SYS_TIMER_COUNTER	(V2M_TIMER01 + 0x4)
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CFG_SYS_TIMER_RATE		1000000
+#define CFG_SYS_TIMER_COUNTER	(V2M_TIMER01 + 0x4)
 
 /* PL011 Serial Configuration */
 #define CONFIG_PL011_CLOCK		24000000
-#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
-					 (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_PL01x_PORTS		{(void *)CFG_SYS_SERIAL0, \
+					 (void *)CFG_SYS_SERIAL1}
 
-#define CONFIG_SYS_SERIAL0		V2M_UART0
-#define CONFIG_SYS_SERIAL1		V2M_UART1
+#define CFG_SYS_SERIAL0		V2M_UART0
+#define CFG_SYS_SERIAL1		V2M_UART1
 
 /* Miscellaneous configurable options */
 #define LINUX_BOOT_PARAM_ADDR		(V2M_BASE + 0x2000)
@@ -135,8 +134,8 @@
 #define PHYS_SDRAM_2_SIZE		0x20000000	/* 512 MB */
 
 /* additions for new relocation code */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE		0x1000
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_INIT_RAM_SIZE		0x1000
 
 /* Basic environment settings */
 #define BOOT_TARGET_DEVICES(func) \
@@ -165,7 +164,7 @@
 		"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
 
 /* FLASH and environment organization */
-#define CONFIG_SYS_FLASH_SIZE		0x04000000
+#define CFG_SYS_FLASH_SIZE		0x04000000
 
 /* Timeout values in ticks */
 
@@ -178,6 +177,6 @@
  */
 
 /* Store environment at top of flash */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ V2M_NOR0, V2M_NOR1 }
+#define CFG_SYS_FLASH_BANKS_LIST	{ V2M_NOR0, V2M_NOR1 }
 
 #endif /* VEXPRESS_COMMON_H */

diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 7e3d347..14e6b2b 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h

@@ -14,7 +14,7 @@
 /* NAND support */
 
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+#define CFG_SYS_NAND_BASE		NFC_BASE_ADDR
 
 /* Dynamic MTD partition support */
 #endif
@@ -123,8 +123,8 @@
 #define PHYS_SDRAM			(0x80000000)
 #define PHYS_SDRAM_SIZE			(128 * 1024 * 1024)
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 #endif

diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index a157296..9f72bdd 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h

@@ -21,17 +21,17 @@
 #define CONFIG_USART_ID			30
 
 /* Timer */
-#define CONFIG_SYS_TIMER_COUNTER	0xfc06863c
+#define CFG_SYS_TIMER_COUNTER	0xfc06863c
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x4000000
+#define CFG_SYS_SDRAM_BASE           0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x4000000
 
 /* MMC */
 
 #ifdef CONFIG_CMD_MMC
 #define ATMEL_BASE_MMCI			0xfc000000
-#define CONFIG_SYS_MMC_CLK_OD		500000
+#define CFG_SYS_MMC_CLK_OD		500000
 
 /* For generating MMC partitions */
 

diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index a4484fd..1a71b30 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h

@@ -10,10 +10,6 @@
 
 #include "mx6_common.h"
 
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	func(MMC, mmc, 1) \
@@ -27,15 +23,14 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* MMC Configuration */
 #define CFG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
 
 /* PMIC */
-#define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* Network */

diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
index 6f36d69..43050d6 100644
--- a/include/configs/vocore2.h
+++ b/include/configs/vocore2.h

@@ -7,22 +7,20 @@
 #define __VOCORE2_CONFIG_H__
 
 /* RAM */
-#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE		0x80000000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CFG_SYS_INIT_SP_OFFSET	0x400000
 
 /* SPL */
 
-#define CONFIG_SYS_UBOOT_START		CONFIG_TEXT_BASE
+#define CFG_SYS_UBOOT_START		CONFIG_TEXT_BASE
 
 /* Dummy value */
-#define CONFIG_SYS_UBOOT_BASE		0
+#define CFG_SYS_UBOOT_BASE		0
 
 /* Serial SPL */
-#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SYS_NS16550_CLK		40000000
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM3		0xb0000e00
+#define CFG_SYS_NS16550_CLK		40000000
+#define CFG_SYS_NS16550_COM3		0xb0000e00
 
 /* RAM */
 

diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 91c1f4b..6923009 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h

@@ -10,8 +10,6 @@
 
 #include "mx6_common.h"
 
-#include "imx6_spl.h"
-
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* MMC Configuration */
@@ -22,10 +20,6 @@
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS		0
 
-/* Framebuffer */
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"console=ttymxc0\0" \
 	"splashpos=m,m\0" \
@@ -91,9 +85,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment organization */
 

diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index a4b12dc..56c90aa 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h

@@ -84,9 +84,9 @@
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* environment organization */
 

diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index a7c805c..010da15 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h

@@ -16,10 +16,8 @@
 /*
  * Memory configurations
  */
-#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
-
-#define CONFIG_RTC_DS1374
+#define CFG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_SIZE		SZ_128M
 
 /*
  * U-Boot General Configurations
@@ -42,8 +40,8 @@
  */
 
 /* driver configuration */
-#define CONFIG_SYS_MAX_NAND_CHIPS 1
-#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
+#define CFG_SYS_MAX_NAND_CHIPS 1
+#define CFG_SYS_NAND_BASE MLC_NAND_BASE
 
 /*
  * GPIO
@@ -63,8 +61,8 @@
 /* SPL will use serial */
 /* SPL will load U-Boot from NAND offset 0x40000 */
 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST   CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST   CONFIG_TEXT_BASE
 
 /*
  * Include SoC specific configuration

diff --git a/include/configs/x530.h b/include/configs/x530.h
index 0add626..dee87cb 100644
--- a/include/configs/x530.h
+++ b/include/configs/x530.h

@@ -13,11 +13,9 @@
 /*
  * NS16550 Configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK		CFG_SYS_TCLK
 #if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_COM1		MV_UART_CONSOLE_BASE
+#define CFG_SYS_NS16550_COM1		MV_UART_CONSOLE_BASE
 #endif
 
 /*

diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 8e22d6e..3e17b53 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h

@@ -21,7 +21,6 @@
 /*-----------------------------------------------------------------------
  * Serial Configuration
  */
-#define CONFIG_SYS_NS16550_PORT_MAPPED
 
 /*
  * Miscellaneous configurable options
@@ -31,7 +30,7 @@
  * CPU Features
  */
 
-#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
+#define CFG_SYS_STACK_SIZE			(32 * 1024)
 
 /*-----------------------------------------------------------------------
  * Environment configuration

diff --git a/include/configs/xea.h b/include/configs/xea.h
index 19ccf63..b432ab2 100644
--- a/include/configs/xea.h
+++ b/include/configs/xea.h

@@ -16,14 +16,14 @@
 
 /* SPL */
 
-#define CONFIG_SYS_SPI_KERNEL_OFFS	SZ_1M
-#define CONFIG_SYS_SPI_ARGS_OFFS	SZ_512K
-#define CONFIG_SYS_SPI_ARGS_SIZE	SZ_32K
+#define CFG_SYS_SPI_KERNEL_OFFS	SZ_1M
+#define CFG_SYS_SPI_ARGS_OFFS	SZ_512K
+#define CFG_SYS_SPI_ARGS_SIZE	SZ_32K
 
 /* Memory configuration */
 #define PHYS_SDRAM_1			0x40000000	/* Base address */
 #define PHYS_SDRAM_1_SIZE		0x10000000	/* Max 256 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
 /* Extra Environment */
 #define CONFIG_HOSTNAME		"xea"

diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h
index 364dae0..612436a 100644
--- a/include/configs/xenguest_arm64.h
+++ b/include/configs/xenguest_arm64.h

@@ -11,7 +11,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS
 
-#undef CONFIG_SYS_SDRAM_BASE
+#undef CFG_SYS_SDRAM_BASE
 
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS	\

diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index 8caf539..ee3130e 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h

@@ -15,7 +15,7 @@
 #define GICR_BASE	0xF9080000
 
 /* Serial setup */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
 	{ 4800, 9600, 19200, 38400, 57600, 115200 }
 
 /* GUID for capsule updatable firmware image */

diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h
index 0ccd38b..7d77189 100644
--- a/include/configs/xilinx_versal_net.h
+++ b/include/configs/xilinx_versal_net.h

@@ -20,7 +20,7 @@
 #define GICR_BASE	0xF9060000
 
 /* Serial setup */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
 	{ 4800, 9600, 19200, 38400, 57600, 115200 }
 
 #if defined(CONFIG_CMD_DFU)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 60f007a..efe241d 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h

@@ -15,7 +15,7 @@
 #define GICC_BASE	0xF9020000
 
 /* Serial setup */
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
 	{ 4800, 9600, 19200, 38400, 57600, 115200 }
 
 /* GUIDs for capsule updatable firmware images */
@@ -192,9 +192,9 @@
 #endif
 
 #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
-# define CONFIG_SYS_SPI_KERNEL_OFFS	0x80000
-# define CONFIG_SYS_SPI_ARGS_OFFS	0xa0000
-# define CONFIG_SYS_SPI_ARGS_SIZE	0xa0000
+# define CFG_SYS_SPI_KERNEL_OFFS	0x80000
+# define CFG_SYS_SPI_ARGS_OFFS	0xa0000
+# define CFG_SYS_SPI_ARGS_SIZE	0xa0000
 #endif
 
 /* u-boot is like dtb */

diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h
index d2c0e91..1b6e26e 100644
--- a/include/configs/xilinx_zynqmp_mini_nand.h
+++ b/include/configs/xilinx_zynqmp_mini_nand.h

@@ -12,7 +12,7 @@
 
 #include <configs/xilinx_zynqmp_mini.h>
 
-#define CONFIG_SYS_SDRAM_SIZE	0x1000000
-#define CONFIG_SYS_SDRAM_BASE	0x0
+#define CFG_SYS_SDRAM_SIZE	0x1000000
+#define CFG_SYS_SDRAM_BASE	0x0
 
 #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */

diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h
index b6bc402..3a7b7e0 100644
--- a/include/configs/xilinx_zynqmp_r5.h
+++ b/include/configs/xilinx_zynqmp_r5.h

@@ -10,13 +10,13 @@
 
 /* Serial drivers */
 /* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE  \
+#define CFG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 /* Boot configuration */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CFG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE	0x1000
 
 /* Extend size of kernel image for uncompression */
 

diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index fc8ec32..3e60489 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h

@@ -10,9 +10,6 @@
 #include "mx6_common.h"
 #include <asm/mach-imx/gpio.h>
 
-/* SPL options */
-#include "imx6_spl.h"
-
 #define CONFIG_MXC_UART_BASE		MX6UL_UART7_BASE_ADDR
 
 /* MMC Configs */
@@ -24,9 +21,9 @@
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 #define PHYS_SDRAM_SIZE			(128 << 20)
 
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE	IRAM_SIZE
 
 /* Environment is in stored in the eMMC boot partition */
 

diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index 58d01f4..9201dac 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h

@@ -21,12 +21,12 @@
 /*===================*/
 
 #if XCHAL_HAVE_PTP_MMU
-#define CONFIG_SYS_MEMORY_BASE		\
+#define CFG_SYS_MEMORY_BASE		\
 	(XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
-#define CONFIG_SYS_IO_BASE		0xf0000000
+#define CFG_SYS_IO_BASE		0xf0000000
 #else
-#define CONFIG_SYS_MEMORY_BASE		0x60000000
-#define CONFIG_SYS_IO_BASE		0x90000000
+#define CFG_SYS_MEMORY_BASE		0x60000000
+#define CFG_SYS_IO_BASE		0x90000000
 #define CONFIG_MAX_MEM_MAPPED		0x10000000
 #endif
 
@@ -42,12 +42,12 @@
  */
 
 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
-#define CONFIG_SYS_SDRAM_SIZE		CONFIG_BOARD_SDRAM_SIZE
+#define CFG_SYS_SDRAM_SIZE		CONFIG_BOARD_SDRAM_SIZE
 #else
-#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+#define CFG_SYS_SDRAM_SIZE		0x10000000
 #endif
 
-#define CONFIG_SYS_SDRAM_BASE		MEMADDR(0x00000000)
+#define CFG_SYS_SDRAM_BASE		MEMADDR(0x00000000)
 
 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
 
@@ -70,12 +70,12 @@
 #endif
 
 #if defined(CONFIG_MAX_MEM_MAPPED) && \
-	CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
+	CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE
 #define XTENSA_SYS_TEXT_ADDR		\
 	(MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
 #else
 #define XTENSA_SYS_TEXT_ADDR		\
-	(MEMADDR(CONFIG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
+	(MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
 #endif
 
 /*==============================*/
@@ -100,16 +100,16 @@
  */
 
 /* FPGA core clock frequency in Hz (also input to UART) */
-#define CONFIG_SYS_FPGAREG_FREQ	IOADDR(0x0D020004)	/* CPU clock frequency*/
+#define CFG_SYS_FPGAREG_FREQ	IOADDR(0x0D020004)	/* CPU clock frequency*/
 
 /*
  * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
  *   Bits 0..5 set the lower 6 bits of the default ethernet MAC.
  *   Bit 6 is reserved for future use by Tensilica.
- *   Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
+ *   Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to
  *   the base of flash * (when on/1) or to the base of RAM (when off/0).
  */
-#define CONFIG_SYS_FPGAREG_DIPSW	IOADDR(0x0D02000C)
+#define CFG_SYS_FPGAREG_DIPSW	IOADDR(0x0D02000C)
 #define FPGAREG_MAC_SHIFT		0	/* Ethernet MAC bits 0..5 */
 #define FPGAREG_MAC_WIDTH		6
 #define FPGAREG_MAC_MASK		0x3f
@@ -120,44 +120,42 @@
 #define FPGAREG_BOOT_FLASH		(1<<FPGAREG_BOOT_SHIFT)
 
 /* Force hard reset of board by writing a code to this register */
-#define CONFIG_SYS_FPGAREG_RESET	IOADDR(0x0D020010) /* Reset board .. */
-#define CONFIG_SYS_FPGAREG_RESET_CODE	0x0000DEAD   /*  by writing this code */
+#define CFG_SYS_FPGAREG_RESET	IOADDR(0x0D020010) /* Reset board .. */
+#define CFG_SYS_FPGAREG_RESET_CODE	0x0000DEAD   /*  by writing this code */
 
 /*====================*/
 /* Serial Driver Info */
 /*====================*/
 
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_COM1		IOADDR(0x0D050020) /* Base address */
+#define CFG_SYS_NS16550_COM1		IOADDR(0x0D050020) /* Base address */
 
 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
-#define CONFIG_SYS_NS16550_CLK		get_board_sys_clk()
+#define CFG_SYS_NS16550_CLK		get_board_sys_clk()
 
 /*======================*/
 /* Ethernet Driver Info */
 /*======================*/
 
 #define CONFIG_ETHBASE			00:50:C2:13:6f:00
-#define CONFIG_SYS_ETHOC_BASE		IOADDR(0x0d030000)
-#define CONFIG_SYS_ETHOC_BUFFER_ADDR	IOADDR(0x0D800000)
+#define CFG_SYS_ETHOC_BASE		IOADDR(0x0d030000)
+#define CFG_SYS_ETHOC_BUFFER_ADDR	IOADDR(0x0D800000)
 
 /*=====================*/
 /* Flash & Environment */
 /*=====================*/
 
 #ifdef CONFIG_XTFPGA_LX60
-# define CONFIG_SYS_FLASH_SIZE		0x0040000	/* 4MB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ	0x2000		/* param size  8KB */
-# define CONFIG_SYS_FLASH_BASE		IOADDR(0x08000000)
+# define CFG_SYS_FLASH_SIZE		0x0040000	/* 4MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ	0x2000		/* param size  8KB */
+# define CFG_SYS_FLASH_BASE		IOADDR(0x08000000)
 #elif defined(CONFIG_XTFPGA_KC705)
-# define CONFIG_SYS_FLASH_SIZE		0x8000000	/* 128MB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ	0x8000		/* param size 32KB */
-# define CONFIG_SYS_FLASH_BASE		IOADDR(0x00000000)
+# define CFG_SYS_FLASH_SIZE		0x8000000	/* 128MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ	0x8000		/* param size 32KB */
+# define CFG_SYS_FLASH_BASE		IOADDR(0x00000000)
 #else
-# define CONFIG_SYS_FLASH_SIZE		0x1000000	/* 16MB */
-# define CONFIG_SYS_FLASH_PARMSECT_SZ	0x8000		/* param size 32KB */
-# define CONFIG_SYS_FLASH_BASE		IOADDR(0x08000000)
+# define CFG_SYS_FLASH_SIZE		0x1000000	/* 16MB */
+# define CFG_SYS_FLASH_PARMSECT_SZ	0x8000		/* param size 32KB */
+# define CFG_SYS_FLASH_BASE		IOADDR(0x08000000)
 #endif
 
 /*

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 6574cf9..b8c142f 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h

@@ -11,13 +11,12 @@
 
 /* Cache options */
 #ifndef CONFIG_SYS_L2CACHE_OFF
-# define CONFIG_SYS_PL310_BASE		0xf8f02000
+# define CFG_SYS_PL310_BASE		0xf8f02000
 #endif
 
 #define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
-#define CONFIG_SYS_TIMERBASE		ZYNQ_SCUTIMER_BASEADDR
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+#define CFG_SYS_TIMERBASE		ZYNQ_SCUTIMER_BASEADDR
+#define CFG_SYS_TIMER_COUNTER	(CFG_SYS_TIMERBASE + 0x4)
 
 /* GUIDs for capsule updatable firmware images */
 #define XILINX_BOOT_IMAGE_GUID \
@@ -30,7 +29,7 @@
 
 /* Serial drivers */
 /* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE  \
+#define CFG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 /* Ethernet driver */
@@ -189,8 +188,8 @@
 
 /* Miscellaneous configurable options */
 
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000
+#define CFG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE	0x2000
 
 
 /* Extend size of kernel image for uncompression */
@@ -201,10 +200,10 @@
 
 /* qspi mode is working fine */
 #ifdef CONFIG_ZYNQ_QSPI
-#define CONFIG_SYS_SPI_ARGS_OFFS	0x200000
-#define CONFIG_SYS_SPI_ARGS_SIZE	0x80000
-#define CONFIG_SYS_SPI_KERNEL_OFFS	(CONFIG_SYS_SPI_ARGS_OFFS + \
-					CONFIG_SYS_SPI_ARGS_SIZE)
+#define CFG_SYS_SPI_ARGS_OFFS	0x200000
+#define CFG_SYS_SPI_ARGS_SIZE	0x80000
+#define CFG_SYS_SPI_KERNEL_OFFS	(CFG_SYS_SPI_ARGS_OFFS + \
+					CFG_SYS_SPI_ARGS_SIZE)
 #endif
 
 /* SP location before relocation, must use scratch RAM */

diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
index cb982c2..ac6e8c4 100644
--- a/include/configs/zynq_cse.h
+++ b/include/configs/zynq_cse.h

@@ -14,9 +14,9 @@
 /* Undef unneeded configs */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 
-#undef CONFIG_SYS_INIT_RAM_ADDR
-#undef CONFIG_SYS_INIT_RAM_SIZE
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFDE000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#undef CFG_SYS_INIT_RAM_ADDR
+#undef CFG_SYS_INIT_RAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR	0xFFFDE000
+#define CFG_SYS_INIT_RAM_SIZE	0x1000
 
 #endif /* __CONFIG_ZYNQ_CSE_H */

diff --git a/include/dm/platform_data/lpc32xx_hsuart.h b/include/dm/platform_data/lpc32xx_hsuart.h
deleted file mode 100644
index 6f41e0e73..0000000
--- a/include/dm/platform_data/lpc32xx_hsuart.h
+++ /dev/null

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef _LPC32XX_HSUART_PLAT_H
-#define _LPC32XX_HSUART_PLAT_H
-
-/**
- * struct lpc32xx_hsuart_plat - NXP LPC32xx HSUART platform data
- *
- * @base:               Base register address
- */
-struct lpc32xx_hsuart_plat {
-	unsigned long base;
-};
-
-#endif

diff --git a/include/e500.h b/include/e500.h
index 255f46b..9f68a83 100644
--- a/include/e500.h
+++ b/include/e500.h

@@ -19,7 +19,7 @@
 	unsigned long freq_localbus;
 	unsigned long freq_qe;
 #ifdef CONFIG_SYS_DPAA_FMAN
-	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+	unsigned long freq_fman[CFG_SYS_NUM_FMAN];
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	unsigned long freq_qman;

diff --git a/include/fm_eth.h b/include/fm_eth.h
index 7475b51..aeb6409 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h

@@ -56,7 +56,7 @@
 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR	(CFG_SYS_FSL_FM1_ADDR + 0xfc000)
 #endif
 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CFG_SYS_FSL_FM1_ADDR + 0xfd000)
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR	(CFG_SYS_FSL_FM2_ADDR + 0xfc000)
 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR	(CFG_SYS_FSL_FM2_ADDR + 0xfd000)
 #endif
@@ -102,7 +102,7 @@
 				 offsetof(struct ccsr_fman, memac[n-1]),\
 }
 #else
-#if (CONFIG_SYS_NUM_FMAN == 2)
+#if (CFG_SYS_NUM_FMAN == 2)
 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
 {									\
 	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)	\
@@ -131,7 +131,7 @@
 #endif
 #endif
 
-#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
+#if (CFG_SYS_NUM_FM1_10GEC >= 3)
 #define FM_TGEC_INFO_INITIALIZER2(idx, n) \
 {									\
 	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\

diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index 07a46a4..c701dc1 100644
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h

@@ -66,7 +66,7 @@
 int get_dpl_apply_status(void);
 int is_lazy_dpl_addr_valid(void);
 void fdt_fixup_mc_ddr(u64 *base, u64 *size);
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 int get_aiop_apply_status(void);
 #endif
 u64 mc_get_dram_addr(void);

diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index 9f243cd..de1e70a 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h

@@ -801,7 +801,7 @@
 #define IFC_RREGS_64KOFFSET	(64*1024)
 
 #define IFC_FCM_BASE_ADDR \
-	((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
+	((struct fsl_ifc_fcm *)CFG_SYS_IFC_ADDR)
 
 #define get_ifc_cspr_ext(i)	\
 		(ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))

diff --git a/include/i2c.h b/include/i2c.h
index e0ee94e..51390f8 100644
--- a/include/i2c.h
+++ b/include/i2c.h

@@ -633,19 +633,19 @@
  */
 #define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */
 
-#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
+#if !defined(CFG_SYS_I2C_MAX_HOPS)
 /* no muxes used bus = i2c adapters */
 #define CONFIG_SYS_I2C_DIRECT_BUS	1
-#define CONFIG_SYS_I2C_MAX_HOPS		0
-#define CONFIG_SYS_NUM_I2C_BUSES	ll_entry_count(struct i2c_adapter, i2c)
+#define CFG_SYS_I2C_MAX_HOPS		0
+#define CFG_SYS_NUM_I2C_BUSES	ll_entry_count(struct i2c_adapter, i2c)
 #else
 /* we use i2c muxes */
 #undef CONFIG_SYS_I2C_DIRECT_BUS
 #endif
 
 /* define the I2C bus number for RTC and DTT if not already done */
-#if !defined(CONFIG_SYS_RTC_BUS_NUM)
-#define CONFIG_SYS_RTC_BUS_NUM		0
+#if !defined(CFG_SYS_RTC_BUS_NUM)
+#define CFG_SYS_RTC_BUS_NUM		0
 #endif
 
 struct i2c_adapter {
@@ -705,7 +705,7 @@
 
 struct i2c_bus_hose {
 	int	adapter;
-	struct i2c_next_hop	next_hop[CONFIG_SYS_I2C_MAX_HOPS];
+	struct i2c_next_hop	next_hop[CFG_SYS_I2C_MAX_HOPS];
 };
 #define I2C_NULL_HOP	{{-1, ""}, 0, 0}
 extern struct i2c_bus_hose	i2c_bus[];
@@ -931,12 +931,12 @@
  * completely to new multibus support.
  */
 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
-# if !defined(CONFIG_SYS_MAX_I2C_BUS)
-#  define CONFIG_SYS_MAX_I2C_BUS		2
+# if !defined(CFG_SYS_MAX_I2C_BUS)
+#  define CFG_SYS_MAX_I2C_BUS		2
 # endif
 # define I2C_MULTI_BUS				1
 #else
-# define CONFIG_SYS_MAX_I2C_BUS		1
+# define CFG_SYS_MAX_I2C_BUS		1
 # define I2C_MULTI_BUS				0
 #endif
 

diff --git a/include/init.h b/include/init.h
index d40d11f..699dc24 100644
--- a/include/init.h
+++ b/include/init.h

@@ -90,8 +90,8 @@
  *
  * If this is not provided, a default implementation will try to set up a
  * single bank. It will do this if CONFIG_NR_DRAM_BANKS and
- * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
- * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
+ * CFG_SYS_SDRAM_BASE are set. The bank will have a start address of
+ * CFG_SYS_SDRAM_BASE and the size will be determined by a call to
  * get_effective_memsize().
  *
  * Return: 0 if OK, -ve on error

diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index 053b68a..636734d 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h

@@ -26,38 +26,38 @@
  * Define default values for some CCSR macros to make header files cleaner*
  *
  * To completely disable CCSR relocation in a board header file, define
- * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
- * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE.  This will force CFG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CFG_SYS_CCSRBAR.
  */
 
-#ifdef CONFIG_SYS_CCSRBAR_PHYS
-#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
-CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#ifdef CFG_SYS_CCSRBAR_PHYS
+#error "Do not define CFG_SYS_CCSRBAR_PHYS directly.  Use \
+CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead."
 #endif
 
 #if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE)
-#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#undef CFG_SYS_CCSRBAR_PHYS_HIGH
+#undef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_HIGH	0
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
+#ifndef CFG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#define CFG_SYS_CCSRBAR_PHYS_HIGH	0xf
 #else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#define CFG_SYS_CCSRBAR_PHYS_HIGH	0
 #endif
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
+#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
+#define CFG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
 #endif
 
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
-				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CFG_SYS_CCSRBAR_PHYS_LOW)
 
 #endif	/* __MPC85xx_H__ */

diff --git a/include/mpc86xx.h b/include/mpc86xx.h
index 9fe4748..ea8d17d 100644
--- a/include/mpc86xx.h
+++ b/include/mpc86xx.h

@@ -16,9 +16,9 @@
  * platform register addresses
  */
 
-#define GUTS_SVR	(CONFIG_SYS_CCSRBAR + 0xE00A4)
-#define MCM_ABCR	(CONFIG_SYS_CCSRBAR + 0x01000)
-#define MCM_DBCR	(CONFIG_SYS_CCSRBAR + 0x01008)
+#define GUTS_SVR	(CFG_SYS_CCSRBAR + 0xE00A4)
+#define MCM_ABCR	(CFG_SYS_CCSRBAR + 0x01000)
+#define MCM_DBCR	(CFG_SYS_CCSRBAR + 0x01008)
 
 /*
  * l2cr values.  Look in config_<BOARD>.h for the actual setup

diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h
index 1321da1..52cd1c4 100644
--- a/include/mtd/cfi_flash.h
+++ b/include/mtd/cfi_flash.h

@@ -147,8 +147,8 @@
 	u8	minor_version;
 } __attribute__((packed));
 
-#ifndef CONFIG_SYS_FLASH_BANKS_LIST
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#ifndef CFG_SYS_FLASH_BANKS_LIST
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
 #endif
 
 /*

diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h
index e75c3fa..0f6f5c2 100644
--- a/include/mvebu_mmc.h
+++ b/include/mvebu_mmc.h

@@ -21,7 +21,7 @@
 
 #define MVEBU_MMC_CLOCKRATE_MAX			50000000
 #define MVEBU_MMC_BASE_DIV_MAX			0x7ff
-#define MVEBU_MMC_BASE_FAST_CLOCK		CONFIG_SYS_TCLK
+#define MVEBU_MMC_BASE_FAST_CLOCK		CFG_SYS_TCLK
 #define MVEBU_MMC_BASE_FAST_CLK_100		100000000
 #define MVEBU_MMC_BASE_FAST_CLK_200		200000000
 

diff --git a/include/ns16550.h b/include/ns16550.h
index 3d9002d..0ee5c4d 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h

@@ -26,7 +26,7 @@
 
 #include <linux/types.h>
 
-#ifdef CONFIG_DM_SERIAL
+#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE)
 /*
  * For driver model we always use one byte per register, and sort out the
  * differences in the driver

diff --git a/include/post.h b/include/post.h
index ec03556..e68d5c8 100644
--- a/include/post.h
+++ b/include/post.h

@@ -16,7 +16,7 @@
 
 #if defined(CONFIG_POST)
 
-#ifndef CONFIG_POST_EXTERNAL_WORD_FUNCS
+#ifndef CFG_POST_EXTERNAL_WORD_FUNCS
 #ifdef CONFIG_SYS_POST_WORD_ADDR
 #define _POST_WORD_ADDR	CONFIG_SYS_POST_WORD_ADDR
 #else
@@ -51,7 +51,7 @@
 extern ulong post_word_load(void);
 extern void post_word_store(ulong value);
 
-#endif /* CONFIG_POST_EXTERNAL_WORD_FUNCS */
+#endif /* CFG_POST_EXTERNAL_WORD_FUNCS */
 #endif /* defined (CONFIG_POST) */
 #endif /* __ASSEMBLY__ */
 
@@ -142,7 +142,7 @@
 
 #define CONFIG_SYS_POST_RTC		0x00000001
 #define CONFIG_SYS_POST_WATCHDOG	0x00000002
-#define CONFIG_SYS_POST_MEMORY		0x00000004
+#define CFG_SYS_POST_MEMORY		0x00000004
 #define CONFIG_SYS_POST_CPU		0x00000008
 #define CONFIG_SYS_POST_I2C		0x00000010
 #define CONFIG_SYS_POST_CACHE		0x00000020
@@ -163,7 +163,7 @@
 #define CONFIG_SYS_POST_CODEC		0x00200000
 #define CONFIG_SYS_POST_COPROC		0x00400000
 #define CONFIG_SYS_POST_FLASH		0x00800000
-#define CONFIG_SYS_POST_MEM_REGIONS	0x01000000
+#define CFG_SYS_POST_MEM_REGIONS	0x01000000
 
 #endif /* CONFIG_POST */
 

diff --git a/include/serial.h b/include/serial.h
index fe01bcf..f4d7dc5 100644
--- a/include/serial.h
+++ b/include/serial.h

@@ -14,7 +14,7 @@
 	int	(*tstc)(void);
 	void	(*putc)(const char c);
 	void	(*puts)(const char *s);
-#if CONFIG_POST & CONFIG_SYS_POST_UART
+#if CFG_POST & CONFIG_SYS_POST_UART
 	void	(*loop)(int);
 #endif
 	struct serial_device	*next;
@@ -242,7 +242,7 @@
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*clear)(struct udevice *dev);
-#if CONFIG_POST & CONFIG_SYS_POST_UART
+#if CFG_POST & CONFIG_SYS_POST_UART
 	/**
 	 * loop() - Control serial device loopback mode
 	 *

diff --git a/include/spl.h b/include/spl.h
index 3eb27de..fb8c279 100644
--- a/include/spl.h
+++ b/include/spl.h

@@ -470,7 +470,7 @@
  * spl_set_header_raw_uboot() - Set up a standard SPL image structure
  *
  * This sets up the given spl_image which the standard values obtained from
- * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START,
+ * config options: CONFIG_SYS_MONITOR_LEN, CFG_SYS_UBOOT_START,
  * CONFIG_TEXT_BASE.
  *
  * @spl_image: Image description to set up

diff --git a/include/system-constants.h b/include/system-constants.h
index 83b41b3..0d6b71b 100644
--- a/include/system-constants.h
+++ b/include/system-constants.h

@@ -12,10 +12,10 @@
 #define SYS_INIT_SP_ADDR	CONFIG_CUSTOM_SYS_INIT_SP_ADDR
 #else
 #ifdef CONFIG_MIPS
-#define SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET)
+#define SYS_INIT_SP_ADDR	(CFG_SYS_SDRAM_BASE + CFG_SYS_INIT_SP_OFFSET)
 #else
 #define SYS_INIT_SP_ADDR	\
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+	(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #endif
 #endif
 

diff --git a/include/tca642x.h b/include/tca642x.h
index bda86c1..c0a3cef 100644
--- a/include/tca642x.h
+++ b/include/tca642x.h

@@ -41,13 +41,13 @@
 #define TCA642X_DIR_IN		1
 
 /* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_TCA642X_ADDR
-#define CONFIG_SYS_I2C_TCA642X_ADDR	(~0)
+#ifndef CFG_SYS_I2C_TCA642X_ADDR
+#define CFG_SYS_I2C_TCA642X_ADDR	(~0)
 #endif
 
 /* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM
-#define CONFIG_SYS_I2C_TCA642X_BUS_NUM	(0)
+#ifndef CFG_SYS_I2C_TCA642X_BUS_NUM
+#define CFG_SYS_I2C_TCA642X_BUS_NUM	(0)
 #endif
 
 struct tca642x_bank_info {

diff --git a/include/tsec.h b/include/tsec.h
index 72f3485..de279b2 100644
--- a/include/tsec.h
+++ b/include/tsec.h

@@ -124,8 +124,8 @@
 
 #define RCTRL_PROM		0x00000008
 
-#ifndef CONFIG_SYS_TBIPA_VALUE
-# define CONFIG_SYS_TBIPA_VALUE	0x1f
+#ifndef CFG_SYS_TBIPA_VALUE
+# define CFG_SYS_TBIPA_VALUE	0x1f
 #endif
 
 #define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN

diff --git a/lib/Kconfig b/lib/Kconfig
index 6abe1d0..c39fc52 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig

@@ -15,6 +15,9 @@
 	help
 	  Sets the number of entries in the virtual-physical mapping table.
 
+config SYS_TIMER_COUNTS_DOWN
+	bool "System timer counts down rathe than up"
+
 config PHYSMEM
 	bool "Access to physical memory region (> 4G)"
 	help

diff --git a/lib/time.c b/lib/time.c
index f3aaf47..8235026 100644
--- a/lib/time.c
+++ b/lib/time.c

@@ -25,21 +25,21 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_SYS_TIMER_RATE
+#ifdef CFG_SYS_TIMER_RATE
 /* Returns tick rate in ticks per second */
 ulong notrace get_tbclk(void)
 {
-	return CONFIG_SYS_TIMER_RATE;
+	return CFG_SYS_TIMER_RATE;
 }
 #endif
 
-#ifdef CONFIG_SYS_TIMER_COUNTER
+#ifdef CFG_SYS_TIMER_COUNTER
 unsigned long notrace timer_read_counter(void)
 {
 #ifdef CONFIG_SYS_TIMER_COUNTS_DOWN
-	return ~readl(CONFIG_SYS_TIMER_COUNTER);
+	return ~readl(CFG_SYS_TIMER_COUNTER);
 #else
-	return readl(CONFIG_SYS_TIMER_COUNTER);
+	return readl(CFG_SYS_TIMER_COUNTER);
 #endif
 }
 
@@ -47,8 +47,8 @@
 {
 	ulong count = timer_read_counter();
 
-#ifdef CONFIG_SYS_TIMER_RATE
-	const ulong timer_rate = CONFIG_SYS_TIMER_RATE;
+#ifdef CFG_SYS_TIMER_RATE
+	const ulong timer_rate = CFG_SYS_TIMER_RATE;
 
 	if (timer_rate == 1000000)
 		return count;

diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c
index edd7411..45263e6 100644
--- a/post/cpu/mpc83xx/ecc.c
+++ b/post/cpu/mpc83xx/ecc.c

@@ -17,7 +17,7 @@
 #include <asm/io.h>
 #include <post.h>
 
-#if CONFIG_POST & CONFIG_SYS_POST_ECC
+#if CFG_POST & CONFIG_SYS_POST_ECC
 /*
  * We use the RAW I/O accessors where possible in order to
  * achieve performance goal, since the test's execution time

diff --git a/post/drivers/flash.c b/post/drivers/flash.c
index 7d65f46..e157d36 100644
--- a/post/drivers/flash.c
+++ b/post/drivers/flash.c

@@ -6,7 +6,7 @@
  * Licensed under the GPL-2 or later.
  */
 
-#if CONFIG_POST & CONFIG_SYS_POST_FLASH
+#if CFG_POST & CONFIG_SYS_POST_FLASH
 #include <common.h>
 #include <malloc.h>
 #include <post.h>

diff --git a/post/drivers/i2c.c b/post/drivers/i2c.c
index 3b37892..057454f 100644
--- a/post/drivers/i2c.c
+++ b/post/drivers/i2c.c

@@ -26,7 +26,7 @@
 #include <post.h>
 #include <i2c.h>
 
-#if CONFIG_POST & CONFIG_SYS_POST_I2C
+#if CFG_POST & CONFIG_SYS_POST_I2C
 
 static int i2c_ignore_device(unsigned int chip)
 {
@@ -94,4 +94,4 @@
 #endif
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_I2C */
+#endif /* CFG_POST & CONFIG_SYS_POST_I2C */

diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index d249942..1be2b41 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c

@@ -138,7 +138,7 @@
 #include <post.h>
 #include <watchdog.h>
 
-#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS)
+#if CFG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -467,7 +467,7 @@
 {
 	struct bd_info *bd = gd->bd;
 
-	*vstart = CONFIG_SYS_SDRAM_BASE;
+	*vstart = CFG_SYS_SDRAM_BASE;
 	*size = (gd->ram_size >= 256 << 20 ?
 			256 << 20 : gd->ram_size) - (1 << 20);
 
@@ -535,4 +535,4 @@
 	return ret;
 }
 
-#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */
+#endif /* CFG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */

diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c
index c603f0e..cfed56b 100644
--- a/post/drivers/rtc.c
+++ b/post/drivers/rtc.c

@@ -26,7 +26,7 @@
 #include <post.h>
 #include <rtc.h>
 
-#if CONFIG_POST & CONFIG_SYS_POST_RTC
+#if CFG_POST & CONFIG_SYS_POST_RTC
 
 static int rtc_post_skip (ulong * diff)
 {
@@ -189,4 +189,4 @@
 	return 0;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_RTC */
+#endif /* CFG_POST & CONFIG_SYS_POST_RTC */

diff --git a/post/lib_powerpc/andi.c b/post/lib_powerpc/andi.c
index d4f60aa..d69d613 100644
--- a/post/lib_powerpc/andi.c
+++ b/post/lib_powerpc/andi.c

@@ -19,7 +19,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
 extern ulong cpu_post_makecr (long v);

diff --git a/post/lib_powerpc/asm.S b/post/lib_powerpc/asm.S
index 91b5999..13302d7 100644
--- a/post/lib_powerpc/asm.S
+++ b/post/lib_powerpc/asm.S

@@ -10,7 +10,7 @@
 #include <ppc_defs.h>
 #include <asm/cache.h>
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 /* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
 	.global	cpu_post_exec_02

diff --git a/post/lib_powerpc/b.c b/post/lib_powerpc/b.c
index 0b02e91..eb9371f 100644
--- a/post/lib_powerpc/b.c
+++ b/post/lib_powerpc/b.c

@@ -24,7 +24,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1);
 extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,

diff --git a/post/lib_powerpc/cmp.c b/post/lib_powerpc/cmp.c
index e708697..e4d0931 100644
--- a/post/lib_powerpc/cmp.c
+++ b/post/lib_powerpc/cmp.c

@@ -23,7 +23,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2);
 

diff --git a/post/lib_powerpc/cmpi.c b/post/lib_powerpc/cmpi.c
index 85a9b0a..983892d 100644
--- a/post/lib_powerpc/cmpi.c
+++ b/post/lib_powerpc/cmpi.c

@@ -23,7 +23,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1);
 

diff --git a/post/lib_powerpc/complex.c b/post/lib_powerpc/complex.c
index bb29e91..d2ec21b 100644
--- a/post/lib_powerpc/complex.c
+++ b/post/lib_powerpc/complex.c

@@ -18,7 +18,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n);
 extern int cpu_post_complex_2_asm (int x, int n);

diff --git a/post/lib_powerpc/cpu.c b/post/lib_powerpc/cpu.c
index 1d47107..77c2538 100644
--- a/post/lib_powerpc/cpu.c
+++ b/post/lib_powerpc/cpu.c

@@ -20,7 +20,7 @@
 #include <post.h>
 #include <asm/mmu.h>
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern int cpu_post_test_cmp (void);
 extern int cpu_post_test_cmpi (void);
@@ -118,4 +118,4 @@
 	return ret;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */
+#endif /* CFG_POST & CONFIG_SYS_POST_CPU */

diff --git a/post/lib_powerpc/cr.c b/post/lib_powerpc/cr.c
index 56ed355..077fb0f 100644
--- a/post/lib_powerpc/cr.c
+++ b/post/lib_powerpc/cr.c

@@ -33,7 +33,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1);
 extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3);

diff --git a/post/lib_powerpc/fpu/20001122-1.c b/post/lib_powerpc/fpu/20001122-1.c
index 4b452dc..eddd3f9 100644
--- a/post/lib_powerpc/fpu/20001122-1.c
+++ b/post/lib_powerpc/fpu/20001122-1.c

@@ -13,7 +13,7 @@
 
 GNU_FPOST_ATTR
 
-#if CONFIG_POST & CONFIG_SYS_POST_FPU
+#if CFG_POST & CONFIG_SYS_POST_FPU
 
 int fpu_post_test_math1 (void)
 {
@@ -40,4 +40,4 @@
 	return 0;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */
+#endif /* CFG_POST & CONFIG_SYS_POST_FPU */

diff --git a/post/lib_powerpc/fpu/20010114-2.c b/post/lib_powerpc/fpu/20010114-2.c
index 4aadd1e..9e3e546 100644
--- a/post/lib_powerpc/fpu/20010114-2.c
+++ b/post/lib_powerpc/fpu/20010114-2.c

@@ -13,7 +13,7 @@
 
 GNU_FPOST_ATTR
 
-#if CONFIG_POST & CONFIG_SYS_POST_FPU
+#if CFG_POST & CONFIG_SYS_POST_FPU
 
 static float rintf (float x)
 {
@@ -45,4 +45,4 @@
 	return 0;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */
+#endif /* CFG_POST & CONFIG_SYS_POST_FPU */

diff --git a/post/lib_powerpc/fpu/20010226-1.c b/post/lib_powerpc/fpu/20010226-1.c
index b09a25c..5bb3860 100644
--- a/post/lib_powerpc/fpu/20010226-1.c
+++ b/post/lib_powerpc/fpu/20010226-1.c

@@ -13,7 +13,7 @@
 
 GNU_FPOST_ATTR
 
-#if CONFIG_POST & CONFIG_SYS_POST_FPU
+#if CFG_POST & CONFIG_SYS_POST_FPU
 
 int fpu_post_test_math3 (void)
 {
@@ -33,4 +33,4 @@
 	return 0;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */
+#endif /* CFG_POST & CONFIG_SYS_POST_FPU */

diff --git a/post/lib_powerpc/fpu/980619-1.c b/post/lib_powerpc/fpu/980619-1.c
index 2fea708..415cd50 100644
--- a/post/lib_powerpc/fpu/980619-1.c
+++ b/post/lib_powerpc/fpu/980619-1.c

@@ -13,7 +13,7 @@
 
 GNU_FPOST_ATTR
 
-#if CONFIG_POST & CONFIG_SYS_POST_FPU
+#if CFG_POST & CONFIG_SYS_POST_FPU
 
 int fpu_post_test_math4 (void)
 {
@@ -39,4 +39,4 @@
 	return 0;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */
+#endif /* CFG_POST & CONFIG_SYS_POST_FPU */

diff --git a/post/lib_powerpc/fpu/acc1.c b/post/lib_powerpc/fpu/acc1.c
index 9e5783b..4cf3b7c 100644
--- a/post/lib_powerpc/fpu/acc1.c
+++ b/post/lib_powerpc/fpu/acc1.c

@@ -13,7 +13,7 @@
 
 GNU_FPOST_ATTR
 
-#if CONFIG_POST & CONFIG_SYS_POST_FPU
+#if CFG_POST & CONFIG_SYS_POST_FPU
 
 static double func (const double *array)
 {
@@ -36,4 +36,4 @@
 	return 0;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */
+#endif /* CFG_POST & CONFIG_SYS_POST_FPU */

diff --git a/post/lib_powerpc/fpu/compare-fp-1.c b/post/lib_powerpc/fpu/compare-fp-1.c
index d46a13a..029600f 100644
--- a/post/lib_powerpc/fpu/compare-fp-1.c
+++ b/post/lib_powerpc/fpu/compare-fp-1.c

@@ -15,7 +15,7 @@
 
 GNU_FPOST_ATTR
 
-#if CONFIG_POST & CONFIG_SYS_POST_FPU
+#if CFG_POST & CONFIG_SYS_POST_FPU
 
 static int failed;
 
@@ -204,4 +204,4 @@
 	return 0;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */
+#endif /* CFG_POST & CONFIG_SYS_POST_FPU */

diff --git a/post/lib_powerpc/fpu/fpu.c b/post/lib_powerpc/fpu/fpu.c
index bd65f62..8993b36 100644
--- a/post/lib_powerpc/fpu/fpu.c
+++ b/post/lib_powerpc/fpu/fpu.c

@@ -21,7 +21,7 @@
 
 GNU_FPOST_ATTR
 
-#if CONFIG_POST & CONFIG_SYS_POST_FPU
+#if CFG_POST & CONFIG_SYS_POST_FPU
 
 #include <watchdog.h>
 
@@ -71,4 +71,4 @@
 	return ret;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */
+#endif /* CFG_POST & CONFIG_SYS_POST_FPU */

diff --git a/post/lib_powerpc/fpu/mul-subnormal-single-1.c b/post/lib_powerpc/fpu/mul-subnormal-single-1.c
index cb61c91..87b882c6 100644
--- a/post/lib_powerpc/fpu/mul-subnormal-single-1.c
+++ b/post/lib_powerpc/fpu/mul-subnormal-single-1.c

@@ -15,7 +15,7 @@
 
 GNU_FPOST_ATTR
 
-#if CONFIG_POST & CONFIG_SYS_POST_FPU
+#if CFG_POST & CONFIG_SYS_POST_FPU
 
 union uf
 {
@@ -82,4 +82,4 @@
 	return 0;
 }
 
-#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */
+#endif /* CFG_POST & CONFIG_SYS_POST_FPU */

diff --git a/post/lib_powerpc/load.c b/post/lib_powerpc/load.c
index 5269563..ece0b27 100644
--- a/post/lib_powerpc/load.c
+++ b/post/lib_powerpc/load.c

@@ -28,7 +28,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3);
 extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2);

diff --git a/post/lib_powerpc/multi.c b/post/lib_powerpc/multi.c
index f082e4c..0e9ee88 100644
--- a/post/lib_powerpc/multi.c
+++ b/post/lib_powerpc/multi.c

@@ -21,7 +21,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_02(ulong *code, ulong op1, ulong op2);
 

diff --git a/post/lib_powerpc/rlwimi.c b/post/lib_powerpc/rlwimi.c
index 7b4dc79..d24a3f6 100644
--- a/post/lib_powerpc/rlwimi.c
+++ b/post/lib_powerpc/rlwimi.c

@@ -19,7 +19,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
     ulong op2);

diff --git a/post/lib_powerpc/rlwinm.c b/post/lib_powerpc/rlwinm.c
index 8a03e9b..9f4a3ed 100644
--- a/post/lib_powerpc/rlwinm.c
+++ b/post/lib_powerpc/rlwinm.c

@@ -19,7 +19,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
 extern ulong cpu_post_makecr (long v);

diff --git a/post/lib_powerpc/rlwnm.c b/post/lib_powerpc/rlwnm.c
index e2beb4e..224e6bd 100644
--- a/post/lib_powerpc/rlwnm.c
+++ b/post/lib_powerpc/rlwnm.c

@@ -19,7 +19,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
     ulong op2);

diff --git a/post/lib_powerpc/srawi.c b/post/lib_powerpc/srawi.c
index d4a8fab..713d4f2 100644
--- a/post/lib_powerpc/srawi.c
+++ b/post/lib_powerpc/srawi.c

@@ -19,7 +19,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
 extern ulong cpu_post_makecr (long v);

diff --git a/post/lib_powerpc/store.c b/post/lib_powerpc/store.c
index 8e278fe..2dbcccf 100644
--- a/post/lib_powerpc/store.c
+++ b/post/lib_powerpc/store.c

@@ -28,7 +28,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3);
 extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2);

diff --git a/post/lib_powerpc/string.c b/post/lib_powerpc/string.c
index 0d8d280..9b54847 100644
--- a/post/lib_powerpc/string.c
+++ b/post/lib_powerpc/string.c

@@ -20,7 +20,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2);
 extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3,

diff --git a/post/lib_powerpc/three.c b/post/lib_powerpc/three.c
index fc6f1f5..55f0ff8 100644
--- a/post/lib_powerpc/three.c
+++ b/post/lib_powerpc/three.c

@@ -22,7 +22,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
     ulong op2);

diff --git a/post/lib_powerpc/threei.c b/post/lib_powerpc/threei.c
index f49c85e..ec52d23 100644
--- a/post/lib_powerpc/threei.c
+++ b/post/lib_powerpc/threei.c

@@ -21,7 +21,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
 extern ulong cpu_post_makecr (long v);

diff --git a/post/lib_powerpc/threex.c b/post/lib_powerpc/threex.c
index 6bc5a54..6f5f0b8 100644
--- a/post/lib_powerpc/threex.c
+++ b/post/lib_powerpc/threex.c

@@ -22,7 +22,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
     ulong op2);

diff --git a/post/lib_powerpc/two.c b/post/lib_powerpc/two.c
index fa376c7..b44dd4e 100644
--- a/post/lib_powerpc/two.c
+++ b/post/lib_powerpc/two.c

@@ -22,7 +22,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
 extern ulong cpu_post_makecr (long v);

diff --git a/post/lib_powerpc/twox.c b/post/lib_powerpc/twox.c
index 5c36012..320cc0a 100644
--- a/post/lib_powerpc/twox.c
+++ b/post/lib_powerpc/twox.c

@@ -22,7 +22,7 @@
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
 extern ulong cpu_post_makecr (long v);

diff --git a/post/post.c b/post/post.c
index b81425d..9964b41 100644
--- a/post/post.c
+++ b/post/post.c

@@ -168,7 +168,7 @@
 	post_word_store(word);
 }
 
-#ifndef CONFIG_POST_SKIP_ENV_FLAGS
+#ifndef CFG_POST_SKIP_ENV_FLAGS
 static void post_get_env_flags(int *test_flags)
 {
 	int  flag[] = {  POST_POWERON,   POST_NORMAL,   POST_SLOWTEST,
@@ -227,7 +227,7 @@
 	for (j = 0; j < post_list_size; j++)
 		test_flags[j] = post_list[j].flags;
 
-#ifndef CONFIG_POST_SKIP_ENV_FLAGS
+#ifndef CFG_POST_SKIP_ENV_FLAGS
 	post_get_env_flags(test_flags);
 #endif
 

diff --git a/post/tests.c b/post/tests.c
index 5c019b6..d61ea74 100644
--- a/post/tests.c
+++ b/post/tests.c

@@ -45,7 +45,7 @@
 
 struct post_test post_list[] =
 {
-#if CONFIG_POST & CONFIG_SYS_POST_OCM
+#if CFG_POST & CONFIG_SYS_POST_OCM
     {
 	"OCM test",
 	"ocm",
@@ -57,7 +57,7 @@
 	CONFIG_SYS_POST_OCM
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_CACHE
+#if CFG_POST & CONFIG_SYS_POST_CACHE
     {
 	"Cache test",
 	"cache",
@@ -69,9 +69,9 @@
 	CONFIG_SYS_POST_CACHE
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
-#if defined(CONFIG_POST_WATCHDOG)
-	CONFIG_POST_WATCHDOG,
+#if CFG_POST & CONFIG_SYS_POST_WATCHDOG
+#if defined(CFG_POST_WATCHDOG)
+	CFG_POST_WATCHDOG,
 #else
     {
 	"Watchdog timer test",
@@ -85,7 +85,7 @@
     },
 #endif
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_I2C
+#if CFG_POST & CONFIG_SYS_POST_I2C
     {
 	"I2C test",
 	"i2c",
@@ -97,7 +97,7 @@
 	CONFIG_SYS_POST_I2C
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_RTC
+#if CFG_POST & CONFIG_SYS_POST_RTC
     {
 	"RTC test",
 	"rtc",
@@ -109,7 +109,7 @@
 	CONFIG_SYS_POST_RTC
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+#if CFG_POST & CFG_SYS_POST_MEMORY
     {
 	"Memory test",
 	"memory",
@@ -118,10 +118,10 @@
 	&memory_post_test,
 	NULL,
 	NULL,
-	CONFIG_SYS_POST_MEMORY
+	CFG_SYS_POST_MEMORY
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_CPU
+#if CFG_POST & CONFIG_SYS_POST_CPU
     {
 	"CPU test",
 	"cpu",
@@ -134,7 +134,7 @@
 	CONFIG_SYS_POST_CPU
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_FPU
+#if CFG_POST & CONFIG_SYS_POST_FPU
     {
 	"FPU test",
 	"fpu",
@@ -147,9 +147,9 @@
 	CONFIG_SYS_POST_FPU
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_UART
-#if defined(CONFIG_POST_UART)
-	CONFIG_POST_UART,
+#if CFG_POST & CONFIG_SYS_POST_UART
+#if defined(CFG_POST_UART)
+	CFG_POST_UART,
 #else
     {
 	"UART test",
@@ -161,9 +161,9 @@
 	NULL,
 	CONFIG_SYS_POST_UART
     },
-#endif /* CONFIG_POST_UART */
+#endif /* CFG_POST_UART */
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_ETHER
+#if CFG_POST & CONFIG_SYS_POST_ETHER
     {
 	"ETHERNET test",
 	"ethernet",
@@ -175,7 +175,7 @@
 	CONFIG_SYS_POST_ETHER
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_USB
+#if CFG_POST & CONFIG_SYS_POST_USB
     {
 	"USB test",
 	"usb",
@@ -187,7 +187,7 @@
 	CONFIG_SYS_POST_USB
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_SPR
+#if CFG_POST & CONFIG_SYS_POST_SPR
     {
 	"SPR test",
 	"spr",
@@ -199,7 +199,7 @@
 	CONFIG_SYS_POST_SPR
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_SYSMON
+#if CFG_POST & CONFIG_SYS_POST_SYSMON
     {
 	"SYSMON test",
 	"sysmon",
@@ -211,7 +211,7 @@
 	CONFIG_SYS_POST_SYSMON
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_DSP
+#if CFG_POST & CONFIG_SYS_POST_DSP
     {
 	"DSP test",
 	"dsp",
@@ -223,7 +223,7 @@
 	CONFIG_SYS_POST_DSP
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_CODEC
+#if CFG_POST & CONFIG_SYS_POST_CODEC
     {
 	"CODEC test",
 	"codec",
@@ -235,7 +235,7 @@
 	CONFIG_SYS_POST_CODEC
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_ECC
+#if CFG_POST & CONFIG_SYS_POST_ECC
     {
 	"ECC test",
 	"ecc",
@@ -247,22 +247,22 @@
 	CONFIG_SYS_POST_ECC
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
-	CONFIG_POST_BSPEC1,
+#if CFG_POST & CONFIG_SYS_POST_BSPEC1
+	CFG_POST_BSPEC1,
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
-	CONFIG_POST_BSPEC2,
+#if CFG_POST & CONFIG_SYS_POST_BSPEC2
+	CFG_POST_BSPEC2,
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
-	CONFIG_POST_BSPEC3,
+#if CFG_POST & CONFIG_SYS_POST_BSPEC3
+	CFG_POST_BSPEC3,
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
-	CONFIG_POST_BSPEC4,
+#if CFG_POST & CONFIG_SYS_POST_BSPEC4
+	CFG_POST_BSPEC4,
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5
-	CONFIG_POST_BSPEC5,
+#if CFG_POST & CONFIG_SYS_POST_BSPEC5
+	CFG_POST_BSPEC5,
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_COPROC
+#if CFG_POST & CONFIG_SYS_POST_COPROC
     {
 	"Coprocessors communication test",
 	"coproc_com",
@@ -274,7 +274,7 @@
 	CONFIG_SYS_POST_COPROC
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_FLASH
+#if CFG_POST & CONFIG_SYS_POST_FLASH
     {
 	"Parallel NOR flash test",
 	"flash",
@@ -286,7 +286,7 @@
 	CONFIG_SYS_POST_FLASH
     },
 #endif
-#if CONFIG_POST & CONFIG_SYS_POST_MEM_REGIONS
+#if CFG_POST & CFG_SYS_POST_MEM_REGIONS
     {
 	"Memory regions test",
 	"mem_regions",
@@ -295,7 +295,7 @@
 	&memory_regions_post_test,
 	NULL,
 	NULL,
-	CONFIG_SYS_POST_MEM_REGIONS
+	CFG_SYS_POST_MEM_REGIONS
     },
 #endif
 };

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index c0f55e4..12c23a5 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt

@@ -1,5 +1,4 @@
 CONFIG_ARM_GIC_BASE_ADDRESS
-CONFIG_AUTO_ZRELADDR
 CONFIG_BOARDDIR
 CONFIG_DFU_ALT
 CONFIG_DFU_ALT_BOOT_EMMC
@@ -8,7 +7,6 @@
 CONFIG_DFU_ENV_SETTINGS
 CONFIG_DM9000_BASE
 CONFIG_DM9000_BYTE_SWAPPED
-CONFIG_DM9000_DEBUG
 CONFIG_DM9000_NO_SROM
 CONFIG_DM9000_USE_16BIT
 CONFIG_DW_WDT_CLOCK_KHZ
@@ -37,26 +35,18 @@
 CONFIG_FLASH_SPANSION_S29WS_N
 CONFIG_FLASH_VERIFY
 CONFIG_FM_PLAT_CLK_DIV
-CONFIG_FSL_CADMUS
 CONFIG_FSL_CPLD
-CONFIG_FSL_DEVICE_DISABLE
 CONFIG_FSL_ESDHC_PIN_MUX
 CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
-CONFIG_FSL_IIM
 CONFIG_FSL_ISBC_KEY_EXT
-CONFIG_FSL_LBC
 CONFIG_FSL_PMIC_BITLEN
 CONFIG_FSL_PMIC_BUS
 CONFIG_FSL_PMIC_CLK
 CONFIG_FSL_PMIC_CS
 CONFIG_FSL_PMIC_MODE
 CONFIG_FSL_SDHC_V2_3
-CONFIG_FSL_SERDES
 CONFIG_FSL_SERDES1
 CONFIG_FSL_SERDES2
-CONFIG_FTMAC100_BASE
-CONFIG_FTRTC010_EXTCLK
-CONFIG_FTRTC010_PCLK
 CONFIG_GATEWAYIP
 CONFIG_GMII
 CONFIG_G_DNL_THOR_PRODUCT_NUM
@@ -64,28 +54,17 @@
 CONFIG_G_DNL_UMS_PRODUCT_NUM
 CONFIG_G_DNL_UMS_VENDOR_NUM
 CONFIG_HDMI_ENCODER_I2C_ADDR
-CONFIG_HIKEY_GPIO
 CONFIG_HOSTNAME
 CONFIG_HSMMC2_8BIT
-CONFIG_HWCONFIG
 CONFIG_HW_ENV_SETTINGS
 CONFIG_I2C_ENV_EEPROM_BUS
 CONFIG_I2C_MULTI_BUS
 CONFIG_I2C_MVTWSI
-CONFIG_I2C_MVTWSI_BASE
 CONFIG_I2C_MVTWSI_BASE0
 CONFIG_I2C_MVTWSI_BASE1
 CONFIG_I2C_RTC_ADDR
 CONFIG_ICS307_REFCLK_HZ
-CONFIG_IMX
 CONFIG_IMX6_PWM_PER_CLK
-CONFIG_IMX_HDMI
-CONFIG_IMX_VIDEO_SKIP
-CONFIG_INTERRUPTS
-CONFIG_IODELAY_RECALIBRATION
-CONFIG_IOMUX_LPSR
-CONFIG_IOMUX_SHARE_CONF_REG
-CONFIG_IO_TRACE
 CONFIG_IPADDR
 CONFIG_IRAM_BASE
 CONFIG_IRAM_END
@@ -122,7 +101,6 @@
 CONFIG_LEGACY_BOOTCMD_ENV
 CONFIG_LOWPOWER_ADDR
 CONFIG_LOWPOWER_FLAG
-CONFIG_LPC32XX_HSUART
 CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY
 CONFIG_LPC32XX_NAND_MLC_NAND_TA
 CONFIG_LPC32XX_NAND_MLC_RD_HIGH
@@ -138,7 +116,6 @@
 CONFIG_LPC32XX_NAND_SLC_WHOLD
 CONFIG_LPC32XX_NAND_SLC_WSETUP
 CONFIG_LPC32XX_NAND_SLC_WWIDTH
-CONFIG_LS102XA_STREAM_ID
 CONFIG_MACB_SEARCH_PHY
 CONFIG_MALLOC_F_ADDR
 CONFIG_MALTA
@@ -149,20 +126,13 @@
 CONFIG_MEM_INIT_VALUE
 CONFIG_MFG_ENV_SETTINGS
 CONFIG_MII_DEFAULT_TSEC
-CONFIG_MISC_COMMON
 CONFIG_MIU_2BIT_21_7_INTERLEAVED
 CONFIG_MIU_2BIT_INTERLEAVED
 CONFIG_MMC_DEFAULT_DEV
 CONFIG_MMC_SUNXI_SLOT
 CONFIG_MONITOR_IS_IN_RAM
-CONFIG_MPC85XX_FEC
-CONFIG_MPC85XX_FEC_NAME
 CONFIG_MTD_NAND_VERIFY_WRITE
-CONFIG_MTD_PARTITION
 CONFIG_MVGBE_PORTS
-CONFIG_MVS
-CONFIG_MX27
-CONFIG_MX27_CLK32
 CONFIG_MXC_GPT_HCLK
 CONFIG_MXC_NAND_HWECC
 CONFIG_MXC_NAND_IP_REGS_BASE
@@ -171,27 +141,15 @@
 CONFIG_MXC_USB_FLAGS
 CONFIG_MXC_USB_PORT
 CONFIG_MXC_USB_PORTSC
-CONFIG_MXS
-CONFIG_MXS_OCOTP
 CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 CONFIG_NAND_CS_INIT
-CONFIG_NAND_ECC_BCH
-CONFIG_NAND_KIRKWOOD
-CONFIG_NAND_KMETER1
-CONFIG_NAND_OMAP_GPMC_WSCFG
-CONFIG_NAND_SECBOOT
-CONFIG_NAND_SPL
 CONFIG_NETDEV
 CONFIG_NETMASK
-CONFIG_NEVER_ASSERT_ODT_TO_CPU
-CONFIG_NOBQFMAN
 CONFIG_NORBOOT
-CONFIG_NS16550_MIN_FUNCTIONS
 CONFIG_NUM_DSP_CPUS
 CONFIG_ODROID_REV_AIN
 CONFIG_OTHBOOTARGS
 CONFIG_OVERWRITE_ETHADDR_ONCE
-CONFIG_PCA953X
 CONFIG_PCIE_IMX_PERST_GPIO
 CONFIG_PCIE_IMX_POWER_GPIO
 CONFIG_PEN_ADDR_BIG_ENDIAN
@@ -202,26 +160,13 @@
 CONFIG_PHY_IRAM_BASE
 CONFIG_PL011_CLOCK
 CONFIG_PL01x_PORTS
-CONFIG_PM
 CONFIG_PME_PLAT_CLK_DIV
 CONFIG_POST
 CONFIG_POSTBOOTMENU
 CONFIG_POST_EXTERNAL_WORD_FUNCS
-CONFIG_POST_SKIP_ENV_FLAGS
-CONFIG_POWER_FSL
-CONFIG_POWER_FSL_MC13892
-CONFIG_POWER_HI6553
-CONFIG_POWER_LTC3676
 CONFIG_POWER_LTC3676_I2C_ADDR
-CONFIG_POWER_PFUZE100
 CONFIG_POWER_PFUZE100_I2C_ADDR
-CONFIG_POWER_PFUZE3000
 CONFIG_POWER_PFUZE3000_I2C_ADDR
-CONFIG_POWER_SPI
-CONFIG_POWER_TPS62362
-CONFIG_POWER_TPS65090_EC
-CONFIG_POWER_TPS65218
-CONFIG_POWER_TPS65910
 CONFIG_PPC_SPINTABLE_COMPATIBLE
 CONFIG_PRAM
 CONFIG_PSRAM_SCFG
@@ -233,14 +178,6 @@
 CONFIG_RESET_VECTOR_ADDRESS
 CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
 CONFIG_ROOTPATH
-CONFIG_RTC_DS1337
-CONFIG_RTC_DS1337_NOOSC
-CONFIG_RTC_DS1338
-CONFIG_RTC_DS1374
-CONFIG_RTC_DS3231
-CONFIG_RTC_MC13XXX
-CONFIG_RTC_MXS
-CONFIG_RTC_PT7C4338
 CONFIG_SANDBOX_ARCH
 CONFIG_SANDBOX_SDL
 CONFIG_SANDBOX_SPI_MAX_BUS
@@ -251,7 +188,6 @@
 CONFIG_SCSI_DEV_LIST
 CONFIG_SC_TIMER_CLK
 CONFIG_SERIAL_BOOT
-CONFIG_SERIAL_SOFTWARE_FIFO
 CONFIG_SERVERIP
 CONFIG_SETUP_INITRD_TAG
 CONFIG_SET_DFU_ALT_BUF_LEN
@@ -260,701 +196,25 @@
 CONFIG_SH_ETHER_CACHE_WRITEBACK
 CONFIG_SH_ETHER_PHY_ADDR
 CONFIG_SH_ETHER_PHY_MODE
-CONFIG_SH_ETHER_SH7734_MII
 CONFIG_SH_ETHER_USE_PORT
-CONFIG_SH_GPIO_PFC
 CONFIG_SH_QSPI_BASE
 CONFIG_SLIC
 CONFIG_SMDK5420
 CONFIG_SMP_PEN_ADDR
-CONFIG_SMSC_LPC47M
-CONFIG_SMSC_SIO1007
 CONFIG_SOCRATES
-CONFIG_SOFT_I2C_READ_REPEATED_START
-CONFIG_SPD_EEPROM
 CONFIG_SPI_ADDR
 CONFIG_SPI_BOOTING
 CONFIG_SPI_FLASH_QUAD
 CONFIG_SPI_FLASH_SIZE
 CONFIG_SPI_HALF_DUPLEX
 CONFIG_SPI_N25Q256A_RESET
-CONFIG_SRIO1
-CONFIG_SRIO2
-CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
-CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1
-CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2
-CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
-CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
-CONFIG_SRIO_PCIE_BOOT_MASTER
-CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK
-CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
-CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
-CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
 CONFIG_STACKBASE
 CONFIG_STANDALONE_LOAD_ADDR
 CONFIG_STD_DEVICES_SETTINGS
-CONFIG_SYS_AMASK0
-CONFIG_SYS_AMASK1
-CONFIG_SYS_AMASK1_FINAL
-CONFIG_SYS_AMASK2
-CONFIG_SYS_AMASK2_FINAL
-CONFIG_SYS_AMASK3
-CONFIG_SYS_AMASK4
-CONFIG_SYS_AMASK6
-CONFIG_SYS_AMASK7
-CONFIG_SYS_AT91_MAIN_CLOCK
-CONFIG_SYS_AT91_PLLA
-CONFIG_SYS_AT91_PLLB
-CONFIG_SYS_AT91_SLOW_CLOCK
 CONFIG_SYS_BAUDRATE_TABLE
-CONFIG_SYS_BMAN_CENA_BASE
-CONFIG_SYS_BMAN_CENA_SIZE
-CONFIG_SYS_BMAN_CINH_BASE
-CONFIG_SYS_BMAN_CINH_SIZE
-CONFIG_SYS_BMAN_MEM_BASE
-CONFIG_SYS_BMAN_MEM_PHYS
-CONFIG_SYS_BMAN_MEM_SIZE
-CONFIG_SYS_BMAN_NUM_PORTALS
-CONFIG_SYS_BMAN_SP_CENA_SIZE
-CONFIG_SYS_BMAN_SP_CINH_SIZE
-CONFIG_SYS_BMAN_SWP_ISDR_REG
-CONFIG_SYS_BOOTMAPSZ
-CONFIG_SYS_CACHE_ACR0
-CONFIG_SYS_CACHE_ACR1
-CONFIG_SYS_CACHE_ACR2
-CONFIG_SYS_CACHE_DCACR
-CONFIG_SYS_CACHE_ICACR
-CONFIG_SYS_CCSRBAR
-CONFIG_SYS_CCSRBAR_PHYS
-CONFIG_SYS_CCSRBAR_PHYS_HIGH
-CONFIG_SYS_CCSRBAR_PHYS_LOW
-CONFIG_SYS_CLK
-CONFIG_SYS_CLKTL_CBCDR
-CONFIG_SYS_CPLD_AMASK
-CONFIG_SYS_CPLD_BASE
-CONFIG_SYS_CPLD_BASE_PHYS
-CONFIG_SYS_CPLD_CSOR
-CONFIG_SYS_CPLD_CSPR
-CONFIG_SYS_CPLD_CSPR_EXT
-CONFIG_SYS_CPLD_FTIM0
-CONFIG_SYS_CPLD_FTIM1
-CONFIG_SYS_CPLD_FTIM2
-CONFIG_SYS_CPLD_FTIM3
-CONFIG_SYS_CPU_CLK
-CONFIG_SYS_CS0_BASE
-CONFIG_SYS_CS0_CTRL
-CONFIG_SYS_CS0_FTIM0
-CONFIG_SYS_CS0_FTIM1
-CONFIG_SYS_CS0_FTIM2
-CONFIG_SYS_CS0_FTIM3
-CONFIG_SYS_CS0_MASK
-CONFIG_SYS_CS1_BASE
-CONFIG_SYS_CS1_CTRL
-CONFIG_SYS_CS1_FTIM0
-CONFIG_SYS_CS1_FTIM1
-CONFIG_SYS_CS1_FTIM2
-CONFIG_SYS_CS1_FTIM3
-CONFIG_SYS_CS1_MASK
-CONFIG_SYS_CS2_BASE
-CONFIG_SYS_CS2_CTRL
-CONFIG_SYS_CS2_FTIM0
-CONFIG_SYS_CS2_FTIM1
-CONFIG_SYS_CS2_FTIM2
-CONFIG_SYS_CS2_FTIM3
-CONFIG_SYS_CS2_MASK
-CONFIG_SYS_CS3_BASE
-CONFIG_SYS_CS3_CTRL
-CONFIG_SYS_CS3_FTIM0
-CONFIG_SYS_CS3_FTIM1
-CONFIG_SYS_CS3_FTIM2
-CONFIG_SYS_CS3_FTIM3
-CONFIG_SYS_CS3_MASK
-CONFIG_SYS_CS4_FTIM0
-CONFIG_SYS_CS4_FTIM1
-CONFIG_SYS_CS4_FTIM2
-CONFIG_SYS_CS4_FTIM3
-CONFIG_SYS_CS6_FTIM0
-CONFIG_SYS_CS6_FTIM1
-CONFIG_SYS_CS6_FTIM2
-CONFIG_SYS_CS6_FTIM3
-CONFIG_SYS_CS7_FTIM0
-CONFIG_SYS_CS7_FTIM1
-CONFIG_SYS_CS7_FTIM2
-CONFIG_SYS_CS7_FTIM3
-CONFIG_SYS_CSOR0
-CONFIG_SYS_CSOR1
-CONFIG_SYS_CSOR2
-CONFIG_SYS_CSOR3
-CONFIG_SYS_CSOR4
-CONFIG_SYS_CSOR6
-CONFIG_SYS_CSOR7
-CONFIG_SYS_CSPR0
-CONFIG_SYS_CSPR0_EXT
-CONFIG_SYS_CSPR0_FINAL
-CONFIG_SYS_CSPR1
-CONFIG_SYS_CSPR1_EXT
-CONFIG_SYS_CSPR1_FINAL
-CONFIG_SYS_CSPR2
-CONFIG_SYS_CSPR2_EXT
-CONFIG_SYS_CSPR2_FINAL
-CONFIG_SYS_CSPR3
-CONFIG_SYS_CSPR3_EXT
-CONFIG_SYS_CSPR3_FINAL
-CONFIG_SYS_CSPR4
-CONFIG_SYS_CSPR4_EXT
-CONFIG_SYS_CSPR6
-CONFIG_SYS_CSPR6_EXT
-CONFIG_SYS_CSPR7
-CONFIG_SYS_CSPR7_EXT
-CONFIG_SYS_DA850_DDR2_DDRPHYCR
-CONFIG_SYS_DA850_DDR2_PBBPR
-CONFIG_SYS_DA850_DDR2_SDBCR
-CONFIG_SYS_DA850_DDR2_SDBCR2
-CONFIG_SYS_DA850_DDR2_SDRCR
-CONFIG_SYS_DA850_DDR2_SDTIMR
-CONFIG_SYS_DA850_DDR2_SDTIMR2
-CONFIG_SYS_DA850_PLL0_PLLM
-CONFIG_SYS_DA850_PLL1_PLLM
-CONFIG_SYS_DA850_SYSCFG_SUSPSRC
-CONFIG_SYS_DCACHE_INV
-CONFIG_SYS_DCSRBAR
-CONFIG_SYS_DCSRBAR_PHYS
-CONFIG_SYS_DCSR_DCFG_ADDR
-CONFIG_SYS_DCSR_DCFG_OFFSET
-CONFIG_SYS_DDRCDR
-CONFIG_SYS_DDRCDR_VALUE
-CONFIG_SYS_DDRUA
-CONFIG_SYS_DDR_BLOCK1_SIZE
-CONFIG_SYS_DDR_BLOCK2_BASE
-CONFIG_SYS_DDR_CLKSEL
-CONFIG_SYS_DDR_CLK_CNTL
-CONFIG_SYS_DDR_CLK_CONTROL
-CONFIG_SYS_DDR_CLK_CTRL
-CONFIG_SYS_DDR_CONFIG
-CONFIG_SYS_DDR_CONFIG_2
-CONFIG_SYS_DDR_CONTROL
-CONFIG_SYS_DDR_CONTROL_2
-CONFIG_SYS_DDR_CS0_BNDS
-CONFIG_SYS_DDR_CS0_CONFIG
-CONFIG_SYS_DDR_CS0_CONFIG_2
-CONFIG_SYS_DDR_CS1_BNDS
-CONFIG_SYS_DDR_CS1_CONFIG
-CONFIG_SYS_DDR_CS1_CONFIG_2
-CONFIG_SYS_DDR_INIT_ADDR
-CONFIG_SYS_DDR_INIT_EXT_ADDR
-CONFIG_SYS_DDR_INTERVAL
-CONFIG_SYS_DDR_MODE
-CONFIG_SYS_DDR_MODE2
-CONFIG_SYS_DDR_MODE_1
-CONFIG_SYS_DDR_MODE_2
-CONFIG_SYS_DDR_MODE_CONTROL
-CONFIG_SYS_DDR_RCW_1
-CONFIG_SYS_DDR_RCW_2
-CONFIG_SYS_DDR_SDRAM_BASE
-CONFIG_SYS_DDR_SDRAM_CFG
-CONFIG_SYS_DDR_SDRAM_CFG2
-CONFIG_SYS_DDR_SDRAM_CLK_CNTL
-CONFIG_SYS_DDR_SR_CNTR
-CONFIG_SYS_DDR_TIMING_0
-CONFIG_SYS_DDR_TIMING_1
-CONFIG_SYS_DDR_TIMING_2
-CONFIG_SYS_DDR_TIMING_3
-CONFIG_SYS_DDR_TIMING_4
-CONFIG_SYS_DDR_TIMING_5
-CONFIG_SYS_DDR_WRLVL_CONTROL
-CONFIG_SYS_DDR_ZQ_CONTROL
-CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
-CONFIG_SYS_DPAA_DCE
-CONFIG_SYS_DPAA_FMAN
-CONFIG_SYS_DPAA_PME
-CONFIG_SYS_DPAA_RMAN
-CONFIG_SYS_DRAM_TEST
-CONFIG_SYS_DV_NOR_BOOT_CFG
-CONFIG_SYS_ENV_SECT_SIZE
-CONFIG_SYS_ETHOC_BASE
-CONFIG_SYS_ETHOC_BUFFER_ADDR
-CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-CONFIG_SYS_FAST_CLK
-CONFIG_SYS_FEC_BUF_USE_SRAM
-CONFIG_SYS_FLASH0
-CONFIG_SYS_FLASH1
-CONFIG_SYS_FLASH1_BASE_PHYS
-CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
-CONFIG_SYS_FLASH_BANKS_LIST
-CONFIG_SYS_FLASH_BANKS_SIZES
-CONFIG_SYS_FLASH_BASE
-CONFIG_SYS_FLASH_BASE_PHYS
-CONFIG_SYS_FLASH_BASE_PHYS_EARLY
-CONFIG_SYS_FLASH_PARMSECT_SZ
-CONFIG_SYS_FLASH_SIZE
-CONFIG_SYS_FM1_10GEC1_PHY_ADDR
-CONFIG_SYS_FM1_CLK
-CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
-CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
-CONFIG_SYS_FM1_DTSEC2_PHY_ADDR
-CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR
-CONFIG_SYS_FM1_DTSEC3_PHY_ADDR
-CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR
-CONFIG_SYS_FM1_DTSEC4_PHY_ADDR
-CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR
-CONFIG_SYS_FM1_DTSEC5_PHY_ADDR
-CONFIG_SYS_FM1_QSGMII11_PHY_ADDR
-CONFIG_SYS_FM1_QSGMII21_PHY_ADDR
-CONFIG_SYS_FM2_CLK
-CONFIG_SYS_FM_MURAM_SIZE
-CONFIG_SYS_FPGAREG_DIPSW
-CONFIG_SYS_FPGAREG_FREQ
-CONFIG_SYS_FPGAREG_RESET
-CONFIG_SYS_FPGAREG_RESET_CODE
-CONFIG_SYS_FPGA_AMASK
-CONFIG_SYS_FPGA_BASE
-CONFIG_SYS_FPGA_CSOR
-CONFIG_SYS_FPGA_CSPR
-CONFIG_SYS_FPGA_CSPR_EXT
-CONFIG_SYS_FPGA_FTIM0
-CONFIG_SYS_FPGA_FTIM1
-CONFIG_SYS_FPGA_FTIM2
-CONFIG_SYS_FPGA_FTIM3
-CONFIG_SYS_FPGA_SIZE
-CONFIG_SYS_FPGA_WAIT
-CONFIG_SYS_GPIO1_EN
-CONFIG_SYS_GPIO1_FUNC
-CONFIG_SYS_GPIO1_LED
-CONFIG_SYS_GPIO1_OUT
-CONFIG_SYS_GPIO_EN
-CONFIG_SYS_GPIO_FUNC
-CONFIG_SYS_GPIO_OUT
-CONFIG_SYS_GPR1
-CONFIG_SYS_HZ_CLOCK
-CONFIG_SYS_I2C_BUSES
-CONFIG_SYS_I2C_EXPANDER_ADDR
-CONFIG_SYS_I2C_FPGA_ADDR
-CONFIG_SYS_I2C_G762_ADDR
-CONFIG_SYS_I2C_IFDR_DIV
-CONFIG_SYS_I2C_MAX_HOPS
-CONFIG_SYS_I2C_NOPROBES
-CONFIG_SYS_I2C_PCA953X_ADDR
-CONFIG_SYS_I2C_PCA953X_WIDTH
-CONFIG_SYS_I2C_PCA9557_ADDR
-CONFIG_SYS_I2C_PINMUX_CLR
-CONFIG_SYS_I2C_PINMUX_REG
-CONFIG_SYS_I2C_PINMUX_SET
-CONFIG_SYS_I2C_RTC_ADDR
-CONFIG_SYS_I2C_TCA642X_ADDR
-CONFIG_SYS_I2C_TCA642X_BUS_NUM
-CONFIG_SYS_ICACHE_INV
-CONFIG_SYS_IFC_ADDR
-CONFIG_SYS_IFC_CCR
-CONFIG_SYS_INIT_DBCR
-CONFIG_SYS_INIT_L2CSR0
-CONFIG_SYS_INIT_L2_ADDR
-CONFIG_SYS_INIT_L2_ADDR_PHYS
-CONFIG_SYS_INIT_L2_END
-CONFIG_SYS_INIT_L3_ADDR
-CONFIG_SYS_INIT_L3_ADDR_PHYS
-CONFIG_SYS_INIT_L3_VADDR
-CONFIG_SYS_INIT_RAM_ADDR
-CONFIG_SYS_INIT_RAM_ADDR_PHYS
-CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
-CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW
-CONFIG_SYS_INIT_RAM_CTRL
-CONFIG_SYS_INIT_RAM_SIZE
-CONFIG_SYS_INIT_SP_OFFSET
-CONFIG_SYS_INT_FLASH_BASE
-CONFIG_SYS_INT_FLASH_ENABLE
-CONFIG_SYS_IO_BASE
-CONFIG_SYS_KMBEC_FPGA_BASE
-CONFIG_SYS_KMBEC_FPGA_SIZE
-CONFIG_SYS_LATCH_ADDR
-CONFIG_SYS_LBC_ADDR
-CONFIG_SYS_LBC_FLASH_BASE
-CONFIG_SYS_LBC_LBCR
-CONFIG_SYS_LBC_LCRR
-CONFIG_SYS_LBC_LSDMR_COMMON
-CONFIG_SYS_LBC_LSRT
-CONFIG_SYS_LBC_MRTPR
-CONFIG_SYS_LBC_SDRAM_BASE
-CONFIG_SYS_LBC_SDRAM_BASE_PHYS
-CONFIG_SYS_LBC_SDRAM_SIZE
-CONFIG_SYS_LDB_CLOCK
-CONFIG_SYS_LIME_BASE
-CONFIG_SYS_LOW
-CONFIG_SYS_LOWMEM_BASE
-CONFIG_SYS_LPAE_SDRAM_BASE
-CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
-CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
-CONFIG_SYS_LS_MC_DPC_MAX_LENGTH
-CONFIG_SYS_LS_MC_DPL_MAX_LENGTH
-CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
-CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
-CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
-CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
-CONFIG_SYS_MAIN_PWR_ON
-CONFIG_SYS_MASTER_CLOCK
-CONFIG_SYS_MATRIX_EBI0CSA_VAL
-CONFIG_SYS_MATRIX_EBICSA_VAL
-CONFIG_SYS_MAX_I2C_BUS
-CONFIG_SYS_MAX_NAND_CHIPS
-CONFIG_SYS_MBAR
-CONFIG_SYS_MBAR2
-CONFIG_SYS_MCKR
-CONFIG_SYS_MCKR1_VAL
-CONFIG_SYS_MCKR2_VAL
-CONFIG_SYS_MCKR_CSS
-CONFIG_SYS_MDIO1_OFFSET
-CONFIG_SYS_MEMORY_BASE
-CONFIG_SYS_MEM_RESERVE_SECURE
-CONFIG_SYS_MFD
-CONFIG_SYS_MMC_CD_PIN
-CONFIG_SYS_MMC_CLK_OD
-CONFIG_SYS_MMC_U_BOOT_DST
-CONFIG_SYS_MMC_U_BOOT_OFFS
-CONFIG_SYS_MMC_U_BOOT_SIZE
-CONFIG_SYS_MMC_U_BOOT_START
-CONFIG_SYS_MOR_VAL
-CONFIG_SYS_MRAM_BASE
-CONFIG_SYS_NAND_AMASK
-CONFIG_SYS_NAND_BASE
-CONFIG_SYS_NAND_BASE2
-CONFIG_SYS_NAND_BASE_LIST
-CONFIG_SYS_NAND_BASE_PHYS
-CONFIG_SYS_NAND_BR_PRELIM
-CONFIG_SYS_NAND_CS
-CONFIG_SYS_NAND_CSOR
-CONFIG_SYS_NAND_CSPR
-CONFIG_SYS_NAND_CSPR_EXT
-CONFIG_SYS_NAND_DATA_BASE
-CONFIG_SYS_NAND_DBW_8
-CONFIG_SYS_NAND_DDR_LAW
-CONFIG_SYS_NAND_ECCBYTES
-CONFIG_SYS_NAND_ECCPOS
-CONFIG_SYS_NAND_ECCSIZE
-CONFIG_SYS_NAND_ECCSTEPS
-CONFIG_SYS_NAND_ECCTOTAL
-CONFIG_SYS_NAND_ECC_BASE
-CONFIG_SYS_NAND_ENABLE_PIN
-CONFIG_SYS_NAND_ENABLE_PIN_SPL
-CONFIG_SYS_NAND_FTIM0
-CONFIG_SYS_NAND_FTIM1
-CONFIG_SYS_NAND_FTIM2
-CONFIG_SYS_NAND_FTIM3
-CONFIG_SYS_NAND_HW_ECC
-CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-CONFIG_SYS_NAND_LARGEPAGE
-CONFIG_SYS_NAND_MASK_ALE
-CONFIG_SYS_NAND_MASK_CLE
-CONFIG_SYS_NAND_MAX_ECCPOS
-CONFIG_SYS_NAND_MAX_OOBFREE
-CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
-CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
-CONFIG_SYS_NAND_OR_PRELIM
-CONFIG_SYS_NAND_PAGE_2K
-CONFIG_SYS_NAND_PAGE_4K
-CONFIG_SYS_NAND_READY_PIN
-CONFIG_SYS_NAND_REGS_BASE
-CONFIG_SYS_NAND_SIZE
-CONFIG_SYS_NAND_U_BOOT_DST
-CONFIG_SYS_NAND_U_BOOT_RELOC_SP
-CONFIG_SYS_NAND_U_BOOT_SIZE
-CONFIG_SYS_NAND_U_BOOT_START
-CONFIG_SYS_NOR0_CSPR
-CONFIG_SYS_NOR0_CSPR_EARLY
-CONFIG_SYS_NOR0_CSPR_EXT
-CONFIG_SYS_NOR1_CSPR
-CONFIG_SYS_NOR1_CSPR_EARLY
-CONFIG_SYS_NOR1_CSPR_EXT
-CONFIG_SYS_NOR_AMASK
-CONFIG_SYS_NOR_AMASK_EARLY
-CONFIG_SYS_NOR_CSOR
-CONFIG_SYS_NOR_CSPR
-CONFIG_SYS_NOR_CSPR_EXT
-CONFIG_SYS_NOR_FTIM0
-CONFIG_SYS_NOR_FTIM1
-CONFIG_SYS_NOR_FTIM2
-CONFIG_SYS_NOR_FTIM3
-CONFIG_SYS_NS16550_CLK
-CONFIG_SYS_NS16550_COM1
-CONFIG_SYS_NS16550_COM2
-CONFIG_SYS_NS16550_COM3
-CONFIG_SYS_NS16550_COM4
-CONFIG_SYS_NS16550_COM5
-CONFIG_SYS_NS16550_COM6
-CONFIG_SYS_NS16550_MEM32
-CONFIG_SYS_NS16550_PORT_MAPPED
-CONFIG_SYS_NS16550_REG_SIZE
-CONFIG_SYS_NS16550_SERIAL
-CONFIG_SYS_NUM_CPC
-CONFIG_SYS_NUM_FM1_10GEC
-CONFIG_SYS_NUM_FM1_DTSEC
-CONFIG_SYS_NUM_FM2_10GEC
-CONFIG_SYS_NUM_FM2_DTSEC
-CONFIG_SYS_NUM_FMAN
-CONFIG_SYS_NUM_I2C_BUSES
-CONFIG_SYS_NVRAM_BASE_ADDR
-CONFIG_SYS_NVRAM_SIZE
-CONFIG_SYS_OBIR
-CONFIG_SYS_OMAP_ABE_SYSCK
-CONFIG_SYS_ONENAND_BASE
-CONFIG_SYS_ONENAND_BLOCK_SIZE
-CONFIG_SYS_OSCIN_FREQ
-CONFIG_SYS_OSPR_OFFSET
-CONFIG_SYS_PACNT
-CONFIG_SYS_PADAT
-CONFIG_SYS_PADDR
-CONFIG_SYS_PAGE_SIZE
-CONFIG_SYS_PAMU_ADDR
-CONFIG_SYS_PASPAR
-CONFIG_SYS_PAXE_BASE
-CONFIG_SYS_PAXE_SIZE
-CONFIG_SYS_PBCNT
-CONFIG_SYS_PBDAT
-CONFIG_SYS_PBDDR
-CONFIG_SYS_PBI_FLASH_BASE
-CONFIG_SYS_PBI_FLASH_WINDOW
-CONFIG_SYS_PCCNT
-CONFIG_SYS_PCDAT
-CONFIG_SYS_PCDDR
-CONFIG_SYS_PCI
-CONFIG_SYS_PCI1_ADDR
-CONFIG_SYS_PCI1_IO_BASE
-CONFIG_SYS_PCI1_IO_BUS
-CONFIG_SYS_PCI1_IO_PHYS
-CONFIG_SYS_PCI1_IO_SIZE
-CONFIG_SYS_PCI1_IO_VIRT
-CONFIG_SYS_PCI1_MEM_BASE
-CONFIG_SYS_PCI1_MEM_BUS
-CONFIG_SYS_PCI1_MEM_PHYS
-CONFIG_SYS_PCI1_MEM_SIZE
-CONFIG_SYS_PCI1_MEM_VIRT
-CONFIG_SYS_PCI2_ADDR
-CONFIG_SYS_PCIE
-CONFIG_SYS_PCIE1_ADDR
-CONFIG_SYS_PCIE1_CFG_BASE
-CONFIG_SYS_PCIE1_CFG_SIZE
-CONFIG_SYS_PCIE1_IO_PHYS
-CONFIG_SYS_PCIE1_IO_VIRT
-CONFIG_SYS_PCIE1_MEM_PHYS
-CONFIG_SYS_PCIE1_MEM_VIRT
-CONFIG_SYS_PCIE1_PHYS_ADDR
-CONFIG_SYS_PCIE1_PHYS_BASE
-CONFIG_SYS_PCIE1_VIRT_ADDR
-CONFIG_SYS_PCIE2_ADDR
-CONFIG_SYS_PCIE2_CFG_BASE
-CONFIG_SYS_PCIE2_CFG_SIZE
-CONFIG_SYS_PCIE2_IO_PHYS
-CONFIG_SYS_PCIE2_IO_VIRT
-CONFIG_SYS_PCIE2_MEM_PHYS
-CONFIG_SYS_PCIE2_MEM_VIRT
-CONFIG_SYS_PCIE2_PHYS_ADDR
-CONFIG_SYS_PCIE2_PHYS_BASE
-CONFIG_SYS_PCIE2_VIRT_ADDR
-CONFIG_SYS_PCIE3_ADDR
-CONFIG_SYS_PCIE3_IO_PHYS
-CONFIG_SYS_PCIE3_IO_VIRT
-CONFIG_SYS_PCIE3_MEM_PHYS
-CONFIG_SYS_PCIE3_MEM_VIRT
-CONFIG_SYS_PCIE3_PHYS_ADDR
-CONFIG_SYS_PCIE3_PHYS_SIZE
-CONFIG_SYS_PCIE4_ADDR
-CONFIG_SYS_PCIE4_IO_PHYS
-CONFIG_SYS_PCIE4_IO_VIRT
-CONFIG_SYS_PCIE4_MEM_BUS
-CONFIG_SYS_PCIE4_MEM_PHYS
-CONFIG_SYS_PCIE4_MEM_VIRT
-CONFIG_SYS_PCIE4_PHYS_ADDR
-CONFIG_SYS_PCIE_MMAP_SIZE
-CONFIG_SYS_PDCNT
-CONFIG_SYS_PEHLPAR
-CONFIG_SYS_PIOC_PDR_VAL
-CONFIG_SYS_PIOC_PDR_VAL1
-CONFIG_SYS_PIOC_PPUDR_VAL
-CONFIG_SYS_PIOD_PDR_VAL1
-CONFIG_SYS_PIOD_PPUDR_VAL
-CONFIG_SYS_PJPAR
-CONFIG_SYS_PL310_BASE
-CONFIG_SYS_PLLAR_VAL
-CONFIG_SYS_PLLCR
-CONFIG_SYS_PLL_BYPASS
-CONFIG_SYS_PLL_FDR
-CONFIG_SYS_PLL_ODR
-CONFIG_SYS_PLL_SETTLING_TIME
-CONFIG_SYS_PMAN
-CONFIG_SYS_PME_CLK
-CONFIG_SYS_POST_MEMORY
-CONFIG_SYS_POST_MEM_REGIONS
-CONFIG_SYS_PUAPAR
-CONFIG_SYS_QMAN_CENA_BASE
-CONFIG_SYS_QMAN_CENA_SIZE
-CONFIG_SYS_QMAN_CINH_BASE
-CONFIG_SYS_QMAN_CINH_SIZE
-CONFIG_SYS_QMAN_MEM_BASE
-CONFIG_SYS_QMAN_MEM_PHYS
-CONFIG_SYS_QMAN_MEM_SIZE
-CONFIG_SYS_QMAN_NUM_PORTALS
-CONFIG_SYS_QMAN_SP_CENA_SIZE
-CONFIG_SYS_QMAN_SP_CINH_SIZE
-CONFIG_SYS_QMAN_SWP_ISDR_REG
-CONFIG_SYS_QRIO_BASE
-CONFIG_SYS_QRIO_BASE_PHYS
-CONFIG_SYS_RCAR_I2C0_BASE
-CONFIG_SYS_RCAR_I2C1_BASE
-CONFIG_SYS_RCAR_I2C2_BASE
-CONFIG_SYS_RCAR_I2C3_BASE
-CONFIG_SYS_RFD
-CONFIG_SYS_RGMII1_PHY_ADDR
-CONFIG_SYS_RGMII2_PHY_ADDR
-CONFIG_SYS_ROM_BASE
-CONFIG_SYS_RSTC_RMR_VAL
-CONFIG_SYS_RTC_BUS_NUM
-CONFIG_SYS_RTC_CNT
-CONFIG_SYS_RTC_SETUP
-CONFIG_SYS_SATA
-CONFIG_SYS_SATA_FAT_BOOT_PARTITION
-CONFIG_SYS_SBFHDR_DATA_OFFSET
-CONFIG_SYS_SBFHDR_SIZE
-CONFIG_SYS_SCCR_SATACM
-CONFIG_SYS_SCCR_TSEC1CM
-CONFIG_SYS_SCCR_TSEC2CM
-CONFIG_SYS_SCCR_USBDRCM
-CONFIG_SYS_SCR
-CONFIG_SYS_SDRAM
-CONFIG_SYS_SDRAM_BASE
-CONFIG_SYS_SDRAM_BASE0
-CONFIG_SYS_SDRAM_BASE1
-CONFIG_SYS_SDRAM_BASE2
-CONFIG_SYS_SDRAM_CFG1
-CONFIG_SYS_SDRAM_CFG2
-CONFIG_SYS_SDRAM_CTRL
-CONFIG_SYS_SDRAM_EMOD
-CONFIG_SYS_SDRAM_MODE
-CONFIG_SYS_SDRAM_SIZE
-CONFIG_SYS_SDRAM_SIZE0
-CONFIG_SYS_SDRAM_SIZE_LAW
-CONFIG_SYS_SDRAM_VAL
-CONFIG_SYS_SDRAM_VAL1
-CONFIG_SYS_SDRAM_VAL10
-CONFIG_SYS_SDRAM_VAL11
-CONFIG_SYS_SDRAM_VAL12
-CONFIG_SYS_SDRAM_VAL2
-CONFIG_SYS_SDRAM_VAL3
-CONFIG_SYS_SDRAM_VAL4
-CONFIG_SYS_SDRAM_VAL5
-CONFIG_SYS_SDRAM_VAL6
-CONFIG_SYS_SDRAM_VAL7
-CONFIG_SYS_SDRAM_VAL8
-CONFIG_SYS_SDRAM_VAL9
-CONFIG_SYS_SDRC_CR_VAL
-CONFIG_SYS_SDRC_MDR_VAL
-CONFIG_SYS_SDRC_MR_VAL
-CONFIG_SYS_SDRC_MR_VAL1
-CONFIG_SYS_SDRC_MR_VAL2
-CONFIG_SYS_SDRC_MR_VAL3
-CONFIG_SYS_SDRC_MR_VAL4
-CONFIG_SYS_SDRC_MR_VAL5
-CONFIG_SYS_SDRC_TR_VAL
-CONFIG_SYS_SDRC_TR_VAL1
-CONFIG_SYS_SDRC_TR_VAL2
-CONFIG_SYS_SEC_MON_ADDR
-CONFIG_SYS_SEC_MON_OFFSET
-CONFIG_SYS_SERIAL0
-CONFIG_SYS_SERIAL1
-CONFIG_SYS_SERIAL2
-CONFIG_SYS_SERIAL3
-CONFIG_SYS_SFP_ADDR
-CONFIG_SYS_SFP_OFFSET
-CONFIG_SYS_SGMII1_PHY_ADDR
-CONFIG_SYS_SGMII2_PHY_ADDR
-CONFIG_SYS_SGMII3_PHY_ADDR
-CONFIG_SYS_SGMII_LINERATE_MHZ
-CONFIG_SYS_SGMII_RATESCALE
-CONFIG_SYS_SGMII_REFCLK_MHZ
-CONFIG_SYS_SH_SDHI0_BASE
-CONFIG_SYS_SH_SDHI1_BASE
-CONFIG_SYS_SH_SDHI2_BASE
-CONFIG_SYS_SH_SDHI3_BASE
-CONFIG_SYS_SH_SDHI_NR_CHANNEL
-CONFIG_SYS_SICRH
-CONFIG_SYS_SICRL
-CONFIG_SYS_SMC0_CYCLE0_VAL
-CONFIG_SYS_SMC0_MODE0_VAL
-CONFIG_SYS_SMC0_PULSE0_VAL
-CONFIG_SYS_SMC0_SETUP0_VAL
-CONFIG_SYS_SPI_ARGS_OFFS
-CONFIG_SYS_SPI_ARGS_SIZE
-CONFIG_SYS_SPI_BASE
-CONFIG_SYS_SPI_CLK
-CONFIG_SYS_SPI_FLASH_U_BOOT_DST
-CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS
-CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE
-CONFIG_SYS_SPI_FLASH_U_BOOT_START
-CONFIG_SYS_SPI_KERNEL_OFFS
-CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-CONFIG_SYS_SPI_U_BOOT_SIZE
-CONFIG_SYS_SPL_MALLOC_START
-CONFIG_SYS_SPR
-CONFIG_SYS_SRIO
-CONFIG_SYS_SRIO1_MEM_PHYS
-CONFIG_SYS_SRIO1_MEM_SIZE
-CONFIG_SYS_SRIO1_MEM_VIRT
-CONFIG_SYS_SRIO2_MEM_PHYS
-CONFIG_SYS_SRIO2_MEM_SIZE
-CONFIG_SYS_SRIO2_MEM_VIRT
-CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
-CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS
-CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR
-CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS
-CONFIG_SYS_SST_SECT
-CONFIG_SYS_SST_SECTSZ
-CONFIG_SYS_STACK_SIZE
-CONFIG_SYS_TBIPA_VALUE
-CONFIG_SYS_TCLK
-CONFIG_SYS_TIMERBASE
-CONFIG_SYS_TIMER_BASE
-CONFIG_SYS_TIMER_COUNTER
-CONFIG_SYS_TIMER_COUNTS_DOWN
-CONFIG_SYS_TIMER_RATE
-CONFIG_SYS_TMPVIRT
-CONFIG_SYS_TSEC1_OFFSET
-CONFIG_SYS_TX_ETH_BUFFER
-CONFIG_SYS_UART2_ALT3_GPIO
-CONFIG_SYS_UART_PORT
-CONFIG_SYS_UBOOT_BASE
-CONFIG_SYS_UBOOT_START
-CONFIG_SYS_UEC
-CONFIG_SYS_UEC2_PHY_ADDR
-CONFIG_SYS_USB_OHCI_REGS_BASE
-CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
-CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
-CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
-CONFIG_SYS_VCXK_BASE
-CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
-CONFIG_SYS_VCXK_DOUBLEBUFFERED
-CONFIG_SYS_VCXK_ENABLE_DDR
-CONFIG_SYS_VCXK_ENABLE_PIN
-CONFIG_SYS_VCXK_ENABLE_PORT
-CONFIG_SYS_VCXK_INVERT_DDR
-CONFIG_SYS_VCXK_INVERT_PIN
-CONFIG_SYS_VCXK_INVERT_PORT
-CONFIG_SYS_VCXK_REQUEST_DDR
-CONFIG_SYS_VCXK_REQUEST_PIN
-CONFIG_SYS_VCXK_REQUEST_PORT
-CONFIG_SYS_VSC7385_BASE
-CONFIG_SYS_VSC7385_BASE_PHYS
-CONFIG_SYS_VSC7385_BR_PRELIM
-CONFIG_SYS_VSC7385_OR_PRELIM
-CONFIG_SYS_WATCHDOG_VALUE
-CONFIG_SYS_WDTC_WDMR_VAL
-CONFIG_SYS_WRITE_SWAPPED_DATA
-CONFIG_SYS_XHCI_USB1_ADDR
-CONFIG_SYS_XHCI_USB2_ADDR
-CONFIG_SYS_XHCI_USB3_ADDR
-CONFIG_TCA642X
 CONFIG_TEGRA_BOARD_STRING
-CONFIG_TEGRA_CLOCK_SCALING
 CONFIG_TEGRA_ENABLE_UARTA
 CONFIG_TEGRA_ENABLE_UARTD
-CONFIG_TEGRA_LP0
-CONFIG_TEGRA_PMU
 CONFIG_TEGRA_SLINK_CTRLS
 CONFIG_TEGRA_SPI
 CONFIG_TEGRA_UARTA_GPU
@@ -964,10 +224,7 @@
 CONFIG_TESTPIN_MASK
 CONFIG_TESTPIN_REG
 CONFIG_THOR_RESET_OFF
-CONFIG_TMU_TIMER
 CONFIG_TPM_TIS_BASE_ADDRESS
-CONFIG_TPS6586X_POWER
-CONFIG_TSEC
 CONFIG_TSEC1
 CONFIG_TSEC1_NAME
 CONFIG_TSEC2
@@ -979,36 +236,24 @@
 CONFIG_TSECV2
 CONFIG_TSECV2_1
 CONFIG_TSEC_TBICR_SETTINGS
-CONFIG_TWL6030_POWER
 CONFIG_UBIFS_VOLUME
 CONFIG_UBI_PART
 CONFIG_UBOOTPATH
 CONFIG_UBOOT_SECTOR_COUNT
 CONFIG_UBOOT_SECTOR_START
 CONFIG_UEC_ETH
-CONFIG_UEC_ETH2
 CONFIG_USART_BASE
 CONFIG_USART_ID
 CONFIG_USBD_HS
-CONFIG_USBD_MANUFACTURER
-CONFIG_USBD_PRODUCTID_CDCACM
-CONFIG_USBD_PRODUCTID_GSERIAL
-CONFIG_USBD_PRODUCT_NAME
-CONFIG_USBD_VENDORID
 CONFIG_USB_BOOTING
-CONFIG_USB_DEVICE
 CONFIG_USB_EXT2_BOOT
 CONFIG_USB_FAT_BOOT
-CONFIG_USB_GADGET_AT91
 CONFIG_USB_ISP1301_I2C_ADDR
-CONFIG_USB_TTY
 CONFIG_U_BOOT_HDR_SIZE
 CONFIG_VAR_SIZE_SPL
 CONFIG_VERY_BIG_RAM
-CONFIG_VSC7385_ENET
 CONFIG_VSC7385_IMAGE
 CONFIG_VSC7385_IMAGE_SIZE
-CONFIG_VSC9953
 CONFIG_WATCHDOG_PRESC
 CONFIG_WATCHDOG_RC
 CONFIG_WATCHDOG_TIMEOUT

diff --git a/test/Kconfig b/test/Kconfig
index a6b463e..9f4641a 100644
--- a/test/Kconfig
+++ b/test/Kconfig

@@ -1,3 +1,8 @@
+config POST
+	bool "Power On Self Test support"
+	help
+	  See doc/README.POST for more details
+
 menuconfig UNIT_TEST
 	bool "Unit tests"
 	help

diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c
index 1cc07bc..b5e9f9d 100644
--- a/test/dm/remoteproc.c
+++ b/test/dm/remoteproc.c

@@ -208,7 +208,7 @@
 	 * at SDRAM_BASE *device* address (p_paddr field).
 	 * Its size is defined by the p_filesz field.
 	 */
-	phdr->p_paddr = CONFIG_SYS_SDRAM_BASE;
+	phdr->p_paddr = CFG_SYS_SDRAM_BASE;
 	loaded_firmware_size = phdr->p_filesz;
 
 	/*
@@ -231,7 +231,7 @@
 	unmap_physmem(loaded_firmware, MAP_NOCACHE);
 
 	/* Resource table */
-	shdr->sh_addr = CONFIG_SYS_SDRAM_BASE;
+	shdr->sh_addr = CFG_SYS_SDRAM_BASE;
 	rsc_table_size = shdr->sh_size;
 
 	loaded_rsc_table_paddr = shdr->sh_addr + DEVICE_TO_PHYSICAL_OFFSET;
@@ -243,7 +243,7 @@
 	/* Load and verify */
 	ut_assertok(rproc_elf32_load_rsc_table(dev, (ulong)valid_elf32, size,
 					       &rsc_addr, &rsc_size));
-	ut_asserteq(rsc_addr, CONFIG_SYS_SDRAM_BASE);
+	ut_asserteq(rsc_addr, CFG_SYS_SDRAM_BASE);
 	ut_asserteq(rsc_size, rsc_table_size);
 	ut_asserteq_mem(loaded_firmware, valid_elf32 + shdr->sh_offset,
 			shdr->sh_size);

diff --git a/tools/envcrc.c b/tools/envcrc.c
index bce7790..a021c78 100644
--- a/tools/envcrc.c
+++ b/tools/envcrc.c

@@ -23,13 +23,13 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_OFFSET
-#  define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#  define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE)
 # endif
 # if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND)
-#  define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
+#  define CONFIG_ENV_ADDR_REDUND	(CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
commit	040227f76d410c389d4403dc505f43173a9b3875	[log] [tgz]
author	Tom Rini <trini@konsulko.com>	Mon Dec 05 21:04:24 2022 -0500
committer	Tom Rini <trini@konsulko.com>	Mon Dec 05 21:04:24 2022 -0500
tree	23ec41dc6f0aff10b800c69396a32ac5ac926817
parent	ca8f571310240395b01f69929726b06ca277913b [diff]
parent	9e7eeec7347177f53d12d93cb4049e19d1db9a67 [diff]