commit 03c3093cf7a4b11e0d5ed9bb80cd15d8c56a5635
author Pragnesh Patel <pragnesh.patel@sifive.com> Sun Jun 21 17:22:18 2020 +0530
committer Jagan Teki <jagan@amarulasolutions.com> Thu Jul 09 20:58:06 2020 +0530
tree 716c011e1e436dd273e126373cbbd997ea0c0da2
parent 8412062a001a5f11344dd6eb463ab975d9c2314d

mtd: spi-nor: Enable QE bit for ISSI flash in case of SFDP

Enable QE bit for ISSI flash chips.

QE enablement logic is similar to what Macronix
has, so reuse the existing code itself.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

drivers/mtd/spi/spi-nor-core.c

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1e3f51d..fdcd830 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1291,7 +1291,7 @@
 	return ret;
 }
 
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
 /**
  * macronix_quad_enable() - set QE bit in Status Register.
  * @nor:	pointer to a 'struct spi_nor'
@@ -1969,7 +1969,7 @@
 		params->quad_enable = spansion_no_read_cr_quad_enable;
 		break;
 #endif
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
 	case BFPT_DWORD15_QER_SR1_BIT6:
 		params->quad_enable = macronix_quad_enable;
 		break;
@@ -2206,8 +2206,9 @@
 	if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
 				   SNOR_HWCAPS_PP_QUAD)) {
 		switch (JEDEC_MFR(info)) {
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
 		case SNOR_MFR_MACRONIX:
+		case SNOR_MFR_ISSI:
 			params->quad_enable = macronix_quad_enable;
 			break;
 #endif