rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c
index bd62aab..32ad469 100644
--- a/cpu/mpc85xx/ether_fcc.c
+++ b/cpu/mpc85xx/ether_fcc.c
@@ -74,8 +74,8 @@
 	PROFF_FCC1,
 	CPM_CR_FCC1_SBLOCK,
 	CPM_CR_FCC1_PAGE,
-	CFG_CMXFCR_MASK1,
-	CFG_CMXFCR_VALUE1
+	CONFIG_SYS_CMXFCR_MASK1,
+	CONFIG_SYS_CMXFCR_VALUE1
 },
 #endif
 
@@ -85,8 +85,8 @@
 	PROFF_FCC2,
 	CPM_CR_FCC2_SBLOCK,
 	CPM_CR_FCC2_PAGE,
-	CFG_CMXFCR_MASK2,
-	CFG_CMXFCR_VALUE2
+	CONFIG_SYS_CMXFCR_MASK2,
+	CONFIG_SYS_CMXFCR_VALUE2
 },
 #endif
 
@@ -96,8 +96,8 @@
 	PROFF_FCC3,
 	CPM_CR_FCC3_SBLOCK,
 	CPM_CR_FCC3_PAGE,
-	CFG_CMXFCR_MASK3,
-	CFG_CMXFCR_VALUE3
+	CONFIG_SYS_CMXFCR_MASK3,
+	CONFIG_SYS_CMXFCR_VALUE3
 },
 #endif
 };
@@ -230,7 +230,7 @@
 {
     struct ether_fcc_info_s * info = dev->priv;
     int i;
-    volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+    volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
     volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
     fcc_enet_t *pram_ptr;
     unsigned long mem_addr;
@@ -257,11 +257,11 @@
 
     /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
     if(info->ether_index == 0) {
-	cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+	cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
     } else if (info->ether_index == 1){
-	cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+	cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
     } else if (info->ether_index == 2){
-	cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+	cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
     }
 
     /* 28.9 - (6): FDSR: Ethernet Syn */
@@ -321,14 +321,14 @@
     pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
     /* localbus SDRAM should be preferred */
     pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
-				       CFG_CPMFCR_RAMTYPE) << 24;
+				       CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
     pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
     pram_ptr->fen_genfcc.fcc_rbdstat = 0;
     pram_ptr->fen_genfcc.fcc_rbdlen = 0;
     pram_ptr->fen_genfcc.fcc_rdptr = 0;
     /* localbus SDRAM should be preferred */
     pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
-				       CFG_CPMFCR_RAMTYPE) << 24;
+				       CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
     pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
     pram_ptr->fen_genfcc.fcc_tbdstat = 0;
     pram_ptr->fen_genfcc.fcc_tbdlen = 0;
@@ -426,7 +426,7 @@
 static void fec_halt(struct eth_device* dev)
 {
     struct ether_fcc_info_s * info = dev->priv;
-    volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
+    volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
 
     /* write GFMR: disable tx/rx */
     if(info->ether_index == 0) {