rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index 1326c3c..9c6ab76 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -118,7 +118,7 @@
#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
void ft_cpu_setup(void *blob, bd_t *bd)
{
- int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
+ int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
char * cpu_path = "/cpus/" OF_CPU;
#ifdef CONFIG_MPC5xxx_FEC
char * eth_path = "/" OF_SOC "/ethernet@3000";
diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index bc6201e..14bd417 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -35,11 +35,11 @@
void cpu_init_f (void)
{
unsigned long addecr = (1 << 25); /* Boot_CS */
-#if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100)
addecr |= (1 << 22); /* SDRAM enable */
#endif
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
@@ -47,95 +47,95 @@
/*
* Memory Controller: configure chip selects and enable them
*/
-#if defined(CFG_BOOTCS_START) && defined(CFG_BOOTCS_SIZE)
- *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CFG_BOOTCS_START);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CFG_BOOTCS_START,
- CFG_BOOTCS_SIZE);
+#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
+ *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CONFIG_SYS_BOOTCS_START);
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START,
+ CONFIG_SYS_BOOTCS_SIZE);
#endif
-#if defined(CFG_BOOTCS_CFG)
- *(vu_long *)MPC5XXX_BOOTCS_CFG = CFG_BOOTCS_CFG;
+#if defined(CONFIG_SYS_BOOTCS_CFG)
+ *(vu_long *)MPC5XXX_BOOTCS_CFG = CONFIG_SYS_BOOTCS_CFG;
#endif
-#if defined(CFG_CS0_START) && defined(CFG_CS0_SIZE)
- *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_CS0_START);
- *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_CS0_START, CFG_CS0_SIZE);
+#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
+ *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_CS0_START);
+ *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE);
/* CS0 and BOOT_CS cannot be enabled at once. */
/* addecr |= (1 << 16); */
#endif
-#if defined(CFG_CS0_CFG)
- *(vu_long *)MPC5XXX_CS0_CFG = CFG_CS0_CFG;
+#if defined(CONFIG_SYS_CS0_CFG)
+ *(vu_long *)MPC5XXX_CS0_CFG = CONFIG_SYS_CS0_CFG;
#endif
-#if defined(CFG_CS1_START) && defined(CFG_CS1_SIZE)
- *(vu_long *)MPC5XXX_CS1_START = START_REG(CFG_CS1_START);
- *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CFG_CS1_START, CFG_CS1_SIZE);
+#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
+ *(vu_long *)MPC5XXX_CS1_START = START_REG(CONFIG_SYS_CS1_START);
+ *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE);
addecr |= (1 << 17);
#endif
-#if defined(CFG_CS1_CFG)
- *(vu_long *)MPC5XXX_CS1_CFG = CFG_CS1_CFG;
+#if defined(CONFIG_SYS_CS1_CFG)
+ *(vu_long *)MPC5XXX_CS1_CFG = CONFIG_SYS_CS1_CFG;
#endif
-#if defined(CFG_CS2_START) && defined(CFG_CS2_SIZE)
- *(vu_long *)MPC5XXX_CS2_START = START_REG(CFG_CS2_START);
- *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, CFG_CS2_SIZE);
+#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
+ *(vu_long *)MPC5XXX_CS2_START = START_REG(CONFIG_SYS_CS2_START);
+ *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE);
addecr |= (1 << 18);
#endif
-#if defined(CFG_CS2_CFG)
- *(vu_long *)MPC5XXX_CS2_CFG = CFG_CS2_CFG;
+#if defined(CONFIG_SYS_CS2_CFG)
+ *(vu_long *)MPC5XXX_CS2_CFG = CONFIG_SYS_CS2_CFG;
#endif
-#if defined(CFG_CS3_START) && defined(CFG_CS3_SIZE)
- *(vu_long *)MPC5XXX_CS3_START = START_REG(CFG_CS3_START);
- *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CFG_CS3_START, CFG_CS3_SIZE);
+#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
+ *(vu_long *)MPC5XXX_CS3_START = START_REG(CONFIG_SYS_CS3_START);
+ *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE);
addecr |= (1 << 19);
#endif
-#if defined(CFG_CS3_CFG)
- *(vu_long *)MPC5XXX_CS3_CFG = CFG_CS3_CFG;
+#if defined(CONFIG_SYS_CS3_CFG)
+ *(vu_long *)MPC5XXX_CS3_CFG = CONFIG_SYS_CS3_CFG;
#endif
-#if defined(CFG_CS4_START) && defined(CFG_CS4_SIZE)
- *(vu_long *)MPC5XXX_CS4_START = START_REG(CFG_CS4_START);
- *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CFG_CS4_START, CFG_CS4_SIZE);
+#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
+ *(vu_long *)MPC5XXX_CS4_START = START_REG(CONFIG_SYS_CS4_START);
+ *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE);
addecr |= (1 << 20);
#endif
-#if defined(CFG_CS4_CFG)
- *(vu_long *)MPC5XXX_CS4_CFG = CFG_CS4_CFG;
+#if defined(CONFIG_SYS_CS4_CFG)
+ *(vu_long *)MPC5XXX_CS4_CFG = CONFIG_SYS_CS4_CFG;
#endif
-#if defined(CFG_CS5_START) && defined(CFG_CS5_SIZE)
- *(vu_long *)MPC5XXX_CS5_START = START_REG(CFG_CS5_START);
- *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CFG_CS5_START, CFG_CS5_SIZE);
+#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
+ *(vu_long *)MPC5XXX_CS5_START = START_REG(CONFIG_SYS_CS5_START);
+ *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE);
addecr |= (1 << 21);
#endif
-#if defined(CFG_CS5_CFG)
- *(vu_long *)MPC5XXX_CS5_CFG = CFG_CS5_CFG;
+#if defined(CONFIG_SYS_CS5_CFG)
+ *(vu_long *)MPC5XXX_CS5_CFG = CONFIG_SYS_CS5_CFG;
#endif
#if defined(CONFIG_MPC5200)
addecr |= 1;
-#if defined(CFG_CS6_START) && defined(CFG_CS6_SIZE)
- *(vu_long *)MPC5XXX_CS6_START = START_REG(CFG_CS6_START);
- *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CFG_CS6_START, CFG_CS6_SIZE);
+#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
+ *(vu_long *)MPC5XXX_CS6_START = START_REG(CONFIG_SYS_CS6_START);
+ *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE);
addecr |= (1 << 26);
#endif
-#if defined(CFG_CS6_CFG)
- *(vu_long *)MPC5XXX_CS6_CFG = CFG_CS6_CFG;
+#if defined(CONFIG_SYS_CS6_CFG)
+ *(vu_long *)MPC5XXX_CS6_CFG = CONFIG_SYS_CS6_CFG;
#endif
-#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
- *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
- *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
+#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
+ *(vu_long *)MPC5XXX_CS7_START = START_REG(CONFIG_SYS_CS7_START);
+ *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE);
addecr |= (1 << 27);
#endif
-#if defined(CFG_CS7_CFG)
- *(vu_long *)MPC5XXX_CS7_CFG = CFG_CS7_CFG;
+#if defined(CONFIG_SYS_CS7_CFG)
+ *(vu_long *)MPC5XXX_CS7_CFG = CONFIG_SYS_CS7_CFG;
#endif
-#if defined(CFG_CS_BURST)
- *(vu_long *)MPC5XXX_CS_BURST = CFG_CS_BURST;
+#if defined(CONFIG_SYS_CS_BURST)
+ *(vu_long *)MPC5XXX_CS_BURST = CONFIG_SYS_CS_BURST;
#endif
-#if defined(CFG_CS_DEADCYCLE)
- *(vu_long *)MPC5XXX_CS_DEADCYCLE = CFG_CS_DEADCYCLE;
+#if defined(CONFIG_SYS_CS_DEADCYCLE)
+ *(vu_long *)MPC5XXX_CS_DEADCYCLE = CONFIG_SYS_CS_DEADCYCLE;
#endif
#endif /* CONFIG_MPC5200 */
@@ -144,8 +144,8 @@
*(vu_long *)MPC5XXX_CS_CTRL = (1 << 24);
/* Setup pin multiplexing */
-#if defined(CFG_GPS_PORT_CONFIG)
- *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CFG_GPS_PORT_CONFIG;
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
+ *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CONFIG_SYS_GPS_PORT_CONFIG;
#endif
#if defined(CONFIG_MPC5200)
@@ -154,28 +154,28 @@
/* Enable snooping for RAM */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
- *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
+ *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_SYS_SDRAM_BASE | 0x1d;
-# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/* Motorola reports IPB should better run at 133 MHz. */
*(vu_long *)MPC5XXX_ADDECR |= 1;
/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
addecr = *(vu_long *)MPC5XXX_CDM_CFG;
addecr &= ~0x103;
-# if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
+# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
addecr |= 0x01;
# else
/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
addecr |= 0x02;
-# endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
+# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
*(vu_long *)MPC5XXX_CDM_CFG = addecr;
-# endif /* CFG_IPBCLK_EQUALS_XLBCLK */
+# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
/* Configure the XLB Arbiter */
*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
-# if defined(CFG_XLB_PIPELINING)
+# if defined(CONFIG_SYS_XLB_PIPELINING)
/* Enable piplining */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
# endif
diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
index a07c776..d140c7e 100644
--- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
+++ b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
@@ -23,7 +23,7 @@
.long 0x00000000
.long 0x00000000
.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */
-.long CFG_MBAR
+.long CONFIG_SYS_MBAR
.globl scEthernetXmit_Entry
scEthernetXmit_Entry: /* Task 1 */
.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */
@@ -33,7 +33,7 @@
.long 0x00000000
.long 0x00000000
.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */
-.long CFG_MBAR
+.long CONFIG_SYS_MBAR
.globl scEthernetRecv_TDT
@@ -151,7 +151,7 @@
.long 0x00000000 /* var[6] */
.long 0x00000000 /* var[7] */
.long 0x00000000 /* var[8] */
-.long (CFG_MBAR + 0x8800) /* var[9] */
+.long (CONFIG_SYS_MBAR + 0x8800) /* var[9] */
.long 0x00000008 /* var[10] */
.long 0x0000000c /* var[11] */
.long 0x80000000 /* var[12] */
@@ -190,7 +190,7 @@
.long 0x00000000 /* var[8] */
.long 0x00000000 /* var[9] */
.long 0x00000000 /* var[10] */
-.long (CFG_MBAR + 0x8800) /* var[11] */
+.long (CONFIG_SYS_MBAR + 0x8800) /* var[11] */
.long 0x00000000 /* var[12] */
.long 0x80000000 /* var[13] */
.long 0x10000000 /* var[14] */
diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c
index 0f02e78..4d16bbe 100644
--- a/cpu/mpc5xxx/i2c.c
+++ b/cpu/mpc5xxx/i2c.c
@@ -30,12 +30,12 @@
#include <mpc5xxx.h>
#include <i2c.h>
-#if (CFG_I2C_MODULE == 2)
+#if (CONFIG_SYS_I2C_MODULE == 2)
#define I2C_BASE MPC5XXX_I2C2
-#elif (CFG_I2C_MODULE == 1)
+#elif (CONFIG_SYS_I2C_MODULE == 1)
#define I2C_BASE MPC5XXX_I2C1
#else
-#error CFG_I2C_MODULE is not properly configured
+#error CONFIG_SYS_I2C_MODULE is not properly configured
#endif
#define I2C_TIMEOUT 100
diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c
index 8816dd1..6035771 100644
--- a/cpu/mpc5xxx/interrupts.c
+++ b/cpu/mpc5xxx/interrupts.c
@@ -229,7 +229,7 @@
int interrupt_init_cpu(ulong * decrementer_count)
{
- *decrementer_count = get_tbclk() / CFG_HZ;
+ *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
mpc5xxx_init_irq();
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 2f01d5c..a3251ab 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -31,8 +31,8 @@
#include <mpc5xxx.h>
/* System RAM mapped over PCI */
-#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
-#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
/* PCIIWCR bit fields */
@@ -125,11 +125,11 @@
/* Set cache line size */
*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
- (CFG_CACHELINE_SIZE / 4);
+ (CONFIG_SYS_CACHELINE_SIZE / 4);
/* Map MBAR to PCI space */
- *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
- *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1;
+ *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
+ *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;
/* Map RAM to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c
index 430d63f..a8a384a 100644
--- a/cpu/mpc5xxx/serial.c
+++ b/cpu/mpc5xxx/serial.c
@@ -106,7 +106,7 @@
/* select clock sources */
#if defined(CONFIG_MGT5100)
psc->psc_clock_select = 0xdd00;
- baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
+ baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
#elif defined(CONFIG_MPC5200)
psc->psc_clock_select = 0;
baseclk = (gd->ipb_clk + 16) / 32;
@@ -247,7 +247,7 @@
unsigned long baseclk, div;
#if defined(CONFIG_MGT5100)
- baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
+ baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
#elif defined(CONFIG_MPC5200)
baseclk = (gd->ipb_clk + 16) / 32;
#endif
diff --git a/cpu/mpc5xxx/speed.c b/cpu/mpc5xxx/speed.c
index 7847adc..0e3e552 100644
--- a/cpu/mpc5xxx/speed.c
+++ b/cpu/mpc5xxx/speed.c
@@ -47,15 +47,15 @@
{
ulong val, vco;
-#if !defined(CFG_MPC5XXX_CLKIN)
-#error clock measuring not implemented yet - define CFG_MPC5XXX_CLKIN
+#if !defined(CONFIG_SYS_MPC5XXX_CLKIN)
+#error clock measuring not implemented yet - define CONFIG_SYS_MPC5XXX_CLKIN
#endif
val = *(vu_long *)MPC5XXX_CDM_PORCFG;
if (val & (1 << 6)) {
- vco = CFG_MPC5XXX_CLKIN * 12;
+ vco = CONFIG_SYS_MPC5XXX_CLKIN * 12;
} else {
- vco = CFG_MPC5XXX_CLKIN * 16;
+ vco = CONFIG_SYS_MPC5XXX_CLKIN * 16;
}
if (val & (1 << 5)) {
gd->bus_clk = vco / 8;
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index 9b1bd48..defe77d 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -106,19 +106,19 @@
/* Move CSBoot and adjust instruction pointer */
/*--------------------------------------------------------------*/
-#if defined(CFG_LOWBOOT)
-# if defined(CFG_RAMBOOT)
-# error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
-# endif /* CFG_RAMBOOT */
+#if defined(CONFIG_SYS_LOWBOOT)
+# if defined(CONFIG_SYS_RAMBOOT)
+# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
+# endif /* CONFIG_SYS_RAMBOOT */
# if defined(CONFIG_MGT5100)
-# error CFG_LOWBOOT is incompatible with MGT5100
+# error CONFIG_SYS_LOWBOOT is incompatible with MGT5100
# endif /* CONFIG_MGT5100 */
- lis r4, CFG_DEFAULT_MBAR@h
- lis r3, START_REG(CFG_BOOTCS_START)@h
- ori r3, r3, START_REG(CFG_BOOTCS_START)@l
+ lis r4, CONFIG_SYS_DEFAULT_MBAR@h
+ lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
+ ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
stw r3, 0x4(r4) /* CS0 start */
- lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
- ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+ lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
+ ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
stw r3, 0x8(r4) /* CS0 stop */
lis r3, 0x02010000@h
ori r3, r3, 0x02010000@l
@@ -130,20 +130,20 @@
blr
lowboot_reentry:
- lis r3, START_REG(CFG_BOOTCS_START)@h
- ori r3, r3, START_REG(CFG_BOOTCS_START)@l
+ lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
+ ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
stw r3, 0x4c(r4) /* Boot start */
- lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
- ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+ lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
+ ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
stw r3, 0x50(r4) /* Boot stop */
lis r3, 0x02000001@h
ori r3, r3, 0x02000001@l
stw r3, 0x54(r4) /* Boot enable, CS0 disable */
-#endif /* CFG_LOWBOOT */
+#endif /* CONFIG_SYS_LOWBOOT */
-#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
- lis r3, CFG_MBAR@h
- ori r3, r3, CFG_MBAR@l
+#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
+ lis r3, CONFIG_SYS_MBAR@h
+ ori r3, r3, CONFIG_SYS_MBAR@l
#if defined(CONFIG_MPC5200)
/* MBAR is mirrored into the MBAR SPR */
mtspr MBAR,r3
@@ -152,9 +152,9 @@
#if defined(CONFIG_MGT5100)
rlwinm r3, r3, 17, 15, 31
#endif
- lis r4, CFG_DEFAULT_MBAR@h
+ lis r4, CONFIG_SYS_DEFAULT_MBAR@h
stw r3, 0(r4)
-#endif /* CFG_DEFAULT_MBAR */
+#endif /* CONFIG_SYS_DEFAULT_MBAR */
/* Initialise the MPC5xxx processor core */
/*--------------------------------------------------------------*/
@@ -165,9 +165,9 @@
/*--------------------------------------------------------------*/
/* set up stack in on-chip SRAM */
- lis r3, CFG_INIT_RAM_ADDR@h
- ori r3, r3, CFG_INIT_RAM_ADDR@l
- ori r1, r3, CFG_INIT_SP_OFFSET
+ lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
+ ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
@@ -400,13 +400,13 @@
/* HID0 also contains cache control */
/*--------------------------------------------------------------*/
- lis r3, CFG_HID0_INIT@h
- ori r3, r3, CFG_HID0_INIT@l
+ lis r3, CONFIG_SYS_HID0_INIT@h
+ ori r3, r3, CONFIG_SYS_HID0_INIT@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID0_FINAL@h
- ori r3, r3, CFG_HID0_FINAL@l
+ lis r3, CONFIG_SYS_HID0_FINAL@h
+ ori r3, r3, CONFIG_SYS_HID0_FINAL@l
SYNC
mtspr HID0, r3
@@ -582,16 +582,16 @@
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
diff --git a/cpu/mpc5xxx/usb.c b/cpu/mpc5xxx/usb.c
index ed467ab..8f2b66a 100644
--- a/cpu/mpc5xxx/usb.c
+++ b/cpu/mpc5xxx/usb.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
#include <mpc5xxx.h>
@@ -51,4 +51,4 @@
return 0;
}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */