diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
index 5738c5b..351aed1 100644
--- a/board/prodrive/pdnb3/flash.c
+++ b/board/prodrive/pdnb3/flash.c
@@ -52,7 +52,7 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; i++)
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++)
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -66,20 +66,20 @@
 
 	/* Monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
-		      &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		      CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	/* Environment protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CONFIG_ENV_ADDR,
 		      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	/* Redundant environment protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CONFIG_ENV_ADDR_REDUND,
 		      CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
-		      &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	flash_info[0].size = size;
 
diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
index 1ce3c8c..2efe027 100644
--- a/board/prodrive/pdnb3/nand.c
+++ b/board/prodrive/pdnb3/nand.c
@@ -136,7 +136,7 @@
 
 int board_nand_init(struct nand_chip *nand)
 {
-	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
+	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
 
 	nand->ecc.mode = NAND_ECC_SOFT;
 
diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c
index 3445a3a..3773ba1 100644
--- a/board/prodrive/pdnb3/pdnb3.c
+++ b/board/prodrive/pdnb3/pdnb3.c
@@ -34,8 +34,8 @@
 
 /* predefine these here for FPGA programming (before including fpga.c) */
 #define SET_FPGA(data)	*IXP425_GPIO_GPOUTR = (data)
-#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_DONE)
-#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_INIT)
+#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
 #define OLD_VAL		old_val
 
 static unsigned long old_val = 0;
@@ -56,46 +56,46 @@
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
 
-	GPIO_OUTPUT_SET(CFG_GPIO_SYS_RUNNING);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_SYS_RUNNING);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
 
 	/*
 	 * Setup GPIO's for FPGA programming
 	 */
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG);
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK);
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_PRG);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_DATA);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_INIT);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_DONE);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
 
 	/*
 	 * Setup GPIO's for interrupts
 	 */
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTORE_INT);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTORE_INT);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTART_INT);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTART_INT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
 
 	/*
 	 * Setup GPIO's for 33MHz clock output
 	 */
 	*IXP425_GPIO_GPCLKR = 0x01FF0000;
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK_33M);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
 
 	/*
 	 * Setup other chip select's
 	 */
-	*IXP425_EXP_CS1 = CFG_EXP_CS1;
+	*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
 
 	return 0;
 }
@@ -132,14 +132,14 @@
 	int status;
 	int index;
 	int i;
-	ulong len = CFG_MALLOC_LEN;
+	ulong len = CONFIG_SYS_MALLOC_LEN;
 
 	/*
 	 * Setup GPIO's for FPGA programming
 	 */
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG);
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK);
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
 
 	/*
 	 * Save value so no readback is required upon programming
@@ -149,8 +149,8 @@
 	/*
 	 * First try to decompress fpga image (gzip compressed?)
 	 */
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf("Error: Image has to be gzipp'ed!\n");
 		return -1;
 	}
@@ -204,9 +204,9 @@
 	/*
 	 * Reset FPGA
 	 */
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
 	udelay(10);
-	GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
 
 	return (0);
 }