commit 03836942b412415379651f656e7d33fe02e408de
author Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Thu Oct 16 15:01:15 2008 +0200
committer Wolfgang Denk <wd@denx.de> Sat Oct 18 21:54:03 2008 +0200
tree ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f
parent 8aee9358b0c08cfcf6c070318beac1e409b88a73

rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

board/freescale/m5373evb/m5373evb.c

diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index a269ee6..376de4b 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -42,7 +42,7 @@
 	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
@@ -50,29 +50,29 @@
 	}
 	i--;
 
-	sdram->cs0 = (CFG_SDRAM_BASE | i);
-	sdram->cfg1 = CFG_SDRAM_CFG1;
-	sdram->cfg2 = CFG_SDRAM_CFG2;
+	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
 
 	/* Issue PALL */
-	sdram->ctrl = CFG_SDRAM_CTRL | 2;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
 
 	/* Issue LEMR */
-	sdram->mode = CFG_SDRAM_EMOD;
-	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
 
-	sdram->mode = CFG_SDRAM_MODE;
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
 
-	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
 
 	udelay(100);
 

board/freescale/m5373evb/mii.c

diff --git a/board/freescale/m5373evb/mii.c b/board/freescale/m5373evb/mii.c
index 8f6abf3..c0f5817 100644
--- a/board/freescale/m5373evb/mii.c
+++ b/board/freescale/m5373evb/mii.c
@@ -50,7 +50,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -134,9 +134,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -201,7 +201,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 

board/freescale/m5373evb/nand.c

diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index 404a9c3..d01b819 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -67,7 +67,7 @@
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
 
-	*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
+	*((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
 	fbcs->csmr2 &= ~FBCS_CSMR_WP;
 
 	/* set up pin configuration */