diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c
index 04c35bc..330978b 100644
--- a/board/emk/common/flash.c
+++ b/board/emk/common/flash.c
@@ -26,7 +26,7 @@
 
 #include <common.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 #if defined (CONFIG_TOP860)
   typedef unsigned short FLASH_PORT_WIDTH;
@@ -95,7 +95,7 @@
 	int i = 0;
 	extern void flash_preinit(void);
 	extern void flash_afterinit(uint, ulong, ulong);
-	ulong flashbase = CFG_FLASH_BASE;
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
 
 	flash_preinit();
 
@@ -105,12 +105,12 @@
 			flash_get_size((FPW *)flashbase, &flash_info[i]);
 	size += flash_info[i].size;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CFG_MONITOR_BASE));
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -147,14 +147,14 @@
 	int i;
 	flash_info_t * info;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
 		if (info->size &&
 			info->start[0] <= base && base <= info->start[0] + info->size - 1)
 			break;
 	}
 
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
 }
 
 /*-----------------------------------------------------------------------
@@ -459,7 +459,7 @@
 		udelay (1000);
 
 		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 
 				if (intel) {
@@ -473,14 +473,14 @@
 			}
 
 			/* show that we're waiting */
-			if ((get_timer(last)) > CFG_HZ) {/* every second */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
 				putc ('.');
 				last = get_timer(0);
 			}
 		}
 
 		/* show that we're waiting */
-		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
 			putc ('.');
 			last = get_timer(0);
 		}
@@ -581,7 +581,7 @@
 
 	/* data polling for D7 */
 	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW)0x00F000F0;	/* reset bank */
 			res = 1;
 		}
diff --git a/board/emk/common/vpd.c b/board/emk/common/vpd.c
index 8a3a12b..c2af219 100644
--- a/board/emk/common/vpd.c
+++ b/board/emk/common/vpd.c
@@ -36,8 +36,8 @@
 	uint len;
 
 	/* get length first */
-	addr = CFG_FACT_OFFSET;
-	if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2)) {
+	addr = CONFIG_SYS_FACT_OFFSET;
+	if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, 2)) {
 	  bailout:
 		printf ("cannot read factory configuration\n");
 		printf ("be sure to set ethaddr	yourself!\n");
@@ -47,14 +47,14 @@
 	addr += 2;
 
 	/* sanity check */
-	if (length < 20 || length > CFG_FACT_SIZE - 2)
+	if (length < 20 || length > CONFIG_SYS_FACT_SIZE - 2)
 		goto bailout;
 
 	/* read lines */
 	while (length > 0) {
 		/* read one line */
 		len = length > 80 ? 80 : length;
-		if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len))
+		if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, len))
 			goto bailout;
 		/* mark end of buffer */
 		buf[len] = 0;
diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c
index 2788626..7efbcb0 100644
--- a/board/emk/top5200/top5200.c
+++ b/board/emk/top5200/top5200.c
@@ -35,7 +35,7 @@
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #if 0
 	ulong	t;
 	ulong	tap_del;
@@ -46,33 +46,33 @@
 	#define	SOFT_REF	4
 
 	/* configure SDRAM start/end */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE;
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
 
 	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2;
 
 	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN;
 	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
-#ifdef CFG_DRAM_DDR
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+#ifdef CONFIG_SYS_DRAM_DDR
 	/* set extended mode register */
-	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE;
 #endif
 	/* set mode register */
-	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400;
 	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
 	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF;
 	/* set mode register */
-	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE;
 	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL;
 	/* write default TAP delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
+	*(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24;
 
 #if 0
 	for (tap_del = 0; tap_del < 32; tap_del++)
@@ -97,7 +97,7 @@
 		}
 	}
 #endif
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
 
diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c
index aca4991..76f7a0c 100644
--- a/board/emk/top860/top860.c
+++ b/board/emk/top860/top860.c
@@ -78,7 +78,7 @@
  *****************************************************************************/
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	/*
@@ -93,8 +93,8 @@
 			   sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
 		memctl->memc_mptpr = 0x0200;
 		memctl->memc_mamr = 0x0ca20330;
-		memctl->memc_or2 = -CFG_DRAM_MAX | OR_CSNT_SAM;
-		memctl->memc_br2 = CFG_DRAM_BASE | BR_MS_UPMA | BR_V;
+		memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM;
+		memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V;
 		/*
 		 * Do 8 read accesses to DRAM
 		 */
@@ -112,7 +112,7 @@
 		addr2[1] = 0x47110815;
 		if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) {
 			/* only 4MB populated */
-			memctl->memc_or2 = -(CFG_DRAM_MAX / 4) | OR_CSNT_SAM;
+			memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM;
 		}
 	}