rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/board/eltec/bab7xx/asm_init.S b/board/eltec/bab7xx/asm_init.S
index 2a9b33e..a85fb8b 100644
--- a/board/eltec/bab7xx/asm_init.S
+++ b/board/eltec/bab7xx/asm_init.S
@@ -125,7 +125,7 @@
lis r2, 0xfee0
ori r2, r2, 0xcfc
-#ifdef CFG_ADDRESS_MAP_A
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
/*
* Switch to address map A if necessary.
*/
@@ -835,17 +835,17 @@
/*
* Get base addr of ISA I/O space
*/
- lis r6, CFG_ISA_IO@h
- ori r6, r6, CFG_ISA_IO@l
+ lis r6, CONFIG_SYS_ISA_IO@h
+ ori r6, r6, CONFIG_SYS_ISA_IO@l
/*
* Set offset to base address for config registers.
*/
-#if defined(CFG_NS87308_BADDR_0x)
+#if defined(CONFIG_SYS_NS87308_BADDR_0x)
addi r4, r0, 0x0279
-#elif defined(CFG_NS87308_BADDR_10)
+#elif defined(CONFIG_SYS_NS87308_BADDR_10)
addi r4, r0, 0x015C
-#elif defined(CFG_NS87308_BADDR_11)
+#elif defined(CONFIG_SYS_NS87308_BADDR_11)
addi r4, r0, 0x002E
#endif
add r6, r6, r4 /* add offset to base */
@@ -867,7 +867,7 @@
addi r5, r0, SIO_LUNENABLE
bl .sio_bw
- lis r8, CFG_ISA_IO@h
+ lis r8, CONFIG_SYS_ISA_IO@h
ori r8, r8, 0x0460
li r9, 0x03
stb r9, 0(r8) /* select PMC2 register */
@@ -898,7 +898,7 @@
/*
* Init COM1 for polled output
*/
- lis r8, CFG_ISA_IO@h
+ lis r8, CONFIG_SYS_ISA_IO@h
ori r8, r8, 0x03f8
li r9, 0x00
stb r9, 1(r8) /* int disabled */
@@ -972,8 +972,8 @@
/*
* Get base addr of ISA I/O space
*/
- lis r3, CFG_ISA_IO@h
- ori r3, r3, CFG_ISA_IO@l
+ lis r3, CONFIG_SYS_ISA_IO@h
+ ori r3, r3, CONFIG_SYS_ISA_IO@l
addi r3, r3, 0x015C /* adjust to superI/O 87308 base */
or r6, r3, r3 /* make a copy */
@@ -1076,7 +1076,7 @@
*/
.globl Printf
Printf:
- lis r10, CFG_ISA_IO@h /* COM1 port */
+ lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
WaitChr:
@@ -1107,7 +1107,7 @@
OutHex:
li r9, 28 /* shift reg for 8 digits */
OHstart:
- lis r10, CFG_ISA_IO@h /* COM1 port */
+ lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
OutDig:
lbz r0, 5(r10) /* read link status */
@@ -1149,7 +1149,7 @@
mullw r10, r0, r6
subf r7, r10, r3
- lis r10, CFG_ISA_IO@h /* COM1 port */
+ lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
or. r7, r7, r7
@@ -1198,7 +1198,7 @@
*/
.globl OutChr
OutChr:
- lis r10, CFG_ISA_IO@h /* COM1 port */
+ lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
OutChr1:
@@ -1216,7 +1216,7 @@
spdRead:
mfspr r26, 8 /* save link register */
- lis r30, CFG_ISA_IO@h
+ lis r30, CONFIG_SYS_ISA_IO@h
ori r30, r30, 0x220 /* GPIO Port 1 */
li r7, 0x00
li r8, 0x100
diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c
index 8c56116..1f78f8d 100644
--- a/board/eltec/bab7xx/bab7xx.c
+++ b/board/eltec/bab7xx/bab7xx.c
@@ -44,7 +44,7 @@
* The GPIO Port 1 on BAB7xx reflects the bus speed.
*/
volatile struct GPIO *gpio =
- (struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
+ (struct GPIO *) (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_GPIO_BASE);
unsigned char data = gpio->dta1;
@@ -87,7 +87,7 @@
int checkboard (void)
{
-#ifdef CFG_ADDRESS_MAP_A
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
puts ("Board: ELTEC BAB7xx PReP\n");
#else
puts ("Board: ELTEC BAB7xx CHRP\n");
@@ -126,16 +126,16 @@
register unsigned long i, msar1, mear1, memSize;
-#if defined(CFG_MEMTEST)
+#if defined(CONFIG_SYS_MEMTEST)
register unsigned long reg;
printf ("Testing DRAM\n");
/* write each mem addr with it's address */
- for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
+ for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
*reg = reg;
- for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
+ for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
if (*reg != reg)
return -1;
}
diff --git a/board/eltec/bab7xx/flash.c b/board/eltec/bab7xx/flash.c
index 442dd00..21ae098 100644
--- a/board/eltec/bab7xx/flash.c
+++ b/board/eltec/bab7xx/flash.c
@@ -34,7 +34,7 @@
#include <asm/processor.h>
#include <asm/pci_io.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
@@ -55,7 +55,7 @@
int i;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
{
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -96,8 +96,8 @@
if (size2 == 4*1024*1024)
{
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+monitor_flash_len-1,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
&flash_info[1]);
}
@@ -370,7 +370,7 @@
last = start;
addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@@ -500,7 +500,7 @@
start = get_timer (0);
while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
diff --git a/board/eltec/bab7xx/l2cache.c b/board/eltec/bab7xx/l2cache.c
index 1e75377..787704f 100644
--- a/board/eltec/bab7xx/l2cache.c
+++ b/board/eltec/bab7xx/l2cache.c
@@ -23,7 +23,7 @@
#include <common.h>
-#if defined(CFG_L2_BAB7xx)
+#if defined(CONFIG_SYS_L2_BAB7xx)
#include <pci.h>
#include <mpc106.h>
@@ -77,7 +77,7 @@
pci_write_config_dword (devbusfn, PCI_PICR2, reg32);
/* cache size */
- if (*(volatile unsigned char *) (CFG_ISA_IO + 0x220) & 0x04)
+ if (*(volatile unsigned char *) (CONFIG_SYS_ISA_IO + 0x220) & 0x04)
{
/* cache size is 512 KB */
picr2CacheSize = PICR2_L2_SIZE_512K;
@@ -156,4 +156,4 @@
/*----------------------------------------------------------------------------*/
-#endif /* (CFG_L2_BAB7xx) */
+#endif /* (CONFIG_SYS_L2_BAB7xx) */
diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c
index 6a24807..1c94a76 100644
--- a/board/eltec/bab7xx/misc.c
+++ b/board/eltec/bab7xx/misc.c
@@ -31,7 +31,7 @@
#include "srom.h"
/* imports */
-extern char console_buffer[CFG_CBSIZE];
+extern char console_buffer[CONFIG_SYS_CBSIZE];
extern int l2_cache_enable (int l2control);
extern void *nvram_read (void *dest, const short src, size_t count);
extern void nvram_write (short dest, const void *src, size_t count);
@@ -134,7 +134,7 @@
SECOND_DEVICE, FIRST_BLOCK);
/* read out current nvram shadow image */
- nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
+ nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
if (strcmp (eerev.magic, "ELTEC") != 0)
{
@@ -162,8 +162,8 @@
copyNv = 1; /* copy to nvram */
}
- if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) !=
- el_srom_checksum((u_char*)buf, CFG_SROM_SIZE)))
+ if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CONFIG_SYS_SROM_SIZE) !=
+ el_srom_checksum((u_char*)buf, CONFIG_SYS_SROM_SIZE)))
{
printf ("Invalid revision info copy in nvram !\n");
printf ("Press key:\n <c> to copy current revision info to nvram.\n");
@@ -304,13 +304,13 @@
printf("OK\n\n");
/* write new values as shadow image to nvram */
- nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
+ nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
} /*if (initSrom) */
/* copy current values as shadow image to nvram */
if (initSrom == 0 && copyNv == 1)
- nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
+ nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
/* update environment */
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
@@ -333,7 +333,7 @@
/*
* L2 cache configuration
*/
-#if defined(CFG_L2_BAB7xx)
+#if defined(CONFIG_SYS_L2_BAB7xx)
ptr = getenv("l2cache");
if (*ptr == '0')
{
diff --git a/board/eltec/bab7xx/pci.c b/board/eltec/bab7xx/pci.c
index edbd3dd..46e5a8b 100644
--- a/board/eltec/bab7xx/pci.c
+++ b/board/eltec/bab7xx/pci.c
@@ -43,41 +43,41 @@
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
/*
* Attention: pci_hose_phys_to_bus() failes in address compare,
- * so we need (CFG_PCI_MEMORY_SIZE-1)
+ * so we need (CONFIG_SYS_PCI_MEMORY_SIZE-1)
*/
- CFG_PCI_MEMORY_SIZE-1,
+ CONFIG_SYS_PCI_MEMORY_SIZE-1,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
- CFG_PCI_MEM_BUS,
- CFG_PCI_MEM_PHYS,
- CFG_PCI_MEM_SIZE,
+ CONFIG_SYS_PCI_MEM_BUS,
+ CONFIG_SYS_PCI_MEM_PHYS,
+ CONFIG_SYS_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* ISA/PCI memory space */
pci_set_region(hose->regions + 2,
- CFG_ISA_MEM_BUS,
- CFG_ISA_MEM_PHYS,
- CFG_ISA_MEM_SIZE,
+ CONFIG_SYS_ISA_MEM_BUS,
+ CONFIG_SYS_ISA_MEM_PHYS,
+ CONFIG_SYS_ISA_MEM_SIZE,
PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region(hose->regions + 3,
- CFG_PCI_IO_BUS,
- CFG_PCI_IO_PHYS,
- CFG_PCI_IO_SIZE,
+ CONFIG_SYS_PCI_IO_BUS,
+ CONFIG_SYS_PCI_IO_PHYS,
+ CONFIG_SYS_PCI_IO_SIZE,
PCI_REGION_IO);
/* ISA/PCI I/O space */
pci_set_region(hose->regions + 4,
- CFG_ISA_IO_BUS,
- CFG_ISA_IO_PHYS,
- CFG_ISA_IO_SIZE,
+ CONFIG_SYS_ISA_IO_BUS,
+ CONFIG_SYS_ISA_IO_PHYS,
+ CONFIG_SYS_ISA_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 5;
diff --git a/board/eltec/bab7xx/srom.h b/board/eltec/bab7xx/srom.h
index c18ab91..504b742 100644
--- a/board/eltec/bab7xx/srom.h
+++ b/board/eltec/bab7xx/srom.h
@@ -40,8 +40,8 @@
#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
/* bab7xx ELTEC srom */
-#define I2C_BUS_DAT (CFG_ISA_IO + 0x220)
-#define I2C_BUS_DIR (CFG_ISA_IO + 0x221)
+#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220)
+#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221)
/* srom at mpc107 */
#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */
diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S
index 1b8d399..8cbe9d8 100644
--- a/board/eltec/elppc/asm_init.S
+++ b/board/eltec/elppc/asm_init.S
@@ -272,15 +272,15 @@
* set LEDs first time
*/
li r3, 0x1
- lis r30, CFG_USR_LED_BASE@h
+ lis r30, CONFIG_SYS_USR_LED_BASE@h
stb r3, 2(r30)
sync
/*
* init COM1 for polled output
*/
- lis r8, CFG_NS16550_COM1@h /* COM1 base address*/
- ori r8, r8, CFG_NS16550_COM1@l
+ lis r8, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r8, r8, CONFIG_SYS_NS16550_COM1@l
li r9, 0x00
stb r9, 1(r8) /* int disabled */
eieio
@@ -290,10 +290,10 @@
li r9, 0x80
stb r9, 3(r8) /* link ctrl */
eieio
- li r9, (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE)
+ li r9, (CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE)
stb r9, 0(r8) /* baud rate (LSB)*/
eieio
- li r9, ((CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8)
+ li r9, ((CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8)
stb r9, 1(r8) /* baud rate (MSB) */
eieio
li r9, 0x07
@@ -589,7 +589,7 @@
* set LEDs end
*/
li r3, 0xf
- lis r30, CFG_USR_LED_BASE@h
+ lis r30, CONFIG_SYS_USR_LED_BASE@h
stb r3, 2(r30)
sync
@@ -602,8 +602,8 @@
*/
Printf:
- lis r10, CFG_NS16550_COM1@h /* COM1 base address*/
- ori r10, r10, CFG_NS16550_COM1@l
+ lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r10, r10, CONFIG_SYS_NS16550_COM1@l
WaitChr:
lbz r0, 5(r10) /* read link status */
eieio
@@ -622,8 +622,8 @@
* print a char to COM1 in polling mode (r10=COM1 port, r3=char)
*/
OutChr:
- lis r10, CFG_NS16550_COM1@h /* COM1 base address*/
- ori r10, r10, CFG_NS16550_COM1@l
+ lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r10, r10, CONFIG_SYS_NS16550_COM1@l
OutChr1:
lbz r0, 5(r10) /* read link status */
eieio
@@ -645,8 +645,8 @@
OutHex:
li r9, 28 /* shift reg for 8 digits */
OHstart:
- lis r10, CFG_NS16550_COM1@h /* COM1 base address*/
- ori r10, r10, CFG_NS16550_COM1@l
+ lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r10, r10, CONFIG_SYS_NS16550_COM1@l
OutDig:
lbz r0, 0(r29) /* slow down dummy read */
lbz r0, 5(r10) /* read link status */
@@ -685,8 +685,8 @@
divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */
mullw r10, r0, r6
subf r7, r10, r3
- lis r10, CFG_NS16550_COM1@h /* COM1 base address*/
- ori r10, r10, CFG_NS16550_COM1@l
+ lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r10, r10, CONFIG_SYS_NS16550_COM1@l
or. r7, r7, r7
bne noblank1
li r3, 0x20
diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c
index d3ac278..e73c712 100644
--- a/board/eltec/elppc/elppc.c
+++ b/board/eltec/elppc/elppc.c
@@ -68,16 +68,16 @@
register unsigned long i, msar1, mear1, memSize;
-#if defined(CFG_MEMTEST)
+#if defined(CONFIG_SYS_MEMTEST)
register unsigned long reg;
printf ("Testing DRAM\n");
/* write each mem addr with it's address */
- for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
+ for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
*reg = reg;
- for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
+ for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
if (*reg != reg)
return -1;
}
diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c
index 442dd00..21ae098 100644
--- a/board/eltec/elppc/flash.c
+++ b/board/eltec/elppc/flash.c
@@ -34,7 +34,7 @@
#include <asm/processor.h>
#include <asm/pci_io.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
@@ -55,7 +55,7 @@
int i;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
{
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -96,8 +96,8 @@
if (size2 == 4*1024*1024)
{
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+monitor_flash_len-1,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
&flash_info[1]);
}
@@ -370,7 +370,7 @@
last = start;
addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@@ -500,7 +500,7 @@
start = get_timer (0);
while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c
index 5e3a81c..cbaf10b 100644
--- a/board/eltec/elppc/misc.c
+++ b/board/eltec/elppc/misc.c
@@ -29,7 +29,7 @@
#include "srom.h"
/* imports */
-extern char console_buffer[CFG_CBSIZE];
+extern char console_buffer[CONFIG_SYS_CBSIZE];
extern int l2_cache_enable (int l2control);
extern int eepro100_write_eeprom (struct eth_device *dev, int location,
int addr_len, unsigned short data);
@@ -95,7 +95,7 @@
SECOND_DEVICE, FIRST_BLOCK);
/* read out current nvram shadow image */
- nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
+ nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
if (strcmp (eerev.magic, "ELTEC") != 0) {
/* srom is not initialized -> create a default revision info */
@@ -124,8 +124,8 @@
}
if ((copyNv == 0)
- && (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) !=
- el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) {
+ && (el_srom_checksum ((u_char *) & eerev, CONFIG_SYS_SROM_SIZE) !=
+ el_srom_checksum ((u_char *) buf, CONFIG_SYS_SROM_SIZE))) {
printf ("Invalid revision info copy in nvram !\n");
printf ("Press key:\n <c> to copy current revision info to nvram.\n");
printf (" <r> to reenter revision info.\n");
@@ -232,16 +232,16 @@
printf ("OK\n\n");
/* write new values as shadow image to nvram */
- nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
- CFG_SROM_SIZE);
+ nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
+ CONFIG_SYS_SROM_SIZE);
}
/*if (initSrom) */
/* copy current values as shadow image to nvram */
if (initSrom == 0 && copyNv == 1)
- nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
- CFG_SROM_SIZE);
+ nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
+ CONFIG_SYS_SROM_SIZE);
/* update environment */
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c
index 5b115ea..bf133b7 100644
--- a/board/eltec/elppc/pci.c
+++ b/board/eltec/elppc/pci.c
@@ -42,37 +42,37 @@
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
- CFG_PCI_MEM_BUS,
- CFG_PCI_MEM_PHYS,
- CFG_PCI_MEM_SIZE,
+ CONFIG_SYS_PCI_MEM_BUS,
+ CONFIG_SYS_PCI_MEM_PHYS,
+ CONFIG_SYS_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* ISA/PCI memory space */
pci_set_region(hose->regions + 2,
- CFG_ISA_MEM_BUS,
- CFG_ISA_MEM_PHYS,
- CFG_ISA_MEM_SIZE,
+ CONFIG_SYS_ISA_MEM_BUS,
+ CONFIG_SYS_ISA_MEM_PHYS,
+ CONFIG_SYS_ISA_MEM_SIZE,
PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region(hose->regions + 3,
- CFG_PCI_IO_BUS,
- CFG_PCI_IO_PHYS,
- CFG_PCI_IO_SIZE,
+ CONFIG_SYS_PCI_IO_BUS,
+ CONFIG_SYS_PCI_IO_PHYS,
+ CONFIG_SYS_PCI_IO_SIZE,
PCI_REGION_IO);
/* ISA/PCI I/O space */
pci_set_region(hose->regions + 4,
- CFG_ISA_IO_BUS,
- CFG_ISA_IO_PHYS,
- CFG_ISA_IO_SIZE,
+ CONFIG_SYS_ISA_IO_BUS,
+ CONFIG_SYS_ISA_IO_PHYS,
+ CONFIG_SYS_ISA_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 5;
diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h
index c18ab91..504b742 100644
--- a/board/eltec/elppc/srom.h
+++ b/board/eltec/elppc/srom.h
@@ -40,8 +40,8 @@
#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
/* bab7xx ELTEC srom */
-#define I2C_BUS_DAT (CFG_ISA_IO + 0x220)
-#define I2C_BUS_DIR (CFG_ISA_IO + 0x221)
+#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220)
+#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221)
/* srom at mpc107 */
#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */
diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c
index 4cc66a9..2fbdb27 100644
--- a/board/eltec/mhpc/flash.c
+++ b/board/eltec/mhpc/flash.c
@@ -25,7 +25,7 @@
#include <mpc8xx.h>
#include <linux/byteorder/swab.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Protection Flags:
@@ -62,13 +62,13 @@
unsigned long flash_init (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0;
int i;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -81,18 +81,18 @@
}
/* Remap FLASH according to real size */
- memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+ memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+ memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
/* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+ size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+ flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+monitor_flash_len-1,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
&flash_info[0]);
flash_info[0].size = size_b0;
@@ -203,10 +203,10 @@
break;
}
- if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CFG_MAX_FLASH_SECT);
- info->sector_count = CFG_MAX_FLASH_SECT;
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = (FPW)0xFF00FF00; /* restore read mode */
@@ -277,7 +277,7 @@
udelay (1000);
while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW)0xB000B000; /* suspend erase */
*addr = (FPW)0xFF00FF00; /* reset to read mode */
@@ -419,7 +419,7 @@
start = get_timer (0);
while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW)0xFF00FF00; /* restore read mode */
return (1);
}
diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c
index 3666791..7cca6b2 100644
--- a/board/eltec/mhpc/mhpc.c
+++ b/board/eltec/mhpc/mhpc.c
@@ -36,7 +36,7 @@
#include <video_fb.h>
/* imports from common/main.c */
-extern char console_buffer[CFG_CBSIZE];
+extern char console_buffer[CONFIG_SYS_CBSIZE];
extern void eeprom_init (void);
extern int eeprom_read (unsigned dev_addr, unsigned offset,
@@ -105,7 +105,7 @@
int board_early_init_f (void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
@@ -160,7 +160,7 @@
int i;
/* check revision data */
- eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
+ eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
printf ("Enter revision number (0-9): %c ",
@@ -228,7 +228,7 @@
}
/* setup new revision data */
- eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
+ eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
32);
}
@@ -253,13 +253,13 @@
phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
- memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
+ memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */
memctl->memc_mptpr = MPTPR_PTP_DIV64;
memctl->memc_mar = 0x00008800;
@@ -267,15 +267,15 @@
/*
* Map controller SDRAM bank 0
*/
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
udelay (200);
/*
* Map controller SDRAM bank 1
*/
- memctl->memc_or2 = CFG_OR2;
- memctl->memc_br2 = CFG_BR2;
+ memctl->memc_or2 = CONFIG_SYS_OR2;
+ memctl->memc_br2 = CONFIG_SYS_BR2;
/*
* Perform SDRAM initializsation sequence
@@ -419,7 +419,7 @@
{
unsigned int clut = 0;
unsigned char *penv;
- immap_t *immr = (immap_t *) CFG_IMMR;
+ immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/* enable video only on CLUT value */
if ((penv = (uchar *)getenv ("clut")) != NULL)
@@ -470,7 +470,7 @@
unsigned char r, unsigned char g, unsigned char b)
{
unsigned int lum;
- unsigned short *pLut = (unsigned short *) (CFG_IMMR + 0x0e00);
+ unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00);
/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
/* y = 0.299*R + 0.587*G + 0.114*B */