rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c
index 49a8f71..33b4a6e 100644
--- a/board/alaska/alaska.c
+++ b/board/alaska/alaska.c
@@ -32,48 +32,48 @@
int blocksize = 0;
/* Flash 0 */
-#if defined (CFG_AMD_BOOT)
- batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+#if defined (CONFIG_SYS_AMD_BOOT)
+ batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
#else
- batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+ batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
#endif
- batl = CFG_FLASH0_BASE | 0x22;
+ batl = CONFIG_SYS_FLASH0_BASE | 0x22;
write_bat (IBAT0, batu, batl);
write_bat (DBAT0, batu, batl);
/* Flash 1 */
-#if defined (CFG_AMD_BOOT)
- batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+#if defined (CONFIG_SYS_AMD_BOOT)
+ batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
#else
- batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+ batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
#endif
- batl = CFG_FLASH1_BASE | 0x22;
+ batl = CONFIG_SYS_FLASH1_BASE | 0x22;
write_bat (IBAT1, batu, batl);
write_bat (DBAT1, batu, batl);
/* CPLD */
- batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
- batl = CFG_CPLD_BASE | 0x22;
+ batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+ batl = CONFIG_SYS_CPLD_BASE | 0x22;
write_bat (IBAT2, 0, 0);
write_bat (DBAT2, batu, batl);
/* FPGA */
- batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
- batl = CFG_FPGA_BASE | 0x22;
+ batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+ batl = CONFIG_SYS_FPGA_BASE | 0x22;
write_bat (IBAT3, 0, 0);
write_bat (DBAT3, batu, batl);
/* MBAR - Data only */
- batu = CFG_MBAR | BPP_RW | BPP_RX;
- batl = CFG_MBAR | 0x22;
+ batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
+ batl = CONFIG_SYS_MBAR | 0x22;
mtspr (IBAT4L, 0);
mtspr (IBAT4U, 0);
mtspr (DBAT4L, batl);
mtspr (DBAT4U, batu);
/* MBAR - SRAM */
- batu = CFG_SRAM_BASE | BPP_RW | BPP_RX;
- batl = CFG_SRAM_BASE | 0x42;
+ batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
+ batl = CONFIG_SYS_SRAM_BASE | 0x42;
mtspr (IBAT5L, batl);
mtspr (IBAT5U, batu);
mtspr (DBAT5L, batl);
@@ -93,8 +93,8 @@
blocksize = BL_256M << 2;
/* Memory */
- batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
- batl = CFG_SDRAM_BASE | 0x42;
+ batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
+ batl = CONFIG_SYS_SDRAM_BASE | 0x42;
mtspr (IBAT6L, batl);
mtspr (IBAT6U, batu);
mtspr (DBAT6L, batl);
@@ -120,9 +120,9 @@
else if (size <= 0x10000000) /* 256MB */
blocksize = BL_256M << 2;
- batu = (CFG_SDRAM_BASE +
+ batu = (CONFIG_SYS_SDRAM_BASE +
0x10000000) | blocksize | BPP_RW | BPP_RX;
- batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42;
+ batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
}
mtspr (IBAT7L, batl);
diff --git a/board/alaska/flash.c b/board/alaska/flash.c
index 556c168..aed3b6f 100644
--- a/board/alaska/flash.c
+++ b/board/alaska/flash.c
@@ -28,7 +28,7 @@
#include <linux/byteorder/swab.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#define FLASH_PORT_WIDTH8
@@ -86,30 +86,30 @@
ulong size = 0;
ulong fsize = 0;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
memset (&flash_info[i], 0, sizeof (flash_info_t));
switch (i) {
case 0:
- flash_get_size ((FPW *) CFG_FLASH1_BASE,
+ flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
&flash_info[i]);
- flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]);
+ flash_get_offsets (CONFIG_SYS_FLASH1_BASE, &flash_info[i]);
break;
case 1:
- flash_get_size ((FPW *) CFG_FLASH1_BASE,
+ flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
&flash_info[i]);
- fsize = CFG_FLASH1_BASE + flash_info[i - 1].size;
+ fsize = CONFIG_SYS_FLASH1_BASE + flash_info[i - 1].size;
flash_get_offsets (fsize, &flash_info[i]);
break;
case 2:
- flash_get_size ((FPW *) CFG_FLASH0_BASE,
+ flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
&flash_info[i]);
- flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]);
+ flash_get_offsets (CONFIG_SYS_FLASH0_BASE, &flash_info[i]);
break;
case 3:
- flash_get_size ((FPW *) CFG_FLASH0_BASE,
+ flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
&flash_info[i]);
- fsize = CFG_FLASH0_BASE + flash_info[i - 1].size;
+ fsize = CONFIG_SYS_FLASH0_BASE + flash_info[i - 1].size;
flash_get_offsets (fsize, &flash_info[i]);
break;
default:
@@ -124,23 +124,23 @@
/* Protect monitor and environment sectors
*/
-#if defined (CFG_AMD_BOOT)
+#if defined (CONFIG_SYS_AMD_BOOT)
flash_protect (FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[2]);
flash_protect (FLAG_PROTECT_SET,
- CFG_INTEL_BASE,
- CFG_INTEL_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_INTEL_BASE,
+ CONFIG_SYS_INTEL_BASE + monitor_flash_len - 1,
&flash_info[1]);
#else
flash_protect (FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[3]);
flash_protect (FLAG_PROTECT_SET,
- CFG_AMD_BASE,
- CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
+ CONFIG_SYS_AMD_BASE,
+ CONFIG_SYS_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
#endif
flash_protect (FLAG_PROTECT_SET,
@@ -294,10 +294,10 @@
break;
}
- if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CFG_MAX_FLASH_SECT);
- info->sector_count = CFG_MAX_FLASH_SECT;
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
if (value == (FPW) INTEL_ID_28F128J3A)
@@ -348,7 +348,7 @@
/*
* first, wait for the WSM to be finished. The rationale for
* waiting for the WSM to become idle for at most
- * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+ * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
* because of: (1) erase, (2) program or (3) lock bit
* configuration. So we just wait for the longest timeout of
* the (1)-(3), i.e. the erase timeout.
@@ -361,7 +361,7 @@
start = get_timer (0);
while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
- if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = (FPW) INTEL_RESET; /* restore read mode */
printf("WSM busy too long, can't get prot status\n");
return 1;
@@ -391,7 +391,7 @@
*/
static unsigned char same_chip_banks (int bank1, int bank2)
{
- unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = {
+ unsigned char same_chip[CONFIG_SYS_MAX_FLASH_BANKS][CONFIG_SYS_MAX_FLASH_BANKS] = {
{1, 1, 0, 0},
{1, 1, 0, 0},
{0, 0, 1, 1},
@@ -467,7 +467,7 @@
} else {
FPWV *base; /* first address in bank */
- base = (FPWV *) (CFG_AMD_BASE);
+ base = (FPWV *) (CONFIG_SYS_AMD_BASE);
base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
@@ -479,7 +479,7 @@
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
if (intel) {
*addr = (FPW) 0x00B000B0; /* suspend erase */
@@ -684,7 +684,7 @@
/* wait while polling the status register */
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
@@ -728,7 +728,7 @@
/* wait while polling the status register */
while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
@@ -746,7 +746,7 @@
/* wait while polling the status register */
while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
@@ -779,7 +779,7 @@
return (2);
}
- base = (FPWV *) (CFG_AMD_BASE);
+ base = (FPWV *) (CONFIG_SYS_AMD_BASE);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -799,7 +799,7 @@
/* data polling for D7 */
while (res == 0
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00F000F0; /* reset bank */
res = 1;
}
@@ -856,7 +856,7 @@
start = get_timer (0);
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
printf ("Flash lock bit operation timed out\n");
rc = 1;
break;
@@ -886,17 +886,17 @@
*/
/* find the current bank number */
- curr_bank = CFG_MAX_FLASH_BANKS + 1;
- for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) {
+ curr_bank = CONFIG_SYS_MAX_FLASH_BANKS + 1;
+ for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; ++j) {
if (&flash_info[j] == info) {
curr_bank = j;
}
}
- if (curr_bank == CFG_MAX_FLASH_BANKS + 1) {
+ if (curr_bank == CONFIG_SYS_MAX_FLASH_BANKS + 1) {
printf("Error: can't determine bank number!\n");
}
- for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) {
+ for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
if (!same_chip_banks(curr_bank, bank)) {
continue;
}
@@ -910,7 +910,7 @@
while ((*addr & INTEL_FINISHED) !=
INTEL_FINISHED) {
if (get_timer (start) >
- CFG_FLASH_UNLOCK_TOUT) {
+ CONFIG_SYS_FLASH_UNLOCK_TOUT) {
printf ("Flash lock bit operation timed out\n");
rc = 1;
break;