Merge branch 'master' of git://git.denx.de/u-boot-video
diff --git a/.mailmap b/.mailmap
index 2f32fe8..02dccfc 100644
--- a/.mailmap
+++ b/.mailmap
@@ -12,7 +12,7 @@
Andreas Bießmann <andreas.devel@googlemail.com>
Aneesh V <aneesh@ti.com>
Dirk Behme <dirk.behme@googlemail.com>
-Fabio Estevam <fabio.estevam@freescale.com>
+Fabio Estevam <fabio.estevam@nxp.com>
Jagan Teki <402jagan@gmail.com>
Jagan Teki <jaganna@gmail.com>
Jagan Teki <jaganna@xilinx.com>
@@ -28,4 +28,5 @@
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Wolfgang Denk <wdenk>
York Sun <yorksun@freescale.com>
+York Sun <york.sun@nxp.com>
Ćukasz Majewski <l.majewski@samsung.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 394be1e..b387207 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -93,12 +93,14 @@
F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/imx-common/
-ARM MARVELL KIRKWOOD
+ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
M: Prafulla Wadaskar <prafulla@marvell.com>
M: Luka Perkov <luka.perkov@sartura.hr>
+M: Stefan Roese <sr@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-marvell.git
F: arch/arm/mach-kirkwood/
+F: arch/arm/mach-mvebu/
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
@@ -107,6 +109,12 @@
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
+ARM ROCKCHIP
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+T: git git://git.denx.de/u-boot-rockchip.git
+F: arch/arm/mach-rockchip/
+
ARM SAMSUNG
M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
@@ -161,7 +169,7 @@
S: Maintained
T: git git://git.denx.de/u-boot-uniphier.git
F: arch/arm/mach-uniphier/
-F: configs/ph1_*_defconfig
+F: configs/uniphier_*_defconfig
N: uniphier
ARM ZYNQ
@@ -239,7 +247,7 @@
T: git git://git.denx.de/u-boot-freebsd.git
FREESCALE QORIQ
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-fsl-qoriq.git
@@ -308,13 +316,13 @@
F: arch/powerpc/include/asm/arch-mpc83xx/
POWERPC MPC85XX
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
POWERPC MPC86XX
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
diff --git a/Makefile b/Makefile
index 028f0be..5882c30 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@
VERSION = 2016
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@@ -915,18 +915,8 @@
u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
$(call if_changed,mkimage)
-# If the kwboot xmodem protocol is used, to boot U-Boot on the MVEBU
-# SoC's, the SPL U-Boot returns to the BootROM after it completes
-# the SDRAM setup. The BootROM expects no U-Boot header in the main
-# U-Boot image. So we need to combine SPL and u-boot.bin instead of
-# u-boot.img in this case.
-ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
-u-boot-spl.kwb: u-boot-dtb.bin spl/u-boot-spl.bin FORCE
- $(call if_changed,mkimage)
-else
u-boot-spl.kwb: u-boot-dtb.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
-endif
MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
@@ -1136,7 +1126,7 @@
$(call if_changed,mkimage)
ifeq ($(ARCH),arm)
-ifdef CONFIG_DM
+ifdef CONFIG_OF_CONTROL
UBOOT_BINLOAD := u-boot-dtb.img
else
UBOOT_BINLOAD := u-boot.img
diff --git a/README b/README
index 43f307f..ece4793 100644
--- a/README
+++ b/README
@@ -34,12 +34,14 @@
Makefile have been tested to some extent and can be considered
"working". In fact, many of them are used in production systems.
-In case of problems see the CHANGELOG and CREDITS files to find out
-who contributed the specific port. The boards.cfg file lists board
-maintainers.
+In case of problems see the CHANGELOG file to find out who contributed
+the specific port. In addition, there are various MAINTAINERS files
+scattered throughout the U-Boot source identifying the people or
+companies responsible for various boards and subsystems.
-Note: There is no CHANGELOG file in the actual U-Boot source tree;
-it can be created dynamically from the Git log using:
+Note: As of August, 2010, there is no longer a CHANGELOG file in the
+actual U-Boot source tree; however, it can be created dynamically
+from the Git log using:
make CHANGELOG
@@ -48,7 +50,7 @@
==================
In case you have questions about, problems with or contributions for
-U-Boot you should send a message to the U-Boot mailing list at
+U-Boot, you should send a message to the U-Boot mailing list at
<u-boot@lists.denx.de>. There is also an archive of previous traffic
on the mailing list - please search the archive before asking FAQ's.
Please see http://lists.denx.de/pipermail/u-boot and
@@ -58,7 +60,7 @@
Where to get source code:
=========================
-The U-Boot source code is maintained in the git repository at
+The U-Boot source code is maintained in the Git repository at
git://www.denx.de/git/u-boot.git ; you can browse it online at
http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
@@ -133,79 +135,24 @@
/arch Architecture specific files
/arc Files generic to ARC architecture
- /cpu CPU specific files
- /arc700 Files specific to ARC 700 CPUs
- /lib Architecture specific library files
/arm Files generic to ARM architecture
- /cpu CPU specific files
- /arm720t Files specific to ARM 720 CPUs
- /arm920t Files specific to ARM 920 CPUs
- /at91 Files specific to Atmel AT91RM9200 CPU
- /imx Files specific to Freescale MC9328 i.MX CPUs
- /s3c24x0 Files specific to Samsung S3C24X0 CPUs
- /arm926ejs Files specific to ARM 926 CPUs
- /arm1136 Files specific to ARM 1136 CPUs
- /pxa Files specific to Intel XScale PXA CPUs
- /sa1100 Files specific to Intel StrongARM SA1100 CPUs
- /lib Architecture specific library files
/avr32 Files generic to AVR32 architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/blackfin Files generic to Analog Devices Blackfin architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/m68k Files generic to m68k architecture
- /cpu CPU specific files
- /mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
- /mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs
- /mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
- /mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
- /mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs
- /lib Architecture specific library files
/microblaze Files generic to microblaze architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/mips Files generic to MIPS architecture
- /cpu CPU specific files
- /mips32 Files specific to MIPS32 CPUs
- /mips64 Files specific to MIPS64 CPUs
- /lib Architecture specific library files
/nds32 Files generic to NDS32 architecture
- /cpu CPU specific files
- /n1213 Files specific to Andes Technology N1213 CPUs
- /lib Architecture specific library files
/nios2 Files generic to Altera NIOS2 architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/openrisc Files generic to OpenRISC architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/powerpc Files generic to PowerPC architecture
- /cpu CPU specific files
- /mpc5xx Files specific to Freescale MPC5xx CPUs
- /mpc5xxx Files specific to Freescale MPC5xxx CPUs
- /mpc8xx Files specific to Freescale MPC8xx CPUs
- /mpc8260 Files specific to Freescale MPC8260 CPUs
- /mpc85xx Files specific to Freescale MPC85xx CPUs
- /ppc4xx Files specific to AMCC PowerPC 4xx CPUs
- /lib Architecture specific library files
+ /sandbox Files generic to HW-independent "sandbox"
/sh Files generic to SH architecture
- /cpu CPU specific files
- /sh2 Files specific to sh2 CPUs
- /sh3 Files specific to sh3 CPUs
- /sh4 Files specific to sh4 CPUs
- /lib Architecture specific library files
/sparc Files generic to SPARC architecture
- /cpu CPU specific files
- /leon2 Files specific to Gaisler LEON2 SPARC CPU
- /leon3 Files specific to Gaisler LEON3 SPARC CPU
- /lib Architecture specific library files
/x86 Files generic to x86 architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/api Machine/arch independent API for external apps
/board Board dependent files
/common Misc architecture independent functions
+/configs Board default configuration files
/disk Code for disk drive partition handling
/doc Documentation (don't expect too much)
/drivers Commonly used device drivers
@@ -213,13 +160,12 @@
/examples Example code for standalone applications, etc.
/fs Filesystem code (cramfs, ext2, jffs2, etc.)
/include Header Files
-/lib Files generic to all architectures
- /libfdt Library files to support flattened device trees
- /lzma Library files to support LZMA decompression
- /lzo Library files to support LZO decompression
+/lib Library routines generic to all architectures
+/Licenses Various license files
/net Networking code
/post Power On Self Test
-/spl Secondary Program Loader framework
+/scripts Various build scripts and Makefiles
+/test Various unit test files
/tools Tools to build S-Record or U-Boot images, etc.
Software Configuration:
@@ -239,11 +185,11 @@
you don't know what you're doing; they have names beginning with
"CONFIG_SYS_".
-Later we will add a configuration tool - probably similar to or even
-identical to what's used for the Linux kernel. Right now, we have to
-do the configuration by hand, which means creating some symbolic
-links and editing some configuration files. We use the TQM8xxL boards
-as an example here.
+Previously, all configuration was done by hand, which involved creating
+symbolic links and editing configuration files manually. More recently,
+U-Boot has added the Kbuild infrastructure used by the Linux kernel,
+allowing you to use the "make menuconfig" command to configure your
+build.
Selection of Processor Architecture and Board Type:
@@ -257,10 +203,9 @@
cd u-boot
make TQM823L_defconfig
-For the Cogent platform, you need to specify the CPU type as well;
-e.g. "make cogent_mpc8xx_defconfig". And also configure the cogent
-directory according to the instructions in cogent/README.
-
+Note: If you're looking for the default configuration file for a board
+you're sure used to be there but is now missing, check the file
+doc/README.scrapyard for a list of no longer supported boards.
Sandbox Environment:
--------------------
@@ -277,13 +222,25 @@
--------------------------
This is the intended start-up flow for boards. This should apply for both
-SPL and U-Boot proper (i.e. they both follow the same rules). At present SPL
-mostly uses a separate code path, but the funtion names and roles of each
-function are the same. Some boards or architectures may not conform to this.
-At least most ARM boards which use CONFIG_SPL_FRAMEWORK conform to this.
+SPL and U-Boot proper (i.e. they both follow the same rules).
+
+Note: "SPL" stands for "Secondary Program Loader," which is explained in
+more detail later in this file.
+
+At present, SPL mostly uses a separate code path, but the function names
+and roles of each function are the same. Some boards or architectures
+may not conform to this. At least most ARM boards which use
+CONFIG_SPL_FRAMEWORK conform to this.
-Execution starts with start.S with three functions called during init after
-that. The purpose and limitations of each is described below.
+Execution typically starts with an architecture-specific (and possibly
+CPU-specific) start.S file, such as:
+
+ - arch/arm/cpu/armv7/start.S
+ - arch/powerpc/cpu/mpc83xx/start.S
+ - arch/mips/cpu/start.S
+
+and so on. From there, three functions are called; the purpose and
+limitations of each of these functions are described below.
lowlevel_init():
- purpose: essential init to permit execution to reach board_init_f()
@@ -933,15 +890,6 @@
'Sane' compilers will generate smaller code if
CONFIG_PRE_CON_BUF_SZ is a power of 2
-- Safe printf() functions
- Define CONFIG_SYS_VSNPRINTF to compile in safe versions of
- the printf() functions. These are defined in
- include/vsprintf.h and include snprintf(), vsnprintf() and
- so on. Code size increase is approximately 300-500 bytes.
- If this option is not given then these functions will
- silently discard their buffer size argument - this means
- you are not getting any overflow checking in this case.
-
- Boot Delay: CONFIG_BOOTDELAY - in seconds
Delay before automatically booting the default image;
set to -1 to disable autoboot.
@@ -5161,14 +5109,11 @@
to port U-Boot to your hardware platform. To do this, follow these
steps:
-1. Add a new configuration option for your board to the toplevel
- "boards.cfg" file, using the existing entries as examples.
- Follow the instructions there to keep the boards in order.
-2. Create a new directory to hold your board specific code. Add any
+1. Create a new directory to hold your board specific code. Add any
files you need. In your board directory, you will need at least
- the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
-3. Create a new configuration file "include/configs/<board>.h" for
- your board
+ the "Makefile" and a "<board>.c".
+2. Create a new configuration file "include/configs/<board>.h" for
+ your board.
3. If you're porting U-Boot to a new CPU, then also create a new
directory to hold your CPU specific code. Add any files you need.
4. Run "make <board>_defconfig" with your new name.
@@ -6630,7 +6575,8 @@
* A CHANGELOG entry as plaintext (separate from the patch)
-* For major contributions, your entry to the CREDITS file
+* For major contributions, add a MAINTAINERS file with your
+ information and associated file and directory references.
* When you add support for a new board, don't forget to add a
maintainer e-mail address to the boards.cfg file, too.
diff --git a/api/api_storage.c b/api/api_storage.c
index ec92ae4..bc2b4d6 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -345,19 +345,6 @@
}
-static int dev_stor_index(block_dev_desc_t *dd)
-{
- int i, type;
-
- type = dev_stor_type(dd);
- for (i = 0; i < specs[type].max_dev; i++)
- if (dd == get_dev(specs[type].name, i))
- return i;
-
- return (specs[type].max_dev);
-}
-
-
lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
{
int type;
@@ -374,5 +361,5 @@
return 0;
}
- return (dd->block_read(dev_stor_index(dd), start, len, buf));
+ return dd->block_read(dd, start, len, buf);
}
diff --git a/arch/Kconfig b/arch/Kconfig
index 1709d40..ec12013 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -55,6 +55,7 @@
select HAVE_PRIVATE_LIBGCC
select HAVE_GENERIC_BOARD
select SYS_GENERIC_BOARD
+ select SUPPORT_OF_CONTROL
config NDS32
bool "NDS32 architecture"
diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts
index 80e6d6b..391d067 100644
--- a/arch/arc/dts/axs10x.dts
+++ b/arch/arc/dts/axs10x.dts
@@ -48,4 +48,10 @@
reg = < 0xe0040000 0x100 >;
interrupts = < 8 >;
};
+
+ ohci@0xe0060000 {
+ compatible = "generic-ohci";
+ reg = < 0xe0060000 0x100 >;
+ interrupts = < 8 >;
+ };
};
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 26a5934..90ee7e0 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -50,18 +50,20 @@
1:
#endif
- /* Setup stack- and frame-pointers */
+ /* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
- /* Allocate and zero GD, update SP */
+ /* Allocate reserved area from current top of stack */
mov %r0, %sp
- bl board_init_f_mem
-
- /* Update stack- and frame-pointers */
+ bl board_init_f_alloc_reserve
+ /* Set stack below reserved area, adjust frame pointer accordingly */
mov %sp, %r0
mov %fp, %sp
+ /* Initialize reserved area - note: r0 already contains address */
+ bl board_init_f_init_reserve
+
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
j board_init_f
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 75d6bbc..dd9cac9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -117,7 +117,14 @@
select OF_CONTROL
select OF_SEPARATE
select DM
+ select DM_ETH
select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select SPL_DM
+ select SPL_DM_SEQ_ALIAS
+ select SPL_OF_CONTROL
+ select SPL_SIMPLE_BUS
config TARGET_DEVKIT3250
bool "Support devkit3250"
@@ -516,8 +523,9 @@
bool "Support sunxi (Allwinner) SoCs"
select CMD_USB
select DM
- select DM_GPIO
select DM_ETH
+ select DM_GPIO
+ select DM_KEYBOARD
select DM_SERIAL
select DM_USB
select OF_CONTROL
@@ -768,8 +776,6 @@
source "board/BuR/tseries/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
-source "board/Marvell/db-88f6820-gp/Kconfig"
-source "board/Marvell/db-mv784mp-gp/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
@@ -808,7 +814,6 @@
source "board/hisilicon/hikey/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/phytec/pcm051/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 18283d1..3d15673 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -49,7 +49,7 @@
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
-machine-$(CONFIG_ARMADA_XP) += mvebu
+machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b1c3f8f..b6db23e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -5,12 +5,14 @@
*/
#include <common.h>
-#include <asm/arch/cpu.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <dm/platform_data/lpc32xx_hsuart.h>
+
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
-#include <dm.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -41,6 +43,37 @@
&clk->u3clk + (uart_id - 3));
}
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct ns16550_platdata lpc32xx_uart[] = {
+ { UART3_BASE, 2, CONFIG_SYS_NS16550_CLK },
+ { UART4_BASE, 2, CONFIG_SYS_NS16550_CLK },
+ { UART5_BASE, 2, CONFIG_SYS_NS16550_CLK },
+ { UART6_BASE, 2, CONFIG_SYS_NS16550_CLK },
+};
+
+#if defined(CONFIG_LPC32XX_HSUART)
+static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
+ { HS_UART1_BASE, },
+ { HS_UART2_BASE, },
+ { HS_UART7_BASE, },
+};
+#endif
+
+U_BOOT_DEVICES(lpc32xx_uarts) = {
+#if defined(CONFIG_LPC32XX_HSUART)
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
+#endif
+ { "ns16550_serial", &lpc32xx_uart[0], },
+ { "ns16550_serial", &lpc32xx_uart[1], },
+ { "ns16550_serial", &lpc32xx_uart[2], },
+ { "ns16550_serial", &lpc32xx_uart[3], },
+#if defined(CONFIG_LPC32XX_HSUART)
+ { "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
+#endif
+};
+#endif
+
void lpc32xx_dma_init(void)
{
/* Enable DMA interface */
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 1972de8..1ec8e2b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -248,6 +248,39 @@
}
/**
+ * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters
+ * @freqsel: One of the POWER_MISC_FREQSEL_xxx defines to select the clock
+ *
+ * This function configures and then enables an alternative PLL clock source
+ * for the DC-DC converters.
+ */
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel)
+{
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
+
+ /* Select clocksource for DC-DC converters */
+ clrsetbits_le32(&power_regs->hw_power_misc,
+ POWER_MISC_FREQSEL_MASK,
+ freqsel);
+ setbits_le32(&power_regs->hw_power_misc,
+ POWER_MISC_SEL_PLLCLK);
+}
+
+/**
+ * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters
+ *
+ * Normally, there is no need to switch DC-DC clocksource. This is the reason,
+ * why this function is a stub and does nothing. However, boards can implement
+ * this function when required and call mxs_power_switch_dcdc_clocksource() to
+ * switch to an alternative clock source.
+ */
+__weak void mxs_power_setup_dcdc_clocksource(void)
+{
+ debug("SPL: Using default DC-DC clocksource\n");
+}
+
+/**
* mxs_src_power_init() - Preconfigure the power block
*
* This function configures reasonable values for the DC-DC control loop
@@ -872,6 +905,7 @@
debug("SPL: Configuring power source\n");
+ mxs_power_setup_dcdc_clocksource();
mxs_src_power_init();
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 466348f..e8d5be3 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -64,8 +64,31 @@
# endif
# endif
};
+
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+ { 0, AM33XX_GPIO0_BASE },
+ { 1, AM33XX_GPIO1_BASE },
+ { 2, AM33XX_GPIO2_BASE },
+ { 3, AM33XX_GPIO3_BASE },
+#ifdef CONFIG_AM43XX
+ { 4, AM33XX_GPIO4_BASE },
+ { 5, AM33XX_GPIO5_BASE },
#endif
+};
+U_BOOT_DEVICES(am33xx_gpios) = {
+ { "gpio_omap", &am33xx_gpio[0] },
+ { "gpio_omap", &am33xx_gpio[1] },
+ { "gpio_omap", &am33xx_gpio[2] },
+ { "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+ { "gpio_omap", &am33xx_gpio[4] },
+ { "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+#endif
+#endif
#ifndef CONFIG_DM_GPIO
static const struct gpio_bank gpio_bank_am33xx[] = {
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index d325191..64514b1 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -727,6 +727,8 @@
reg = readl(&imx_ccm->CCGR2);
reg |= MXC_CCM_CCGR2_LCD_MASK;
writel(reg, &imx_ccm->CCGR2);
+
+ return 0;
}
#endif
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 6b039e4..567ddc4 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -796,7 +796,6 @@
debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
debug("SRT=%d\n", ddr3_cfg->SRT);
- debug("tcl=%d\n", tcl);
debug("twr=%d\n", twr);
/*
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 984eaf9..23d6b73 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -197,6 +197,19 @@
}
#endif
+static void erratum_a009929(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
+ struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
+ u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
+
+ rstrqmr1 |= 0x00000400;
+ gur_out32(&gur->rstrqmr1, rstrqmr1);
+ writel(0x01000000, dcsr_cop_ccp);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -216,6 +229,9 @@
*/
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /* Erratum */
+ erratum_a009929();
}
#endif
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 03f984a..64b8371 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -48,8 +48,11 @@
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_MVEBU) += \
+ armada-388-clearfog.dtb \
armada-388-gp.dtb \
- armada-xp-gp.dtb
+ armada-xp-gp.dtb \
+ armada-xp-maxbcm.dtb \
+ armada-xp-synology-ds414.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld4-ref.dtb \
@@ -125,6 +128,7 @@
sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a10s-wobo-i5.dtb \
sun5i-a13-ampe-a76.dtb \
+ sun5i-a13-empire-electronix-d709.dtb \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-inet-86vs.dtb \
sun5i-a13-inet-98v-rev2.dtb \
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index 3fffe1e..c95d1d3 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -25,6 +25,7 @@
serial0 = &uart0;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
+ spi0 = &qspi;
};
cpus {
@@ -908,7 +909,9 @@
qspi: qspi@47900000 {
compatible = "ti,am4372-qspi";
- reg = <0x47900000 0x100>;
+ reg = <0x47900000 0x100>,
+ <0x30000000 0x4000000>;
+ reg-names = "qspi_base", "qspi_mmap";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts
index 3f9d808..89feaf3 100644
--- a/arch/arm/dts/am437x-sk-evm.dts
+++ b/arch/arm/dts/am437x-sk-evm.dts
@@ -567,7 +567,7 @@
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "mx66l51235l";
+ compatible = "mx66l51235l","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-cpol;
diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi
index a718866..0b2a78d 100644
--- a/arch/arm/dts/armada-370-xp.dtsi
+++ b/arch/arm/dts/armada-370-xp.dtsi
@@ -141,6 +141,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+ u-boot,dm-pre-reloc;
rtc@10300 {
compatible = "marvell,orion-rtc";
diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts
new file mode 100644
index 0000000..b2dfd56
--- /dev/null
+++ b/arch/arm/dts/armada-388-clearfog.dts
@@ -0,0 +1,509 @@
+/*
+ * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-388.dtsi"
+
+/ {
+ model = "SolidRun Clearfog A1";
+ compatible = "solidrun,clearfog-a1", "marvell,armada388",
+ "marvell,armada385", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = ð0;
+ ethernet2 = ð1;
+ ethernet3 = ð2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; /* 256 MB */
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+
+ internal-regs {
+ ethernet@30000 {
+ mac-address = [00 50 43 02 02 02];
+ phy-mode = "sgmii";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ ethernet@34000 {
+ mac-address = [00 50 43 02 02 03];
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ status = "okay";
+ };
+
+ ethernet@70000 {
+ mac-address = [00 50 43 02 02 01];
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy_dedicated>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+ };
+
+ i2c@11000 {
+ /* Is there anything on this? */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * PCA9655 GPIO expander, up to 1MHz clock.
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ expander0: gpio-expander@20 {
+ /*
+ * This is how it should be:
+ * compatible = "onnn,pca9655",
+ * "nxp,pca9555";
+ * but you can't do this because of
+ * the way I2C works.
+ */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+
+ pcie1_0_clkreq {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+ pcie1_0_w_disable {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+ usb3_ilimit {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+ usb3_power {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb3-power";
+ };
+ m2_devslp {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ };
+
+ /* The MCP3021 is 100kHz clock only */
+ mikrobus_adc: mcp3021@4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+
+ /* Also something at 0x64 */
+ };
+
+ i2c@11100 {
+ /*
+ * Routed to SFP, mikrobus, and PCIe.
+ * SFP limits this to 100kHz, and requires
+ * an AT24C01A/02/04 with address pins tied
+ * low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C
+ * bus being present.
+ * PCIe uses ARP to assign addresses, or
+ * 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&clearfog_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ mdio@72004 {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ phy_dedicated: ethernet-phy@0 {
+ /*
+ * Annoyingly, the marvell phy driver
+ * configures the LED register, rather
+ * than preserving reset-loaded setting.
+ * We undo that rubbish here.
+ */
+ marvell,reg-init = <3 16 0 0x101e>;
+ reg = <0>;
+ };
+ };
+
+ pinctrl@18000 {
+ clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
+ marvell,pins = "mpp46";
+ marvell,function = "ref";
+ };
+ clearfog_dsa0_pins: clearfog-dsa0-pins {
+ marvell,pins = "mpp23", "mpp41";
+ marvell,function = "gpio";
+ };
+ clearfog_i2c1_pins: i2c1-pins {
+ /* SFP, PCIe, mSATA, mikrobus */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+ clearfog_sdhci_pins: clearfog-sdhci-pins {
+ marvell,pins = "mpp21", "mpp28",
+ "mpp37", "mpp38",
+ "mpp39", "mpp40";
+ marvell,function = "sd0";
+ };
+ clearfog_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "spi1";
+ };
+ mikro_pins: mikro-pins {
+ /* int: mpp22 rst: mpp29 */
+ marvell,pins = "mpp22", "mpp29";
+ marvell,function = "gpio";
+ };
+ mikro_spi_pins: mikro-spi-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "spi1";
+ };
+ mikro_uart_pins: mikro-uart-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "ua1";
+ };
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+ };
+
+ rtc@a3800 {
+ /*
+ * If the rtc doesn't work, run "date reset"
+ * twice in u-boot.
+ */
+ status = "okay";
+ };
+
+ sata@a8000 {
+ /* pinctrl? */
+ status = "okay";
+ };
+
+ sata@e0000 {
+ /* pinctrl? */
+ status = "okay";
+ };
+
+ sdhci@d8000 {
+ bus-width = <4>;
+ cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ pinctrl-0 = <&clearfog_sdhci_pins
+ &clearfog_sdhci_cd_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc = <®_3p3v>;
+ wp-inverted;
+ };
+
+ serial@12000 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ serial@12100 {
+ /* mikrobus uart */
+ pinctrl-0 = <&mikro_uart_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ spi@10680 {
+ /*
+ * We don't seem to have the W25Q32 on the
+ * A1 Rev 2.0 boards, so disable SPI.
+ * CS0: W25Q32 (doesn't appear to be present)
+ * CS1:
+ * CS2: mikrobus
+ */
+ pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "w25q32", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <3000000>;
+ status = "disabled";
+ };
+ };
+
+ usb3@f8000 {
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+ /*
+ * The two PCIe units are accessible through
+ * the mini-PCIe connectors on the board.
+ */
+ pcie@2,0 {
+ /* Port 1, Lane 0. CONN3, nearest power. */
+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ pcie@3,0 {
+ /* Port 2, Lane 0. CONN2, nearest CPU. */
+ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ };
+ };
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
+ moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
+ sfp,ethernet = <ð2>;
+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ dsa@0 {
+ compatible = "marvell,dsa";
+ dsa,ethernet = <ð1>;
+ dsa,mii-bus = <&mdio>;
+ pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
+ pinctrl-names = "default";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ switch@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4 0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ };
+
+ port@6 {
+ /* 88E1512 external phy */
+ reg = <6>;
+ label = "lan6";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&rear_button_pins>;
+ pinctrl-names = "default";
+
+ button_0 {
+ /* The rear SW3 button */
+ label = "Rear Button";
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+ };
+};
+
+/*
++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
+MPP18: gpio ? (pca9655 int?)
+MPP19: gpio ? (clkreq?)
+MPP20: gpio ? (sd0 detect)
+MPP21: sd0:cmd x sd0
+MPP22: gpio x mikro int
+MPP23: gpio x switch irq
++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
+MPP24: ua1:rxd x mikro rx
+MPP25: ua1:txd x mikro tx
+MPP26: i2c1:sck x mikro sck
+MPP27: i2c1:sda x mikro sda
+MPP28: sd0:clk x sd0
+MPP29: gpio x mikro rst
+MPP30: ge1:txd2 ? (config)
+MPP31: ge1:txd3 ? (config)
++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
+MPP32: ge1:txctl ? (unused)
+MPP33: gpio ? (pic_com0)
+MPP34: gpio x rear button (pic_com1)
+MPP35: gpio ? (pic_com2)
+MPP36: gpio ? (unused)
+MPP37: sd0:d3 x sd0
+MPP38: sd0:d0 x sd0
+MPP39: sd0:d1 x sd0
++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
+MPP40: sd0:d2 x sd0
+MPP41: gpio x switch reset
+MPP42: gpio ? sw1-1
+MPP43: spi1:cs2 x mikro cs
+MPP44: sata3:prsnt ? (unused)
+MPP45: ref:clk_out0 ?
+MPP46: ref:clk_out1 x switch clk
+MPP47: 4 ? (unused)
++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
+MPP48: tdm:pclk
+MPP49: tdm:fsync
+MPP50: tdm:drx
+MPP51: tdm:dtx
+MPP52: tdm:int
+MPP53: tdm:rst
+MPP54: gpio ? (pwm)
+MPP55: spi1:cs1 x slic
++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
+MPP56: spi1:mosi x mikro mosi
+MPP57: spi1:sck x mikro sck
+MPP58: spi1:miso x mikro miso
+MPP59: spi1:cs0 x w25q32
+*/
diff --git a/arch/arm/dts/armada-388-gp.dts b/arch/arm/dts/armada-388-gp.dts
index fd4f6fd..7bc878f 100644
--- a/arch/arm/dts/armada-388-gp.dts
+++ b/arch/arm/dts/armada-388-gp.dts
@@ -51,6 +51,12 @@
stdout-path = "serial0:115200n8";
};
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ spi0 = &spi0;
+ };
+
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
@@ -65,8 +71,10 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
+ u-boot,dm-pre-reloc;
spi-flash@0 {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
@@ -122,6 +130,7 @@
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
+ u-boot,dm-pre-reloc;
};
/* GE1 CON15 */
diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi
index 04ecfe6..dc8a1a6 100644
--- a/arch/arm/dts/armada-38x.dtsi
+++ b/arch/arm/dts/armada-38x.dtsi
@@ -70,6 +70,7 @@
soc {
compatible = "marvell,armada380-mbus", "simple-bus";
+ u-boot,dm-pre-reloc;
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
@@ -134,6 +135,7 @@
internal-regs {
compatible = "simple-bus";
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-gp.dts
index bf724ca..27799d1 100644
--- a/arch/arm/dts/armada-xp-gp.dts
+++ b/arch/arm/dts/armada-xp-gp.dts
@@ -68,6 +68,10 @@
stdout-path = "serial0:115200n8";
};
+ aliases {
+ spi0 = &spi0;
+ };
+
memory {
device_type = "memory";
/*
@@ -148,6 +152,7 @@
internal-regs {
serial@12000 {
status = "okay";
+ u-boot,dm-pre-reloc;
};
serial@12100 {
status = "okay";
@@ -223,8 +228,10 @@
spi0: spi@10600 {
status = "okay";
+ u-boot,dm-pre-reloc;
spi-flash@0 {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
diff --git a/arch/arm/dts/armada-xp-maxbcm.dts b/arch/arm/dts/armada-xp-maxbcm.dts
new file mode 100644
index 0000000..d7d7f65
--- /dev/null
+++ b/arch/arm/dts/armada-xp-maxbcm.dts
@@ -0,0 +1,249 @@
+/*
+ * Device Tree file for Marvell Armada XP maxbcm board
+ *
+ * Copyright (C) 2013-2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78460.dtsi"
+
+/ {
+ model = "Marvell Armada XP MAXBCM";
+ compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ /*
+ * 8 GB of plug-in RAM modules by default.The amount
+ * of memory available can be changed by the
+ * bootloader according the size of the module
+ * actually plugged. However, memory between
+ * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
+ * the address range used for I/O (internal registers,
+ * MBus windows).
+ */
+ reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
+ <0x00000001 0x00000000 0x00000001 0x00000000>;
+ };
+
+ cpus {
+ pm_pic {
+ ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
+ <&gpio0 17 GPIO_ACTIVE_LOW>,
+ <&gpio0 18 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+ devbus-bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+
+ /* NOR 16 MiB */
+ nor@0 {
+ compatible = "cfi-flash";
+ reg = <0 0x1000000>;
+ bank-width = <2>;
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * The 3 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ internal-regs {
+ serial@12000 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+ serial@12100 {
+ status = "okay";
+ };
+ serial@12200 {
+ status = "okay";
+ };
+ serial@12300 {
+ status = "okay";
+ };
+ pinctrl {
+ pinctrl-0 = <&pic_pins>;
+ pinctrl-names = "default";
+ pic_pins: pic-pins-0 {
+ marvell,pins = "mpp16", "mpp17",
+ "mpp18";
+ marvell,function = "gpio";
+ };
+ };
+ sata@a0000 {
+ nr-ports = <2>;
+ status = "okay";
+ };
+
+ mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+
+ ethernet@70000 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ };
+ ethernet@74000 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "sgmii";
+ };
+ ethernet@30000 {
+ status = "okay";
+ phy = <&phy2>;
+ phy-mode = "sgmii";
+ };
+ ethernet@34000 {
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "sgmii";
+ };
+
+ /* Front-side USB slot */
+ usb@50000 {
+ status = "okay";
+ };
+
+ /* Back-side USB slot */
+ usb@51000 {
+ status = "okay";
+ };
+
+ spi0: spi@10600 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
+ };
+
+ nand@d0000 {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-xp-synology-ds414.dts b/arch/arm/dts/armada-xp-synology-ds414.dts
new file mode 100644
index 0000000..0a60ddf
--- /dev/null
+++ b/arch/arm/dts/armada-xp-synology-ds414.dts
@@ -0,0 +1,337 @@
+/*
+ * Device Tree file for Synology DS414
+ *
+ * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the old 0xd0000000).
+ * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
+ * bootloaders provided by Marvell. It is used in recent versions of
+ * DSM software provided by Synology. Nonetheless, some earlier boards
+ * were delivered with an older version of u-boot that left internal
+ * registers mapped at 0xd0000000. If you have such a device you will
+ * not be able to directly boot a kernel based on this Device Tree. In
+ * that case, the preferred solution is to update your bootloader (e.g.
+ * by upgrading to latest version of DSM, or building a new one and
+ * installing it from u-boot prompt) or adjust the Devive Tree
+ * (s/0xf1000000/0xd0000000/ in 'ranges' below).
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+ model = "Synology DS414";
+ compatible = "synology,ds414", "marvell,armadaxp-mv78230",
+ "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1GB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+ pcie-controller {
+ status = "okay";
+
+ /*
+ * Connected to Marvell 88SX7042 SATA-II controller
+ * handling the four disks.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /*
+ * Connected to EtronTech EJ168A XHCI controller
+ * providing the two rear USB 3.0 ports.
+ */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ internal-regs {
+
+ /* RTC is provided by Seiko S-35390A below */
+ rtc@10300 {
+ status = "disabled";
+ };
+
+ spi0: spi@10600 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q064";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+
+ /*
+ * Warning!
+ *
+ * Synology u-boot uses its compiled-in environment
+ * and it seems Synology did not care to change u-boot
+ * default configuration in order to allow saving a
+ * modified environment at a sensible location. So,
+ * if you do a 'saveenv' under u-boot, your modified
+ * environment will be saved at 1MB after the start
+ * of the flash, i.e. in the middle of the uImage.
+ * For that reason, it is strongly advised not to
+ * change the default environment, unless you know
+ * what you are doing.
+ */
+ partition@00000000 { /* u-boot */
+ label = "RedBoot";
+ reg = <0x00000000 0x000d0000>; /* 832KB */
+ };
+
+ partition@000c0000 { /* uImage */
+ label = "zImage";
+ reg = <0x000d0000 0x002d0000>; /* 2880KB */
+ };
+
+ partition@003a0000 { /* uInitramfs */
+ label = "rd.gz";
+ reg = <0x003a0000 0x00430000>; /* 4250KB */
+ };
+
+ partition@007d0000 { /* MAC address and serial number */
+ label = "vendor";
+ reg = <0x007d0000 0x00010000>; /* 64KB */
+ };
+
+ partition@007e0000 {
+ label = "RedBoot config";
+ reg = <0x007e0000 0x00010000>; /* 64KB */
+ };
+
+ partition@007f0000 {
+ label = "FIS directory";
+ reg = <0x007f0000 0x00010000>; /* 64KB */
+ };
+ };
+ };
+
+ i2c@11000 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ s35390a: s35390a@30 {
+ compatible = "sii,s35390a";
+ reg = <0x30>;
+ };
+ };
+
+ /* Connected to a header on device's PCB. This
+ * provides the main console for the device.
+ *
+ * Warning: the device may not boot with a 3.3V
+ * USB-serial converter connected when the power
+ * button is pressed. The converter needs to be
+ * connected a few seconds after pressing the
+ * power button. This is possibly due to UART0_TXD
+ * pin being sampled at reset (bit 0 of SAR).
+ */
+ serial@12000 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ /* Connected to a Microchip PIC16F883 for power control */
+ serial@12100 {
+ status = "okay";
+ };
+
+ poweroff@12100 {
+ compatible = "synology,power-off";
+ reg = <0x12100 0x100>;
+ clocks = <&coreclk 0>;
+ };
+
+ /* Front USB 2.0 port */
+ usb@50000 {
+ status = "okay";
+ };
+
+ mdio {
+ phy0: ethernet-phy@0 { /* Marvell 88E1512 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+ reg = <1>;
+ };
+ };
+
+ ethernet@70000 {
+ status = "okay";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
+
+ ethernet@74000 {
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
+ &sata3_pwr_pin &sata4_pwr_pin>;
+ pinctrl-names = "default";
+
+ sata1_regulator: sata1-regulator {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "SATA1 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <2000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata2_regulator: sata2-regulator {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "SATA2 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <4000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata3_regulator: sata3-regulator {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "SATA3 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <6000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ sata4_regulator: sata4-regulator {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "SATA4 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <8000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pinctrl {
+ sata1_pwr_pin: sata1-pwr-pin {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+
+ sata2_pwr_pin: sata2-pwr-pin {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+
+ sata3_pwr_pin: sata3-pwr-pin {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+
+ sata4_pwr_pin: sata4-pwr-pin {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+
+ sata1_pres_pin: sata1-pres-pin {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+
+ sata2_pres_pin: sata2-pres-pin {
+ marvell,pins = "mpp35";
+ marvell,function = "gpio";
+ };
+
+ sata3_pres_pin: sata3-pres-pin {
+ marvell,pins = "mpp40";
+ marvell,function = "gpio";
+ };
+
+ sata4_pres_pin: sata4-pres-pin {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+
+ syno_id_bit0_pin: syno-id-bit0-pin {
+ marvell,pins = "mpp26";
+ marvell,function = "gpio";
+ };
+
+ syno_id_bit1_pin: syno-id-bit1-pin {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+
+ syno_id_bit2_pin: syno-id-bit2-pin {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ fan1_alarm_pin: fan1-alarm-pin {
+ marvell,pins = "mpp33";
+ marvell,function = "gpio";
+ };
+
+ fan2_alarm_pin: fan2-alarm-pin {
+ marvell,pins = "mpp32";
+ marvell,function = "gpio";
+ };
+};
diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi
index 3de9b76..3fac39e 100644
--- a/arch/arm/dts/armada-xp.dtsi
+++ b/arch/arm/dts/armada-xp.dtsi
@@ -63,6 +63,7 @@
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
+ u-boot,dm-pre-reloc;
bootrom {
compatible = "marvell,bootrom";
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index e4daa99..797d411 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -487,7 +487,7 @@
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "s25fl256s1";
+ compatible = "s25fl256s1","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index feb3708..e7fecf7 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -41,6 +41,7 @@
ethernet1 = &cpsw_emac1;
d_can0 = &dcan1;
d_can1 = &dcan2;
+ spi0 = &qspi;
};
timer {
@@ -1113,8 +1114,11 @@
qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi";
- reg = <0x4b300000 0x100>;
- reg-names = "qspi_base";
+ reg = <0x4b300000 0x100>,
+ <0x5c000000 0x4000000>,
+ <0x4a002558 0x4>;
+ reg-names = "qspi_base", "qspi_mmap",
+ "qspi_ctrlmod";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index efb544c..a62550f 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -604,7 +604,7 @@
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "s25fl256s1";
+ compatible = "s25fl256s1","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 7d1836e..5933a40 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -25,6 +25,7 @@
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
+ udc0 = &usb1;
};
regulator_3_3v: 3-3-v-regulator {
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
index b649c9a..dc09bed 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -16,6 +16,7 @@
aliases {
ethernet0 = &gmac1;
+ udc0 = &usb1;
};
memory {
@@ -59,3 +60,7 @@
status = "okay";
u-boot,dm-pre-reloc;
};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
index e1e3d73..7d3f989 100644
--- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
@@ -16,6 +16,7 @@
aliases {
ethernet0 = &gmac0;
+ udc0 = &usb1;
};
memory {
@@ -51,3 +52,7 @@
bus-width = <8>;
u-boot,dm-pre-reloc;
};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 9eb5a22..a202709 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -25,6 +25,7 @@
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
+ udc0 = &usb1;
};
regulator_3_3v: 3-3-v-regulator {
@@ -33,6 +34,10 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
};
&gmac1 {
@@ -77,10 +82,6 @@
vqmmc-supply = <®ulator_3_3v>;
};
-&usb1 {
- status = "okay";
-};
-
&qspi {
status = "okay";
@@ -100,3 +101,7 @@
tslch-ns = <4>;
};
};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts
index d7c41c8..e45c2ab 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -14,9 +14,10 @@
bootargs = "console=ttyS0,115200";
};
- aliases {
+ aliases {
ethernet0 = &gmac1;
- };
+ udc0 = &usb1;
+ };
memory {
name = "memory";
@@ -90,3 +91,7 @@
tslch-ns = <4>;
};
};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 05b935d..591d96c 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -14,6 +14,10 @@
bootargs = "console=ttyS0,115200";
};
+ aliases {
+ udc0 = &usb1;
+ };
+
memory {
name = "memory";
device_type = "memory";
@@ -28,6 +32,15 @@
&gmac1 {
status = "okay";
phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
};
&i2c0 {
@@ -63,3 +76,7 @@
tslch-ns = <4>;
};
};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts
new file mode 100644
index 0000000..7fbb0b0
--- /dev/null
+++ b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts
@@ -0,0 +1,241 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Empire Electronix D709 tablet";
+ compatible = "empire-electronix,d709", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ /* TODO: backlight uses axp gpio1 as enable pin */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+
+ mmccard: mmccard@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PG2";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_usb0_vbus {
+ gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb0_vbus_pin_a {
+ allwinner,pins = "PG12";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_ldo3>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
new file mode 100644
index 0000000..5d4b2cf
--- /dev/null
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -0,0 +1,105 @@
+/*
+ * Device Tree Source commonly used by UniPhier ARM SoCs
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+
+ extbus: extbus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&uart_clk>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&uart_clk>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&uart_clk>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&uart_clk>;
+ };
+
+ system-bus-controller@58c00000 {
+ compatible = "socionext,uniphier-system-bus-controller";
+ reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ pinctrl: pinctrl@5f801000 {
+ /* specify compatible in each SoC DTSI */
+ reg = <0x5f801000 0xe00>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
index 9d697c1..469bd05 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -20,8 +20,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 5f12e10..856c207 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -6,7 +6,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-ld4";
@@ -19,6 +19,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
};
@@ -41,183 +42,117 @@
clock-frequency = <100000000>;
};
};
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 29 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+};
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(512 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <400000>;
+ };
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- interrupts = <0 80 4>;
- };
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- interrupts = <0 81 4>;
- };
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- interrupts = <0 82 4>;
- };
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,ph1-ld4-pinctrl",
- "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ };
+};
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <36864000>;
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
- clocks = <&arm_timer_clk>;
- };
+&serial1 {
+ clock-frequency = <36864000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial2 {
+ clock-frequency = <36864000>;
+};
- nand: nand@68000000 {
- compatible = "denali,denali-nand-dt";
- reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- };
- };
+&serial3 {
+ interrupts = <0 29 4>;
+ clock-frequency = <36864000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,ph1-ld4-pinctrl", "syscon";
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
index ccadd81..e0a972f 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
@@ -20,8 +20,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index a825069..02e74a7 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -20,8 +20,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index a11b628..244ccf6 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -6,7 +6,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-pro4";
@@ -20,12 +20,14 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ next-level-cache = <&l2>;
};
};
@@ -48,216 +50,149 @@
clock-frequency = <50000000>;
};
};
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- clock-frequency = <73728000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- clock-frequency = <73728000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- clock-frequency = <73728000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 29 4>;
- clocks = <&uart_clk>;
- clock-frequency = <73728000>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+};
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(768 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* i2c4 does not exist */
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* i2c4 does not exist */
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- usb2: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- interrupts = <0 80 4>;
- };
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- usb3: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- interrupts = <0 81 4>;
- };
+ usb2: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ };
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- interrupts = <0 134 4>;
- };
+ usb3: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ };
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- interrupts = <0 137 4>;
- };
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,ph1-pro4-pinctrl",
- "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ };
+};
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <73728000>;
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
- clocks = <&arm_timer_clk>;
- };
+&serial1 {
+ clock-frequency = <73728000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial2 {
+ clock-frequency = <73728000>;
+};
- nand: nand@68000000 {
- compatible = "denali,denali-nand-dt";
- reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- };
- };
+&serial3 {
+ clock-frequency = <73728000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,ph1-pro4-pinctrl", "syscon";
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
index 52dd1f9..d46e827 100644
--- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
+++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
@@ -19,8 +19,7 @@
};
chosen {
- bootargs = "console=ttyS1,115200";
- stdout-path = &serial1;
+ stdout-path = "serial1:115200n8";
};
aliases {
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 6f19bf8..0049106 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -6,7 +6,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-pro5";
@@ -20,12 +20,14 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ next-level-cache = <&l2>;
};
};
@@ -48,187 +50,143 @@
clock-frequency = <50000000>;
};
};
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- };
+};
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 177 4>;
- clocks = <&uart_clk>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
+ interrupts = <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ next-level-cache = <&l3>;
+ };
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ l3: l3-cache@500c8000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <256>;
+ cache-level = <3>;
+ };
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* i2c4 does not exist */
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* i2c4 does not exist */
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,ph1-pro5-pinctrl", "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
- clocks = <&arm_timer_clk>;
- };
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
+ };
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <73728000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial1 {
+ clock-frequency = <73728000>;
+};
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- interrupts = <0 134 4>;
- };
+&serial2 {
+ clock-frequency = <73728000>;
+};
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
- interrupts = <0 137 4>;
- };
- };
+&serial3 {
+ clock-frequency = <73728000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,ph1-pro5-pinctrl", "syscon";
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index c760b6d..1f3aee9 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -21,8 +21,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
index 2cfcaff..b58bf07 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -20,8 +20,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index 7d06f7e..cb28bc4 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -6,7 +6,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-sld8";
@@ -19,6 +19,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
};
@@ -41,183 +42,117 @@
clock-frequency = <100000000>;
};
};
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- clock-frequency = <80000000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- clock-frequency = <80000000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- clock-frequency = <80000000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 29 4>;
- clocks = <&uart_clk>;
- clock-frequency = <80000000>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+};
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(256 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <400000>;
+ };
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- interrupts = <0 80 4>;
- };
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- interrupts = <0 81 4>;
- };
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- interrupts = <0 82 4>;
- };
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,ph1-sld8-pinctrl",
- "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ };
+};
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <80000000>;
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
- clocks = <&arm_timer_clk>;
- };
+&serial1 {
+ clock-frequency = <80000000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial2 {
+ clock-frequency = <80000000>;
+};
- nand: nand@68000000 {
- compatible = "denali,denali-nand-dt";
- reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- };
- };
+&serial3 {
+ interrupts = <0 29 4>;
+ clock-frequency = <80000000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,ph1-sld8-pinctrl", "syscon";
+};
diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi
index b584213..b1691d0 100644
--- a/arch/arm/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/dts/uniphier-pinctrl.dtsi
@@ -7,6 +7,11 @@
*/
&pinctrl {
+ pinctrl_emmc: emmc_grp {
+ groups = "emmc", "emmc_dat8";
+ function = "emmc";
+ };
+
pinctrl_i2c0: i2c0_grp {
groups = "i2c0";
function = "i2c0";
@@ -27,6 +32,16 @@
function = "i2c3";
};
+ pinctrl_sd: sd_grp {
+ groups = "sd";
+ function = "sd";
+ };
+
+ pinctrl_sd1: sd1_grp {
+ groups = "sd1";
+ function = "sd1";
+ };
+
pinctrl_uart0: uart0_grp {
groups = "uart0";
function = "uart0";
diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
index d0af8ac..a49215e 100644
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -19,8 +19,7 @@
};
chosen {
- bootargs = "console=ttyS2,115200";
- stdout-path = &serial2;
+ stdout-path = "serial2:115200n8";
};
aliases {
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts
index 92d7404..63bd363 100644
--- a/arch/arm/dts/uniphier-proxstream2-vodka.dts
+++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts
@@ -19,8 +19,7 @@
};
chosen {
- bootargs = "console=ttyS2,115200";
- stdout-path = &serial2;
+ stdout-path = "serial2:115200n8";
};
aliases {
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index cd0cf4e..3ba6a4a 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -6,7 +6,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,proxstream2";
@@ -20,24 +20,28 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ next-level-cache = <&l2>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
+ next-level-cache = <&l2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
+ next-level-cache = <&l2>;
};
};
@@ -60,200 +64,140 @@
clock-frequency = <50000000>;
};
};
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- clock-frequency = <88900000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- clock-frequency = <88900000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- clock-frequency = <88900000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 177 4>;
- clocks = <&uart_clk>;
- clock-frequency = <88900000>;
- };
+};
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(1280 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ interrupts = <0 43 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for DMD */
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for STM */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* chip-internal connection for DMD */
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* chip-internal connection for STM */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,proxstream2-pinctrl", "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+ };
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0xf04>;
- clocks = <&arm_timer_clk>;
- };
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+ };
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0xf04>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <88900000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial1 {
+ clock-frequency = <88900000>;
+};
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
- interrupts = <0 134 4>;
- };
+&serial2 {
+ clock-frequency = <88900000>;
+};
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
- interrupts = <0 137 4>;
- };
- };
+&serial3 {
+ clock-frequency = <88900000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,proxstream2-pinctrl", "syscon";
+};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index 5088cfe..1ba3a1c 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -18,6 +18,7 @@
i2c0 = &i2c0;
serial0 = &uart1;
spi0 = &qspi;
+ mmc0 = &sdhci0;
};
memory {
@@ -291,6 +292,7 @@
};
&sdhci0 {
+ u-boot,dm-pre-reloc;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 51d67d9..5ec59e2 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -17,6 +17,7 @@
ethernet0 = &gem0;
serial0 = &uart1;
spi0 = &qspi;
+ mmc0 = &sdhci0;
};
memory {
@@ -50,6 +51,7 @@
};
&sdhci0 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index dcfc00e..fbbb891 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -16,6 +16,8 @@
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
};
memory {
@@ -28,6 +30,10 @@
stdout-path = "serial0:115200n8";
};
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
};
&clkc {
@@ -45,10 +51,22 @@
};
&sdhci0 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
};
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index ac6e40e..caa45cf 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -20,7 +20,15 @@
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
+ unsigned int bmode = readl(&psrc->sbmr2);
+ /*
+ * Check for BMODE if serial downloader is enabled
+ * BOOT_MODE - see IMX6DQRM Table 8-1
+ */
+ if ((((bmode >> 24) & 0x03) == 0x01) || /* Serial Downloader */
+ (gpr10_boot && (reg == 1)))
+ return BOOT_DEVICE_UART;
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & 0x000000FF) >> 4) {
/* EIM: See 8.5.1, Table 8-9 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 6e5224e..49b113d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -166,6 +166,7 @@
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
+#define CONFIG_SYS_FSL_ERRATUM_A009929
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index e7def3a..21b803f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -11,7 +11,8 @@
#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_DCSRBAR 0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
+#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
+#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index d76514e..3b7f6bd 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -16,35 +16,21 @@
#define CONFIG_NR_DRAM_BANKS_MAX 2
/* UART configuration */
-#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
-#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
+#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
(CONFIG_SYS_LPC32XX_UART == 7)
+#if !defined(CONFIG_LPC32XX_HSUART)
#define CONFIG_LPC32XX_HSUART
-#else
-#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
#endif
-
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_NS16550_COM1 UART3_BASE
-#define CONFIG_SYS_NS16550_COM2 UART4_BASE
-#define CONFIG_SYS_NS16550_COM3 UART5_BASE
-#define CONFIG_SYS_NS16550_COM4 UART6_BASE
#endif
-#if defined(CONFIG_LPC32XX_HSUART)
-#if CONFIG_SYS_LPC32XX_UART == 1
-#define HS_UART_BASE HS_UART1_BASE
-#elif CONFIG_SYS_LPC32XX_UART == 2
-#define HS_UART_BASE HS_UART2_BASE
-#else /* CONFIG_SYS_LPC32XX_UART == 7 */
-#define HS_UART_BASE HS_UART7_BASE
+#if !defined(CONFIG_SYS_NS16550_CLK)
+#define CONFIG_SYS_NS16550_CLK 13000000
#endif
+
+#if !defined(CONFIG_LPC32XX_HSUART)
+#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
+#else
+#define CONFIG_CONS_INDEX CONFIG_SYS_LPC32XX_UART
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 2f068e5..f24525e 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -335,10 +335,10 @@
#include <asm/types.h>
/* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
- MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
-#define LCDIF1_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL)) ? \
- MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR
+#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \
+ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
+#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 20ff101..f2b075e 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -25,6 +25,8 @@
void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size);
+
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
#endif
struct mxs_pair {
diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h
index 984c8b9..48ba622 100644
--- a/arch/arm/include/asm/arch-omap4/ehci.h
+++ b/arch/arm/include/asm/arch-omap4/ehci.h
@@ -6,17 +6,7 @@
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _OMAP4_EHCI_H_
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h
index 9d447ab..28f483c 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h
@@ -2,18 +2,7 @@
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_R8A7740_H__
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740.h b/arch/arm/include/asm/arch-rmobile/r8a7740.h
index 8f17950..989da33 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7740.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7740.h
@@ -1,19 +1,7 @@
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_R8A7740_H
diff --git a/arch/arm/include/asm/arch-tegra/funcmux.h b/arch/arm/include/asm/arch-tegra/funcmux.h
index f101e5e..d9bcf60 100644
--- a/arch/arm/include/asm/arch-tegra/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra/funcmux.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra high-level function multiplexing */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
index eeeb247..341df74 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
@@ -3,23 +3,7 @@
*
* Copyright 2010-2011 NVIDIA Corporation
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA_I2C_H_
diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h
index 3f910f5..d451181 100644
--- a/arch/arm/include/asm/arch-tegra114/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra114 clock PLL tables */
diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h
index 9bee397..4d58bf1 100644
--- a/arch/arm/include/asm/arch-tegra114/clock.h
+++ b/arch/arm/include/asm/arch-tegra114/clock.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra114 clock control functions */
diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/include/asm/arch-tegra114/flow.h
index c7eb051..2e4045f 100644
--- a/arch/arm/include/asm/arch-tegra114/flow.h
+++ b/arch/arm/include/asm/arch-tegra114/flow.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_FLOW_H_
diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h
index 7f48f25..9c62cc3 100644
--- a/arch/arm/include/asm/arch-tegra114/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra114/funcmux.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra114 high-level function multiplexing */
diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
index 41ce677..21fa4f2 100644
--- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_GP_PADCTRL_H_
diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h
index 21853b6..d6eaa1b 100644
--- a/arch/arm/include/asm/arch-tegra114/gpio.h
+++ b/arch/arm/include/asm/arch-tegra114/gpio.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_GPIO_H_
diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h
index c6e2381..3104a1b 100644
--- a/arch/arm/include/asm/arch-tegra114/pmu.h
+++ b/arch/arm/include/asm/arch-tegra114/pmu.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_PMU_H_
diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h
index c05e2c3..38220aa 100644
--- a/arch/arm/include/asm/arch-tegra114/sysctr.h
+++ b/arch/arm/include/asm/arch-tegra114/sysctr.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_SYSCTR_H_
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
index c3d061e..f8407d1 100644
--- a/arch/arm/include/asm/arch-tegra114/tegra.h
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_H_
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h
index 37998a4..d97b2c8 100644
--- a/arch/arm/include/asm/arch-tegra124/mc.h
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA124_MC_H_
diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h
index f7c7af8..16b4b96 100644
--- a/arch/arm/include/asm/arch-tegra30/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra30 clock PLL tables */
diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h
index 410c352..46cd7d8 100644
--- a/arch/arm/include/asm/arch-tegra30/clock.h
+++ b/arch/arm/include/asm/arch-tegra30/clock.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra30 clock control functions */
diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/include/asm/arch-tegra30/flow.h
index f5966a8..73cb0ee 100644
--- a/arch/arm/include/asm/arch-tegra30/flow.h
+++ b/arch/arm/include/asm/arch-tegra30/flow.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_FLOW_H_
diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h
index 24b2bca..ae62362 100644
--- a/arch/arm/include/asm/arch-tegra30/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra30/funcmux.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra30 high-level function multiplexing */
diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
index 23d184f..1c50176 100644
--- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_GP_PADCTRL_H_
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
index f1c89f5..d2c6c78 100644
--- a/arch/arm/include/asm/arch-tegra30/gpio.h
+++ b/arch/arm/include/asm/arch-tegra30/gpio.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_GPIO_H_
diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h
index 52bea29..f01c37e 100644
--- a/arch/arm/include/asm/arch-tegra30/pmu.h
+++ b/arch/arm/include/asm/arch-tegra30/pmu.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_PMU_H_
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
index 9367179..280245e 100644
--- a/arch/arm/include/asm/arch-tegra30/tegra.h
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA30_H_
diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h
index c7bca05..5a53e40 100644
--- a/arch/arm/include/asm/ehci-omap.h
+++ b/arch/arm/include/asm/ehci-omap.h
@@ -6,17 +6,7 @@
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com*
* Author: Govindraj R <govindraj.raja@ti.com>
*
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _OMAP_COMMON_EHCI_H_
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 80548eb..2f4c14e 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -83,8 +83,11 @@
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#endif
mov r0, sp
- bl board_init_f_mem
+ bl board_init_f_alloc_reserve
mov sp, r0
+ /* set up gd here, outside any C code */
+ mov r9, r0
+ bl board_init_f_init_reserve
mov r0, #0
bl board_init_f
@@ -133,6 +136,7 @@
bl spl_relocate_stack_gd
cmp r0, #0
movne sp, r0
+ movne r9, r0
# endif
ldr r0, =__bss_start /* this is auto-relocated! */
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index cef1c71..cad22c7 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -75,8 +75,12 @@
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
#endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
- bl board_init_f_mem
+ mov x0, sp
+ bl board_init_f_alloc_reserve
mov sp, x0
+ /* set up gd here, outside any C code */
+ mov x18, x0
+ bl board_init_f_init_reserve
mov x0, #0
bl board_init_f
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index e90d3bb..d2d366b 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -4,14 +4,7 @@
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/arch/arm/mach-bcm283x/lowlevel_init.S b/arch/arm/mach-bcm283x/lowlevel_init.S
index c7b0843..965de1d 100644
--- a/arch/arm/mach-bcm283x/lowlevel_init.S
+++ b/arch/arm/mach-bcm283x/lowlevel_init.S
@@ -4,14 +4,7 @@
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
.globl lowlevel_init
diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c
index 8c37ad9..72cdc31 100644
--- a/arch/arm/mach-bcm283x/reset.c
+++ b/arch/arm/mach-bcm283x/reset.c
@@ -4,14 +4,7 @@
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index d049395..0c4309f 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -135,4 +135,9 @@
#define CONFIG_SYS_I2C_SPEED 100000
#endif
+/* Use common timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
+#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
+
#endif /* _KW_CONFIG_H */
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 79ff0e8..b962846 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,31 +1,74 @@
if ARCH_MVEBU
+config ARMADA_38X
+ bool
+
+config ARMADA_XP
+ bool
+
+config MV78230
+ bool
+ select ARMADA_XP
+
+config MV78260
+ bool
+ select ARMADA_XP
+
+config MV78460
+ bool
+ select ARMADA_XP
+
+config DB_88F6820_GP
+ bool
+ select ARMADA_38X
+
choice
prompt "Marvell MVEBU (Armada XP/38x) board select"
optional
+config TARGET_CLEARFOG
+ bool "Support ClearFog"
+ select DB_88F6820_GP
+
config TARGET_DB_88F6820_GP
bool "Support DB-88F6820-GP"
+ select DB_88F6820_GP
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
+ select MV78460
+
+config TARGET_DS414
+ bool "Support Synology DS414"
+ select MV78230
config TARGET_MAXBCM
bool "Support maxbcm"
+ select MV78460
endchoice
-config SYS_SOC
- default "mvebu"
+config SYS_BOARD
+ default "clearfog" if TARGET_CLEARFOG
+ default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+ default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+ default "ds414" if TARGET_DS414
+ default "maxbcm" if TARGET_MAXBCM
-config MVEBU_BOOTROM_UARTBOOT
- bool "Use kwboot to boot via BootROM xmodem protocol"
- help
- This option provides support for booting via the Marvell
- xmodem protocol, used by the kwboot tool.
+config SYS_CONFIG_NAME
+ default "clearfog" if TARGET_CLEARFOG
+ default "db-88f6820-gp" if TARGET_DB_88F6820_GP
+ default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+ default "ds414" if TARGET_DS414
+ default "maxbcm" if TARGET_MAXBCM
- Please don't forget to configure the boot device in
- the board specific kwbimage.cfg file this way:
- BOOT_FROM uart
+config SYS_VENDOR
+ default "Marvell" if TARGET_DB_MV784MP_GP
+ default "Marvell" if TARGET_DB_88F6820_GP
+ default "solidrun" if TARGET_CLEARFOG
+ default "Synology" if TARGET_DS414
+
+config SYS_SOC
+ default "mvebu"
endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 21c56a4..b96b81b 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -15,8 +15,8 @@
obj-y = cpu.o
obj-y += dram.o
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ../../../drivers/ddr/marvell/a38x/xor.o
-obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ../../../drivers/ddr/marvell/axp/xor.o
+obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
+obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
endif
obj-y += gpio.o
obj-y += mbus.o
@@ -24,7 +24,7 @@
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
-obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += serdes/a38x/
-obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += serdes/axp/
+obj-$(CONFIG_ARMADA_38X) += serdes/a38x/
+obj-$(CONFIG_ARMADA_XP) += serdes/axp/
endif
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 895ad92..30b175c 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -1,11 +1,10 @@
/*
- * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <netdev.h>
#include <ahci.h>
#include <linux/mbus.h>
#include <asm/io.h>
@@ -50,25 +49,106 @@
{
u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
- if (devid == SOC_MV78460_ID)
+ switch (devid) {
+ case SOC_MV78230_ID:
+ case SOC_MV78260_ID:
+ case SOC_MV78460_ID:
return MVEBU_SOC_AXP;
-
- if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
- devid == SOC_88F6828_ID)
+ case SOC_88F6810_ID:
+ case SOC_88F6820_ID:
+ case SOC_88F6828_ID:
return MVEBU_SOC_A38X;
-
+ }
return MVEBU_SOC_UNKNOWN;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
+
+#if defined(CONFIG_ARMADA_38X)
+/* SAR frequency values for Armada 38x */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0x0, 0x0, 666, 333, 333 },
+ { 0x2, 0x0, 800, 400, 400 },
+ { 0x4, 0x0, 1066, 533, 533 },
+ { 0x6, 0x0, 1200, 600, 600 },
+ { 0x8, 0x0, 1332, 666, 666 },
+ { 0xc, 0x0, 1600, 800, 800 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#else
+/* SAR frequency values for Armada XP */
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0xa, 0x5, 800, 400, 400 },
+ { 0x1, 0x5, 1066, 533, 533 },
+ { 0x2, 0x5, 1200, 600, 600 },
+ { 0x2, 0x9, 1200, 600, 400 },
+ { 0x3, 0x5, 1333, 667, 667 },
+ { 0x4, 0x5, 1500, 750, 750 },
+ { 0x4, 0x9, 1500, 750, 500 },
+ { 0xb, 0x9, 1600, 800, 533 },
+ { 0xb, 0xa, 1600, 800, 640 },
+ { 0xb, 0x5, 1600, 800, 800 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
+#endif
+
+void get_sar_freq(struct sar_freq_modes *sar_freq)
+{
+ u32 val;
+ u32 freq;
+ int i;
+
+ val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
+ freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
+#if !defined(CONFIG_ARMADA_38X)
+ /*
+ * Shift CPU0 clock frequency select bit from SAR2 register
+ * into correct position
+ */
+ freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
+ >> SAR2_CPU_FREQ_OFFS) << 3;
+#endif
+ for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
+ if (sar_freq_tab[i].val == freq) {
+#if defined(CONFIG_ARMADA_38X)
+ *sar_freq = sar_freq_tab[i];
+ return;
+#else
+ int k;
+ u8 ffc;
+
+ ffc = (val & SAR_FFC_FREQ_MASK) >>
+ SAR_FFC_FREQ_OFFS;
+ for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
+ if (sar_freq_tab[k].ffc == ffc) {
+ *sar_freq = sar_freq_tab[k];
+ return;
+ }
+ }
+ i = k;
+#endif
+ }
+ }
+
+ /* SAR value not found, return 0 for frequencies */
+ *sar_freq = sar_freq_tab[i - 1];
+}
+
int print_cpuinfo(void)
{
u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
+ struct sar_freq_modes sar_freq;
puts("SoC: ");
switch (devid) {
+ case SOC_MV78230_ID:
+ puts("MV78230-");
+ break;
+ case SOC_MV78260_ID:
+ puts("MV78260-");
+ break;
case SOC_MV78460_ID:
puts("MV78460-");
break;
@@ -89,13 +169,13 @@
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
switch (revid) {
case 1:
- puts("A0\n");
+ puts("A0");
break;
case 2:
- puts("B0\n");
+ puts("B0");
break;
default:
- printf("?? (%x)\n", revid);
+ printf("?? (%x)", revid);
break;
}
}
@@ -103,17 +183,20 @@
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
switch (revid) {
case MV_88F68XX_Z1_ID:
- puts("Z1\n");
+ puts("Z1");
break;
case MV_88F68XX_A0_ID:
- puts("A0\n");
+ puts("A0");
break;
default:
- printf("?? (%x)\n", revid);
+ printf("?? (%x)", revid);
break;
}
}
+ get_sar_freq(&sar_freq);
+ printf(" at %d MHz\n", sar_freq.p_clk);
+
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
@@ -199,10 +282,10 @@
clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
/* Power up PLL and PHY channel */
- clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9));
+ setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
/* Assert VCOCAL_START */
- clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21));
+ setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
mdelay(1);
@@ -211,18 +294,20 @@
*/
for (dev = 0; dev < 3; dev++) {
- clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15));
+ setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
/* Assert REG_RCAL_START in channel REG 1 */
- clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12));
+ setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
udelay(40);
- clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0);
+ clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
}
}
+/*
+ * This function is not called from the SPL U-Boot version
+ */
int arch_cpu_init(void)
{
-#if !defined(CONFIG_SPL_BUILD)
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -233,27 +318,26 @@
* still locked to cache.
*/
mmu_disable();
-#endif
/* Linux expects the internal registers to be at 0xf1000000 */
writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
set_cbar(SOC_REGS_PHY_BASE + 0xC000);
-#if !defined(CONFIG_SPL_BUILD)
/*
* From this stage on, the SoC detection is working. As we have
* configured the internal register base to the value used
* in the macros / defines in the U-Boot header (soc.h).
*/
- /*
- * To fully release / unlock this area from cache, we need
- * to flush all caches and disable the L2 cache.
- */
- icache_disable();
- dcache_disable();
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-#endif
+ if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+ /*
+ * To fully release / unlock this area from cache, we need
+ * to flush all caches and disable the L2 cache.
+ */
+ icache_disable();
+ dcache_disable();
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ }
/*
* We need to call mvebu_mbus_probe() before calling
@@ -326,30 +410,6 @@
}
#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_MVNETA
-int cpu_eth_init(bd_t *bis)
-{
- u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
- MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
- u8 phy_addr[] = CONFIG_PHY_ADDR;
- int i;
-
- /*
- * Only Armada XP supports all 4 ethernet interfaces. A38x has
- * slightly different base addresses for its 2-3 interfaces.
- */
- if (mvebu_soc_family() != MVEBU_SOC_AXP) {
- enet_base[1] = MVEBU_EGIGA2_BASE;
- enet_base[2] = MVEBU_EGIGA3_BASE;
- }
-
- for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
- mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_MV_SDHCI
int board_mmc_init(bd_t *bis)
{
@@ -413,20 +473,43 @@
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
- struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-
- /* First disable L2 cache - may still be enable from BootROM */
- if (mvebu_soc_family() == MVEBU_SOC_A38X)
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
-#endif
+
+void v7_outer_cache_enable(void)
+{
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+ u32 u;
+
+ /* The L2 cache is already disabled at this point */
+
+ /*
+ * For Aurora cache in no outer mode, enable via the CP15
+ * coprocessor broadcasting of cache commands to L2.
+ */
+ asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
+ u |= BIT(8); /* Set the FW bit */
+ asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
+
+ isb();
+
+ /* Enable the L2 cache */
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ }
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c
index ddc5b7e..a8ec5ea 100644
--- a/arch/arm/mach-mvebu/dram.c
+++ b/arch/arm/mach-mvebu/dram.c
@@ -12,14 +12,11 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#ifdef CONFIG_SYS_MVEBU_DDR_A38X
+#if defined(CONFIG_ARCH_MVEBU)
+/* Use common XOR definitions for A3x and AXP */
#include "../../../drivers/ddr/marvell/axp/xor.h"
#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
#endif
-#ifdef CONFIG_SYS_MVEBU_DDR_AXP
-#include "../../../drivers/ddr/marvell/axp/xor.h"
-#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
-#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -112,7 +109,7 @@
mvebu_sdram_bs_set(bank, size);
}
-#if defined(CONFIG_SYS_MVEBU_DDR_A38X) || defined(CONFIG_SYS_MVEBU_DDR_AXP)
+#if defined(CONFIG_ARCH_MVEBU)
static u32 xor_ctrl_save;
static u32 xor_base_save;
static u32 xor_mask_save;
@@ -292,11 +289,18 @@
}
}
+#if defined(CONFIG_ARCH_MVEBU)
void board_add_ram_info(int use_default)
{
+ struct sar_freq_modes sar_freq;
+
+ get_sar_freq(&sar_freq);
+ printf(" (%d MHz, ", sar_freq.d_clk);
+
if (ecc_enabled())
- printf(" (ECC");
+ printf("ECC");
else
- printf(" (ECC not");
+ printf("ECC not");
printf(" enabled)");
}
+#endif
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
index 1d49cab..cc1fc5f 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -17,12 +17,22 @@
#include <asm/arch/soc.h>
-#if defined(CONFIG_ARMADA_XP)
+#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X)
+/*
+ * Set this for the common xor register definitions needed in dram.c
+ * for A38x as well here.
+ */
#define MV88F78X60 /* for the DDR training bin_hdr code */
#endif
#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_L2_PL310
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#endif
+
/*
* By default kwbimage.cfg from board specific folder is used
* If for some board, different configuration file need to be used,
@@ -47,8 +57,7 @@
* SPI Flash configuration
*/
#ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI 1
-#define CONFIG_KIRKWOOD_SPI 1
+#define CONFIG_KIRKWOOD_SPI
#ifndef CONFIG_ENV_SPI_BUS
# define CONFIG_ENV_SPI_BUS 0
#endif
@@ -60,6 +69,9 @@
#endif
#endif
+/* Needed for SPI NOR booting in SPL */
+#define CONFIG_DM_SEQ_ALIAS 1
+
/*
* Ethernet Driver configuration
*/
@@ -85,9 +97,9 @@
#define CONFIG_SYS_I2C_SPEED 100000
#endif
-/* Common SPL configuration */
-#ifndef CONFIG_SPL_LDSCRIPT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds"
-#endif
+/* Use common timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
+#define CONFIG_SYS_TIMER_RATE 25000000
#endif /* __MVEBU_CONFIG_H */
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index 5e8bf0c..47f45c1 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -106,6 +106,14 @@
u32 irq_level;
};
+struct sar_freq_modes {
+ u8 val;
+ u8 ffc; /* Fabric Frequency Configuration */
+ u32 p_clk;
+ u32 nb_clk;
+ u32 d_clk;
+};
+
/* Needed for dynamic (board-specific) mbus configuration */
extern struct mvebu_mbus_state mbus_state;
@@ -123,6 +131,8 @@
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
+void get_sar_freq(struct sar_freq_modes *sar_freq);
+
/*
* Highspeed SERDES PHY config init, ported from bin_hdr
* to mainline U-Boot
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 22abde0..cb216bc 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -11,6 +11,8 @@
#ifndef _MVEBU_SOC_H
#define _MVEBU_SOC_H
+#define SOC_MV78230_ID 0x7823
+#define SOC_MV78260_ID 0x7826
#define SOC_MV78460_ID 0x7846
#define SOC_88F6810_ID 0x6810
#define SOC_88F6820_ID 0x6820
@@ -33,10 +35,11 @@
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
#if defined(CONFIG_SPL_BUILD)
/*
- * On A38x switching the regs base address without running from
- * SDRAM doesn't seem to work. So let the SPL still use the
- * default base address and switch to the new address in the
- * main u-boot later.
+ * The SPL U-Boot version still runs with the default
+ * address for the internal registers, configured by
+ * the BootROM. Only the main U-Boot version uses the
+ * new internal register base address, that also is
+ * required for the Linux kernel.
*/
#define SOC_REGS_PHY_BASE 0xd0000000
#else
@@ -47,10 +50,7 @@
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
-#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
-#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
-#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
@@ -60,13 +60,9 @@
#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
-#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
-#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
#define MVEBU_AXP_USB_BASE (MVEBU_REGISTER(0x50000))
#define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000))
-#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
-#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
@@ -101,4 +97,49 @@
#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
+#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
+
+/* BootROM error register (also includes some status infos) */
+#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
+#define BOOTROM_ERR_MODE_OFFS 28
+#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS)
+#define BOOTROM_ERR_MODE_UART 0x6
+
+#if defined(CONFIG_ARMADA_38X)
+/* SAR values for Armada 38x */
+#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
+
+#define SAR_CPU_FREQ_OFFS 10
+#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS 4
+#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS 4
+#define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART 0x28
+#define BOOT_FROM_SPI 0x32
+#define BOOT_FROM_MMC 0x30
+#define BOOT_FROM_MMC_ALT 0x31
+#else
+/* SAR values for Armada XP */
+#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
+#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
+
+#define SAR_CPU_FREQ_OFFS 21
+#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
+#define SAR_FFC_FREQ_OFFS 24
+#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS)
+#define SAR2_CPU_FREQ_OFFS 20
+#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS 5
+#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS 5
+#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART 0x2
+#define BOOT_FROM_SPI 0x3
+#endif
+
#endif /* _MVEBU_SOC_H */
diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S b/arch/arm/mach-mvebu/lowlevel_spl.S
index 2e2181e..49e0b90 100644
--- a/arch/arm/mach-mvebu/lowlevel_spl.S
+++ b/arch/arm/mach-mvebu/lowlevel_spl.S
@@ -5,7 +5,6 @@
#include <config.h>
#include <linux/linkage.h>
-#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
ENTRY(save_boot_params)
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
@@ -19,11 +18,6 @@
mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */
ENDPROC(return_to_bootrom)
-#else
-ENTRY(save_boot_params)
- b save_boot_params_ret
-ENDPROC(save_boot_params)
-#endif
/*
* cache_inv - invalidate Cache line
diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c
index 346278e..df263bc 100644
--- a/arch/arm/mach-mvebu/mbus.c
+++ b/arch/arm/mach-mvebu/mbus.c
@@ -491,7 +491,7 @@
#if defined(CONFIG_KIRKWOOD)
mbus_state.soc = &kirkwood_mbus_data;
#endif
-#if defined(CONFIG_ARMADA_XP)
+#if defined(CONFIG_ARCH_MVEBU)
mbus_state.soc = &armada_370_xp_mbus_data;
#endif
diff --git a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
index 36e0ed8..c8d9485 100644
--- a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
+++ b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
@@ -32,7 +32,7 @@
#define BOARD_ID_BASE 0x0
/* New board ID numbers */
-#define DB_88F78XX0_BP_ID (BOARD_ID_BASE)
+#define DB_88F78XX0_BP_ID (BOARD_ID_BASE + 1)
#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1)
#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1)
#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1)
@@ -44,7 +44,7 @@
#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1)
#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1)
#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1)
-#define INVALID_BAORD_ID 0xFFFFFFFF
+#define INVALID_BOARD_ID 0xFFFFFFFF
/* Sample at Reset */
#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
index 702273a..afc0cef 100644
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
@@ -75,16 +75,24 @@
#endif
}
-static u8 board_sat_r_get(u8 dev_num, u8 reg)
+__weak u8 board_sat_r_get(u8 dev_num, u8 reg)
{
u8 data;
u8 *dev;
u32 board_id = board_id_get();
int ret;
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
switch (board_id) {
+ case DB_78X60_AMC_ID:
+ case DB_78X60_PCAC_REV2_ID:
+ case RD_78460_CUSTOMER_ID:
+ case RD_78460_SERVER_ID:
+ case RD_78460_SERVER_REV2_ID:
+ case DB_78X60_PCAC_ID:
+ return (0x1 << 1) | 1;
+ case FPGA_88F78XX0_ID:
+ case RD_78460_NAS_ID:
+ return (0x0 << 1) | 1;
case DB_784MP_GP_ID:
dev = rd78460gp_twsi_dev;
@@ -94,15 +102,12 @@
dev = db88f78xx0rev2_twsi_dev;
break;
- case DB_78X60_PCAC_ID:
- case FPGA_88F78XX0_ID:
- case DB_78X60_PCAC_REV2_ID:
- case RD_78460_SERVER_REV2_ID:
default:
return 0;
}
/* Read MPP module ID */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
if (ret)
return MV_ERROR;
@@ -190,8 +195,17 @@
u16 ctrl_model_get(void)
{
- /* Right now only MV78460 supported */
+ /*
+ * SoC version can't be autodetected. So we need to rely on a define
+ * from the config system here.
+ */
+#if defined(CONFIG_MV78230)
+ return MV_78230_DEV_ID;
+#elif defined(CONFIG_MV78260)
+ return MV_78260_DEV_ID;
+#else
return MV_78460_DEV_ID;
+#endif
}
u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
@@ -202,6 +216,20 @@
return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
}
+static int serdes_max_lines_get(void)
+{
+ switch (ctrl_model_get()) {
+ case MV_78230_DEV_ID:
+ return 7;
+ case MV_78260_DEV_ID:
+ return 12;
+ case MV_78460_DEV_ID:
+ return 16;
+ }
+
+ return 0;
+}
+
int serdes_phy_config(void)
{
int status = MV_OK;
@@ -221,39 +249,19 @@
u8 device_rev;
u32 rx_high_imp_mode;
u16 ctrl_mode;
- u32 board_id = board_id_get();
u32 pex_if;
u32 pex_if_num;
/*
- * TODO:
- * Right now we only support the MV78460 with 16 serdes lines
+ * Get max. serdes lines count
*/
- max_serdes_lines = 16;
+ max_serdes_lines = serdes_max_lines_get();
if (max_serdes_lines == 0)
return MV_OK;
- switch (board_id) {
- case DB_78X60_AMC_ID:
- case DB_78X60_PCAC_REV2_ID:
- case RD_78460_CUSTOMER_ID:
- case RD_78460_SERVER_ID:
- case RD_78460_SERVER_REV2_ID:
- case DB_78X60_PCAC_ID:
- satr11 = (0x1 << 1) | 1;
- break;
- case FPGA_88F78XX0_ID:
- case RD_78460_NAS_ID:
- satr11 = (0x0 << 1) | 1;
- break;
- case DB_88F78XX0_BP_REV2_ID:
- case DB_784MP_GP_ID:
- case DB_88F78XX0_BP_ID:
- satr11 = board_sat_r_get(1, 1);
- if ((u8) MV_ERROR == (u8) satr11)
- return MV_ERROR;
- break;
- }
+ satr11 = board_sat_r_get(1, 1);
+ if ((u8) MV_ERROR == (u8) satr11)
+ return MV_ERROR;
board_modules_scan();
memset(addr, 0, sizeof(addr));
@@ -1356,19 +1364,19 @@
pex_if, PEX_DEVICE_AND_VENDOR_ID));
devId &= 0xFFFF;
devId |= ((ctrl_mode << 16) & 0xffff0000);
- DEBUG_INIT_S("Update Device ID PEX");
- DEBUG_INIT_D(pex_if, 1);
- DEBUG_INIT_D(devId, 8);
- DEBUG_INIT_S("\n");
+ DEBUG_INIT_FULL_S("Update Device ID PEX");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_D(devId, 8);
+ DEBUG_INIT_FULL_S("\n");
reg_write(PEX_CFG_DIRECT_ACCESS
(pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
if ((pex_if < 8) &&
(info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
pex_if += 3;
}
- DEBUG_INIT_S("Update PEX Device ID 0x");
- DEBUG_INIT_D(ctrl_mode, 4);
- DEBUG_INIT_S("0\n");
+ DEBUG_INIT_FULL_S("Update PEX Device ID 0x");
+ DEBUG_INIT_FULL_D(ctrl_mode, 4);
+ DEBUG_INIT_FULL_S("0\n");
}
tmp = reg_read(PEX_DBG_STATUS_REG(0));
DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 0ab729a..0879873 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -1,10 +1,13 @@
/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <debug_uart.h>
+#include <fdtdec.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
@@ -12,14 +15,45 @@
DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void)
+static u32 get_boot_device(void)
{
-#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
- return BOOT_DEVICE_SPI;
-#endif
-#if defined(CONFIG_SPL_MMC_SUPPORT)
- return BOOT_DEVICE_MMC1;
+ u32 val;
+ u32 boot_device;
+
+ /*
+ * First check, if UART boot-mode is active. This can only
+ * be done, via the bootrom error register. Here the
+ * MSB marks if the UART mode is active.
+ */
+ val = readl(CONFIG_BOOTROM_ERR_REG);
+ boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
+ debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
+ if (boot_device == BOOTROM_ERR_MODE_UART)
+ return BOOT_DEVICE_UART;
+
+ /*
+ * Now check the SAR register for the strapped boot-device
+ */
+ val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
+ boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
+ debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
+ switch (boot_device) {
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ case BOOT_FROM_MMC:
+ case BOOT_FROM_MMC_ALT:
+ return BOOT_DEVICE_MMC1;
#endif
+ case BOOT_FROM_UART:
+ return BOOT_DEVICE_UART;
+ case BOOT_FROM_SPI:
+ default:
+ return BOOT_DEVICE_SPI;
+ };
+}
+
+u32 spl_boot_device(void)
+{
+ return get_boot_device();
}
#ifdef CONFIG_SPL_MMC_SUPPORT
@@ -31,18 +65,7 @@
void board_init_f(ulong dummy)
{
-#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT
- /*
- * Only call arch_cpu_init() when not returning to the
- * Marvell BootROM, which is done when booting via
- * the xmodem protocol (kwboot tool). Otherwise the
- * internal register will get remapped and the BootROM
- * can't continue to run correctly.
- */
-
- /* Linux expects the internal registers to be at 0xf1000000 */
- arch_cpu_init();
-#endif
+ int ret;
/*
* Pin muxing needs to be done before UART output, since
@@ -51,6 +74,27 @@
*/
board_early_init_f();
+ /* Example code showing how to enable the debug UART on MVEBU */
+#ifdef EARLY_UART
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+#endif
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ /* Use special translation offset for SPL */
+ dm_set_translation_offset(0xd0000000 - 0xf1000000);
+
preloader_console_init();
timer_init();
@@ -61,7 +105,6 @@
/* Setup DDR */
ddr3_init();
-#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
/*
* Return to the BootROM to continue the Marvell xmodem
* UART boot protocol. As initiated by the kwboot tool.
@@ -73,6 +116,6 @@
* need to return to the BootROM to enable this xmodem
* UART download.
*/
- return_to_bootrom();
-#endif
+ if (get_boot_device() == BOOT_DEVICE_UART)
+ return_to_bootrom();
}
diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c
index 5449a89..f5c2eaa 100644
--- a/arch/arm/mach-mvebu/timer.c
+++ b/arch/arm/mach-mvebu/timer.c
@@ -2,6 +2,8 @@
* Copyright (C) Marvell International Ltd. and its affiliates
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,108 +11,14 @@
#include <asm/io.h>
#include <asm/arch/soc.h>
-#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG &tmr_regs->ctrl
-#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload
-#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
-#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
-#if defined(CONFIG_ARMADA_XP)
-#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11)
-#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
-#else
-#define CTCR_ARM_TIMER_25MHZ(cntr) 0
-#endif
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static int init_done __attribute__((section(".data"))) = 0;
-
-/* Timer reload and current value registers */
-struct kwtmr_val {
- u32 reload; /* Timer reload reg */
- u32 val; /* Timer value reg */
-};
-
-/* Timer registers */
-struct kwtmr_registers {
- u32 ctrl; /* Timer control reg */
- u32 pad[3];
- struct kwtmr_val tmr[4];
- u32 wdt_reload;
- u32 wdt_val;
-};
-
DECLARE_GLOBAL_DATA_PTR;
-static struct kwtmr_registers *tmr_regs =
- (struct kwtmr_registers *)MVEBU_TIMER_BASE;
-
-static inline ulong read_timer(void)
-{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000);
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec +
- (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
+#define TIMER_LOAD_VAL 0xffffffff
-void __udelay(unsigned long usec)
-{
- uint current;
- ulong delayticks;
-
- current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
- if (current < delayticks) {
- delayticks -= current;
- while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
- while ((TIMER_LOAD_VAL - delayticks) <
- readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
- } else {
- while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
- (current - delayticks)) ;
- }
-}
+static int init_done __attribute__((section(".data"))) = 0;
/*
- * init the counter
+ * Timer initialization
*/
int timer_init(void)
{
@@ -120,35 +28,15 @@
init_done = 1;
/* load value into timer */
- writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
- writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+ writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10);
+ writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14);
+#if defined(CONFIG_ARCH_MVEBU)
+ /* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */
+ setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11));
+#endif
/* enable timer in auto reload mode */
- clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
- CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
- CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
-
- /* init the timestamp and lastdec value */
- lastdec = read_timer();
- timestamp = 0;
+ setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3);
return 0;
}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/mach-mvebu/u-boot-spl.lds b/arch/arm/mach-mvebu/u-boot-spl.lds
deleted file mode 100644
index eee1db4..0000000
--- a/arch/arm/mach-mvebu/u-boot-spl.lds
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
- LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- .text :
- {
- __start = .;
- arch/arm/cpu/armv7/start.o (.text*)
- *(.text*)
- *(.vectors)
- } >.sram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*_i2c_*)));
- } >.sram
-
- . = ALIGN(4);
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sdram
-}
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index aef1a45..d3bddb7 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -17,21 +17,6 @@
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
-config ROCKCHIP_SPL_HDR
- string "Header of rockchip's spl loader"
- help
- Rockchip's bootrom requires the spl loader to start with a 4-bytes
- header. The content of this header depends on the chip type.
-
-config ROCKCHIP_MAX_SPL_SIZE
- hex "Max size of rockchip's spl loader"
- help
- Different chip may have different sram size. And if we want to jump
- back to the bootrom after spl, we may need to reserve some sram space
- for the bootrom.
- The max spl loader size should be sram size minus reserved
- size(if needed)
-
config SYS_MALLOC_F
default y
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index b703c3c..1cc4a96 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -11,7 +11,6 @@
obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
endif
obj-y += rk_timer.o
-obj-y += rk_early_print.o
obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c
index 3a1491c..8015481 100644
--- a/arch/arm/mach-rockchip/rk3036-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3036-board-spl.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <debug_uart.h>
#include <asm/io.h>
#include <asm/arch/grf_rk3036.h>
#include <asm/arch/hardware.h>
@@ -34,7 +35,7 @@
GPIO1C2_MASK << GPIO1C2_SHIFT,
GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
- rk_uart_init((void *)DEBUG_UART_BASE);
+ debug_uart_init();
#endif
rockchip_timer_init();
sdram_init();
@@ -53,3 +54,9 @@
while (1)
;
}
+
+void hang(void)
+{
+ while (1)
+ ;
+}
diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig
index 95fb2b9..cc03808 100644
--- a/arch/arm/mach-rockchip/rk3036/Kconfig
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -3,21 +3,19 @@
config TARGET_EVB_RK3036
bool "EVB_RK3036"
+config TARGET_KYLIN_RK3036
+ bool "KYLIN_RK3036"
+
config SYS_SOC
default "rockchip"
config SYS_MALLOC_F_LEN
default 0x400
-config ROCKCHIP_SPL_HDR
- default "RK30"
-
-config ROCKCHIP_MAX_SPL_SIZE
- default 0x1000
-
config ROCKCHIP_COMMON
bool "Support rk common fuction"
source "board/evb_rk3036/evb_rk3036/Kconfig"
+source "board/kylin/kylin_rk3036/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 7a05e31..e3ca870 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -701,15 +701,19 @@
static void sdram_all_config(struct rk3036_sdram_priv *priv)
{
u32 os_reg = 0;
+ u32 cs1_row = 0;
struct rk3036_ddr_config config = priv->ddr_config;
+ if (config.rank > 1)
+ cs1_row = config.cs1_row - 13;
+
os_reg = config.ddr_type << DDR_TYPE_SHIFT |
0 << DDR_CHN_CNT_SHIFT |
(config.rank - 1) << DDR_RANK_CNT_SHIFT |
(config.col - 1) << DDR_COL_SHIFT |
(config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT |
(config.cs0_row - 13) << DDR_CS0_ROW_SHIFT |
- (config.cs1_row - 13) << DDR_CS1_ROW_SHIFT |
+ cs1_row << DDR_CS1_ROW_SHIFT |
1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT;
writel(os_reg, &priv->grf->os_reg[1]);
}
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 3de3878..d0a7276 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -16,12 +16,6 @@
WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
-config ROCKCHIP_SPL_HDR
- default "RK32"
-
-config ROCKCHIP_MAX_SPL_SIZE
- default 0x8000
-
config SYS_SOC
default "rockchip"
diff --git a/arch/arm/mach-rockchip/rk_early_print.c b/arch/arm/mach-rockchip/rk_early_print.c
deleted file mode 100644
index a1c14b0..0000000
--- a/arch/arm/mach-rockchip/rk_early_print.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <asm/arch/uart.h>
-#include <common.h>
-
-static struct rk_uart *uart_ptr;
-
-static void uart_wrtie_byte(char byte)
-{
- writel(byte, &uart_ptr->rbr);
- while (!(readl(&uart_ptr->lsr) & 0x40))
- ;
-}
-
-void print(char *s)
-{
- while (*s) {
- if (*s == '\n')
- uart_wrtie_byte('\r');
- uart_wrtie_byte(*s);
- s++;
- }
-}
-
-void print_hex(unsigned int n)
-{
- int i;
- int temp;
-
- uart_wrtie_byte('0');
- uart_wrtie_byte('x');
-
- for (i = 8; i > 0; i--) {
- temp = (n >> (i - 1) * 4) & 0x0f;
- if (temp < 10)
- uart_wrtie_byte((char)(temp + '0'));
- else
- uart_wrtie_byte((char)(temp - 10 + 'a'));
- }
- uart_wrtie_byte('\n');
- uart_wrtie_byte('\r');
-}
-
-/*
- * TODO: since rk3036 only 4K sram to use in SPL, for saving space,
- * we implement uart driver this way, we should convert this to use
- * ns16550 driver in future, which support DEBUG_UART in the standard way
- */
-void rk_uart_init(void *base)
-{
- uart_ptr = (struct rk_uart *)base;
- writel(0x83, &uart_ptr->lcr);
- writel(0x0d, &uart_ptr->rbr);
- writel(0x03, &uart_ptr->lcr);
-
- /* fifo enable, sfe is shadow register of FCR[0] */
- writel(0x01, &uart_ptr->sfe);
-}
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0cb9f9e..dea4ce5 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -2,9 +2,14 @@
config TARGET_SOCFPGA_ARRIA5
bool
+ select TARGET_SOCFPGA_GEN5
config TARGET_SOCFPGA_CYCLONE5
bool
+ select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_GEN5
+ bool
choice
prompt "Altera SOCFPGA board select"
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 316b326..809cd47 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,11 +8,12 @@
#
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
- fpga_manager.o scan_manager.o
+ fpga_manager.o board.o
+
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
# QTS-generated config file wrappers
-obj-y += wrap_pll_config.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o
obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
wrap_sdram_config.o
CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
new file mode 100644
index 0000000..a41d089
--- /dev/null
+++ b/arch/arm/mach-socfpga/board.c
@@ -0,0 +1,64 @@
+/*
+ * Altera SoCFPGA common board code
+ *
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_GADGET
+struct dwc2_plat_otg_data socfpga_otg_data = {
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node[2], count;
+ fdt_addr_t addr;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
+ COMPAT_ALTERA_SOCFPGA_DWC2USB,
+ node, 2);
+ if (count <= 0) /* No controller found. */
+ return 0;
+
+ addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("UDC Controller has no 'reg' property!\n");
+ return -EINVAL;
+ }
+
+ /* Patch the address from OF into the controller pdata. */
+ socfpga_otg_data.regs_otg = addr;
+
+ return dwc2_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index e50fbd8..2f070f2 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -65,12 +65,13 @@
*/
#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NAND RSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6)
#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8)
#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 8712f8e..c45edea 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -129,9 +129,13 @@
#define SYSMGR_FPGAINTF_NAND (1 << 4)
#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
-/* FIXME: This is questionable macro. */
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
- ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#else
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#endif
+
+#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
/* EMAC Group Bit definitions */
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index b110f5b..9b43b92 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -54,14 +54,23 @@
void v7_outer_cache_enable(void)
{
- /* disable the L2 cache */
- writel(0, &pl310->pl310_ctrl);
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |
L310_AUX_CTRL_INST_PREFETCH_MASK |
L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ /* Enable the L2 cache */
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
/*
@@ -350,6 +359,10 @@
socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
#endif
+#ifdef CONFIG_NAND_DENALI
+ socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
+
return 0;
}
diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh
index c1640bc..1adfbf7 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -3,13 +3,15 @@
#
# Process iocsr_config_*.[ch]
# $1: SoC type
-# $2: Input directory
-# $3: Output directory
+# $2: Input handoff directory
+# $3: Input BSP Generated directory
+# $4: Output directory
#
process_iocsr_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -26,13 +28,13 @@
# Retrieve the scan chain lengths
grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
- ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
echo ""
# Retrieve the scan chain config and zap the ad-hoc length encoding
sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
- ${in_dir}/generated/iocsr_config_${soc}.c
+ ${in_bsp_dir}/generated/iocsr_config_${soc}.c
cat << EOF
@@ -49,8 +51,9 @@
#
process_pinmux_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -67,7 +70,7 @@
# Retrieve the pinmux config and zap the ad-hoc length encoding
sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \
- ${in_dir}/generated/pinmux_config_${soc}.c
+ ${in_bsp_dir}/generated/pinmux_config_${soc}.c
cat << EOF
@@ -84,8 +87,9 @@
#
process_pll_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -102,7 +106,7 @@
# Retrieve the pll config and zap parenthesis
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \
- ${in_dir}/generated/pll_config.h
+ ${in_bsp_dir}/generated/pll_config.h
cat << EOF
@@ -126,8 +130,9 @@
#
process_sdram_config() {
soc="$1"
- in_dir="$2"
- out_dir="$3"
+ in_qts_dir="$2"
+ in_bsp_dir="$3"
+ out_dir="$4"
(
cat << EOF
@@ -144,29 +149,32 @@
echo "/* SDRAM configuration */"
# Retrieve the sdram config, zap broken lines and zap parenthesis
- sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" ${in_dir}/generated/sdram/sdram_config.h |
+ sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" \
+ ${in_bsp_dir}/generated/sdram/sdram_config.h |
sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
sort -u | grep_sdram_config
echo ""
echo "/* Sequencer auto configuration */"
sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
- ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u | grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer defines configuration */"
sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
- ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u | grep_sdram_config
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
+ sort -u | grep_sdram_config
echo ""
echo "/* Sequencer ac_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
echo ""
echo "/* Sequencer inst_rom_init configuration */"
sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
- ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+ ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
cat << EOF
@@ -176,30 +184,36 @@
}
usage() {
- echo "$0 [soc_type] [input_dir] [output_dir]"
+ echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
echo "Process QTS-generated headers into U-Boot compatible ones."
echo ""
- echo " soc_type\t\tType of SoC, either 'cyclone5' or 'arria5',"
- echo " input_dir\t\tDirectory with the QTS project."
- echo " output_dir\t\tDirectory to store the U-Boot compatible headers."
+ echo -e " soc_type\t-\tType of SoC, either 'cyclone5' or 'arria5'."
+ echo -e " input_qts_dir\t-\tDirectory with compiled Quartus project"
+ echo -e "\t\t\t\tand containing the Quartus project file (QPF)."
+ echo -e " input_bsp_dir\t-\tDirectory with generated bsp containing"
+ echo -e "\t\t\t\tthe settings.bsp file."
+ echo -e " output_dir\t-\tDirectory to store the U-Boot compatible"
+ echo -e "\t\t\t\theaders."
echo ""
}
soc="$1"
-in_dir="$2"
-out_dir="$3"
+in_qts_dir="$2"
+in_bsp_dir="$3"
+out_dir="$4"
-if [ "$#" -ne 3 ] ; then
+if [ "$#" -ne 4 ] ; then
usage
exit 1
fi
-if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then
+if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
+ ! -d "${out_dir}" -o -z "${soc}" ] ; then
usage
exit 3
fi
-process_iocsr_config "${soc}" "${in_dir}" "${out_dir}"
-process_pinmux_config "${soc}" "${in_dir}" "${out_dir}"
-process_pll_config "${soc}" "${in_dir}" "${out_dir}"
-process_sdram_config "${soc}" "${in_dir}" "${out_dir}"
+process_iocsr_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
+process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
+process_pll_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
+process_sdram_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 775a827..98c16a0 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -40,6 +40,7 @@
return BOOT_DEVICE_RAM;
case 0x2: /* NAND Flash (1.8V) */
case 0x3: /* NAND Flash (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
return BOOT_DEVICE_NAND;
case 0x4: /* SD/MMC External Transceiver (1.8V) */
case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index fbfb204..48a387c 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -3,6 +3,7 @@
config TEGRA_COMMON
bool "Tegra common options"
select DM
+ select DM_ETH
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c
index 0e9cb97..6dad403 100644
--- a/arch/arm/mach-tegra/cache.c
+++ b/arch/arm/mach-tegra/cache.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra cache routines */
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index f75c6c6..c50d56d 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra SoC common clock control functions */
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index ba04a56..a3ebb57 100644
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
index c7d705d..0dbddd4 100644
--- a/arch/arm/mach-tegra/gpu.c
+++ b/arch/arm/mach-tegra/gpu.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra vpr routines */
diff --git a/arch/arm/mach-tegra/tegra114/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c
index 52441c7..ca9d970 100644
--- a/arch/arm/mach-tegra/tegra114/funcmux.c
+++ b/arch/arm/mach-tegra/tegra114/funcmux.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra114 high-level function multiplexing */
diff --git a/arch/arm/mach-tegra/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c
index 67f49d7..7fbc2e2 100644
--- a/arch/arm/mach-tegra/tegra20/cpu.c
+++ b/arch/arm/mach-tegra/tegra20/cpu.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c
index c76e74c..66b021b 100644
--- a/arch/arm/mach-tegra/tegra30/cpu.c
+++ b/arch/arm/mach-tegra/tegra30/cpu.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/arch/arm/mach-tegra/tegra30/funcmux.c b/arch/arm/mach-tegra/tegra30/funcmux.c
index 409335c..8c68339 100644
--- a/arch/arm/mach-tegra/tegra30/funcmux.c
+++ b/arch/arm/mach-tegra/tegra30/funcmux.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
/* Tegra30 high-level function multiplexing */
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 9e6ac3a..03256be 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -70,8 +70,17 @@
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
+ depends on ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 || \
+ ARCH_UNIPHIER_PH1_SLD8
help
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
+config CMD_DDRMPHY_DUMP
+ bool "Enable dump command of DDR Multi PHY parameters"
+ depends on ARCH_UNIPHIER_PROXSTREAM2 || ARCH_UNIPHIER_PH1_LD6B
+ help
+ The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
+ training; it is useful for the evaluation of DDR Multi PHY training.
+
endif
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index b597a13..ea3ae54 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -6,9 +6,8 @@
obj-y += lowlevel_init.o
obj-y += init_page_table.o
-obj-y += boards.o
-obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/
+obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
obj-$(CONFIG_DEBUG_LL) += debug_ll.o
@@ -25,14 +24,13 @@
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-y += reset.o
obj-y += cache_uniphier.o
-obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
-obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
obj-y += pinctrl/ clk/
endif
obj-y += timer.o
+obj-y += boards.o
obj-y += soc_info.o
obj-y += boot-mode/
diff --git a/arch/arm/mach-uniphier/include/mach/arm-mpcore.h b/arch/arm/mach-uniphier/arm-mpcore.h
similarity index 100%
rename from arch/arm/mach-uniphier/include/mach/arm-mpcore.h
rename to arch/arm/mach-uniphier/arm-mpcore.h
diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
index e9d3761..f82c7d1 100644
--- a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/bcu-regs.h>
-#include <mach/init.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
index cb6f862..75ccd15 100644
--- a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/bcu-regs.h>
-#include <mach/init.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
diff --git a/arch/arm/mach-uniphier/include/mach/bcu-regs.h b/arch/arm/mach-uniphier/bcu/bcu-regs.h
similarity index 100%
rename from arch/arm/mach-uniphier/include/mach/bcu-regs.h
rename to arch/arm/mach-uniphier/bcu/bcu-regs.h
diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c
index 198004b..020ffca 100644
--- a/arch/arm/mach-uniphier/board_common.c
+++ b/arch/arm/mach-uniphier/board_common.c
@@ -5,7 +5,8 @@
*/
#include <common.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
int board_init(void)
{
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index 5e0d246..824da25 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
-#include <mach/soc_info.h>
+#include "init.h"
+#include "micro-support-card.h"
+#include "soc-info.h"
int board_early_init_f(void)
{
diff --git a/arch/arm/mach-uniphier/board_early_init_r.c b/arch/arm/mach-uniphier/board_early_init_r.c
index 28c7f82..b26da36 100644
--- a/arch/arm/mach-uniphier/board_early_init_r.c
+++ b/arch/arm/mach-uniphier/board_early_init_r.c
@@ -5,7 +5,8 @@
*/
#include <common.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
int board_early_init_r(void)
{
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index a7530eb..c2a3261 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <spl.h>
+#include <libfdt.h>
#include <nand.h>
#include <linux/io.h>
#include <../drivers/mtd/nand/denali.h>
@@ -25,6 +26,38 @@
#endif
}
+struct uniphier_fdt_file {
+ const char *compatible;
+ const char *file_name;
+};
+
+static const struct uniphier_fdt_file uniphier_fdt_files[] = {
+ { "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
+ { "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
+ { "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
+ { "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
+ { "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", },
+ { "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", },
+ { "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", },
+ { "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", },
+ { "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", },
+};
+
+static void uniphier_set_fdt_file(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ int i;
+
+ /* lookup DTB file name based on the compatible string */
+ for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) {
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+ uniphier_fdt_files[i].compatible)) {
+ setenv("fdt_file", uniphier_fdt_files[i].file_name);
+ return;
+ }
+ }
+}
+
int board_late_init(void)
{
puts("MODE: ");
@@ -48,5 +81,7 @@
return -1;
}
+ uniphier_set_fdt_file();
+
return 0;
}
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 812c58f..f124150 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -4,9 +4,13 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
#include <libfdt.h>
#include <linux/kernel.h>
-#include <mach/init.h>
+
+#include "init.h"
+
+DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
static const struct uniphier_board_data ph1_sld3_data = {
@@ -71,8 +75,7 @@
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
static const struct uniphier_board_data proxstream2_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x40000000,
@@ -83,6 +86,21 @@
.dram_ch2_base = 0xe0000000,
.dram_ch2_size = 0x20000000,
.dram_ch2_width = 16,
+ .dram_freq = 2133,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+static const struct uniphier_board_data ph1_ld6b_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x40000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xc0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 32,
+ .dram_ch2_base = 0xe0000000,
+ .dram_ch2_size = 0x20000000,
+ .dram_ch2_width = 16,
.dram_freq = 1866,
};
#endif
@@ -112,16 +130,16 @@
{ "socionext,proxstream2", &proxstream2_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- { "socionext,ph1-ld6b", &proxstream2_data, },
+ { "socionext,ph1-ld6b", &ph1_ld6b_data, },
#endif
};
-const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
+const struct uniphier_board_data *uniphier_get_board_param(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
- if (!fdt_node_check_compatible(fdt, 0,
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0,
uniphier_boards[i].compatible))
return uniphier_boards[i].param;
}
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index 0797d6e..be0de8f 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -11,3 +11,5 @@
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += boot-mode-ph1-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += boot-mode-proxstream2.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += boot-mode-proxstream2.o
+
+obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h
similarity index 100%
rename from arch/arm/mach-uniphier/include/mach/boot-device.h
rename to arch/arm/mach-uniphier/boot-mode/boot-device.h
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c
index f974d9f..8334373 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c
@@ -7,9 +7,9 @@
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
-#include <mach/sbc-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c
index c68cb59..0ec6a08 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c
@@ -7,9 +7,9 @@
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c
index c943e12..b0f3f9a 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c
@@ -7,9 +7,9 @@
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
-#include <mach/sbc-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
index 10a47c6..de12953 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
@@ -7,10 +7,9 @@
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index c6cafa7..0c5749b 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -6,10 +6,10 @@
#include <common.h>
#include <spl.h>
-#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/soc_info.h>
+
+#include "../sbc/sbc-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
u32 spl_boot_device(void)
{
diff --git a/arch/arm/mach-uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
similarity index 92%
rename from arch/arm/mach-uniphier/cmd_pinmon.c
rename to arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
index b15ee9d..3ff756b 100644
--- a/arch/arm/mach-uniphier/cmd_pinmon.c
+++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
@@ -5,9 +5,10 @@
*/
#include <common.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/soc_info.h>
+
+#include "../sbc/sbc-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c
index bf85ad6..b4ca8b6 100644
--- a/arch/arm/mach-uniphier/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/cache_uniphier.c
@@ -7,7 +7,8 @@
#include <common.h>
#include <linux/io.h>
#include <asm/armv7.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
static void uniphier_cache_maint_all(u32 operation)
diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
index 8b95fbb..4de9bfb 100644
--- a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_ld4_clk_init(void)
{
diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
index 2e1b20a..3df017e 100644
--- a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_pro4_clk_init(void)
{
diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c
index f78edbb..039da73 100644
--- a/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_pro5_clk_init(void)
{
diff --git a/arch/arm/mach-uniphier/clk/clk-proxstream2.c b/arch/arm/mach-uniphier/clk/clk-proxstream2.c
index b494021..a528f04 100644
--- a/arch/arm/mach-uniphier/clk/clk-proxstream2.c
+++ b/arch/arm/mach-uniphier/clk/clk-proxstream2.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void proxstream2_clk_init(void)
{
diff --git a/arch/arm/mach-uniphier/cmd_ddrmphy.c b/arch/arm/mach-uniphier/cmd_ddrmphy.c
new file mode 100644
index 0000000..c18f099
--- /dev/null
+++ b/arch/arm/mach-uniphier/cmd_ddrmphy.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "ddrmphy-regs.h"
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS " "
+
+static void __iomem *get_phy_base(int ch)
+{
+ return (void __iomem *)(0x5b830000 + ch * 0x00200000);
+}
+
+static int get_nr_ch(void)
+{
+ const struct uniphier_board_data *bd = uniphier_get_board_param();
+
+ return bd->dram_ch2_width ? 3 : 2;
+}
+
+static int get_nr_datx8(int ch)
+{
+ unsigned int width;
+
+ const struct uniphier_board_data *bd = uniphier_get_board_param();
+
+ switch (ch) {
+ case 0:
+ width = bd->dram_ch0_width;
+ break;
+ case 1:
+ width = bd->dram_ch1_width;
+ break;
+ default:
+ width = bd->dram_ch2_width;
+ break;
+ }
+
+ return width / 8;
+}
+
+static void print_bdl(void __iomem *reg, int n)
+{
+ u32 val = readl(reg);
+ int i;
+
+ for (i = 0; i < n; i++)
+ printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
+}
+
+static void dump_loop(void (*callback)(void __iomem *))
+{
+ int ch, dx, nr_ch, nr_dx;
+ void __iomem *dx_base;
+
+ nr_ch = get_nr_ch();
+
+ for (ch = 0; ch < nr_ch; ch++) {
+ dx_base = get_phy_base(ch) + DMPHY_DX_BASE;
+ nr_dx = get_nr_datx8(ch);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ printf("CH%dDX%d:", ch, dx);
+ (*callback)(dx_base);
+ dx_base += DMPHY_DX_STRIDE;
+ printf("\n");
+ }
+ }
+}
+
+static void zq_dump(void)
+{
+ int ch, zq, nr_ch, nr_zq, i;
+ void __iomem *zq_base;
+ u32 dr, pr;
+
+ printf("\n--- Impedance Data ---\n");
+ printf(" ZPD ZPU OPD OPU ZDV ODV\n");
+
+ nr_ch = get_nr_ch();
+
+ for (ch = 0; ch < nr_ch; ch++) {
+ zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE;
+ nr_zq = 3;
+
+ for (zq = 0; zq < nr_zq; zq++) {
+ printf("CH%dZQ%d:", ch, zq);
+
+ dr = readl(zq_base + DMPHY_ZQ_DR);
+ for (i = 0; i < 4; i++) {
+ printf(FS PRINTF_FORMAT, dr & 0x7f);
+ dr >>= 7;
+ }
+
+ pr = readl(zq_base + DMPHY_ZQ_PR);
+ for (i = 0; i < 2; i++) {
+ printf(FS PRINTF_FORMAT, pr & 0xf);
+ pr >>= 4;
+ }
+
+ zq_base += DMPHY_ZQ_STRIDE;
+ printf("\n");
+ }
+ }
+}
+
+static void __wbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + DMPHY_DX_BDLR0, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR1, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR2, 2);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ readl(dx_base + DMPHY_DX_LCDLR1) & 0xff);
+}
+
+static void wbdl_dump(void)
+{
+ printf("\n--- Write Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
+
+ dump_loop(&__wbdl_dump);
+}
+
+static void __rbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + DMPHY_DX_BDLR3, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR4, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR5, 1);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff);
+}
+
+static void rbdl_dump(void)
+{
+ printf("\n--- Read Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
+
+ dump_loop(&__rbdl_dump);
+}
+
+static void __wld_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0);
+ u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+ u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "%sT", wld,
+ wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+ }
+}
+
+static void wld_dump(void)
+{
+ printf("\n--- Write Leveling Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__wld_dump);
+}
+
+static void __dqsgd_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2);
+ u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+ u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+ }
+}
+
+static void dqsgd_dump(void)
+{
+ printf("\n--- DQS Gating Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__dqsgd_dump);
+}
+
+static void __mdl_dump(void __iomem *dx_base)
+{
+ int i;
+ u32 mdl = readl(dx_base + DMPHY_DX_MDLR);
+
+ for (i = 0; i < 3; i++)
+ printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+static void mdl_dump(void)
+{
+ printf("\n--- Master Delay Line ---\n");
+ printf(" IPRD TPRD MDLD\n");
+
+ dump_loop(&__mdl_dump);
+}
+
+#define REG_DUMP(x) \
+ { int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst; \
+ printf("%3d: %-10s: %p : %08x\n", \
+ ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); }
+
+#define DX_REG_DUMP(dx, x) \
+ { int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) + \
+ DMPHY_DX_## x; \
+ void __iomem *reg = phy_base + ofst; \
+ printf("%3d: DX%d%-7s: %p : %08x\n", \
+ ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); }
+
+static void reg_dump(void)
+{
+ int ch, dx, nr_ch, nr_dx;
+ void __iomem *phy_base;
+
+ printf("\n--- DDR PHY registers ---\n");
+
+ nr_ch = get_nr_ch();
+
+ for (ch = 0; ch < nr_ch; ch++) {
+ phy_base = get_phy_base(ch);
+ nr_dx = get_nr_datx8(ch);
+
+ printf("== Ch%d ==\n", ch);
+ printf(" No: Name : Address : Data\n");
+
+ REG_DUMP(RIDR);
+ REG_DUMP(PIR);
+ REG_DUMP(PGCR0);
+ REG_DUMP(PGCR1);
+ REG_DUMP(PGCR2);
+ REG_DUMP(PGCR3);
+ REG_DUMP(PGSR0);
+ REG_DUMP(PGSR1);
+ REG_DUMP(PLLCR);
+ REG_DUMP(PTR0);
+ REG_DUMP(PTR1);
+ REG_DUMP(PTR2);
+ REG_DUMP(PTR3);
+ REG_DUMP(PTR4);
+ REG_DUMP(ACMDLR);
+ REG_DUMP(ACBDLR0);
+ REG_DUMP(DXCCR);
+ REG_DUMP(DSGCR);
+ REG_DUMP(DCR);
+ REG_DUMP(DTPR0);
+ REG_DUMP(DTPR1);
+ REG_DUMP(DTPR2);
+ REG_DUMP(DTPR3);
+ REG_DUMP(MR0);
+ REG_DUMP(MR1);
+ REG_DUMP(MR2);
+ REG_DUMP(MR3);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ DX_REG_DUMP(dx, GCR0);
+ DX_REG_DUMP(dx, GCR1);
+ DX_REG_DUMP(dx, GCR2);
+ DX_REG_DUMP(dx, GCR3);
+ DX_REG_DUMP(dx, GTR);
+ }
+ }
+}
+
+static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *cmd = argv[1];
+
+ if (argc == 1)
+ cmd = "all";
+
+ if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
+ zq_dump();
+
+ if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+ wbdl_dump();
+
+ if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+ rbdl_dump();
+
+ if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+ wld_dump();
+
+ if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+ dqsgd_dump();
+
+ if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+ mdl_dump();
+
+ if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+ reg_dump();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ddrm, 2, 1, do_ddrm,
+ "UniPhier DDR PHY parameters dumper",
+ "- dump all of the followings\n"
+ "ddrm zq - dump Impedance Data\n"
+ "ddrm wbdl - dump Write Bit Delay\n"
+ "ddrm rbdl - dump Read Bit Delay\n"
+ "ddrm wld - dump Write Leveling\n"
+ "ddrm dqsgd - dump DQS Gating Delay\n"
+ "ddrm mdl - dump Master Delay Line\n"
+ "ddrm reg - dump registers\n"
+);
diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c
index 5d9ed84..4e9d01b 100644
--- a/arch/arm/mach-uniphier/cpu_info.c
+++ b/arch/arm/mach-uniphier/cpu_info.c
@@ -6,7 +6,8 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/sg-regs.h>
+
+#include "sg-regs.h"
int print_cpuinfo(void)
{
@@ -43,13 +44,18 @@
case 0x2F:
puts("PH1-LD6b (MN2WS0320)");
break;
+ case 0x31:
+ puts("PH1-sLD11 ()");
+ break;
+ case 0x32:
+ puts("PH1-LD10 ()");
+ break;
default:
printf("Unknown Processor ID (0x%x)\n", revision);
return -1;
}
- if (model > 1)
- printf(" model %d", model);
+ printf(" model %d", model);
printf(" (rev. %d)\n", rev);
diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile b/arch/arm/mach-uniphier/ddrphy/Makefile
deleted file mode 100644
index d0f4bd3..0000000
--- a/arch/arm/mach-uniphier/ddrphy/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o
diff --git a/arch/arm/mach-uniphier/debug_ll.S b/arch/arm/mach-uniphier/debug_ll.S
index d8c9fe4..6aa5f89 100644
--- a/arch/arm/mach-uniphier/debug_ll.S
+++ b/arch/arm/mach-uniphier/debug_ll.S
@@ -8,9 +8,10 @@
#include <linux/serial_reg.h>
#include <linux/linkage.h>
-#include <mach/bcu-regs.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "bcu/bcu-regs.h"
+#include "sc-regs.h"
+#include "sg-regs.h"
#if !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
new file mode 100644
index 0000000..cab7df1
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -0,0 +1,15 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \
+ ddrphy-training.o ddrphy-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \
+ ddrphy-training.o ddrphy-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \
+ ddrphy-training.o ddrphy-ph1-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o
+
+obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
+obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o
diff --git a/arch/arm/mach-uniphier/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
similarity index 95%
rename from arch/arm/mach-uniphier/cmd_ddrphy.c
rename to arch/arm/mach-uniphier/dram/cmd_ddrphy.c
index dbbefd4..078eb6f 100644
--- a/arch/arm/mach-uniphier/cmd_ddrphy.c
+++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
@@ -6,7 +6,8 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
/* Select either decimal or hexadecimal */
#if 1
@@ -50,7 +51,7 @@
printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
}
-void wbdl_dump(void)
+static void wbdl_dump(void)
{
printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
@@ -68,7 +69,7 @@
printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
}
-void rbdl_dump(void)
+static void rbdl_dump(void)
{
printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
@@ -91,7 +92,7 @@
}
}
-void wld_dump(void)
+static void wld_dump(void)
{
printf("\n--- Write Leveling Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
@@ -113,7 +114,7 @@
}
}
-void dqsgd_dump(void)
+static void dqsgd_dump(void)
{
printf("\n--- DQS Gating Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
@@ -129,7 +130,7 @@
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
-void mdl_dump(void)
+static void mdl_dump(void)
{
printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n");
@@ -141,7 +142,7 @@
{ u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
p - (u32 *)phy, #x, p, readl(p)); }
-void reg_dump(void)
+static void reg_dump(void)
{
int ch, p;
struct ddrphy __iomem *phy;
diff --git a/arch/arm/mach-uniphier/dram/ddrmphy-regs.h b/arch/arm/mach-uniphier/dram/ddrmphy-regs.h
new file mode 100644
index 0000000..569504d
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/ddrmphy-regs.h
@@ -0,0 +1,146 @@
+/*
+ * UniPhier DDR MultiPHY registers
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRMPHY_REGS_H
+#define ARCH_DDRMPHY_REGS_H
+
+#include <linux/bitops.h>
+
+#define DMPHY_SHIFT 2
+
+#define DMPHY_RIDR (0x000 << DMPHY_SHIFT)
+#define DMPHY_PIR (0x001 << DMPHY_SHIFT)
+#define DMPHY_PIR_INIT BIT(0) /* Initialization Trigger */
+#define DMPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define DMPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define DMPHY_PIR_DCAL BIT(5) /* DDL Calibration */
+#define DMPHY_PIR_PHYRST BIT(6) /* PHY Reset */
+#define DMPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define DMPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define DMPHY_PIR_WL BIT(9) /* Write Leveling */
+#define DMPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define DMPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define DMPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define DMPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define DMPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define DMPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define DMPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define DMPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
+#define DMPHY_PGCR0 (0x002 << DMPHY_SHIFT)
+#define DMPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
+#define DMPHY_PGCR1 (0x003 << DMPHY_SHIFT)
+#define DMPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
+#define DMPHY_PGCR2 (0x004 << DMPHY_SHIFT)
+#define DMPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
+#define DMPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
+#define DMPHY_PGCR3 (0x005 << DMPHY_SHIFT)
+#define DMPHY_PGSR0 (0x006 << DMPHY_SHIFT)
+#define DMPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
+#define DMPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define DMPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define DMPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define DMPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define DMPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define DMPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define DMPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define DMPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define DMPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define DMPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define DMPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define DMPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
+#define DMPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define DMPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define DMPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define DMPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define DMPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define DMPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define DMPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define DMPHY_PGSR1 (0x007 << DMPHY_SHIFT)
+#define DMPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
+#define DMPHY_PLLCR (0x008 << DMPHY_SHIFT)
+#define DMPHY_PTR0 (0x009 << DMPHY_SHIFT)
+#define DMPHY_PTR1 (0x00A << DMPHY_SHIFT)
+#define DMPHY_PTR2 (0x00B << DMPHY_SHIFT)
+#define DMPHY_PTR3 (0x00C << DMPHY_SHIFT)
+#define DMPHY_PTR4 (0x00D << DMPHY_SHIFT)
+#define DMPHY_ACMDLR (0x00E << DMPHY_SHIFT)
+#define DMPHY_ACLCDLR (0x00F << DMPHY_SHIFT)
+#define DMPHY_ACBDLR0 (0x010 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR1 (0x011 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR2 (0x012 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR3 (0x013 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR4 (0x014 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR5 (0x015 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR6 (0x016 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR7 (0x017 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR8 (0x018 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR9 (0x019 << DMPHY_SHIFT)
+#define DMPHY_ACIOCR0 (0x01A << DMPHY_SHIFT)
+#define DMPHY_ACIOCR1 (0x01B << DMPHY_SHIFT)
+#define DMPHY_ACIOCR2 (0x01C << DMPHY_SHIFT)
+#define DMPHY_ACIOCR3 (0x01D << DMPHY_SHIFT)
+#define DMPHY_ACIOCR4 (0x01E << DMPHY_SHIFT)
+#define DMPHY_ACIOCR5 (0x01F << DMPHY_SHIFT)
+#define DMPHY_DXCCR (0x020 << DMPHY_SHIFT)
+#define DMPHY_DSGCR (0x021 << DMPHY_SHIFT)
+#define DMPHY_DCR (0x022 << DMPHY_SHIFT)
+#define DMPHY_DTPR0 (0x023 << DMPHY_SHIFT)
+#define DMPHY_DTPR1 (0x024 << DMPHY_SHIFT)
+#define DMPHY_DTPR2 (0x025 << DMPHY_SHIFT)
+#define DMPHY_DTPR3 (0x026 << DMPHY_SHIFT)
+#define DMPHY_MR0 (0x027 << DMPHY_SHIFT)
+#define DMPHY_MR1 (0x028 << DMPHY_SHIFT)
+#define DMPHY_MR2 (0x029 << DMPHY_SHIFT)
+#define DMPHY_MR3 (0x02A << DMPHY_SHIFT)
+#define DMPHY_ODTCR (0x02B << DMPHY_SHIFT)
+#define DMPHY_DTCR (0x02C << DMPHY_SHIFT)
+#define DMPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define DMPHY_DTCR_RANKEN_MASK (0xf << (DMPHY_DTCR_RANKEN_SHIFT))
+#define DMPHY_DTAR0 (0x02D << DMPHY_SHIFT)
+#define DMPHY_DTAR1 (0x02E << DMPHY_SHIFT)
+#define DMPHY_DTAR2 (0x02F << DMPHY_SHIFT)
+#define DMPHY_DTAR3 (0x030 << DMPHY_SHIFT)
+#define DMPHY_DTDR0 (0x031 << DMPHY_SHIFT)
+#define DMPHY_DTDR1 (0x032 << DMPHY_SHIFT)
+#define DMPHY_DTEDR0 (0x033 << DMPHY_SHIFT)
+#define DMPHY_DTEDR1 (0x034 << DMPHY_SHIFT)
+#define DMPHY_ZQCR (0x090 << DMPHY_SHIFT)
+#define DMPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
+#define DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */
+/* ZQ */
+#define DMPHY_ZQ_BASE (0x091 << DMPHY_SHIFT)
+#define DMPHY_ZQ_STRIDE (0x004 << DMPHY_SHIFT)
+#define DMPHY_ZQ_PR (0x000 << DMPHY_SHIFT)
+#define DMPHY_ZQ_DR (0x001 << DMPHY_SHIFT)
+#define DMPHY_ZQ_SR (0x002 << DMPHY_SHIFT)
+/* DATX8 */
+#define DMPHY_DX_BASE (0x0A0 << DMPHY_SHIFT)
+#define DMPHY_DX_STRIDE (0x020 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR0 (0x000 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define DMPHY_DX_GCR0_WLRKEN_MASK (0xf << (DMPHY_DX_GCR0_WLRKEN_SHIFT))
+#define DMPHY_DX_GCR1 (0x001 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR2 (0x002 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR3 (0x003 << DMPHY_SHIFT)
+#define DMPHY_DX_GSR0 (0x004 << DMPHY_SHIFT)
+#define DMPHY_DX_GSR1 (0x005 << DMPHY_SHIFT)
+#define DMPHY_DX_GSR2 (0x006 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR0 (0x007 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR1 (0x008 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR2 (0x009 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR3 (0x00A << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR4 (0x00B << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR5 (0x00C << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR6 (0x00D << DMPHY_SHIFT)
+#define DMPHY_DX_LCDLR0 (0x00E << DMPHY_SHIFT)
+#define DMPHY_DX_LCDLR1 (0x00F << DMPHY_SHIFT)
+#define DMPHY_DX_LCDLR2 (0x010 << DMPHY_SHIFT)
+#define DMPHY_DX_MDLR (0x011 << DMPHY_SHIFT)
+#define DMPHY_DX_GTR (0x012 << DMPHY_SHIFT)
+
+#endif /* ARCH_DDRMPHY_REGS_H */
diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
similarity index 97%
rename from arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c
rename to arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
index 991d929..d2bc5a1 100644
--- a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
@@ -6,7 +6,8 @@
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
similarity index 97%
rename from arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c
rename to arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
index bc47ba3..2c8cbc2 100644
--- a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
@@ -6,7 +6,8 @@
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
similarity index 98%
rename from arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c
rename to arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
index 39024a0..6510690 100644
--- a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
@@ -7,7 +7,8 @@
#include <config.h>
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
similarity index 63%
rename from arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
rename to arch/arm/mach-uniphier/dram/ddrphy-regs.h
index adcc972..03aedc2 100644
--- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
@@ -9,6 +9,7 @@
#ifndef ARCH_DDRPHY_REGS_H
#define ARCH_DDRPHY_REGS_H
+#include <linux/bitops.h>
#include <linux/compiler.h>
#ifndef __ASSEMBLY__
@@ -79,52 +80,52 @@
#endif /* __ASSEMBLY__ */
-#define PIR_INIT (1 << 0) /* Initialization Trigger */
-#define PIR_ZCAL (1 << 1) /* Impedance Calibration */
-#define PIR_PLLINIT (1 << 4) /* PLL Initialization */
-#define PIR_DCAL (1 << 5) /* DDL Calibration */
-#define PIR_PHYRST (1 << 6) /* PHY Reset */
-#define PIR_DRAMRST (1 << 7) /* DRAM Reset */
-#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */
-#define PIR_WL (1 << 9) /* Write Leveling */
-#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */
-#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */
-#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */
-#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */
-#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */
-#define PIR_WREYE (1 << 15) /* Write Data Eye Training */
-#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */
-#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */
-#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */
-#define PIR_INITBYP (1 << 31) /* Initialization Bypass */
+#define PIR_INIT BIT(0) /* Initialization Trigger */
+#define PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define PIR_DCAL BIT(5) /* DDL Calibration */
+#define PIR_PHYRST BIT(6) /* PHY Reset */
+#define PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define PIR_WL BIT(9) /* Write Leveling */
+#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
+#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
+#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define PIR_INITBYP BIT(31) /* Initialization Bypass */
-#define PGSR0_IDONE (1 << 0) /* Initialization Done */
-#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */
-#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */
-#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */
-#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */
-#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */
-#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */
-#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */
-#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */
-#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */
-#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */
-#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */
-#define PGSR0_IERR (1 << 16) /* Initialization Error */
-#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */
-#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */
-#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */
-#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */
-#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */
-#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */
-#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */
-#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */
-#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */
-#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */
-#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */
+#define PGSR0_IDONE BIT(0) /* Initialization Done */
+#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define PGSR0_IERR BIT(16) /* Initialization Error */
+#define PGSR0_PLERR BIT(17) /* PLL Lock Error */
+#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */
+#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */
+#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
+#define PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */
#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
-#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */
+#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */
#define DXCCR_DQSRES_OPEN (0 << 5)
#define DXCCR_DQSRES_688_OHM (1 << 5)
@@ -146,9 +147,9 @@
#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
-#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */
-#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */
-#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT))
+#define DTCR_DTMPR BIT(6) /* Data Training using MPR */
+#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c b/arch/arm/mach-uniphier/dram/ddrphy-training.c
similarity index 91%
rename from arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
rename to arch/arm/mach-uniphier/dram/ddrphy-training.c
index a98b814..a348136 100644
--- a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-training.c
@@ -5,8 +5,10 @@
*/
#include <common.h>
+#include <linux/err.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
{
@@ -32,8 +34,8 @@
/* Use Multi-Purpose Register for DQS gate training */
tmp |= DTCR_DTMPR;
/* Specify the rank enabled for data-training */
- tmp &= ~DTCR_RNKEN_MASK;
- tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
+ tmp &= ~DTCR_RANKEN_MASK;
+ tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
writel(tmp, p);
}
@@ -44,7 +46,7 @@
u32 err_flag;
};
-static struct ddrphy_init_sequence init_sequence[] = {
+static const struct ddrphy_init_sequence init_sequence[] = {
{
"DRAM Initialization",
PIR_DRAMRST | PIR_DRAMINIT,
@@ -117,7 +119,7 @@
if (--timeout < 0) {
printf("%s: error: timeout during DDR training\n",
__func__);
- return -1;
+ return -ETIMEDOUT;
}
udelay(1);
pgsr0 = readl(&phy->pgsr[0]);
@@ -127,7 +129,7 @@
if (pgsr0 & init_sequence[i].err_flag) {
printf("%s: error: %s failed\n", __func__,
init_sequence[i].description);
- return -1;
+ return -EIO;
}
}
diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
similarity index 98%
rename from arch/arm/mach-uniphier/umc/umc-ph1-ld4.c
rename to arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
index 8124685..ffd7aa9 100644
--- a/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
@@ -8,9 +8,10 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
similarity index 98%
rename from arch/arm/mach-uniphier/umc/umc-ph1-pro4.c
rename to arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
index 8c9f057..4d976e3 100644
--- a/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
@@ -8,9 +8,10 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
similarity index 98%
rename from arch/arm/mach-uniphier/umc/umc-ph1-sld8.c
rename to arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
index bc60a34..09f9ccf 100644
--- a/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
@@ -8,9 +8,10 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
new file mode 100644
index 0000000..63a84e6
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
@@ -0,0 +1,669 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
+ * Copyright (C) 2015 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "../soc-info.h"
+#include "ddrmphy-regs.h"
+
+/* UM registers */
+#define UMC_MBUS0 0x00080004
+#define UMC_MBUS1 0x00081004
+#define UMC_MBUS2 0x00082004
+#define UMC_MBUS3 0x00083004
+
+/* UD registers */
+#define UMC_BITPERPIXELMODE_D0 0x010
+#define UMC_PAIR1DOFF_D0 0x054
+
+/* DC registers */
+#define UMC_INITSET 0x014
+#define UMC_INITSTAT 0x018
+#define UMC_CMDCTLA 0x000
+#define UMC_CMDCTLB 0x004
+#define UMC_SPCCTLA 0x030
+#define UMC_SPCCTLB 0x034
+#define UMC_SPCSETB 0x03c
+#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
+#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
+#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
+#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
+#define UMC_ACSSETA 0x060
+#define UMC_FLOWCTLA 0x400
+#define UMC_FLOWCTLB 0x404
+#define UMC_FLOWCTLC 0x408
+#define UMC_FLOWCTLG 0x508
+#define UMC_FLOWCTLOB0 0x520
+#define UMC_FLOWCTLOB1 0x524
+#define UMC_RDATACTL_D0 0x600
+#define UMC_RDATACTL_RADLTY_SHIFT 4
+#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
+#define UMC_RDATACTL_RAD2LTY_SHIFT 8
+#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
+#define UMC_WDATACTL_D0 0x604
+#define UMC_RDATACTL_D1 0x608
+#define UMC_WDATACTL_D1 0x60c
+#define UMC_DATASET 0x610
+#define UMC_RESPCTL 0x624
+#define UMC_DCCGCTL 0x720
+#define UMC_ERRMASKA 0x958
+#define UMC_ERRMASKB 0x95c
+#define UMC_BSICMAPSET 0x988
+#define UMC_DIOCTLA 0xc00
+#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
+#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
+#define UMC_DFICUPDCTLA 0xc20
+
+enum dram_freq {
+ FREQ_1866M,
+ FREQ_2133M,
+ FREQ_NR,
+};
+
+enum dram_size {
+ SIZE_0,
+ SIZE_512M,
+ SIZE_1G,
+ SIZE_NR,
+};
+
+static u32 ddrphy_pgcr2[FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
+static u32 ddrphy_ptr0[FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
+static u32 ddrphy_ptr1[FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
+static u32 ddrphy_ptr3[FREQ_NR] = {0x15171e45, 0x18182357};
+static u32 ddrphy_ptr4[FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
+static u32 ddrphy_dtpr0[FREQ_NR] = {0x35a00d88, 0x39e40e88};
+static u32 ddrphy_dtpr1[FREQ_NR] = {0x2288cc2c, 0x228a04d0};
+static u32 ddrphy_dtpr2[FREQ_NR] = {0x50005e00, 0x50006a00};
+static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89};
+static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125};
+static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8};
+
+static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722};
+/*
+ * The ch2 is a different generation UMC core.
+ * The register spec is different, unfortunately.
+ */
+static u32 umc_cmdctlb_ch01[FREQ_NR] = {0x13E87C44, 0x18F88C44};
+static u32 umc_cmdctlb_ch2[FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
+static u32 umc_spcctla[FREQ_NR][SIZE_NR] = {
+ {0x00000000, 0x004A071D, 0x0078071D},
+ {0x00000000, 0x0055081E, 0x0089081E},
+};
+
+static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
+/* The ch2 is different for some reason only hardware guys know... */
+static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
+static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
+
+/* DDR multiPHY */
+static inline int ddrphy_get_rank(int dx)
+{
+ return dx / 2;
+}
+
+static void ddrphy_fifo_reset(void __iomem *phy_base)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + DMPHY_PGCR0);
+ tmp &= ~DMPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + DMPHY_PGCR0);
+
+ udelay(1);
+
+ tmp |= DMPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + DMPHY_PGCR0);
+
+ udelay(1);
+}
+
+static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + DMPHY_PGCR1);
+
+ if (enable)
+ tmp &= ~DMPHY_PGCR1_INHVT;
+ else
+ tmp |= DMPHY_PGCR1_INHVT;
+
+ writel(tmp, phy_base + DMPHY_PGCR1);
+
+ if (!enable) {
+ while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP))
+ cpu_relax();
+ }
+}
+
+static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
+{
+ int dx;
+ u32 lcdlr1, rdqsd;
+ void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1);
+ rdqsd = (lcdlr1 >> 8) & 0xff;
+ rdqsd = clamp(rdqsd + step, 0U, 0xffU);
+ lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
+ writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1);
+ readl(dx_base + DMPHY_DX_LCDLR1); /* relax */
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
+{
+ void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+ const int nr_dx = width / 8;
+ int dx, rank;
+ u32 gtr;
+ int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ gtr = readl(dx_base + DMPHY_DX_GTR);
+ for (rank = 0; rank < 4; rank++) {
+ dgsl = gtr & 0x7;
+ /* if dgsl is zero, this rank was not trained. skip. */
+ if (dgsl) {
+ dgsl_min = min(dgsl_min, dgsl);
+ dgsl_max = max(dgsl_max, dgsl);
+ }
+ gtr >>= 3;
+ }
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ if (dgsl_min != dgsl_max)
+ printf("DQS Gateing System Latencies are not all leveled.\n");
+
+ return dgsl_max;
+}
+
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width)
+{
+ u32 tmp;
+ void __iomem *zq_base, *dx_base;
+ int zq, dx;
+ int nr_dx;
+
+ nr_dx = width / 8;
+
+ writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR);
+ /*
+ * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
+ * to avoid read error issue.
+ */
+ writel(0x07d81e37, phy_base + DMPHY_PGCR0);
+ writel(0x0200c4e0, phy_base + DMPHY_PGCR1);
+
+ tmp = ddrphy_pgcr2[freq];
+ if (width >= 32)
+ tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC;
+ writel(tmp, phy_base + DMPHY_PGCR2);
+
+ writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0);
+ writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1);
+ writel(0x00083def, phy_base + DMPHY_PTR2);
+ writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3);
+ writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4);
+
+ writel(0x55555555, phy_base + DMPHY_ACIOCR1);
+ writel(0x00000000, phy_base + DMPHY_ACIOCR2);
+ writel(0x55555555, phy_base + DMPHY_ACIOCR3);
+ writel(0x00000000, phy_base + DMPHY_ACIOCR4);
+ writel(0x00000055, phy_base + DMPHY_ACIOCR5);
+ writel(0x00181aa4, phy_base + DMPHY_DXCCR);
+
+ writel(0x0024641e, phy_base + DMPHY_DSGCR);
+ writel(0x0000040b, phy_base + DMPHY_DCR);
+ writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0);
+ writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1);
+ writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2);
+ writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3);
+ writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0);
+ writel(0x00000006, phy_base + DMPHY_MR1);
+ writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2);
+ writel(0x00000000, phy_base + DMPHY_MR3);
+
+ tmp = 0;
+ for (dx = 0; dx < nr_dx; dx++)
+ tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
+ writel(0x90003087 | tmp, phy_base + DMPHY_DTCR);
+
+ writel(0x00000000, phy_base + DMPHY_DTAR0);
+ writel(0x00000008, phy_base + DMPHY_DTAR1);
+ writel(0x00000010, phy_base + DMPHY_DTAR2);
+ writel(0x00000018, phy_base + DMPHY_DTAR3);
+ writel(0xdd22ee11, phy_base + DMPHY_DTDR0);
+ writel(0x7788bb44, phy_base + DMPHY_DTDR1);
+
+ /* impedance control settings */
+ writel(0x04048900, phy_base + DMPHY_ZQCR);
+
+ zq_base = phy_base + DMPHY_ZQ_BASE;
+ for (zq = 0; zq < 4; zq++) {
+ /*
+ * board-dependent
+ * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
+ */
+ writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR);
+ zq_base += DMPHY_ZQ_STRIDE;
+ }
+
+ /* DATX8 settings */
+ dx_base = phy_base + DMPHY_DX_BASE;
+ for (dx = 0; dx < 4; dx++) {
+ tmp = readl(dx_base + DMPHY_DX_GCR0);
+ tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK;
+ tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
+ DMPHY_DX_GCR0_WLRKEN_MASK;
+ writel(tmp, dx_base + DMPHY_DX_GCR0);
+
+ writel(0x00000000, dx_base + DMPHY_DX_GCR1);
+ writel(0x00000000, dx_base + DMPHY_DX_GCR2);
+ writel(0x00000000, dx_base + DMPHY_DX_GCR3);
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE))
+ cpu_relax();
+
+ ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
+ {
+ "Impedance Calibration",
+ DMPHY_PIR_ZCAL,
+ DMPHY_PGSR0_ZCDONE,
+ DMPHY_PGSR0_ZCERR,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence dram_init_sequence[] = {
+ {
+ "DRAM Initialization",
+ DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT,
+ DMPHY_PGSR0_DIDONE,
+ 0,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence training_sequence[] = {
+ {
+ "Write Leveling",
+ DMPHY_PIR_WL,
+ DMPHY_PGSR0_WLDONE,
+ DMPHY_PGSR0_WLERR,
+ },
+ {
+ "Read DQS Gate Training",
+ DMPHY_PIR_QSGATE,
+ DMPHY_PGSR0_QSGDONE,
+ DMPHY_PGSR0_QSGERR,
+ },
+ {
+ "Write Leveling Adjustment",
+ DMPHY_PIR_WLADJ,
+ DMPHY_PGSR0_WLADONE,
+ DMPHY_PGSR0_WLAERR,
+ },
+ {
+ "Read Bit Deskew",
+ DMPHY_PIR_RDDSKW,
+ DMPHY_PGSR0_RDDONE,
+ DMPHY_PGSR0_RDERR,
+ },
+ {
+ "Write Bit Deskew",
+ DMPHY_PIR_WRDSKW,
+ DMPHY_PGSR0_WDDONE,
+ DMPHY_PGSR0_WDERR,
+ },
+ {
+ "Read Eye Training",
+ DMPHY_PIR_RDEYE,
+ DMPHY_PGSR0_REDONE,
+ DMPHY_PGSR0_REERR,
+ },
+ {
+ "Write Eye Training",
+ DMPHY_PIR_WREYE,
+ DMPHY_PGSR0_WEDONE,
+ DMPHY_PGSR0_WEERR,
+ },
+ { /* sentinel */ }
+};
+
+static int __ddrphy_training(void __iomem *phy_base,
+ const struct ddrphy_init_sequence *seq)
+{
+ const struct ddrphy_init_sequence *s;
+ u32 pgsr0;
+ u32 init_flag = DMPHY_PIR_INIT;
+ u32 done_flag = DMPHY_PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+#ifdef DISPLAY_ELAPSED_TIME
+ ulong start = get_timer(0);
+#endif
+
+ for (s = seq; s->description; s++) {
+ init_flag |= s->init_flag;
+ done_flag |= s->done_flag;
+ }
+
+ writel(init_flag, phy_base + DMPHY_PIR);
+
+ do {
+ if (--timeout < 0) {
+ printf("%s: error: timeout during DDR training\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ udelay(1);
+ pgsr0 = readl(phy_base + DMPHY_PGSR0);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (s = seq; s->description; s++) {
+ if (pgsr0 & s->err_flag) {
+ printf("%s: error: %s failed\n", __func__,
+ s->description);
+ return -EIO;
+ }
+ }
+
+#ifdef DISPLAY_ELAPSED_TIME
+ printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+ return 0;
+}
+
+static int ddrphy_impedance_calibration(void __iomem *phy_base)
+{
+ int ret;
+ u32 tmp;
+
+ ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
+ if (ret)
+ return ret;
+
+ /*
+ * Because of a hardware bug, IDONE flag is set when the first ZQ block
+ * is calibrated. The flag does not guarantee the completion for all
+ * the ZQ blocks. Wait a little more just in case.
+ */
+ udelay(1);
+
+ /* reflect ZQ settings and enable average algorithm*/
+ tmp = readl(phy_base + DMPHY_ZQCR);
+ tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ writel(tmp, phy_base + DMPHY_ZQCR);
+ tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ tmp |= DMPHY_ZQCR_AVGEN;
+ writel(tmp, phy_base + DMPHY_ZQCR);
+
+ return 0;
+}
+
+static int ddrphy_dram_init(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, dram_init_sequence);
+}
+
+static int ddrphy_training(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, training_sequence);
+}
+
+/* UMC */
+static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency)
+{
+ u32 val;
+ int latency;
+
+ val = readl(umc_dc_base + UMC_RDATACTL_D0);
+ latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
+ latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
+ UMC_RDATACTL_RAD2LTY_SHIFT;
+ /*
+ * UMC works at the half clock rate of the PHY.
+ * The LSB of latency is ignored
+ */
+ latency += phy_latency & ~1;
+
+ val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, umc_dc_base + UMC_RDATACTL_D0);
+ writel(val, umc_dc_base + UMC_RDATACTL_D1);
+
+ readl(umc_dc_base + UMC_RDATACTL_D1); /* relax */
+}
+
+/* enable/disable auto refresh */
+void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(umc_dc_base + UMC_SPCSETB);
+ tmp &= ~UMC_SPCSETB_AREFMD_MASK;
+
+ if (enable)
+ tmp |= UMC_SPCSETB_AREFMD_ARB;
+ else
+ tmp |= UMC_SPCSETB_AREFMD_REG;
+
+ writel(tmp, umc_dc_base + UMC_SPCSETB);
+ udelay(1);
+}
+
+static void umc_ud_init(void __iomem *umc_base, int ch)
+{
+ writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
+
+ if (ch == 2)
+ writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
+}
+
+static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq,
+ enum dram_size size, int ch, int width)
+{
+ int latency;
+ u32 val;
+
+ writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA);
+
+ writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
+ umc_dc_base + UMC_CMDCTLB);
+
+ writel(umc_spcctla[freq][size / (width / 16)],
+ umc_dc_base + UMC_SPCCTLA);
+ writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB);
+
+ val = 0x000e000e;
+ latency = 12;
+ /* ES2 inserted one more FF to the logic. */
+ if (uniphier_get_soc_model() >= 2)
+ latency += 2;
+
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, umc_dc_base + UMC_RDATACTL_D0);
+ if (width >= 32)
+ writel(val, umc_dc_base + UMC_RDATACTL_D1);
+
+ writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D0);
+ if (width >= 32)
+ writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D1);
+ writel(0x04000000, umc_dc_base + UMC_DATASET);
+ writel(0x00400020, umc_dc_base + UMC_DCCGCTL);
+ writel(0x00000084, umc_dc_base + UMC_FLOWCTLG);
+ writel(0x00000000, umc_dc_base + UMC_ACSSETA);
+
+ writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
+ umc_dc_base + UMC_FLOWCTLA);
+
+ writel(0x00004400, umc_dc_base + UMC_FLOWCTLC);
+ writel(0x200A0A00, umc_dc_base + UMC_SPCSETB);
+ writel(0x00000520, umc_dc_base + UMC_DFICUPDCTLA);
+ writel(0x0000000D, umc_dc_base + UMC_RESPCTL);
+
+ if (ch != 2) {
+ writel(0x00202000, umc_dc_base + UMC_FLOWCTLB);
+ writel(0xFDBFFFFF, umc_dc_base + UMC_FLOWCTLOB0);
+ writel(0xFFFFFFFF, umc_dc_base + UMC_FLOWCTLOB1);
+ writel(0x00080700, umc_dc_base + UMC_BSICMAPSET);
+ } else {
+ writel(0x00200000, umc_dc_base + UMC_FLOWCTLB);
+ writel(0x00000000, umc_dc_base + UMC_BSICMAPSET);
+ }
+
+ writel(0x00000000, umc_dc_base + UMC_ERRMASKA);
+ writel(0x00000000, umc_dc_base + UMC_ERRMASKB);
+}
+
+static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch,
+ enum dram_size size, int width)
+{
+ void __iomem *umc_dc_base = umc_base + 0x00011000;
+ void __iomem *phy_base = umc_base + 0x00030000;
+ int ret;
+
+ writel(0x00000002, umc_dc_base + UMC_INITSET);
+ while (readl(umc_dc_base + UMC_INITSTAT) & BIT(2))
+ cpu_relax();
+
+ /* deassert PHY reset signals */
+ writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
+ umc_dc_base + UMC_DIOCTLA);
+
+ ddrphy_init(phy_base, freq, width);
+
+ ret = ddrphy_impedance_calibration(phy_base);
+ if (ret)
+ return ret;
+
+ ddrphy_dram_init(phy_base);
+ if (ret)
+ return ret;
+
+ umc_dc_init(umc_dc_base, freq, size, ch, width);
+
+ umc_ud_init(umc_base, ch);
+
+ if (size) {
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+ }
+
+ udelay(1);
+
+ /* match the system latency between UMC and PHY */
+ umc_set_system_latency(umc_dc_base,
+ ddrphy_get_system_latency(phy_base, width));
+
+ udelay(1);
+
+ /* stop auto refresh before clearing FIFO in PHY */
+ umc_refresh_ctrl(umc_dc_base, 0);
+ ddrphy_fifo_reset(phy_base);
+ umc_refresh_ctrl(umc_dc_base, 1);
+
+ udelay(10);
+
+ return 0;
+}
+
+static void um_init(void __iomem *um_base)
+{
+ writel(0x000000ff, um_base + UMC_MBUS0);
+ writel(0x000000ff, um_base + UMC_MBUS1);
+ writel(0x000000ff, um_base + UMC_MBUS2);
+ writel(0x000000ff, um_base + UMC_MBUS3);
+}
+
+int proxstream2_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *um_base = (void __iomem *)0x5b600000;
+ void __iomem *umc_ch0_base = (void __iomem *)0x5b800000;
+ void __iomem *umc_ch1_base = (void __iomem *)0x5ba00000;
+ void __iomem *umc_ch2_base = (void __iomem *)0x5bc00000;
+ enum dram_freq freq;
+ int ret;
+
+ switch (bd->dram_freq) {
+ case 1866:
+ freq = FREQ_1866M;
+ break;
+ case 2133:
+ freq = FREQ_2133M;
+ break;
+ default:
+ printf("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+ return -EINVAL;
+ }
+
+ ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M,
+ bd->dram_ch0_width);
+ if (ret) {
+ printf("failed to initialize UMC ch0\n");
+ return ret;
+ }
+
+ ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M,
+ bd->dram_ch1_width);
+ if (ret) {
+ printf("failed to initialize UMC ch1\n");
+ return ret;
+ }
+
+ ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M,
+ bd->dram_ch2_width);
+ if (ret) {
+ printf("failed to initialize UMC ch2\n");
+ return ret;
+ }
+
+ um_init(um_base);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/include/mach/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h
similarity index 100%
rename from arch/arm/mach-uniphier/include/mach/umc-regs.h
rename to arch/arm/mach-uniphier/dram/umc-regs.h
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c
index f646c9b..6574767 100644
--- a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c
@@ -7,8 +7,9 @@
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c
index 007d3b8..d986358 100644
--- a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c
index c303f16..a573a96 100644
--- a/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c
@@ -7,8 +7,9 @@
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int proxstream2_early_clk_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c
index 1bb9375..7923644 100644
--- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+#include "../init.h"
+#include "../sg-regs.h"
int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/init.h
similarity index 95%
rename from arch/arm/mach-uniphier/include/mach/init.h
rename to arch/arm/mach-uniphier/init.h
index 5108edd..0a47e70 100644
--- a/arch/arm/mach-uniphier/include/mach/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -20,7 +20,7 @@
unsigned int dram_freq;
};
-const struct uniphier_board_data *uniphier_get_board_param(const void *fdt);
+const struct uniphier_board_data *uniphier_get_board_param(void);
int ph1_sld3_init(const struct uniphier_board_data *bd);
int ph1_ld4_init(const struct uniphier_board_data *bd);
@@ -80,6 +80,7 @@
int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
+int proxstream2_umc_init(const struct uniphier_board_data *bd);
void ph1_sld3_pin_init(void);
void ph1_ld4_pin_init(void);
diff --git a/arch/arm/mach-uniphier/init/init-ph1-ld4.c b/arch/arm/mach-uniphier/init/init-ph1-ld4.c
index 8d0ef03..a9c6d72 100644
--- a/arch/arm/mach-uniphier/init/init-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/init/init-ph1-ld4.c
@@ -6,9 +6,9 @@
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_ld4_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro4.c b/arch/arm/mach-uniphier/init/init-ph1-pro4.c
index b9ce08d..6fcd8b6 100644
--- a/arch/arm/mach-uniphier/init/init-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/init/init-ph1-pro4.c
@@ -6,9 +6,9 @@
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_pro4_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro5.c b/arch/arm/mach-uniphier/init/init-ph1-pro5.c
index 92b3f21..45c65cf 100644
--- a/arch/arm/mach-uniphier/init/init-ph1-pro5.c
+++ b/arch/arm/mach-uniphier/init/init-ph1-pro5.c
@@ -6,9 +6,9 @@
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_pro5_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld3.c b/arch/arm/mach-uniphier/init/init-ph1-sld3.c
index 1146fda..7827ec0 100644
--- a/arch/arm/mach-uniphier/init/init-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/init/init-ph1-sld3.c
@@ -6,9 +6,9 @@
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_sld3_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld8.c b/arch/arm/mach-uniphier/init/init-ph1-sld8.c
index 741e88c..6c96aed 100644
--- a/arch/arm/mach-uniphier/init/init-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/init/init-ph1-sld8.c
@@ -6,9 +6,9 @@
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_sld8_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/init/init-proxstream2.c b/arch/arm/mach-uniphier/init/init-proxstream2.c
index 8d03b8f..029c544 100644
--- a/arch/arm/mach-uniphier/init/init-proxstream2.c
+++ b/arch/arm/mach-uniphier/init/init-proxstream2.c
@@ -6,12 +6,14 @@
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int proxstream2_init(const struct uniphier_board_data *bd)
{
+ int ret;
+
proxstream2_sbc_init(bd);
support_card_reset();
@@ -37,5 +39,11 @@
led_puts("L4");
+ ret = proxstream2_umc_init(bd);
+ if (ret)
+ return ret;
+
+ led_puts("L5");
+
return 0;
}
diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c
index bbfc8e5..b30f3bd 100644
--- a/arch/arm/mach-uniphier/init/init.c
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -6,16 +6,15 @@
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/soc_info.h>
-DECLARE_GLOBAL_DATA_PTR;
+#include "../init.h"
+#include "../soc-info.h"
void spl_board_init(void)
{
const struct uniphier_board_data *param;
- param = uniphier_get_board_param(gd->fdt_blob);
+ param = uniphier_get_board_param();
if (!param)
hang();
diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S
index 1363364..cce91df 100644
--- a/arch/arm/mach-uniphier/late_lowlevel_init.S
+++ b/arch/arm/mach-uniphier/late_lowlevel_init.S
@@ -6,7 +6,8 @@
*/
#include <linux/linkage.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
ENTRY(lowlevel_init)
ldr r1, = SSCC
diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index 5936045..2913370 100644
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -8,9 +8,8 @@
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
-#include <mach/arm-mpcore.h>
-#include <mach/sbc-regs.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call
diff --git a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
index e13f56d1..9718cc5 100644
--- a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
@@ -8,8 +8,9 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
index d7bf0d4..9a91fb3 100644
--- a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
+++ b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
@@ -8,8 +8,9 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int proxstream2_memconf_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c
index d490736..f2a0eaf 100644
--- a/arch/arm/mach-uniphier/memconf/memconf.c
+++ b/arch/arm/mach-uniphier/memconf/memconf.c
@@ -8,8 +8,9 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int memconf_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c
index 4c34748..f777ac1 100644
--- a/arch/arm/mach-uniphier/micro-support-card.c
+++ b/arch/arm/mach-uniphier/micro-support-card.c
@@ -7,7 +7,8 @@
#include <common.h>
#include <linux/ctype.h>
#include <linux/io.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
#define MICRO_SUPPORT_CARD_BASE 0x43f00000
#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
@@ -70,7 +71,6 @@
#if !defined(CONFIG_SYS_NO_FLASH)
#include <mtd/cfi_flash.h>
-#include <mach/sbc-regs.h>
struct memory_bank {
phys_addr_t base;
diff --git a/arch/arm/mach-uniphier/include/mach/micro-support-card.h b/arch/arm/mach-uniphier/micro-support-card.h
similarity index 100%
rename from arch/arm/mach-uniphier/include/mach/micro-support-card.h
rename to arch/arm/mach-uniphier/micro-support-card.h
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
index 160d3ef..8168a63 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_ld4_pin_init(void)
{
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c
index 4f950d3..4faeaf5 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_ld6b_pin_init(void)
{
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
index f50644c..23b5f93 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_pro4_pin_init(void)
{
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c
index a6cc082..79160d6 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_pro5_pin_init(void)
{
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
index f1b2bbb..6fc0dee 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_sld3_pin_init(void)
{
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
index f936a53..a4e3e7a 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_sld8_pin_init(void)
{
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c
index 96abd02..a662db8 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void proxstream2_pin_init(void)
{
diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c
index a272a90..b2de9e8 100644
--- a/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c
@@ -7,9 +7,10 @@
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c
index 906c22f..69d518d 100644
--- a/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c
@@ -7,9 +7,10 @@
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c
index 6294a45..b93806c 100644
--- a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
+#include "../init.h"
int ph1_sld3_pll_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c
index f249abe..3c75504 100644
--- a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c
@@ -6,9 +6,10 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
static void dpll_init(void)
{
diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c
index cad0ed8..a1c8089 100644
--- a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c
@@ -5,8 +5,9 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c
index 43dc973..94654ee 100644
--- a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c
@@ -6,8 +6,9 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/print_misc_info.c b/arch/arm/mach-uniphier/print_misc_info.c
index 5140b0c..695b7ae 100644
--- a/arch/arm/mach-uniphier/print_misc_info.c
+++ b/arch/arm/mach-uniphier/print_misc_info.c
@@ -1,11 +1,10 @@
/*
- * Copyright (C) 2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/micro-support-card.h>
+#include "micro-support-card.h"
int misc_init_f(void)
{
diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c
index 4c82511..b5825bc 100644
--- a/arch/arm/mach-uniphier/reset.c
+++ b/arch/arm/mach-uniphier/reset.c
@@ -6,7 +6,8 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/sc-regs.h>
+
+#include "sc-regs.h"
void reset_cpu(unsigned long ignored)
{
diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c
index 929f50a..fcce43c 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c
@@ -6,9 +6,10 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c
index 1032c54..8313c5a 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c
@@ -6,9 +6,10 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c
index fb707be..c03c284 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c
@@ -6,9 +6,10 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c
index 9c3aeb7..0d9ffe1 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c
@@ -5,9 +5,10 @@
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int proxstream2_sbc_init(const struct uniphier_board_data *bd)
{
diff --git a/arch/arm/mach-uniphier/include/mach/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h
similarity index 100%
rename from arch/arm/mach-uniphier/include/mach/sbc-regs.h
rename to arch/arm/mach-uniphier/sbc/sbc-regs.h
diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h
similarity index 100%
rename from arch/arm/mach-uniphier/include/mach/sc-regs.h
rename to arch/arm/mach-uniphier/sc-regs.h
diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
similarity index 100%
rename from arch/arm/mach-uniphier/include/mach/sg-regs.h
rename to arch/arm/mach-uniphier/sg-regs.h
diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h b/arch/arm/mach-uniphier/soc-info.h
similarity index 78%
rename from arch/arm/mach-uniphier/include/mach/soc_info.h
rename to arch/arm/mach-uniphier/soc-info.h
index 623e7ef..3cfd1e9 100644
--- a/arch/arm/mach-uniphier/include/mach/soc_info.h
+++ b/arch/arm/mach-uniphier/soc-info.h
@@ -15,6 +15,8 @@
SOC_UNIPHIER_PH1_PRO5,
SOC_UNIPHIER_PROXSTREAM2,
SOC_UNIPHIER_PH1_LD6B,
+ SOC_UNIPHIER_PH1_SLD11,
+ SOC_UNIPHIER_PH1_LD10,
SOC_UNIPHIER_UNKNOWN,
};
@@ -25,7 +27,9 @@
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD10)
#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
@@ -55,9 +59,18 @@
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
return SOC_UNIPHIER_PH1_LD6B;
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD11)
+ return SOC_UNIPHIER_PH1_SLD11;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD10)
+ return SOC_UNIPHIER_PH1_LD10;
+#endif
return SOC_UNIPHIER_UNKNOWN;
}
#endif
+int uniphier_get_soc_model(void);
+int uniphier_get_soc_revision(void);
+
#endif /* __MACH_SOC_INFO_H__ */
diff --git a/arch/arm/mach-uniphier/soc_info.c b/arch/arm/mach-uniphier/soc_info.c
index 3e8e7f4..fd799ca 100644
--- a/arch/arm/mach-uniphier/soc_info.c
+++ b/arch/arm/mach-uniphier/soc_info.c
@@ -6,8 +6,9 @@
#include <linux/io.h>
#include <linux/types.h>
-#include <mach/sg-regs.h>
-#include <mach/soc_info.h>
+
+#include "sg-regs.h"
+#include "soc-info.h"
#if UNIPHIER_MULTI_SOC
enum uniphier_soc_id uniphier_get_soc_type(void)
@@ -51,6 +52,16 @@
ret = SOC_UNIPHIER_PH1_LD6B;
break;
#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD11
+ case 0x31:
+ ret = SOC_UNIPHIER_PH1_SLD11;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD10
+ case 0x32:
+ ret = SOC_UNIPHIER_PH1_LD10;
+ break;
+#endif
default:
ret = SOC_UNIPHIER_UNKNOWN;
break;
@@ -59,3 +70,15 @@
return ret;
}
#endif
+
+int uniphier_get_soc_model(void)
+{
+ return (readl(SG_REVISION) & SG_REVISION_MODEL_MASK) >>
+ SG_REVISION_MODEL_SHIFT;
+}
+
+int uniphier_get_soc_revision(void)
+{
+ return (readl(SG_REVISION) & SG_REVISION_REV_MASK) >>
+ SG_REVISION_REV_SHIFT;
+}
diff --git a/arch/arm/mach-uniphier/include/mach/ssc-regs.h b/arch/arm/mach-uniphier/ssc-regs.h
similarity index 100%
rename from arch/arm/mach-uniphier/include/mach/ssc-regs.h
rename to arch/arm/mach-uniphier/ssc-regs.h
diff --git a/arch/arm/mach-uniphier/timer.c b/arch/arm/mach-uniphier/timer.c
index 27ada29..a34e30b 100644
--- a/arch/arm/mach-uniphier/timer.c
+++ b/arch/arm/mach-uniphier/timer.c
@@ -6,7 +6,8 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/arm-mpcore.h>
+
+#include "arm-mpcore.h"
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
diff --git a/arch/arm/mach-uniphier/umc/Makefile b/arch/arm/mach-uniphier/umc/Makefile
deleted file mode 100644
index 89b2dec..0000000
--- a/arch/arm/mach-uniphier/umc/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index afe6cc3..d396a13 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -33,7 +33,6 @@
config TARGET_ZYNQ_ZYBO
bool "Zynq Zybo Board"
- select ZYNQ_CUSTOM_INIT
endchoice
diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile
deleted file mode 100644
index de243fea..0000000
--- a/arch/arm/mvebu-common/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = dram.o
-obj-y += gpio.o
-obj-$(CONFIG_ARMADA_XP) += mbus.o
-obj-y += timer.o
-
-obj-y += serdes/
diff --git a/arch/m68k/include/asm/fsl_i2c.h b/arch/m68k/include/asm/fsl_i2c.h
index 2bc9bf4..1b1c25e 100644
--- a/arch/m68k/include/asm/fsl_i2c.h
+++ b/arch/m68k/include/asm/fsl_i2c.h
@@ -8,23 +8,7 @@
* and Jeff Brown.
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_FSL_I2C_H_
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 077b2a7..604f681 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -11,6 +11,8 @@
config TARGET_MICROBLAZE_GENERIC
bool "Support microblaze-generic"
select SUPPORT_SPL
+ select OF_CONTROL
+ select DM
endchoice
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 14f46a8..206be3e 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -25,7 +25,7 @@
addi r8, r0, __end
mts rslr, r8
- /* TODO: Redo this code to call board_init_f_mem() */
+ /* TODO: Redo this code to call board_init_f_*() */
#if defined(CONFIG_SPL_BUILD)
addi r1, r0, CONFIG_SPL_STACK_ADDR
mts rshr, r1
@@ -142,7 +142,7 @@
ori r12, r12, 0x1a0
mts rmsr, r12
- /* TODO: Redo this code to call board_init_f_mem() */
+ /* TODO: Redo this code to call board_init_f_*() */
clear_bss:
/* clear BSS segments */
addi r5, r0, __bss_start
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7f7e258..1b39c4c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -28,6 +28,7 @@
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SWAP_IO_SPACE
+ select MIPS_L1_CACHE_SHIFT_6
config TARGET_VCT
bool "Support vct"
@@ -43,6 +44,7 @@
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select MIPS_TUNE_4KC
config TARGET_PB1X00
bool "Support pb1x00"
@@ -50,7 +52,7 @@
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
-
+ select MIPS_TUNE_4KC
endchoice
@@ -174,6 +176,15 @@
bool
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
+config MIPS_TUNE_4KC
+ bool
+
+config MIPS_TUNE_14KC
+ bool
+
+config MIPS_TUNE_24KC
+ bool
+
config 32BIT
bool
@@ -186,6 +197,26 @@
config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
+config MIPS_L1_CACHE_SHIFT_4
+ bool
+
+config MIPS_L1_CACHE_SHIFT_5
+ bool
+
+config MIPS_L1_CACHE_SHIFT_6
+ bool
+
+config MIPS_L1_CACHE_SHIFT_7
+ bool
+
+config MIPS_L1_CACHE_SHIFT
+ int
+ default "7" if MIPS_L1_CACHE_SHIFT_7
+ default "6" if MIPS_L1_CACHE_SHIFT_6
+ default "5" if MIPS_L1_CACHE_SHIFT_5
+ default "4" if MIPS_L1_CACHE_SHIFT_4
+ default "5"
+
endif
endmenu
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 43f0f5c..2133e7e 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -7,4 +7,25 @@
libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
-libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
+machine-$(CONFIG_SOC_AU1X00) += au1x00
+
+machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
+libs-y += $(machdirs)
+
+PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
+
+# Optimize for MIPS architectures
+arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
+arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
+arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
+arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+
+# Allow extra optimization for specific CPUs/SoCs
+tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
+tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
+tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
+
+# Include default header files
+cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
+
+PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) $(cflags-y)
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 52e28f2..609a998 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -35,12 +35,6 @@
OBJCOPYFLAGS += -O $(64bit-bfd)
endif
-cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
-cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
-cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
-cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
-PLATFORM_CPPFLAGS += $(cpuflags-y)
-
PLATFORM_CPPFLAGS += -D__MIPS__
#
@@ -63,10 +57,21 @@
# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
# to RAM. $28 is always used as gp.
#
-PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
+ifdef CONFIG_SPL_BUILD
+PF_ABICALLS := -mno-abicalls
+PF_PIC := -fno-pic
+PF_PIE :=
+else
+PF_ABICALLS := -mabicalls
+PF_PIC := -fpic
+PF_PIE := -pie
+PF_OBJCOPY := -j .got -j .u_boot_list -j .rel.dyn -j .padding
+PF_OBJCOPY += -j .dtb.init.rodata
+endif
+
+PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC)
PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-LDFLAGS_FINAL += --gc-sections -pie
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got
-OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding
+LDFLAGS_FINAL += --gc-sections $(PF_PIE)
+OBJCOPYFLAGS += -j .text -j .rodata -j .data $(PF_OBJCOPY)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 3b5b622..e95cdca 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -56,9 +56,7 @@
.set noreorder
- .globl _start
- .text
-_start:
+ENTRY(_start)
/* U-boot entry point */
b reset
nop
@@ -192,6 +190,8 @@
jr t9
move ra, zero
+ END(_start)
+
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@@ -202,9 +202,7 @@
* a1 = gd
* a2 = destination address
*/
- .globl relocate_code
- .ent relocate_code
-relocate_code:
+ENTRY(relocate_code)
move sp, a0 # set new stack pointer
move fp, sp
@@ -317,4 +315,4 @@
jr t9
move ra, zero
- .end relocate_code
+ END(relocate_code)
diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore
new file mode 100644
index 0000000..b60ed20
--- /dev/null
+++ b/arch/mips/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
new file mode 100644
index 0000000..47b6eb5
--- /dev/null
+++ b/arch/mips/dts/Makefile
@@ -0,0 +1,16 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+dtb-y +=
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
diff --git a/arch/mips/dts/include/dt-bindings b/arch/mips/dts/include/dt-bindings
new file mode 120000
index 0000000..0cecb3d
--- /dev/null
+++ b/arch/mips/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi
new file mode 100644
index 0000000..24ee6c3
--- /dev/null
+++ b/arch/mips/dts/skeleton.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value. The bootloader will typically populate the memory
+ * node.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ };
+
+ aliases {
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>;
+ };
+};
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index b768bb5..0994e96 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -1,15 +1,15 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1996, 99 Ralf Baechle
* Copyright (C) 2000, 2002 Maciej W. Rozycki
* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ADDRSPACE_H
#define _ASM_ADDRSPACE_H
+#include <spaces.h>
+
/*
* Configure language
*/
@@ -50,7 +50,7 @@
*/
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
- _CONST64_(0x000000ffffffffff))
+ _CONST64_(0x0000ffffffffffff))
#ifdef CONFIG_64BIT
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 933ccb1..44694a3 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -1,8 +1,4 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
@@ -13,6 +9,8 @@
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ASM_H
#define __ASM_ASM_H
@@ -33,50 +31,58 @@
* Not used for the kernel but here seems to be the right place.
*/
#ifdef __PIC__
-#define CPRESTORE(register) \
+#define CPRESTORE(register) \
.cprestore register
-#define CPADD(register) \
+#define CPADD(register) \
.cpadd register
-#define CPLOAD(register) \
- .cpload register
+#define CPLOAD(register) \
+ .cpload register
#else
#define CPRESTORE(register)
#define CPADD(register)
#define CPLOAD(register)
#endif
+#define ENTRY(symbol) \
+ .globl symbol; \
+ .type symbol, @function; \
+ .ent symbol, 0; \
+symbol:
+
/*
* LEAF - declare leaf routine
*/
-#define LEAF(symbol) \
- .globl symbol; \
- .align 2; \
- .type symbol, @function; \
- .ent symbol, 0; \
+#define LEAF(symbol) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol, @function; \
+ .ent symbol, 0; \
+ .section .text.symbol, "x"; \
symbol: .frame sp, 0, ra
/*
* NESTED - declare nested routine entry point
*/
-#define NESTED(symbol, framesize, rpc) \
- .globl symbol; \
- .align 2; \
- .type symbol, @function; \
- .ent symbol, 0; \
+#define NESTED(symbol, framesize, rpc) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol, @function; \
+ .ent symbol, 0; \
+ .section .text.symbol, "x"; \
symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
-#define END(function) \
- .end function; \
+#define END(function) \
+ .end function; \
.size function, .-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
- .globl symbol; \
+ .globl symbol; \
symbol:
/*
@@ -90,16 +96,16 @@
/*
* ABS - export absolute symbol
*/
-#define ABS(symbol,value) \
- .globl symbol; \
+#define ABS(symbol,value) \
+ .globl symbol; \
symbol = value
-#define PANIC(msg) \
+#define PANIC(msg) \
.set push; \
- .set reorder; \
- PTR_LA a0, 8f; \
- jal panic; \
-9: b 9b; \
+ .set reorder; \
+ PTR_LA a0, 8f; \
+ jal panic; \
+9: b 9b; \
.set pop; \
TEXT(msg)
@@ -107,31 +113,31 @@
* Print formatted string
*/
#ifdef CONFIG_PRINTK
-#define PRINT(string) \
+#define PRINT(string) \
.set push; \
- .set reorder; \
- PTR_LA a0, 8f; \
- jal printk; \
+ .set reorder; \
+ PTR_LA a0, 8f; \
+ jal printk; \
.set pop; \
TEXT(string)
#else
#define PRINT(string)
#endif
-#define TEXT(msg) \
+#define TEXT(msg) \
.pushsection .data; \
-8: .asciiz msg; \
+8: .asciiz msg; \
.popsection;
/*
* Build text tables
*/
-#define TTABLE(string) \
+#define TTABLE(string) \
.pushsection .text; \
- .word 1f; \
+ .word 1f; \
.popsection \
.pushsection .data; \
-1: .asciiz string; \
+1: .asciiz string; \
.popsection
/*
@@ -143,21 +149,29 @@
*/
#ifdef CONFIG_CPU_HAS_PREFETCH
-#define PREF(hint,addr) \
+#define PREF(hint, addr) \
.set push; \
- .set mips4; \
+ .set arch=r5000; \
pref hint, addr; \
.set pop
+#define PREFE(hint, addr) \
+ .set push; \
+ .set mips0; \
+ .set eva; \
+ prefe hint, addr; \
+ .set pop
+
-#define PREFX(hint,addr) \
+#define PREFX(hint, addr) \
.set push; \
- .set mips4; \
+ .set arch=r5000; \
prefx hint, addr; \
.set pop
#else /* !CONFIG_CPU_HAS_PREFETCH */
#define PREF(hint, addr)
+#define PREFE(hint, addr)
#define PREFX(hint, addr)
#endif /* !CONFIG_CPU_HAS_PREFETCH */
@@ -166,42 +180,42 @@
* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
-#define MOVN(rd, rs, rt) \
+#define MOVN(rd, rs, rt) \
.set push; \
.set reorder; \
- beqz rt, 9f; \
- move rd, rs; \
+ beqz rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
-#define MOVZ(rd, rs, rt) \
+#define MOVZ(rd, rs, rt) \
.set push; \
.set reorder; \
- bnez rt, 9f; \
- move rd, rs; \
+ bnez rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
-#define MOVN(rd, rs, rt) \
+#define MOVN(rd, rs, rt) \
.set push; \
.set noreorder; \
- bnezl rt, 9f; \
- move rd, rs; \
+ bnezl rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
-#define MOVZ(rd, rs, rt) \
+#define MOVZ(rd, rs, rt) \
.set push; \
.set noreorder; \
- beqzl rt, 9f; \
- move rd, rs; \
+ beqzl rt, 9f; \
+ move rd, rs; \
.set pop; \
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define MOVN(rd, rs, rt) \
+#define MOVN(rd, rs, rt) \
movn rd, rs, rt
-#define MOVZ(rd, rs, rt) \
+#define MOVZ(rd, rs, rt) \
movz rd, rs, rt
#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
@@ -296,6 +310,7 @@
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_S sw
+#define LONG_SP swp
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
@@ -318,6 +333,7 @@
#define LONG_SUBU dsubu
#define LONG_L ld
#define LONG_S sd
+#define LONG_SP sdp
#define LONG_SLL dsll
#define LONG_SLLV dsllv
#define LONG_SRL dsrl
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index c31ff6e..cce6995 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -1,10 +1,8 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org)
* Copyright (c) 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
index b5e685f..67fdf71 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -1,9 +1,7 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 0dfb54e..806bd26 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -7,15 +7,9 @@
#ifndef __MIPS_CACHE_H__
#define __MIPS_CACHE_H__
-/*
- * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use
- * that as a default for aligning DMA buffers unless the board config has
- * specified another cache line size.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN 128
-#endif
+#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
#endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h
index f3ce721..5e77dfa 100644
--- a/arch/mips/include/asm/cachectl.h
+++ b/arch/mips/include/asm/cachectl.h
@@ -1,9 +1,7 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_CACHECTL
#define _ASM_CACHECTL
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index af2adc7..a3b07c6 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -1,12 +1,10 @@
/*
* Cache operations for the cache instruction.
*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
* (C) Copyright 1999 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_CACHEOPS_H
#define __ASM_CACHEOPS_H
diff --git a/arch/mips/include/asm/const.h b/arch/mips/include/asm/const.h
new file mode 100644
index 0000000..f600e7a
--- /dev/null
+++ b/arch/mips/include/asm/const.h
@@ -0,0 +1,31 @@
+/*
+ * const.h: Macros for dealing with constants.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _LINUX_CONST_H
+#define _LINUX_CONST_H
+
+/* Some constant macros are used in both assembler and
+ * C code. Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally. We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y) X
+#define _AT(T,X) X
+#else
+#define __AC(X,Y) (X##Y)
+#define _AC(X,Y) __AC(X,Y)
+#define _AT(T,X) ((T)(X))
+#endif
+
+#define _BITUL(x) (_AC(1,UL) << (x))
+#define _BITULL(x) (_AC(1,ULL) << (x))
+
+#endif /* !(_LINUX_CONST_H) */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
new file mode 100644
index 0000000..a6e9d94
--- /dev/null
+++ b/arch/mips/include/asm/cpu-features.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <cpu-feature-overrides.h>
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits 0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 0
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits 1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 1
+# endif
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/gpio.h b/arch/mips/include/asm/gpio.h
new file mode 100644
index 0000000..306ab4c
--- /dev/null
+++ b/arch/mips/include/asm/gpio.h
@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index a7ab087..b8ac5a5 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -1,21 +1,28 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995 Waldorf GmbH
- * Copyright (C) 1994 - 2000 Ralf Baechle
+ * Copyright (C) 1994 - 2000, 06 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 FSMLabs, Inc.
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
+ * Author: Maciej W. Rozycki <macro@mips.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_IO_H
#define _ASM_IO_H
-#if 0
-#include <linux/pagemap.h>
-#endif
+#include <linux/compiler.h>
+#include <linux/types.h>
+
#include <asm/addrspace.h>
#include <asm/byteorder.h>
+#include <asm/cpu-features.h>
+#include <asm/pgtable-bits.h>
+#include <asm/processor.h>
+#include <asm/string.h>
+
+#include <ioremap.h>
+#include <mangle-port.h>
+#include <spaces.h>
/*
* Slowdown I/O port space accesses for antique hardware.
@@ -23,44 +30,20 @@
#undef CONF_SLOWDOWN_IO
/*
- * Sane hardware offers swapping of I/O space accesses in hardware; less
- * sane hardware forces software to fiddle with this ...
+ * Raw operations are never swapped in software. OTOH values that raw
+ * operations are working on may or may not have been swapped by the bus
+ * hardware. An example use would be for flash memory that's used for
+ * execute in place.
*/
-#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
+# define __raw_ioswabb(a, x) (x)
+# define __raw_ioswabw(a, x) (x)
+# define __raw_ioswabl(a, x) (x)
+# define __raw_ioswabq(a, x) (x)
+# define ____raw_ioswabq(a, x) (x)
-#define __ioswab8(x) (x)
-#define __ioswab16(x) swab16(x)
-#define __ioswab32(x) swab32(x)
-
-#else
+/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
-#define __ioswab8(x) (x)
-#define __ioswab16(x) (x)
-#define __ioswab32(x) (x)
-
-#endif
-
-/*
- * This file contains the definitions for the MIPS counterpart of the
- * x86 in/out instructions. This heap of macros and C results in much
- * better code than the approach of doing it in plain C. The macros
- * result in code that is to fast for certain hardware. On the other
- * side the performance of the string functions should be improved for
- * sake of certain devices like EIDE disks that do highspeed polled I/O.
- *
- * Ralf
- *
- * This file contains the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
- *
- * This file is not meant to be obfuscating: it's just complicated
- * to (a) handle it all in a way that makes gcc able to optimize it
- * as well as possible and (b) trying to avoid writing the same thing
- * over and over again with slight variations and possibly making a
- * mistake somewhere.
- */
+#define IO_SPACE_LIMIT 0xffff
/*
* On MIPS I/O ports are memory mapped, so we access them using normal
@@ -84,6 +67,7 @@
static inline void set_io_port_base(unsigned long base)
{
* (unsigned long *) &mips_io_port_base = base;
+ barrier();
}
/*
@@ -114,378 +98,429 @@
#endif
/*
- * Change virtual addresses to physical addresses and vv.
- * These are trivial on the 1:1 Linux/MIPS mapping
+ * virt_to_phys - map virtual addresses to physical
+ * @address: address to remap
+ *
+ * The returned physical address is the physical (CPU) mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses directly mapped or allocated via kmalloc.
+ *
+ * This function does not give bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
*/
-static inline phys_addr_t virt_to_phys(volatile void * address)
+static inline unsigned long virt_to_phys(volatile const void *address)
{
-#ifndef CONFIG_64BIT
- return CPHYSADDR(address);
-#else
- return XPHYSADDR(address);
-#endif
-}
+ unsigned long addr = (unsigned long)address;
-static inline void * phys_to_virt(unsigned long address)
-{
-#ifndef CONFIG_64BIT
- return (void *)KSEG0ADDR(address);
+ /* this corresponds to kernel implementation of __pa() */
+#ifdef CONFIG_64BIT
+ if (addr < CKSEG0)
+ return XPHYSADDR(addr);
+
+ return CPHYSADDR(addr);
#else
- return (void *)CKSEG0ADDR(address);
+ return addr - PAGE_OFFSET + PHYS_OFFSET;
#endif
}
/*
- * IO bus memory addresses are also 1:1 with the physical address
+ * phys_to_virt - map physical address to virtual
+ * @address: address to remap
+ *
+ * The returned virtual address is a current CPU mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses that have a kernel mapping
+ *
+ * This function does not handle bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
*/
-static inline unsigned long virt_to_bus(volatile void * address)
+static inline void *phys_to_virt(unsigned long address)
{
-#ifndef CONFIG_64BIT
- return CPHYSADDR(address);
-#else
- return XPHYSADDR(address);
-#endif
-}
-
-static inline void * bus_to_virt(unsigned long address)
-{
-#ifndef CONFIG_64BIT
- return (void *)KSEG0ADDR(address);
-#else
- return (void *)CKSEG0ADDR(address);
-#endif
+ return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
}
/*
- * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
- * for the processor.
+ * ISA I/O bus memory addresses are 1:1 with the physical address.
*/
-extern unsigned long isa_slot_offset;
-
-extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-
-#if 0
-static inline void *ioremap(unsigned long offset, unsigned long size)
+static inline unsigned long isa_virt_to_bus(volatile void *address)
{
- return __ioremap(offset, size, _CACHE_UNCACHED);
+ return (unsigned long)address - PAGE_OFFSET;
}
-static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+static inline void *isa_bus_to_virt(unsigned long address)
{
- return __ioremap(offset, size, _CACHE_UNCACHED);
+ return (void *)(address + PAGE_OFFSET);
}
-extern void iounmap(void *addr);
-#endif
+#define isa_page_to_bus page_to_phys
/*
- * XXX We need system specific versions of these to handle EISA address bits
- * 24-31 on SNI.
- * XXX more SNI hacks.
+ * However PCI ones are not necessarily 1:1 and therefore these interfaces
+ * are forbidden in portable PCI drivers.
+ *
+ * Allow them for x86 for legacy drivers, though.
*/
-#define __raw_readb(addr) (*(volatile unsigned char *)(addr))
-#define __raw_readw(addr) (*(volatile unsigned short *)(addr))
-#define __raw_readl(addr) (*(volatile unsigned int *)(addr))
-#define readb(addr) __raw_readb((addr))
-#define readw(addr) __ioswab16(__raw_readw((addr)))
-#define readl(addr) __ioswab32(__raw_readl((addr)))
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
-#define __raw_writeb(b, addr) (*(volatile unsigned char *)(addr)) = (b)
-#define __raw_writew(b, addr) (*(volatile unsigned short *)(addr)) = (b)
-#define __raw_writel(b, addr) (*(volatile unsigned int *)(addr)) = (b)
-#define writeb(b, addr) __raw_writeb((b), (addr))
-#define writew(b, addr) __raw_writew(__ioswab16(b), (addr))
-#define writel(b, addr) __raw_writel(__ioswab32(b), (addr))
+static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
+{
+ void __iomem *addr;
+ phys_addr_t phys_addr;
-#define memset_io(a,b,c) memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+ addr = plat_ioremap(offset, size, flags);
+ if (addr)
+ return addr;
-/* END SNI HACKS ... */
+ phys_addr = fixup_bigphys_addr(offset, size);
+ return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr);
+}
/*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
+ * ioremap - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
*/
-#define __ISA_IO_base ((char *)(PAGE_OFFSET))
-
-#define isa_readb(a) readb(a)
-#define isa_readw(a) readw(a)
-#define isa_readl(a) readl(a)
-#define isa_writeb(b,a) writeb(b,a)
-#define isa_writew(w,a) writew(w,a)
-#define isa_writel(l,a) writel(l,a)
-
-#define isa_memset_io(a,b,c) memset_io((a),(b),(c))
-#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
-#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c))
+#define ioremap(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_UNCACHED)
/*
- * We don't have csum_partial_copy_fromio() yet, so we cheat here and
- * just copy it. The net code will then do the checksum later.
+ * ioremap_nocache - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked uncachable
+ * on the CPU as well as honouring existing caching rules from things like
+ * the PCI bus. Note that there are other caches and buffers on many
+ * busses. In particular driver authors should read up on PCI writes
+ *
+ * It's useful if some control registers are in such an area and
+ * write combining or read caching is not desirable:
*/
-#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
-#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
-
-static inline int check_signature(unsigned long io_addr,
- const unsigned char *signature, int length)
-{
- int retval = 0;
- do {
- if (readb(io_addr) != *signature)
- goto out;
- io_addr++;
- signature++;
- length--;
- } while (length);
- retval = 1;
-out:
- return retval;
-}
-#define isa_check_signature(io, s, l) check_signature(i,s,l)
+#define ioremap_nocache(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_UNCACHED)
+#define ioremap_uc ioremap_nocache
/*
- * Talk about misusing macros..
+ * ioremap_cachable - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked cachable by
+ * the CPU. Also enables full write-combining. Useful for some
+ * memory-like regions on I/O busses.
*/
-
-#define __OUT1(s) \
-static inline void __out##s(unsigned int value, unsigned int port) {
-
-#define __OUT2(m) \
-__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
-
-#define __OUT(m,s,w) \
-__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
-__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \
-__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
- SLOW_DOWN_IO; } \
-__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \
- SLOW_DOWN_IO; }
-
-#define __IN1(t,s) \
-static inline t __in##s(unsigned int port) { t _v;
+#define ioremap_cachable(offset, size) \
+ __ioremap_mode((offset), (size), _page_cachable_default)
/*
- * Required nops will be inserted by the assembler
+ * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
+ * requests a cachable mapping, ioremap_uncached_accelerated requests a
+ * mapping using the uncached accelerated mode which isn't supported on
+ * all processors.
*/
-#define __IN2(m) \
-__asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
-
-#define __IN(t,m,s,w) \
-__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
-__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \
-__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \
-__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
+#define ioremap_cacheable_cow(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
+#define ioremap_uncached_accelerated(offset, size) \
+ __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
-#define __INS1(s) \
-static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
-
-#define __INS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,%4(%5)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,(%0)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __INS(m,s,i) \
-__INS1(s) __INS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), \
- "r" (mips_io_port_base+port), "I" (i) \
- : "$1");} \
-__INS1(s##c) __INS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "ir" (port), \
- "r" (mips_io_port_base), "I" (i) \
- : "$1");}
-
-#define __OUTS1(s) \
-static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
-
-#define __OUTS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n" \
- "1:\tl" #m "\t$1,(%0)\n\t" \
- "subu\t%1,1\n\t" \
- "s" #m "\t$1,%4(%5)\n\t" \
- "bne\t$0,%1,1b\n\t" \
- "addiu\t%0,%6\n\t" \
- ".set\tat\n\t" \
- ".set\treorder"
-
-#define __OUTS(m,s,i) \
-__OUTS1(s) __OUTS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
- : "$1");} \
-__OUTS1(s##c) __OUTS2(m) \
- : "=r" (addr), "=r" (count) \
- : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
- : "$1");}
-
-__IN(unsigned char,b,b,8)
-__IN(unsigned short,h,w,16)
-__IN(unsigned int,w,l,32)
-
-__OUT(b,b,8)
-__OUT(h,w,16)
-__OUT(w,l,32)
+static inline void iounmap(const volatile void __iomem *addr)
+{
+ plat_iounmap(addr);
+}
-__INS(b,b,1)
-__INS(h,w,2)
-__INS(w,l,4)
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define war_octeon_io_reorder_wmb() wmb()
+#else
+#define war_octeon_io_reorder_wmb() do { } while (0)
+#endif
-__OUTS(b,b,1)
-__OUTS(h,w,2)
-__OUTS(w,l,4)
+#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
+ \
+static inline void pfx##write##bwlq(type val, \
+ volatile void __iomem *mem) \
+{ \
+ volatile type *__mem; \
+ type __val; \
+ \
+ war_octeon_io_reorder_wmb(); \
+ \
+ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
+ \
+ __val = pfx##ioswab##bwlq(__mem, val); \
+ \
+ if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+ *__mem = __val; \
+ else if (cpu_has_64bits) { \
+ type __tmp; \
+ \
+ __asm__ __volatile__( \
+ ".set arch=r4000" "\t\t# __writeq""\n\t" \
+ "dsll32 %L0, %L0, 0" "\n\t" \
+ "dsrl32 %L0, %L0, 0" "\n\t" \
+ "dsll32 %M0, %M0, 0" "\n\t" \
+ "or %L0, %L0, %M0" "\n\t" \
+ "sd %L0, %2" "\n\t" \
+ ".set mips0" "\n" \
+ : "=r" (__tmp) \
+ : "0" (__val), "m" (*__mem)); \
+ } else \
+ BUG(); \
+} \
+ \
+static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
+{ \
+ volatile type *__mem; \
+ type __val; \
+ \
+ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
+ \
+ if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+ __val = *__mem; \
+ else if (cpu_has_64bits) { \
+ __asm__ __volatile__( \
+ ".set arch=r4000" "\t\t# __readq" "\n\t" \
+ "ld %L0, %1" "\n\t" \
+ "dsra32 %M0, %L0, 0" "\n\t" \
+ "sll %L0, %L0, 0" "\n\t" \
+ ".set mips0" "\n" \
+ : "=r" (__val) \
+ : "m" (*__mem)); \
+ } else { \
+ __val = 0; \
+ BUG(); \
+ } \
+ \
+ return pfx##ioswab##bwlq(__mem, __val); \
+}
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
+ \
+static inline void pfx##out##bwlq##p(type val, unsigned long port) \
+{ \
+ volatile type *__addr; \
+ type __val; \
+ \
+ war_octeon_io_reorder_wmb(); \
+ \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ \
+ __val = pfx##ioswab##bwlq(__addr, val); \
+ \
+ /* Really, we want this to be atomic */ \
+ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
+ \
+ *__addr = __val; \
+ slow; \
+} \
+ \
+static inline type pfx##in##bwlq##p(unsigned long port) \
+{ \
+ volatile type *__addr; \
+ type __val; \
+ \
+ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ \
+ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
+ \
+ __val = *__addr; \
+ slow; \
+ \
+ return pfx##ioswab##bwlq(__addr, __val); \
+}
-/*
- * Note that due to the way __builtin_constant_p() works, you
- * - can't use it inside an inline function (it will never be true)
- * - you don't have to worry about side effects within the __builtin..
- */
-#define outb(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outbc((val),(port)) : \
- __outb((val),(port)))
+#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
+ \
+__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
-#define inb(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inbc(port) : \
- __inb(port))
+#define BUILDIO_MEM(bwlq, type) \
+ \
+__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
+__BUILD_MEMORY_PFX(, bwlq, type) \
+__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
-#define outb_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outbc_p((val),(port)) : \
- __outb_p((val),(port)))
+BUILDIO_MEM(b, u8)
+BUILDIO_MEM(w, u16)
+BUILDIO_MEM(l, u32)
+BUILDIO_MEM(q, u64)
-#define inb_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inbc_p(port) : \
- __inb_p(port))
+#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
-#define outw(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outwc((val),(port)) : \
- __outw((val),(port)))
+#define BUILDIO_IOPORT(bwlq, type) \
+ __BUILD_IOPORT_PFX(, bwlq, type) \
+ __BUILD_IOPORT_PFX(__mem_, bwlq, type)
-#define inw(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inwc(port) : \
- __inw(port))
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+#ifdef CONFIG_64BIT
+BUILDIO_IOPORT(q, u64)
+#endif
-#define outw_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outwc_p((val),(port)) : \
- __outw_p((val),(port)))
+#define __BUILDIO(bwlq, type) \
+ \
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
-#define inw_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inwc_p(port) : \
- __inw_p(port))
+__BUILDIO(q, u64)
-#define outl(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outlc((val),(port)) : \
- __outl((val),(port)))
+#define readb_relaxed readb
+#define readw_relaxed readw
+#define readl_relaxed readl
+#define readq_relaxed readq
-#define inl(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inlc(port) : \
- __inl(port))
+#define writeb_relaxed writeb
+#define writew_relaxed writew
+#define writel_relaxed writel
+#define writeq_relaxed writeq
-#define outl_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outlc_p((val),(port)) : \
- __outl_p((val),(port)))
+#define readb_be(addr) \
+ __raw_readb((__force unsigned *)(addr))
+#define readw_be(addr) \
+ be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
+#define readl_be(addr) \
+ be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
+#define readq_be(addr) \
+ be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
-#define inl_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inlc_p(port) : \
- __inl_p(port))
+#define writeb_be(val, addr) \
+ __raw_writeb((val), (__force unsigned *)(addr))
+#define writew_be(val, addr) \
+ __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
+#define writel_be(val, addr) \
+ __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
+#define writeq_be(val, addr) \
+ __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
+/*
+ * Some code tests for these symbols
+ */
+#define readq readq
+#define writeq writeq
-#define outsb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outsbc((port),(addr),(count)) : \
- __outsb ((port),(addr),(count)))
+#define __BUILD_MEMORY_STRING(bwlq, type) \
+ \
+static inline void writes##bwlq(volatile void __iomem *mem, \
+ const void *addr, unsigned int count) \
+{ \
+ const volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ __mem_write##bwlq(*__addr, mem); \
+ __addr++; \
+ } \
+} \
+ \
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
+ unsigned int count) \
+{ \
+ volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ *__addr = __mem_read##bwlq(mem); \
+ __addr++; \
+ } \
+}
-#define insb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __insbc((port),(addr),(count)) : \
- __insb((port),(addr),(count)))
+#define __BUILD_IOPORT_STRING(bwlq, type) \
+ \
+static inline void outs##bwlq(unsigned long port, const void *addr, \
+ unsigned int count) \
+{ \
+ const volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ __mem_out##bwlq(*__addr, port); \
+ __addr++; \
+ } \
+} \
+ \
+static inline void ins##bwlq(unsigned long port, void *addr, \
+ unsigned int count) \
+{ \
+ volatile type *__addr = addr; \
+ \
+ while (count--) { \
+ *__addr = __mem_in##bwlq(port); \
+ __addr++; \
+ } \
+}
-#define outsw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outswc((port),(addr),(count)) : \
- __outsw ((port),(addr),(count)))
+#define BUILDSTRING(bwlq, type) \
+ \
+__BUILD_MEMORY_STRING(bwlq, type) \
+__BUILD_IOPORT_STRING(bwlq, type)
-#define insw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inswc((port),(addr),(count)) : \
- __insw((port),(addr),(count)))
+BUILDSTRING(b, u8)
+BUILDSTRING(w, u16)
+BUILDSTRING(l, u32)
+#ifdef CONFIG_64BIT
+BUILDSTRING(q, u64)
+#endif
-#define outsl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __outslc((port),(addr),(count)) : \
- __outsl ((port),(addr),(count)))
-#define insl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
- __inslc((port),(addr),(count)) : \
- __insl((port),(addr),(count)))
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define mmiowb() wmb()
+#else
+/* Depends on MIPS II instruction set */
+#define mmiowb() asm volatile ("sync" ::: "memory")
+#endif
-#define IO_SPACE_LIMIT 0xffff
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+ memset((void __force *)addr, val, count);
+}
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
+{
+ memcpy(dst, (void __force *)src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
+{
+ memcpy((void __force *)dst, src, count);
+}
/*
- * The caches on some architectures aren't dma-coherent and have need to
- * handle this in software. There are three types of operations that
- * can be applied to dma buffers.
- *
- * - dma_cache_wback_inv(start, size) makes caches and coherent by
- * writing the content of the caches back to memory, if necessary.
- * The function also invalidates the affected part of the caches as
- * necessary before DMA transfers from outside to memory.
- * - dma_cache_wback(start, size) makes caches and coherent by
- * writing the content of the caches back to memory, if necessary.
- * The function also invalidates the affected part of the caches as
- * necessary before DMA transfers from outside to memory.
- * - dma_cache_inv(start, size) invalidates the affected parts of the
- * caches. Dirty lines of the caches may be written back or simply
- * be discarded. This operation is necessary before dma operations
- * to the memory.
+ * Read a 32-bit register that requires a 64-bit read cycle on the bus.
+ * Avoid interrupt mucking, just adjust the address for 4-byte access.
+ * Assume the addresses are 8-byte aligned.
*/
-extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+#ifdef __MIPSEB__
+#define __CSR_32_ADJUST 4
+#else
+#define __CSR_32_ADJUST 0
+#endif
-#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
-#define dma_cache_wback(start,size) _dma_cache_wback(start,size)
-#define dma_cache_inv(start,size) _dma_cache_inv(start,size)
-
-static inline void sync(void)
-{
-}
+#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
+ * U-Boot specific
*/
-#define MAP_NOCACHE (0)
+#define sync() mmiowb()
+
+#define MAP_NOCACHE (1)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
@@ -493,6 +528,9 @@
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
+ if (flags == MAP_NOCACHE)
+ return ioremap(paddr, len);
+
return (void *)paddr;
}
@@ -501,7 +539,61 @@
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
+}
+
+#define __BUILD_CLRBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define __BUILD_SETBITS(bwlq, sfx, end, type) \
+ \
+static inline void setbits_##sfx(volatile void __iomem *mem, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
+}
+#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrsetbits_##sfx(volatile void __iomem *mem, \
+ type clr, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val); \
+ __val &= ~clr; \
+ __val |= set; \
+ __val = cpu_to_##end(__val); \
+ __raw_write##bwlq(__val, mem); \
}
+#define BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+__BUILD_CLRBITS(bwlq, sfx, end, type) \
+__BUILD_SETBITS(bwlq, sfx, end, type) \
+__BUILD_CLRSETBITS(bwlq, sfx, end, type)
+
+#define __to_cpu(v) (v)
+#define cpu_to__(v) (v)
+
+BUILD_CLRSETBITS(b, 8, _, u8)
+BUILD_CLRSETBITS(w, le16, le16, u16)
+BUILD_CLRSETBITS(w, be16, be16, u16)
+BUILD_CLRSETBITS(w, 16, _, u16)
+BUILD_CLRSETBITS(l, le32, le32, u32)
+BUILD_CLRSETBITS(l, be32, be32, u32)
+BUILD_CLRSETBITS(l, 32, _, u32)
+BUILD_CLRSETBITS(q, le64, le64, u64)
+BUILD_CLRSETBITS(q, be64, be64, u64)
+BUILD_CLRSETBITS(q, 64, _, u64)
+
#endif /* _ASM_IO_H */
diff --git a/arch/mips/include/asm/isadep.h b/arch/mips/include/asm/isadep.h
index 24c6cda..3d79ebc 100644
--- a/arch/mips/include/asm/isadep.h
+++ b/arch/mips/include/asm/isadep.h
@@ -4,6 +4,8 @@
* of Coprocessor 0 registers.
*
* Copyright (c) 1998 Harald Koerfgen
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ISADEP_H
@@ -18,7 +20,7 @@
* kernel or user mode? (CP0_STATUS)
*/
#define KU_MASK 0x08
-#define KU_USER 0x08
+#define KU_USER 0x08
#define KU_KERN 0x00
#else
@@ -26,7 +28,7 @@
* kernel or user mode?
*/
#define KU_MASK 0x18
-#define KU_USER 0x10
+#define KU_USER 0x10
#define KU_KERN 0x00
#endif
diff --git a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
new file mode 100644
index 0000000..613f844
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2003 Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+
+/* Intentionally empty file ... */
+
+#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h
new file mode 100644
index 0000000..6b191d5
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/ioremap.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+ phys_addr_t size)
+{
+ return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
+{
+ return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+ return 0;
+}
+
+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-generic/mangle-port.h b/arch/mips/include/asm/mach-generic/mangle-port.h
new file mode 100644
index 0000000..f18e53f
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/mangle-port.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port) (port)
+#define __swizzle_addr_w(port) (port)
+#define __swizzle_addr_l(port) (port)
+#define __swizzle_addr_q(port) (port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time. Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses. The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) le16_to_cpu(x)
+# define __mem_ioswabw(a, x) (x)
+# define ioswabl(a, x) le32_to_cpu(x)
+# define __mem_ioswabl(a, x) (x)
+# define ioswabq(a, x) le64_to_cpu(x)
+# define __mem_ioswabq(a, x) (x)
+
+#else
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) (x)
+# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define ioswabl(a, x) (x)
+# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define ioswabq(a, x) (x)
+# define __mem_ioswabq(a, x) cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
new file mode 100644
index 0000000..ab06674
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002 Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _ASM_MACH_GENERIC_SPACES_H
+#define _ASM_MACH_GENERIC_SPACES_H
+
+#include <asm/const.h>
+
+/*
+ * This gives the physical RAM offset.
+ */
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET _AC(0, UL)
+#endif
+
+#ifdef CONFIG_32BIT
+#ifdef CONFIG_KVM_GUEST
+#define CAC_BASE _AC(0x40000000, UL)
+#else
+#define CAC_BASE _AC(0x80000000, UL)
+#endif
+#ifndef IO_BASE
+#define IO_BASE _AC(0xa0000000, UL)
+#endif
+#ifndef UNCAC_BASE
+#define UNCAC_BASE _AC(0xa0000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#ifdef CONFIG_KVM_GUEST
+#define MAP_BASE _AC(0x60000000, UL)
+#else
+#define MAP_BASE _AC(0xc0000000, UL)
+#endif
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START _AC(0x20000000, UL)
+#endif
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#ifndef CAC_BASE
+#ifdef CONFIG_DMA_NONCOHERENT
+#define CAC_BASE _AC(0x9800000000000000, UL)
+#else
+#define CAC_BASE _AC(0xa800000000000000, UL)
+#endif
+#endif
+
+#ifndef IO_BASE
+#define IO_BASE _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef UNCAC_BASE
+#define UNCAC_BASE _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#define MAP_BASE _AC(0xc000000000000000, UL)
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ * Fixme: 59 bits is a fictive number and makes assumptions about processors
+ * in the distant future. Nobody will care for a few years :-)
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL))
+#endif
+
+#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
+#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * This handles the memory map.
+ */
+#ifndef PAGE_OFFSET
+#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET)
+#endif
+
+#ifndef FIXADDR_TOP
+#ifdef CONFIG_KVM_GUEST
+#define FIXADDR_TOP ((unsigned long)(long)(int)0x7ffe0000)
+#else
+#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
+#endif
+#endif
+
+#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index c7a0849..3185dc7 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1,22 +1,16 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
* Copyright (C) 2000 Silicon Graphics, Inc.
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000, 07 MIPS Technologies, Inc.
* Copyright (C) 2003, 2004 Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
-#if 0
-#include <linux/linkage.h>
-#endif
-
/*
* The following macros are especially useful for __asm__
* inline assembler.
@@ -49,7 +43,9 @@
#define CP0_PAGEMASK $5
#define CP0_WIRED $6
#define CP0_INFO $7
+#define CP0_HWRENA $7, 0
#define CP0_BADVADDR $8
+#define CP0_BADINSTR $8, 1
#define CP0_COUNT $9
#define CP0_ENTRYHI $10
#define CP0_COMPARE $11
@@ -57,7 +53,11 @@
#define CP0_CAUSE $13
#define CP0_EPC $14
#define CP0_PRID $15
+#define CP0_EBASE $15, 1
+#define CP0_CMGCRBASE $15, 3
#define CP0_CONFIG $16
+#define CP0_CONFIG3 $16, 3
+#define CP0_CONFIG5 $16, 5
#define CP0_LLADDR $17
#define CP0_WATCHLO $18
#define CP0_WATCHHI $19
@@ -98,74 +98,36 @@
/*
* Coprocessor 0 Set 2 register names
*/
-#define CP0_S2_SRSCTL $12 /* MIPSR2 */
+#define CP0_S2_SRSCTL $12 /* MIPSR2 */
/*
* Coprocessor 0 Set 3 register names
*/
-#define CP0_S3_SRSMAP $12 /* MIPSR2 */
+#define CP0_S3_SRSMAP $12 /* MIPSR2 */
/*
* TX39 Series
*/
#define CP0_TX39_CACHE $7
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION $0
-#define CP1_STATUS $31
-
-/*
- * FPU Status Register Values
- */
-/*
- * Status Register Values
- */
-
-#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
-#define FPU_CSR_COND 0x00800000 /* $fcc0 */
-#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
-#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
-#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
-#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
-#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
-#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
-#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
-#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
-/*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
- */
-#define FPU_CSR_ALL_X 0x0003f000
-#define FPU_CSR_UNI_X 0x00020000
-#define FPU_CSR_INV_X 0x00010000
-#define FPU_CSR_DIV_X 0x00008000
-#define FPU_CSR_OVF_X 0x00004000
-#define FPU_CSR_UDF_X 0x00002000
-#define FPU_CSR_INE_X 0x00001000
-
-#define FPU_CSR_ALL_E 0x00000f80
-#define FPU_CSR_INV_E 0x00000800
-#define FPU_CSR_DIV_E 0x00000400
-#define FPU_CSR_OVF_E 0x00000200
-#define FPU_CSR_UDF_E 0x00000100
-#define FPU_CSR_INE_E 0x00000080
+/* Generic EntryLo bit definitions */
+#define ENTRYLO_G (_ULCAST_(1) << 0)
+#define ENTRYLO_V (_ULCAST_(1) << 1)
+#define ENTRYLO_D (_ULCAST_(1) << 2)
+#define ENTRYLO_C_SHIFT 3
+#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
-#define FPU_CSR_ALL_S 0x0000007c
-#define FPU_CSR_INV_S 0x00000040
-#define FPU_CSR_DIV_S 0x00000020
-#define FPU_CSR_OVF_S 0x00000010
-#define FPU_CSR_UDF_S 0x00000008
-#define FPU_CSR_INE_S 0x00000004
+/* R3000 EntryLo bit definitions */
+#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
+#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
+#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
+#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
-/* rounding mode */
-#define FPU_CSR_RN 0x0 /* nearest */
-#define FPU_CSR_RZ 0x1 /* towards zero */
-#define FPU_CSR_RU 0x2 /* towards +Infinity */
-#define FPU_CSR_RD 0x3 /* towards -Infinity */
+/* MIPS32/64 EntryLo bit definitions */
+#define MIPS_ENTRYLO_PFN_SHIFT 6
+#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
+#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
/*
* Values for PageMask register
@@ -183,14 +145,22 @@
#else
#define PM_4K 0x00000000
+#define PM_8K 0x00002000
#define PM_16K 0x00006000
+#define PM_32K 0x0000e000
#define PM_64K 0x0001e000
+#define PM_128K 0x0003e000
#define PM_256K 0x0007e000
+#define PM_512K 0x000fe000
#define PM_1M 0x001fe000
+#define PM_2M 0x003fe000
#define PM_4M 0x007fe000
+#define PM_8M 0x00ffe000
#define PM_16M 0x01ffe000
+#define PM_32M 0x03ffe000
#define PM_64M 0x07ffe000
#define PM_256M 0x1fffe000
+#define PM_1G 0x7fffe000
#endif
@@ -208,10 +178,22 @@
#define PL_256M 28
/*
+ * PageGrain bits
+ */
+#define PG_RIE (_ULCAST_(1) << 31)
+#define PG_XIE (_ULCAST_(1) << 30)
+#define PG_ELPA (_ULCAST_(1) << 29)
+#define PG_ESP (_ULCAST_(1) << 28)
+#define PG_IEC (_ULCAST_(1) << 27)
+
+/* MIPS32/64 EntryHI bit definitions */
+#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
+
+/*
* R4x00 interrupt enable / cause bits
*/
-#define IE_SW0 (_ULCAST_(1) << 8)
-#define IE_SW1 (_ULCAST_(1) << 9)
+#define IE_SW0 (_ULCAST_(1) << 8)
+#define IE_SW1 (_ULCAST_(1) << 9)
#define IE_IRQ0 (_ULCAST_(1) << 10)
#define IE_IRQ1 (_ULCAST_(1) << 11)
#define IE_IRQ2 (_ULCAST_(1) << 12)
@@ -222,8 +204,8 @@
/*
* R4x00 interrupt cause bits
*/
-#define C_SW0 (_ULCAST_(1) << 8)
-#define C_SW1 (_ULCAST_(1) << 9)
+#define C_SW0 (_ULCAST_(1) << 8)
+#define C_SW1 (_ULCAST_(1) << 9)
#define C_IRQ0 (_ULCAST_(1) << 10)
#define C_IRQ1 (_ULCAST_(1) << 11)
#define C_IRQ2 (_ULCAST_(1) << 12)
@@ -271,7 +253,7 @@
/*
* Bits specific to the R4640/R4650
*/
-#define ST0_UM (_ULCAST_(1) << 4)
+#define ST0_UM (_ULCAST_(1) << 4)
#define ST0_IL (_ULCAST_(1) << 23)
#define ST0_DL (_ULCAST_(1) << 24)
@@ -281,75 +263,43 @@
#define ST0_MX 0x01000000
/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT 19
-#define TX39_CONF_ICS_MASK 0x00380000
-#define TX39_CONF_ICS_1KB 0x00000000
-#define TX39_CONF_ICS_2KB 0x00080000
-#define TX39_CONF_ICS_4KB 0x00100000
-#define TX39_CONF_ICS_8KB 0x00180000
-#define TX39_CONF_ICS_16KB 0x00200000
-
-#define TX39_CONF_DCS_SHIFT 16
-#define TX39_CONF_DCS_MASK 0x00070000
-#define TX39_CONF_DCS_1KB 0x00000000
-#define TX39_CONF_DCS_2KB 0x00010000
-#define TX39_CONF_DCS_4KB 0x00020000
-#define TX39_CONF_DCS_8KB 0x00030000
-#define TX39_CONF_DCS_16KB 0x00040000
-
-#define TX39_CONF_CWFON 0x00004000
-#define TX39_CONF_WBON 0x00002000
-#define TX39_CONF_RF_SHIFT 10
-#define TX39_CONF_RF_MASK 0x00000c00
-#define TX39_CONF_DOZE 0x00000200
-#define TX39_CONF_HALT 0x00000100
-#define TX39_CONF_LOCK 0x00000080
-#define TX39_CONF_ICE 0x00000020
-#define TX39_CONF_DCE 0x00000010
-#define TX39_CONF_IRSIZE_SHIFT 2
-#define TX39_CONF_IRSIZE_MASK 0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT 0
-#define TX39_CONF_DRSIZE_MASK 0x00000003
-
-/*
* Status register bits available in all MIPS CPUs.
*/
#define ST0_IM 0x0000ff00
-#define STATUSB_IP0 8
-#define STATUSF_IP0 (_ULCAST_(1) << 8)
-#define STATUSB_IP1 9
-#define STATUSF_IP1 (_ULCAST_(1) << 9)
-#define STATUSB_IP2 10
-#define STATUSF_IP2 (_ULCAST_(1) << 10)
-#define STATUSB_IP3 11
-#define STATUSF_IP3 (_ULCAST_(1) << 11)
-#define STATUSB_IP4 12
-#define STATUSF_IP4 (_ULCAST_(1) << 12)
-#define STATUSB_IP5 13
-#define STATUSF_IP5 (_ULCAST_(1) << 13)
-#define STATUSB_IP6 14
-#define STATUSF_IP6 (_ULCAST_(1) << 14)
-#define STATUSB_IP7 15
-#define STATUSF_IP7 (_ULCAST_(1) << 15)
-#define STATUSB_IP8 0
-#define STATUSF_IP8 (_ULCAST_(1) << 0)
-#define STATUSB_IP9 1
-#define STATUSF_IP9 (_ULCAST_(1) << 1)
-#define STATUSB_IP10 2
-#define STATUSF_IP10 (_ULCAST_(1) << 2)
-#define STATUSB_IP11 3
-#define STATUSF_IP11 (_ULCAST_(1) << 3)
-#define STATUSB_IP12 4
-#define STATUSF_IP12 (_ULCAST_(1) << 4)
-#define STATUSB_IP13 5
-#define STATUSF_IP13 (_ULCAST_(1) << 5)
-#define STATUSB_IP14 6
-#define STATUSF_IP14 (_ULCAST_(1) << 6)
-#define STATUSB_IP15 7
-#define STATUSF_IP15 (_ULCAST_(1) << 7)
+#define STATUSB_IP0 8
+#define STATUSF_IP0 (_ULCAST_(1) << 8)
+#define STATUSB_IP1 9
+#define STATUSF_IP1 (_ULCAST_(1) << 9)
+#define STATUSB_IP2 10
+#define STATUSF_IP2 (_ULCAST_(1) << 10)
+#define STATUSB_IP3 11
+#define STATUSF_IP3 (_ULCAST_(1) << 11)
+#define STATUSB_IP4 12
+#define STATUSF_IP4 (_ULCAST_(1) << 12)
+#define STATUSB_IP5 13
+#define STATUSF_IP5 (_ULCAST_(1) << 13)
+#define STATUSB_IP6 14
+#define STATUSF_IP6 (_ULCAST_(1) << 14)
+#define STATUSB_IP7 15
+#define STATUSF_IP7 (_ULCAST_(1) << 15)
+#define STATUSB_IP8 0
+#define STATUSF_IP8 (_ULCAST_(1) << 0)
+#define STATUSB_IP9 1
+#define STATUSF_IP9 (_ULCAST_(1) << 1)
+#define STATUSB_IP10 2
+#define STATUSF_IP10 (_ULCAST_(1) << 2)
+#define STATUSB_IP11 3
+#define STATUSF_IP11 (_ULCAST_(1) << 3)
+#define STATUSB_IP12 4
+#define STATUSF_IP12 (_ULCAST_(1) << 4)
+#define STATUSB_IP13 5
+#define STATUSF_IP13 (_ULCAST_(1) << 5)
+#define STATUSB_IP14 6
+#define STATUSF_IP14 (_ULCAST_(1) << 6)
+#define STATUSB_IP15 7
+#define STATUSF_IP15 (_ULCAST_(1) << 7)
#define ST0_CH 0x00040000
+#define ST0_NMI 0x00080000
#define ST0_SR 0x00100000
#define ST0_TS 0x00200000
#define ST0_BEV 0x00400000
@@ -363,36 +313,52 @@
#define ST0_XX 0x80000000 /* MIPS IV naming */
/*
+ * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
+ */
+#define INTCTLB_IPFDC 23
+#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
+#define INTCTLB_IPPCI 26
+#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
+#define INTCTLB_IPTI 29
+#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
+
+/*
* Bitfields and bit numbers in the coprocessor 0 cause register.
*
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
*/
-#define CAUSEB_EXCCODE 2
-#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
-#define CAUSEB_IP 8
-#define CAUSEF_IP (_ULCAST_(255) << 8)
-#define CAUSEB_IP0 8
-#define CAUSEF_IP0 (_ULCAST_(1) << 8)
-#define CAUSEB_IP1 9
-#define CAUSEF_IP1 (_ULCAST_(1) << 9)
-#define CAUSEB_IP2 10
-#define CAUSEF_IP2 (_ULCAST_(1) << 10)
-#define CAUSEB_IP3 11
-#define CAUSEF_IP3 (_ULCAST_(1) << 11)
-#define CAUSEB_IP4 12
-#define CAUSEF_IP4 (_ULCAST_(1) << 12)
-#define CAUSEB_IP5 13
-#define CAUSEF_IP5 (_ULCAST_(1) << 13)
-#define CAUSEB_IP6 14
-#define CAUSEF_IP6 (_ULCAST_(1) << 14)
-#define CAUSEB_IP7 15
-#define CAUSEF_IP7 (_ULCAST_(1) << 15)
-#define CAUSEB_IV 23
-#define CAUSEF_IV (_ULCAST_(1) << 23)
-#define CAUSEB_CE 28
-#define CAUSEF_CE (_ULCAST_(3) << 28)
-#define CAUSEB_BD 31
-#define CAUSEF_BD (_ULCAST_(1) << 31)
+#define CAUSEB_EXCCODE 2
+#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
+#define CAUSEB_IP 8
+#define CAUSEF_IP (_ULCAST_(255) << 8)
+#define CAUSEB_IP0 8
+#define CAUSEF_IP0 (_ULCAST_(1) << 8)
+#define CAUSEB_IP1 9
+#define CAUSEF_IP1 (_ULCAST_(1) << 9)
+#define CAUSEB_IP2 10
+#define CAUSEF_IP2 (_ULCAST_(1) << 10)
+#define CAUSEB_IP3 11
+#define CAUSEF_IP3 (_ULCAST_(1) << 11)
+#define CAUSEB_IP4 12
+#define CAUSEF_IP4 (_ULCAST_(1) << 12)
+#define CAUSEB_IP5 13
+#define CAUSEF_IP5 (_ULCAST_(1) << 13)
+#define CAUSEB_IP6 14
+#define CAUSEF_IP6 (_ULCAST_(1) << 14)
+#define CAUSEB_IP7 15
+#define CAUSEF_IP7 (_ULCAST_(1) << 15)
+#define CAUSEB_FDCI 21
+#define CAUSEF_FDCI (_ULCAST_(1) << 21)
+#define CAUSEB_IV 23
+#define CAUSEF_IV (_ULCAST_(1) << 23)
+#define CAUSEB_PCI 26
+#define CAUSEF_PCI (_ULCAST_(1) << 26)
+#define CAUSEB_CE 28
+#define CAUSEF_CE (_ULCAST_(3) << 28)
+#define CAUSEB_TI 30
+#define CAUSEF_TI (_ULCAST_(1) << 30)
+#define CAUSEB_BD 31
+#define CAUSEF_BD (_ULCAST_(1) << 31)
/*
* Bits in the coprocessor 0 config register.
@@ -410,43 +376,43 @@
#define CONF_BE (_ULCAST_(1) << 15)
/* Bits common to various processors. */
-#define CONF_CU (_ULCAST_(1) << 3)
-#define CONF_DB (_ULCAST_(1) << 4)
-#define CONF_IB (_ULCAST_(1) << 5)
-#define CONF_DC (_ULCAST_(7) << 6)
-#define CONF_IC (_ULCAST_(7) << 9)
+#define CONF_CU (_ULCAST_(1) << 3)
+#define CONF_DB (_ULCAST_(1) << 4)
+#define CONF_IB (_ULCAST_(1) << 5)
+#define CONF_DC (_ULCAST_(7) << 6)
+#define CONF_IC (_ULCAST_(7) << 9)
#define CONF_EB (_ULCAST_(1) << 13)
#define CONF_EM (_ULCAST_(1) << 14)
#define CONF_SM (_ULCAST_(1) << 16)
#define CONF_SC (_ULCAST_(1) << 17)
#define CONF_EW (_ULCAST_(3) << 18)
-#define CONF_EP (_ULCAST_(15)<< 24)
+#define CONF_EP (_ULCAST_(15) << 24)
#define CONF_EC (_ULCAST_(7) << 28)
#define CONF_CM (_ULCAST_(1) << 31)
-/* Bits specific to the R4xx0. */
+/* Bits specific to the R4xx0. */
#define R4K_CONF_SW (_ULCAST_(1) << 20)
#define R4K_CONF_SS (_ULCAST_(1) << 21)
#define R4K_CONF_SB (_ULCAST_(3) << 22)
-/* Bits specific to the R5000. */
+/* Bits specific to the R5000. */
#define R5K_CONF_SE (_ULCAST_(1) << 12)
#define R5K_CONF_SS (_ULCAST_(3) << 20)
-/* Bits specific to the RM7000. */
-#define RM7K_CONF_SE (_ULCAST_(1) << 3)
+/* Bits specific to the RM7000. */
+#define RM7K_CONF_SE (_ULCAST_(1) << 3)
#define RM7K_CONF_TE (_ULCAST_(1) << 12)
#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
#define RM7K_CONF_TC (_ULCAST_(1) << 17)
#define RM7K_CONF_SI (_ULCAST_(3) << 20)
#define RM7K_CONF_SC (_ULCAST_(1) << 31)
-/* Bits specific to the R10000. */
-#define R10K_CONF_DN (_ULCAST_(3) << 3)
-#define R10K_CONF_CT (_ULCAST_(1) << 5)
-#define R10K_CONF_PE (_ULCAST_(1) << 6)
-#define R10K_CONF_PM (_ULCAST_(3) << 7)
-#define R10K_CONF_EC (_ULCAST_(15)<< 9)
+/* Bits specific to the R10000. */
+#define R10K_CONF_DN (_ULCAST_(3) << 3)
+#define R10K_CONF_CT (_ULCAST_(1) << 5)
+#define R10K_CONF_PE (_ULCAST_(1) << 6)
+#define R10K_CONF_PM (_ULCAST_(3) << 7)
+#define R10K_CONF_EC (_ULCAST_(15) << 9)
#define R10K_CONF_SB (_ULCAST_(1) << 13)
#define R10K_CONF_SK (_ULCAST_(1) << 14)
#define R10K_CONF_SS (_ULCAST_(7) << 16)
@@ -454,14 +420,14 @@
#define R10K_CONF_DC (_ULCAST_(7) << 26)
#define R10K_CONF_IC (_ULCAST_(7) << 29)
-/* Bits specific to the VR41xx. */
+/* Bits specific to the VR41xx. */
#define VR41_CONF_CS (_ULCAST_(1) << 12)
#define VR41_CONF_P4K (_ULCAST_(1) << 13)
#define VR41_CONF_BP (_ULCAST_(1) << 16)
#define VR41_CONF_M16 (_ULCAST_(1) << 20)
#define VR41_CONF_AD (_ULCAST_(1) << 23)
-/* Bits specific to the R30xx. */
+/* Bits specific to the R30xx. */
#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
#define R30XX_CONF_REV (_ULCAST_(1) << 22)
#define R30XX_CONF_AC (_ULCAST_(1) << 23)
@@ -478,8 +444,10 @@
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
-/* Bits specific to the MIPS32/64 PRA. */
-#define MIPS_CONF_MT (_ULCAST_(7) << 7)
+/* Bits specific to the MIPS32/64 PRA. */
+#define MIPS_CONF_MT (_ULCAST_(7) << 7)
+#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
+#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
#define MIPS_CONF_M (_ULCAST_(1) << 31)
@@ -487,51 +455,246 @@
/*
* Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
*/
-#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
-#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
-#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
-#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
-#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
-#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
-#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
-#define MIPS_CONF1_DA_SHIFT 7
-#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
-#define MIPS_CONF1_DL_SHIFT 10
+#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
+#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
+#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
+#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
+#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
+#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
+#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
+#define MIPS_CONF1_DA_SHF 7
+#define MIPS_CONF1_DA_SZ 3
+#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
+#define MIPS_CONF1_DL_SHF 10
+#define MIPS_CONF1_DL_SZ 3
#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
-#define MIPS_CONF1_DS_SHIFT 13
+#define MIPS_CONF1_DS_SHF 13
+#define MIPS_CONF1_DS_SZ 3
#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
-#define MIPS_CONF1_IA_SHIFT 16
+#define MIPS_CONF1_IA_SHF 16
+#define MIPS_CONF1_IA_SZ 3
#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
-#define MIPS_CONF1_IL_SHIFT 19
+#define MIPS_CONF1_IL_SHF 19
+#define MIPS_CONF1_IL_SZ 3
#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
-#define MIPS_CONF1_IS_SHIFT 22
+#define MIPS_CONF1_IS_SHF 22
+#define MIPS_CONF1_IS_SZ 3
#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
+#define MIPS_CONF1_TLBS_SHIFT (25)
+#define MIPS_CONF1_TLBS_SIZE (6)
+#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
-#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
-#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
-#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
-#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
-#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
-#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
-#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
+#define MIPS_CONF2_SA (_ULCAST_(15) << 0)
+#define MIPS_CONF2_SL (_ULCAST_(15) << 4)
+#define MIPS_CONF2_SS (_ULCAST_(15) << 8)
+#define MIPS_CONF2_SU (_ULCAST_(15) << 12)
+#define MIPS_CONF2_TA (_ULCAST_(15) << 16)
+#define MIPS_CONF2_TL (_ULCAST_(15) << 20)
+#define MIPS_CONF2_TS (_ULCAST_(15) << 24)
#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
-#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
-#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
-#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
-#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
-#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
-#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
-#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
+#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
+#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
+#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
+#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
+#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
+#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
+#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
+#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
+#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
+#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
+#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
+#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
+#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
+#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
+#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
+#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
+#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
+#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
+#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
+#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
+#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
+#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
+#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
+#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
+#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
+
+#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
+#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
+#define MIPS_CONF4_FTLBSETS_SHIFT (0)
+#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
+#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
+#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
+#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
+/* bits 10:8 in FTLB-only configurations */
+#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+/* bits 12:8 in VTLB-FTLB only configurations */
+#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
+#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
+#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
+#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
+#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
+#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
+#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
+#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
+#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
+#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
+
+#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
+#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
+#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
+#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
+#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
+#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
+#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
+#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
+#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
+#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
+#define MIPS_CONF5_K (_ULCAST_(1) << 30)
+
+#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
+/* proAptiv FTLB on/off bit */
+#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
+/* FTLB probability bits */
+#define MIPS_CONF6_FTLBP_SHIFT (16)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
+/* FTLB probability bits for R6 */
+#define MIPS_CONF7_FTLBP_SHIFT (18)
+
+/* MAAR bit definitions */
+#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
+#define MIPS_MAAR_ADDR_SHIFT 12
+#define MIPS_MAAR_S (_ULCAST_(1) << 1)
+#define MIPS_MAAR_V (_ULCAST_(1) << 0)
+
+/* CMGCRBase bit definitions */
+#define MIPS_CMGCRB_BASE 11
+#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
+
+/*
+ * Bits in the MIPS32 Memory Segmentation registers.
+ */
+#define MIPS_SEGCFG_PA_SHIFT 9
+#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
+#define MIPS_SEGCFG_AM_SHIFT 4
+#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
+#define MIPS_SEGCFG_EU_SHIFT 3
+#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
+#define MIPS_SEGCFG_C_SHIFT 0
+#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
+
+#define MIPS_SEGCFG_UUSK _ULCAST_(7)
+#define MIPS_SEGCFG_USK _ULCAST_(5)
+#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
+#define MIPS_SEGCFG_MUSK _ULCAST_(3)
+#define MIPS_SEGCFG_MSK _ULCAST_(2)
+#define MIPS_SEGCFG_MK _ULCAST_(1)
+#define MIPS_SEGCFG_UK _ULCAST_(0)
+
+#define MIPS_PWFIELD_GDI_SHIFT 24
+#define MIPS_PWFIELD_GDI_MASK 0x3f000000
+#define MIPS_PWFIELD_UDI_SHIFT 18
+#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
+#define MIPS_PWFIELD_MDI_SHIFT 12
+#define MIPS_PWFIELD_MDI_MASK 0x0003f000
+#define MIPS_PWFIELD_PTI_SHIFT 6
+#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
+#define MIPS_PWFIELD_PTEI_SHIFT 0
+#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
+
+#define MIPS_PWSIZE_GDW_SHIFT 24
+#define MIPS_PWSIZE_GDW_MASK 0x3f000000
+#define MIPS_PWSIZE_UDW_SHIFT 18
+#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
+#define MIPS_PWSIZE_MDW_SHIFT 12
+#define MIPS_PWSIZE_MDW_MASK 0x0003f000
+#define MIPS_PWSIZE_PTW_SHIFT 6
+#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
+#define MIPS_PWSIZE_PTEW_SHIFT 0
+#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
+
+#define MIPS_PWCTL_PWEN_SHIFT 31
+#define MIPS_PWCTL_PWEN_MASK 0x80000000
+#define MIPS_PWCTL_DPH_SHIFT 7
+#define MIPS_PWCTL_DPH_MASK 0x00000080
+#define MIPS_PWCTL_HUGEPG_SHIFT 6
+#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
+#define MIPS_PWCTL_PSN_SHIFT 0
+#define MIPS_PWCTL_PSN_MASK 0x0000003f
+
+/* CDMMBase register bit definitions */
+#define MIPS_CDMMBASE_SIZE_SHIFT 0
+#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
+#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
+#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
+#define MIPS_CDMMBASE_ADDR_SHIFT 11
+#define MIPS_CDMMBASE_ADDR_START 15
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT 19
+#define TX39_CONF_ICS_MASK 0x00380000
+#define TX39_CONF_ICS_1KB 0x00000000
+#define TX39_CONF_ICS_2KB 0x00080000
+#define TX39_CONF_ICS_4KB 0x00100000
+#define TX39_CONF_ICS_8KB 0x00180000
+#define TX39_CONF_ICS_16KB 0x00200000
+
+#define TX39_CONF_DCS_SHIFT 16
+#define TX39_CONF_DCS_MASK 0x00070000
+#define TX39_CONF_DCS_1KB 0x00000000
+#define TX39_CONF_DCS_2KB 0x00010000
+#define TX39_CONF_DCS_4KB 0x00020000
+#define TX39_CONF_DCS_8KB 0x00030000
+#define TX39_CONF_DCS_16KB 0x00040000
+
+#define TX39_CONF_CWFON 0x00004000
+#define TX39_CONF_WBON 0x00002000
+#define TX39_CONF_RF_SHIFT 10
+#define TX39_CONF_RF_MASK 0x00000c00
+#define TX39_CONF_DOZE 0x00000200
+#define TX39_CONF_HALT 0x00000100
+#define TX39_CONF_LOCK 0x00000080
+#define TX39_CONF_ICE 0x00000020
+#define TX39_CONF_DCE 0x00000010
+#define TX39_CONF_IRSIZE_SHIFT 2
+#define TX39_CONF_IRSIZE_MASK 0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT 0
+#define TX39_CONF_DRSIZE_MASK 0x00000003
+
+/*
+ * Interesting Bits in the R10K CP0 Branch Diagnostic Register
+ */
+/* Disable Branch Target Address Cache */
+#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
+/* Enable Branch Prediction Global History */
+#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
+/* Disable Branch Return Cache */
+#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
+
/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION $0
+#define CP1_UFR $1
+#define CP1_UNFR $4
+#define CP1_FCCR $25
+#define CP1_FEXR $26
+#define CP1_FENR $28
+#define CP1_STATUS $31
+
+
+/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/
#define MIPS_FPIR_S (_ULCAST_(1) << 16)
@@ -541,11 +704,150 @@
#define MIPS_FPIR_W (_ULCAST_(1) << 20)
#define MIPS_FPIR_L (_ULCAST_(1) << 21)
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
+ */
+#define MIPS_FCCR_CONDX_S 0
+#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S 0
+#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S 1
+#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S 2
+#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S 3
+#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S 4
+#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S 5
+#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S 6
+#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S 7
+#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
+ */
+#define MIPS_FENR_FS_S 2
+#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
+
+/*
+ * FPU Status Register Values
+ */
+#define FPU_CSR_COND_S 23 /* $fcc0 */
+#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
+
+#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
+#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
+
+#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
+#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S 25 /* $fcc1 */
+#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S 26 /* $fcc2 */
+#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S 27 /* $fcc3 */
+#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S 28 /* $fcc4 */
+#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S 29 /* $fcc5 */
+#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S 30 /* $fcc6 */
+#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S 31 /* $fcc7 */
+#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
+
+/*
+ * Bits 22:20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
+
+#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X 0x0003f000
+#define FPU_CSR_UNI_X 0x00020000
+#define FPU_CSR_INV_X 0x00010000
+#define FPU_CSR_DIV_X 0x00008000
+#define FPU_CSR_OVF_X 0x00004000
+#define FPU_CSR_UDF_X 0x00002000
+#define FPU_CSR_INE_X 0x00001000
+
+#define FPU_CSR_ALL_E 0x00000f80
+#define FPU_CSR_INV_E 0x00000800
+#define FPU_CSR_DIV_E 0x00000400
+#define FPU_CSR_OVF_E 0x00000200
+#define FPU_CSR_UDF_E 0x00000100
+#define FPU_CSR_INE_E 0x00000080
+
+#define FPU_CSR_ALL_S 0x0000007c
+#define FPU_CSR_INV_S 0x00000040
+#define FPU_CSR_DIV_S 0x00000020
+#define FPU_CSR_OVF_S 0x00000010
+#define FPU_CSR_UDF_S 0x00000008
+#define FPU_CSR_INE_S 0x00000004
+
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM 0x00000003
+#define FPU_CSR_RN 0x0 /* nearest */
+#define FPU_CSR_RZ 0x1 /* towards zero */
+#define FPU_CSR_RU 0x2 /* towards +Infinity */
+#define FPU_CSR_RD 0x3 /* towards -Infinity */
+
#ifndef __ASSEMBLY__
/*
- * Functions to access the R10000 performance counters. These are basically
+ * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
+ */
+#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
+ defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
+#define get_isa16_mode(x) ((x) & 0x1)
+#define msk_isa16_mode(x) ((x) & ~0x1)
+#define set_isa16_mode(x) do { (x) |= 0x1; } while (0)
+#else
+#define get_isa16_mode(x) 0
+#define msk_isa16_mode(x) (x)
+#define set_isa16_mode(x) do { } while (0)
+#endif
+
+/*
+ * microMIPS instructions can be 16-bit or 32-bit in length. This
+ * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
+ */
+static inline int mm_insn_16bit(u16 insn)
+{
+ u16 opcode = (insn >> 10) & 0x7;
+
+ return (opcode >= 1 && opcode <= 3) ? 1 : 0;
+}
+
+/*
+ * TLB Invalidate Flush
+ */
+static inline void tlbinvf(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ ".word 0x42000004\n\t" /* tlbinvf */
+ ".set pop");
+}
+
+
+/*
+ * Functions to access the R10000 performance counters. These are basically
* mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
* performance counter number encoded into bits 1 ... 5 of the instruction.
* Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
@@ -589,6 +891,7 @@
: "r" (val), "i" (counter)); \
} while (0)
+
/*
* Macros to access the system control coprocessor
*/
@@ -705,8 +1008,8 @@
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
- "dsrl\t%M0, %M0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
+ "dsra\t%M0, %M0, 32\n\t" \
+ "dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (__val)); \
else \
@@ -714,8 +1017,8 @@
".set\tmips64\n\t" \
"dmfc0\t%M0, " #source ", " #sel "\n\t" \
"dsll\t%L0, %M0, 32\n\t" \
- "dsrl\t%M0, %M0, 32\n\t" \
- "dsrl\t%L0, %L0, 32\n\t" \
+ "dsra\t%M0, %M0, 32\n\t" \
+ "dsra\t%L0, %L0, 32\n\t" \
".set\tmips0" \
: "=r" (__val)); \
local_irq_restore(__flags); \
@@ -751,15 +1054,57 @@
local_irq_restore(__flags); \
} while (0)
+#define __readx_32bit_c0_register(source) \
+({ \
+ unsigned int __res; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " .set mips32r2 \n" \
+ " .insn \n" \
+ " # mfhc0 $1, %1 \n" \
+ " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__res) \
+ : "i" (source)); \
+ __res; \
+})
+
+#define __writex_32bit_c0_register(register, value) \
+({ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " .set mips32r2 \n" \
+ " move $1, %0 \n" \
+ " # mthc0 $1, %1 \n" \
+ " .insn \n" \
+ " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
+ " .set pop \n" \
+ : \
+ : "r" (value), "i" (register)); \
+})
+
#define read_c0_index() __read_32bit_c0_register($0, 0)
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
+#define read_c0_random() __read_32bit_c0_register($1, 0)
+#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
+
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
+#define readx_c0_entrylo0() __readx_32bit_c0_register(2)
+#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
+
#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
+#define readx_c0_entrylo1() __readx_32bit_c0_register(3)
+#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
+
#define read_c0_conf() __read_32bit_c0_register($3, 0)
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
@@ -767,17 +1112,20 @@
#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
-#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
+#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
+#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
+
#define read_c0_wired() __read_32bit_c0_register($6, 0)
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
#define read_c0_info() __read_32bit_c0_register($7, 0)
-#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
+#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
@@ -805,19 +1153,8 @@
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
#define read_c0_status() __read_32bit_c0_register($12, 0)
-#ifdef CONFIG_MIPS_MT_SMTC
-#define write_c0_status(val) \
-do { \
- __write_32bit_c0_register($12, 0, val); \
- __ehb(); \
-} while (0)
-#else
-/*
- * Legacy non-SMTC code, which may be hazardous
- * but which might not support EHB
- */
+
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
-#endif /* CONFIG_MIPS_MT_SMTC */
#define read_c0_cause() __read_32bit_c0_register($13, 0)
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
@@ -827,6 +1164,8 @@
#define read_c0_prid() __read_32bit_c0_register($15, 0)
+#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
+
#define read_c0_config() __read_32bit_c0_register($16, 0)
#define read_c0_config1() __read_32bit_c0_register($16, 1)
#define read_c0_config2() __read_32bit_c0_register($16, 2)
@@ -844,8 +1183,15 @@
#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
+#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
+#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
+#define read_c0_maar() __read_ulong_c0_register($17, 1)
+#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
+#define read_c0_maari() __read_32bit_c0_register($17, 2)
+#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
+
/*
- * The WatchLo register. There may be upto 8 of them.
+ * The WatchLo register. There may be up to 8 of them.
*/
#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
@@ -865,7 +1211,7 @@
#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
/*
- * The WatchHi register. There may be upto 8 of them.
+ * The WatchHi register. There may be up to 8 of them.
*/
#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
@@ -892,15 +1238,15 @@
#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
#define read_c0_framemask() __read_32bit_c0_register($21, 0)
-#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
-
-/* RM9000 PerfControl performance counter control register */
-#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
-#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
#define read_c0_diag() __read_32bit_c0_register($22, 0)
#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
+/* R10K CP0 Branch Diagnostic register is 64bits wide */
+#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
+#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
+
#define read_c0_diag1() __read_32bit_c0_register($22, 1)
#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
@@ -926,36 +1272,40 @@
* MIPS32 / MIPS64 performance counters
*/
#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
-#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
+#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
-#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
+#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
-#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
+#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
-#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
+#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
-#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
+#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
-#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
+#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
-#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
+#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
-#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
-
-/* RM9000 PerfCount performance counter register */
-#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
-#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
+#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
+#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
+#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
-#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
-#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
@@ -963,6 +1313,12 @@
#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
+#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
+#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
+
+#define read_c0_staglo() __read_32bit_c0_register($28, 4)
+#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
+
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
@@ -985,271 +1341,524 @@
#define read_c0_ebase() __read_32bit_c0_register($15, 1)
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
+#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
+#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
+
+/* MIPSR3 */
+#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
+#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
+
+#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
+#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
+
+#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
+#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
+
+/* Hardware Page Table Walker */
+#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
+#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
+
+#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
+#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
+
+#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
+#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
+
+#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
+#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
+
+/* Cavium OCTEON (cnMIPS) */
+#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
+#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
+
+#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
+#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
+
+#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
+#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
/*
- * Macros to access the floating point coprocessor control registers
+ * The cacheerr registers are not standardized. On OCTEON, they are
+ * 64 bits wide.
*/
-#define read_32bit_cp1_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "cfc1\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
+#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
+#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
-#define rddsp(mask) \
+#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
+#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
+
+/* BMIPS3300 */
+#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
+
+/* BMIPS43xx */
+#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
+#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
+
+/* BMIPS5000 */
+#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
+#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define _read_32bit_cp1_register(source, gas_hardfloat) \
({ \
unsigned int __res; \
\
__asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # rddsp $1, %x1 \n" \
- " .word 0x7c000cb8 | (%x1 << 16) \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__res) \
- : "i" (mask)); \
+ " .set push \n" \
+ " .set reorder \n" \
+ " # gas fails to assemble cfc1 for some archs, \n" \
+ " # like Octeon. \n" \
+ " .set mips1 \n" \
+ " "STR(gas_hardfloat)" \n" \
+ " cfc1 %0,"STR(source)" \n" \
+ " .set pop \n" \
+ : "=r" (__res)); \
__res; \
})
-#define wrdsp(val, mask) \
-do { \
+#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
- " .set noat \n" \
- " move $1, %0 \n" \
- " # wrdsp $1, %x1 \n" \
- " .word 0x7c2004f8 | (%x1 << 11) \n" \
+ " .set reorder \n" \
+ " "STR(gas_hardfloat)" \n" \
+ " ctc1 %0,"STR(dest)" \n" \
" .set pop \n" \
+ : : "r" (val)); \
+})
+
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source) \
+ _read_32bit_cp1_register(source, .set hardfloat)
+#define write_32bit_cp1_register(dest, val) \
+ _write_32bit_cp1_register(dest, val, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source) \
+ _read_32bit_cp1_register(source, )
+#define write_32bit_cp1_register(dest, val) \
+ _write_32bit_cp1_register(dest, val, )
+#endif
+
+#ifdef HAVE_AS_DSP
+#define rddsp(mask) \
+({ \
+ unsigned int __dspctl; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " rddsp %0, %x1 \n" \
+ " .set pop \n" \
+ : "=r" (__dspctl) \
+ : "i" (mask)); \
+ __dspctl; \
+})
+
+#define wrdsp(val, mask) \
+({ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " wrdsp %0, %x1 \n" \
+ " .set pop \n" \
: \
: "r" (val), "i" (mask)); \
-} while (0)
+})
+
+#define mflo0() \
+({ \
+ long mflo0; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac0 \n" \
+ " .set pop \n" \
+ : "=r" (mflo0)); \
+ mflo0; \
+})
+
+#define mflo1() \
+({ \
+ long mflo1; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac1 \n" \
+ " .set pop \n" \
+ : "=r" (mflo1)); \
+ mflo1; \
+})
+
+#define mflo2() \
+({ \
+ long mflo2; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac2 \n" \
+ " .set pop \n" \
+ : "=r" (mflo2)); \
+ mflo2; \
+})
+
+#define mflo3() \
+({ \
+ long mflo3; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mflo %0, $ac3 \n" \
+ " .set pop \n" \
+ : "=r" (mflo3)); \
+ mflo3; \
+})
#define mfhi0() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac0 \n" \
- " .word 0x00000810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi0; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac0 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi0)); \
+ mfhi0; \
})
#define mfhi1() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac1 \n" \
- " .word 0x00200810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi1; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac1 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi1)); \
+ mfhi1; \
})
#define mfhi2() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac2 \n" \
- " .word 0x00400810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi2; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac2 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi2)); \
+ mfhi2; \
})
#define mfhi3() \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mfhi %0, $ac3 \n" \
- " .word 0x00600810 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ long mfhi3; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mfhi %0, $ac3 \n" \
+ " .set pop \n" \
+ : "=r" (mfhi3)); \
+ mfhi3; \
})
-#define mflo0() \
+
+#define mtlo0(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac0 \n" \
- " .word 0x00000812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac0 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
-#define mflo1() \
+#define mtlo1(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac1 \n" \
- " .word 0x00200812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac1 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
-#define mflo2() \
+#define mtlo2(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac2 \n" \
- " .word 0x00400812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac2 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
-#define mflo3() \
+#define mtlo3(x) \
({ \
- unsigned long __treg; \
- \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " # mflo %0, $ac3 \n" \
- " .word 0x00600812 \n" \
- " move %0, $1 \n" \
- " .set pop \n" \
- : "=r" (__treg)); \
- __treg; \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mtlo %0, $ac3 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
})
#define mthi0(x) \
-do { \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noat \n" \
- " move $1, %0 \n" \
- " # mthi $1, $ac0 \n" \
- " .word 0x00200011 \n" \
- " .set pop \n" \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac0 \n" \
+ " .set pop \n" \
: \
: "r" (x)); \
-} while (0)
+})
#define mthi1(x) \
-do { \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac1 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+})
+
+#define mthi2(x) \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac2 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+})
+
+#define mthi3(x) \
+({ \
+ __asm__( \
+ " .set push \n" \
+ " .set dsp \n" \
+ " mthi %0, $ac3 \n" \
+ " .set pop \n" \
+ : \
+ : "r" (x)); \
+})
+
+#else
+
+#ifdef CONFIG_CPU_MICROMIPS
+#define rddsp(mask) \
+({ \
+ unsigned int __res; \
+ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " move $1, %0 \n" \
- " # mthi $1, $ac1 \n" \
- " .word 0x00200811 \n" \
+ " # rddsp $1, %x1 \n" \
+ " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
+ " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
+ " move %0, $1 \n" \
" .set pop \n" \
- : \
- : "r" (x)); \
-} while (0)
+ : "=r" (__res) \
+ : "i" (mask)); \
+ __res; \
+})
-#define mthi2(x) \
-do { \
+#define wrdsp(val, mask) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mthi $1, $ac2 \n" \
- " .word 0x00201011 \n" \
+ " # wrdsp $1, %x1 \n" \
+ " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
+ " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (mask)); \
+})
-#define mthi3(x) \
-do { \
+#define _umips_dsp_mfxxx(ins) \
+({ \
+ unsigned long __treg; \
+ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " move $1, %0 \n" \
- " # mthi $1, $ac3 \n" \
- " .word 0x00201811 \n" \
+ " .hword 0x0001 \n" \
+ " .hword %x1 \n" \
+ " move %0, $1 \n" \
" .set pop \n" \
- : \
- : "r" (x)); \
-} while (0)
+ : "=r" (__treg) \
+ : "i" (ins)); \
+ __treg; \
+})
-#define mtlo0(x) \
-do { \
+#define _umips_dsp_mtxxx(val, ins) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mtlo $1, $ac0 \n" \
- " .word 0x00200013 \n" \
+ " .hword 0x0001 \n" \
+ " .hword %x1 \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (ins)); \
+})
-#define mtlo1(x) \
-do { \
+#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
+#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
+
+#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
+#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
+
+#define mflo0() _umips_dsp_mflo(0)
+#define mflo1() _umips_dsp_mflo(1)
+#define mflo2() _umips_dsp_mflo(2)
+#define mflo3() _umips_dsp_mflo(3)
+
+#define mfhi0() _umips_dsp_mfhi(0)
+#define mfhi1() _umips_dsp_mfhi(1)
+#define mfhi2() _umips_dsp_mfhi(2)
+#define mfhi3() _umips_dsp_mfhi(3)
+
+#define mtlo0(x) _umips_dsp_mtlo(x, 0)
+#define mtlo1(x) _umips_dsp_mtlo(x, 1)
+#define mtlo2(x) _umips_dsp_mtlo(x, 2)
+#define mtlo3(x) _umips_dsp_mtlo(x, 3)
+
+#define mthi0(x) _umips_dsp_mthi(x, 0)
+#define mthi1(x) _umips_dsp_mthi(x, 1)
+#define mthi2(x) _umips_dsp_mthi(x, 2)
+#define mthi3(x) _umips_dsp_mthi(x, 3)
+
+#else /* !CONFIG_CPU_MICROMIPS */
+#define rddsp(mask) \
+({ \
+ unsigned int __res; \
+ \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noat \n" \
+ " # rddsp $1, %x1 \n" \
+ " .word 0x7c000cb8 | (%x1 << 16) \n" \
+ " move %0, $1 \n" \
+ " .set pop \n" \
+ : "=r" (__res) \
+ : "i" (mask)); \
+ __res; \
+})
+
+#define wrdsp(val, mask) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mtlo $1, $ac1 \n" \
- " .word 0x00200813 \n" \
+ " # wrdsp $1, %x1 \n" \
+ " .word 0x7c2004f8 | (%x1 << 11) \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (mask)); \
+})
-#define mtlo2(x) \
-do { \
+#define _dsp_mfxxx(ins) \
+({ \
+ unsigned long __treg; \
+ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " move $1, %0 \n" \
- " # mtlo $1, $ac2 \n" \
- " .word 0x00201013 \n" \
+ " .word (0x00000810 | %1) \n" \
+ " move %0, $1 \n" \
" .set pop \n" \
- : \
- : "r" (x)); \
-} while (0)
+ : "=r" (__treg) \
+ : "i" (ins)); \
+ __treg; \
+})
-#define mtlo3(x) \
-do { \
+#define _dsp_mtxxx(val, ins) \
+({ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
- " # mtlo $1, $ac3 \n" \
- " .word 0x00201813 \n" \
+ " .word (0x00200011 | %1) \n" \
" .set pop \n" \
: \
- : "r" (x)); \
-} while (0)
+ : "r" (val), "i" (ins)); \
+})
+
+#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
+#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
+
+#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
+#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
+
+#define mflo0() _dsp_mflo(0)
+#define mflo1() _dsp_mflo(1)
+#define mflo2() _dsp_mflo(2)
+#define mflo3() _dsp_mflo(3)
+
+#define mfhi0() _dsp_mfhi(0)
+#define mfhi1() _dsp_mfhi(1)
+#define mfhi2() _dsp_mfhi(2)
+#define mfhi3() _dsp_mfhi(3)
+
+#define mtlo0(x) _dsp_mtlo(x, 0)
+#define mtlo1(x) _dsp_mtlo(x, 1)
+#define mtlo2(x) _dsp_mtlo(x, 2)
+#define mtlo3(x) _dsp_mtlo(x, 3)
+
+#define mthi0(x) _dsp_mthi(x, 0)
+#define mthi1(x) _dsp_mthi(x, 1)
+#define mthi2(x) _dsp_mthi(x, 2)
+#define mthi3(x) _dsp_mthi(x, 3)
+
+#endif /* CONFIG_CPU_MICROMIPS */
+#endif
/*
* TLB operations.
@@ -1324,11 +1933,11 @@
static inline unsigned int \
set_c0_##name(unsigned int set) \
{ \
- unsigned int res; \
+ unsigned int res, new; \
\
res = read_c0_##name(); \
- res |= set; \
- write_c0_##name(res); \
+ new = res | set; \
+ write_c0_##name(new); \
\
return res; \
} \
@@ -1336,24 +1945,24 @@
static inline unsigned int \
clear_c0_##name(unsigned int clear) \
{ \
- unsigned int res; \
+ unsigned int res, new; \
\
res = read_c0_##name(); \
- res &= ~clear; \
- write_c0_##name(res); \
+ new = res & ~clear; \
+ write_c0_##name(new); \
\
return res; \
} \
\
static inline unsigned int \
-change_c0_##name(unsigned int change, unsigned int new) \
+change_c0_##name(unsigned int change, unsigned int val) \
{ \
- unsigned int res; \
+ unsigned int res, new; \
\
res = read_c0_##name(); \
- res &= ~change; \
- res |= (new & change); \
- write_c0_##name(res); \
+ new = res & ~change; \
+ new |= (val & change); \
+ write_c0_##name(new); \
\
return res; \
}
@@ -1361,9 +1970,27 @@
__BUILD_SET_C0(status)
__BUILD_SET_C0(cause)
__BUILD_SET_C0(config)
+__BUILD_SET_C0(config5)
__BUILD_SET_C0(intcontrol)
__BUILD_SET_C0(intctl)
__BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(pagegrain)
+__BUILD_SET_C0(brcm_config_0)
+__BUILD_SET_C0(brcm_bus_pll)
+__BUILD_SET_C0(brcm_reset)
+__BUILD_SET_C0(brcm_cmt_intr)
+__BUILD_SET_C0(brcm_cmt_ctrl)
+__BUILD_SET_C0(brcm_config)
+__BUILD_SET_C0(brcm_mode)
+
+/*
+ * Return low 10 bits of ebase.
+ * Note that under KVM (MIPSVZ) this returns vcpu id.
+ */
+static inline unsigned int get_ebase_cpunum(void)
+{
+ return read_c0_ebase() & 0x3ff;
+}
#endif /* !__ASSEMBLY__ */
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
new file mode 100644
index 0000000..9e5fa98
--- /dev/null
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 1994 - 2002 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2002 Maciej W. Rozycki
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _ASM_PGTABLE_BITS_H
+#define _ASM_PGTABLE_BITS_H
+
+
+/*
+ * Note that we shift the lower 32bits of each EntryLo[01] entry
+ * 6 bits to the left. That way we can convert the PFN into the
+ * physical address by a single 'and' operation and gain 6 additional
+ * bits for storing information which isn't present in a normal
+ * MIPS page table.
+ *
+ * Similar to the Alpha port, we need to keep track of the ref
+ * and mod bits in software. We have a software "yeah you can read
+ * from this page" bit, and a hardware one which actually lets the
+ * process read from the page. On the same token we have a software
+ * writable bit and the real hardware one which actually lets the
+ * process write to the page, this keeps a mod bit via the hardware
+ * dirty bit.
+ *
+ * Certain revisions of the R4000 and R5000 have a bug where if a
+ * certain sequence occurs in the last 3 instructions of an executable
+ * page, and the following page is not mapped, the cpu can do
+ * unpredictable things. The code (when it is written) to deal with
+ * this problem will be in the update_mmu_cache() code for the r4k.
+ */
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+
+/*
+ * The following bits are implemented by the TLB hardware
+ */
+#define _PAGE_NO_EXEC_SHIFT 0
+#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
+#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
+#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_MASK (7 << _CACHE_SHIFT)
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT (24)
+#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
+
+#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+
+/*
+ * Bits for extended EntryLo0/EntryLo1 registers
+ */
+#define _PFNX_MASK 0xffffff
+
+#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT (0)
+#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
+
+/*
+ * The following bits are implemented by the TLB hardware
+ */
+#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
+#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
+#define _CACHE_MASK _CACHE_UNCACHED
+
+#define _PFN_SHIFT PAGE_SHIFT
+
+#else
+/*
+ * Below are the "Normal" R4K cases
+ */
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT 0
+#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
+/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#else
+#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
+#endif
+#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
+
+#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+/* Huge TLB page */
+#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
+#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
+#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
+#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
+#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
+
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+/* XI - page cannot be executed */
+#ifdef _PAGE_SPLITTING_SHIFT
+#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
+#else
+#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
+#endif
+#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
+
+/* RI - page cannot be read */
+#define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
+#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
+#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
+#endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */
+
+#if defined(_PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
+#elif defined(_PAGE_SPLITTING_SHIFT)
+#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
+#else
+#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
+#endif
+#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
+
+#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_MASK (7 << _CACHE_SHIFT)
+
+#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+
+#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
+
+#ifndef _PAGE_NO_EXEC
+#define _PAGE_NO_EXEC 0
+#endif
+#ifndef _PAGE_NO_READ
+#define _PAGE_NO_READ 0
+#endif
+
+#define _PAGE_SILENT_READ _PAGE_VALID
+#define _PAGE_SILENT_WRITE _PAGE_DIRTY
+
+#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
+
+/*
+ * The final layouts of the PTE bits are:
+ *
+ * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
+ * 32-bit, R1 or earler: CCC D V G M A W R P
+ * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
+ * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
+ */
+
+
+#ifndef __ASSEMBLY__
+/*
+ * pte_to_entrylo converts a page table entry (PTE) into a Mips
+ * entrylo0/1 value.
+ */
+static inline uint64_t pte_to_entrylo(unsigned long pte_val)
+{
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+ if (cpu_has_rixi) {
+ int sa;
+#ifdef CONFIG_32BIT
+ sa = 31 - _PAGE_NO_READ_SHIFT;
+#else
+ sa = 63 - _PAGE_NO_READ_SHIFT;
+#endif
+ /*
+ * C has no way to express that this is a DSRL
+ * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
+ * in the fast path this is done in assembly
+ */
+ return (pte_val >> _PAGE_GLOBAL_SHIFT) |
+ ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
+ }
+#endif
+
+ return pte_val >> _PAGE_GLOBAL_SHIFT;
+}
+#endif
+
+/*
+ * Cache attributes
+ */
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+#define _CACHE_CACHABLE_NONCOHERENT 0
+#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
+
+#elif defined(CONFIG_CPU_SB1)
+
+/* No penalty for being coherent on the SB1, so just
+ use it for "noncoherent" spaces, too. Shouldn't hurt. */
+
+#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
+
+#elif defined(CONFIG_CPU_LOONGSON3)
+
+/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
+
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
+#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
+
+#elif defined(CONFIG_MACH_INGENIC)
+
+/* Ingenic uses the WA bit to achieve write-combine memory writes */
+#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
+
+#endif
+
+#ifndef _CACHE_CACHABLE_NO_WA
+#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_WA
+#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED
+#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_NONCOHERENT
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CE
+#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_COW
+#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CUW
+#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED_ACCELERATED
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
+#endif
+
+#define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
+#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
+ _PFN_MASK | _CACHE_MASK)
+
+#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
index 4deac52..90c0aff 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -1,10 +1,7 @@
-/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
+/*
* Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_POSIX_TYPES_H
#define _ASM_POSIX_TYPES_H
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index ba7f538..02a3b16 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -1,12 +1,10 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994 Waldorf GMBH
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
* Copyright (C) 1996 Paul M. Antoine
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 5659c0c..da051f6 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -1,35 +1,27 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_PTRACE_H
#define _ASM_PTRACE_H
-/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
-#define FPR_BASE 32
-#define PC 64
-#define CAUSE 65
-#define BADVADDR 66
-#define MMHI 67
-#define MMLO 68
-#define FPC_CSR 69
-#define FPC_EIR 70
-#define DSP_BASE 71 /* 3 more hi / lo register pairs */
-#define DSP_CONTROL 77
-#define ACX 78
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/isadep.h>
/*
* This struct defines the way the registers are stored on the stack during a
* system call/exception. As usual the registers k0/k1 aren't being saved.
+ *
+ * If you add a register here, also add it to regoffset_table[] in
+ * arch/mips/kernel/ptrace.c.
*/
struct pt_regs {
#ifdef CONFIG_32BIT
/* Pad bytes for argument save space on the stack. */
- unsigned long pad0[6];
+ unsigned long pad0[8];
#endif
/* Saved main processor registers. */
@@ -45,34 +37,50 @@
unsigned long cp0_badvaddr;
unsigned long cp0_cause;
unsigned long cp0_epc;
-#ifdef CONFIG_MIPS_MT_SMTC
- unsigned long cp0_tcstatus;
-#endif /* CONFIG_MIPS_MT_SMTC */
-} __attribute__ ((aligned (8)));
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ unsigned long long mpl[6]; /* MTM{0-5} */
+ unsigned long long mtp[6]; /* MTP{0-5} */
+#endif
+ unsigned long __last[0];
+} __aligned(8);
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-/* #define PTRACE_GETFPXREGS 18 */
-/* #define PTRACE_SETFPXREGS 19 */
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+ return regs->regs[31];
+}
-#define PTRACE_OLDSETOPTIONS 21
+/*
+ * Don't use asm-generic/ptrace.h it defines FP accessors that don't make
+ * sense on MIPS. We rather want an error if they get invoked.
+ */
-#define PTRACE_GET_THREAD_AREA 25
-#define PTRACE_SET_THREAD_AREA 26
+static inline void instruction_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ regs->cp0_epc = val;
+}
-/* Calls to trace a 64bit program from a 32bit program. */
-#define PTRACE_PEEKTEXT_3264 0xc0
-#define PTRACE_PEEKDATA_3264 0xc1
-#define PTRACE_POKETEXT_3264 0xc2
-#define PTRACE_POKEDATA_3264 0xc3
-#define PTRACE_GET_THREAD_AREA_3264 0xc4
+/* Query offset/name of register from its name/offset */
+extern int regs_query_register_offset(const char *name);
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
-#ifdef __KERNEL__
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs: pt_regs from which register value is gotten.
+ * @offset: offset number of the register.
+ *
+ * regs_get_register returns the value of a register. The @offset is the
+ * offset of the register in struct pt_regs address which specified by @regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+ unsigned int offset)
+{
+ if (unlikely(offset > MAX_REG_OFFSET))
+ return 0;
-#include <asm/isadep.h>
+ return *(unsigned long *)((unsigned long)regs + offset);
+}
/*
* Does the process account for user or for system time?
@@ -82,6 +90,17 @@
#define instruction_pointer(regs) ((regs)->cp0_epc)
#define profile_pc(regs) instruction_pointer(regs)
-#endif
+/* Helpers for working with the user stack pointer */
+
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+ return regs->regs[29];
+}
+
+static inline void user_stack_pointer_set(struct pt_regs *regs,
+ unsigned long val)
+{
+ regs->regs[29] = val;
+}
#endif /* _ASM_PTRACE_H */
diff --git a/arch/mips/include/asm/reboot.h b/arch/mips/include/asm/reboot.h
index 978d206..2a6b724 100644
--- a/arch/mips/include/asm/reboot.h
+++ b/arch/mips/include/asm/reboot.h
@@ -1,10 +1,8 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
* Copyright (C) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_REBOOT_H
#define _ASM_REBOOT_H
diff --git a/arch/mips/include/asm/reg.h b/arch/mips/include/asm/reg.h
index fc6bc0c..af6fbb4 100644
--- a/arch/mips/include/asm/reg.h
+++ b/arch/mips/include/asm/reg.h
@@ -2,12 +2,10 @@
* Various register offset definitions for debuggers, core file
* examiners and whatnot.
*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1995, 1999 by Ralf Baechle
* Copyright (C) 1995, 1999 Silicon Graphics
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_MIPS_REG_H
#define __ASM_MIPS_REG_H
diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
index 2e65cc3..f1efc45 100644
--- a/arch/mips/include/asm/regdef.h
+++ b/arch/mips/include/asm/regdef.h
@@ -1,11 +1,11 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2011 Wind River Systems,
+ * written by Ralf Baechle <ralf@linux-mips.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H
@@ -30,9 +30,13 @@
#define t2 $10
#define t3 $11
#define t4 $12
+#define ta0 $12
#define t5 $13
+#define ta1 $13
#define t6 $14
+#define ta2 $14
#define t7 $15
+#define ta3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
diff --git a/arch/mips/include/asm/sgidefs.h b/arch/mips/include/asm/sgidefs.h
index 67f2658..2a03886 100644
--- a/arch/mips/include/asm/sgidefs.h
+++ b/arch/mips/include/asm/sgidefs.h
@@ -1,11 +1,9 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1996, 1999, 2001 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_SGIDEFS_H
#define __ASM_SGIDEFS_H
diff --git a/arch/mips/include/asm/string.h b/arch/mips/include/asm/string.h
index 579a591..1fbe899 100644
--- a/arch/mips/include/asm/string.h
+++ b/arch/mips/include/asm/string.h
@@ -1,11 +1,9 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
* Copyright (c) 2000 by Silicon Graphics, Inc.
* Copyright (c) 2001 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_STRING_H
#define _ASM_STRING_H
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index d56f73b..e6435cc 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -1,8 +1,4 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994 - 1999 by Ralf Baechle
* Copyright (C) 1996 by Paul M. Antoine
* Copyright (C) 1994 - 1999 by Ralf Baechle
@@ -12,6 +8,8 @@
*
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index aebafdb..627440d 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -1,10 +1,8 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_TYPES_H
#define _ASM_TYPES_H
diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h
index c25a846..eebe06a 100644
--- a/arch/mips/include/asm/unaligned.h
+++ b/arch/mips/include/asm/unaligned.h
@@ -1,9 +1,7 @@
/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_MIPS_UNALIGNED_H
#define _ASM_MIPS_UNALIGNED_H
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index e245614..bf8ff59 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -27,7 +27,7 @@
{
unsigned long conf1, il;
conf1 = read_c0_config1();
- il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
+ il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
return 0;
return 2 << il;
@@ -37,7 +37,7 @@
{
unsigned long conf1, dl;
conf1 = read_c0_config1();
- dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
+ dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
return 0;
return 2 << dl;
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 137d728..14cc2c4 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -54,24 +54,24 @@
mfc0 $1, CP0_CONFIG, 1
/* detect line size */
- srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT
- andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
+ srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
+ andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
move \sz, zero
beqz \line_sz, 10f
li \sz, 2
sllv \line_sz, \sz, \line_sz
/* detect associativity */
- srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT
- andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
+ srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
+ andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
addi \sz, \sz, 1
/* sz *= line_sz */
mul \sz, \sz, \line_sz
/* detect log32(sets) */
- srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT
- andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
+ srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
+ andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
addiu $1, $1, 1
andi $1, $1, 0x7
@@ -103,14 +103,14 @@
li t2, CONFIG_SYS_ICACHE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
#else
- l1_info t2, t8, MIPS_CONF1_IA_SHIFT
+ l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
#ifdef CONFIG_SYS_DCACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t9, CONFIG_SYS_CACHELINE_SIZE
#else
- l1_info t3, t9, MIPS_CONF1_DA_SHIFT
+ l1_info t3, t9, MIPS_CONF1_DA_SHF
#endif
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
diff --git a/arch/mips/mach-au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c
index d6ebe07..9216860 100644
--- a/arch/mips/mach-au1x00/au1x00_eth.c
+++ b/arch/mips/mach-au1x00/au1x00_eth.c
@@ -43,7 +43,7 @@
#include <net.h>
#include <command.h>
#include <asm/io.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#if defined(CONFIG_CMD_MII)
#include <miiphy.h>
@@ -279,7 +279,7 @@
memset(dev, 0, sizeof *dev);
- sprintf(dev->name, "Au1X00 ethernet");
+ strcpy(dev->name, "Au1X00 ethernet");
dev->iobase = 0;
dev->priv = 0;
dev->init = au1x00_init;
diff --git a/arch/mips/mach-au1x00/au1x00_serial.c b/arch/mips/mach-au1x00/au1x00_serial.c
index 0463508..4784504 100644
--- a/arch/mips/mach-au1x00/au1x00_serial.c
+++ b/arch/mips/mach-au1x00/au1x00_serial.c
@@ -11,7 +11,7 @@
#include <config.h>
#include <common.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#include <serial.h>
#include <linux/compiler.h>
diff --git a/arch/mips/mach-au1x00/au1x00_usb_ohci.c b/arch/mips/mach-au1x00/au1x00_usb_ohci.c
index 74bdb77..42484e5 100644
--- a/arch/mips/mach-au1x00/au1x00_usb_ohci.c
+++ b/arch/mips/mach-au1x00/au1x00_usb_ohci.c
@@ -23,7 +23,7 @@
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#include <usb.h>
#include "au1x00_usb_ohci.h"
diff --git a/arch/mips/mach-au1x00/config.mk b/arch/mips/mach-au1x00/config.mk
deleted file mode 100644
index 5c89129..0000000
--- a/arch/mips/mach-au1x00/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2011
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mtune=4kc
diff --git a/arch/mips/include/asm/au1x00.h b/arch/mips/mach-au1x00/include/mach/au1x00.h
similarity index 100%
rename from arch/mips/include/asm/au1x00.h
rename to arch/mips/mach-au1x00/include/mach/au1x00.h
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index f6d5cd3..be7f99c 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -21,6 +21,14 @@
}
#endif /* CONFIG_DISPLAY_CPUINFO */
+#ifdef CONFIG_ALTERA_SYSID
+int checkboard(void)
+{
+ display_sysid();
+ return 0;
+}
+#endif
+
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S
index 54787c5..204d0cd 100644
--- a/arch/nios2/cpu/start.S
+++ b/arch/nios2/cpu/start.S
@@ -106,14 +106,18 @@
stw r0, 4(sp)
mov fp, sp
- /* Allocate and zero GD, update SP */
+ /* Allocate and initialize reserved area, update SP */
mov r4, sp
- movhi r2, %hi(board_init_f_mem@h)
- ori r2, r2, %lo(board_init_f_mem@h)
+ movhi r2, %hi(board_init_f_alloc_reserve@h)
+ ori r2, r2, %lo(board_init_f_alloc_reserve@h)
callr r2
-
- /* Update stack- and frame-pointers */
mov sp, r2
+ mov r4, sp
+ movhi r2, %hi(board_init_f_init_reserve@h)
+ ori r2, r2, %lo(board_init_f_init_reserve@h)
+ callr r2
+
+ /* Update frame-pointer */
mov fp, sp
/* Call board_init_f -- never returns */
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 94eb0d3..54793f0 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -91,6 +91,7 @@
li r5,GD_SIZE /* parameter 3: count */
bl memset
+ li r3, 0 /* parameter 1: bootflag */
bl board_init_f /* run 1st part of board init code (in Flash)*/
/* NOTREACHED - board_init_f() does not return */
#else
@@ -169,6 +170,7 @@
/* r3: IMMR */
bl cpu_init_f /* run low-level CPU init code (in Flash)*/
+ li r3, 0 /* parameter 1: bootflag */
bl board_init_f /* run 1st part of board init code (in Flash)*/
/* NOTREACHED - board_init_f() does not return */
diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c
index 5ba8bed..fff8f2b 100644
--- a/arch/powerpc/cpu/mpc8260/ether_scc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_scc.c
@@ -355,7 +355,7 @@
dev = (struct eth_device *) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
- sprintf(dev->name, "SCC");
+ strcpy(dev->name, "SCC");
dev->init = sec_init;
dev->halt = sec_halt;
dev->send = sec_send;
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index 985a024..2a486e4 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -37,7 +37,7 @@
printf("Memory Error Disable:\n");
printf(" Multiple-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
- printf(" Sinle-Bit Error Disable: %d\n",
+ printf(" Single-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
printf(" Memory Select Error Disable: %d\n\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
@@ -273,7 +273,7 @@
count = simple_strtoul(argv[3], NULL, 16);
if ((u32) addr % 8) {
- printf("Address not alligned on "
+ printf("Address not aligned on "
"double word boundary\n");
return 1;
}
@@ -312,7 +312,7 @@
count = simple_strtoul(argv[3], NULL, 16);
if ((u32) addr % 8) {
- printf("Address not alligned on "
+ printf("Address not aligned on "
"double word boundary\n");
return 1;
}
diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c
index 262ae7f..997aea4 100644
--- a/arch/powerpc/cpu/mpc83xx/law.c
+++ b/arch/powerpc/cpu/mpc83xx/law.c
@@ -1,9 +1,7 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index 30606fb..c7ea94c 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -123,7 +123,7 @@
int i;
if (num_buses > MAX_BUSES) {
- printf("%d PCI buses requsted, %d supported\n",
+ printf("%d PCI buses requested, %d supported\n",
num_buses, MAX_BUSES);
num_buses = MAX_BUSES;
diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c
index 4fae19c..106704d 100644
--- a/arch/powerpc/cpu/mpc83xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc83xx/qe_io.c
@@ -23,7 +23,7 @@
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
- /* Caculate pin location and 2bit mask and dir */
+ /* Calculate pin location and 2bit mask and dir */
pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index f62e1b7..21ab015 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -599,7 +599,7 @@
/*
* Empirically set ~MCAS-to-preamble override for DDR 2.
- * Your milage will vary.
+ * Your mileage will vary.
*/
cpo = 0;
if (spd.mem_type == SPD_MEMTYPE_DDR2) {
@@ -843,7 +843,7 @@
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
- * Use timebase counter, get_timer() is not availabe
+ * Use timebase counter, get_timer() is not available
* at this point of initialization yet.
*/
static __inline__ unsigned long get_tbms (void)
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 1865626..2e91f51 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -170,7 +170,7 @@
tsec1_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TSEC1CM value */
+ /* unknown SCCR_TSEC1CM value */
return -2;
}
#endif
@@ -191,7 +191,7 @@
usbdr_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_USBDRCM value */
+ /* unknown SCCR_USBDRCM value */
return -3;
}
#endif
@@ -212,7 +212,7 @@
tsec2_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TSEC2CM value */
+ /* unknown SCCR_TSEC2CM value */
return -4;
}
#elif defined(CONFIG_MPC8313)
@@ -239,7 +239,7 @@
usbmph_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_USBMPHCM value */
+ /* unknown SCCR_USBMPHCM value */
return -5;
}
@@ -266,7 +266,7 @@
enc_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_ENCCM value */
+ /* unknown SCCR_ENCCM value */
return -7;
}
#endif
@@ -286,7 +286,7 @@
sdhc_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_SDHCCM value */
+ /* unknown SCCR_SDHCCM value */
return -8;
}
#endif
@@ -305,7 +305,7 @@
tdm_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TDMCM value */
+ /* unknown SCCR_TDMCM value */
return -8;
}
#endif
@@ -345,7 +345,7 @@
pciexp1_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_PCIEXP1CM value */
+ /* unknown SCCR_PCIEXP1CM value */
return -9;
}
@@ -363,7 +363,7 @@
pciexp2_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_PCIEXP2CM value */
+ /* unknown SCCR_PCIEXP2CM value */
return -10;
}
#endif
@@ -383,7 +383,7 @@
sata_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_SATACM value */
+ /* unknown SCCR_SATA1CM value */
return -11;
}
#endif
@@ -413,7 +413,7 @@
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
- /* corecnf_tab_index is too high, possibly worng value */
+ /* corecnf_tab_index is too high, possibly wrong value */
return -11;
}
switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
@@ -435,7 +435,7 @@
core_clk = 3 * csb_clk;
break;
default:
- /* unkown core to csb ratio */
+ /* unknown core to csb ratio */
return -13;
}
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 784f4ab..845861e 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -47,7 +47,7 @@
(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
#endif
- /* Enable Time Base & Decrimenter (so we will have udelay()) */
+ /* Enable Time Base & Decrementer (so we will have udelay()) */
im->sysconf.spcr |= SPCR_TBEN;
/* DDR control driver register */
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index 26a65c5..dd99155 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008, 2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index 2e19603..ea4ab3a 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -148,7 +148,7 @@
/* for FEC1 make sure that the name of the interface is the same
as the old one for compatibility reasons */
if (i == 0) {
- sprintf (dev->name, "FEC");
+ strcpy(dev->name, "FEC");
} else {
sprintf (dev->name, "FEC%d",
ether_fcc_info[i].ether_index + 1);
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index 5498440..3474637 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -77,7 +77,7 @@
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
- sprintf(dev->name, "SCC");
+ strcpy(dev->name, "SCC");
dev->iobase = 0;
dev->priv = 0;
dev->init = scc_init;
diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c
index 15cee3f..c35406d 100644
--- a/arch/powerpc/cpu/mpc8xx/video.c
+++ b/arch/powerpc/cpu/mpc8xx/video.c
@@ -981,11 +981,11 @@
U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info);
- sprintf (info, "(C) 2002 DENX Software Engineering");
+ strcpy(info, "(C) 2002 DENX Software Engineering");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
info);
- sprintf (info, " Wolfgang DENK, wd@denx.de");
+ strcpy(info, " Wolfgang DENK, wd@denx.de");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
info);
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index c1fe579..728a351 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -1,9 +1,7 @@
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 3dd0557..137afce 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -762,8 +762,9 @@
bl cpu_init_f /* run low-level CPU init code (from Flash) */
#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
- bl board_init_f_mem
+ bl board_init_f_alloc_reserve
mr r1, r3
+ bl board_init_f_init_reserve
li r0,0
stwu r0, -4(r1)
stwu r0, -4(r1)
@@ -1038,8 +1039,9 @@
bl cpu_init_f /* run low-level CPU init code (from Flash) */
#ifdef CONFIG_SYS_GENERIC_BOARD
mr r3, r1
- bl board_init_f_mem
+ bl board_init_f_alloc_reserve
mr r1, r3
+ bl board_init_f_init_reserve
stwu r0, -4(r1)
stwu r0, -4(r1)
#endif
diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h
index 1164191..9e46e22 100644
--- a/arch/powerpc/include/asm/fsl_dma.h
+++ b/arch/powerpc/include/asm/fsl_dma.h
@@ -3,23 +3,7 @@
*
* Copyright 2006 Freescale Semiconductor, Inc.
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_FSL_DMA_H_
diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h
index d6537fd..cbbc834 100644
--- a/arch/powerpc/include/asm/fsl_i2c.h
+++ b/arch/powerpc/include/asm/fsl_i2c.h
@@ -8,23 +8,7 @@
* and Jeff Brown.
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_FSL_I2C_H_
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 8e1d22a..2a759c8 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _FSL_LAW_H_
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index b0082af..c8da8b2 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -3,23 +3,7 @@
*
* Copyright 2008 Qstreams Networks, Inc.
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_MPC8XXX_SPI_H_
diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c
index b76a731..ab64f6e 100644
--- a/arch/sandbox/cpu/eth-raw-os.c
+++ b/arch/sandbox/cpu/eth-raw-os.c
@@ -76,6 +76,10 @@
printf("Failed to set promiscuous mode: %d %s\n"
"Falling back to the old \"flags\" way...\n",
errno, strerror(errno));
+ if (strlen(ifname) >= IFNAMSIZ) {
+ printf("Interface name %s is too long.\n", ifname);
+ return -EINVAL;
+ }
strncpy(ifr.ifr_name, ifname, IFNAMSIZ);
if (ioctl(priv->sd, SIOCGIFFLAGS, &ifr) < 0) {
printf("Failed to read flags: %d %s\n", errno,
@@ -194,7 +198,8 @@
addr.sin_family = AF_INET;
addr.sin_port = udph->source;
addr.sin_addr.s_addr = iph->saddr;
- retval = bind(priv->local_bind_sd, &addr, sizeof(addr));
+ retval = bind(priv->local_bind_sd, (struct sockaddr *)&addr,
+ sizeof(addr));
if (retval < 0)
printf("Failed to bind: %d %s\n", errno,
strerror(errno));
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index b6d9a15..2e0d320 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -279,6 +279,11 @@
0x38 8>;
};
+ timer {
+ compatible = "sandbox,timer";
+ clock-frequency = <1000000>;
+ };
+
uart0: serial {
compatible = "sandbox,serial";
u-boot,dm-pre-reloc;
diff --git a/arch/sh/include/asm/mmc.h b/arch/sh/include/asm/mmc.h
index 85a5300..c096057 100644
--- a/arch/sh/include/asm/mmc.h
+++ b/arch/sh/include/asm/mmc.h
@@ -4,9 +4,7 @@
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2012 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
+ * SPDX-License-Identifier: GPL-2.0
*
*/
#ifndef _SH_MMC_H_
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 7e7cb61..f07567c 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -242,6 +242,15 @@
help
Additional size of malloc() pool before relocation.
+config FSP_USE_UPD
+ bool
+ depends on HAVE_FSP
+ default y
+ help
+ Most FSPs use UPD data region for some FSP customization. But there
+ are still some FSPs that might not even have UPD. For such FSPs,
+ override this to n in their platform Kconfig files.
+
config ENABLE_MRC_CACHE
bool "Enable MRC cache"
depends on !EFI && !SYS_COREBOOT
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
index a72d615..d49b8d2 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -121,16 +121,23 @@
};
/**
- * Override the FSP's UPD.
+ * Override the FSP's configuration data.
* If the device tree does not specify an integer setting, use the default
* provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
*/
-void update_fsp_upd(struct upd_region *fsp_upd)
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
{
+ struct upd_region *fsp_upd = &config->fsp_upd;
struct memory_down_data *mem;
const void *blob = gd->fdt_blob;
int node;
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
+
fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 9b30451..7299f2c 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -14,12 +14,12 @@
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+ {},
};
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("ValleyView SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("ValleyView SDHCI", mmc_supported);
}
#ifndef CONFIG_EFI_APP
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 56abd8f..1768a26 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -48,7 +48,6 @@
config CPU_SPECIFIC_OPTIONS
def_bool y
select SMM_TSEG
- select HAVE_INTEL_ME
select X86_RAMTEST
config SMM_TSEG_SIZE
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 3e7a907..434dfd6 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -86,8 +86,10 @@
debug("%s: Cannot find GMA node\n", __func__);
return -EINVAL;
}
- ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob,
- gma_node);
+ ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
+ if (ret)
+ return ret;
+ ret = gma_func0_init(dev, blob, gma_node);
if (ret)
return ret;
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 89d4a5e..85a09c64 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -728,8 +728,7 @@
return res;
}
-int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
- const void *blob, int node)
+int gma_func0_init(struct udevice *dev, const void *blob, int node)
{
#ifdef CONFIG_VIDEO
ulong start;
@@ -740,16 +739,16 @@
int ret;
/* IGD needs to be Bus Master */
- reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
+ dm_pci_read_config32(dev, PCI_COMMAND, ®32);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- x86_pci_write_config32(dev, PCI_COMMAND, reg32);
+ dm_pci_write_config32(dev, PCI_COMMAND, reg32);
/* Use write-combining for the graphics memory, 256MB */
- base = pci_read_bar32(hose, dev, 2);
+ base = dm_pci_read_bar32(dev, 2);
mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
mtrr_commit(true);
- gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
+ gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
debug("GT bar %p\n", gtt_bar);
ret = gma_pm_init_pre_vbios(gtt_bar);
if (ret)
@@ -757,8 +756,8 @@
#ifdef CONFIG_VIDEO
start = get_timer(0);
- ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
+ ret = dm_pci_run_vga_bios(dev, int15_handler,
+ PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK);
debug("BIOS ran in %lums\n", get_timer(start));
#endif
/* Post VBIOS init */
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 4334f5b..7917350 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -20,8 +20,11 @@
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm/sipi.h>
+#include <asm/fw_cfg.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
#include <linux/linkage.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -104,7 +107,7 @@
}
}
-static int find_cpu_by_apid_id(int apic_id, struct udevice **devp)
+static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
{
struct udevice *dev;
@@ -137,7 +140,7 @@
enable_lapic();
apic_id = lapicid();
- ret = find_cpu_by_apid_id(apic_id, &dev);
+ ret = find_cpu_by_apic_id(apic_id, &dev);
if (ret) {
debug("Unknown CPU apic_id %x\n", apic_id);
goto done;
@@ -210,7 +213,7 @@
return msr_count;
}
-static int load_sipi_vector(atomic_t **ap_countp)
+static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
{
struct sipi_params_16bit *params16;
struct sipi_params *params;
@@ -239,7 +242,7 @@
params->idt_ptr = (uint32_t)x86_get_idt();
params->stack_size = CONFIG_AP_STACK_SIZE;
- size = params->stack_size * CONFIG_MAX_CPUS;
+ size = params->stack_size * num_cpus;
stack = memalign(size, 4096);
if (!stack)
return -ENOMEM;
@@ -432,7 +435,7 @@
lapic_setup();
apic_id = lapicid();
- ret = find_cpu_by_apid_id(apic_id, devp);
+ ret = find_cpu_by_apic_id(apic_id, devp);
if (ret) {
printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
return ret;
@@ -441,6 +444,69 @@
return 0;
}
+#ifdef CONFIG_QEMU
+static int qemu_cpu_fixup(void)
+{
+ int ret;
+ int cpu_num;
+ int cpu_online;
+ struct udevice *dev, *pdev;
+ struct cpu_platdata *plat;
+ char *cpu;
+
+ /* first we need to find '/cpus' */
+ for (device_find_first_child(dm_root(), &pdev);
+ pdev;
+ device_find_next_child(&pdev)) {
+ if (!strcmp(pdev->name, "cpus"))
+ break;
+ }
+ if (!pdev) {
+ printf("unable to find cpus device\n");
+ return -ENODEV;
+ }
+
+ /* calculate cpus that are already bound */
+ cpu_num = 0;
+ for (uclass_find_first_device(UCLASS_CPU, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ cpu_num++;
+ }
+
+ /* get actual cpu number */
+ cpu_online = qemu_fwcfg_online_cpus();
+ if (cpu_online < 0) {
+ printf("unable to get online cpu number: %d\n", cpu_online);
+ return cpu_online;
+ }
+
+ /* bind addtional cpus */
+ dev = NULL;
+ for (; cpu_num < cpu_online; cpu_num++) {
+ /*
+ * allocate device name here as device_bind_driver() does
+ * not copy device name, 8 bytes are enough for
+ * sizeof("cpu@") + 3 digits cpu number + '\0'
+ */
+ cpu = malloc(8);
+ if (!cpu) {
+ printf("unable to allocate device name\n");
+ return -ENOMEM;
+ }
+ sprintf(cpu, "cpu@%d", cpu_num);
+ ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev);
+ if (ret) {
+ printf("binding cpu@%d failed: %d\n", cpu_num, ret);
+ return ret;
+ }
+ plat = dev_get_parent_platdata(dev);
+ plat->cpu_id = cpu_num;
+ }
+ return 0;
+}
+#endif
+
int mp_init(struct mp_params *p)
{
int num_aps;
@@ -454,6 +520,12 @@
if (ret)
return ret;
+#ifdef CONFIG_QEMU
+ ret = qemu_cpu_fixup();
+ if (ret)
+ return ret;
+#endif
+
ret = init_bsp(&cpu);
if (ret) {
debug("Cannot init boot CPU: err=%d\n", ret);
@@ -483,7 +555,7 @@
mp_info.records = p->flight_plan;
/* Load the SIPI vector */
- ret = load_sipi_vector(&ap_count);
+ ret = load_sipi_vector(&ap_count, num_cpus);
if (ap_count == NULL)
return -1;
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 3f3958a..176ea54 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -7,5 +7,5 @@
ifndef CONFIG_EFI_STUB
obj-y += car.o dram.o
endif
-obj-y += qemu.o
+obj-y += cpu.o fw_cfg.o qemu.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
new file mode 100644
index 0000000..a1b70c6
--- /dev/null
+++ b/arch/x86/cpu/qemu/cpu.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2015, Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cpu.h>
+#include <asm/fw_cfg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size)
+{
+ if (size < CPU_MAX_NAME_LEN)
+ return -ENOSPC;
+
+ cpu_get_name(buf);
+
+ return 0;
+}
+
+static int cpu_qemu_get_count(struct udevice *dev)
+{
+ return qemu_fwcfg_online_cpus();
+}
+
+static const struct cpu_ops cpu_qemu_ops = {
+ .get_desc = cpu_qemu_get_desc,
+ .get_count = cpu_qemu_get_count,
+};
+
+static const struct udevice_id cpu_qemu_ids[] = {
+ { .compatible = "cpu-qemu" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_qemu_drv) = {
+ .name = "cpu_qemu",
+ .id = UCLASS_CPU,
+ .of_match = cpu_qemu_ids,
+ .ops = &cpu_qemu_ops,
+};
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
new file mode 100644
index 0000000..0599214
--- /dev/null
+++ b/arch/x86/cpu/qemu/fw_cfg.c
@@ -0,0 +1,283 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaoebst@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/fw_cfg.h>
+
+static bool fwcfg_present;
+static bool fwcfg_dma_present;
+
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+ uint32_t size, void *address)
+{
+ uint32_t i = 0;
+ uint8_t *data = address;
+
+ /*
+ * writting FW_CFG_INVALID will cause read operation to resume at
+ * last offset, otherwise read will start at offset 0
+ */
+ if (entry != FW_CFG_INVALID)
+ outw(entry, FW_CONTROL_PORT);
+ while (size--)
+ data[i++] = inb(FW_DATA_PORT);
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+ uint32_t size, void *address)
+{
+ struct fw_cfg_dma_access dma;
+
+ dma.length = cpu_to_be32(size);
+ dma.address = cpu_to_be64((uintptr_t)address);
+ dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+ /*
+ * writting FW_CFG_INVALID will cause read operation to resume at
+ * last offset, otherwise read will start at offset 0
+ */
+ if (entry != FW_CFG_INVALID)
+ dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+ barrier();
+
+ debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
+ address, size, be32_to_cpu(dma.control));
+
+ outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
+
+ while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
+ __asm__ __volatile__ ("pause");
+}
+
+static bool qemu_fwcfg_present(void)
+{
+ uint32_t qemu;
+
+ qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+ return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
+}
+
+static bool qemu_fwcfg_dma_present(void)
+{
+ uint8_t dma_enabled;
+
+ qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+ if (dma_enabled & FW_CFG_DMA_ENABLED)
+ return true;
+
+ return false;
+}
+
+static void qemu_fwcfg_read_entry(uint16_t entry,
+ uint32_t length, void *address)
+{
+ if (fwcfg_dma_present)
+ qemu_fwcfg_read_entry_dma(entry, length, address);
+ else
+ qemu_fwcfg_read_entry_pio(entry, length, address);
+}
+
+int qemu_fwcfg_online_cpus(void)
+{
+ uint16_t nb_cpus;
+
+ if (!fwcfg_present)
+ return -ENODEV;
+
+ qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+ return le16_to_cpu(nb_cpus);
+}
+
+/*
+ * This function prepares kernel for zboot. It loads kernel data
+ * to 'load_addr', initrd to 'initrd_addr' and kernel command
+ * line using qemu fw_cfg interface.
+ */
+static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
+{
+ char *data_addr;
+ uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
+
+ qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
+ qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
+
+ if (setup_size == 0 || kernel_size == 0) {
+ printf("warning: no kernel available\n");
+ return -1;
+ }
+
+ data_addr = load_addr;
+ qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
+ le32_to_cpu(setup_size), data_addr);
+ data_addr += le32_to_cpu(setup_size);
+
+ qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
+ le32_to_cpu(kernel_size), data_addr);
+ data_addr += le32_to_cpu(kernel_size);
+
+ data_addr = initrd_addr;
+ qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
+ if (initrd_size == 0) {
+ printf("warning: no initrd available\n");
+ } else {
+ qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
+ le32_to_cpu(initrd_size), data_addr);
+ data_addr += le32_to_cpu(initrd_size);
+ }
+
+ qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
+ if (cmdline_size) {
+ qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
+ le32_to_cpu(cmdline_size), data_addr);
+ /*
+ * if kernel cmdline only contains '\0', (e.g. no -append
+ * when invoking qemu), do not update bootargs
+ */
+ if (*data_addr != '\0') {
+ if (setenv("bootargs", data_addr) < 0)
+ printf("warning: unable to change bootargs\n");
+ }
+ }
+
+ printf("loading kernel to address %p size %x", load_addr,
+ le32_to_cpu(kernel_size));
+ if (initrd_size)
+ printf(" initrd %p size %x\n",
+ initrd_addr,
+ le32_to_cpu(initrd_size));
+ else
+ printf("\n");
+
+ return 0;
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+ int i;
+ uint32_t count;
+ struct fw_cfg_files *files;
+
+ qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+ if (!count)
+ return 0;
+
+ count = be32_to_cpu(count);
+ files = malloc(count * sizeof(struct fw_cfg_file));
+ if (!files)
+ return -ENOMEM;
+
+ files->count = count;
+ qemu_fwcfg_read_entry(FW_CFG_INVALID,
+ count * sizeof(struct fw_cfg_file),
+ files->files);
+
+ for (i = 0; i < files->count; i++)
+ printf("%-56s\n", files->files[i].name);
+ free(files);
+ return 0;
+}
+
+void qemu_fwcfg_init(void)
+{
+ fwcfg_present = qemu_fwcfg_present();
+ if (fwcfg_present)
+ fwcfg_dma_present = qemu_fwcfg_dma_present();
+}
+
+static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ if (qemu_fwcfg_list_firmware() < 0)
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int ret = qemu_fwcfg_online_cpus();
+ if (ret < 0) {
+ printf("QEMU fw_cfg interface not found\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+
+ return 0;
+}
+
+static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ char *env;
+ void *load_addr;
+ void *initrd_addr;
+
+ env = getenv("loadaddr");
+ load_addr = env ?
+ (void *)simple_strtoul(env, NULL, 16) :
+ (void *)CONFIG_LOADADDR;
+
+ env = getenv("ramdiskaddr");
+ initrd_addr = env ?
+ (void *)simple_strtoul(env, NULL, 16) :
+ (void *)CONFIG_RAMDISK_ADDR;
+
+ if (argc == 2) {
+ load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+ initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ } else if (argc == 1) {
+ load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+ }
+
+ return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
+}
+
+static cmd_tbl_t fwcfg_commands[] = {
+ U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
+ U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
+ U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
+};
+
+static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+ cmd_tbl_t *fwcfg_cmd;
+
+ if (!fwcfg_present) {
+ printf("QEMU fw_cfg interface not found\n");
+ return CMD_RET_USAGE;
+ }
+
+ fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
+ ARRAY_SIZE(fwcfg_commands));
+ argc -= 2;
+ argv += 2;
+ if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
+ return CMD_RET_USAGE;
+
+ ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+
+ return cmd_process_error(fwcfg_cmd, ret);
+}
+
+U_BOOT_CMD(
+ qfw, 4, 1, do_qemu_fw,
+ "QEMU firmware interface",
+ "<command>\n"
+ " - list : print firmware(s) currently loaded\n"
+ " - cpus : print online cpu number\n"
+ " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
+)
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 1f93f72..46111c9 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -11,6 +11,7 @@
#include <asm/processor.h>
#include <asm/arch/device.h>
#include <asm/arch/qemu.h>
+#include <asm/fw_cfg.h>
static bool i440fx;
@@ -57,6 +58,8 @@
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
CONFIG_PCIE_ECAM_BASE | BAR_EN);
}
+
+ qemu_fwcfg_init();
}
int arch_cpu_init(void)
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index c2bf497..72c681d 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -19,6 +19,7 @@
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
+ {},
};
/*
@@ -251,17 +252,6 @@
*/
quark_setup_bars();
- /*
- * Initialize PCIe controller
- *
- * Quark SoC holds the PCIe controller in reset following a power on.
- * U-Boot needs to release the PCIe controller from reset. The PCIe
- * controller (D23:F0/F1) will not be visible in PCI configuration
- * space and any access to its PCI configuration registers will cause
- * system hang while it is held in reset.
- */
- quark_pcie_early_init();
-
/* Initialize USB2 PHY */
quark_usb_early_init();
@@ -276,6 +266,22 @@
return 0;
}
+int arch_cpu_init_dm(void)
+{
+ /*
+ * Initialize PCIe controller
+ *
+ * Quark SoC holds the PCIe controller in reset following a power on.
+ * U-Boot needs to release the PCIe controller from reset. The PCIe
+ * controller (D23:F0/F1) will not be visible in PCI configuration
+ * space and any access to its PCI configuration registers will cause
+ * system hang while it is held in reset.
+ */
+ quark_pcie_early_init();
+
+ return 0;
+}
+
int print_cpuinfo(void)
{
post_code(POST_CPU_INFO);
@@ -337,8 +343,7 @@
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("Quark SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("Quark SDHCI", mmc_supported);
}
void cpu_irq_init(void)
diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c
index 78bc966..f83bb5f 100644
--- a/arch/x86/cpu/queensbay/fsp_configs.c
+++ b/arch/x86/cpu/queensbay/fsp_configs.c
@@ -8,13 +8,13 @@
#include <common.h>
#include <asm/fsp/fsp_support.h>
-void update_fsp_upd(struct upd_region *fsp_upd)
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
{
- /* Override any UPD setting if required */
-
- /* Uncomment the line below to enable DEBUG message */
- /* fsp_upd->serial_dbgport_type = 1; */
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
- /* Examples on how to initialize the pointers in UPD region */
- /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */
+ /* Override any UPD setting if required */
}
diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
index 9faf1b9..b76dd7d 100644
--- a/arch/x86/cpu/queensbay/topcliff.c
+++ b/arch/x86/cpu/queensbay/topcliff.c
@@ -11,10 +11,10 @@
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
+ {},
};
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("Topcliff SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("Topcliff SDHCI", mmc_supported);
}
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 5b4ee79..485868f 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -123,8 +123,9 @@
#endif
/* Set up global data */
mov %esp, %eax
- call board_init_f_mem
+ call board_init_f_alloc_reserve
mov %eax, %esp
+ call board_init_f_init_reserve
#ifdef CONFIG_DEBUG_UART
call debug_uart_init
diff --git a/arch/x86/dts/microcode/m12306a2_00000008.dtsi b/arch/x86/dts/microcode/m12306a2_00000008.dtsi
new file mode 100644
index 0000000..6b35c39
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a2_00000008.dtsi
@@ -0,0 +1,554 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x8>;
+intel,date-code = <0x5182011>;
+intel,processor-signature = <0x306a2>;
+intel,checksum = <0xa0e51feb>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x08000000 0x11201805 0xa2060300
+ 0xeb1fe5a0 0x01000000 0x12000000 0xd01f0000
+ 0x00200000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x08000000
+ 0x00000000 0x00000000 0x17051120 0xd1070000
+ 0x01000000 0xa2060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x5665ff94 0x179da7cf 0x1e819fb2 0xb0c24e8e
+ 0x5cb7beb5 0x43af9a6c 0xcb0b4ccc 0x195d8712
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0x72873db0 0x0f41a6d6 0x609f17c3
+ 0x1b1349d0 0xe1950c52 0xdbc8e4fc 0xebc212b5
+ 0x77697371 0x7b156982 0xe71e5ccf 0x78bd638c
+ 0x1b196322 0x8b7ebfbf 0xc2e2588f 0xf139b826
+ 0x98ac3169 0xaa9131b0 0x2d7563f8 0xa1300b39
+ 0x5bd4675f 0x25a4b079 0xe006afb1 0x2bd60828
+ 0x453a0abb 0x3b944679 0x33fd63fd 0xd26ff3c9
+ 0x23c0a581 0xf3beb03a 0xc07109cb 0x2e4c27d9
+ 0xc857a22e 0x470c5b1d 0x5b990a43 0x9f6999e6
+ 0xb5d88f30 0x48c6a95c 0x3756bdc5 0xdc7011d2
+ 0x705d8ef2 0xa657f56c 0xa0b168a4 0x219a3d73
+ 0xb761630a 0x3fa1fb9a 0xe82b74c6 0x037911be
+ 0x5104f10d 0xb4b9e04c 0x4db05893 0x86feb635
+ 0x7391fed4 0x5a690081 0x05797a02 0xce30465e
+ 0x989cdec2 0xa478a8c8 0xa406b02b 0x4ac6e170
+ 0x54ceef3f 0xbbe5e10f 0x7e60e8e1 0x32a015cf
+ 0xaf6491a8 0xef6c1c39 0x38d54b81 0xbca9aa3f
+ 0x7be47871 0x1af28407 0x07fde04d 0x56d82648
+ 0x9f91a24f 0xa71eb768 0x263f176d 0x324196dd
+ 0xa31a37a9 0x3f14178c 0xb3fbb89e 0x18d29b03
+ 0x95c2e349 0xbf559bbe 0xa011c68a 0x0be59ecf
+ 0x644217f4 0x330a8356 0x89f5956e 0xb7103120
+ 0x7d0d2203 0x9d40fc96 0xa9279679 0x81d22306
+ 0x1bc7b5fa 0x679e3a28 0x511a7129 0x81a006a4
+ 0x9791dd09 0xed9dd69a 0xe28904ab 0x90621a2e
+ 0x22efe24d 0x215fd043 0x833f7214 0xf4603491
+ 0x38147d32 0xb4a8fadf 0x306947c3 0xf0998693
+ 0x42fc3ed8 0xe04820c4 0x377e0027 0xd9ed3c92
+ 0xcd166b69 0x1d43b6b7 0x16efc18a 0x5890992a
+ 0xae281f65 0x94b09325 0x6129dee5 0x60ccec89
+ 0xae1b35bb 0xdbe389b3 0xd140a7cf 0xccfe2e86
+ 0x72eff1e3 0x625e92d5 0x7e85420e 0x857f43db
+ 0x22c8784b 0x614e4fff 0x02e87cf8 0x2cb6de43
+ 0xd0bc235d 0xcd19968c 0xcce91f04 0xf36b1f2b
+ 0x8552a638 0x8c3b66fa 0x6fce17b0 0xa1a44384
+ 0x141c8798 0xa8981b4d 0x5d62efa2 0x2b9c0cdd
+ 0x985db4b2 0xbdcb9557 0xd46a70e4 0x90353762
+ 0xdb088ed9 0xcb410eb4 0x7d6bb4b1 0x9b451d22
+ 0xd96dca73 0xec56e8fc 0xa450a765 0x327ca511
+ 0x8d498359 0x1c9ec3a8 0x1986a9a5 0x42c679d5
+ 0xbfbe6164 0xde72b0ba 0xec2c6e93 0x97079604
+ 0x11657c6b 0xf82e6bbe 0x98cddc0b 0xb3168682
+ 0xc22896e3 0x33885964 0xc4791283 0x50553998
+ 0x21976704 0x167c459a 0xb083168c 0x77f08c0f
+ 0x31bbef07 0xff142fda 0xca69c3aa 0x56b2c97c
+ 0x4ba16716 0x7c0688a8 0x8a975497 0x5b7d39f6
+ 0x92815873 0x83bba85a 0x561a8fe1 0xd8b1a419
+ 0x092b76af 0xa708fdcc 0x49986eb3 0xd6ff3b26
+ 0x7bc162a2 0xe1d164fb 0x008705e0 0x825bf6b2
+ 0x5f14e5be 0x69a27ff8 0xd8803cea 0x813c89d2
+ 0xd0558aee 0x88dfdd34 0xb959a0e2 0x948e4309
+ 0xd11e40fa 0x12e739ee 0x453a6b84 0xb85174b9
+ 0x433b0d8c 0x44a8a145 0xe904b21b 0x6a824691
+ 0xf9a191ff 0xe930a249 0x54cc511b 0x76860260
+ 0x268756d3 0x6c535556 0xa89514ea 0x553d3792
+ 0xcb004a7b 0xa2f0234b 0x044d0f13 0x92fa800e
+ 0x5c3ff9d0 0x58dbc14d 0xe305c4da 0xa8af0443
+ 0x88efda5c 0xdeba05ec 0xb128acf7 0x8246648d
+ 0x1ff6d432 0xe919faec 0xd7593779 0xbf4f4ffa
+ 0x26ff3f67 0xe385e75c 0xece43afa 0xd18361ac
+ 0x6f1ff0fd 0x34930c03 0x21c3bb52 0x18508c5a
+ 0x5fac5947 0x93bf46c5 0x0093135f 0x976eee2b
+ 0x0d151deb 0x4b80987a 0x172ce7ac 0x3858dca0
+ 0xf97070db 0x2ac62f48 0xb4a51e8a 0x419c1d35
+ 0xdd9e5157 0xdb21aaea 0xb81f9985 0x19ad9859
+ 0x2074a3fb 0x6f15f27d 0xef3f652b 0x9896582e
+ 0x6787efe9 0xcd8c63a6 0xb94fa052 0xe20b59c5
+ 0x1ae5c0b4 0x46c3b1cc 0xe47ae0a2 0x979ceb01
+ 0x8281c594 0x87d430bc 0x8e6942f1 0x73f40077
+ 0x201415c5 0x46f3e2ea 0x2804b307 0xfa897dc7
+ 0xb79c8456 0x9a7f1b68 0x21f77388 0x0a40a857
+ 0xfa9f096e 0x097fec4b 0xb59a8326 0x25825192
+ 0x68c6b0a0 0xd2757f43 0xd09b408f 0x725ee748
+ 0x4391e4eb 0x8147e982 0x2f153b18 0x6251b500
+ 0x69963d11 0xdd3d67f7 0x67efacc9 0xface6418
+ 0xf4d9b154 0x3e6a6c27 0x95ab29e6 0x75d11283
+ 0xe5377709 0x08831cbb 0x9151f9ee 0x23e3dd5e
+ 0x8b7c87d1 0x71e2550f 0x85943522 0x4486916b
+ 0x8c253c1f 0x197c271c 0xda897e03 0x0ba0b957
+ 0xfefb65f3 0x53e500f3 0xcc52630b 0x008ec579
+ 0x225da363 0xfb129d9f 0x7069493e 0x4657e2d2
+ 0xc1d73c79 0xd292191b 0x26314c0f 0x8a20f248
+ 0x76a162b3 0x5b55dd77 0xa03e9e9b 0xca6b073d
+ 0x813cbaa7 0x7078a94e 0x7d14ed49 0xd86e4ddc
+ 0xe2038ab7 0x75e3ca49 0xd65dfae1 0x340125b8
+ 0x815bb509 0xe7270f14 0xd9f5770c 0x9aca22c5
+ 0x0c48deca 0x3c2ff24f 0x2afdbc05 0x1dafce0a
+ 0x3cbe90b4 0xb37b8faf 0xb83cc372 0xe0468ba6
+ 0x32dca511 0x3c026766 0xceb30b38 0x4cfe6196
+ 0x98bbba31 0xe6322e2c 0x7bcd465a 0x9825fc05
+ 0xe9a469ad 0x94e517ec 0x49318a22 0xbee03c9e
+ 0x85e37df3 0x44358a91 0x00c0490a 0xad1e4041
+ 0xef509388 0xf3194050 0xda5a0de5 0x849d1b1a
+ 0xad5c5ce7 0x624cadd7 0xef00b2c8 0x5c423950
+ 0x8ecbf150 0x98314268 0xe7188ca4 0x4c7ab52e
+ 0xe8bd4c4f 0xdd2360e4 0xf72623e8 0xed45c186
+ 0xf1271f39 0xf128076c 0x499fe644 0xc243460d
+ 0xb399912a 0x1894c1fc 0xcc5a12f5 0xb554e06c
+ 0xf7cf59fd 0xd09ce7ed 0x8f93995d 0xad38e480
+ 0x92cfa3cb 0xef29ce8c 0x1ca8efb2 0x4c390618
+ 0x33e36271 0x752074a0 0xda478d2d 0x10a52d8c
+ 0xd99a36a7 0x50d0db0d 0x728e2f68 0x2eaec798
+ 0x6f5ee097 0x965b0f08 0x0e15ab52 0xadcd83da
+ 0xc2a386bb 0x9ba0071f 0xac242740 0x362668f6
+ 0x01e0adea 0x6d1b2254 0xdbd0fa8d 0x2ef68fe9
+ 0x19742cda 0xa2522cd1 0xad6009c1 0x56374b42
+ 0xf77e7b87 0xf47d5152 0x34ef274c 0x6c8f69db
+ 0xe7c1cd2a 0x60ad1a6c 0x5f11b920 0xe4e903e2
+ 0x6d6d9227 0xcd1f2eb2 0x5c81902d 0x637840a0
+ 0x47f88b3c 0xfcc51034 0xad97af5c 0x14403d02
+ 0x9aae22d0 0x42c50b60 0xdf483d6e 0x5b123f8f
+ 0xb8567830 0x4552282d 0x67ecb54f 0xc5279a68
+ 0x47ca430f 0xf3b581cf 0x70084982 0x04e7a816
+ 0x339e2452 0x0ef1fb04 0x15e018cc 0xd2f83552
+ 0x25be4294 0x643a42a0 0x6ea8207e 0xfd01053a
+ 0xfb25050b 0x8f9d5a9b 0x97e55134 0xb338c705
+ 0xcd1fed07 0x21e5fea1 0xbefd892a 0xe870d3b7
+ 0x696555e9 0x02e80efb 0x91be36e5 0xe98e722a
+ 0x0984101b 0x5b7e344c 0x2c37b88d 0xd153be06
+ 0x58a02ee9 0xb74cde84 0xf2c74516 0x86e3e608
+ 0xf476e86e 0x08053489 0xd8eaa295 0x1042e1aa
+ 0xdc1f613a 0x87af7b7b 0x4bc87db1 0xa005aa8f
+ 0xf85e8566 0xeefb7891 0x6a71cdde 0xc897237c
+ 0xd08778ac 0xdb46f47e 0x87900844 0x19bf15ab
+ 0x0fac1b10 0xbca22485 0xf09a3374 0x222594b1
+ 0xbeac6e17 0x9751d50a 0xe57b78de 0x00c901d4
+ 0x6f8569b0 0x7d778d8e 0x146b7a5e 0x017752fe
+ 0xd2efab56 0x92b6414b 0x796c0dac 0xf2c9ba15
+ 0xffaaf707 0x9e1e0c82 0x22410900 0x703caaf1
+ 0x3ba1fbb8 0x6e330a79 0xe8e3416d 0x19f96d99
+ 0xaad45f95 0x8c23afce 0x79ee1c03 0xf9926e38
+ 0x4552598e 0x2a1ab185 0x9614a74f 0x3ee75de8
+ 0xcfd5e9bf 0xfa7c8c10 0xec727ddd 0x596c2a3a
+ 0x2602a577 0xc8701cc0 0x90670ca5 0x6fd2074a
+ 0x237729e5 0xf94389fe 0x56294aca 0xf0e25fcb
+ 0x92d8755e 0xc9ebab69 0x0056c4bf 0x0802b4bd
+ 0xdca506fb 0x8af71ac1 0x5664ee70 0xc0cc9b12
+ 0x1f2b957c 0x86d75b65 0x0356f061 0xb2a7df2d
+ 0xeebcaed9 0x82240f86 0xd442e66e 0x1c90f7a0
+ 0x340ffd46 0x6665830d 0x92d79070 0x5b84b23b
+ 0x73652140 0x9cc4ba89 0x7a5e361b 0x889de8a4
+ 0xf767445b 0x9c6e7316 0x35e07fc4 0x762678c9
+ 0x8a3e23a1 0x8cf392c6 0xbb9bba49 0xb212b538
+ 0x786d11be 0xc04b989b 0xd286c664 0x9e666e96
+ 0x28987d62 0x5620e31f 0x09284b40 0x2c655487
+ 0xce2d6072 0x1f253329 0xffdc93fe 0x7945e700
+ 0x3e063409 0x6b24a76c 0xdc165d13 0x3f1924ad
+ 0x9a20aec4 0xabbd3741 0xa9242541 0x9c2e780b
+ 0xc8369a55 0x285bee8f 0x34564d35 0x36e55913
+ 0x3e64991f 0x17d9e58c 0x8dd1fb64 0x4d8358d3
+ 0x87a80361 0xa4d61dc4 0xf6dfa482 0x81d24c35
+ 0xaf27cba3 0x5e332395 0xfad6e5a3 0x9cabf33a
+ 0xdcf0921d 0xd893c3a9 0xee8cd5a4 0x4803a801
+ 0x4083023b 0x23272921 0xbe63102a 0x6b62f4fc
+ 0xd1358925 0x4c87470c 0xed7e0c37 0x789f86b5
+ 0x48312d14 0xb50547c3 0x310318b3 0xad0e876b
+ 0x3a2b377d 0xed05829b 0x652ded97 0x316081ba
+ 0xd2d2e21c 0xfc3ca2b5 0x1d480f5b 0x854ae0b9
+ 0x1cb9edae 0x1e8f5f6c 0x0b1cac90 0xd02474f8
+ 0xb6cb0359 0x991a241f 0x961dfdd4 0xf4f8a95b
+ 0xa67e5206 0xbe5efa25 0xdc619c64 0xf350e2b2
+ 0x8244d7a0 0x95ff2840 0x1c8b0751 0x001daf7b
+ 0xb4690af6 0x8ada4365 0xebae8afb 0xa9899cc7
+ 0x651b4e76 0xd42501d5 0xbb5a2d30 0x6b0b4fe7
+ 0xb66d5241 0xe4793b34 0x18e98006 0x2f6217e4
+ 0x9dd33721 0xfdd14fb3 0x03e82ad0 0xd5e2dfaa
+ 0xa248461b 0xa309bef3 0x47472de0 0x0ce6c4c7
+ 0xd9c0bf01 0x5c54a2ca 0x9e55fa97 0x992a4b89
+ 0xc75b9782 0xb02d7a3d 0xd948fab4 0x1b6501d6
+ 0x2674a8ad 0xb1ca0d48 0xcfb534c8 0x729864bb
+ 0x047b2178 0xd88ea657 0x863cf450 0xf0fb6923
+ 0x8399574f 0x2bc03d5c 0xb0f7d334 0xfddf7c72
+ 0x462f1132 0x0640ff38 0x03b426be 0x6af7f1f8
+ 0x474d955c 0xd8174573 0x9975e719 0x4956644c
+ 0x38702613 0xa5ca4cdd 0xc55e5234 0xcd7f3532
+ 0x5696e34e 0xbe5a5c3a 0x1faa53bc 0xba0b5b0a
+ 0xc02b0e33 0xa13f7ec5 0x424cbc5c 0x5aa097cf
+ 0x8e8d1c22 0xab66e427 0x9c1053f7 0x7e62751d
+ 0xd4b094a1 0x57d4766f 0xd023b33a 0xbe020296
+ 0x8102755f 0x6bda667c 0x98f6ea76 0x6deaffb3
+ 0x151caa3c 0x0a1040da 0xf125ebd5 0x929de719
+ 0x6618f307 0x30725caa 0x43a034bf 0x3c576c26
+ 0x77fcf426 0xc360ce49 0x11bc4948 0x2e6dcbf3
+ 0x8b97bf44 0x6eb13c10 0x00cd36ab 0x96b6882c
+ 0x0b312e25 0x534ce45f 0xa6989601 0x6c6c7cdf
+ 0x55fcf9b5 0xea942bc0 0x8252c5ce 0xfd09785c
+ 0x229c3b7d 0xe7129a97 0x9f8db8fb 0xcf692362
+ 0xec8bd49b 0x5b8af7c5 0x020d4843 0xb93cf2c8
+ 0xedcd4fa7 0xf2a9574a 0xa90f2c74 0x5e07cf79
+ 0x0eec3c4c 0x7072b5f5 0x510792d6 0x903a8ca6
+ 0x0952d985 0xa48b5979 0xc6f1cfc7 0xbac813be
+ 0x736163ef 0x6c8e44e9 0x06d2bd0a 0x3fc587d5
+ 0x286e1d65 0x5b6555f6 0x275f8dcc 0x5edb3403
+ 0x412474ed 0x4e41ec00 0xb715c278 0x2777a192
+ 0x40ded494 0x319ec8a6 0xb39c0eef 0xfe4dafca
+ 0xa708b162 0x11d2111f 0xc2806d8e 0x2b631990
+ 0xfc59bb27 0x440667ec 0xc1c43799 0x4aa51bc7
+ 0x08ce990d 0x2425580c 0x9645de2a 0xe7196d6c
+ 0x08d4d524 0xcf4e772a 0x21c18347 0x5bd72d56
+ 0x883bf90b 0xbc262ff0 0x10cfdc55 0x18022197
+ 0x5f0ab36f 0xd689e2b8 0x1c69f462 0x48bba7d6
+ 0x0ab172cd 0xdf060504 0xf8973c1b 0x3206adfe
+ 0xb2cb1735 0xcd9a2237 0xa5fb46de 0x9ffccb44
+ 0xf10d190e 0x587966c0 0xc51151f6 0xadf04413
+ 0x3d06c31b 0x04ee4955 0xc8e0c658 0xc18cf4b3
+ 0xb8819010 0xca4f5220 0xe344f060 0x570b4cda
+ 0x012d0bbc 0xddd75842 0xa6785823 0x03817bbe
+ 0x0a36b9c3 0xa63ce601 0xb400ed89 0x54269ffd
+ 0x932e8525 0xe2e69e40 0xe58b54cc 0x719413e6
+ 0x7d4f6793 0x646d4539 0x697134ac 0x5e748699
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+ 0x8a0518ba 0x013d8f80 0xd32a05ed 0x7d9d8209
+ 0x548cb1d4 0x69457a2c 0x668a0a70 0x8cc2b661
+ 0xb72d4ad3 0x19b388c7 0xb844dd6f 0x4dc39493
+ 0x7e96565c 0x53959236 0x1dd4a349 0xe50914a5
+ 0x319844c0 0xddbb2abd 0x2f126ba4 0xa46c6d63
+ 0xd6829c4d 0x8f178677 0x8ae6291d 0xb5660702
+ >;
diff --git a/arch/x86/dts/microcode/m12306a4_00000007.dtsi b/arch/x86/dts/microcode/m12306a4_00000007.dtsi
new file mode 100644
index 0000000..c39fbd3
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a4_00000007.dtsi
@@ -0,0 +1,618 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9082011>;
+intel,processor-signature = <0x306a4>;
+intel,checksum = <0x7e23e5af>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x07000000 0x11200809 0xa4060300
+ 0xafe5237e 0x01000000 0x12000000 0xd0230000
+ 0x00240000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x07000000
+ 0x00000000 0x00000000 0x07091120 0xd1080000
+ 0x01000000 0xa4060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x9539a0b3 0xc7bb991d 0x308f0f1a 0xb1ba077d
+ 0x8bd7260b 0xd710ad0c 0xf82ee64b 0xe6f11ce1
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0x71f0ab19 0x85635e57 0xfecdeb36
+ 0x7c93f457 0x13e3fb92 0xa512551d 0x6ac10509
+ 0x423fe38d 0x778481b6 0xff413c23 0x534d1d6c
+ 0xade61b9c 0x8cc43e62 0x0a8e5091 0x47382579
+ 0x8ee1d885 0x370915dc 0x8d8274f9 0xff11ba81
+ 0xb0919d7d 0xac434821 0x46d13494 0xe7fcc12e
+ 0x37876ec1 0x67a67b02 0x8d80b952 0xa2bdb26e
+ 0xf19c0c77 0x7b1f5296 0x544fbc2f 0xa8a3b1de
+ 0x8285fcfb 0xcab6dcc3 0x2a63f8de 0xab28edcf
+ 0x86e0e1cf 0xc21e5137 0x04616818 0x3172cc2e
+ 0x4a472e10 0xea8d7f3d 0x7e225494 0x7df2be43
+ 0x8a86b11c 0xf6894a26 0x81b6df9a 0x967c4076
+ 0x8c3e7b47 0xf81709e7 0x8bc622d9 0x4ed8aeae
+ 0x7cc696b5 0x45fb131d 0x77f322fb 0x4801173e
+ 0x056db13d 0x9a64fc3a 0x1508afa7 0xbb357cd3
+ 0xb863aa72 0xe57b932d 0x30892535 0x56a5e167
+ 0x842d402f 0x3113bd4c 0x04016ae3 0x7d81c983
+ 0xdeb79060 0x950e14e6 0xab7833c9 0x297e8abe
+ 0x49252831 0x489acc6f 0x9ed63fab 0x3166416d
+ 0x97319343 0x28ad40d7 0x3fbb9b52 0x203c7460
+ 0xe03bf6a8 0xbe288f65 0x8183b5d7 0x3752814b
+ 0x57405958 0xb4b3ab8d 0x235ba207 0x20bf3240
+ 0x9ea6da77 0xb8f77bf6 0x83d7ce90 0x5575d3de
+ 0x21f46a2d 0xaba56e91 0xb5657416 0x6ed3bce3
+ 0x1cf28b50 0x7e3f8573 0x76ed8028 0x8c785c22
+ 0x5a0fec15 0xbec7ac15 0x3763a0c6 0xd0fcfcdb
+ 0x39581ba2 0x386e0e74 0x4336b4a8 0x4bcc5176
+ 0x314b2da1 0x2ec76c38 0x2a517be5 0x17ce6f78
+ 0x7f124d6b 0xc68ce86a 0xac7d29f3 0x7ea7cbd0
+ 0x053169e4 0x4c0d5e6c 0xe39aa81a 0x083a39bd
+ 0x6d71ce68 0x7c50cc9b 0x10aa72b9 0xdd11c952
+ 0x43bea88d 0x9c1ddab6 0x41b013af 0x1e98de66
+ 0x554b92a3 0x86bac233 0x50fae8f6 0x358742c8
+ 0xa80c50d9 0xdfe9302d 0xc9b4c715 0xdb4b1c66
+ 0x78b7d75b 0xadde8aa8 0x59c09d74 0xa46b87d0
+ 0x548cc5b2 0xf9b8b729 0xa738e8c3 0x1c5a00e1
+ 0xd9c2d59a 0x8d1cc5de 0x05bae2e5 0x0ecdfd2e
+ 0xab3a984e 0xcf53db57 0x3ebc3c88 0x6b60e477
+ 0xa112a3b0 0x827400c9 0x9e7d8495 0xea378c48
+ 0xb19eaf60 0xdfe2da05 0x796b70f0 0x6c595e5c
+ 0xc0600c02 0x9e038536 0xea914072 0xa53e20b8
+ 0x30ab9653 0xb0bb4beb 0xce3d842c 0xb2a5cc91
+ 0xaa6f847f 0xe2aa1414 0xeede8231 0x067d99da
+ 0xa5638b21 0x27ac1f32 0x2231ada1 0x5ca081e4
+ 0x8e30a578 0x21f9f43d 0xc3b5ea88 0x1f1a9d74
+ 0xf7faba90 0x8163a801 0x09b1dcd6 0x3419385a
+ 0xd4ecb2e1 0x33e9df04 0xd5659af7 0x9eea6e2e
+ 0xf6ae859e 0x7c268181 0xaa07ea78 0x892c1c42
+ 0xe66a5fe0 0x9e7f5446 0xf18c42cb 0x49c7296a
+ 0x671484a0 0x3bdf31e2 0xed31d1d1 0xc2e8900b
+ 0x1175996c 0x70a0c04f 0x0394f2c4 0x070d9ca3
+ 0xc67229d1 0xcf29d228 0x4fd61fc4 0x92aa5df4
+ 0xa88afb58 0xb683a2c7 0x16239fe4 0x84bb685b
+ 0xb09cdc69 0x58be548c 0x99f0c940 0xa54bae2d
+ 0x108d7ccf 0x08773f13 0x4ba953c8 0xd290c27c
+ 0x9913f3be 0x8338ab76 0x4a51ca62 0xeb00862c
+ 0x03320962 0xd9bfb225 0x7e90e28e 0x7a86a4ae
+ 0x3a919994 0x91afec57 0xaef1a380 0x30ee8b2c
+ 0xb3dca7a3 0x26bb0fb1 0x36a18ed7 0xe0f1e5bc
+ 0xcd3c7b7b 0x6a3e7546 0x11fbb8ef 0x45800497
+ 0xd18d2714 0x5b2205e1 0x88903c77 0xb04c3c71
+ 0x8f52ca2c 0x3410f445 0x47847239 0x519adc73
+ 0x5e0b948c 0x0d8399f7 0x095d1fd0 0x001a43d5
+ 0xe806d835 0x199ff3d8 0x615fb809 0xa6d8aa7f
+ 0x64f3fdf1 0x6d048b33 0x69967629 0x2036eaf5
+ 0xd2514a6d 0x1719f81a 0x8030c9aa 0x3b1623af
+ 0xc8990859 0xea7d5f87 0x925fddd1 0x3470f55e
+ 0xcc4c6a72 0x4e94dba8 0x51861bfd 0xfc3aa50e
+ 0x65570977 0x615bbb67 0xd1cd8c1c 0xe8c52c28
+ 0xa4b1b599 0xef092f99 0x38c67c4b 0xa48b1fb0
+ 0x34bbdfee 0x162a0308 0x0118df20 0x839c54dd
+ 0x30c28bc9 0xd195aab6 0x14eecbfa 0x5292e262
+ 0xc4d26048 0xc8a7f725 0xb5be922b 0x540c734a
+ 0x12c53607 0x84a598b9 0x7c8418f2 0xe70c82dc
+ 0xa5f9f219 0x7023a821 0x7223e7ef 0xd63c008e
+ 0x29ddf8f4 0x586ac4ea 0x8f734809 0xbf22ff2d
+ 0x1c9b1aef 0x4249d5db 0xc4140c09 0xc927aae3
+ 0xf6c17d0d 0x822bd729 0x1ea56fbc 0x941240f4
+ 0x93a2e220 0x8596eba8 0xb9dc285a 0x58343237
+ 0x649f47b3 0xc214fb8a 0x1aceb84c 0x8a311f8a
+ 0x408e4b98 0xd0401a07 0x99fe7a30 0xdba70218
+ 0x6eabcecb 0x963f4937 0x4c980ab1 0xb1700cb8
+ 0x8762c553 0xed8d7267 0x96ef21bd 0x851452e1
+ 0x0cacc88c 0xb6320bf9 0x2c99e72e 0x98acaadf
+ 0x19c2f27d 0xe6a43a58 0x3b516fcf 0x643305c1
+ 0x28a991c1 0xcf0b9c6f 0x061e8030 0xcf1faf5c
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+ 0xa691d65e 0x824db77d 0xeb09d413 0x9b723ebc
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+ 0x03ab13b7 0x69bf8a84 0xbcb641eb 0x5e89208b
+ 0xc4e51876 0xd58dd9be 0x4ebdf2ac 0x14b79754
+ 0x8cc79438 0xb6d37437 0x6b843097 0x0d11bde4
+ 0x2ef0fd04 0x788b3007 0x6feca051 0xe147b98e
+ 0xa6b9139c 0x9446b26d 0x4920adab 0x7cb94980
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+ 0xd99aa4fc 0xebec0bf5 0xf10d6c52 0x5d97f82c
+ 0x0738353b 0x208e43a6 0xcec8ddb3 0x999847e8
+ 0x10d94541 0x68d5c5a2 0xee34f623 0x86536280
+ 0x4f4e5bc0 0x4e569e0e 0x4c7d1738 0x427d42c3
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+ 0x3303af3f 0x6b058a55 0x3f960abd 0x8d362407
+ 0x33415c6f 0xdbad54d0 0xfd473812 0x9394e4c2
+ 0xac3c803a 0x489113cd 0xeb749070 0x4f813729
+ 0x1f83102e 0xda39d44d 0x2f995892 0x178549e4
+ 0xaa04838d 0xc08bc6f2 0x8e965361 0xe5633efb
+ 0x39927e9f 0x5c7d5014 0x783f5048 0x1c872f55
+ 0xe41ba625 0xeacfc296 0x1e1202d9 0xde9fa0a6
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+ 0x0296fd66 0xcf07611f 0xc27022bd 0x34aaa9c9
+ 0x0ad7b71d 0xb13ec602 0xabd244cc 0x3d3387f0
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+ 0xaee55dfd 0x9a5c2137 0x8d3a85e0 0xf748d910
+ 0xe25eb57f 0xb3dbafe4 0x386b0f20 0x767872b5
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+ 0xec13dbff 0x44ecef5f 0x716a95b1 0x8e2ed760
+ 0xfc1cdbf3 0x363ab021 0x529c749c 0xb8361787
+ 0xb576b8dd 0x05ba72be 0xbd94ddca 0x995823cd
+ 0x4bf10e99 0x6350d475 0x6fab0d5d 0xa3fb7ef0
+ 0xa755d719 0xefeb5c22 0x8369b60e 0xa190b7b2
+ 0xf1ca5eba 0x406fbd8f 0x0b858d59 0x9f4f3a99
+ 0x600706c0 0x8efb77fd 0x8ebd23fe 0xa82b4e93
+ 0x44d50e4f 0x92a2b5a1 0xde8229a0 0xa9128ba4
+ 0x6dc829bb 0x5d63bac1 0x8948d416 0xbb85eebc
+ 0x4b280f18 0x6156e24b 0x5271526e 0x3a550970
+ 0x7212c942 0x09040eba 0x0c199ae0 0x3f41b3f9
+ 0x8d439401 0x83319b2d 0xf3deffb4 0xfd813e2a
+ 0xa8ac6a50 0x72858022 0x5650a6ea 0x8b9e18a3
+ 0x7dc2d48e 0xabf0c35c 0xe9d93f5c 0x228412d4
+ 0xa7b07016 0x0babb01b 0x36faa524 0x3157fe90
+ 0x4cf0fd08 0x1272a76a 0x8e701e54 0xd1ed3067
+ 0xe92bc6ac 0xea2fcc5d 0xdae1a6c7 0x4ec3465f
+ 0x97556141 0xda282893 0x2bdf77f3 0x458abb7b
+ 0x8c98d27e 0x9f2ddc8e 0x4bf66134 0x7ef33d1d
+ 0xe7bfef39 0xa9b37d3e 0x2272b785 0x41bc32d3
+ 0x16790e7a 0xfcd172a9 0x4dcbdb4f 0xadc6cea4
+ 0xe72aab79 0xd3a530cd 0x153171ea 0x60d6122e
+ 0x1b00ebde 0x366861f2 0x6781fc14 0xe6d6189c
+ 0x3b9beebb 0x5c239e07 0x51999573 0x5b900c94
+ 0x52a14fae 0xc7c0bdfb 0x5bebb646 0xaaebca2f
+ 0x360c6d2f 0xc8b43453 0x16ae683d 0x11248d2a
+ 0x08fa3017 0x2bfc636f 0x7360ae91 0x793ad23c
+ 0x7d2bc4bc 0x2d505664 0xee449c94 0xbd0beb6a
+ 0xa9b818e7 0x251354ca 0x119825e5 0xae8b8d2c
+ 0xeea15a2f 0x8b3c47ad 0x2af74ac7 0xaedb8156
+ 0x9b96ee47 0x05034a2f 0x752f8722 0x0f1ee372
+ 0xff55b4b5 0xd12d4ead 0x554c31c4 0xc167849a
+ 0x118d9c61 0x9825a5b5 0xd1941592 0xa21440d6
+ 0x0c8fa874 0xd23ff93c 0xf592f75b 0x6d171131
+ 0xe1cc848b 0xe73fe5cf 0x38677f4a 0xddbbd004
+ 0x6af79754 0xa666b38e 0xf5afba55 0x036b1f0b
+ 0xd55860f2 0x1efdbe6f 0xafc557a4 0x3b24c27d
+ 0x68f319ef 0xf863285e 0x80e88563 0xbe2af6a4
+ 0x81360909 0xcfbaac9a 0xa0a07505 0x8c653634
+ 0xf630bc25 0xdea1640f 0x51445022 0x8bd02194
+ 0x593185c9 0xc23f98f1 0x06b6d384 0x432278ed
+ 0x9c422519 0x0664dc91 0x733e7075 0x9e05a4c2
+ 0x1b014110 0xc4787233 0x4aad488b 0x756f0d47
+ 0x9e29a6df 0xabde4b5d 0x23727bdb 0xf1e3a05d
+ 0xa1f22c40 0x2d290090 0x62d3b212 0xcc247195
+ 0xcd5c84a1 0xf277c61f 0x4f9f213a 0xa69e7391
+ 0xf09f4162 0x44771471 0x6be202f9 0xf27e05bd
+ 0xef27ffc6 0xb94d8b95 0xcc124e11 0x6d22e955
+ 0x8c572ef0 0xc59727f0 0xa68aa858 0x034de5f4
+ 0x242700ae 0xcad4225a 0xb5e792ea 0xf791ab32
+ 0x8f75a863 0xd078bb02 0xec889a62 0xbae59fa8
+ 0xd0e96b37 0x7127e3a9 0x69283a7c 0x7fe26fca
+ 0x3b33f97f 0xef3bfad2 0x0a33c011 0x060e0e58
+ 0x27de1402 0x55f0b8c9 0xf48de31c 0xacbc1c7e
+ 0x228459e6 0x9119a04c 0xeae173ef 0x50347a6c
+ 0x6da1ae72 0xcea1256b 0xc328fe6a 0x85a48b53
+ 0xd8bdb49b 0x857cd611 0x2218a975 0x4893fbe3
+ 0xbd0b7590 0xdc35b430 0x0b37d8a4 0xc1938a77
+ 0x78423be3 0xbb14bb91 0x0c900fe5 0x82037d1e
+ 0x1fc0a8c5 0x5b83cd7a 0xf1a7ff8d 0x36cb83e6
+ >;
diff --git a/arch/x86/dts/microcode/m12306a5_00000007.dtsi b/arch/x86/dts/microcode/m12306a5_00000007.dtsi
new file mode 100644
index 0000000..de50372
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a5_00000007.dtsi
@@ -0,0 +1,618 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9092011>;
+intel,processor-signature = <0x306a5>;
+intel,checksum = <0x8e38731>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x07000000 0x11200909 0xa5060300
+ 0x3187e308 0x01000000 0x12000000 0xd0230000
+ 0x00240000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x07000000
+ 0x00000000 0x00000000 0x08091120 0x71080000
+ 0x01000000 0xa5060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x27649db1 0x904b6445 0x6acff7e8 0xc4ac0631
+ 0x6830ec45 0x3aece98d 0x97bf40c8 0x83b8fef0
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0xb290ba8e 0x6671b099 0x7834fb60
+ 0xe02e439f 0x55712161 0x5dca20ba 0xb62c06df
+ 0x83d86103 0x35cbe438 0xeb7841c9 0xded7ad9a
+ 0xda76b9f2 0xa39233f5 0x11377a10 0x6928a0e1
+ 0xf6164be1 0xab9cb400 0x0ac5e864 0x978e6cdc
+ 0x51d9070c 0x3786d896 0xa6b103d0 0x288c8c83
+ 0x9c644099 0xf9a8a7ad 0xd2a96566 0x2e985d7e
+ 0x3531b0b8 0x3906909b 0xce3878c3 0x30b950a6
+ 0x536b312c 0xb9f07473 0x29366b16 0x7a515f52
+ 0xce7d21ff 0xfe5aef73 0x69b91f78 0xd50b9686
+ 0xa384ac5c 0x6e90981b 0xc37028fa 0xc448c695
+ 0x3c5275e0 0x2ea780c0 0x5fe9aeb5 0xa733e8e1
+ 0x2a04c422 0x68243f2e 0x5311d43b 0x93c27dfc
+ 0xc78b431f 0x9a7bd54e 0x7731f225 0x0f71db56
+ 0xf89a8f8c 0xc5eb2d2a 0x45f973ec 0xbb0635b3
+ 0x5b825acf 0x8744ccef 0xceb1dfca 0x5e5b882f
+ 0x356cfd00 0x68e42c02 0xf0ea6e97 0xa0c1327c
+ 0x5fb06338 0x3e7df893 0x5c3eb0ec 0xac7cc79f
+ 0x3dee3b4b 0x313a2915 0x4002db54 0xe8a96a04
+ 0xb79c367e 0x6d53a3a8 0x9b2720c7 0xf5e7dee4
+ 0x357fc3d7 0xcfc9b54e 0x72f9732e 0x3ccbe991
+ 0xe0486033 0xabeab549 0x032089b2 0xeb1467b3
+ 0x3898e23d 0x4f25f3d4 0xe2f64597 0x3e7facd4
+ 0x455514e6 0x99dea4e4 0xc1201200 0x72d68181
+ 0x25046d7e 0xd3b6ada4 0xd3f358b2 0xb6a0dcf5
+ 0xfbf43626 0xd9cafa7a 0x27ec8d4a 0x84d60c14
+ 0x35e79275 0x413169be 0xbc9847c4 0x0ddcad0f
+ 0x5e098c03 0x03187763 0xed64abff 0x8eaada0c
+ 0xdf378018 0xf394b0fa 0xd4abca64 0x3ad203b6
+ 0x1347cdf9 0xffaf1040 0x078c6baf 0xf2e7d31f
+ 0xdfc334c5 0x061d2348 0x85877503 0x561b6cef
+ 0xfc9aa2ed 0x6057d0b6 0x288df59a 0xda7c47f2
+ 0x727a8584 0x58f74d64 0x8afa48dc 0xf50d3582
+ 0x9f42eec8 0x776d1b6a 0x35f42768 0xbdb7f7bb
+ 0xa239bc05 0x1d26bcce 0x025568ca 0xa2ef8189
+ 0x0054417e 0xf9aff2b5 0x56cc33be 0xed695186
+ 0x58b21d0d 0xea2215c7 0xa565b724 0x2931c422
+ 0xe20b2043 0xa85a082d 0xd7760789 0x58c317cd
+ 0x8c500d70 0xecd22975 0x79542e54 0x790b048f
+ 0xcbbc98fb 0x125b81f9 0xe3e74009 0xc6f4ebc8
+ 0x1e22f4b7 0x0485cac9 0xeb4dc6c9 0xab9076a3
+ 0x9feccd38 0x733e57dc 0xe250d25c 0xf0eb5a8f
+ 0x3db33c3c 0x36c52b3b 0xfe5f92fa 0x0ddc38bf
+ 0x003c6542 0x154abb1d 0x4feb8d85 0x6aae78dd
+ 0x59282b12 0x04fec81c 0xf6f117c7 0x7123b56e
+ 0xd8c53d48 0xff2eeac6 0x09716dee 0x5d24cb13
+ 0xae7c77ef 0xf0213c38 0xd7290320 0xfe3ce627
+ 0x9402607f 0x42ebf5c3 0x4b25a536 0x7167f997
+ 0xe456ed20 0x5a8ed54c 0x8f774e9c 0xa9f1bf83
+ 0x2322ca10 0x3bd6021f 0x2ad0affb 0x0a727ca8
+ 0x228cf77f 0x19f54f70 0x2b7cc811 0xa7193b61
+ 0xcc097688 0x395a8700 0x073e2b6b 0x8e90c718
+ 0x0855f8c6 0x7de3d62b 0x2f582aee 0xeb8667b7
+ 0x6a09f600 0x119a656a 0x7502100c 0x36d51cb0
+ 0xb398a2fe 0xce1a11fe 0xa75b725b 0xf8d69c5a
+ 0x69b6a07f 0x3b5e712b 0x07d647d0 0x80bbe6af
+ 0x80cdefb0 0x03ae17e9 0xda7da860 0x39610997
+ 0x67afea64 0x2d141230 0xd845efe5 0x346b9c22
+ 0xf03d45ce 0xa7f96ffd 0x21bbd7fd 0x035297c4
+ 0x27b88b33 0x8ff80f90 0xa41161cc 0xe38a33d1
+ 0x3d12c73c 0xc81ca705 0x55bb79a9 0xc80037b2
+ 0x2b1b7c7d 0x47ccc91e 0x440370f4 0xb754bfe2
+ 0xf9774b91 0xa8d2fa85 0xb7db3a31 0x102a7131
+ 0x61a200b0 0xea8bf0f9 0x826ca613 0xd3842856
+ 0x27fa5f1b 0xdc6f7aa8 0xc4351ff1 0x13e8d56c
+ 0x3b81f6fb 0x444bb6a0 0xb5fadf26 0xf1e0fd81
+ 0x5c75fa49 0x1e66f533 0x74f83da7 0x749327f5
+ 0x1f41d35d 0xabb10c2c 0x15ff553f 0xbb5ad732
+ 0x904b2bde 0x6eb6c5d7 0xc38cef3e 0x5b62a4c7
+ 0x4c1d0297 0xeb0d88e3 0xe147c6c8 0x726bde4d
+ 0x2cce53ca 0x2e0ad784 0xb5ce9c2e 0x04fa3a1c
+ 0x85fdc1ba 0x87a73107 0x3b1a12db 0x84f7c886
+ 0xbb9c65d3 0xf319fa80 0x8684ad1a 0x8b675754
+ 0xcefe8be8 0x19fb7f42 0x9fbc80de 0xea169c83
+ 0x7aeb705a 0xee25f4ee 0x2f51d222 0xe553b558
+ 0x3bbc3526 0x9b99ac52 0x97b7fa61 0x997ff0fd
+ 0x1d90099d 0x611d8fdf 0x180e1256 0x02436dd8
+ 0xf5c0088b 0x977ce145 0x3e22559a 0xa7434bbc
+ 0xbc0af767 0x61f2adbd 0x6b414aa5 0x23256487
+ 0xcd90a1de 0xa212e85f 0x5a8cbfda 0x901ce98d
+ 0x58784538 0x3a02ddb2 0xd388d8fe 0x18e21114
+ 0xc0ce52ac 0x10eb99b3 0x434dbf0d 0x9fc25de8
+ 0xf4166b7d 0xf520d339 0x80889748 0x36c5122f
+ 0xb0f53d62 0x78f18c2b 0x10b7e0ec 0xb515926e
+ 0x70065726 0xd83b26cb 0x284b191e 0x33c4a3f7
+ 0x97998f96 0xd7458672 0x5e23c14e 0x78a584f9
+ 0xa334e7d1 0x8fcf2992 0x0d7748be 0x3d5e9309
+ 0xa4a46124 0x536108b4 0x57af0c09 0x7ec11806
+ 0xd6b8c03b 0x8618900f 0x6c1c60bb 0x9650af3b
+ 0x83b8c109 0xfbe91320 0x681cc792 0x76fb441f
+ 0x69eace4a 0x66563862 0x86a7a909 0x59815c86
+ 0x604c949f 0xba39a0a4 0x51a1322d 0xaff2a150
+ 0xcba82656 0xc82a79cb 0x9eaa5989 0x5602a25b
+ 0x91917c30 0x46e610b4 0xcb698616 0x571cacc8
+ 0x642c25fd 0xc61a5c96 0x5c0d7b2b 0xb22e2868
+ 0xc5697ac3 0xf69795be 0x9aa5f24f 0xbd4c0815
+ 0x61e63957 0x9a2c3a0c 0x452bd662 0x06ce51e9
+ 0x849769c2 0xe7d1ece0 0x53fbe99a 0x1f8c3976
+ 0x04bbf199 0xa11ebe8b 0xcf862106 0x75f9410f
+ 0x4e573a0f 0xd37b1822 0x45e821b5 0xa72f103e
+ 0x87d41b9a 0x751c1360 0xa3d9bf04 0x38817c3b
+ 0xa1243092 0xeaffa979 0x315d68ea 0xdf4544d4
+ 0xd7bc8ed8 0x4200e14f 0x46cb8d5d 0xe53e695a
+ 0x20fdcc05 0x7bc91fc1 0x21a08c38 0x70377159
+ 0xf000b852 0x010b2051 0x64f27dae 0xa5d40c9f
+ 0x0d2d05db 0x035026b4 0x4dfd9dc6 0xe1ba51b6
+ 0x182921b3 0x3a14fd50 0xfd822b9f 0x1c475677
+ 0xa23ca2d4 0xa4471500 0xb0a3425d 0xc384422e
+ 0x1791bb5e 0x300db057 0x015cdb9b 0xa9254782
+ 0x850a6ed2 0x939270a4 0x6173f301 0x59c678bd
+ 0x8dc33d87 0x8ea24bbe 0x8ffaf807 0xd132392a
+ 0xeb824b6c 0x6dc0e254 0xba2588ea 0x83c5b65b
+ 0xed46fa12 0xc9932295 0x6feb2198 0x74cef43c
+ 0xda34147d 0x338e8acd 0xb6bc8ae3 0x62eeeb57
+ 0xcfd703ec 0x0fa51fb7 0xe6dedfc6 0x06e05089
+ 0x0cd711f6 0x43f73969 0xf43b945e 0x1a63c878
+ 0x366aa911 0x946e06d0 0x8ff0d6f5 0x99e7a128
+ 0x96bf8c82 0x93ffc377 0x9e7d65a8 0x6ef2f639
+ 0x57ac2e72 0xd0d643e2 0x228bc4cd 0x76f8d2a3
+ 0x2c845f50 0x830d3729 0x58d7485d 0x0024caa6
+ 0xac3a5590 0xf18e17a6 0x684dc526 0x6c727c92
+ 0x9abaaa66 0xbd78b8b8 0xac5a3426 0x15c1111b
+ 0x0ee1a7c1 0x665f4531 0x617e891f 0x3285e4d5
+ 0x4cf347dd 0x7b66024a 0x081de006 0x1005600a
+ 0xf124826a 0x2fcb5728 0xc1ddc0de 0xbd7c76d8
+ 0xed4d9ef0 0xaeb0472a 0x2b07a2b0 0x3737ffed
+ 0xd40ef124 0xd1c577fc 0x58076c85 0xb88a0dc0
+ 0x87a5020d 0x062dc1d0 0xb7c62806 0x9aa2c8cf
+ 0xca896ae8 0x40ff25d1 0xe97e160f 0x9f55451b
+ 0x9ba07423 0x6c93a22f 0x55f124cf 0x39ef755e
+ 0x04dac73b 0xa8e8c97c 0xf97d7be2 0xd6200b18
+ 0xf9299b79 0x86abae89 0x661f5e34 0x7317dfda
+ 0x38dff8e7 0x9cea93ba 0x503971a0 0x2837691c
+ 0xbf4eb209 0xa20ce894 0x255c4fff 0x74180a05
+ 0x3c5715da 0x017ec40b 0x6f580634 0xaab316b4
+ 0xcaf9fe94 0x3ca6b65e 0x74015cee 0x4a3ca213
+ 0xa7db4345 0x5a2bb90c 0x2bc01b3e 0x8949fab9
+ 0x548cbb0d 0xf8fda387 0x6e833630 0x786ab073
+ 0xe6fa5787 0x0a659d86 0xe75b17ce 0xf2d07498
+ 0x2ab3ef78 0x74b31ba9 0x623e7ee5 0x1dd7ac63
+ 0xf30617ca 0x34385e0c 0x5cffcadd 0x97bb21b4
+ 0x0aa7cae5 0x679e83e2 0xd15be3a7 0x35a68299
+ 0x7bb0a530 0x33f4793d 0x098b4d9e 0x10123f64
+ 0x39dfe4c1 0xc826ca0c 0xc0f0959a 0x8ab66a8d
+ 0x537e4273 0x93a9c3ac 0xd8d04d5a 0xec511096
+ 0xe14318ca 0x2933223b 0xf89e7a44 0x8fe3680d
+ 0x0ac46c4f 0x87bfbc2e 0xaf4161d7 0x80a1d020
+ 0x91b7b729 0x212b7294 0x6cf14779 0x89faf74a
+ 0x7c5ebbfa 0x6dc0b4a0 0xd3617c72 0x08525097
+ 0x102bb960 0xcfc6c0ca 0x65a604bd 0xd39affdb
+ 0xcab7df61 0x2fb9080d 0x48175e89 0x25133092
+ 0x4a0229e5 0xf88ec53d 0xac24abe7 0xb84598f8
+ 0x1bab71db 0x3c6fa6cd 0x2c4dfd2e 0x22dbc3ef
+ 0x5ac3e6cb 0x66234a29 0x2c26aacb 0xfcb4bb99
+ 0x204c226c 0xc20561ac 0x1e5bffaf 0xaacafe8c
+ 0xf03bfa31 0x0dbe0396 0xd7561d7f 0xb53794dc
+ 0xfe641d5e 0x54e48453 0x611700e5 0x0639b5cf
+ 0x7028a7ef 0x6f3be4b7 0xda5b1755 0xc988199a
+ 0x48497e7a 0x4e3cf3fe 0x99d212e3 0xbd2b89e6
+ 0x98b4ef8a 0xeef8e602 0xef153f89 0x143151c2
+ 0x90557d9b 0xe6a8ef65 0x2e380066 0xe54ac324
+ 0x8e8fc6dc 0xc23f7add 0xaf1fb336 0x3e60c29a
+ 0xe1d56ba3 0x8f654c53 0xf30e755d 0x3b4fa485
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+ 0x718cc961 0x3fa14697 0xd76b4e28 0x7377f49f
+ 0x0e1723b2 0xb2b34ca2 0xe5a713af 0xd0f2eef9
+ 0xd425d842 0x1bf685de 0xfc688084 0xe01d0db4
+ 0x2b33af87 0x523f542e 0x583949fb 0x716d5dcf
+ 0xf2b516b2 0xbbb40cb1 0x28a395af 0x416d8047
+ 0x3add469e 0x2bdda5d5 0x4a0bab2f 0xbb26bb5a
+ 0xa5c4458f 0x87aea38d 0x0d84fbbc 0xc91c5dee
+ 0x226d403f 0xa89803b1 0x362f6461 0xd327ccc3
+ 0x0d3172fe 0x5ee8f57a 0xed862a4e 0xc9e72fca
+ 0xaf37a7bb 0x0e823c62 0xc1f1d185 0x32e22081
+ 0x72427d25 0x9492c7ad 0xaed29771 0xdff35edf
+ 0xbdef0a5e 0x5d9d2f18 0xa0bc1ee9 0x0c397a65
+ 0xc911d530 0x481d294c 0x1a84ce5d 0xf5a5504b
+ 0x22cfca7e 0xaff7e8e9 0x0394d9b1 0x7832305b
+ 0xf853d344 0x89571b4e 0xd2e2bfdd 0x0c72e467
+ 0xb236aea0 0xde6cabce 0xfce515d5 0x0f8c4779
+ 0x3c74d971 0x81b0b3e3 0x2d4c4ecc 0xf4da0ae0
+ 0xa0947a82 0x47609cd3 0x6f81ad8f 0x2bf75b0c
+ 0x46cf40b8 0x344f9edf 0xbad2a5af 0x9e13f884
+ 0x205ea013 0xd54fcb5d 0x20a86658 0x739cfb67
+ 0x7971ea26 0x7841375b 0x649b81e7 0x31ab0179
+ 0xb0730487 0xdba21463 0xa5f6cb07 0xd4f92687
+ 0xca5fbcda 0xc8de464e 0xc7263f7b 0xb93678db
+ 0x1b3ca8dd 0x4636a901 0xd4a16614 0xf96c26e1
+ 0xc58c8da6 0x2965c74a 0x59ff32cd 0x4d77e88e
+ 0x23843ad3 0xa85b9246 0xfd2d5bef 0x1257bf58
+ 0x9c0aa762 0x9ec8ac35 0x77d9bc0a 0xa2bbdee5
+ 0x56d690cf 0x5cdc4461 0x3ef6afed 0xaeb51f80
+ 0x492d6fc9 0xfe4df4b1 0xce23606f 0x40eff82d
+ 0x715eaa41 0xa4e8b2ad 0x19c3e72f 0x9333d4f2
+ 0x9b902cf0 0x70c9bbd4 0x9901f889 0xc342ab6d
+ 0xd36492ae 0x38dc739c 0x0928ffce 0x8d724b2b
+ 0xd5b29bbc 0xa0ce992d 0x8856178b 0x026948bf
+ 0x08809e04 0x541c960d 0x210b71e0 0xf1b9e474
+ 0x85bca8cc 0x90ce42b7 0x6682b7d8 0xe0c50c48
+ 0x25a8075e 0x33dc1ab1 0xf0ff1627 0x89d6d8e9
+ 0x4790ebbb 0x7ba5cfb5 0xe97327bb 0xb06fa0d6
+ 0x7db34b48 0xdf96d115 0xce3fb871 0x03b1557c
+ 0x7eb6d43c 0xceaf3826 0x247e0851 0x840637d2
+ 0x9f979955 0x08f67a6a 0x525d8295 0xdee447c9
+ 0x91ed75bc 0xe4960419 0xb9700051 0x0344b46e
+ 0xbd6b6827 0xa38ab219 0x817e8ba0 0xe86dd20f
+ 0xb9240181 0x4765dd8c 0xc59d8325 0x9b8cfb61
+ 0x6632d86e 0xaf8c2a11 0xbc47dcfb 0x26544374
+ 0xe2beca9d 0xf6355863 0x4291bd11 0x94489a1c
+ 0xc52476f9 0x05fb6fda 0x4d315edb 0xa8e285d0
+ 0x0cd624e3 0x599b9d80 0xd21d8746 0x4d9f3528
+ 0x3a634276 0x9a1f1481 0xa5a015ee 0x6639f7bd
+ 0xd5d20e14 0xe90d52f1 0x3318a40d 0xf3f4f5db
+ 0xb92a7eb5 0x2d730844 0x8282ae9d 0x2f369ced
+ 0x5355d63d 0x984d651b 0x47041c38 0xd65d225b
+ 0xfc2c77a5 0x8822efe6 0x49087974 0xff3c04f0
+ 0xcba80501 0x7e6e1c68 0xa7b7421d 0x6b906771
+ 0x4b2b3b5e 0x233421e5 0x78d0d0d8 0x222dad37
+ 0x875b564f 0x336662fa 0x2bfae345 0x47ff9f91
+ 0xb3e7beee 0x3a7ae071 0x3bd0f29e 0xaee9af97
+ 0x6f0d58fd 0xb5147803 0x32a6ea49 0x70a0a245
+ 0x25b0ace0 0x281e4418 0xfcb5553f 0x1151518f
+ 0x50e67760 0x068c8b22 0xbed7234a 0x4120c5d6
+ 0xec22b6d5 0xc600bef1 0xfd9bd4a2 0xa29451b6
+ 0xcd51bac2 0xc1bd0e26 0xe8432d25 0x2deb06a0
+ 0x9ae54a7a 0x536799e4 0xef4fab62 0x4c9f3e5d
+ 0xeda219fb 0x5947eebd 0x2dec73ae 0x11da15cf
+ 0x94ddc24c 0x2c28b710 0xa5c3620c 0x0722dd36
+ 0xedd98464 0xafa8e23c 0xfd750c04 0x829dc6d6
+ 0x6ee56697 0x2cf2380f 0x3cfa8cd6 0xfa42971f
+ 0x415ad936 0x0b1fea9a 0x65c8b5d2 0x1a5828a6
+ 0x4295092a 0x54596d12 0xa419acef 0xefeddbf9
+ 0xcabda915 0x053abb3c 0xe4b38d10 0x141d9ebc
+ 0xcceb3e75 0xa4fdd9cf 0x9450f718 0xe2a7e7e0
+ 0xbf98f6a0 0x4885a7d5 0x53f871b3 0x0a57e4cf
+ 0x22b36b98 0xd705d611 0x12db0f11 0x546186e1
+ 0x2629257f 0x74587452 0x2659526c 0x2913ca70
+ 0xb3d5b27e 0x1040c827 0x18a192d1 0x2731ba8a
+ 0x5865a15d 0x12b9dce7 0xd0b05fea 0xe35d2de2
+ 0x0f1fc309 0x28df230d 0xcac0338a 0x724f0b25
+ 0x0a36bfeb 0x4c196443 0x392068ee 0x8cc1a2d9
+ 0xbc4f0871 0xea33986e 0x22e90aa1 0x2a43d9e3
+ 0x81214348 0x3745f469 0xaed24012 0x092a728f
+ 0x6b5bb659 0xb46d810d 0xc146cfa5 0xdd3e6954
+ 0x20d6283c 0x0a47baee 0x45aa3873 0xe2c0795b
+ 0xf1cb3519 0x566f951f 0x5e34314d 0xab31c4f1
+ 0x10e0b305 0xfa7d0a3c 0x9adc26fc 0x55fc8af5
+ 0x90314c7d 0xa54954f9 0x27cc0f21 0xbe30da42
+ 0xa04432b0 0x670e176c 0x904a4df4 0x4342618d
+ 0x8b43d3f8 0x086fbc28 0x54954d7a 0x73502d23
+ 0x2ebbaa2e 0x2549f553 0x06946ef5 0x61b621d4
+ 0xafde5d4c 0xbc0faabe 0x0e110c04 0x44ddda52
+ 0xad3883ba 0x1464c595 0x3c5d9f28 0x95573165
+ 0x3e92db93 0x41f19b03 0xb60a4c71 0xf519a623
+ 0x5dc2b562 0xa822e25d 0x09ba6793 0x5e3f5958
+ 0xb80ae32a 0x3f2a8120 0x50cab916 0x8a2664c7
+ 0xe9a0730e 0x74ef9c02 0xbe1b891b 0x8cdeb1cb
+ 0x8f05f87e 0xf4ebaee8 0x12fab9dd 0xfbc8ab3c
+ 0xe6d443b8 0xbaaf9253 0xa4b28356 0x3a105c02
+ 0xb3ceb634 0x26c2d231 0x1e509d45 0xb010dc16
+ 0xbaed93e6 0xffd995a5 0x2274c579 0x081c20f5
+ 0x0e890545 0x9bf20a67 0x534d1668 0xbe0d8a9e
+ 0xe6a3b6a6 0xa19826e8 0x8c369600 0x9b00d171
+ 0xdec22ff7 0x0de50b44 0x4ca2d735 0xe9142307
+ 0xb2d75e8f 0x74018651 0x8a93b3dc 0x679f8926
+ 0xf216f6dc 0xaebc58e5 0x820b6760 0x6e49feb6
+ 0x3ad58a8f 0x62ab576e 0x31829e46 0xb1a2bd35
+ 0xd3db9735 0x248c8e9a 0x8db52fa6 0x8b65b2de
+ 0xebfee08e 0x0d2bdaa1 0xb3d9a282 0xde361f30
+ 0xc121c45c 0x12cdcb27 0x8d7ab875 0xcefac8dc
+ 0x573f8424 0x783fb263 0xbc2d8f2f 0x04f05791
+ 0xa880912a 0x22042163 0xb7891d1d 0x27a3b82a
+ 0x70e35ee9 0xb0b74dc8 0x72b51ef4 0xc074941c
+ 0xeb765569 0x8fba1f5b 0x044aaefa 0xc0db48d0
+ 0x31bed72a 0x7f5ad220 0x132e1da0 0x4cc7e7b5
+ 0x145a80c6 0x39367173 0x0689d163 0x96822f9a
+ >;
diff --git a/arch/x86/dts/microcode/m12306a8_00000010.dtsi b/arch/x86/dts/microcode/m12306a8_00000010.dtsi
new file mode 100644
index 0000000..0672ff1
--- /dev/null
+++ b/arch/x86/dts/microcode/m12306a8_00000010.dtsi
@@ -0,0 +1,682 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x10>;
+intel,date-code = <0x2202012>;
+intel,processor-signature = <0x306a8>;
+intel,checksum = <0xe44a4ef2>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x10000000 0x12202002 0xa8060300
+ 0xf24e4ae4 0x01000000 0x12000000 0xd0270000
+ 0x00280000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x10000000
+ 0x00000000 0x00000000 0x17021220 0xe1090000
+ 0x01000000 0xa8060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x493d401b 0x64106cf1 0x0ffc7f0f 0x9b4b97f6
+ 0xb8fab9c2 0x46353316 0x0247d91b 0x3c36c361
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0xe5ffd18e 0x9c10c032 0xef097758
+ 0x5b44fb3b 0xabbc6973 0xb040312f 0x6267ab0a
+ 0x35ef3655 0x694c0da7 0x6eaf94db 0x293feb5f
+ 0x225a62bf 0x550edd27 0x8e4da670 0x9afcd29b
+ 0x62ad52f1 0xddcdc6fb 0x059e156b 0x9472a491
+ 0x20d8e6fb 0x7041822d 0x5af9c518 0x7e6c342f
+ 0xb113a311 0xdec46650 0x91c8a91c 0x157cde4d
+ 0xec563d5d 0x92470d0e 0x373c488c 0xf18a8f84
+ 0x757fa8ad 0xf8959ce7 0x95e1e3c9 0x47347f30
+ 0xfbd6e4a3 0x18c2f2e2 0xb6c6eb68 0xd2a81838
+ 0xa44964bb 0x36893d55 0x0b411d47 0x5addcf15
+ 0x47584269 0x972c08b3 0x0935b300 0xec7d36a7
+ 0x1c373823 0x487626be 0xacfecd64 0x6688c83c
+ 0xb96f01f9 0x2b6c9719 0x97e955da 0xc4f3b25a
+ 0xfcf12050 0x961bc5be 0x53ebb1e4 0xdc7deaa3
+ 0x3b86819a 0x7c498a21 0x129bc1b6 0x2aa5c324
+ 0x6fb58020 0x0c8e24a8 0xb7c1f0cf 0x37287581
+ 0xf417e311 0x5fd7b8cb 0xe615c56a 0x6a6c6aa7
+ 0x46c97d63 0xcc71adee 0x239b7483 0xea6750f7
+ 0x17bae7c2 0xbf4de5e1 0x6c37a1e0 0x314fc762
+ 0x68bffc94 0x4069875c 0x60d3a593 0x3a923495
+ 0x70f7a899 0xc959db6f 0xfd440374 0x0be4f668
+ 0xc15b74e9 0x9eb15fc7 0x04dc5939 0x1c2d0faf
+ 0x8ca378c9 0x15aaae90 0x2c53e471 0x2ada3977
+ 0x750d6d3b 0xd3e27cdd 0xf63ece4c 0xcbbf9463
+ 0xf0b26aad 0xacc9dc7e 0xcb2131eb 0xc2da14bc
+ 0x01b57719 0x901319e9 0x86b16d25 0x89fe5e27
+ 0xfa3135cd 0x51ebcf8e 0x91b36807 0x6efb87a1
+ 0xbe05489f 0x0461f6c7 0x4f1ddb59 0x007a7e35
+ 0xdde5c360 0xf137a520 0x153d9512 0xebe49940
+ 0xb81727b3 0xdff04ada 0x504811d5 0x6192a2a1
+ 0x418ad287 0x44278f0f 0xc8d70fcc 0x5d5953ca
+ 0xeca4ae03 0xb507f886 0x90a6726b 0xec2c60b6
+ 0xfe003923 0x8cd52bb2 0x87397bbb 0xec98c514
+ 0x28501352 0xd5518d70 0xf3258a19 0x15e4e0f4
+ 0xae272618 0x164ece6f 0x19b5449c 0x2717cf2a
+ 0xffee98cf 0xf18d6c04 0xffb6f744 0x5ed2cb50
+ 0x9421a65a 0x76150be7 0x9689d9eb 0xe6ce395b
+ 0xa5857737 0xe51b5a0f 0x5cc95766 0x365a6f04
+ 0xee8a6d1b 0x219da3e7 0x81004946 0xce4f00f9
+ 0x852eebd0 0x3a39b164 0x96863ddd 0x43b46d69
+ 0x064e138b 0x2ac312a3 0xe7eac082 0xb958803f
+ 0x3138940e 0x4c1d5d99 0x49e9ed02 0xeb3a904e
+ 0x14c2ce82 0x8449493e 0x3cdd6dbf 0xdddb592e
+ 0xaae39fca 0x163c6e65 0xee5a0e52 0xae8c2f8c
+ 0x07fd1416 0x406bd0dc 0x52811c06 0x18316363
+ 0xf954d2eb 0xa8ec83dc 0xe24996e9 0xc92af45f
+ 0x5a73f1d0 0xf5b9948f 0xa6960f5f 0xef3d1266
+ 0x97ac2b43 0x20ce72fe 0x0d774f96 0x29653967
+ 0xca765fe6 0x470ded7f 0x42a9b87e 0x3c9cfb36
+ 0xcd9354db 0x0f2fa889 0xb35e5c71 0xc3da1e0d
+ 0x85f9bfd0 0x1afc94a1 0xf05524d4 0x2b2138ef
+ 0x3c77b905 0x55d26a06 0xcc3a045d 0xad05a556
+ 0xef80f5b7 0x3ca6e8de 0xc40df9e4 0xdc5bdd8a
+ 0xdee9349d 0x258ecbc9 0xa29faf0e 0xf41daab4
+ 0x47af938b 0x6a6a1cf1 0x7a3d2f4a 0x11ede796
+ 0x61f25722 0x6864a35e 0xb4d96fae 0xcdc6a722
+ 0xce64615d 0xef56b252 0x0b89020b 0x2a1ac24c
+ 0x582c3283 0x124f274e 0xf6a58fdc 0x847c262d
+ 0x31517f9b 0x8cd34984 0xc60f7204 0xa94875c1
+ 0x12abf4e6 0xfbdd2b29 0xdb51a1c1 0xb10f9ec9
+ 0xc52b5d3c 0xfa5f75c4 0xb63c6fef 0x8ccd4fe0
+ 0x74b6cc11 0x013babd9 0x0bc30209 0xb1597dcf
+ 0xbda5ac76 0x0371d13a 0x67252505 0xf3081369
+ 0x0d7a4e53 0x25f89a9f 0xd0d9e53f 0xa25d897d
+ 0x822f83e0 0x3008eae6 0x428d3320 0x9890d235
+ 0xfec38910 0x56c87e21 0x7f7f594b 0xdf46866a
+ 0x34a34b40 0x0987267e 0xb47033d1 0x331f5d40
+ 0x935a4ec5 0xab480f95 0x1803d8e7 0x00e2e693
+ 0xab18b053 0x1cf706dd 0x7dda5849 0xb422e2e3
+ 0xba5fd0f3 0x3aee2ce1 0x33b21147 0x5fdec0d7
+ 0xd509d289 0x61187bf4 0xf7687684 0x48edbc90
+ 0x519dcd0b 0x77f026eb 0xc52eb470 0x1d4dd497
+ 0x2fa69c9c 0x8fcfef0d 0x1ed8a0b3 0x9312d199
+ 0x596b55be 0xc8c68e56 0x6aa8dc28 0x3100ec70
+ 0x737bfff7 0x40e51f14 0x695baf1f 0xad786740
+ 0x6278b108 0xcd066fb0 0x74f9d22c 0x9dd7d6f6
+ 0xc9d8d081 0xb82f32ae 0x797beeed 0xa34ce8dd
+ 0xd57ad56e 0xa4bec19f 0xe2cc7268 0xd2b85f64
+ 0x4faf835d 0xda6f3933 0x28397cd3 0x010b5a17
+ 0x6d904bfb 0x26fc2b26 0xdc7b440c 0x4e985f16
+ 0x92fb8abe 0xab8d7b77 0xb906004f 0xb0bdac98
+ 0xee64230b 0xe768ebf6 0x3c96a534 0x4e2aa084
+ 0x5f4c5c4a 0x7bff964e 0x4b4fdde3 0xfc36550b
+ 0xe90220be 0x0056c3d4 0x65599751 0x00c71265
+ 0x83011ea4 0x5bd8113f 0x616bc4ab 0xcdbbfdab
+ 0x187abde6 0xcb0b2059 0x24244c94 0xa05cac8b
+ 0x15e0e4eb 0xe93d7e1e 0xd4016e08 0x8144e1e9
+ 0x1c256625 0x841f4379 0x782edb54 0x6a70674d
+ 0x5de874f9 0x075b423b 0x71a8adc4 0x3f7c5ed1
+ 0xc045ffb0 0xd94e8bbf 0xf7ff3edc 0xb1d3aab5
+ 0x7e78f4b5 0x2e9f0c64 0x17efe45a 0x2a2dd14b
+ 0x9eda4e59 0x2c3689c7 0xe15e5efc 0xf4f11a2f
+ 0x0edb0000 0xf7afa169 0x05558b03 0x1ed6aa69
+ 0x8174d362 0x922814cc 0xcfb1c31c 0xe7cbaba6
+ 0x6aa77d7a 0xea48a37b 0x23b7a2af 0xc2b602da
+ 0x03076aeb 0xef659eb5 0x3c2833e6 0x7dd8521b
+ 0xe80a8ff3 0xe3af24d2 0x6d15f067 0x1c05b90b
+ 0x306e10ea 0xd45b1a99 0xc65a85ac 0xb4ddda13
+ 0x1f2b0bbe 0x716421c1 0x33c2f599 0x0deba688
+ 0xa44de1c2 0x1d33833e 0x3d454600 0x07cdb855
+ 0x57b42914 0x2b3015d8 0xf7893119 0xa754aa11
+ 0xfc8bab1c 0x6aabb3ff 0xeb9a35ba 0x9433e224
+ 0x88225f56 0xb3376d46 0x9203225d 0xfdd591f8
+ 0xb4452f63 0xeccbcf9c 0x60d07a28 0x021f7b69
+ 0xc355e1f5 0xdabc3f4b 0x3a3925e8 0xffc15e96
+ 0xd37cf717 0xbd580830 0x9527f96c 0x91b1119b
+ 0x527baf62 0xdcd8cb14 0xceff6ef8 0x7a64b27d
+ 0xc2bced42 0x62693867 0x171d7869 0x82a502af
+ 0x98c84c3e 0x8a0dd77e 0xcb01c7bb 0x91373992
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+ 0xfd9f88af 0x52b7abff 0x24d20402 0x8dbc246d
+ 0x530452a4 0x4b3714e2 0x91d99e62 0x4be86c83
+ 0xcfa73676 0x814cc9f1 0x49a05ec7 0xea75e853
+ 0xb2fae459 0xe049bf6d 0x95f9d78f 0xb512a76f
+ 0x763fb577 0x124d55c3 0x77080e28 0x89672472
+ 0xce578237 0xcf59d373 0x17a45e2d 0xaad3c482
+ 0x50161024 0xbdc8ade7 0xe9e474e0 0x30db1f08
+ 0x3e595fba 0x0bdae343 0x35fdbe82 0x03192612
+ 0x61ba73cc 0x40f41633 0xa9e1d9ca 0x4ab72299
+ 0x4e9bcaa8 0x87c09d3b 0xd5a2e624 0xfe31b004
+ 0xe080acaf 0xf52cb59f 0x0ed69789 0xbc7aae50
+ 0x097d0dc9 0xb250835a 0xac4d2b62 0x72d775ab
+ 0x29ed99ad 0xda94151f 0xd12aaa71 0xd5c01185
+ 0xb51d0b88 0x0c9d6f2d 0xa48394c5 0xdbb2d57e
+ 0x3ae4d70a 0xd6add3d7 0x4b3dc251 0xafd1be1f
+ 0x90687d0a 0x84a07d85 0xe78eca6b 0x68f66aa8
+ 0x6b64a3ee 0x44a0e334 0x8085791b 0xcc8b9893
+ 0x600ef53c 0xa4cb69a7 0x9d30e312 0x1128eb16
+ 0x4d51ce44 0xdc2d0736 0xdf605b7f 0x854b83b3
+ 0x2ee28ee7 0x16c889b3 0x2550ce0f 0x4cff4ea3
+ 0x42b5a123 0x36773c1c 0xde358d32 0x063a64a5
+ 0xca073150 0x8e55ad6d 0x358ee044 0x1afb0721
+ 0x9a3e1062 0x2bbaa6af 0x29679c34 0x7e073a7d
+ 0x3d8e6461 0x8146fcbe 0xbfc9ae45 0x893e8e8c
+ 0x06f5508c 0xad4dc27a 0x8eb524c1 0x089d6e8a
+ 0x06814420 0xf195e6a0 0x5b9651b1 0x7f55737a
+ 0xf23fb3b1 0x270a10c0 0xc6d1adf6 0x16ef7ed1
+ 0x463492b7 0xa71a7736 0xc8685ff2 0x46eebcad
+ 0x4489c299 0xc46ea5cd 0x0ba37c88 0x8e744be1
+ 0xeb2b315f 0xb3c180ee 0xab833e40 0x2223d8a2
+ 0x4e18ba02 0x830b5559 0xc100c3e5 0x89bca4cd
+ 0x43646b89 0xa94d0f31 0x517daa8f 0xf0633802
+ 0x5f2d9886 0x476f3e91 0x80a20ec9 0x65039697
+ 0x58c021c0 0x06adc086 0x9a7a6ddc 0xedd48be9
+ 0x85383dec 0xb5dea0f4 0xd3b438a3 0x20ef6788
+ 0x0334f429 0xc98fbe55 0x11a38f24 0x020f0f38
+ 0x1d6b4e0f 0x4a99af26 0x1af1d8ca 0x0f61b492
+ 0x2df039b8 0xc8db9dd9 0x978c1442 0xd43af75a
+ 0xaba9101a 0x47778b7d 0x58a36cad 0x2b062567
+ 0x1b68832e 0xe730afd3 0xd083acdf 0x4beec818
+ 0xe15e1338 0x134b9a6c 0xe5a65f74 0x82d64ded
+ 0x552ec9e0 0x36ff5ade 0x0eec84ce 0xdff77b21
+ 0xc2337bb4 0xb038c393 0x8661a487 0x1c47bd8e
+ 0x1664330e 0x4793df4e 0xba9c357b 0xbcecf2a9
+ 0xf8484a42 0x89e26341 0xdea84220 0x7173ff02
+ 0xf091e01b 0xd1789105 0x8876a7a3 0x249398c1
+ 0x35a96528 0x2c9cd555 0x8f9026bb 0x4683dfe7
+ 0x0d322c0e 0xcfdeadc2 0x2e6d657a 0x214f7fad
+ 0x1a6feb96 0x70f24984 0x1e2e919b 0x709a412c
+ 0x7c0820e0 0x4372a2e0 0x3a5fca7b 0x7e098692
+ 0xdcdadb6a 0x83bbaece 0xcf7b4ee7 0xa15deb5c
+ 0x0a5cd850 0x76432692 0xd633e87a 0x3b106b75
+ 0xfb1f675d 0xe2d75d53 0xe525819e 0x639ec794
+ 0xaf3fce1e 0x31f7c2fa 0xf62eed9a 0xa581cbe4
+ 0xdcfd3909 0x683b240a 0x5e609152 0xc011e52c
+ 0xe2b40996 0xd4a9c582 0x34f1b16e 0x67fcc219
+ 0x58554b65 0xee82ffee 0x574d2326 0xb3f72df1
+ 0xe75f740b 0x2081271b 0x21039cca 0x274f5ed9
+ 0xad0e16f1 0x92958ca8 0xbc9af36f 0xde0d81c0
+ 0x8e549069 0x7b675ff9 0xc469cd4a 0x7e9286fe
+ 0xad955974 0x5ddaf59f 0xb444e3c3 0x48c0da41
+ 0x08496091 0x13083e2e 0xd769c0e7 0x12c9c1ac
+ 0xad0eaf72 0x9fb4dc0e 0xba8dec9f 0x92ebb8b1
+ 0x17cfb953 0xbd1aa608 0xa7488be0 0x07020299
+ 0x680e40ed 0x8a1eb384 0x337e047e 0xa68e6188
+ 0x8063eb28 0xc3415333 0x4f744899 0x5c55f1d1
+ 0x8f71d1e3 0x06a02111 0x258ecec0 0x1fd1abc5
+ 0x11c9dd66 0xa4dad7d5 0xedaeecfc 0x1b172d78
+ 0x0f433cf3 0x43c8a18e 0x64af2f5a 0x08374214
+ 0x1bd2211e 0x42d44134 0xd45b7bb7 0x7f981a8e
+ 0x8ca78cbb 0xe2f1e4d6 0xb75e239a 0x43be0647
+ 0x374a4e0e 0xd9bb5925 0xcf158582 0xf229203f
+ 0x70b8fb27 0xa245b677 0xd2d8d526 0x192a9510
+ 0x83a24fed 0xdb806e4b 0xd667de62 0x79119c25
+ 0x28a26484 0x259f5647 0x38653837 0x27084263
+ 0x291da1ad 0x08629d2d 0xc645256f 0x5f5bfebc
+ 0x1c2c0a54 0xd29134d5 0xeb5f441c 0x4dcab922
+ 0x96bd0275 0x9ce7c4f4 0xe74c3ecf 0x4d7ebf4a
+ 0xccb98c87 0x4087533d 0x4bc9d551 0x1dd9b49f
+ 0x470182f8 0xe5764366 0x5cbcbbf4 0xa6e3cd20
+ 0x0beefab1 0x71e29729 0x023e9dad 0xc2816f30
+ 0x8c17209c 0xdb579ef7 0xc2f38a82 0x81219d22
+ 0xa7eaac3a 0x51b5e632 0x8cd23cfa 0x1c14a751
+ 0x4e942e65 0xa8c73ba0 0xf949b6d7 0xe78fc2f1
+ 0x89974a85 0xed5eb057 0xdee39bb6 0xed8c0cab
+ 0x2a526c09 0xcfe60940 0x0d610c5e 0x484899ee
+ 0x92d4c509 0x3d822950 0x9cc21bfc 0x8635bf03
+ 0xaca9721d 0x654adb87 0x9642ee22 0x292d68fd
+ 0x55542325 0x511bb3dd 0x0db3d7c3 0x219cfd34
+ 0x70b944ee 0x9a96b3bf 0x7c7dbd32 0x47237e37
+ 0x93236405 0xc16867a0 0x71709059 0x6a602b3c
+ 0xe0c44204 0x21c010ac 0x1114b7b2 0x994094dc
+ 0x66e3fa66 0x6abb8afa 0x3dd1c246 0x1f35d1c9
+ 0xd6386abd 0x5a1e92ef 0x8214e792 0x1742727b
+ 0xea5724b8 0xd117876c 0x8aeae636 0xc339960b
+ 0xb491151d 0x1cdc17a3 0xe583b556 0x3927556b
+ 0x56b62c9e 0xda90add3 0x2c40a08f 0xb062928a
+ 0x31b7fb6e 0xa031f67e 0x9ac90564 0x09a4791e
+ 0x8675a98c 0x14d0da71 0x9c0e13a7 0xfad7410d
+ 0xdfeab9b3 0x8f798c75 0x2359e65a 0x666c074e
+ 0x79a559b9 0x297a6cfc 0x9b80d725 0x231980df
+ 0x5aba4182 0x6b8930ed 0xfad6b3bf 0x03b99393
+ 0x2ce7b19b 0xd12071f4 0x4c2d0204 0x54833fe9
+ 0x1c8d0433 0xb32e9724 0x02a273bf 0xc52a9d5a
+ 0x62aa1fa6 0x68ca34ad 0x1ac94c91 0x1794e58d
+ 0xa74691ef 0x0e22c1d3 0x66be923f 0x6f6f2c45
+ 0x15ce79a4 0x3b8c9c40 0xa11ff2f9 0xb18f0e8a
+ 0x1e0763e8 0xab472e97 0xd011b9c7 0x7f4cd77e
+ 0x60291b08 0xfc4746db 0x1101cb2f 0x7127e03e
+ 0x39dd8454 0x9e18e09b 0x449c71ba 0xc1106522
+ 0xee38c53b 0x8e30f2a1 0x30a5c398 0xbde9c623
+ 0x49ff1078 0x36360091 0x2b797c99 0x553ff25a
+ 0x063174e2 0xcd5fb064 0xbaf1c003 0xbbbba060
+ 0x9e7bd54a 0xe3bb944c 0xa7586ca4 0x4586a706
+ 0x5bd43e12 0x9139b258 0x5962b23e 0xb20799b8
+ 0x23ef9a21 0xb505a156 0xed51d1ae 0x82dced20
+ 0xfed14015 0xe50de153 0xcb1de201 0x20407156
+ 0x6e6c8c9f 0x4e33f0f7 0xb61006ea 0x81bcca2d
+ 0x8fd94695 0x576fe5c7 0x074ff2db 0xd707ccf4
+ 0x581503ca 0xfcc1c71b 0xcfc21805 0xcb8251a8
+ 0x69361b9a 0x14ec2bbe 0x2df3d3f6 0xa5e66081
+ 0xc5c70b23 0x5dfa028b 0x22338ffa 0x1932168a
+ 0x11a0ed71 0xf676d717 0x823b48d7 0xe02bc37e
+ 0xfc624cac 0x03795ade 0x845ff149 0x5b657ed4
+ 0xbe434a2e 0x8a77afde 0x3615b39d 0xba7200d9
+ 0x674e4541 0x12f91c65 0x694cb6ab 0x22e78146
+ 0x8f574161 0x58f35068 0xce5b6f43 0xd1f0f21e
+ 0x1be73d35 0x7b2dd03f 0x39bf4987 0xd9a00a8b
+ 0xa1285004 0x64b6871e 0xee7377af 0x51d239c8
+ 0x54521a4e 0xcb661f19 0xf26dc3a8 0x8772cda3
+ 0x2c827fa9 0x16f8f76f 0x1de27a89 0xf8b4a070
+ 0xab4243b4 0x2c910203 0x1fc663ad 0xe310c2a3
+ 0x9476000d 0x11e66913 0x346d42a8 0xa513fd81
+ 0xfc260d0f 0x54c7995a 0x228585bc 0xefc0dbb0
+ 0xb9999ca4 0x7dfc9ec2 0x1556bde4 0x2749b83f
+ 0x753da831 0x5d415b40 0x763debe4 0x94a2d4df
+ 0xcc560707 0x08a3de8d 0x7d9f0997 0xe3ff555e
+ 0xa8d05131 0xc75a1e9c 0xd696df91 0x633551a7
+ 0x7ead2980 0x6c8b10b9 0x2b97f758 0xa785048f
+ 0x744ba0dc 0xd350342d 0x6dbdccaa 0x10a5e224
+ 0x0963176d 0x71a4325c 0xa9bfeca5 0x73c90b16
+ 0x5f486277 0xc897525a 0x57a8234d 0x78a73eeb
+ 0x2640604e 0x1598efd9 0x135cb408 0x486bd6d3
+ 0xef98ab1b 0x0ce2744c 0x6a690e5d 0xa65e3af1
+ 0x5263f69d 0x10feb14e 0xd857d93a 0x94d52946
+ 0x52162f56 0xe72a0b7d 0x3e7d7b23 0xdff4b663
+ 0xcbad0105 0x4886da29 0x7d5521d0 0xa37ad7b6
+ 0xe4e79a68 0x4c6cc715 0xbb746a87 0x0a222aa2
+ 0xcff26451 0xe5b51d1a 0xd786658d 0x0edc8ddc
+ 0x95a91b59 0x2b7b0dd7 0xc4003ca8 0xa90e574b
+ 0xf6d1b6c5 0x0880fcaa 0xda31fd31 0x5e2c3099
+ 0x9e9cf801 0x069347b4 0x66215bcc 0x8698d9cc
+ 0x5d53b7ce 0x3b0a3025 0x1765a598 0xba1f4f29
+ 0xa6017b4a 0x1db6bb22 0xd9b63caf 0x531e2601
+ 0x24fa819b 0x8ab091a2 0xbbc3b96a 0x6d4e061d
+ 0x5f7b1d3a 0x13fc2925 0x564b9a06 0x2b0d7a90
+ 0x933a10c7 0x8aa5e38a 0x9b79b254 0x9444c3c2
+ 0xd737212d 0xb13f74df 0x7193f8c1 0xa95f42de
+ 0x6c5a39de 0xf1263eb0 0x57c322ea 0x829cf7e7
+ 0xf8c58a2e 0x2408ad3a 0xe05fa2b7 0xf61c2132
+ 0x47bcb102 0x167f4eb3 0x6a9ca49a 0x03c76439
+ 0x69fa64cc 0xd715eab1 0x26b9ff58 0x65a0d362
+ 0x168ed37e 0x1c4f3752 0xd4e7d4de 0x26e7865d
+ 0xfbd25786 0x347be5c6 0xb610ff32 0xdae6720f
+ 0xa01ff608 0x4a093466 0x7dce182b 0x5eb3cc1e
+ 0xadd542b4 0xfff308b2 0x9deaf2fb 0xd6fa9bac
+ 0x7f1729b9 0x54ae192c 0x85e8e337 0x840f4bfc
+ 0x566993d1 0x2cf2af63 0xf86cbf7b 0xa78e4aa1
+ 0x11806adc 0x06070f3d 0xa833c724 0x3ffef088
+ 0x78febf93 0x2cf6ae38 0x8c4d8867 0x485a2845
+ 0x003a5def 0xe8d1b155 0xcb675ca8 0xcf4fec75
+ 0xb7fe3198 0xf5da0890 0x9f1599b4 0xb952a34e
+ 0x7f1bc151 0x362e7bbb 0x063507a0 0x99c65de4
+ 0xd5130eb3 0x8613ee0b 0xfd6a8987 0x01c85a32
+ 0xed25a8ce 0x3e81114d 0x3f96d0be 0xfa892912
+ 0xb8ab3d94 0x7f10a909 0xe20ebd7e 0x30e900b7
+ 0x05b0d117 0x423ee599 0xd09dacd3 0xd385eb38
+ 0xa0839eee 0x4f29f80c 0x7f253d6e 0xbc757a72
+ 0x326c615c 0x43e0c8e2 0x21771593 0xa71e6072
+ 0xf355b109 0xf2852219 0x9a6ab7b6 0x9b1c39ad
+ 0x2edb942f 0x51234e78 0xbbe44b02 0x9078446a
+ 0x1ff97b31 0xb2967297 0x5f1267ac 0xf8ccd029
+ 0x846ccba2 0x3a2a8297 0xf60c1eae 0xd8b7a467
+ 0x517e2f1f 0xe0087865 0x2a952fa4 0x75963d8d
+ 0x1bb14788 0x1375edb3 0x941303f7 0x6738a9c9
+ 0xe3c99502 0x5f42b5ec 0xb53339d3 0x65896cac
+ 0x8d992623 0x8b09fdc1 0x47e71464 0xc09733fb
+ 0xfa8cfbfe 0x898ba57d 0xe74ca247 0x4fc21f9f
+ 0xc880e39a 0x973ab5b7 0x78628ad6 0x8a6fe2a0
+ 0x92a5a189 0x7a6ff475 0x7db81d10 0x81deea09
+ 0xa4ff44fd 0x056e383e 0x7cd47b4c 0x2182a401
+ 0xd0c4ce01 0xeb313665 0x8bbb4e07 0xbb4d4a64
+ 0x15fe41cb 0x53a267ce 0x8ee4ae7c 0x01678630
+ 0xda477daf 0x7ee74db4 0xf6e9228b 0x06c57aef
+ 0x5b9c8e80 0x1e05611b 0x26682707 0x7111591a
+ 0x7646cb3b 0x20f2d117 0x4dae44a9 0x395871da
+ 0x54e6172c 0x4ab90f71 0x65209536 0xb3b57c85
+ 0x11d10b0b 0xc9e50256 0x47521f5a 0x4416012f
+ 0x6d8042b6 0x454542fa 0x77f0fea3 0xce983a27
+ 0x40f74a4e 0xabc2d476 0xcd6a647d 0xca633336
+ 0xeb7fa467 0x4b14425f 0xd7abae15 0xb9652306
+ 0x990b3a98 0x03e6f53a 0xa5f3ec3c 0xb40c953f
+ 0x5cd8470a 0xbf93da01 0x89a52e28 0x5984bd42
+ 0xe9d93e95 0xa3b67bbf 0x099ff7cf 0x07b80086
+ 0x20cdf1cb 0xcfbbdb2e 0xeb0da53d 0x33b82f36
+ 0x28fb9aca 0x013bb5b7 0xcfbfefea 0x7f4400d1
+ 0xd3ad108f 0xe32556f3 0xa9e77e41 0x92955338
+ 0x3d102663 0x63bde93f 0xbbb464c4 0xcc1ff27f
+ 0x7968d83b 0xca32b52d 0x1d4102ff 0x84cfd695
+ 0x8303a6d3 0xc6f8ba69 0xdd78d4ef 0x98b195af
+ 0x50f92a15 0x2066c503 0x61281597 0x5d0197b7
+ 0x59e6f0be 0x02423dd6 0x9b4d27af 0xb2a0755d
+ 0x72f2eb4e 0xdb5aa819 0xddb42e82 0x9688712a
+ 0xb430e384 0x6484e439 0x44f68d17 0x195c6382
+ 0xddee2db1 0xd9af2e18 0x7fbd30d6 0x2ac223db
+ 0x0d3bd809 0xec982530 0x1a41d13f 0xef2849a8
+ 0x9c233021 0xc074a29c 0xe7b8f28f 0xd0adf47f
+ 0x23cdf70d 0x6795e85d 0x1168d6ea 0x3c8bb4c7
+ 0xad1d00c9 0xf3eeb5d0 0x2f950982 0x9fbbde57
+ 0xdc733a93 0xb23e2beb 0x7dbb34af 0xf1323cff
+ 0xf6c9a9bc 0xf69900a6 0x9447ab0b 0xf03e55fa
+ 0x2816479b 0x487e507e 0x494087fb 0x0601d1ef
+ 0x27c86510 0x6a14691a 0xb78886de 0xe89e8c84
+ 0xf2cd073c 0x09144b70 0xa82227a5 0x82f88828
+ 0x71f7e10a 0x6c2b46b6 0xf813fe7d 0xf76d2602
+ 0x044d5543 0x9e1b6a76 0x967ad7b5 0xe803b0a7
+ 0x01e03dd9 0x6d5c94d8 0x112357c8 0x8e0bfe12
+ 0xcc8c7461 0xfbc1c562 0x9838886c 0xa16c46a7
+ 0x020631ad 0x70fb29ff 0x5f5f1795 0x07a762e8
+ 0x3467aa2b 0xd396d1d7 0xa12aaf4c 0xd3c13b6b
+ 0xf158d7dd 0x17b1317a 0xd847a91d 0x7612ab8e
+ >;
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 8a06229..9086b46 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -32,17 +32,10 @@
cpu@0 {
device_type = "cpu";
- compatible = "cpu-x86";
+ compatible = "cpu-qemu";
reg = <0>;
intel,apic-id = <0>;
};
-
- cpu@1 {
- device_type = "cpu";
- compatible = "cpu-x86";
- reg = <1>;
- intel,apic-id = <1>;
- };
};
tsc-timer {
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 0b685c8..145e811 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -43,17 +43,10 @@
cpu@0 {
device_type = "cpu";
- compatible = "cpu-x86";
+ compatible = "cpu-qemu";
reg = <0>;
intel,apic-id = <0>;
};
-
- cpu@1 {
- device_type = "cpu";
- compatible = "cpu-x86";
- reg = <1>;
- intel,apic-id = <1>;
- };
};
tsc-timer {
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
new file mode 100644
index 0000000..e539890
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct upd_region fsp_upd;
+};
+
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
+};
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-coreboot/timestamp.h b/arch/x86/include/asm/arch-coreboot/timestamp.h
index fcfc1d5..0cd7a99 100644
--- a/arch/x86/include/asm/arch-coreboot/timestamp.h
+++ b/arch/x86/include/asm/arch-coreboot/timestamp.h
@@ -3,18 +3,7 @@
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __COREBOOT_TIMESTAMP_H__
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index 7786493..fcdf6e2 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -12,8 +12,7 @@
void bd82x6x_pci_init(pci_dev_t dev);
void bd82x6x_usb_ehci_init(pci_dev_t dev);
void bd82x6x_usb_xhci_init(pci_dev_t dev);
-int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
- const void *blob, int node);
+int gma_func0_init(struct udevice *dev, const void *blob, int node);
int bd82x6x_init(void);
/**
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index 21df083..31437c8 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -105,6 +105,8 @@
#define GPIO_ROUT 0xb8
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */
+#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */
#define LPC_EN 0x82 /* LPC IF Enables Register */
#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
@@ -121,6 +123,14 @@
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
+#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */
+#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */
+#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */
+#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */
+#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */
+#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */
+#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */
+#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */
/* PCI Configuration Space (D31:F1): IDE */
#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h
new file mode 100644
index 0000000..e539890
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct upd_region fsp_upd;
+};
+
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
+};
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h
index 2d34d13..afafb30 100644
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@@ -11,6 +11,16 @@
#include <linux/linkage.h>
/*
+ * FSP common configuration structure.
+ * This needs to be included in the platform-specific struct fsp_config_data.
+ */
+struct fsp_cfg_common {
+ struct fsp_header *fsp_hdr;
+ u32 stack_top;
+ u32 boot_mode;
+};
+
+/*
* FspInit continuation function prototype.
* Control will be returned to this callback function after FspInit API call.
*/
@@ -30,7 +40,7 @@
* Stack top pointer used by the bootloader. The new stack frame will be
* set up at this location after FspInit API call.
*/
- u32 *stack_top;
+ u32 stack_top;
u32 boot_mode; /* Current system boot mode */
void *upd_data; /* User platform configuraiton data region */
u32 reserved[7]; /* Reserved */
diff --git a/arch/x86/include/asm/fsp/fsp_platform.h b/arch/x86/include/asm/fsp/fsp_platform.h
deleted file mode 100644
index 61286ce..0000000
--- a/arch/x86/include/asm/fsp/fsp_platform.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: Intel
- */
-
-#ifndef __FSP_PLATFORM_H__
-#define __FSP_PLATFORM_H__
-
-struct fspinit_rtbuf {
- struct common_buf common; /* FSP common runtime data structure */
-};
-
-#endif
diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
index 7317dda..61d811f 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -13,16 +13,10 @@
#include "fsp_ffs.h"
#include "fsp_api.h"
#include "fsp_hob.h"
-#include "fsp_platform.h"
#include "fsp_infoheader.h"
#include "fsp_bootmode.h"
#include <asm/arch/fsp/fsp_vpd.h>
-
-struct shared_data {
- struct fsp_header *fsp_hdr;
- u32 *stack_top;
- struct upd_region fsp_upd;
-};
+#include <asm/arch/fsp/fsp_configs.h>
#define FSP_LOWMEM_BASE 0x100000UL
#define FSP_HIGHMEM_BASE 0x100000000ULL
@@ -49,14 +43,12 @@
/**
* FSP Continuation function
*
- * @shared_data: Shared data base before stack migration
* @status: Always 0
* @hob_list: HOB list pointer
*
* @retval: Never returns
*/
-void fsp_continue(struct shared_data *shared_data, u32 status,
- void *hob_list);
+void fsp_continue(u32 status, void *hob_list);
/**
* Find FSP header offset in FSP image
@@ -199,13 +191,15 @@
void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
/**
- * This function overrides the default configurations in the UPD data region.
+ * This function overrides the default configurations of FSP.
*
- * @fsp_upd: A pointer to the upd_region data strcture
+ * @config: A pointer to the FSP configuration data structure
+ * @rt_buf: A pointer to the FSP runtime buffer data structure
*
* @return: None
*/
-void update_fsp_upd(struct upd_region *fsp_upd);
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf);
/**
* fsp_init_phase_pci() - Tell the FSP that we have completed PCI init
diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h
new file mode 100644
index 0000000..fb110fa
--- /dev/null
+++ b/arch/x86/include/asm/fw_cfg.h
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FW_CFG__
+#define __FW_CFG__
+
+#define FW_CONTROL_PORT 0x510
+#define FW_DATA_PORT 0x511
+#define FW_DMA_PORT_LOW 0x514
+#define FW_DMA_PORT_HIGH 0x518
+
+enum qemu_fwcfg_items {
+ FW_CFG_SIGNATURE = 0x00,
+ FW_CFG_ID = 0x01,
+ FW_CFG_UUID = 0x02,
+ FW_CFG_RAM_SIZE = 0x03,
+ FW_CFG_NOGRAPHIC = 0x04,
+ FW_CFG_NB_CPUS = 0x05,
+ FW_CFG_MACHINE_ID = 0x06,
+ FW_CFG_KERNEL_ADDR = 0x07,
+ FW_CFG_KERNEL_SIZE = 0x08,
+ FW_CFG_KERNEL_CMDLINE = 0x09,
+ FW_CFG_INITRD_ADDR = 0x0a,
+ FW_CFG_INITRD_SIZE = 0x0b,
+ FW_CFG_BOOT_DEVICE = 0x0c,
+ FW_CFG_NUMA = 0x0d,
+ FW_CFG_BOOT_MENU = 0x0e,
+ FW_CFG_MAX_CPUS = 0x0f,
+ FW_CFG_KERNEL_ENTRY = 0x10,
+ FW_CFG_KERNEL_DATA = 0x11,
+ FW_CFG_INITRD_DATA = 0x12,
+ FW_CFG_CMDLINE_ADDR = 0x13,
+ FW_CFG_CMDLINE_SIZE = 0x14,
+ FW_CFG_CMDLINE_DATA = 0x15,
+ FW_CFG_SETUP_ADDR = 0x16,
+ FW_CFG_SETUP_SIZE = 0x17,
+ FW_CFG_SETUP_DATA = 0x18,
+ FW_CFG_FILE_DIR = 0x19,
+ FW_CFG_FILE_FIRST = 0x20,
+ FW_CFG_WRITE_CHANNEL = 0x4000,
+ FW_CFG_ARCH_LOCAL = 0x8000,
+ FW_CFG_INVALID = 0xffff,
+};
+
+#define FW_CFG_FILE_SLOTS 0x10
+#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
+#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
+
+#define FW_CFG_MAX_FILE_PATH 56
+
+#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
+
+#define FW_CFG_DMA_ERROR (1 << 0)
+#define FW_CFG_DMA_READ (1 << 1)
+#define FW_CFG_DMA_SKIP (1 << 2)
+#define FW_CFG_DMA_SELECT (1 << 3)
+
+#define FW_CFG_DMA_ENABLED (1 << 1)
+
+struct fw_cfg_file {
+ __be32 size;
+ __be16 select;
+ __be16 reserved;
+ char name[FW_CFG_MAX_FILE_PATH];
+};
+
+struct fw_cfg_files {
+ __be32 count;
+ struct fw_cfg_file files[];
+};
+
+struct fw_cfg_dma_access {
+ __be32 control;
+ __be32 length;
+ __be64 address;
+};
+
+/**
+ * Initialize QEMU fw_cfg interface
+ */
+void qemu_fwcfg_init(void);
+
+/**
+ * Get system cpu number
+ *
+ * @return: cpu number in system
+ */
+int qemu_fwcfg_online_cpus(void);
+
+#endif
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index 1d75cfc..9324bdb 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -242,9 +242,10 @@
vbe_set_mode(mode_info);
}
-void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
struct vbe_mode_info *mode_info)
{
+ pci_dev_t pcidev = dm_pci_get_bdf(dev);
u32 num_dev;
num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 |
diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c
index 47d9f59..e8ca6e6 100644
--- a/arch/x86/lib/bios_interrupts.c
+++ b/arch/x86/lib/bios_interrupts.c
@@ -105,13 +105,15 @@
unsigned short func = (unsigned short)M.x86.R_EAX;
int retval = 1;
unsigned short devid, vendorid, devfn;
+ struct udevice *dev;
/* Use short to get rid of gabage in upper half of 32-bit register */
short devindex;
unsigned char bus;
- pci_dev_t dev;
+ pci_dev_t bdf;
u32 dword;
u16 word;
u8 byte, reg;
+ int ret;
switch (func) {
case 0xb101: /* PCIBIOS Check */
@@ -131,17 +133,20 @@
devid = M.x86.R_ECX;
vendorid = M.x86.R_EDX;
devindex = M.x86.R_ESI;
- dev = pci_find_device(vendorid, devid, devindex);
- if (dev != -1) {
+ bdf = -1;
+ ret = dm_pci_find_device(vendorid, devid, devindex, &dev);
+ if (!ret) {
unsigned short busdevfn;
+
+ bdf = dm_pci_get_bdf(dev);
M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
/*
* busnum is an unsigned char;
* devfn is an int, so we mask it off.
*/
- busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 |
- PCI_FUNC(dev);
+ busdevfn = (PCI_BUS(bdf) << 8) | PCI_DEV(bdf) << 3 |
+ PCI_FUNC(bdf);
debug("0x%x: return 0x%x\n", func, busdevfn);
M.x86.R_EBX = busdevfn;
retval = 1;
@@ -160,35 +165,40 @@
devfn = M.x86.R_EBX & 0xff;
bus = M.x86.R_EBX >> 8;
reg = M.x86.R_EDI;
- dev = PCI_BDF(bus, devfn >> 3, devfn & 7);
+ bdf = PCI_BDF(bus, devfn >> 3, devfn & 7);
+
+ ret = dm_pci_bus_find_bdf(bdf, &dev);
+ if (ret) {
+ debug("%s: Device %x not found\n", __func__, bdf);
+ break;
+ }
switch (func) {
case 0xb108: /* Read Config Byte */
- byte = x86_pci_read_config8(dev, reg);
+ dm_pci_read_config8(dev, reg, &byte);
M.x86.R_ECX = byte;
break;
case 0xb109: /* Read Config Word */
- word = x86_pci_read_config16(dev, reg);
+ dm_pci_read_config16(dev, reg, &word);
M.x86.R_ECX = word;
break;
case 0xb10a: /* Read Config Dword */
- dword = x86_pci_read_config32(dev, reg);
+ dm_pci_read_config32(dev, reg, &dword);
M.x86.R_ECX = dword;
break;
case 0xb10b: /* Write Config Byte */
byte = M.x86.R_ECX;
- x86_pci_write_config8(dev, reg, byte);
+ dm_pci_write_config8(dev, reg, byte);
break;
case 0xb10c: /* Write Config Word */
word = M.x86.R_ECX;
- x86_pci_write_config16(dev, reg, word);
+ dm_pci_write_config16(dev, reg, word);
break;
case 0xb10d: /* Write Config Dword */
dword = M.x86.R_ECX;
- x86_pci_write_config32(dev, reg, dword);
+ dm_pci_write_config32(dev, reg, dword);
break;
}
-
#ifdef CONFIG_REALMODE_DEBUG
debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
bus, devfn, reg, M.x86.R_ECX);
diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c
index 4959edf..2554663 100644
--- a/arch/x86/lib/fsp/cmd_fsp.c
+++ b/arch/x86/lib/fsp/cmd_fsp.c
@@ -69,7 +69,7 @@
printf("---|----------|-----------|------|-");
printf("------------------------------------------\n");
while (!end_of_hob(hdr)) {
- printf("%-2d | %08x | ", i, (unsigned int)hdr);
+ printf("%02x | %08x | ", i, (unsigned int)hdr);
type = hdr->type;
if (type == HOB_TYPE_UNUSED)
desc = "*Unused*";
@@ -79,7 +79,7 @@
desc = hob_type[type];
else
desc = "*Invalid*";
- printf("%-9s | %-4d | ", desc, hdr->len);
+ printf("%-9s | %04x | ", desc, hdr->len);
if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC ||
type == HOB_TYPE_GUID_EXT) {
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 5276ce6..8479af1 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -90,8 +90,8 @@
/*
* The second time we enter here, adjust the size of malloc()
* pool before relocation. Given gd->malloc_base was adjusted
- * after the call to board_init_f_mem() in arch/x86/cpu/start.S,
- * we should fix up gd->malloc_limit here.
+ * after the call to board_init_f_init_reserve() in arch/x86/
+ * cpu/start.S, we should fix up gd->malloc_limit here.
*/
gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
}
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index 1d48ff4..875c96a 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -87,42 +87,28 @@
return (struct fsp_header *)fsp;
}
-void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
+void fsp_continue(u32 status, void *hob_list)
{
- u32 stack_len;
- u32 stack_base;
- u32 stack_top;
-
post_code(POST_MRC);
assert(status == 0);
- /* Get the migrated stack in normal memory */
- stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len);
- assert(stack_base != 0);
- stack_top = stack_base + stack_len - sizeof(u32);
-
- /*
- * Old stack base is stored at the very end of the stack top,
- * use it to calculate the migrated shared data base
- */
- shared_data = (struct shared_data *)(stack_base +
- ((u32)shared_data - *(u32 *)stack_top));
-
/* The boot loader main function entry */
fsp_init_done(hob_list);
}
void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
{
- struct shared_data shared_data;
+ struct fsp_config_data config_data;
fsp_init_f init;
struct fsp_init_params params;
struct fspinit_rtbuf rt_buf;
- struct vpd_region *fsp_vpd;
struct fsp_header *fsp_hdr;
struct fsp_init_params *params_ptr;
+#ifdef CONFIG_FSP_USE_UPD
+ struct vpd_region *fsp_vpd;
struct upd_region *fsp_upd;
+#endif
#ifdef CONFIG_DEBUG_UART
setup_early_uart();
@@ -134,14 +120,11 @@
panic("Invalid FSP header");
}
- fsp_upd = &shared_data.fsp_upd;
- memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
-
- /* Reserve a gap in stack top */
- rt_buf.common.stack_top = (u32 *)stack_top - 32;
- rt_buf.common.boot_mode = boot_mode;
- rt_buf.common.upd_data = fsp_upd;
+ config_data.common.fsp_hdr = fsp_hdr;
+ config_data.common.stack_top = stack_top;
+ config_data.common.boot_mode = boot_mode;
+#ifdef CONFIG_FSP_USE_UPD
/* Get VPD region start */
fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
fsp_hdr->cfg_region_off);
@@ -149,15 +132,20 @@
/* Verify the VPD data region is valid */
assert(fsp_vpd->sign == VPD_IMAGE_ID);
+ fsp_upd = &config_data.fsp_upd;
+
/* Copy default data from Flash */
memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
sizeof(struct upd_region));
/* Verify the UPD data region is valid */
assert(fsp_upd->terminator == UPD_TERMINATOR);
+#endif
- /* Override any UPD setting if required */
- update_fsp_upd(fsp_upd);
+ memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
+
+ /* Override any configuration if required */
+ update_fsp_configs(&config_data, &rt_buf);
memset(¶ms, 0, sizeof(struct fsp_init_params));
params.nvs_buf = nvs_buf;
@@ -167,28 +155,24 @@
init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
params_ptr = ¶ms;
- shared_data.fsp_hdr = fsp_hdr;
- shared_data.stack_top = (u32 *)stack_top;
-
post_code(POST_PRE_MRC);
/* Load GDT for FSP */
setup_fsp_gdt();
/*
- * Use ASM code to ensure the register value in EAX & ECX
- * will be passed into BlContinuationFunc
+ * Use ASM code to ensure the register value in EAX & EDX
+ * will be passed into fsp_continue
*/
asm volatile (
"pushl %0;"
"call *%%eax;"
".global asm_continuation;"
"asm_continuation:;"
- "movl %%ebx, %%eax;" /* shared_data */
- "movl 4(%%esp), %%edx;" /* status */
- "movl 8(%%esp), %%ecx;" /* hob_list */
+ "movl 4(%%esp), %%eax;" /* status */
+ "movl 8(%%esp), %%edx;" /* hob_list */
"jmp fsp_continue;"
- : : "m"(params_ptr), "a"(init), "b"(&shared_data)
+ : : "m"(params_ptr), "a"(init)
);
/*
diff --git a/arch/x86/lib/gcc.c b/arch/x86/lib/gcc.c
index 497ad75..3c70d79 100644
--- a/arch/x86/lib/gcc.c
+++ b/arch/x86/lib/gcc.c
@@ -3,18 +3,7 @@
*
* Copyright (C) 2009 coresystems GmbH
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 or later of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifdef __GNUC__
diff --git a/board/Marvell/db-88f6820-gp/Kconfig b/board/Marvell/db-88f6820-gp/Kconfig
deleted file mode 100644
index f12b968..0000000
--- a/board/Marvell/db-88f6820-gp/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DB_88F6820_GP
-
-config SYS_BOARD
- default "db-88f6820-gp"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "db-88f6820-gp"
-
-endif
diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg b/board/Marvell/db-88f6820-gp/kwbimage.cfg
index cc05792..1f748db 100644
--- a/board/Marvell/db-88f6820-gp/kwbimage.cfg
+++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg
@@ -9,4 +9,4 @@
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig
deleted file mode 100644
index 428a5e1..0000000
--- a/board/Marvell/db-mv784mp-gp/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DB_MV784MP_GP
-
-config SYS_BOARD
- default "db-mv784mp-gp"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "db-mv784mp-gp"
-
-endif
diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
index d7aa149..9305284 100644
--- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -87,40 +87,32 @@
return pci_eth_init(bis);
}
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1545 PHY */
-void reset_phy(void)
+int board_phy_config(struct phy_device *phydev)
{
- u8 phy_addr[] = CONFIG_PHY_ADDR;
- u16 devadr = phy_addr[0];
- char *name = "neta0";
u16 reg;
- if (miiphy_set_current_dev(name))
- return;
-
/* Enable QSGMII AN */
/* Set page to 4 */
- miiphy_write(name, devadr, 0x16, 4);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
/* Enable AN */
- miiphy_write(name, devadr, 0x0, 0x1140);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
/* Set page to 0 */
- miiphy_write(name, devadr, 0x16, 0);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
/* Phy C_ANEG */
- miiphy_read(name, devadr, 0x4, ®);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
reg |= 0x1E0;
- miiphy_write(name, devadr, 0x4, reg);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
/* Soft-Reset */
- miiphy_write(name, devadr, 22, 0x0000);
- miiphy_write(name, devadr, 0, 0x9140);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
/* Power up the phy */
- miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
- miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg);
+ phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
- printf("88E1545 Initialized on %s\n", name);
+ printf("88E1545 Initialized\n");
+ return 0;
}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
index cc05792..1f748db 100644
--- a/board/Marvell/db-mv784mp-gp/kwbimage.cfg
+++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
@@ -9,4 +9,4 @@
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/Synology/common/Makefile b/board/Synology/common/Makefile
new file mode 100644
index 0000000..e66aeb8
--- /dev/null
+++ b/board/Synology/common/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cmd_syno.o
diff --git a/board/Synology/common/cmd_syno.c b/board/Synology/common/cmd_syno.c
new file mode 100644
index 0000000..20544e2
--- /dev/null
+++ b/board/Synology/common/cmd_syno.c
@@ -0,0 +1,227 @@
+/*
+ * Commands to deal with Synology specifics.
+ *
+ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <linux/mtd/mtd.h>
+
+#include <asm/io.h>
+#include "../drivers/ddr/marvell/axp/ddr3_init.h"
+
+#define ETH_ALEN 6
+#define ETHADDR_MAX 4
+#define SYNO_SN_TAG "SN="
+#define SYNO_CHKSUM_TAG "CHK="
+
+
+static int do_syno_populate(int argc, char * const argv[])
+{
+ unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+ unsigned int cs = CONFIG_SF_DEFAULT_CS;
+ unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
+ unsigned int mode = CONFIG_SF_DEFAULT_MODE;
+ struct spi_flash *flash;
+ unsigned long addr = 0x80000; /* XXX: parameterize this? */
+ loff_t offset = 0x007d0000;
+ loff_t len = 0x00010000;
+ char *buf, *bufp;
+ char var[128];
+ char val[128];
+ int ret, n;
+
+ /* XXX: arg parsing to select flash here? */
+
+ flash = spi_flash_probe(bus, cs, speed, mode);
+ if (!flash) {
+ printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
+ return 1;
+ }
+
+ buf = map_physmem(addr, len, MAP_WRBACK);
+ if (!buf) {
+ puts("Failed to map physical memory\n");
+ return 1;
+ }
+
+ ret = spi_flash_read(flash, offset, len, buf);
+ if (ret) {
+ puts("Failed to read from SPI flash\n");
+ goto out_unmap;
+ }
+
+ for (n = 0; n < ETHADDR_MAX; n++) {
+ char ethaddr[ETH_ALEN];
+ int i, sum = 0;
+ unsigned char csum = 0;
+
+ for (i = 0, bufp = buf + n * 7; i < ETH_ALEN; i++) {
+ sum += bufp[i];
+ csum += bufp[i];
+ ethaddr[i] = bufp[i];
+ }
+ if (!sum) /* MAC address empty */
+ continue;
+ if (csum != bufp[i]) { /* seventh byte is checksum value */
+ printf("Invalid MAC address for interface %d!\n", n);
+ continue;
+ }
+ if (n == 0)
+ sprintf(var, "ethaddr");
+ else
+ sprintf(var, "eth%daddr", n);
+ snprintf(val, sizeof(val) - 1,
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ ethaddr[0], ethaddr[1], ethaddr[2],
+ ethaddr[3], ethaddr[4], ethaddr[5]);
+ printf("parsed %s = %s\n", var, val);
+ setenv(var, val);
+ }
+ if (!strncmp(buf + 32, SYNO_SN_TAG, strlen(SYNO_SN_TAG))) {
+ char *snp, *csump;
+ int csum = 0;
+ unsigned long c;
+
+ snp = bufp = buf + 32 + strlen(SYNO_SN_TAG);
+ for (n = 0; bufp[n] && bufp[n] != ','; n++)
+ csum += bufp[n];
+ bufp[n] = '\0';
+
+ /* should come right after, but you never know */
+ bufp = strstr(bufp + n + 1, SYNO_CHKSUM_TAG);
+ if (!bufp) {
+ printf("Serial number checksum tag missing!\n");
+ goto out_unmap;
+ }
+
+ csump = bufp += strlen(SYNO_CHKSUM_TAG);
+ for (n = 0; bufp[n] && bufp[n] != ','; n++)
+ ;
+ bufp[n] = '\0';
+
+ if (strict_strtoul(csump, 10, &c) || c != csum) {
+ puts("Invalid serial number found!\n");
+ ret = 1;
+ goto out_unmap;
+ }
+ printf("parsed SN = %s\n", snp);
+ setenv("SN", snp);
+ } else { /* old style format */
+ unsigned char csum = 0;
+
+ for (n = 0, bufp = buf + 32; n < 10; n++)
+ csum += bufp[n];
+
+ if (csum != bufp[n]) {
+ puts("Invalid serial number found!\n");
+ ret = 1;
+ goto out_unmap;
+ }
+ bufp[n] = '\0';
+ printf("parsed SN = %s\n", buf + 32);
+ setenv("SN", buf + 32);
+ }
+out_unmap:
+ unmap_physmem(buf, len);
+ return ret;
+}
+
+/* map bit position to function in POWER_MNG_CTRL_REG */
+static const char * const pwr_mng_bit_func[] = {
+ "audio",
+ "ge3", "ge2", "ge1", "ge0",
+ "pcie00", "pcie01", "pcie02", "pcie03",
+ "pcie10", "pcie11", "pcie12", "pcie13",
+ "bp",
+ "sata0_link", "sata0_core",
+ "lcd",
+ "sdio",
+ "usb0", "usb1", "usb2",
+ "idma", "xor0", "crypto",
+ NULL,
+ "tdm",
+ "pcie20", "pcie30",
+ "xor1",
+ "sata1_link", "sata1_core",
+ NULL,
+};
+
+static int do_syno_clk_gate(int argc, char * const argv[])
+{
+ u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
+ const char *func, *state;
+ int i, val;
+
+ if (argc < 2)
+ return -1;
+
+ if (!strcmp(argv[1], "get")) {
+ puts("Clock Gating:\n");
+ for (i = 0; i < 32; i++) {
+ func = pwr_mng_bit_func[i];
+ if (!func)
+ continue;
+ state = pwr_mng_ctrl_reg & (1 << i) ? "ON" : "OFF";
+ printf("%s:\t\t%s\n", func, state);
+ }
+ return 0;
+ }
+ if (argc < 4)
+ return -1;
+ if (!strcmp(argv[1], "set")) {
+ func = argv[2];
+ state = argv[3];
+ for (i = 0; i < 32; i++) {
+ if (!pwr_mng_bit_func[i])
+ continue;
+ if (!strcmp(func, pwr_mng_bit_func[i]))
+ break;
+ }
+ if (i == 32) {
+ printf("Error: name '%s' not known\n", func);
+ return -1;
+ }
+ val = state[0] != '0';
+ pwr_mng_ctrl_reg |= (val << i);
+ pwr_mng_ctrl_reg &= ~(!val << i);
+ reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
+ }
+ return 0;
+}
+
+static int do_syno(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ const char *cmd;
+ int ret = 0;
+
+ if (argc < 2)
+ goto usage;
+
+ cmd = argv[1];
+ --argc;
+ ++argv;
+
+ if (!strcmp(cmd, "populate_env"))
+ ret = do_syno_populate(argc, argv);
+ else if (!strcmp(cmd, "clk_gate"))
+ ret = do_syno_clk_gate(argc, argv);
+
+ if (ret != -1)
+ return ret;
+usage:
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ syno, 5, 1, do_syno,
+ "Synology specific commands",
+ "populate_env - Read vendor data from SPI flash into environment\n"
+ "clk_gate (get|set name 1|0) - Manage clock gating\n"
+);
diff --git a/board/Synology/ds414/Makefile b/board/Synology/ds414/Makefile
new file mode 100644
index 0000000..0f4c32d
--- /dev/null
+++ b/board/Synology/ds414/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ds414.o
diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c
new file mode 100644
index 0000000..d563e89
--- /dev/null
+++ b/board/Synology/ds414/ds414.c
@@ -0,0 +1,185 @@
+/*
+ *
+ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
+
+#define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30))
+#define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15))
+#define DS414_GPP_OUT_VAL_HIGH (0)
+
+#define DS414_GPP_OUT_POL_LOW (0)
+#define DS414_GPP_OUT_POL_MID (0)
+#define DS414_GPP_OUT_POL_HIGH (0)
+
+#define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30)))
+#define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \
+ BIT(13) | BIT(14) | BIT(15)))
+#define DS414_GPP_OUT_ENA_HIGH (~0)
+
+static const u32 ds414_mpp_control[] = {
+ 0x11111111,
+ 0x22221111,
+ 0x22222222,
+ 0x00000000,
+ 0x11110000,
+ 0x00004000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+/* DDR3 static MC configuration */
+
+/* 1G_v1 (4x2Gbits) adapted by DS414 */
+MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
+ {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
+ {0x00001404, 0x30000800}, /*Dunit Control Low Register */
+ {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */
+ {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */
+
+ {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */
+
+ {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
+ {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
+ {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
+ {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */
+ {0x00001428, 0x000F8830}, /*Dunit Control High Register */
+ {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */
+ {0x0000147C, 0x0000C671},
+
+ {0x000014a0, 0x00000001},
+ {0x000014a8, 0x00000100}, /*2:1 */
+ {0x00020220, 0x00000006},
+
+ {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
+ {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
+ {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */
+
+ {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */
+ {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */
+
+ {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
+ {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
+
+ {0x0001504, 0x3FFFFFE1}, /* CS0 Size */
+ {0x000150C, 0x00000000}, /* CS1 Size */
+ {0x0001514, 0x00000000}, /* CS2 Size */
+ {0x000151C, 0x00000000}, /* CS3 Size */
+
+ {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
+ {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */
+
+ {0x000015D0, 0x00000650}, /*MR0 */
+ {0x000015D4, 0x00000044}, /*MR1 */
+ {0x000015D8, 0x00000010}, /*MR2 */
+ {0x000015DC, 0x00000000}, /*MR3 */
+
+ {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
+ {0x000015EC, 0xF800A225}, /*DDR PHY */
+
+ {0x0, 0x0}
+};
+
+MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
+ {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
+};
+
+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
+
+MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
+ { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
+ { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
+ PEX_BUS_DISABLED },
+ 0x0040, serdes_change_m_phy
+ }
+};
+
+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
+{
+ return &ds414_ddr_modes[0];
+}
+
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+{
+ return &ds414_serdes_cfg[0];
+}
+
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+ return (0x1 << 1 | 1);
+}
+
+int board_early_init_f(void)
+{
+ int i;
+
+ /* Set GPP Out value */
+ reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
+ reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
+ reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
+
+ /* set GPP polarity */
+ reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
+ reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
+ reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
+
+ /* Set GPP Out Enable */
+ reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
+ reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
+ reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
+
+ for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
+ reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ u32 pwr_mng_ctrl_reg;
+
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* Gate unused clocks
+ *
+ * Note: Disabling unused PCIe lanes will hang PCI bus scan.
+ * Once this is resolved, bits 10-12, 26 and 27 can be
+ * unset here as well.
+ */
+ pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
+ pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */
+ pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */
+ pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */
+ pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */
+ pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */
+ pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */
+ pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */
+ reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: DS414\n");
+
+ return 0;
+}
diff --git a/board/Synology/ds414/kwbimage.cfg b/board/Synology/ds414/kwbimage.cfg
new file mode 100644
index 0000000..1f748db
--- /dev/null
+++ b/board/Synology/ds414/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/altera/arria5-socdk/socfpga.c b/board/altera/arria5-socdk/socfpga.c
index a1dbc49..97fb902 100644
--- a/board/altera/arria5-socdk/socfpga.c
+++ b/board/altera/arria5-socdk/socfpga.c
@@ -3,83 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/s3c_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return s3c_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 33cf1fd..f1e6d2b 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -9,19 +9,19 @@
const u8 sys_mgr_init_table[] = {
3, /* EMACIO0 */
- 3, /* EMACIO1 */
- 3, /* EMACIO2 */
- 3, /* EMACIO3 */
- 3, /* EMACIO4 */
- 3, /* EMACIO5 */
- 3, /* EMACIO6 */
- 3, /* EMACIO7 */
- 3, /* EMACIO8 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
3, /* EMACIO9 */
- 3, /* EMACIO10 */
- 3, /* EMACIO11 */
- 3, /* EMACIO12 */
- 3, /* EMACIO13 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
0, /* EMACIO14 */
0, /* EMACIO15 */
0, /* EMACIO16 */
@@ -55,8 +55,8 @@
0, /* GENERALIO12 */
2, /* GENERALIO13 */
2, /* GENERALIO14 */
- 0, /* GENERALIO15 */
- 0, /* GENERALIO16 */
+ 3, /* GENERALIO15 */
+ 3, /* GENERALIO16 */
2, /* GENERALIO17 */
2, /* GENERALIO18 */
0, /* GENERALIO19 */
@@ -72,27 +72,27 @@
0, /* GENERALIO29 */
0, /* GENERALIO30 */
0, /* GENERALIO31 */
- 0, /* MIXED1IO0 */
- 1, /* MIXED1IO1 */
- 1, /* MIXED1IO2 */
- 1, /* MIXED1IO3 */
- 1, /* MIXED1IO4 */
- 0, /* MIXED1IO5 */
- 0, /* MIXED1IO6 */
- 0, /* MIXED1IO7 */
- 1, /* MIXED1IO8 */
- 1, /* MIXED1IO9 */
- 1, /* MIXED1IO10 */
- 1, /* MIXED1IO11 */
- 0, /* MIXED1IO12 */
- 0, /* MIXED1IO13 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
- 1, /* MIXED1IO15 */
- 1, /* MIXED1IO16 */
- 1, /* MIXED1IO17 */
- 1, /* MIXED1IO18 */
- 0, /* MIXED1IO19 */
- 0, /* MIXED1IO20 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
0, /* MIXED1IO21 */
0, /* MIXED2IO0 */
0, /* MIXED2IO1 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index 3d621ed..4abd2e0 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -14,7 +14,7 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
@@ -31,7 +31,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c
index a1dbc49..97fb902 100644
--- a/board/altera/cyclone5-socdk/socfpga.c
+++ b/board/altera/cyclone5-socdk/socfpga.c
@@ -3,83 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/s3c_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return s3c_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c
index 20eb191..b3a4a41 100644
--- a/board/broadcom/bcm28155_ap/bcm28155_ap.c
+++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
@@ -13,7 +13,7 @@
#include <asm/arch/sysmap.h>
#include <usb.h>
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
#include <g_dnl.h>
#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000
@@ -95,14 +95,14 @@
#endif
#ifdef CONFIG_USB_GADGET
-static struct s3c_plat_otg_data bcm_otg_data = {
+static struct dwc2_plat_otg_data bcm_otg_data = {
.regs_otg = HSOTG_BASE_ADDR
};
int board_usb_init(int index, enum usb_init_type init)
{
- debug("%s: performing s3c_udc_probe\n", __func__);
- return s3c_udc_probe(&bcm_otg_data);
+ debug("%s: performing dwc2_udc_probe\n", __func__);
+ return dwc2_udc_probe(&bcm_otg_data);
}
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index 462ab05..cd99294 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -4,14 +4,7 @@
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
index c9da80d..723293f 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -13,7 +13,6 @@
#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
#include <i2c.h>
-#include <netdev.h>
void pin_mux_usb(void)
{
@@ -41,10 +40,3 @@
/* For CD GPIO PP1 */
pinmux_tristate_disable(PMUX_PINGRP_DAP3);
}
-
-#ifdef CONFIG_PCI
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-#endif
diff --git a/board/congatec/cgtqmx6eval/MAINTAINERS b/board/congatec/cgtqmx6eval/MAINTAINERS
index c41ebf5..48c0889 100644
--- a/board/congatec/cgtqmx6eval/MAINTAINERS
+++ b/board/congatec/cgtqmx6eval/MAINTAINERS
@@ -3,4 +3,4 @@
S: Maintained
F: board/congatec/cgtqmx6eval/
F: include/configs/cgtqmx6eval.h
-F: configs/cgtqmx6qeval_defconfig
+F: configs/cgtqmx6eval_defconfig
diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README
index 1d736dc..f2c9599 100644
--- a/board/congatec/cgtqmx6eval/README
+++ b/board/congatec/cgtqmx6eval/README
@@ -25,11 +25,15 @@
=> sf probe
+=> setenv serverip <server_ip_address>
+
+=> setenv ipaddr <board_ip_address>
+
=> tftp 0x12000000 SPL
=> sf erase 0x0 0x10000
-=> sf write 0x12000000 0x400 0x100
+=> sf write 0x12000000 0x400 0x10000
=> tftp 0x12000000 u-boot.img
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index 5fd526d..225de7c 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -404,7 +404,7 @@
#ifdef CONFIG_MXC_SPI
static void setup_spi(void)
{
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+ SETUP_IOMUX_PADS(ecspi1_pads);
gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
}
#endif
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index bef2570..f69aeb6 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -6,19 +6,7 @@
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
index bd20f6e..75e6f0e 100644
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <command.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
index 842fb76..409f8ee 100644
--- a/board/dbau1x00/lowlevel_init.S
+++ b/board/dbau1x00/lowlevel_init.S
@@ -1,8 +1,8 @@
/* Memory sub-system initialization code */
#include <config.h>
+#include <mach/au1x00.h>
#include <asm/regdef.h>
-#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#define AU1500_SYS_ADDR 0xB1900000
diff --git a/board/denx/mcvevk/socfpga.c b/board/denx/mcvevk/socfpga.c
index 1a23a7d..6be58f0 100644
--- a/board/denx/mcvevk/socfpga.c
+++ b/board/denx/mcvevk/socfpga.c
@@ -3,43 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/s3c_udc.h>
-#include <usb_mass_storage.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return s3c_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c
index a1dbc49..97fb902 100644
--- a/board/ebv/socrates/socfpga.c
+++ b/board/ebv/socrates/socfpga.c
@@ -3,83 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/s3c_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return s3c_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index 2c17156..eb10a6f 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index df90476..4b2303e 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -408,22 +408,22 @@
sizeof(f_link));
break;
case 0x98: /* XAUI interface */
- sprintf(alias, "phy_xaui_slot1");
+ strcpy(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
- sprintf(alias, "phy_xaui_slot2");
+ strcpy(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x9e: /* XAUI interface */
case 0x9a:
case 0x93:
case 0x91:
- sprintf(alias, "phy_xaui_slot1");
+ strcpy(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x97: /* XAUI interface */
case 0xc3:
- sprintf(alias, "phy_xaui_slot2");
+ strcpy(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
default:
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 783c46d..69afa83 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -13,7 +13,8 @@
int pfuze_mode_init(struct pmic *p, u32 mode)
{
unsigned char offset, i, switch_num;
- u32 id, ret;
+ u32 id;
+ int ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &id);
id = id & 0xf;
diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c
index 022f38b..e55a030 100644
--- a/board/freescale/common/sdhc_boot.c
+++ b/board/freescale/common/sdhc_boot.c
@@ -29,7 +29,7 @@
return 1;
/* read out the first block, get the config data information */
- n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf);
+ n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf);
if (!n) {
free(tmp_buf);
return 1;
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index e7e893a..f3ba41a 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index 172a55b..55437e8 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -170,7 +170,7 @@
bus->read = hydra_mdio_read;
bus->write = hydra_mdio_write;
bus->reset = hydra_mdio_reset;
- sprintf(bus->name, fakebusname);
+ strcpy(bus->name, fakebusname);
hmdio->realbus = miiphy_get_dev_by_name(realbusname);
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index 62b1635..3f11f5f 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -175,7 +175,7 @@
bus->read = super_hydra_mdio_read;
bus->write = super_hydra_mdio_write;
bus->reset = super_hydra_mdio_reset;
- sprintf(bus->name, fakebusname);
+ strcpy(bus->name, fakebusname);
hmdio->realbus = miiphy_get_dev_by_name(realbusname);
diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c
index 4dead9c..20785b1 100644
--- a/board/freescale/corenet_ds/p3041ds_ddr.c
+++ b/board/freescale/corenet_ds/p3041ds_ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
index d572a5f..f470306 100644
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
index 9aaf6db..9747d90 100644
--- a/board/freescale/corenet_ds/p5020ds_ddr.c
+++ b/board/freescale/corenet_ds/p5020ds_ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c
index 9aaf6db..9747d90 100644
--- a/board/freescale/corenet_ds/p5040ds_ddr.c
+++ b/board/freescale/corenet_ds/p5040ds_ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c
index be351be..bf3e08a 100644
--- a/board/freescale/ls1021aqds/eth.c
+++ b/board/freescale/ls1021aqds/eth.c
@@ -113,7 +113,7 @@
bus->read = ls1021a_mdio_read;
bus->write = ls1021a_mdio_write;
bus->reset = ls1021a_mdio_reset;
- sprintf(bus->name, fakebusname);
+ strcpy(bus->name, fakebusname);
lsmdio->realbus = miiphy_get_dev_by_name(realbusname);
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index b7fc360..88b10a0 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -136,7 +136,7 @@
bus->read = ls1043aqds_mdio_read;
bus->write = ls1043aqds_mdio_write;
bus->reset = ls1043aqds_mdio_reset;
- sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
index 935ffc0..d87058b 100644
--- a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
+++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# serdes protocol
-0810000f 0c000000 00000000 00000000
-14550002 80004012 e0106000 61002000
+08100010 0a000000 00000000 00000000
+14550002 80004012 e0106000 c1002000
00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
index 17a5dd0..b6b5e0b 100644
--- a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
@@ -2,7 +2,7 @@
aa55aa55 01ee0100
# RCW
# Enable IFC; disable QSPI
-0810000f 0c000000 00000000 00000000
-14550002 80004012 60040000 61002000
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
index 935ffc0..d87058b 100644
--- a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# serdes protocol
-0810000f 0c000000 00000000 00000000
-14550002 80004012 e0106000 61002000
+08100010 0a000000 00000000 00000000
+14550002 80004012 e0106000 c1002000
00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
index 28cd958..e2ee34b 100644
--- a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# RCW
-0810000f 0c000000 00000000 00000000
-14550002 80004012 60040000 61002000
+08100010 0a000000 00000000 00000000
+14550002 80004012 60040000 c1002000
00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
index 03ca168..975ea2d 100644
--- a/board/freescale/ls2080a/MAINTAINERS
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
F: board/freescale/ls2080a/
F: include/configs/ls2080a_emu.h
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 0637ecf..ebc9d47 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -412,7 +412,7 @@
bus->read = ls2080a_qds_mdio_read;
bus->write = ls2080a_qds_mdio_write;
bus->reset = ls2080a_qds_mdio_reset;
- sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
index ebe3ba4..f269feb 100644
--- a/board/freescale/mpc8536ds/ddr.c
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 41d4cfe..10fb2b3 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
index d2ac6c4..e438737 100644
--- a/board/freescale/mpc8541cds/ddr.c
+++ b/board/freescale/mpc8541cds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index aa30cab..93c7f4b 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
index b31ea34..0d5783a 100644
--- a/board/freescale/mpc8548cds/ddr.c
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
index d2ac6c4..e438737 100644
--- a/board/freescale/mpc8555cds/ddr.c
+++ b/board/freescale/mpc8555cds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 41d4cfe..10fb2b3 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
index 6db92ef..cb3b707 100644
--- a/board/freescale/mpc8568mds/ddr.c
+++ b/board/freescale/mpc8568mds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index ef404b1..89e9297 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8572ds/MAINTAINERS b/board/freescale/mpc8572ds/MAINTAINERS
index 4c9b968..46c2903 100644
--- a/board/freescale/mpc8572ds/MAINTAINERS
+++ b/board/freescale/mpc8572ds/MAINTAINERS
@@ -1,5 +1,5 @@
MPC8572DS BOARD
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
F: board/freescale/mpc8572ds/
F: include/configs/MPC8572DS.h
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 2bfc1a1..524ed60 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index aa30cab..93c7f4b 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 7cd0395..00670bc 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008,2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/mx25pdk/MAINTAINERS b/board/freescale/mx25pdk/MAINTAINERS
index 6322176..fa4651e 100644
--- a/board/freescale/mx25pdk/MAINTAINERS
+++ b/board/freescale/mx25pdk/MAINTAINERS
@@ -1,5 +1,5 @@
MX25PDK BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx25pdk/
F: include/configs/mx25pdk.h
diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS
index 1caf5fb..a98a705 100644
--- a/board/freescale/mx28evk/MAINTAINERS
+++ b/board/freescale/mx28evk/MAINTAINERS
@@ -1,5 +1,5 @@
MX28EVK BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx28evk/
F: include/configs/mx28evk.h
diff --git a/board/freescale/mx53ard/MAINTAINERS b/board/freescale/mx53ard/MAINTAINERS
index 7cc0e5e..fa81afe 100644
--- a/board/freescale/mx53ard/MAINTAINERS
+++ b/board/freescale/mx53ard/MAINTAINERS
@@ -1,5 +1,5 @@
MX53ARD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx53ard/
F: include/configs/mx53ard.h
diff --git a/board/freescale/mx53smd/MAINTAINERS b/board/freescale/mx53smd/MAINTAINERS
index 8830321..17ec376 100644
--- a/board/freescale/mx53smd/MAINTAINERS
+++ b/board/freescale/mx53smd/MAINTAINERS
@@ -1,5 +1,5 @@
MX53SMD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx53smd/
F: include/configs/mx53smd.h
diff --git a/board/freescale/mx6qsabreauto/MAINTAINERS b/board/freescale/mx6qsabreauto/MAINTAINERS
index 75a8862..687f68c 100644
--- a/board/freescale/mx6qsabreauto/MAINTAINERS
+++ b/board/freescale/mx6qsabreauto/MAINTAINERS
@@ -1,5 +1,5 @@
MX6QSABREAUTO BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6qsabreauto/
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 7c0e90a..c2e9c57 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -412,14 +412,44 @@
}
#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ clrbits_le32(&iomux->gpr[2],
+ IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+ IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+}
+
static void do_enable_hdmi(struct display_info_t const *dev)
{
+ disable_lvds(dev);
imx_enable_hdmi_phy();
}
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = NULL,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.enable = do_enable_hdmi,
@@ -440,18 +470,69 @@
} } };
size_t display_count = ARRAY_SIZE(displays);
+iomux_v3_cfg_t const backlight_pads[] = {
+ MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_backlight(void)
+{
+ gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+}
+
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
+ setup_iomux_backlight();
enable_ipu_clock();
imx_setup_hdmi();
+ /* Turn on LDB_DI0 and LDB_DI1 clocks */
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
reg = readl(&mxc_ccm->chsccdr);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+ IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+ reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
}
#endif /* CONFIG_VIDEO_IPUV3 */
@@ -467,9 +548,6 @@
int board_early_init_f(void)
{
setup_iomux_uart();
-#ifdef CONFIG_VIDEO_IPUV3
- setup_display();
-#endif
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
@@ -494,6 +572,9 @@
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
setup_iomux_eimnor();
return 0;
}
diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS
index 0011ec7..add2314 100644
--- a/board/freescale/mx6sabresd/MAINTAINERS
+++ b/board/freescale/mx6sabresd/MAINTAINERS
@@ -1,5 +1,5 @@
MX6SABRESD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx6sabresd/
F: include/configs/mx6sabresd.h
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 581c9d5..d20953d 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -94,8 +94,9 @@
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+ udelay(100);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -340,39 +341,6 @@
}
#endif
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
#if defined(CONFIG_VIDEO_IPUV3)
static void disable_lvds(struct display_info_t const *dev)
{
diff --git a/board/freescale/mx6slevk/MAINTAINERS b/board/freescale/mx6slevk/MAINTAINERS
index f4e74ba..2e25433 100644
--- a/board/freescale/mx6slevk/MAINTAINERS
+++ b/board/freescale/mx6slevk/MAINTAINERS
@@ -1,5 +1,5 @@
MX6SLEVK BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6slevk/
diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS
index c0f5d9c..1dcec67 100644
--- a/board/freescale/mx6sxsabresd/MAINTAINERS
+++ b/board/freescale/mx6sxsabresd/MAINTAINERS
@@ -1,5 +1,5 @@
MX6SXSABRESD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx6sxsabresd/
F: include/configs/mx6sxsabresd.h
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 3ee4662..56dc020 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -150,11 +150,15 @@
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg;
+ int reg, ret;
/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
+ ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+ if (ret)
+ return ret;
+
imx_iomux_v3_setup_multiple_pads(phy_control_pads,
ARRAY_SIZE(phy_control_pads));
@@ -163,14 +167,14 @@
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(IMX_GPIO_NR(2, 7), 1);
reg = readl(&anatop->pll_enet);
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
- return enable_fec_anatop_clock(0, ENET_125MHZ);
+ return 0;
}
int board_eth_init(bd_t *bis)
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 946d503..1f3793b 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index b8bbcdf..b2493e1 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
index a0fca0d..6cb5692 100644
--- a/board/freescale/qemu-ppce500/qemu-ppce500.c
+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
@@ -81,7 +81,7 @@
ulong map_addr;
int r;
- r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size);
+ r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size);
if (r)
return r;
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
index 99c23f7..ca54e2a 100644
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -148,7 +148,7 @@
bus->read = t1024qds_mdio_read;
bus->write = t1024qds_mdio_write;
bus->reset = t1024qds_mdio_reset;
- sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 8bf34fa..872e6e8 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -162,7 +162,7 @@
bus->read = t1040_qds_mdio_read;
bus->write = t1040_qds_mdio_write;
bus->reset = t1040_qds_mdio_reset;
- sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
index 3348971..f1aff54 100644
--- a/board/freescale/t208xqds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 1c0ce24..f08cff2 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -176,7 +176,7 @@
bus->read = t208xqds_mdio_read;
bus->write = t208xqds_mdio_write;
bus->reset = t208xqds_mdio_reset;
- sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index 8a26276..053f128 100644
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 7abd38d..62d58c5 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 or later as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 2dfdcbb..83a3a9b 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -153,7 +153,7 @@
bus->read = t4240qds_mdio_read;
bus->write = t4240qds_mdio_write;
bus->reset = t4240qds_mdio_reset;
- sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
+ strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c
index 1d6eb7b..262ead5 100644
--- a/board/gdsys/common/ihs_mdio.c
+++ b/board/gdsys/common/ihs_mdio.c
@@ -80,7 +80,7 @@
bus->read = ihs_mdio_read;
bus->write = ihs_mdio_write;
bus->reset = ihs_mdio_reset;
- sprintf(bus->name, info->name);
+ strcpy(bus->name, info->name);
bus->priv = info;
diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c
index 11d075c..2c6c698 100644
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -2,20 +2,7 @@
* (C) Copyright 2013
* Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* TODO: some more #ifdef's to avoid unneeded code for stage 1 / stage 2 */
@@ -232,7 +219,7 @@
ofs = src % blk_len;
if (ofs) {
- n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1,
+ n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1,
tmp_buf);
if (!n)
goto failure;
@@ -243,7 +230,7 @@
}
cnt = size / blk_len;
if (cnt) {
- n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no, cnt,
+ n = mmc->block_dev.block_read(&mmc->block_dev, block_no, cnt,
dst);
if (n != cnt)
goto failure;
@@ -253,7 +240,7 @@
block_no += cnt;
}
if (size) {
- n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1,
+ n = mmc->block_dev.block_read(&mmc->block_dev, block_no++, 1,
tmp_buf);
if (!n)
goto failure;
diff --git a/board/gdsys/p1022/controlcenterd-id.h b/board/gdsys/p1022/controlcenterd-id.h
index de4770a..b6f4702 100644
--- a/board/gdsys/p1022/controlcenterd-id.h
+++ b/board/gdsys/p1022/controlcenterd-id.h
@@ -2,20 +2,7 @@
* (C) Copyright 2013
* Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONTROLCENTER_ID_H
diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c
index 7596736..58f63f3 100644
--- a/board/gdsys/p1022/ddr.c
+++ b/board/gdsys/p1022/ddr.c
@@ -3,10 +3,7 @@
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/board/gdsys/p1022/diu.c b/board/gdsys/p1022/diu.c
index 52ac1e6..af0608b 100644
--- a/board/gdsys/p1022/diu.c
+++ b/board/gdsys/p1022/diu.c
@@ -4,10 +4,7 @@
*
* FSL DIU Framebuffer driver
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/board/gdsys/p1022/law.c b/board/gdsys/p1022/law.c
index 96f38f7..1438d9f 100644
--- a/board/gdsys/p1022/law.c
+++ b/board/gdsys/p1022/law.c
@@ -3,10 +3,7 @@
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c
index fd0e910..6a4a6ef 100644
--- a/board/gdsys/p1022/sdhc_boot.c
+++ b/board/gdsys/p1022/sdhc_boot.c
@@ -43,7 +43,7 @@
return 1;
/* read out the first block, get the config data information */
- n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf);
+ n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf);
if (!n) {
free(tmp_buf);
return 1;
diff --git a/board/gdsys/p1022/tlb.c b/board/gdsys/p1022/tlb.c
index 9cad692..aee86a4 100644
--- a/board/gdsys/p1022/tlb.c
+++ b/board/gdsys/p1022/tlb.c
@@ -3,10 +3,7 @@
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 6b13939..fa12f33 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -19,6 +19,7 @@
def_bool y
select X86_RESET_VECTOR
select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
config PCIE_ECAM_BASE
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index ae96d23..2af3aa9 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -20,6 +20,7 @@
def_bool y
select X86_RESET_VECTOR
select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
config SYS_CAR_ADDR
diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c
index 0015323..1578a33 100644
--- a/board/highbank/ahci.c
+++ b/board/highbank/ahci.c
@@ -1,18 +1,7 @@
/*
* Copyright 2012 Calxeda, Inc.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 79562f7..cae4a21 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -53,8 +53,9 @@
static enum core_card malta_core_card(void)
{
u32 corid, rev;
+ const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
- rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+ rev = __raw_readl(reg);
corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
switch (corid) {
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 8de129d..a42f3ec 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -168,7 +168,7 @@
printf("can't get the IVM_Boardid\n");
return 1;
}
- sprintf((char *)buf, "%s", p);
+ strcpy((char *)buf, p);
setenv("boardid", (char *)buf);
printf("set boardid=%s\n", buf);
@@ -177,7 +177,7 @@
printf("can't get the IVM_HWKey\n");
return 1;
}
- sprintf((char *)buf, "%s", p);
+ strcpy((char *)buf, p);
setenv("hwkey", (char *)buf);
printf("set hwkey=%s\n", buf);
printf("Execute manually saveenv for persistent storage.\n");
diff --git a/board/kylin/kylin_rk3036/Kconfig b/board/kylin/kylin_rk3036/Kconfig
new file mode 100644
index 0000000..5d75c1f
--- /dev/null
+++ b/board/kylin/kylin_rk3036/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_KYLIN_RK3036
+
+config SYS_BOARD
+ default "kylin_rk3036"
+
+config SYS_VENDOR
+ default "kylin"
+
+config SYS_CONFIG_NAME
+ default "kylin_rk3036"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/kylin/kylin_rk3036/MAINTAINERS b/board/kylin/kylin_rk3036/MAINTAINERS
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/board/kylin/kylin_rk3036/MAINTAINERS
diff --git a/board/kylin/kylin_rk3036/Makefile b/board/kylin/kylin_rk3036/Makefile
new file mode 100644
index 0000000..0663270
--- /dev/null
+++ b/board/kylin/kylin_rk3036/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += kylin_rk3036.o
diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c b/board/kylin/kylin_rk3036/kylin_rk3036.c
new file mode 100644
index 0000000..40d6b52
--- /dev/null
+++ b/board/kylin/kylin_rk3036/kylin_rk3036.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/uart.h>
+#include <asm/arch/sdram_rk3036.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void get_ddr_config(struct rk3036_ddr_config *config)
+{
+ /* K4B4G1646Q config */
+ config->ddr_type = 3;
+ config->rank = 1;
+ config->cs0_row = 15;
+ config->cs1_row = 15;
+
+ /* 8bank */
+ config->bank = 3;
+ config->col = 10;
+
+ /* 16bit bw */
+ config->bw = 1;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = sdram_size();
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
diff --git a/board/lge/sniper/sniper.h b/board/lge/sniper/sniper.h
index b2a09b3..e5d0774 100644
--- a/board/lge/sniper/sniper.h
+++ b/board/lge/sniper/sniper.h
@@ -51,13 +51,13 @@
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */ \
/* GPMC */ \
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \
- MUX_VAL(CP(GPMC_A2), (IEN | PTU | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \
+ MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\
MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* GPIO_38: MODEM_PWR_CHK */\
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* GPIO_39: MODEM_WAKE */\
- MUX_VAL(CP(GPMC_A7), (IEN | PTU | DIS | M4)) /* GPIO_40: MUIC_INT_N */\
+ MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* GPIO_40: MUIC_INT_N */\
MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* GPIO_41: GYRO_INT_N */\
MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* GPIO_42: MOTION_INT_N */\
MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* GPIO_43: BT_HOST_WAKEUP */\
@@ -129,7 +129,7 @@
MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* CAM_VS */ \
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* CAM_XCLKA */ \
MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* CAM_PCLK */ \
- MUX_VAL(CP(CAM_FLD), (IDIS | PTU | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* CSI2_DX2 */ \
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* CSI2_DY2 */ \
MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* GPIO_101: IFX_USB_VBUS_EN */ \
@@ -156,12 +156,12 @@
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* MCBSP2_DR */ \
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* MCBSP2_DX */ \
/* MMC1 */ \
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /* MMC1_CLK */ \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) /* MMC1_CMD */ \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) /* MMC1_DAT0 */ \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) /* MMC1_DAT1 */ \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) /* MMC1_DAT2 */ \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) /* MMC1_DAT3 */ \
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* MMC1_CLK */ \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* MMC1_CMD */ \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* MMC1_DAT0 */ \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* MMC1_DAT1 */ \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* MMC1_DAT2 */ \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* MMC1_DAT3 */ \
MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
@@ -183,15 +183,15 @@
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP3_CLKX */ \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* MCBSP3_FSX */ \
/* UART2 */ \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | DIS | M0)) /* UART2_CTS */ \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTU | DIS | M0)) /* UART2_RTS */ \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* UART2_CTS */ \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* UART2_RTS */ \
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* UART2_TX */ \
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* UART2_RX */ \
/* UART1 */ \
- MUX_VAL(CP(UART1_TX), (IDIS | PTU | DIS | M0)) /* UART1_TX */ \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTU | DIS | M0)) /* UART1_RTS */ \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /* UART1_CTS */ \
- MUX_VAL(CP(UART1_RX), (IEN | PTU | DIS | M0)) /* UART1_RX */ \
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */ \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* UART1_RTS */ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* UART1_CTS */ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ \
/* MCBSP4 */ \
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_152: GPS_PWR_ON */ \
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* GPIO_153: GPS_RESET_N */ \
@@ -227,11 +227,11 @@
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */ \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */ \
/* I2C2 */ \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | DIS | M0)) /* I2C2_SCL */ \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | DIS | M0)) /* I2C2_SDA */ \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* I2C2_SCL */ \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* I2C2_SDA */ \
/* I2C3 */ \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | DIS | M0)) /* I2C3_SCL */ \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | DIS | M0)) /* I2C3_SDA */ \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* I2C3_SCL */ \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* I2C3_SDA */ \
/* I2C4 */ \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */ \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */ \
@@ -242,13 +242,13 @@
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | DIS | M4)) /* GPIO_175: GAUGE_INT */ \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /* GPIO_176: MODEM_SEND */ \
- MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /* GPIO_177: MODEM_CHK */ \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* GPIO_175: GAUGE_INT */ \
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* GPIO_176: MODEM_SEND */ \
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* GPIO_177: MODEM_CHK */ \
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* MCSPI2_CLK */ \
MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* MCSPI2_SIMO */ \
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* MCSPI2_SOMI */ \
- MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \
+ MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \
MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* GPIO_182: USIF1_SW */ \
/* SYS */ \
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */ \
@@ -262,25 +262,25 @@
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* SYS_OFF_MODE */ \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* SAFE_MODE */ \
/* JTAG */ \
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* JTAG_NTRST */ \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* JTAG_TCK */ \
MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* JTAG_TMS */ \
MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* JTAG_TDI */ \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | DIS | M0)) /* JTAG_EMU0 */ \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | DIS | M0)) /* JTAG_EMU1 */ \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* JTAG_EMU0 */ \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* JTAG_EMU1 */ \
/* ETK */ \
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_CLK */ \
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* SDMMC3_CMD */ \
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* GPIO_14: PROX_OUT */ \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* GPIO_16: BT_EN */ \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT3 */ \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT0 */ \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT1 */ \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M2)) /* SDMMC3_DAT2 */ \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT3 */ \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT0 */ \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT1 */ \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT2 */ \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* GPIO_21: IPC_SRDY */ \
MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_22: IPC_MRDY */ \
MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_23: WLAN_EN */ \
@@ -330,7 +330,7 @@
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* D2D_MCAD36 */ \
MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* D2D_CLK26MI */ \
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* D2D_NRESPWRON */ \
- MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTU | DIS | M0)) /* D2D_NRESWARM */ \
+ MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* D2D_NRESWARM */ \
MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* D2D_ARM9NIRQ */ \
MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* D2D_UMA2P6FIQ */ \
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* D2D_SPINT */ \
@@ -355,8 +355,8 @@
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* D2D_SREAD */ \
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_MBUSFLAG */ \
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_SBUSFLAG */ \
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | DIS | M0)) /* SDRC_CKE0 */ \
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /* SDRC_CKE1 */ \
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* SDRC_CKE0 */ \
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* SDRC_CKE1 */ \
MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \
MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* GPIO_126: OMAP_SEND */ \
MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* GPIO_128: KEY_LED_RESET */ \
diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig
deleted file mode 100644
index 2edccfe..0000000
--- a/board/maxbcm/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MAXBCM
-
-config SYS_BOARD
- default "maxbcm"
-
-config SYS_CONFIG_NAME
- default "maxbcm"
-
-endif
diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg
index cc05792..1f748db 100644
--- a/board/maxbcm/kwbimage.cfg
+++ b/board/maxbcm/kwbimage.cfg
@@ -9,4 +9,4 @@
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c
index 119ba4c..db6ad99 100644
--- a/board/maxbcm/maxbcm.c
+++ b/board/maxbcm/maxbcm.c
@@ -138,17 +138,15 @@
return 0;
}
-#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E6185 switch */
-void reset_phy(void)
+int board_phy_config(struct phy_device *phydev)
{
- char *name = "neta0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* todo: fill this with the real setup / config code */
-
- printf("88E6185 Initialized on %s\n", name);
+ /*
+ * todo:
+ * Fill this with the real setup / config code.
+ * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+ * for details.
+ */
+ printf("88E6185 Initialized\n");
+ return 0;
}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/micronas/vct/vct.h b/board/micronas/vct/vct.h
index 0a1c5fc..67da6a8 100644
--- a/board/micronas/vct/vct.h
+++ b/board/micronas/vct/vct.h
@@ -80,12 +80,14 @@
*/
static inline void reg_write(u32 addr, u32 data)
{
- __raw_writel(data, addr + REG_GLOBAL_START_ADDR);
+ void *reg = (void *)(addr + REG_GLOBAL_START_ADDR);
+ __raw_writel(data, reg);
}
static inline u32 reg_read(u32 addr)
{
- return __raw_readl(addr + REG_GLOBAL_START_ADDR);
+ const void *reg = (const void *)(addr + REG_GLOBAL_START_ADDR);
+ return __raw_readl(reg);
}
#endif /* _VCT_H */
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 6b96bd5..2262175 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -698,12 +698,12 @@
s=getenv ("serial#");
#ifdef CONFIG_PIP405
if (!s || strncmp (s, "PIP405", 6)) {
- sprintf(buf,"### No HW ID - assuming PIP405");
+ strcpy(buf,"### No HW ID - assuming PIP405");
}
#endif
#ifdef CONFIG_MIP405
if (!s || strncmp (s, "MIP405", 6)) {
- sprintf(buf,"### No HW ID - assuming MIP405");
+ strcpy(buf,"### No HW ID - assuming MIP405");
}
#endif
else {
@@ -718,7 +718,7 @@
}
buf[i++] = *s;
}
- sprintf(&buf[i]," SN ");
+ strcpy(&buf[i]," SN ");
i+=4;
for (; s < e; ++s) {
buf[i++] = *s;
@@ -744,7 +744,7 @@
ctfb.modeIdent);
return;
case 1:
- sprintf (buf, "%s",CONFIG_IDENT_STRING);
+ strcpy(buf, CONFIG_IDENT_STRING);
sprintf (info, " %s", &buf[1]);
return;
}
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
index 1540526..ba15e2e 100644
--- a/board/nvidia/cardhu/cardhu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -13,7 +13,6 @@
#include <asm/gpio.h>
#include "pinmux-config-cardhu.h"
#include <i2c.h>
-#include <netdev.h>
#define PMU_I2C_ADDRESS 0x2D
#define MAX_I2C_RETRY 3
@@ -129,9 +128,4 @@
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* PCI */
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
index 255e4cd..c21c30c 100644
--- a/board/nvidia/cardhu/pinmux-config-cardhu.h
+++ b/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _PINMUX_CONFIG_CARDHU_H_
diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c
index d7c1a69..e4c4bfb 100644
--- a/board/nvidia/dalmore/dalmore.c
+++ b/board/nvidia/dalmore/dalmore.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h
index 891ac07..294731e 100644
--- a/board/nvidia/dalmore/pinmux-config-dalmore.h
+++ b/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _PINMUX_CONFIG_DALMORE_H_
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c
index 52425a8..6f189aa 100644
--- a/board/nvidia/jetson-tk1/jetson-tk1.c
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -6,7 +6,6 @@
*/
#include <common.h>
-#include <netdev.h>
#include <power/as3722.h>
#include <asm/arch/gpio.h>
@@ -73,9 +72,4 @@
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* PCI */
diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c
index 57f577d8..0f587ea 100644
--- a/board/nvidia/p2371-2180/p2371-2180.c
+++ b/board/nvidia/p2371-2180/p2371-2180.c
@@ -6,7 +6,6 @@
*/
#include <common.h>
-#include <netdev.h>
#include <i2c.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
@@ -73,9 +72,4 @@
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* PCI */
diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S
index b145e43..98d9536 100644
--- a/board/pb1x00/lowlevel_init.S
+++ b/board/pb1x00/lowlevel_init.S
@@ -1,8 +1,8 @@
/* Memory sub-system initialization code */
#include <config.h>
+#include <mach/au1x00.h>
#include <asm/regdef.h>
-#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#define AU1500_SYS_ADDR 0xB1900000
diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
index 34814c4..eb92914 100644
--- a/board/pb1x00/pb1x00.c
+++ b/board/pb1x00/pb1x00.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <command.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index d943d63..1600568 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -10,7 +10,7 @@
#include <asm/gpio.h>
#include <asm/arch/mmc.h>
#include <power/pmic.h>
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
#include <asm/arch/cpu.h>
#include <power/max8998_pmic.h>
#include <samsung/misc.h>
@@ -183,7 +183,7 @@
return 0;
}
-struct s3c_plat_otg_data s5pc110_otg_data = {
+struct dwc2_plat_otg_data s5pc110_otg_data = {
.phy_control = s5pc1xx_phy_control,
.regs_phy = S5PC110_PHY_BASE,
.regs_otg = S5PC110_OTG_BASE,
@@ -193,7 +193,7 @@
int board_usb_init(int index, enum usb_init_type init)
{
debug("USB_udc_probe\n");
- return s3c_udc_probe(&s5pc110_otg_data);
+ return dwc2_udc_probe(&s5pc110_otg_data);
}
#endif
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index 36d493d5..b4cb332 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -19,7 +19,7 @@
#include <errno.h>
#include <mmc.h>
#include <usb.h>
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
#include <samsung/misc.h>
#include "setup.h"
@@ -452,7 +452,7 @@
return regulator_set_mode(dev, OPMODE_LPM);
}
-struct s3c_plat_otg_data s5pc210_otg_data = {
+struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4X12_USBPHY_BASE,
.regs_otg = EXYNOS4X12_USBOTG_BASE,
@@ -510,6 +510,6 @@
}
#endif
debug("USB_udc_probe\n");
- return s3c_udc_probe(&s5pc210_otg_data);
+ return dwc2_udc_probe(&s5pc210_otg_data);
}
#endif
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index e163e45..54d01ec 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -18,7 +18,7 @@
#include <asm/arch/watchdog.h>
#include <asm/arch/power.h>
#include <power/pmic.h>
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
#include <power/max8997_pmic.h>
#include <power/max8997_muic.h>
#include <power/battery.h>
@@ -41,7 +41,7 @@
#endif
static void check_hw_revision(void);
-struct s3c_plat_otg_data s5pc210_otg_data;
+struct dwc2_plat_otg_data s5pc210_otg_data;
int exynos_init(void)
{
@@ -419,7 +419,7 @@
return 0;
}
-struct s3c_plat_otg_data s5pc210_otg_data = {
+struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4_USBPHY_BASE,
.regs_otg = EXYNOS4_USBOTG_BASE,
@@ -430,7 +430,7 @@
int board_usb_init(int index, enum usb_init_type init)
{
debug("USB_udc_probe\n");
- return s3c_udc_probe(&s5pc210_otg_data);
+ return dwc2_udc_probe(&s5pc210_otg_data);
}
int g_dnl_board_usb_cable_connected(void)
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index a737749..7b28ae8 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -21,7 +21,7 @@
#include <libtizen.h>
#include <errno.h>
#include <usb.h>
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
#include <usb_mass_storage.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -303,7 +303,7 @@
return 0;
}
-struct s3c_plat_otg_data s5pc210_otg_data = {
+struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4X12_USBPHY_BASE,
.regs_otg = EXYNOS4X12_USBOTG_BASE,
@@ -314,7 +314,7 @@
int board_usb_init(int index, enum usb_init_type init)
{
debug("USB_udc_probe\n");
- return s3c_udc_probe(&s5pc210_otg_data);
+ return dwc2_udc_probe(&s5pc210_otg_data);
}
int g_dnl_board_usb_cable_connected(void)
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index df46713..426ae14 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -17,7 +17,7 @@
#include <ld9040.h>
#include <power/pmic.h>
#include <usb.h>
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
#include <asm/arch/cpu.h>
#include <power/max8998_pmic.h>
#include <libtizen.h>
@@ -179,7 +179,7 @@
return 0;
}
-struct s3c_plat_otg_data s5pc210_otg_data = {
+struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4_USBPHY_BASE,
.regs_otg = EXYNOS4_USBOTG_BASE,
@@ -191,7 +191,7 @@
int board_usb_init(int index, enum usb_init_type init)
{
debug("USB_udc_probe\n");
- return s3c_udc_probe(&s5pc210_otg_data);
+ return dwc2_udc_probe(&s5pc210_otg_data);
}
int exynos_early_init_f(void)
@@ -355,10 +355,10 @@
}
/* Request soft I2C gpios */
- sprintf(buf, "soft_i2c_scl");
+ strcpy(buf, "soft_i2c_scl");
gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
- sprintf(buf, "soft_i2c_sda");
+ strcpy(buf, "soft_i2c_sda");
gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
check_hw_revision();
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 24cc776..2ffafa8 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
index b31ea34..0d5783a 100644
--- a/board/sbc8641d/ddr.c
+++ b/board/sbc8641d/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index f94e3e5..b3c666c 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -480,7 +480,7 @@
sprintf(tmp, "%s_%s", factory_dat.asn,
factory_dat.comp_version);
else
- sprintf(tmp, "QMX7.E38_4.0");
+ strcpy(tmp, "QMX7.E38_4.0");
ret = setenv("boardid", tmp);
if (ret)
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
index 6bad4da..fe8a8bf 100644
--- a/board/socrates/ddr.c
+++ b/board/socrates/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/solidrun/clearfog/MAINTAINERS b/board/solidrun/clearfog/MAINTAINERS
new file mode 100644
index 0000000..298e501
--- /dev/null
+++ b/board/solidrun/clearfog/MAINTAINERS
@@ -0,0 +1,6 @@
+CLEARFOG BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/soldrun/clearfog/
+F: include/configs/clearfog.h
+F: configs/clearfog_defconfig
diff --git a/board/solidrun/clearfog/Makefile b/board/solidrun/clearfog/Makefile
new file mode 100644
index 0000000..1920d6b
--- /dev/null
+++ b/board/solidrun/clearfog/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := clearfog.o
diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README
new file mode 100644
index 0000000..2cfa5bf
--- /dev/null
+++ b/board/solidrun/clearfog/README
@@ -0,0 +1,18 @@
+Update from original Marvell U-Boot to mainline U-Boot:
+-------------------------------------------------------
+
+Generate the U-Boot image with these commands:
+
+$ make clearfog_defconfig
+$ make
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+Now all you need to do is copy this image on a SD card.
+For example with this command:
+
+$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
+
+Please use the correct device node for your setup instead
+of "/dev/sdX" here!
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
new file mode 100644
index 0000000..2773f59
--- /dev/null
+++ b/board/solidrun/clearfog/clearfog.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ETH_PHY_CTRL_REG 0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-15t1-clearfog"
+ */
+#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
+#define BOARD_GPP_OUT_ENA_MID 0xffffffff
+
+#define BOARD_GPP_OUT_VAL_LOW 0x0
+#define BOARD_GPP_OUT_VAL_MID 0x0
+#define BOARD_GPP_POL_LOW 0x0
+#define BOARD_GPP_POL_MID 0x0
+
+/* IO expander on Marvell GP board includes e.g. fan enabling */
+struct marvell_io_exp {
+ u8 chip;
+ u8 addr;
+ u8 val;
+};
+
+static struct marvell_io_exp io_exp[] = {
+ { 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */
+ { 0x20, 6, 0xf9 },
+ { 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */
+ { 0x20, 6, 0xb9 },
+ { 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */
+ { 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */
+};
+
+static struct serdes_map board_serdes_map[] = {
+ {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+ {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+ {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+ *serdes_map_array = board_serdes_map;
+ *count = ARRAY_SIZE(board_serdes_map);
+ return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map = {
+ 0x1, /* active interfaces */
+ /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+ { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+ SPEED_BIN_DDR_1600K, /* speed_bin */
+ BUS_WIDTH_16, /* memory_width */
+ MEM_4G, /* mem_size */
+ DDR_FREQ_800, /* frequency */
+ 0, 0, /* cas_l cas_wl */
+ HWS_TEMP_LOW} }, /* temperature */
+ 5, /* Num Of Bus Per Interface*/
+ BUS_MASK_32BIT /* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+ /* Return the board topology as defined in the board code */
+ return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+ writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+ writel(0x10400011, MVEBU_MPP_BASE + 0x08);
+ writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
+ writel(0x44400002, MVEBU_MPP_BASE + 0x10);
+ writel(0x41144004, MVEBU_MPP_BASE + 0x14);
+ writel(0x40333333, MVEBU_MPP_BASE + 0x18);
+ writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+ /* Set GPP Out value */
+ writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ int i;
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* Toggle GPIO41 to reset onboard switch and phy */
+ clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
+ clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
+ mdelay(1);
+ setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
+ mdelay(10);
+
+ /* Init I2C IO expanders */
+ for (i = 0; i < ARRAY_SIZE(io_exp); i++)
+ i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: SolidRun ClearFog\n");
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in controller(s) come first */
+ return pci_eth_init(bis);
+}
diff --git a/board/solidrun/clearfog/kwbimage.cfg b/board/solidrun/clearfog/kwbimage.cfg
new file mode 100644
index 0000000..c650c2c
--- /dev/null
+++ b/board/solidrun/clearfog/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM sdio
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS
index a3506c2..81f82bc 100644
--- a/board/solidrun/mx6cuboxi/MAINTAINERS
+++ b/board/solidrun/mx6cuboxi/MAINTAINERS
@@ -1,5 +1,5 @@
MX6CUBOXI BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/solidrun/mx6cuboxi/
F: include/configs/mx6cuboxi.h
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index fc37f1e..823b70f 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -143,8 +143,9 @@
SETUP_IOMUX_PADS(enet_pads);
gpio_direction_output(ETH_PHY_RESET, 0);
- mdelay(2);
+ mdelay(10);
gpio_set_value(ETH_PHY_RESET, 1);
+ udelay(100);
}
int board_phy_config(struct phy_device *phydev)
@@ -594,10 +595,6 @@
writel(0x007F007F, &iomux->gpr[7]);
}
-/*
- * This section requires the differentiation between Solidrun mx6 boards, but
- * for now, it will configure only for the mx6dual hummingboard version.
- */
static void spl_dram_init(int width)
{
struct mx6_ddr_sysinfo sysinfo = {
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index fc0918f..858a9ca 100644
--- a/board/spear/spear600/spear600.c
+++ b/board/spear/spear600/spear600.c
@@ -48,9 +48,6 @@
#if defined(CONFIG_ETH_DESIGNWARE)
u32 interface = PHY_INTERFACE_MODE_MII;
-#if defined(CONFIG_DW_AUTONEG)
- interface = PHY_INTERFACE_MODE_GMII;
-#endif
if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c
index 9f89584..617dffa 100644
--- a/board/sr1500/socfpga.c
+++ b/board/sr1500/socfpga.c
@@ -5,27 +5,10 @@
*/
#include <common.h>
-#include <i2c.h>
-#include <miiphy.h>
#include <asm/arch/reset_manager.h>
#include <asm/gpio.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
int board_early_init_f(void)
{
int ret;
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 57acc20..131c341 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -25,6 +25,7 @@
F: configs/Auxtek-T003_defconfig
F: configs/Auxtek-T004_defconfig
F: configs/CHIP_defconfig
+F: configs/Empire_electronix_d709_defconfig
F: configs/inet98v_rev2_defconfig
F: configs/mk802_a10s_defconfig
F: configs/q8_a13_tablet_defconfig
diff --git a/board/terasic/de0-nano-soc/socfpga.c b/board/terasic/de0-nano-soc/socfpga.c
index 85700b0..97fb902 100644
--- a/board/terasic/de0-nano-soc/socfpga.c
+++ b/board/terasic/de0-nano-soc/socfpga.c
@@ -3,70 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9031
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x70);
- if (ret)
- return ret;
-
- ret = ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x7777);
- if (ret)
- return ret;
-
- ret = ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0);
- if (ret)
- return ret;
-
- ret = ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x03FC);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
diff --git a/board/terasic/sockit/socfpga.c b/board/terasic/sockit/socfpga.c
index a1dbc49..97fb902 100644
--- a/board/terasic/sockit/socfpga.c
+++ b/board/terasic/sockit/socfpga.c
@@ -3,83 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/s3c_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return s3c_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c
index 879006f..3f56971 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -14,7 +14,6 @@
#include <asm/io.h>
#include <dm.h>
#include <i2c.h>
-#include <netdev.h>
#include "pinmux-config-apalis_t30.h"
@@ -92,9 +91,4 @@
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* CONFIG_PCI_TEGRA */
diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
index c988d39..16d1a64 100644
--- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
+++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2014, Marcel Ziswiler
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _PINMUX_CONFIG_APALIS_T30_H_
diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
index 4e73c07..407c6c3 100644
--- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
+++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2013-2014, Stefan Agner
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _PINMUX_CONFIG_COLIBRI_T30_H_
diff --git a/board/udoo/MAINTAINERS b/board/udoo/MAINTAINERS
index 789e98f..b05243c 100644
--- a/board/udoo/MAINTAINERS
+++ b/board/udoo/MAINTAINERS
@@ -1,5 +1,5 @@
UDOO BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/udoo/
F: include/configs/udoo.h
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index 638d14f..ac44e32 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -346,7 +346,7 @@
/* get production data */
if (read_eeprom(&header)) {
- sprintf(model, "211");
+ strcpy(model, "211");
} else {
sprintf(model, "%d", header.SystemId);
if (header.SystemId == 215) {
diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS
index 0680517..d7cbae8 100644
--- a/board/wandboard/MAINTAINERS
+++ b/board/wandboard/MAINTAINERS
@@ -1,5 +1,5 @@
WANDBOARD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/wandboard/
F: include/configs/wandboard.h
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 0af63d2..ac001ed 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -121,8 +121,9 @@
/* Reset AR8031 PHY */
gpio_direction_output(ETH_PHY_RESET, 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(ETH_PHY_RESET, 1);
+ udelay(100);
}
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
@@ -187,39 +188,6 @@
return 0;
}
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
#if defined(CONFIG_VIDEO_IPUV3)
struct i2c_pads_info mx6q_i2c2_pad_info = {
.scl = {
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
index 5c5eadc..b73dd81 100644
--- a/board/xes/xpedite520x/ddr.c
+++ b/board/xes/xpedite520x/ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index 0c8bd7d..dfa6293 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -69,6 +69,7 @@
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_XILINX_GPIO
if (reset_pin != -1)
gpio_direction_output(reset_pin, 1);
@@ -77,7 +78,7 @@
#ifdef CONFIG_XILINX_TB_WATCHDOG
hw_watchdog_disable();
#endif
-
+#endif
puts ("Reseting board\n");
__asm__ __volatile__ (" mts rmsr, r0;" \
"bra r0");
@@ -122,40 +123,5 @@
txpp, rxpp);
#endif
-#ifdef CONFIG_XILINX_LL_TEMAC
-# ifdef XILINX_LLTEMAC_BASEADDR
-# ifdef XILINX_LLTEMAC_FIFO_BASEADDR
- ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
- XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
-# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
-# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
- ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
- XILINX_LL_TEMAC_M_SDMA_DCR,
- XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
-# else
- ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
- XILINX_LL_TEMAC_M_SDMA_PLB,
- XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
-# endif
-# endif
-# endif
-# ifdef XILINX_LLTEMAC_BASEADDR1
-# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
- ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
- XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
-# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
-# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
- ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
- XILINX_LL_TEMAC_M_SDMA_DCR,
- XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
-# else
- ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
- XILINX_LL_TEMAC_M_SDMA_PLB,
- XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
-# endif
-# endif
-# endif
-#endif
-
return ret;
}
diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
index d6d0d67..8ba146c 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -56,12 +56,6 @@
/* Ethernet controller is Ethernet_MAC */
#define XILINX_EMACLITE_BASEADDR 0x40C00000
-/* LL_TEMAC Ethernet controller */
-#define XILINX_LLTEMAC_BASEADDR 0x44000000
-#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180
-#define XILINX_LLTEMAC_BASEADDR1 0x44200000
-#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000
-
/* Watchdog IP is wxi_timebase_wdt_0 */
#define XILINX_WATCHDOG_BASEADDR 0x50000000
#define XILINX_WATCHDOG_IRQ 1
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 88047ec..eab9303 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -12,6 +12,7 @@
hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED) := MicroZed_hw_platform
hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702) := ZC702_hw_platform
hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706) := ZC706_hw_platform
+hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO) := zybo_hw_platform
# If you want to use customized ps7_init_gpl.c/h,
# enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/.
# This line must be placed at the bottom of the list because
diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c
index ed75872..eb29002 100644
--- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c
@@ -1,18 +1,7 @@
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
******************************************************************************/
diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h
index c61cf2a..bdea5a0 100644
--- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h
@@ -3,18 +3,7 @@
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
*******************************************************************************/
diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c
index ac5e0bc..abfd911 100644
--- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c
@@ -1,18 +1,7 @@
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
******************************************************************************/
diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h
index 584e1e1..16fa810 100644
--- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h
@@ -3,18 +3,7 @@
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
*******************************************************************************/
diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c
index 98bad67..77fd949 100644
--- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c
@@ -1,18 +1,7 @@
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
******************************************************************************/
diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h
index 6c94c42..8527eef 100644
--- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h
@@ -3,18 +3,7 @@
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
*******************************************************************************/
diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c
index 34485db..f4f45be 100644
--- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c
@@ -1,18 +1,7 @@
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
******************************************************************************/
diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h
index cd8ead4..9b41e28 100644
--- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h
@@ -3,18 +3,7 @@
*
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
+* SPDX-License-Identifier: GPL-2.0+
*
*
*******************************************************************************/
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
new file mode 100644
index 0000000..2c0feca
--- /dev/null
+++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
@@ -0,0 +1,11948 @@
+/*
+ * Copyright (c) Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: PLL SLCR REGISTERS */
+ /* .. .. START: ARM PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x177 */
+ /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x1a */
+ /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. ARM_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. SRCSEL = 0x0 */
+ /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. .. DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
+ /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
+ /* .. .. .. CPU_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. .. CPU_1XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. .. CPU_PERI_CLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ /* .. .. FINISH: ARM PLL INIT */
+ /* .. .. START: DDR PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1db */
+ /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x15 */
+ /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. DDR_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. DDR_3XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. DDR_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+ /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+ /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ /* .. .. FINISH: DDR PLL INIT */
+ /* .. .. START: IO PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1f4 */
+ /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x14 */
+ /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. IO_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. FINISH: IO PLL INIT */
+ /* .. FINISH: PLL SLCR REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: CLOCK CONTROL SLCR REGISTERS */
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000128[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. DIVISOR0 = 0x34 */
+ /* .. ==> 0XF8000128[13:8] = 0x00000034U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
+ /* .. DIVISOR1 = 0x2 */
+ /* .. ==> 0XF8000128[25:20] = 0x00000002U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000138[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000138[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000140[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000140[6:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x8 */
+ /* .. ==> 0XF8000140[13:8] = 0x00000008U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
+ /* .. DIVISOR1 = 0x1 */
+ /* .. ==> 0XF8000140[25:20] = 0x00000001U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF800014C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF800014C[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x5 */
+ /* .. ==> 0XF800014C[13:8] = 0x00000005U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ /* .. CLKACT0 = 0x1 */
+ /* .. ==> 0XF8000150[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. CLKACT1 = 0x0 */
+ /* .. ==> 0XF8000150[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000150[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x14 */
+ /* .. ==> 0XF8000150[13:8] = 0x00000014U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+ /* .. CLKACT0 = 0x0 */
+ /* .. ==> 0XF8000154[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. CLKACT1 = 0x1 */
+ /* .. ==> 0XF8000154[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000154[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x14 */
+ /* .. ==> 0XF8000154[13:8] = 0x00000014U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U),
+ /* .. .. START: TRACE CLOCK */
+ /* .. .. FINISH: TRACE CLOCK */
+ /* .. .. CLKACT = 0x1 */
+ /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR = 0x5 */
+ /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0xa */
+ /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ /* .. .. SRCSEL = 0x3 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */
+ /* .. .. DIVISOR0 = 0x6 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
+ /* .. .. SRCSEL = 0x2 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */
+ /* .. .. DIVISOR0 = 0x35 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */
+ /* .. .. DIVISOR1 = 0x2 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0xa */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+ /* .. .. CLK_621_TRUE = 0x1 */
+ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ /* .. .. DMA_CPU_2XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. USB0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. USB1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
+ /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
+ /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
+ /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. UART0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. UART1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
+ /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
+ /* .. .. SMC_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+ /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+ /* .. START: THIS SHOULD BE BLANK */
+ /* .. FINISH: THIS SHOULD BE BLANK */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: DDR INITIALIZATION */
+ /* .. .. START: LOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ /* .. .. FINISH: LOCK DDR */
+ /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+ /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
+ /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
+ /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+ /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
+ /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
+ /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
+ /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+ /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
+ /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+ /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ /* .. .. reg_ddrc_t_rc = 0x1a */
+ /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+ /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
+ /* .. .. reg_ddrc_t_rfc_min = 0x54 */
+ /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+ /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
+ /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+ /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+ /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+ /* .. .. reg_ddrc_wr2pre = 0x12 */
+ /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
+ /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+ /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_t_faw = 0x15 */
+ /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+ /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
+ /* .. .. reg_ddrc_t_ras_max = 0x23 */
+ /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+ /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
+ /* .. .. reg_ddrc_t_ras_min = 0x13 */
+ /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
+ /* .. .. reg_ddrc_t_cke = 0x4 */
+ /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+ /* .. .. reg_ddrc_write_latency = 0x5 */
+ /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_rd2wr = 0x7 */
+ /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
+ /* .. .. reg_ddrc_wr2rd = 0xe */
+ /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+ /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
+ /* .. .. reg_ddrc_t_xp = 0x4 */
+ /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
+ /* .. .. reg_ddrc_pad_pd = 0x0 */
+ /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd2pre = 0x4 */
+ /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
+ /* .. .. reg_ddrc_t_rcd = 0x7 */
+ /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ /* .. .. reg_ddrc_t_ccd = 0x4 */
+ /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
+ /* .. .. reg_ddrc_t_rrd = 0x6 */
+ /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_refresh_margin = 0x2 */
+ /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_rp = 0x7 */
+ /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
+ /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+ /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+ /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_mobile = 0x0 */
+ /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
+ /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_read_latency = 0x7 */
+ /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+ /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
+ /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+ /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+ /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_prefer_write = 0x0 */
+ /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_wr = 0x0 */
+ /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_addr = 0x0 */
+ /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_data = 0x0 */
+ /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+ /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_type = 0x0 */
+ /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+ /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+ /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+ /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_t_mrd = 0x4 */
+ /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ /* .. .. reg_ddrc_emr2 = 0x8 */
+ /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
+ /* .. .. reg_ddrc_emr3 = 0x0 */
+ /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ /* .. .. reg_ddrc_mr = 0x930 */
+ /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
+ /* .. .. reg_ddrc_emr = 0x4 */
+ /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ /* .. .. reg_ddrc_burst_rdwr = 0x4 */
+ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */
+ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
+ /* .. .. reg_ddrc_burstchop = 0x0 */
+ /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U),
+ /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_dq = 0x0 */
+ /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+ /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+ /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
+ /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+ /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
+ /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+ /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+ /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+ /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+ /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+ /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+ /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+ /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+ /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+ /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+ /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+ /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+ /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+ /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
+ /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+ /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+ /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+ /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+ /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ /* .. .. reg_phy_rd_local_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
+ /* .. .. reg_phy_idle_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
+ /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
+ /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+ /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
+ /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+ /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_fixed_re = 0x1 */
+ /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+ /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+ /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_phy_clk_stall_level = 0x0 */
+ /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+ /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+ /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
+ /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+ /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+ /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+ /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ /* .. .. reg_ddrc_pageclose = 0x0 */
+ /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+ /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+ /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
+ /* .. .. reg_ddrc_auto_pre_en = 0x0 */
+ /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_refresh_update_level = 0x0 */
+ /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_wc = 0x0 */
+ /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+ /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_selfref_en = 0x0 */
+ /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+ /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
+ /* .. .. reg_arb_go2critical_en = 0x1 */
+ /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+ /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
+ /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+ /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
+ /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+ /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+ /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
+ /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+ /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+ /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+ /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
+ /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+ /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
+ /* .. .. reg_ddrc_t_cksre = 0x6 */
+ /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_t_cksrx = 0x6 */
+ /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_t_ckesr = 0x4 */
+ /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ /* .. .. reg_ddrc_t_ckpde = 0x2 */
+ /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_ckpdx = 0x2 */
+ /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
+ /* .. .. reg_ddrc_t_ckdpde = 0x2 */
+ /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+ /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
+ /* .. .. reg_ddrc_t_ckcsx = 0x3 */
+ /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+ /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_ddr3 = 0x1 */
+ /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_mod = 0x200 */
+ /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+ /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
+ /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+ /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+ /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+ /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ /* .. .. t_zq_short_interval_x1024 = 0xc845 */
+ /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+ /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
+ /* .. .. dram_rstn_x1024 = 0x67 */
+ /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+ /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ /* .. .. deeppowerdown_en = 0x0 */
+ /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. deeppowerdown_to_x1024 = 0xff */
+ /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+ /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
+ /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
+ /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+ /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+ /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ /* .. .. reg_ddrc_skip_ocd = 0x1 */
+ /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+ /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+ /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+ /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+ /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ /* .. .. START: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ /* .. .. FINISH: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ /* .. .. CORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+ /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ /* .. .. STAT_NUM_CORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
+ /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_ecc_mode = 0x0 */
+ /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_scrub = 0x1 */
+ /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ /* .. .. reg_phy_dif_on = 0x0 */
+ /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_dif_off = 0x0 */
+ /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+ /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+ /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+ /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+ /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+ /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+ /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+ /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+ /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+ /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+ /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+ /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+ /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+ /* .. .. reg_phy_bl2 = 0x0 */
+ /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_at_spd_atpg = 0x0 */
+ /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_enable = 0x0 */
+ /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_force_err = 0x0 */
+ /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_mode = 0x0 */
+ /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. .. reg_phy_invert_clkout = 0x1 */
+ /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. .. reg_phy_sel_logic = 0x0 */
+ /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+ /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
+ /* .. .. reg_phy_ctrl_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
+ /* .. .. reg_phy_lpddr = 0x0 */
+ /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_cmd_latency = 0x0 */
+ /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ /* .. .. reg_phy_wr_rl_delay = 0x2 */
+ /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
+ /* .. .. reg_phy_rd_rl_delay = 0x4 */
+ /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
+ /* .. .. reg_phy_dll_lock_diff = 0xf */
+ /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
+ /* .. .. reg_phy_use_wr_level = 0x1 */
+ /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
+ /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
+ /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+ /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_dis_calib_rst = 0x0 */
+ /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ /* .. .. reg_arb_page_addr_mask = 0x0 */
+ /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_ddrc_lpddr2 = 0x0 */
+ /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_derate_enable = 0x0 */
+ /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr4_margin = 0x0 */
+ /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+ /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+ /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
+ /* .. .. reg_ddrc_t_mrw = 0x5 */
+ /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+ /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
+ /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ /* .. .. START: POLL ON DCI STATUS */
+ /* .. .. DONE = 1 */
+ /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ /* .. .. FINISH: POLL ON DCI STATUS */
+ /* .. .. START: UNLOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0x1 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ /* .. .. FINISH: UNLOCK DDR */
+ /* .. .. START: CHECK DDR STATUS */
+ /* .. .. ddrc_reg_operating_mode = 1 */
+ /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ /* .. .. FINISH: CHECK DDR STATUS */
+ /* .. FINISH: DDR INITIALIZATION */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: OCM REMAPPING */
+ /* .. VREF_EN = 0x1 */
+ /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. VREF_SEL = 0x0 */
+ /* .. ==> 0XF8000B00[6:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
+ /* .. FINISH: OCM REMAPPING */
+ /* .. START: DDRIOB SETTINGS */
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCI_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCI_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCI_TYPE = 0x3 */
+ /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCI_TYPE = 0x3 */
+ /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCI_TYPE = 0x3 */
+ /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCI_TYPE = 0x3 */
+ /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCI_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ /* .. reserved_DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. reserved_DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. reserved_SLEW_P = 0x3 */
+ /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
+ /* .. reserved_SLEW_N = 0x3 */
+ /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
+ /* .. reserved_GTL = 0x0 */
+ /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. reserved_RTERM = 0x0 */
+ /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ /* .. reserved_DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. reserved_DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. reserved_SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. reserved_SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. reserved_GTL = 0x0 */
+ /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. reserved_RTERM = 0x0 */
+ /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. reserved_DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. reserved_DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. reserved_SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. reserved_SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. reserved_GTL = 0x0 */
+ /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. reserved_RTERM = 0x0 */
+ /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. reserved_DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. reserved_DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. reserved_SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. reserved_SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. reserved_GTL = 0x0 */
+ /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. reserved_RTERM = 0x0 */
+ /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. VREF_INT_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. VREF_SEL = 0x0 */
+ /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+ /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
+ /* .. VREF_EXT_EN = 0x3 */
+ /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. reserved_VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. REFIO_EN = 0x1 */
+ /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. reserved_REFIO_TEST = 0x0 */
+ /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
+ /* .. reserved_REFIO_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. reserved_DRST_B_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. reserved_CKE_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+ /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ /* .. .. START: ASSERT RESET */
+ /* .. .. RESET = 1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ /* .. .. FINISH: ASSERT RESET */
+ /* .. .. START: DEASSERT RESET */
+ /* .. .. RESET = 0 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reserved_VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ /* .. .. FINISH: DEASSERT RESET */
+ /* .. .. RESET = 0x1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. ENABLE = 0x1 */
+ /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. reserved_VRP_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reserved_VRN_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reserved_VRP_OUT = 0x0 */
+ /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reserved_VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. NREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. .. NREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
+ /* .. .. NREF_OPT4 = 0x1 */
+ /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
+ /* .. .. PREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
+ /* .. .. PREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
+ /* .. .. UPDATE_CONTROL = 0x0 */
+ /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. reserved_INIT_COMPLETE = 0x0 */
+ /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. reserved_TST_CLK = 0x0 */
+ /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. reserved_TST_HLN = 0x0 */
+ /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. reserved_TST_HLP = 0x0 */
+ /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. reserved_TST_RST = 0x0 */
+ /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reserved_INT_DCI_EN = 0x0 */
+ /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ /* .. FINISH: DDRIOB SETTINGS */
+ /* .. START: MIO PROGRAMMING */
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000704[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000704[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000704[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000704[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000704[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000704[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000704[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000704[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000704[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000708[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000708[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000708[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000708[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000708[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000708[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000708[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000708[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000708[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800070C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800070C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800070C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800070C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800070C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800070C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800070C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800070C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800070C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000710[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000710[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000710[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000710[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000710[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000710[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000710[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000710[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000710[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000714[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000714[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000714[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000714[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000714[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000714[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000714[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000714[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000714[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000718[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000718[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000718[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000718[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000718[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000718[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000718[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000718[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000718[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000740[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000740[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000740[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000740[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000740[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000740[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000740[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000740[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000740[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000744[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000744[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000744[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000744[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000744[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000744[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000744[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000744[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000744[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000748[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000748[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000748[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000748[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000748[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000748[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000748[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000748[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000748[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800074C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800074C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800074C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800074C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800074C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800074C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800074C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800074C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF800074C[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000750[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000750[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000750[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000750[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000750[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000750[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000750[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000750[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000750[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000754[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000754[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000754[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000754[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000754[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000754[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000754[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000754[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000754[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000758[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000758[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000758[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000758[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000758[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000758[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000758[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000758[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000758[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800075C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800075C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800075C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800075C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800075C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800075C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800075C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800075C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800075C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000760[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000760[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000760[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000760[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000760[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000760[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000760[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000760[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000760[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000764[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000764[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000764[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000764[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000764[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000764[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000764[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000764[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000764[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000768[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000768[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000768[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000768[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000768[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000768[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000768[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000768[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000768[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800076C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800076C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800076C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800076C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800076C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800076C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800076C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800076C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800076C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000770[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000770[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000770[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000770[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000770[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000770[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000770[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000770[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000770[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000774[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000774[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000774[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000774[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000774[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000774[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000774[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000774[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000774[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000778[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000778[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000778[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000778[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000778[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000778[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000778[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000778[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000778[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800077C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800077C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800077C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800077C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800077C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800077C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800077C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800077C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800077C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000780[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000780[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000780[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000780[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000780[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000780[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000780[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000780[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000780[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000784[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000784[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000784[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000784[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000784[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000784[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000784[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000784[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000784[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000788[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000788[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000788[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000788[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000788[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000788[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000788[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000788[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000788[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800078C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800078C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800078C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800078C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800078C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800078C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800078C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800078C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800078C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000790[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000790[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000790[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000790[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000790[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000790[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000790[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000790[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000790[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000794[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000794[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000794[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000794[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000794[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000794[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000794[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000794[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000794[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000798[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000798[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000798[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000798[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000798[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000798[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000798[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000798[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000798[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800079C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800079C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800079C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800079C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800079C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800079C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800079C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800079C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800079C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+ /* .. SDIO0_WP_SEL = 55 */
+ /* .. ==> 0XF8000830[5:0] = 0x00000037U */
+ /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
+ /* .. SDIO0_CD_SEL = 47 */
+ /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+ /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+ /* .. FINISH: MIO PROGRAMMING */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* .. START: SRAM/NOR SET OPMODE */
+ /* .. FINISH: SRAM/NOR SET OPMODE */
+ /* .. START: UART REGISTERS */
+ /* .. BDIV = 0x6 */
+ /* .. ==> 0XE0001034[7:0] = 0x00000006U */
+ /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ /* .. CD = 0x3e */
+ /* .. ==> 0XE0001018[15:0] = 0x0000003EU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU),
+ /* .. STPBRK = 0x0 */
+ /* .. ==> 0XE0001000[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. STTBRK = 0x0 */
+ /* .. ==> 0XE0001000[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. RSTTO = 0x0 */
+ /* .. ==> 0XE0001000[6:6] = 0x00000000U */
+ /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. TXDIS = 0x0 */
+ /* .. ==> 0XE0001000[5:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. TXEN = 0x1 */
+ /* .. ==> 0XE0001000[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. RXDIS = 0x0 */
+ /* .. ==> 0XE0001000[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. RXEN = 0x1 */
+ /* .. ==> 0XE0001000[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. TXRES = 0x1 */
+ /* .. ==> 0XE0001000[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. RXRES = 0x1 */
+ /* .. ==> 0XE0001000[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ /* .. CHMODE = 0x0 */
+ /* .. ==> 0XE0001004[9:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
+ /* .. NBSTOP = 0x0 */
+ /* .. ==> 0XE0001004[7:6] = 0x00000000U */
+ /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. PAR = 0x4 */
+ /* .. ==> 0XE0001004[5:3] = 0x00000004U */
+ /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
+ /* .. CHRL = 0x0 */
+ /* .. ==> 0XE0001004[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. CLKS = 0x0 */
+ /* .. ==> 0XE0001004[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+ /* .. FINISH: UART REGISTERS */
+ /* .. START: TPIU WIDTH IN CASE OF EMIO */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. .. START: TRACE CURRENT PORT SIZE */
+ /* .. .. a = 2 */
+ /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
+ /* .. .. FINISH: TRACE CURRENT PORT SIZE */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0X0 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
+ /* .. START: QSPI REGISTERS */
+ /* .. Holdb_dr = 1 */
+ /* .. ==> 0XE000D000[19:19] = 0x00000001U */
+ /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ /* .. FINISH: QSPI REGISTERS */
+ /* .. START: PL POWER ON RESET REGISTERS */
+ /* .. PCFG_POR_CNT_4K = 0 */
+ /* .. ==> 0XF8007000[29:29] = 0x00000000U */
+ /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ /* .. FINISH: PL POWER ON RESET REGISTERS */
+ /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* .. .. START: NAND SET CYCLE */
+ /* .. .. FINISH: NAND SET CYCLE */
+ /* .. .. START: OPMODE */
+ /* .. .. FINISH: OPMODE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS0 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS0 BASE ADDRESS */
+ /* .. .. START: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS1 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS1 BASE ADDRESS */
+ /* .. .. START: USB RESET */
+ /* .. .. .. START: USB0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB0 RESET */
+ /* .. .. .. START: USB1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB1 RESET */
+ /* .. .. FINISH: USB RESET */
+ /* .. .. START: ENET RESET */
+ /* .. .. .. START: ENET0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET0 RESET */
+ /* .. .. .. START: ENET1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET1 RESET */
+ /* .. .. FINISH: ENET RESET */
+ /* .. .. START: I2C RESET */
+ /* .. .. .. START: I2C0 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C0 RESET */
+ /* .. .. .. START: I2C1 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C1 RESET */
+ /* .. .. FINISH: I2C RESET */
+ /* .. .. START: NOR CHIP SELECT */
+ /* .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. FINISH: NOR CHIP SELECT */
+ /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: ENABLING LEVEL SHIFTER */
+ /* .. USER_LVL_INP_EN_0 = 1 */
+ /* .. ==> 0XF8000900[3:3] = 0x00000001U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. USER_LVL_OUT_EN_0 = 1 */
+ /* .. ==> 0XF8000900[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. USER_LVL_INP_EN_1 = 1 */
+ /* .. ==> 0XF8000900[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. USER_LVL_OUT_EN_1 = 1 */
+ /* .. ==> 0XF8000900[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ /* .. FINISH: ENABLING LEVEL SHIFTER */
+ /* .. START: TPIU WIDTH IN CASE OF EMIO */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. .. START: TRACE CURRENT PORT SIZE */
+ /* .. .. a = 2 */
+ /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
+ /* .. .. FINISH: TRACE CURRENT PORT SIZE */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0X0 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
+ /* .. START: FPGA RESETS TO 0 */
+ /* .. reserved_3 = 0 */
+ /* .. ==> 0XF8000240[31:25] = 0x00000000U */
+ /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_ACP_RST = 0 */
+ /* .. ==> 0XF8000240[24:24] = 0x00000000U */
+ /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_AXDS3_RST = 0 */
+ /* .. ==> 0XF8000240[23:23] = 0x00000000U */
+ /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_AXDS2_RST = 0 */
+ /* .. ==> 0XF8000240[22:22] = 0x00000000U */
+ /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_AXDS1_RST = 0 */
+ /* .. ==> 0XF8000240[21:21] = 0x00000000U */
+ /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_AXDS0_RST = 0 */
+ /* .. ==> 0XF8000240[20:20] = 0x00000000U */
+ /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. reserved_2 = 0 */
+ /* .. ==> 0XF8000240[19:18] = 0x00000000U */
+ /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. reserved_FSSW1_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[17:17] = 0x00000000U */
+ /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. reserved_FSSW0_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[16:16] = 0x00000000U */
+ /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. reserved_1 = 0 */
+ /* .. ==> 0XF8000240[15:14] = 0x00000000U */
+ /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_FMSW1_RST = 0 */
+ /* .. ==> 0XF8000240[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_FMSW0_RST = 0 */
+ /* .. ==> 0XF8000240[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_DMA3_RST = 0 */
+ /* .. ==> 0XF8000240[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. reserved_FPGA_DMA2_RST = 0 */
+ /* .. ==> 0XF8000240[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. reserved_FPGA_DMA1_RST = 0 */
+ /* .. ==> 0XF8000240[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. reserved_FPGA_DMA0_RST = 0 */
+ /* .. ==> 0XF8000240[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. reserved = 0 */
+ /* .. ==> 0XF8000240[7:4] = 0x00000000U */
+ /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. FPGA3_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. FPGA2_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. FPGA1_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. FPGA0_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ /* .. FINISH: FPGA RESETS TO 0 */
+ /* .. START: AFI REGISTERS */
+ /* .. .. START: AFI0 REGISTERS */
+ /* .. .. FINISH: AFI0 REGISTERS */
+ /* .. .. START: AFI1 REGISTERS */
+ /* .. .. FINISH: AFI1 REGISTERS */
+ /* .. .. START: AFI2 REGISTERS */
+ /* .. .. FINISH: AFI2 REGISTERS */
+ /* .. .. START: AFI3 REGISTERS */
+ /* .. .. FINISH: AFI3 REGISTERS */
+ /* .. FINISH: AFI REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_debug_3_0[] = {
+ /* START: top */
+ /* .. START: CROSS TRIGGER CONFIGURATIONS */
+ /* .. .. START: UNLOCKING CTI REGISTERS */
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: UNLOCKING CTI REGISTERS */
+ /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: PLL SLCR REGISTERS */
+ /* .. .. START: ARM PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x177 */
+ /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x1a */
+ /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. ARM_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. SRCSEL = 0x0 */
+ /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. .. DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
+ /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
+ /* .. .. .. CPU_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. .. CPU_1XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. .. CPU_PERI_CLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ /* .. .. FINISH: ARM PLL INIT */
+ /* .. .. START: DDR PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1db */
+ /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x15 */
+ /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. DDR_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. DDR_3XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. DDR_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+ /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+ /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ /* .. .. FINISH: DDR PLL INIT */
+ /* .. .. START: IO PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1f4 */
+ /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x14 */
+ /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. IO_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. FINISH: IO PLL INIT */
+ /* .. FINISH: PLL SLCR REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: CLOCK CONTROL SLCR REGISTERS */
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000128[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. DIVISOR0 = 0x34 */
+ /* .. ==> 0XF8000128[13:8] = 0x00000034U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
+ /* .. DIVISOR1 = 0x2 */
+ /* .. ==> 0XF8000128[25:20] = 0x00000002U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000138[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000138[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000140[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000140[6:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x8 */
+ /* .. ==> 0XF8000140[13:8] = 0x00000008U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
+ /* .. DIVISOR1 = 0x1 */
+ /* .. ==> 0XF8000140[25:20] = 0x00000001U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF800014C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF800014C[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x5 */
+ /* .. ==> 0XF800014C[13:8] = 0x00000005U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ /* .. CLKACT0 = 0x1 */
+ /* .. ==> 0XF8000150[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. CLKACT1 = 0x0 */
+ /* .. ==> 0XF8000150[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000150[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x14 */
+ /* .. ==> 0XF8000150[13:8] = 0x00000014U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+ /* .. CLKACT0 = 0x0 */
+ /* .. ==> 0XF8000154[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. CLKACT1 = 0x1 */
+ /* .. ==> 0XF8000154[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000154[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x14 */
+ /* .. ==> 0XF8000154[13:8] = 0x00000014U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U),
+ /* .. .. START: TRACE CLOCK */
+ /* .. .. FINISH: TRACE CLOCK */
+ /* .. .. CLKACT = 0x1 */
+ /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR = 0x5 */
+ /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0xa */
+ /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ /* .. .. SRCSEL = 0x3 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */
+ /* .. .. DIVISOR0 = 0x6 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
+ /* .. .. SRCSEL = 0x2 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */
+ /* .. .. DIVISOR0 = 0x35 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */
+ /* .. .. DIVISOR1 = 0x2 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0xa */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+ /* .. .. CLK_621_TRUE = 0x1 */
+ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ /* .. .. DMA_CPU_2XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. USB0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. USB1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
+ /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
+ /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
+ /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. UART0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. UART1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
+ /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
+ /* .. .. SMC_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+ /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+ /* .. START: THIS SHOULD BE BLANK */
+ /* .. FINISH: THIS SHOULD BE BLANK */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: DDR INITIALIZATION */
+ /* .. .. START: LOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ /* .. .. FINISH: LOCK DDR */
+ /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+ /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
+ /* .. .. reg_ddrc_active_ranks = 0x1 */
+ /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+ /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_block = 0x1 */
+ /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+ /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+ /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+ /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+ /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+ /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
+ /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
+ /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+ /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
+ /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+ /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ /* .. .. reg_ddrc_t_rc = 0x1a */
+ /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+ /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
+ /* .. .. reg_ddrc_t_rfc_min = 0x54 */
+ /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+ /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
+ /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+ /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+ /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+ /* .. .. reg_ddrc_wr2pre = 0x12 */
+ /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
+ /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+ /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_t_faw = 0x15 */
+ /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+ /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
+ /* .. .. reg_ddrc_t_ras_max = 0x23 */
+ /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+ /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
+ /* .. .. reg_ddrc_t_ras_min = 0x13 */
+ /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
+ /* .. .. reg_ddrc_t_cke = 0x4 */
+ /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+ /* .. .. reg_ddrc_write_latency = 0x5 */
+ /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_rd2wr = 0x7 */
+ /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
+ /* .. .. reg_ddrc_wr2rd = 0xe */
+ /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+ /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
+ /* .. .. reg_ddrc_t_xp = 0x4 */
+ /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
+ /* .. .. reg_ddrc_pad_pd = 0x0 */
+ /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd2pre = 0x4 */
+ /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
+ /* .. .. reg_ddrc_t_rcd = 0x7 */
+ /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ /* .. .. reg_ddrc_t_ccd = 0x4 */
+ /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
+ /* .. .. reg_ddrc_t_rrd = 0x6 */
+ /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_refresh_margin = 0x2 */
+ /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_rp = 0x7 */
+ /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
+ /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+ /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+ /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_sdram = 0x1 */
+ /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_mobile = 0x0 */
+ /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_clock_stop_en = 0x0 */
+ /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_read_latency = 0x7 */
+ /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+ /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
+ /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+ /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_loopback = 0x0 */
+ /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+ /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+ /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+ /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_prefer_write = 0x0 */
+ /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_max_rank_rd = 0xf */
+ /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
+ /* .. .. reg_ddrc_mr_wr = 0x0 */
+ /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_addr = 0x0 */
+ /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_data = 0x0 */
+ /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+ /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_type = 0x0 */
+ /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+ /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+ /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+ /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_t_mrd = 0x4 */
+ /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ /* .. .. reg_ddrc_emr2 = 0x8 */
+ /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
+ /* .. .. reg_ddrc_emr3 = 0x0 */
+ /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ /* .. .. reg_ddrc_mr = 0x930 */
+ /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
+ /* .. .. reg_ddrc_emr = 0x4 */
+ /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ /* .. .. reg_ddrc_burst_rdwr = 0x4 */
+ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */
+ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
+ /* .. .. reg_ddrc_burstchop = 0x0 */
+ /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U),
+ /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_dq = 0x0 */
+ /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_debug_mode = 0x0 */
+ /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_level_start = 0x0 */
+ /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_level_start = 0x0 */
+ /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq0_wait_t = 0x0 */
+ /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+ /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+ /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+ /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
+ /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+ /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
+ /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+ /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+ /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+ /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+ /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+ /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+ /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+ /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+ /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+ /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+ /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+ /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+ /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+ /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
+ /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+ /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+ /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+ /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+ /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
+ /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
+ /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. .. reg_phy_rd_local_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
+ /* .. .. reg_phy_idle_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
+ /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+ /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
+ /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+ /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_fixed_re = 0x1 */
+ /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+ /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+ /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_phy_clk_stall_level = 0x0 */
+ /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
+ /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+ /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+ /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+ /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
+ /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+ /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+ /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+ /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ /* .. .. reg_ddrc_pageclose = 0x0 */
+ /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+ /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+ /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
+ /* .. .. reg_ddrc_auto_pre_en = 0x0 */
+ /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_refresh_update_level = 0x0 */
+ /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_wc = 0x0 */
+ /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+ /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_selfref_en = 0x0 */
+ /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+ /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
+ /* .. .. reg_arb_go2critical_en = 0x1 */
+ /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+ /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
+ /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+ /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
+ /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+ /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+ /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
+ /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+ /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+ /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+ /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
+ /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+ /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
+ /* .. .. reg_ddrc_t_cksre = 0x6 */
+ /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_t_cksrx = 0x6 */
+ /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_t_ckesr = 0x4 */
+ /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ /* .. .. reg_ddrc_t_ckpde = 0x2 */
+ /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_ckpdx = 0x2 */
+ /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
+ /* .. .. reg_ddrc_t_ckdpde = 0x2 */
+ /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+ /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
+ /* .. .. reg_ddrc_t_ckcsx = 0x3 */
+ /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ /* .. .. refresh_timer0_start_value_x32 = 0x0 */
+ /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
+ /* .. .. refresh_timer1_start_value_x32 = 0x8 */
+ /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+ /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+ /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_ddr3 = 0x1 */
+ /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_mod = 0x200 */
+ /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+ /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
+ /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+ /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+ /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+ /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ /* .. .. t_zq_short_interval_x1024 = 0xc845 */
+ /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+ /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
+ /* .. .. dram_rstn_x1024 = 0x67 */
+ /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+ /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ /* .. .. deeppowerdown_en = 0x0 */
+ /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. deeppowerdown_to_x1024 = 0xff */
+ /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+ /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
+ /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
+ /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+ /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+ /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ /* .. .. reg_ddrc_2t_delay = 0x0 */
+ /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_skip_ocd = 0x1 */
+ /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+ /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+ /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+ /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+ /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+ /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+ /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ /* .. .. START: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ /* .. .. FINISH: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ /* .. .. CORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+ /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ /* .. .. STAT_NUM_CORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
+ /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_ecc_mode = 0x0 */
+ /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_scrub = 0x1 */
+ /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ /* .. .. reg_phy_dif_on = 0x0 */
+ /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_dif_off = 0x0 */
+ /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+ /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+ /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+ /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+ /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+ /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+ /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+ /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+ /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+ /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+ /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+ /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+ /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+ /* .. .. reg_phy_loopback = 0x0 */
+ /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_phy_bl2 = 0x0 */
+ /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_at_spd_atpg = 0x0 */
+ /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_enable = 0x0 */
+ /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_force_err = 0x0 */
+ /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_mode = 0x0 */
+ /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. .. reg_phy_invert_clkout = 0x1 */
+ /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+ /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_phy_sel_logic = 0x0 */
+ /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+ /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
+ /* .. .. reg_phy_ctrl_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_rank0_delays = 0x1 */
+ /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. reg_phy_lpddr = 0x0 */
+ /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_cmd_latency = 0x0 */
+ /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_int_lpbk = 0x0 */
+ /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+ /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+ /* .. .. reg_phy_wr_rl_delay = 0x2 */
+ /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
+ /* .. .. reg_phy_rd_rl_delay = 0x4 */
+ /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
+ /* .. .. reg_phy_dll_lock_diff = 0xf */
+ /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
+ /* .. .. reg_phy_use_wr_level = 0x1 */
+ /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
+ /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
+ /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+ /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_dis_calib_rst = 0x0 */
+ /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ /* .. .. reg_arb_page_addr_mask = 0x0 */
+ /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_ddrc_lpddr2 = 0x0 */
+ /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+ /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_derate_enable = 0x0 */
+ /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr4_margin = 0x0 */
+ /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+ /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+ /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+ /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
+ /* .. .. reg_ddrc_t_mrw = 0x5 */
+ /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+ /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
+ /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ /* .. .. START: POLL ON DCI STATUS */
+ /* .. .. DONE = 1 */
+ /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ /* .. .. FINISH: POLL ON DCI STATUS */
+ /* .. .. START: UNLOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0x1 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ /* .. .. FINISH: UNLOCK DDR */
+ /* .. .. START: CHECK DDR STATUS */
+ /* .. .. ddrc_reg_operating_mode = 1 */
+ /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ /* .. .. FINISH: CHECK DDR STATUS */
+ /* .. FINISH: DDR INITIALIZATION */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: OCM REMAPPING */
+ /* .. VREF_EN = 0x1 */
+ /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. CLK_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. SRSTN_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+ /* .. FINISH: OCM REMAPPING */
+ /* .. START: DDRIOB SETTINGS */
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x3 */
+ /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
+ /* .. SLEW_N = 0x3 */
+ /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. VREF_INT_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. VREF_SEL = 0x0 */
+ /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+ /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
+ /* .. VREF_EXT_EN = 0x3 */
+ /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. REFIO_EN = 0x1 */
+ /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. REFIO_TEST = 0x0 */
+ /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
+ /* .. REFIO_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DRST_B_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. CKE_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+ /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ /* .. .. START: ASSERT RESET */
+ /* .. .. RESET = 1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+ /* .. .. FINISH: ASSERT RESET */
+ /* .. .. START: DEASSERT RESET */
+ /* .. .. RESET = 0 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ /* .. .. FINISH: DEASSERT RESET */
+ /* .. .. RESET = 0x1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. ENABLE = 0x1 */
+ /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. VRP_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. VRN_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. VRP_OUT = 0x0 */
+ /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. NREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. .. NREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
+ /* .. .. NREF_OPT4 = 0x1 */
+ /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
+ /* .. .. PREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
+ /* .. .. PREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
+ /* .. .. UPDATE_CONTROL = 0x0 */
+ /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. INIT_COMPLETE = 0x0 */
+ /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. TST_CLK = 0x0 */
+ /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. TST_HLN = 0x0 */
+ /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. TST_HLP = 0x0 */
+ /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. TST_RST = 0x0 */
+ /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. INT_DCI_EN = 0x0 */
+ /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+ /* .. FINISH: DDRIOB SETTINGS */
+ /* .. START: MIO PROGRAMMING */
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000704[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000704[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000704[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000704[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000704[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000704[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000704[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000704[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000704[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000708[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000708[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000708[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000708[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000708[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000708[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000708[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000708[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000708[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800070C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800070C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800070C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800070C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800070C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800070C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800070C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800070C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800070C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000710[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000710[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000710[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000710[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000710[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000710[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000710[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000710[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000710[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000714[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000714[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000714[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000714[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000714[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000714[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000714[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000714[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000714[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000718[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000718[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000718[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000718[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000718[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000718[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000718[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000718[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000718[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000740[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000740[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000740[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000740[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000740[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000740[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000740[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000740[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000740[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000744[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000744[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000744[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000744[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000744[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000744[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000744[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000744[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000744[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000748[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000748[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000748[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000748[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000748[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000748[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000748[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000748[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000748[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800074C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800074C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800074C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800074C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800074C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800074C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800074C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800074C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF800074C[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000750[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000750[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000750[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000750[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000750[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000750[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000750[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000750[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000750[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000754[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000754[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000754[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000754[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000754[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000754[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000754[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000754[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000754[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000758[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000758[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000758[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000758[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000758[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000758[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000758[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000758[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000758[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800075C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800075C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800075C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800075C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800075C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800075C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800075C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800075C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800075C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000760[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000760[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000760[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000760[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000760[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000760[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000760[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000760[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000760[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000764[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000764[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000764[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000764[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000764[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000764[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000764[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000764[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000764[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000768[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000768[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000768[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000768[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000768[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000768[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000768[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000768[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000768[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800076C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800076C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800076C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800076C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800076C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800076C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800076C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800076C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800076C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000770[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000770[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000770[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000770[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000770[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000770[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000770[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000770[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000770[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000774[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000774[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000774[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000774[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000774[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000774[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000774[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000774[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000774[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000778[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000778[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000778[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000778[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000778[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000778[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000778[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000778[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000778[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800077C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800077C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800077C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800077C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800077C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800077C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800077C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800077C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800077C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000780[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000780[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000780[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000780[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000780[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000780[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000780[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000780[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000780[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000784[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000784[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000784[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000784[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000784[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000784[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000784[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000784[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000784[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000788[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000788[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000788[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000788[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000788[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000788[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000788[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000788[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000788[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800078C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800078C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800078C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800078C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800078C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800078C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800078C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800078C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800078C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000790[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000790[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000790[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000790[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000790[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000790[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000790[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000790[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000790[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000794[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000794[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000794[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000794[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000794[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000794[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000794[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000794[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000794[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000798[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000798[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000798[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000798[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000798[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000798[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000798[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000798[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000798[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800079C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800079C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800079C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800079C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800079C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800079C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800079C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800079C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800079C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+ /* .. SDIO0_WP_SEL = 55 */
+ /* .. ==> 0XF8000830[5:0] = 0x00000037U */
+ /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
+ /* .. SDIO0_CD_SEL = 47 */
+ /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+ /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+ /* .. FINISH: MIO PROGRAMMING */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* .. START: SRAM/NOR SET OPMODE */
+ /* .. FINISH: SRAM/NOR SET OPMODE */
+ /* .. START: UART REGISTERS */
+ /* .. BDIV = 0x6 */
+ /* .. ==> 0XE0001034[7:0] = 0x00000006U */
+ /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ /* .. CD = 0x3e */
+ /* .. ==> 0XE0001018[15:0] = 0x0000003EU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU),
+ /* .. STPBRK = 0x0 */
+ /* .. ==> 0XE0001000[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. STTBRK = 0x0 */
+ /* .. ==> 0XE0001000[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. RSTTO = 0x0 */
+ /* .. ==> 0XE0001000[6:6] = 0x00000000U */
+ /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. TXDIS = 0x0 */
+ /* .. ==> 0XE0001000[5:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. TXEN = 0x1 */
+ /* .. ==> 0XE0001000[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. RXDIS = 0x0 */
+ /* .. ==> 0XE0001000[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. RXEN = 0x1 */
+ /* .. ==> 0XE0001000[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. TXRES = 0x1 */
+ /* .. ==> 0XE0001000[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. RXRES = 0x1 */
+ /* .. ==> 0XE0001000[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ /* .. IRMODE = 0x0 */
+ /* .. ==> 0XE0001004[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. UCLKEN = 0x0 */
+ /* .. ==> 0XE0001004[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. CHMODE = 0x0 */
+ /* .. ==> 0XE0001004[9:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
+ /* .. NBSTOP = 0x0 */
+ /* .. ==> 0XE0001004[7:6] = 0x00000000U */
+ /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. PAR = 0x4 */
+ /* .. ==> 0XE0001004[5:3] = 0x00000004U */
+ /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
+ /* .. CHRL = 0x0 */
+ /* .. ==> 0XE0001004[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. CLKS = 0x0 */
+ /* .. ==> 0XE0001004[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
+ /* .. FINISH: UART REGISTERS */
+ /* .. START: TPIU WIDTH IN CASE OF EMIO */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. .. START: TRACE CURRENT PORT SIZE */
+ /* .. .. a = 2 */
+ /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
+ /* .. .. FINISH: TRACE CURRENT PORT SIZE */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0X0 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
+ /* .. START: QSPI REGISTERS */
+ /* .. Holdb_dr = 1 */
+ /* .. ==> 0XE000D000[19:19] = 0x00000001U */
+ /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ /* .. FINISH: QSPI REGISTERS */
+ /* .. START: PL POWER ON RESET REGISTERS */
+ /* .. PCFG_POR_CNT_4K = 0 */
+ /* .. ==> 0XF8007000[29:29] = 0x00000000U */
+ /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ /* .. FINISH: PL POWER ON RESET REGISTERS */
+ /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* .. .. START: NAND SET CYCLE */
+ /* .. .. FINISH: NAND SET CYCLE */
+ /* .. .. START: OPMODE */
+ /* .. .. FINISH: OPMODE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS0 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS0 BASE ADDRESS */
+ /* .. .. START: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS1 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS1 BASE ADDRESS */
+ /* .. .. START: USB RESET */
+ /* .. .. .. START: USB0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB0 RESET */
+ /* .. .. .. START: USB1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB1 RESET */
+ /* .. .. FINISH: USB RESET */
+ /* .. .. START: ENET RESET */
+ /* .. .. .. START: ENET0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET0 RESET */
+ /* .. .. .. START: ENET1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET1 RESET */
+ /* .. .. FINISH: ENET RESET */
+ /* .. .. START: I2C RESET */
+ /* .. .. .. START: I2C0 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C0 RESET */
+ /* .. .. .. START: I2C1 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C1 RESET */
+ /* .. .. FINISH: I2C RESET */
+ /* .. .. START: NOR CHIP SELECT */
+ /* .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. FINISH: NOR CHIP SELECT */
+ /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: ENABLING LEVEL SHIFTER */
+ /* .. USER_INP_ICT_EN_0 = 3 */
+ /* .. ==> 0XF8000900[1:0] = 0x00000003U */
+ /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
+ /* .. USER_INP_ICT_EN_1 = 3 */
+ /* .. ==> 0XF8000900[3:2] = 0x00000003U */
+ /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ /* .. FINISH: ENABLING LEVEL SHIFTER */
+ /* .. START: TPIU WIDTH IN CASE OF EMIO */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. .. START: TRACE CURRENT PORT SIZE */
+ /* .. .. a = 2 */
+ /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
+ /* .. .. FINISH: TRACE CURRENT PORT SIZE */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0X0 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
+ /* .. START: FPGA RESETS TO 0 */
+ /* .. reserved_3 = 0 */
+ /* .. ==> 0XF8000240[31:25] = 0x00000000U */
+ /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
+ /* .. FPGA_ACP_RST = 0 */
+ /* .. ==> 0XF8000240[24:24] = 0x00000000U */
+ /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS3_RST = 0 */
+ /* .. ==> 0XF8000240[23:23] = 0x00000000U */
+ /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS2_RST = 0 */
+ /* .. ==> 0XF8000240[22:22] = 0x00000000U */
+ /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS1_RST = 0 */
+ /* .. ==> 0XF8000240[21:21] = 0x00000000U */
+ /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS0_RST = 0 */
+ /* .. ==> 0XF8000240[20:20] = 0x00000000U */
+ /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. reserved_2 = 0 */
+ /* .. ==> 0XF8000240[19:18] = 0x00000000U */
+ /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. FSSW1_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[17:17] = 0x00000000U */
+ /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. FSSW0_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[16:16] = 0x00000000U */
+ /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. reserved_1 = 0 */
+ /* .. ==> 0XF8000240[15:14] = 0x00000000U */
+ /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
+ /* .. FPGA_FMSW1_RST = 0 */
+ /* .. ==> 0XF8000240[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. FPGA_FMSW0_RST = 0 */
+ /* .. ==> 0XF8000240[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. FPGA_DMA3_RST = 0 */
+ /* .. ==> 0XF8000240[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. FPGA_DMA2_RST = 0 */
+ /* .. ==> 0XF8000240[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. FPGA_DMA1_RST = 0 */
+ /* .. ==> 0XF8000240[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. FPGA_DMA0_RST = 0 */
+ /* .. ==> 0XF8000240[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. reserved = 0 */
+ /* .. ==> 0XF8000240[7:4] = 0x00000000U */
+ /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. FPGA3_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. FPGA2_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. FPGA1_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. FPGA0_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ /* .. FINISH: FPGA RESETS TO 0 */
+ /* .. START: AFI REGISTERS */
+ /* .. .. START: AFI0 REGISTERS */
+ /* .. .. FINISH: AFI0 REGISTERS */
+ /* .. .. START: AFI1 REGISTERS */
+ /* .. .. FINISH: AFI1 REGISTERS */
+ /* .. .. START: AFI2 REGISTERS */
+ /* .. .. FINISH: AFI2 REGISTERS */
+ /* .. .. START: AFI3 REGISTERS */
+ /* .. .. FINISH: AFI3 REGISTERS */
+ /* .. FINISH: AFI REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_debug_2_0[] = {
+ /* START: top */
+ /* .. START: CROSS TRIGGER CONFIGURATIONS */
+ /* .. .. START: UNLOCKING CTI REGISTERS */
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: UNLOCKING CTI REGISTERS */
+ /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: PLL SLCR REGISTERS */
+ /* .. .. START: ARM PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x177 */
+ /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x1a */
+ /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. ARM_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. SRCSEL = 0x0 */
+ /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. .. DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
+ /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
+ /* .. .. .. CPU_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. .. CPU_1XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. .. CPU_PERI_CLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ /* .. .. FINISH: ARM PLL INIT */
+ /* .. .. START: DDR PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1db */
+ /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x15 */
+ /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. DDR_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. DDR_3XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. DDR_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+ /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+ /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ /* .. .. FINISH: DDR PLL INIT */
+ /* .. .. START: IO PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1f4 */
+ /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x14 */
+ /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. IO_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. FINISH: IO PLL INIT */
+ /* .. FINISH: PLL SLCR REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: CLOCK CONTROL SLCR REGISTERS */
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000128[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. DIVISOR0 = 0x34 */
+ /* .. ==> 0XF8000128[13:8] = 0x00000034U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
+ /* .. DIVISOR1 = 0x2 */
+ /* .. ==> 0XF8000128[25:20] = 0x00000002U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000138[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000138[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000140[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000140[6:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x8 */
+ /* .. ==> 0XF8000140[13:8] = 0x00000008U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
+ /* .. DIVISOR1 = 0x1 */
+ /* .. ==> 0XF8000140[25:20] = 0x00000001U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF800014C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF800014C[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x5 */
+ /* .. ==> 0XF800014C[13:8] = 0x00000005U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ /* .. CLKACT0 = 0x1 */
+ /* .. ==> 0XF8000150[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. CLKACT1 = 0x0 */
+ /* .. ==> 0XF8000150[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000150[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x14 */
+ /* .. ==> 0XF8000150[13:8] = 0x00000014U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+ /* .. CLKACT0 = 0x0 */
+ /* .. ==> 0XF8000154[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. CLKACT1 = 0x1 */
+ /* .. ==> 0XF8000154[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000154[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x14 */
+ /* .. ==> 0XF8000154[13:8] = 0x00000014U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U),
+ /* .. .. START: TRACE CLOCK */
+ /* .. .. FINISH: TRACE CLOCK */
+ /* .. .. CLKACT = 0x1 */
+ /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR = 0x5 */
+ /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0xa */
+ /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ /* .. .. SRCSEL = 0x3 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */
+ /* .. .. DIVISOR0 = 0x6 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U),
+ /* .. .. SRCSEL = 0x2 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */
+ /* .. .. DIVISOR0 = 0x35 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */
+ /* .. .. DIVISOR1 = 0x2 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0xa */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U),
+ /* .. .. CLK_621_TRUE = 0x1 */
+ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ /* .. .. DMA_CPU_2XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. USB0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. USB1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
+ /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
+ /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
+ /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. UART0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. UART1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
+ /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
+ /* .. .. SMC_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+ /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+ /* .. START: THIS SHOULD BE BLANK */
+ /* .. FINISH: THIS SHOULD BE BLANK */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: DDR INITIALIZATION */
+ /* .. .. START: LOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ /* .. .. FINISH: LOCK DDR */
+ /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+ /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
+ /* .. .. reg_ddrc_active_ranks = 0x1 */
+ /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+ /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_block = 0x1 */
+ /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+ /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+ /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+ /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+ /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+ /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
+ /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
+ /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+ /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
+ /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+ /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ /* .. .. reg_ddrc_t_rc = 0x1a */
+ /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+ /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
+ /* .. .. reg_ddrc_t_rfc_min = 0x54 */
+ /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+ /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
+ /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+ /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+ /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+ /* .. .. reg_ddrc_wr2pre = 0x12 */
+ /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
+ /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+ /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_t_faw = 0x15 */
+ /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+ /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
+ /* .. .. reg_ddrc_t_ras_max = 0x23 */
+ /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+ /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
+ /* .. .. reg_ddrc_t_ras_min = 0x13 */
+ /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
+ /* .. .. reg_ddrc_t_cke = 0x4 */
+ /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+ /* .. .. reg_ddrc_write_latency = 0x5 */
+ /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_rd2wr = 0x7 */
+ /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
+ /* .. .. reg_ddrc_wr2rd = 0xe */
+ /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+ /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
+ /* .. .. reg_ddrc_t_xp = 0x4 */
+ /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
+ /* .. .. reg_ddrc_pad_pd = 0x0 */
+ /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd2pre = 0x4 */
+ /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
+ /* .. .. reg_ddrc_t_rcd = 0x7 */
+ /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ /* .. .. reg_ddrc_t_ccd = 0x4 */
+ /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
+ /* .. .. reg_ddrc_t_rrd = 0x6 */
+ /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_refresh_margin = 0x2 */
+ /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_rp = 0x7 */
+ /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
+ /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+ /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+ /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_sdram = 0x1 */
+ /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_mobile = 0x0 */
+ /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_clock_stop_en = 0x0 */
+ /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_read_latency = 0x7 */
+ /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+ /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
+ /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+ /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_loopback = 0x0 */
+ /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+ /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+ /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+ /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_prefer_write = 0x0 */
+ /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_max_rank_rd = 0xf */
+ /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
+ /* .. .. reg_ddrc_mr_wr = 0x0 */
+ /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_addr = 0x0 */
+ /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_data = 0x0 */
+ /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+ /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_type = 0x0 */
+ /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+ /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+ /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+ /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_t_mrd = 0x4 */
+ /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ /* .. .. reg_ddrc_emr2 = 0x8 */
+ /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
+ /* .. .. reg_ddrc_emr3 = 0x0 */
+ /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ /* .. .. reg_ddrc_mr = 0x930 */
+ /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
+ /* .. .. reg_ddrc_emr = 0x4 */
+ /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ /* .. .. reg_ddrc_burst_rdwr = 0x4 */
+ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */
+ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
+ /* .. .. reg_ddrc_burstchop = 0x0 */
+ /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U),
+ /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_dq = 0x0 */
+ /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_debug_mode = 0x0 */
+ /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_level_start = 0x0 */
+ /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_level_start = 0x0 */
+ /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq0_wait_t = 0x0 */
+ /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+ /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+ /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+ /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
+ /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+ /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
+ /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+ /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+ /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+ /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+ /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+ /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+ /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+ /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+ /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+ /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+ /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+ /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+ /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+ /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
+ /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+ /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+ /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+ /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+ /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
+ /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
+ /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. .. reg_phy_rd_local_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
+ /* .. .. reg_phy_idle_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
+ /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+ /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
+ /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+ /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_fixed_re = 0x1 */
+ /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+ /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+ /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_phy_clk_stall_level = 0x0 */
+ /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
+ /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+ /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+ /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+ /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
+ /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+ /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+ /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+ /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ /* .. .. reg_ddrc_pageclose = 0x0 */
+ /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+ /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+ /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
+ /* .. .. reg_ddrc_auto_pre_en = 0x0 */
+ /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_refresh_update_level = 0x0 */
+ /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_wc = 0x0 */
+ /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+ /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_selfref_en = 0x0 */
+ /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+ /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
+ /* .. .. reg_arb_go2critical_en = 0x1 */
+ /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+ /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
+ /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+ /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
+ /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+ /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+ /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
+ /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+ /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ /* .. .. refresh_timer0_start_value_x32 = 0x0 */
+ /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
+ /* .. .. refresh_timer1_start_value_x32 = 0x8 */
+ /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+ /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+ /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_ddr3 = 0x1 */
+ /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_mod = 0x200 */
+ /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+ /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
+ /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+ /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+ /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+ /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ /* .. .. t_zq_short_interval_x1024 = 0xc845 */
+ /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+ /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
+ /* .. .. dram_rstn_x1024 = 0x67 */
+ /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+ /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ /* .. .. deeppowerdown_en = 0x0 */
+ /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. deeppowerdown_to_x1024 = 0xff */
+ /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+ /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
+ /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
+ /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+ /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+ /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ /* .. .. reg_ddrc_2t_delay = 0x0 */
+ /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_skip_ocd = 0x1 */
+ /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+ /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+ /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+ /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+ /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+ /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+ /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ /* .. .. START: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ /* .. .. FINISH: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ /* .. .. CORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+ /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ /* .. .. STAT_NUM_CORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
+ /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_ecc_mode = 0x0 */
+ /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_scrub = 0x1 */
+ /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ /* .. .. reg_phy_dif_on = 0x0 */
+ /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_dif_off = 0x0 */
+ /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+ /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+ /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+ /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+ /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+ /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+ /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+ /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+ /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+ /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+ /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+ /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+ /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+ /* .. .. reg_phy_loopback = 0x0 */
+ /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_phy_bl2 = 0x0 */
+ /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_at_spd_atpg = 0x0 */
+ /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_enable = 0x0 */
+ /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_force_err = 0x0 */
+ /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_mode = 0x0 */
+ /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. .. reg_phy_invert_clkout = 0x1 */
+ /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+ /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_phy_sel_logic = 0x0 */
+ /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+ /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
+ /* .. .. reg_phy_ctrl_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_rank0_delays = 0x1 */
+ /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. reg_phy_lpddr = 0x0 */
+ /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_cmd_latency = 0x0 */
+ /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_int_lpbk = 0x0 */
+ /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+ /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+ /* .. .. reg_phy_wr_rl_delay = 0x2 */
+ /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
+ /* .. .. reg_phy_rd_rl_delay = 0x4 */
+ /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
+ /* .. .. reg_phy_dll_lock_diff = 0xf */
+ /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
+ /* .. .. reg_phy_use_wr_level = 0x1 */
+ /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
+ /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
+ /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+ /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_dis_calib_rst = 0x0 */
+ /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ /* .. .. reg_arb_page_addr_mask = 0x0 */
+ /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_ddrc_lpddr2 = 0x0 */
+ /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+ /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_derate_enable = 0x0 */
+ /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr4_margin = 0x0 */
+ /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+ /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+ /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+ /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
+ /* .. .. reg_ddrc_t_mrw = 0x5 */
+ /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+ /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
+ /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ /* .. .. START: POLL ON DCI STATUS */
+ /* .. .. DONE = 1 */
+ /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ /* .. .. FINISH: POLL ON DCI STATUS */
+ /* .. .. START: UNLOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0x1 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ /* .. .. FINISH: UNLOCK DDR */
+ /* .. .. START: CHECK DDR STATUS */
+ /* .. .. ddrc_reg_operating_mode = 1 */
+ /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ /* .. .. FINISH: CHECK DDR STATUS */
+ /* .. FINISH: DDR INITIALIZATION */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: OCM REMAPPING */
+ /* .. VREF_EN = 0x1 */
+ /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. CLK_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. SRSTN_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+ /* .. FINISH: OCM REMAPPING */
+ /* .. START: DDRIOB SETTINGS */
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x3 */
+ /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
+ /* .. SLEW_N = 0x3 */
+ /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. VREF_INT_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. VREF_SEL = 0x0 */
+ /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+ /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
+ /* .. VREF_EXT_EN = 0x3 */
+ /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. REFIO_EN = 0x1 */
+ /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. REFIO_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DRST_B_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. CKE_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+ /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+ /* .. .. START: ASSERT RESET */
+ /* .. .. RESET = 1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+ /* .. .. FINISH: ASSERT RESET */
+ /* .. .. START: DEASSERT RESET */
+ /* .. .. RESET = 0 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ /* .. .. FINISH: DEASSERT RESET */
+ /* .. .. RESET = 0x1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. ENABLE = 0x1 */
+ /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. VRP_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. VRN_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. VRP_OUT = 0x0 */
+ /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. NREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. .. NREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
+ /* .. .. NREF_OPT4 = 0x1 */
+ /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
+ /* .. .. PREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
+ /* .. .. PREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
+ /* .. .. UPDATE_CONTROL = 0x0 */
+ /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. INIT_COMPLETE = 0x0 */
+ /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. TST_CLK = 0x0 */
+ /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. TST_HLN = 0x0 */
+ /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. TST_HLP = 0x0 */
+ /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. TST_RST = 0x0 */
+ /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. INT_DCI_EN = 0x0 */
+ /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+ /* .. FINISH: DDRIOB SETTINGS */
+ /* .. START: MIO PROGRAMMING */
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000704[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000704[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000704[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000704[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000704[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000704[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000704[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000704[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000704[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000708[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000708[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000708[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000708[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000708[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000708[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000708[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000708[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000708[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800070C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800070C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800070C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800070C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800070C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800070C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800070C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800070C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800070C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000710[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000710[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000710[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000710[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000710[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000710[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000710[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000710[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000710[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000714[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000714[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000714[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000714[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000714[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000714[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000714[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000714[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000714[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000718[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000718[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000718[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000718[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000718[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000718[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000718[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000718[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000718[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000740[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000740[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000740[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000740[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000740[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000740[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000740[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000740[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000740[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000744[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000744[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000744[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000744[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000744[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000744[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000744[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000744[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000744[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000748[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000748[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000748[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000748[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000748[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000748[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000748[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000748[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000748[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800074C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800074C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800074C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800074C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800074C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800074C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800074C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800074C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF800074C[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000750[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000750[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000750[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000750[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000750[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000750[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000750[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000750[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000750[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000754[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000754[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000754[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000754[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000754[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000754[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000754[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000754[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000754[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000758[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000758[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000758[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000758[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000758[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000758[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000758[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000758[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000758[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800075C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800075C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800075C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800075C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800075C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800075C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800075C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800075C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800075C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000760[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000760[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000760[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000760[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000760[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000760[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000760[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000760[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000760[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000764[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000764[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000764[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000764[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000764[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000764[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000764[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000764[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000764[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000768[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000768[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000768[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000768[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000768[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000768[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000768[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000768[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000768[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800076C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800076C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800076C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800076C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800076C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800076C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800076C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800076C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800076C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000770[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000770[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000770[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000770[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000770[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000770[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000770[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000770[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000770[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000774[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000774[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000774[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000774[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000774[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000774[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000774[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000774[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000774[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000778[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000778[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000778[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000778[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000778[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000778[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000778[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000778[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000778[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800077C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800077C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800077C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800077C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800077C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800077C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800077C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800077C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800077C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000780[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000780[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000780[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000780[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000780[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000780[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000780[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000780[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000780[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000784[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000784[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000784[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000784[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000784[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000784[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000784[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000784[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000784[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000788[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000788[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000788[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000788[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000788[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000788[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000788[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000788[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000788[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800078C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800078C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800078C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800078C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800078C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800078C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800078C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800078C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800078C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000790[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000790[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000790[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000790[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000790[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000790[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000790[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000790[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000790[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000794[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000794[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000794[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000794[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000794[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000794[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000794[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000794[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000794[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000798[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000798[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000798[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000798[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000798[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000798[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000798[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000798[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000798[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800079C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800079C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800079C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800079C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800079C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800079C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800079C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800079C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800079C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+ /* .. SDIO0_WP_SEL = 55 */
+ /* .. ==> 0XF8000830[5:0] = 0x00000037U */
+ /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
+ /* .. SDIO0_CD_SEL = 47 */
+ /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+ /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+ /* .. FINISH: MIO PROGRAMMING */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* .. START: SRAM/NOR SET OPMODE */
+ /* .. FINISH: SRAM/NOR SET OPMODE */
+ /* .. START: UART REGISTERS */
+ /* .. BDIV = 0x6 */
+ /* .. ==> 0XE0001034[7:0] = 0x00000006U */
+ /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ /* .. CD = 0x3e */
+ /* .. ==> 0XE0001018[15:0] = 0x0000003EU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU),
+ /* .. STPBRK = 0x0 */
+ /* .. ==> 0XE0001000[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. STTBRK = 0x0 */
+ /* .. ==> 0XE0001000[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. RSTTO = 0x0 */
+ /* .. ==> 0XE0001000[6:6] = 0x00000000U */
+ /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. TXDIS = 0x0 */
+ /* .. ==> 0XE0001000[5:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. TXEN = 0x1 */
+ /* .. ==> 0XE0001000[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. RXDIS = 0x0 */
+ /* .. ==> 0XE0001000[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. RXEN = 0x1 */
+ /* .. ==> 0XE0001000[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. TXRES = 0x1 */
+ /* .. ==> 0XE0001000[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. RXRES = 0x1 */
+ /* .. ==> 0XE0001000[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ /* .. IRMODE = 0x0 */
+ /* .. ==> 0XE0001004[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. UCLKEN = 0x0 */
+ /* .. ==> 0XE0001004[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. CHMODE = 0x0 */
+ /* .. ==> 0XE0001004[9:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
+ /* .. NBSTOP = 0x0 */
+ /* .. ==> 0XE0001004[7:6] = 0x00000000U */
+ /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. PAR = 0x4 */
+ /* .. ==> 0XE0001004[5:3] = 0x00000004U */
+ /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
+ /* .. CHRL = 0x0 */
+ /* .. ==> 0XE0001004[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. CLKS = 0x0 */
+ /* .. ==> 0XE0001004[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
+ /* .. FINISH: UART REGISTERS */
+ /* .. START: TPIU WIDTH IN CASE OF EMIO */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. .. START: TRACE CURRENT PORT SIZE */
+ /* .. .. a = 2 */
+ /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
+ /* .. .. FINISH: TRACE CURRENT PORT SIZE */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0X0 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
+ /* .. START: QSPI REGISTERS */
+ /* .. Holdb_dr = 1 */
+ /* .. ==> 0XE000D000[19:19] = 0x00000001U */
+ /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ /* .. FINISH: QSPI REGISTERS */
+ /* .. START: PL POWER ON RESET REGISTERS */
+ /* .. PCFG_POR_CNT_4K = 0 */
+ /* .. ==> 0XF8007000[29:29] = 0x00000000U */
+ /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ /* .. FINISH: PL POWER ON RESET REGISTERS */
+ /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* .. .. START: NAND SET CYCLE */
+ /* .. .. FINISH: NAND SET CYCLE */
+ /* .. .. START: OPMODE */
+ /* .. .. FINISH: OPMODE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS0 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS0 BASE ADDRESS */
+ /* .. .. START: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS1 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS1 BASE ADDRESS */
+ /* .. .. START: USB RESET */
+ /* .. .. .. START: USB0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB0 RESET */
+ /* .. .. .. START: USB1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB1 RESET */
+ /* .. .. FINISH: USB RESET */
+ /* .. .. START: ENET RESET */
+ /* .. .. .. START: ENET0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET0 RESET */
+ /* .. .. .. START: ENET1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET1 RESET */
+ /* .. .. FINISH: ENET RESET */
+ /* .. .. START: I2C RESET */
+ /* .. .. .. START: I2C0 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C0 RESET */
+ /* .. .. .. START: I2C1 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C1 RESET */
+ /* .. .. FINISH: I2C RESET */
+ /* .. .. START: NOR CHIP SELECT */
+ /* .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. FINISH: NOR CHIP SELECT */
+ /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: ENABLING LEVEL SHIFTER */
+ /* .. USER_INP_ICT_EN_0 = 3 */
+ /* .. ==> 0XF8000900[1:0] = 0x00000003U */
+ /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
+ /* .. USER_INP_ICT_EN_1 = 3 */
+ /* .. ==> 0XF8000900[3:2] = 0x00000003U */
+ /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ /* .. FINISH: ENABLING LEVEL SHIFTER */
+ /* .. START: TPIU WIDTH IN CASE OF EMIO */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. .. START: TRACE CURRENT PORT SIZE */
+ /* .. .. a = 2 */
+ /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U),
+ /* .. .. FINISH: TRACE CURRENT PORT SIZE */
+ /* .. .. START: TRACE LOCK ACCESS REGISTER */
+ /* .. .. a = 0X0 */
+ /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */
+ /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */
+ /* .. START: FPGA RESETS TO 0 */
+ /* .. reserved_3 = 0 */
+ /* .. ==> 0XF8000240[31:25] = 0x00000000U */
+ /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
+ /* .. FPGA_ACP_RST = 0 */
+ /* .. ==> 0XF8000240[24:24] = 0x00000000U */
+ /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS3_RST = 0 */
+ /* .. ==> 0XF8000240[23:23] = 0x00000000U */
+ /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS2_RST = 0 */
+ /* .. ==> 0XF8000240[22:22] = 0x00000000U */
+ /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS1_RST = 0 */
+ /* .. ==> 0XF8000240[21:21] = 0x00000000U */
+ /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS0_RST = 0 */
+ /* .. ==> 0XF8000240[20:20] = 0x00000000U */
+ /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. reserved_2 = 0 */
+ /* .. ==> 0XF8000240[19:18] = 0x00000000U */
+ /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. FSSW1_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[17:17] = 0x00000000U */
+ /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. FSSW0_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[16:16] = 0x00000000U */
+ /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. reserved_1 = 0 */
+ /* .. ==> 0XF8000240[15:14] = 0x00000000U */
+ /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
+ /* .. FPGA_FMSW1_RST = 0 */
+ /* .. ==> 0XF8000240[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. FPGA_FMSW0_RST = 0 */
+ /* .. ==> 0XF8000240[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. FPGA_DMA3_RST = 0 */
+ /* .. ==> 0XF8000240[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. FPGA_DMA2_RST = 0 */
+ /* .. ==> 0XF8000240[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. FPGA_DMA1_RST = 0 */
+ /* .. ==> 0XF8000240[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. FPGA_DMA0_RST = 0 */
+ /* .. ==> 0XF8000240[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. reserved = 0 */
+ /* .. ==> 0XF8000240[7:4] = 0x00000000U */
+ /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. FPGA3_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. FPGA2_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. FPGA1_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. FPGA0_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ /* .. FINISH: FPGA RESETS TO 0 */
+ /* .. START: AFI REGISTERS */
+ /* .. .. START: AFI0 REGISTERS */
+ /* .. .. FINISH: AFI0 REGISTERS */
+ /* .. .. START: AFI1 REGISTERS */
+ /* .. .. FINISH: AFI1 REGISTERS */
+ /* .. .. START: AFI2 REGISTERS */
+ /* .. .. FINISH: AFI2 REGISTERS */
+ /* .. .. START: AFI3 REGISTERS */
+ /* .. .. FINISH: AFI3 REGISTERS */
+ /* .. FINISH: AFI REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_debug_1_0[] = {
+ /* START: top */
+ /* .. START: CROSS TRIGGER CONFIGURATIONS */
+ /* .. .. START: UNLOCKING CTI REGISTERS */
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: UNLOCKING CTI REGISTERS */
+ /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char *getPS7MessageInfo(unsigned key)
+{
+ char *err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS:
+ err_msg = "PS7 initialization successful";
+ break;
+ case PS7_INIT_CORRUPT:
+ err_msg = "PS7 init Data Corrupted";
+ break;
+ case PS7_INIT_TIMEOUT:
+ err_msg = "PS7 init mask poll timeout";
+ break;
+ case PS7_POLL_FAILED_DDR_INIT:
+ err_msg = "Mask Poll failed for DDR Init";
+ break;
+ case PS7_POLL_FAILED_DMA:
+ err_msg = "Mask Poll failed for PLL Init";
+ break;
+ case PS7_POLL_FAILED_PLL:
+ err_msg = "Mask Poll failed for DMA done bit";
+ break;
+ default:
+ err_msg = "Undefined error status";
+ break;
+ }
+
+ return err_msg;
+}
+
+unsigned long ps7GetSiliconVersion(void)
+{
+ /* Read PS version from MCTRL register [31:28] */
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long *)0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write(unsigned long add, unsigned long mask, unsigned long val)
+{
+ unsigned long *addr = (unsigned long *)add;
+ *addr = (val & mask) | (*addr & ~mask);
+}
+
+int mask_poll(unsigned long add, unsigned long mask)
+{
+ volatile unsigned long *addr = (volatile unsigned long *)add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME)
+ return -1;
+ i++;
+ }
+ return 1;
+}
+
+unsigned long mask_read(unsigned long add, unsigned long mask)
+{
+ unsigned long *addr = (unsigned long *)add;
+ unsigned long val = (*addr & mask);
+ return val;
+}
+
+int ps7_config(unsigned long *ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; /* current instruction .. */
+ unsigned long args[16]; /* no opcode has so many args ... */
+ int numargs; /* number of arguments of this instruction */
+ int j; /* general purpose index */
+
+ volatile unsigned long *addr; /* some variable to make code readable */
+ unsigned long val, mask; /* some variable to make code readable */
+
+ int finish = -1; /* loop while this is negative ! */
+ int i = 0; /* Timeout variable */
+
+ while (finish < 0) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for (j = 0; j < numargs; j++)
+ args[j] = ptr[j + 1];
+ ptr += numargs + 1;
+
+ switch (opcode) {
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long *)args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long *)args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long *)args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = (val & mask) | (*addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long *)args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ addr = (unsigned long *)args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay))
+ ;
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+ /* Get the PS_VERSION on run time */
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_debug(void)
+{
+ /* Get the PS_VERSION on run time */
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ /* Get the PS_VERSION on run time */
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret;
+ /*int pcw_ver = 0; */
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ /*pcw_ver = 1; */
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ /*pcw_ver = 2; */
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ /*pcw_ver = 3; */
+ }
+
+ /* MIO init */
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ /* PLL init */
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ /* Clock init */
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ /* DDR init */
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ /* Peripherals init */
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
+
+/* For delay calculation using global timer */
+
+/* start timer */
+void perf_start_clock(void)
+{
+ *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */
+ (1 << 3) | /* Auto-increment */
+ (0 << 8) /* Pre-scale */
+ );
+}
+
+/* stop timer and reset timer count regs */
+void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
+ return APU_FREQ * delay / (2 * 1000);
+}
+
+/* stop timer */
+void perf_disable_clock(void)
+{
+ *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer(void)
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
new file mode 100644
index 0000000..62b8a58
--- /dev/null
+++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*typedef unsigned int u32; */
+
+/** do we need to make this name more unique ? **/
+/*extern u32 ps7_init_data[]; */
+extern unsigned long *ps7_ddr_init_data;
+extern unsigned long *ps7_mio_init_data;
+extern unsigned long *ps7_pll_init_data;
+extern unsigned long *ps7_clock_init_data;
+extern unsigned long *ps7_peripherals_init_data;
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
+#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr
+#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
+#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
+#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask
+#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */
+#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */
+#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */
+#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */
+#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */
+#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 650000000
+#define DDR_FREQ 525000000
+#define DCI_FREQ 10096154
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 125000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 50000000
+#define UART_FREQ 50000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 108333336
+#define WDT_FREQ 108333336
+#define TTC_FREQ 50000000
+#define CAN_FREQ 10000000
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 100000000
+#define FPGA1_FREQ 175000000
+#define FPGA2_FREQ 12264151
+#define FPGA3_FREQ 100000000
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config(unsigned long *);
+int ps7_init(void);
+int ps7_post_config(void);
+int ps7_debug(void);
+char *getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(void);
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
diff --git a/common/Kconfig b/common/Kconfig
index ccf5475..9d446bf 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -184,6 +184,9 @@
help
Extract a part of a multi-image.
+config CMD_POWEROFF
+ bool
+
endmenu
menu "Environment commands"
diff --git a/common/cli.c b/common/cli.c
index fbcd339..119d282 100644
--- a/common/cli.c
+++ b/common/cli.c
@@ -103,9 +103,9 @@
* is pretty rare.
*/
rcode = cli_simple_run_command_list(buff, flag);
+#endif
if (need_buff)
free(buff);
-#endif
return rcode;
}
diff --git a/common/cli_simple.c b/common/cli_simple.c
index 9c3d073..bb96aae 100644
--- a/common/cli_simple.c
+++ b/common/cli_simple.c
@@ -276,7 +276,8 @@
flag = 0; /* assume no special flags for now */
if (len > 0)
- strcpy(lastcommand, console_buffer);
+ strlcpy(lastcommand, console_buffer,
+ CONFIG_SYS_CBSIZE + 1);
else if (len == 0)
flag |= CMD_FLAG_REPEAT;
#ifdef CONFIG_BOOT_RETRY_TIME
diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 8f2e070..72f2cf3 100644
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -61,3 +61,11 @@
"Perform RESET of the CPU",
""
);
+
+#ifdef CONFIG_CMD_POWEROFF
+U_BOOT_CMD(
+ poweroff, 1, 0, do_poweroff,
+ "Perform POWEROFF of the device",
+ ""
+);
+#endif
diff --git a/common/cmd_disk.c b/common/cmd_disk.c
index 8a1fda9..3025225 100644
--- a/common/cmd_disk.c
+++ b/common/cmd_disk.c
@@ -56,7 +56,7 @@
", Block Size: %ld\n",
info.start, info.size, info.blksz);
- if (dev_desc->block_read(dev, info.start, 1, (ulong *) addr) != 1) {
+ if (dev_desc->block_read(dev_desc, info.start, 1, (ulong *)addr) != 1) {
printf("** Read error on %d:%d\n", dev, part);
bootstage_error(BOOTSTAGE_ID_IDE_PART_READ);
return 1;
@@ -100,8 +100,8 @@
cnt /= info.blksz;
cnt -= 1;
- if (dev_desc->block_read(dev, info.start + 1, cnt,
- (ulong *)(addr + info.blksz)) != cnt) {
+ if (dev_desc->block_read(dev_desc, info.start + 1, cnt,
+ (ulong *)(addr + info.blksz)) != cnt) {
printf("** Read error on %d:%d\n", dev, part);
bootstage_error(BOOTSTAGE_ID_IDE_READ);
return 1;
diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index 86e694a..5190cc6 100644
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -288,9 +288,10 @@
(size_t)255));
} else {
tmp = getenv("bootdev");
- if (tmp)
- ptr = sprintf(build_buf, tmp);
- else
+ if (tmp) {
+ strcpy(build_buf, tmp);
+ ptr = strlen(tmp);
+ } else
printf("## VxWorks boot device not specified\n");
tmp = getenv("bootfile");
@@ -331,8 +332,10 @@
ptr += sprintf(build_buf + ptr, "tn=%s ", tmp);
tmp = getenv("othbootargs");
- if (tmp)
- ptr += sprintf(build_buf + ptr, tmp);
+ if (tmp) {
+ strcpy(build_buf + ptr, tmp);
+ ptr += strlen(tmp);
+ }
memcpy((void *)bootaddr, build_buf,
max(strlen(build_buf), (size_t)255));
diff --git a/common/cmd_fs.c b/common/cmd_fs.c
index e146254..8f8f1b2 100644
--- a/common/cmd_fs.c
+++ b/common/cmd_fs.c
@@ -3,17 +3,7 @@
*
* Inspired by cmd_ext_common.c, cmd_fat.c.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index ecd3e9d..f19a7ce 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -79,8 +79,8 @@
#ifdef CONFIG_ATAPI
static void atapi_inquiry(block_dev_desc_t *dev_desc);
-static ulong atapi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer);
+static ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer);
#endif
@@ -187,6 +187,7 @@
if (strcmp(argv[1], "read") == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong cnt = simple_strtoul(argv[4], NULL, 16);
+ block_dev_desc_t *dev_desc;
ulong n;
#ifdef CONFIG_SYS_64BIT_LBA
@@ -201,9 +202,9 @@
curr_device, blk, cnt);
#endif
- n = ide_dev_desc[curr_device].block_read(curr_device,
- blk, cnt,
- (ulong *)addr);
+ dev_desc = &ide_dev_desc[curr_device];
+ n = dev_desc->block_read(dev_desc, blk, cnt,
+ (ulong *)addr);
/* flush cache after read */
flush_cache(addr,
cnt * ide_dev_desc[curr_device].blksz);
@@ -230,7 +231,8 @@
printf("\nIDE write: device %d block # %ld, count %ld ... ",
curr_device, blk, cnt);
#endif
- n = ide_write(curr_device, blk, cnt, (ulong *) addr);
+ n = ide_write(&ide_dev_desc[curr_device], blk, cnt,
+ (ulong *)addr);
printf("%ld blocks written: %s\n",
n, (n == cnt) ? "OK" : "ERROR");
@@ -711,8 +713,10 @@
/* ------------------------------------------------------------------------- */
-ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
{
+ int device = block_dev->dev;
ulong n = 0;
unsigned char c;
unsigned char pwrsave = 0; /* power save */
@@ -835,8 +839,10 @@
/* ------------------------------------------------------------------------- */
-ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt, const void *buffer)
+ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
{
+ int device = block_dev->dev;
ulong n = 0;
unsigned char c;
@@ -1388,8 +1394,10 @@
#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
-ulong atapi_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
+ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
{
+ int device = block_dev->dev;
ulong n = 0;
unsigned char ccb[12]; /* Command descriptor block */
ulong cnt;
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 9fb2584..efa3929 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -931,7 +931,7 @@
addr[offset] = 0;
}
- return 0;
+ return errs;
}
static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
@@ -990,7 +990,7 @@
val += incr;
}
- return 0;
+ return errs;
}
/*
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index a6b7313..1c7156f 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -312,20 +312,14 @@
return CMD_RET_FAILURE;
}
/* Switch to the RPMB partition */
- original_part = mmc->part_num;
- if (mmc->part_num != MMC_PART_RPMB) {
- if (mmc_switch_part(curr_device, MMC_PART_RPMB) != 0)
- return CMD_RET_FAILURE;
- mmc->part_num = MMC_PART_RPMB;
- }
+ original_part = mmc->block_dev.part_num;
+ if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0)
+ return CMD_RET_FAILURE;
ret = cp->cmd(cmdtp, flag, argc, argv);
/* Return to original partition */
- if (mmc->part_num != original_part) {
- if (mmc_switch_part(curr_device, original_part) != 0)
- return CMD_RET_FAILURE;
- mmc->part_num = original_part;
- }
+ if (mmc_select_hwpart(curr_device, original_part) != 0)
+ return CMD_RET_FAILURE;
return ret;
}
#endif
@@ -351,7 +345,7 @@
printf("\nMMC read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
- n = mmc->block_dev.block_read(curr_device, blk, cnt, addr);
+ n = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512); /* FIXME */
printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
@@ -383,7 +377,7 @@
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = mmc->block_dev.block_write(curr_device, blk, cnt, addr);
+ n = mmc->block_dev.block_write(&mmc->block_dev, blk, cnt, addr);
printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
@@ -411,7 +405,7 @@
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = mmc->block_dev.block_erase(curr_device, blk, cnt);
+ n = mmc->block_dev.block_erase(&mmc->block_dev, blk, cnt);
printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
@@ -483,7 +477,7 @@
printf("mmc%d is current device\n", curr_device);
else
printf("mmc%d(part %d) is current device\n",
- curr_device, mmc->part_num);
+ curr_device, mmc->block_dev.hwpart);
return CMD_RET_SUCCESS;
}
diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c
index 422c069..dab1958 100644
--- a/common/cmd_mtdparts.c
+++ b/common/cmd_mtdparts.c
@@ -1086,7 +1086,7 @@
return 0;
}
- sprintf(p, "mtdparts=");
+ strcpy(p, "mtdparts=");
p += 9;
list_for_each(dentry, &devices) {
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 2f9cdd0..5ae9d9d 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -595,7 +595,7 @@
/* Set read buffer to initial value or empty sting */
init_val = getenv(argv[1]);
if (init_val)
- sprintf(buffer, "%s", init_val);
+ snprintf(buffer, CONFIG_SYS_CBSIZE, "%s", init_val);
else
buffer[0] = '\0';
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index 4e0951f..8094d33 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -606,7 +606,7 @@
}
#ifdef CONFIG_DM_PCI
- ret = pci_bus_find_bdf(bdf, &dev);
+ ret = dm_pci_bus_find_bdf(bdf, &dev);
if (ret) {
printf("No such device\n");
return CMD_RET_FAILURE;
diff --git a/common/cmd_read.c b/common/cmd_read.c
index f0fc9bf..8710288 100644
--- a/common/cmd_read.c
+++ b/common/cmd_read.c
@@ -66,7 +66,7 @@
return 1;
}
- if (dev_desc->block_read(dev, offset + blk, cnt, addr) < 0) {
+ if (dev_desc->block_read(dev_desc, offset + blk, cnt, addr) < 0) {
printf("Error reading blocks\n");
return 1;
}
diff --git a/common/cmd_sata.c b/common/cmd_sata.c
index 51f6703..76bacea 100644
--- a/common/cmd_sata.c
+++ b/common/cmd_sata.c
@@ -18,6 +18,18 @@
static int sata_curr_device = -1;
block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+static unsigned long sata_bread(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, void *dst)
+{
+ return sata_read(block_dev->dev, start, blkcnt, dst);
+}
+
+static unsigned long sata_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *buffer)
+{
+ return sata_write(block_dev->dev, start, blkcnt, buffer);
+}
+
int __sata_initialize(void)
{
int rc;
@@ -32,8 +44,8 @@
sata_dev_desc[i].lba = 0;
sata_dev_desc[i].blksz = 512;
sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
- sata_dev_desc[i].block_read = sata_read;
- sata_dev_desc[i].block_write = sata_write;
+ sata_dev_desc[i].block_read = sata_bread;
+ sata_dev_desc[i].block_write = sata_bwrite;
rc = init_sata(i);
if (!rc) {
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index 31c4319..bc7d1b6 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -66,9 +66,9 @@
static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
unsigned long *blksz);
-static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer);
-static ulong scsi_write(int device, lbaint_t blknr,
+static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer);
+static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer);
@@ -184,7 +184,7 @@
#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
void scsi_init(void)
{
- int busdevfunc;
+ int busdevfunc = -1;
int i;
/*
* Find a device from the list, this driver will support a single
@@ -192,9 +192,21 @@
*/
for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
/* get PCI Device ID */
+#ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+ int ret;
+
+ ret = dm_pci_find_device(scsi_device_list[i].vendor,
+ scsi_device_list[i].device, 0, &dev);
+ if (!ret) {
+ busdevfunc = dm_pci_get_bdf(dev);
+ break;
+ }
+#else
busdevfunc = pci_find_device(scsi_device_list[i].vendor,
scsi_device_list[i].device,
0);
+#endif
if (busdevfunc != -1)
break;
}
@@ -334,7 +346,8 @@
ulong n;
printf ("\nSCSI read: device %d block # %ld, count %ld ... ",
scsi_curr_dev, blk, cnt);
- n = scsi_read(scsi_curr_dev, blk, cnt, (ulong *)addr);
+ n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
+ blk, cnt, (ulong *)addr);
printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR");
return 0;
} else if (strcmp(argv[1], "write") == 0) {
@@ -345,8 +358,8 @@
printf("\nSCSI write: device %d block # %ld, "
"count %ld ... ",
scsi_curr_dev, blk, cnt);
- n = scsi_write(scsi_curr_dev, blk, cnt,
- (ulong *)addr);
+ n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
+ blk, cnt, (ulong *)addr);
printf("%ld blocks written: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
return 0;
@@ -363,9 +376,10 @@
#define SCSI_MAX_READ_BLK 0xFFFF
#define SCSI_LBA48_READ 0xFFFFFFF
-static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer)
+static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks = 0;
@@ -429,9 +443,10 @@
/* Almost the maximum amount of the scsi_ext command.. */
#define SCSI_MAX_WRITE_BLK 0xFFFF
-static ulong scsi_write(int device, lbaint_t blknr,
+static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index a540b42..c7b642c 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -759,7 +759,7 @@
printf("\nUSB read: device %d block # %ld, count %ld"
" ... ", usb_stor_curr_dev, blk, cnt);
stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
- n = stor_dev->block_read(usb_stor_curr_dev, blk, cnt,
+ n = stor_dev->block_read(stor_dev, blk, cnt,
(ulong *)addr);
printf("%ld blocks read: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
@@ -781,7 +781,7 @@
printf("\nUSB write: device %d block # %ld, count %ld"
" ... ", usb_stor_curr_dev, blk, cnt);
stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
- n = stor_dev->block_write(usb_stor_curr_dev, blk, cnt,
+ n = stor_dev->block_write(stor_dev, blk, cnt,
(ulong *)addr);
printf("%ld blocks write: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c
index 0407389..0415591 100644
--- a/common/cmd_usb_mass_storage.c
+++ b/common/cmd_usb_mass_storage.c
@@ -2,6 +2,8 @@
* Copyright (C) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -17,50 +19,107 @@
static int ums_read_sector(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, void *buf)
{
- block_dev_desc_t *block_dev = ums_dev->block_dev;
+ block_dev_desc_t *block_dev = &ums_dev->block_dev;
lbaint_t blkstart = start + ums_dev->start_sector;
- int dev_num = block_dev->dev;
- return block_dev->block_read(dev_num, blkstart, blkcnt, buf);
+ return block_dev->block_read(block_dev, blkstart, blkcnt, buf);
}
static int ums_write_sector(struct ums *ums_dev,
ulong start, lbaint_t blkcnt, const void *buf)
{
- block_dev_desc_t *block_dev = ums_dev->block_dev;
+ block_dev_desc_t *block_dev = &ums_dev->block_dev;
lbaint_t blkstart = start + ums_dev->start_sector;
- int dev_num = block_dev->dev;
- return block_dev->block_write(dev_num, blkstart, blkcnt, buf);
+ return block_dev->block_write(block_dev, blkstart, blkcnt, buf);
}
-static struct ums ums_dev = {
- .read_sector = ums_read_sector,
- .write_sector = ums_write_sector,
- .name = "UMS disk",
-};
+static struct ums *ums;
+static int ums_count;
-struct ums *ums_init(const char *devtype, const char *devnum)
+static void ums_fini(void)
{
+ int i;
+
+ for (i = 0; i < ums_count; i++)
+ free((void *)ums[i].name);
+ free(ums);
+ ums = 0;
+ ums_count = 0;
+}
+
+#define UMS_NAME_LEN 16
+
+static int ums_init(const char *devtype, const char *devnums)
+{
+ char *s, *t, *devnum, *name;
block_dev_desc_t *block_dev;
int ret;
+ struct ums *ums_new;
- ret = get_device(devtype, devnum, &block_dev);
- if (ret < 0)
- return NULL;
+ s = strdup(devnums);
+ if (!s)
+ return -1;
+
+ t = s;
+ ums_count = 0;
+
+ for (;;) {
+ devnum = strsep(&t, ",");
+ if (!devnum)
+ break;
+
+ ret = get_device(devtype, devnum, &block_dev);
+ if (ret < 0)
+ goto cleanup;
+
+ /* f_mass_storage.c assumes SECTOR_SIZE sectors */
+ if (block_dev->blksz != SECTOR_SIZE) {
+ ret = -1;
+ goto cleanup;
+ }
+
+ ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums));
+ if (!ums_new) {
+ ret = -1;
+ goto cleanup;
+ }
+ ums = ums_new;
+
+ ums[ums_count].read_sector = ums_read_sector;
+ ums[ums_count].write_sector = ums_write_sector;
+ ums[ums_count].start_sector = 0;
+ ums[ums_count].num_sectors = block_dev->lba;
+ name = malloc(UMS_NAME_LEN);
+ if (!name) {
+ ret = -1;
+ goto cleanup;
+ }
+ snprintf(name, UMS_NAME_LEN, "UMS disk %d", ums_count);
+ ums[ums_count].name = name;
+ ums[ums_count].block_dev = *block_dev;
+
+ printf("UMS: LUN %d, dev %d, hwpart %d, sector %#x, count %#x\n",
+ ums_count, ums[ums_count].block_dev.dev,
+ ums[ums_count].block_dev.hwpart,
+ ums[ums_count].start_sector,
+ ums[ums_count].num_sectors);
+
+ ums_count++;
+ }
- /* f_mass_storage.c assumes SECTOR_SIZE sectors */
- if (block_dev->blksz != SECTOR_SIZE)
- return NULL;
+ if (!ums_count)
+ ret = -1;
+ else
+ ret = 0;
- ums_dev.block_dev = block_dev;
- ums_dev.start_sector = 0;
- ums_dev.num_sectors = block_dev->lba;
+cleanup:
+ free(s);
- printf("UMS: disk start sector: %#x, count: %#x\n",
- ums_dev.start_sector, ums_dev.num_sectors);
+ if (ret < 0)
+ ums_fini();
- return &ums_dev;
+ return ret;
}
int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
@@ -69,7 +128,6 @@
const char *usb_controller;
const char *devtype;
const char *devnum;
- struct ums *ums;
unsigned int controller_index;
int rc;
int cable_ready_timeout __maybe_unused;
@@ -86,27 +144,30 @@
devnum = argv[2];
}
- ums = ums_init(devtype, devnum);
- if (!ums)
+ rc = ums_init(devtype, devnum);
+ if (rc < 0)
return CMD_RET_FAILURE;
controller_index = (unsigned int)(simple_strtoul(
usb_controller, NULL, 0));
if (board_usb_init(controller_index, USB_INIT_DEVICE)) {
error("Couldn't init USB controller.");
- return CMD_RET_FAILURE;
+ rc = CMD_RET_FAILURE;
+ goto cleanup_ums_init;
}
- rc = fsg_init(ums);
+ rc = fsg_init(ums, ums_count);
if (rc) {
error("fsg_init failed");
- return CMD_RET_FAILURE;
+ rc = CMD_RET_FAILURE;
+ goto cleanup_board;
}
rc = g_dnl_register("usb_dnl_ums");
if (rc) {
error("g_dnl_register failed");
- return CMD_RET_FAILURE;
+ rc = CMD_RET_FAILURE;
+ goto cleanup_board;
}
/* Timeout unit: seconds */
@@ -122,12 +183,14 @@
while (!g_dnl_board_usb_cable_connected()) {
if (ctrlc()) {
puts("\rCTRL+C - Operation aborted.\n");
- goto exit;
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
}
if (!cable_ready_timeout) {
puts("\rUSB cable not detected.\n" \
"Command exit.\n");
- goto exit;
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
}
printf("\rAuto exit in: %.2d s.", cable_ready_timeout);
@@ -150,13 +213,19 @@
if (rc == -EPIPE)
printf("\rCTRL+C - Operation aborted\n");
- goto exit;
+ rc = CMD_RET_SUCCESS;
+ goto cleanup_register;
}
}
-exit:
+
+cleanup_register:
g_dnl_unregister();
+cleanup_board:
board_usb_cleanup(controller_index, USB_INIT_DEVICE);
- return CMD_RET_SUCCESS;
+cleanup_ums_init:
+ ums_fini();
+
+ return rc;
}
U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
diff --git a/common/ddr_spd.c b/common/ddr_spd.c
index 438e71a..0aa1cbf 100644
--- a/common/ddr_spd.c
+++ b/common/ddr_spd.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/common/env_callback.c b/common/env_callback.c
index f4d3dbd..1957cc1 100644
--- a/common/env_callback.c
+++ b/common/env_callback.c
@@ -97,6 +97,7 @@
e.key = name;
e.data = NULL;
+ e.callback = NULL;
hsearch_r(e, FIND, &ep, &env_htab, 0);
/* does the env variable actually exist? */
diff --git a/common/env_flags.c b/common/env_flags.c
index e682d85..9c3aed1 100644
--- a/common/env_flags.c
+++ b/common/env_flags.c
@@ -152,7 +152,7 @@
{
int i;
- for (i = 0; i < sizeof(env_flags_varaccess_mask); i++)
+ for (i = 0; i < ARRAY_SIZE(env_flags_varaccess_mask); i++)
if (env_flags_varaccess_mask[i] ==
(binflags & ENV_FLAGS_VARACCESS_BIN_MASK))
return (enum env_flags_varaccess)i;
@@ -455,6 +455,7 @@
e.key = name;
e.data = NULL;
+ e.callback = NULL;
hsearch_r(e, FIND, &ep, &env_htab, 0);
/* does the env variable actually exist? */
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 9639822..15aa43d 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -69,6 +69,8 @@
return CONFIG_SYS_MMC_ENV_PART;
}
+static unsigned char env_mmc_orig_hwpart;
+
static int mmc_set_env_part(struct mmc *mmc)
{
uint part = mmc_get_env_part(mmc);
@@ -79,11 +81,10 @@
dev = 0;
#endif
- if (part != mmc->part_num) {
- ret = mmc_switch_part(dev, part);
- if (ret)
- puts("MMC partition switch failed\n");
- }
+ env_mmc_orig_hwpart = mmc->block_dev.hwpart;
+ ret = mmc_select_hwpart(dev, part);
+ if (ret)
+ puts("MMC partition switch failed\n");
return ret;
}
@@ -113,8 +114,7 @@
#ifdef CONFIG_SPL_BUILD
dev = 0;
#endif
- if (mmc_get_env_part(mmc) != mmc->part_num)
- mmc_switch_part(dev, mmc->part_num);
+ mmc_select_hwpart(dev, env_mmc_orig_hwpart);
#endif
}
@@ -127,7 +127,7 @@
blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
- n = mmc->block_dev.block_write(CONFIG_SYS_MMC_ENV_DEV, blk_start,
+ n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
blk_cnt, (u_char *)buffer);
return (n == blk_cnt) ? 0 : -1;
@@ -192,16 +192,12 @@
unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
- int dev = CONFIG_SYS_MMC_ENV_DEV;
-
-#ifdef CONFIG_SPL_BUILD
- dev = 0;
-#endif
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(dev, blk_start, blk_cnt, (uchar *)buffer);
+ n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
+ (uchar *)buffer);
return (n == blk_cnt) ? 0 : -1;
}
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index b480e76..6e742da 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -58,7 +58,7 @@
block_dev_desc_t *dev_desc = sparse->dev_desc;
int ret;
- ret = dev_desc->block_write(dev_desc->dev, offset, size, data);
+ ret = dev_desc->block_write(dev_desc, offset, size, data);
if (!ret)
return -EIO;
@@ -84,8 +84,7 @@
puts("Flashing Raw Image\n");
- blks = dev_desc->block_write(dev_desc->dev, info->start, blkcnt,
- buffer);
+ blks = dev_desc->block_write(dev_desc, info->start, blkcnt, buffer);
if (blks != blkcnt) {
error("failed writing to device %d\n", dev_desc->dev);
fastboot_fail(response_str, "failed writing to device");
@@ -206,7 +205,7 @@
printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n",
blks_start, blks_start + blks_size);
- blks = dev_desc->block_erase(dev_desc->dev, blks_start, blks_size);
+ blks = dev_desc->block_erase(dev_desc, blks_start, blks_size);
if (blks != blks_size) {
error("failed erasing from device %d", dev_desc->dev);
fastboot_fail(response_str, "failed erasing from device");
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 66464db..09f9237 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -482,47 +482,49 @@
void fdt_fixup_ethernet(void *fdt)
{
int node, i, j;
- char enet[16], *tmp, *end;
+ char *tmp, *end;
char mac[16];
const char *path;
unsigned char mac_addr[6];
+ int offset;
node = fdt_path_offset(fdt, "/aliases");
if (node < 0)
return;
- if (!getenv("ethaddr")) {
- if (getenv("usbethaddr")) {
- strcpy(mac, "usbethaddr");
- } else {
- debug("No ethernet MAC Address defined\n");
- return;
- }
- } else {
- strcpy(mac, "ethaddr");
- }
-
- i = 0;
- while ((tmp = getenv(mac)) != NULL) {
- sprintf(enet, "ethernet%d", i);
- path = fdt_getprop(fdt, node, enet, NULL);
- if (!path) {
- debug("No alias for %s\n", enet);
- sprintf(mac, "eth%daddr", ++i);
- continue;
- }
+ for (offset = fdt_first_property_offset(fdt, node);
+ offset > 0;
+ offset = fdt_next_property_offset(fdt, offset)) {
+ const char *name;
+ int len = strlen("ethernet");
- for (j = 0; j < 6; j++) {
- mac_addr[j] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
- if (tmp)
- tmp = (*end) ? end+1 : end;
- }
+ path = fdt_getprop_by_offset(fdt, offset, &name, NULL);
+ if (!strncmp(name, "ethernet", len)) {
+ i = trailing_strtol(name);
+ if (i != -1) {
+ if (i == 0)
+ strcpy(mac, "ethaddr");
+ else
+ sprintf(mac, "eth%daddr", i);
+ } else {
+ continue;
+ }
+ tmp = getenv(mac);
+ if (!tmp)
+ continue;
- do_fixup_by_path(fdt, path, "mac-address", &mac_addr, 6, 0);
- do_fixup_by_path(fdt, path, "local-mac-address",
- &mac_addr, 6, 1);
+ for (j = 0; j < 6; j++) {
+ mac_addr[j] = tmp ?
+ simple_strtoul(tmp, &end, 16) : 0;
+ if (tmp)
+ tmp = (*end) ? end + 1 : end;
+ }
- sprintf(mac, "eth%daddr", ++i);
+ do_fixup_by_path(fdt, path, "mac-address",
+ &mac_addr, 6, 0);
+ do_fixup_by_path(fdt, path, "local-mac-address",
+ &mac_addr, 6, 1);
+ }
}
}
@@ -952,8 +954,7 @@
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDR FDT_ADDR_T_NONE
-#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
- (ns) > 0)
+#define OF_CHECK_COUNTS(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS)
/* Debug utility */
#ifdef DEBUG
@@ -1121,7 +1122,7 @@
/* Cound address cells & copy address locally */
bus->count_cells(blob, parent, &na, &ns);
- if (!OF_CHECK_COUNTS(na, ns)) {
+ if (!OF_CHECK_COUNTS(na)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
fdt_get_name(blob, node_offset, NULL));
goto bail;
@@ -1148,7 +1149,7 @@
/* Get new parent bus and counts */
pbus = &of_busses[0];
pbus->count_cells(blob, parent, &pna, &pns);
- if (!OF_CHECK_COUNTS(pna, pns)) {
+ if (!OF_CHECK_COUNTS(pna)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
fdt_get_name(blob, node_offset, NULL));
break;
diff --git a/common/hash.c b/common/hash.c
index a1b0482..41de4df 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -247,6 +247,29 @@
return 0;
}
+int hash_block(const char *algo_name, const void *data, unsigned int len,
+ uint8_t *output, int *output_size)
+{
+ struct hash_algo *algo;
+ int ret;
+
+ ret = hash_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ if (output_size && *output_size < algo->digest_size) {
+ debug("Output buffer size %d too small (need %d bytes)",
+ *output_size, algo->digest_size);
+ return -ENOSPC;
+ }
+ if (output_size)
+ *output_size = algo->digest_size;
+ algo->hash_func_ws(data, len, output, algo->chunk_size);
+
+ return 0;
+}
+
+#if defined(CONFIG_CMD_HASH) || defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32)
/**
* store_result: Store the resulting sum to an address or variable
*
@@ -359,7 +382,7 @@
return 0;
}
-void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
+static void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
{
int i;
@@ -368,28 +391,6 @@
printf("%02x", output[i]);
}
-int hash_block(const char *algo_name, const void *data, unsigned int len,
- uint8_t *output, int *output_size)
-{
- struct hash_algo *algo;
- int ret;
-
- ret = hash_lookup_algo(algo_name, &algo);
- if (ret)
- return ret;
-
- if (output_size && *output_size < algo->digest_size) {
- debug("Output buffer size %d too small (need %d bytes)",
- *output_size, algo->digest_size);
- return -ENOSPC;
- }
- if (output_size)
- *output_size = algo->digest_size;
- algo->hash_func_ws(data, len, output, algo->chunk_size);
-
- return 0;
-}
-
int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
@@ -473,3 +474,4 @@
return 0;
}
#endif
+#endif
diff --git a/common/image.c b/common/image.c
index c36927f..f4a1dc8 100644
--- a/common/image.c
+++ b/common/image.c
@@ -472,9 +472,9 @@
#if defined(CONFIG_ARM) && defined(CONFIG_NR_DRAM_BANKS)
- return gd->bd->bi_dram[0].size - tmp;
+ return gd->bd->bi_dram[0].size - (tmp - gd->bd->bi_dram[0].start);
#else
- return gd->bd->bi_memsize - tmp;
+ return gd->bd->bi_memsize - (tmp - gd->bd->bi_memstart);
#endif
}
@@ -1113,8 +1113,7 @@
if (initrd_high == ~0)
initrd_copy_to_ram = 0;
} else {
- /* not set, no restrictions to load high */
- initrd_high = ~0;
+ initrd_high = getenv_bootm_mapsize() + getenv_bootm_low();
}
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 1c6126d..d17bb29 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -21,39 +21,128 @@
#define _USE_MEMCPY
#endif
-/* Unfortunately x86 can't compile this code as gd cannot be assigned */
-#ifndef CONFIG_X86
+/* Unfortunately x86 or ARM can't compile this code as gd cannot be assigned */
+#if !defined(CONFIG_X86) && !defined(CONFIG_ARM)
__weak void arch_setup_gd(struct global_data *gd_ptr)
{
gd = gd_ptr;
}
-#endif /* !CONFIG_X86 */
+#endif /* !CONFIG_X86 && !CONFIG_ARM */
-ulong board_init_f_mem(ulong top)
+/*
+ * Allocate reserved space for use as 'globals' from 'top' address and
+ * return 'bottom' address of allocated space
+ *
+ * Notes:
+ *
+ * Actual reservation cannot be done from within this function as
+ * it requires altering the C stack pointer, so this will be done by
+ * the caller upon return from this function.
+ *
+ * IMPORTANT:
+ *
+ * Alignment constraints may differ for each 'chunk' allocated. For now:
+ *
+ * - GD is aligned down on a 16-byte boundary
+ *
+ * - the early malloc arena is not aligned, therefore it follows the stack
+ * alignment constraint of the architecture for which we are bulding.
+ *
+ * - GD is allocated last, so that the return value of this functions is
+ * both the bottom of the reserved area and the address of GD, should
+ * the calling context need it.
+ */
+
+ulong board_init_f_alloc_reserve(ulong top)
+{
+ /* Reserve early malloc arena */
+#if defined(CONFIG_SYS_MALLOC_F)
+ top -= CONFIG_SYS_MALLOC_F_LEN;
+#endif
+ /* LAST : reserve GD (rounded up to a multiple of 16 bytes) */
+ top = rounddown(top-sizeof(struct global_data), 16);
+
+ return top;
+}
+
+/*
+ * Initialize reserved space (which has been safely allocated on the C
+ * stack from the C runtime environment handling code).
+ *
+ * Notes:
+ *
+ * Actual reservation was done by the caller; the locations from base
+ * to base+size-1 (where 'size' is the value returned by the allocation
+ * function above) can be accessed freely without risk of corrupting the
+ * C runtime environment.
+ *
+ * IMPORTANT:
+ *
+ * Upon return from the allocation function above, on some architectures
+ * the caller will set gd to the lowest reserved location. Therefore, in
+ * this initialization function, the global data MUST be placed at base.
+ *
+ * ALSO IMPORTANT:
+ *
+ * On some architectures, gd will already be good when entering this
+ * function. On others, it will only be good once arch_setup_gd() returns.
+ * Therefore, global data accesses must be done:
+ *
+ * - through gd_ptr if before the call to arch_setup_gd();
+ *
+ * - through gd once arch_setup_gd() has been called.
+ *
+ * Do not use 'gd->' until arch_setup_gd() has been called!
+ *
+ * IMPORTANT TOO:
+ *
+ * Initialization for each "chunk" (GD, early malloc arena...) ends with
+ * an incrementation line of the form 'base += <some size>'. The last of
+ * these incrementations seems useless, as base will not be used any
+ * more after this incrementation; but if/when a new "chunk" is appended,
+ * this increment will be essential as it will give base right value for
+ * this new chunk (which will have to end with its own incrementation
+ * statement). Besides, the compiler's optimizer will silently detect
+ * and remove the last base incrementation, therefore leaving that last
+ * (seemingly useless) incrementation causes no code increase.
+ */
+
+void board_init_f_init_reserve(ulong base)
{
struct global_data *gd_ptr;
#ifndef _USE_MEMCPY
int *ptr;
#endif
- /* Leave space for the stack we are running with now */
- top -= 0x40;
+ /*
+ * clear GD entirely and set it up.
+ * Use gd_ptr, as gd may not be properly set yet.
+ */
- top -= sizeof(struct global_data);
- top = ALIGN(top, 16);
- gd_ptr = (struct global_data *)top;
+ gd_ptr = (struct global_data *)base;
+ /* zero the area */
#ifdef _USE_MEMCPY
memset(gd_ptr, '\0', sizeof(*gd));
#else
for (ptr = (int *)gd_ptr; ptr < (int *)(gd_ptr + 1); )
*ptr++ = 0;
#endif
+ /* set GD unless architecture did it already */
+#if !defined(CONFIG_ARM)
arch_setup_gd(gd_ptr);
+#endif
+ /* next alloc will be higher by one GD plus 16-byte alignment */
+ base += roundup(sizeof(struct global_data), 16);
+
+ /*
+ * record early malloc arena start.
+ * Use gd as it is now properly set for all architectures.
+ */
#if defined(CONFIG_SYS_MALLOC_F)
- top -= CONFIG_SYS_MALLOC_F_LEN;
- gd->malloc_base = top;
+ /* go down one 'early malloc arena' */
+ gd->malloc_base = base;
+ /* next alloc will be higher by one 'early malloc arena' size */
+ base += CONFIG_SYS_MALLOC_F_LEN;
#endif
-
- return top;
}
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 7a393dc..e5167bf 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -431,8 +431,13 @@
* more stack space for things like the MMC sub-system.
*
* This function calculates the stack position, copies the global_data into
- * place and returns the new stack position. The caller is responsible for
- * setting up the sp register.
+ * place, sets the new gd (except for ARM, for which setting GD within a C
+ * function may not always work) and returns the new stack position. The
+ * caller is responsible for setting up the sp register and, in the case
+ * of ARM, setting up gd.
+ *
+ * All of this is done using the same layout and alignments as done in
+ * board_init_f_init_reserve() / board_init_f_alloc_reserve().
*
* @return new stack location, or 0 to use the same stack
*/
@@ -440,19 +445,12 @@
{
#ifdef CONFIG_SPL_STACK_R
gd_t *new_gd;
- ulong ptr;
-
- /* Get stack position: use 8-byte alignment for ABI compliance */
- ptr = CONFIG_SPL_STACK_R_ADDR - sizeof(gd_t);
- ptr &= ~7;
- new_gd = (gd_t *)ptr;
- memcpy(new_gd, (void *)gd, sizeof(gd_t));
- gd = new_gd;
+ ulong ptr = CONFIG_SPL_STACK_R_ADDR;
#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
if (!(gd->flags & GD_FLG_SPL_INIT))
- panic("spl_init must be called before heap reloc");
+ panic_str("spl_init must be called before heap reloc");
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
@@ -460,7 +458,13 @@
gd->malloc_ptr = 0;
}
#endif
-
+ /* Get stack position: use 8-byte alignment for ABI compliance */
+ ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16);
+ new_gd = (gd_t *)ptr;
+ memcpy(new_gd, (void *)gd, sizeof(gd_t));
+#if !defined(CONFIG_ARM)
+ gd = new_gd;
+#endif
return ptr;
#else
return 0;
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index c1c29c0..c3931c6 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -23,13 +23,12 @@
unsigned long count;
u32 image_size_sectors;
struct image_header *header;
- int dev_num = mmc->block_dev.dev;
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
sizeof(struct image_header));
/* read image header to find the image size & load address */
- count = mmc->block_dev.block_read(dev_num, sector, 1, header);
+ count = mmc->block_dev.block_read(&mmc->block_dev, sector, 1, header);
debug("read sector %lx, count=%lu\n", sector, count);
if (count == 0)
goto end;
@@ -46,7 +45,8 @@
mmc->read_bl_len;
/* Read the header too to avoid extra memcpy */
- count = mmc->block_dev.block_read(dev_num, sector, image_size_sectors,
+ count = mmc->block_dev.block_read(&mmc->block_dev, sector,
+ image_size_sectors,
(void *)(ulong)spl_image.load_addr);
debug("read %x sectors to %x\n", image_size_sectors,
spl_image.load_addr);
@@ -150,8 +150,7 @@
{
unsigned long count;
- count = mmc->block_dev.block_read(
- mmc->block_dev.dev,
+ count = mmc->block_dev.block_read(&mmc->block_dev,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS,
(void *) CONFIG_SYS_SPL_ARGS_ADDR);
diff --git a/common/usb.c b/common/usb.c
index 700bfc3..c7b8b0e 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -456,7 +456,7 @@
}
epno = dev->config.if_desc[ifno].no_of_ep;
if_desc = &dev->config.if_desc[ifno];
- if (epno > USB_MAXENDPOINTS) {
+ if (epno >= USB_MAXENDPOINTS) {
printf("Interface %d has too many endpoints!\n",
if_desc->desc.bInterfaceNumber);
return -EINVAL;
@@ -566,13 +566,12 @@
}
/**********************************************************************
- * gets configuration cfgno and store it in the buffer
+ * gets len of configuration cfgno
*/
-int usb_get_configuration_no(struct usb_device *dev,
- unsigned char *buffer, int cfgno)
+int usb_get_configuration_len(struct usb_device *dev, int cfgno)
{
int result;
- unsigned int length;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, 9);
struct usb_config_descriptor *config;
config = (struct usb_config_descriptor *)&buffer[0];
@@ -586,17 +585,23 @@
"(expected %i, got %i)\n", 9, result);
return -EIO;
}
- length = le16_to_cpu(config->wTotalLength);
+ return le16_to_cpu(config->wTotalLength);
+}
- if (length > USB_BUFSIZ) {
- printf("%s: failed to get descriptor - too long: %d\n",
- __func__, length);
- return -EIO;
- }
+/**********************************************************************
+ * gets configuration cfgno and store it in the buffer
+ */
+int usb_get_configuration_no(struct usb_device *dev, int cfgno,
+ unsigned char *buffer, int length)
+{
+ int result;
+ struct usb_config_descriptor *config;
+ config = (struct usb_config_descriptor *)&buffer[0];
result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, length);
- debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, length);
- config->wTotalLength = length; /* validated, with CPU byte order */
+ debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result,
+ le16_to_cpu(config->wTotalLength));
+ config->wTotalLength = result; /* validated, with CPU byte order */
return result;
}
@@ -1070,7 +1075,7 @@
int usb_select_config(struct usb_device *dev)
{
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ);
+ unsigned char *tmpbuf = 0;
int err;
err = get_descriptor_len(dev, USB_DT_DEVICE_SIZE, USB_DT_DEVICE_SIZE);
@@ -1084,14 +1089,23 @@
le16_to_cpus(&dev->descriptor.bcdDevice);
/* only support for one config for now */
- err = usb_get_configuration_no(dev, tmpbuf, 0);
+ err = usb_get_configuration_len(dev, 0);
+ if (err >= 0) {
+ tmpbuf = (unsigned char *)malloc_cache_aligned(err);
+ if (!tmpbuf)
+ err = -ENOMEM;
+ else
+ err = usb_get_configuration_no(dev, 0, tmpbuf, err);
+ }
if (err < 0) {
printf("usb_new_device: Cannot read configuration, " \
"skipping device %04x:%04x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
+ free(tmpbuf);
return err;
}
usb_parse_config(dev, tmpbuf, 0);
+ free(tmpbuf);
usb_set_maxpacket(dev);
/*
* we set the default configuration here
@@ -1199,5 +1213,61 @@
return parent->children[port] != NULL;
#endif
}
+
+#ifdef CONFIG_DM_USB
+void usb_find_usb2_hub_address_port(struct usb_device *udev,
+ uint8_t *hub_address, uint8_t *hub_port)
+{
+ struct udevice *parent;
+ struct usb_device *uparent, *ttdev;
+
+ /*
+ * When called from usb-uclass.c: usb_scan_device() udev->dev points
+ * to the parent udevice, not the actual udevice belonging to the
+ * udev as the device is not instantiated yet. So when searching
+ * for the first usb-2 parent start with udev->dev not
+ * udev->dev->parent .
+ */
+ ttdev = udev;
+ parent = udev->dev;
+ uparent = dev_get_parent_priv(parent);
+
+ while (uparent->speed != USB_SPEED_HIGH) {
+ struct udevice *dev = parent;
+
+ if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
+ printf("Error: Cannot find high speed parent of usb-1 device\n");
+ *hub_address = 0;
+ *hub_port = 0;
+ return;
+ }
+
+ ttdev = dev_get_parent_priv(dev);
+ parent = dev->parent;
+ uparent = dev_get_parent_priv(parent);
+ }
+ *hub_address = uparent->devnum;
+ *hub_port = ttdev->portnr;
+}
+#else
+void usb_find_usb2_hub_address_port(struct usb_device *udev,
+ uint8_t *hub_address, uint8_t *hub_port)
+{
+ /* Find out the nearest parent which is high speed */
+ while (udev->parent->parent != NULL)
+ if (udev->parent->speed != USB_SPEED_HIGH) {
+ udev = udev->parent;
+ } else {
+ *hub_address = udev->parent->devnum;
+ *hub_port = udev->portnr;
+ return;
+ }
+
+ printf("Error: Cannot find high speed parent of usb-1 device\n");
+ *hub_address = 0;
+ *hub_port = 0;
+}
+#endif
+
/* EOF */
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 069fbd2..cbb1995 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -476,6 +476,9 @@
USB_KBD_BOOT_REPORT_SIZE, data->new,
data->intinterval);
if (!data->intq) {
+#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP)
+ if (usb_get_report(dev, iface->desc.bInterfaceNumber,
+ 1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE) < 0) {
#else
if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize,
data->intinterval) < 0) {
@@ -608,6 +611,41 @@
return ret;
}
+static int usb_kbd_remove(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ struct usb_kbd_pdata *data;
+ struct stdio_dev *sdev;
+ int ret;
+
+ sdev = stdio_get_by_name(DEVNAME);
+ if (!sdev) {
+ ret = -ENXIO;
+ goto err;
+ }
+ data = udev->privptr;
+ if (stdio_deregister_dev(sdev, true)) {
+ ret = -EPERM;
+ goto err;
+ }
+#ifdef CONFIG_CONSOLE_MUX
+ if (iomux_doenv(stdin, getenv("stdin"))) {
+ ret = -ENOLINK;
+ goto err;
+ }
+#endif
+#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+ destroy_int_queue(udev, data->intq);
+#endif
+ free(data->new);
+ free(data);
+
+ return 0;
+err:
+ printf("%s: warning, ret=%d", __func__, ret);
+ return ret;
+}
+
static const struct udevice_id usb_kbd_ids[] = {
{ .compatible = "usb-keyboard" },
{ }
@@ -618,6 +656,7 @@
.id = UCLASS_KEYBOARD,
.of_match = usb_kbd_ids,
.probe = usb_kbd_probe,
+ .remove = usb_kbd_remove,
};
static const struct usb_device_id kbd_id_table[] = {
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 4fa6538..4fdb55f 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -65,7 +65,7 @@
static ccb usb_ccb __attribute__((aligned(ARCH_DMA_MINALIGN)));
static __u32 CBWTag;
-#define USB_MAX_STOR_DEV 5
+#define USB_MAX_STOR_DEV 7
static int usb_max_devs; /* number of highest available usb device */
static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV];
@@ -119,10 +119,10 @@
block_dev_desc_t *dev_desc);
int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,
struct us_data *ss);
-unsigned long usb_stor_read(int device, lbaint_t blknr,
- lbaint_t blkcnt, void *buffer);
-unsigned long usb_stor_write(int device, lbaint_t blknr,
- lbaint_t blkcnt, const void *buffer);
+static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer);
+static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, const void *buffer);
void uhci_show_temp_int_td(void);
#ifdef CONFIG_PARTITIONS
@@ -1027,9 +1027,10 @@
}
#endif /* CONFIG_USB_BIN_FIXUP */
-unsigned long usb_stor_read(int device, lbaint_t blknr,
- lbaint_t blkcnt, void *buffer)
+static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
@@ -1097,9 +1098,10 @@
return blkcnt;
}
-unsigned long usb_stor_write(int device, lbaint_t blknr,
- lbaint_t blkcnt, const void *buffer)
+static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, const void *buffer)
{
+ int device = block_dev->dev;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index 0d18e8d..a0d29a0 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -3,6 +3,7 @@
CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
+CONFIG_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index 8bc13f3..9d249c7 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -3,6 +3,7 @@
CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
+CONFIG_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index f616388..001d31b 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -3,6 +3,9 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC3_CD_PIN="PH0"
+CONFIG_MMC3_PINS="PH"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
new file mode 100644
index 0000000..5973fbf
--- /dev/null
+++ b/configs/Empire_electronix_d709_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_EMR1=0
+CONFIG_MMC0_CD_PIN="PG0"
+CONFIG_USB0_VBUS_PIN="PG12"
+CONFIG_USB0_VBUS_DET="PG1"
+CONFIG_USB0_ID_DET="PG2"
+CONFIG_AXP_GPIO=y
+# CONFIG_VIDEO_HDMI is not set
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="AXP0-0"
+CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index 5689cff..806fb64 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -9,4 +9,5 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index a9b6f52..8f78eeb 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -18,3 +18,6 @@
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 38bb9ab..25e4570 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -12,3 +12,4 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 3c65c83..a208a27 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -21,7 +21,6 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index f462e05..0879d1e 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -37,4 +37,3 @@
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index da47707..a515d8d 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -27,7 +27,9 @@
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_FULL is not set
CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_ROCKCHIP_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
@@ -41,5 +43,7 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_ROCKCHIP_SPI=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index dbfbb97..baa0ed8 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -38,5 +38,4 @@
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_TPM=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index ed4428f..c368cc0 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -33,5 +33,4 @@
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_TPM=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
new file mode 100644
index 0000000..57d6a64
--- /dev/null
+++ b/configs/clearfog_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_CLEARFOG=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index cd2be18..fda0db2 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -25,5 +25,4 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_TPM=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 932d9ec..6bc4b8d 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -36,4 +36,3 @@
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index cdcd34c..111f3a1 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_88F6820_GP=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
CONFIG_SPL=y
@@ -7,9 +8,14 @@
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 4c4329d..6dda2ae 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -1,16 +1,23 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_MV784MP_GP=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index 64a0fb0..ddf09fe 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -1,5 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_DEVKIT3250=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL=y
# CONFIG_CMD_FPGA is not set
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 3205bd5..b57ecca 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -20,3 +20,5 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 394edbe..6e5a705 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -19,3 +19,5 @@
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
new file mode 100644
index 0000000..4c3c1df
--- /dev/null
+++ b/configs/ds414_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_DS414=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 2e915ff..c196bd6 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -24,3 +24,9 @@
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_NS16550=y
+CONFIG_DEBUG_UART_BASE=0x20068000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+# CONFIG_SPL_SERIAL_PRESENT is not set
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index b645af5..be4ca88 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -42,5 +42,6 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 0604aa7..925d3ee 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -28,4 +28,3 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
new file mode 100644
index 0000000..60cdebf
--- /dev/null
+++ b/configs/kylin-rk3036_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3036=y
+CONFIG_TARGET_KYLIN_RK3036=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CLK=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_RESET=y
+CONFIG_LED=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_RAM=y
+CONFIG_DM_MMC=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 921c6c4..200c7a0 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -1,14 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MAXBCM=y
-CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 1fe2e0f..54aa3ef 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -1,9 +1,9 @@
CONFIG_MICROBLAZE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL=y
CONFIG_SYS_PROMPT="U-Boot-mONStR> "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 864fd1b..af6a8ec 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -39,4 +39,3 @@
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 75afca9..358caa5 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
# CONFIG_VIDEO is not set
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
deleted file mode 100644
index 4474ec3..0000000
--- a/configs/ph1_sld8_defconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_UNIPHIER_PH1_SLD8=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_UNIPHIER_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 8c86931..b0c935c 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -30,4 +30,3 @@
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_VSNPRINTF=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 5c9e69a..bd81ee6 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -6,5 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index b8b267f..5d27909 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -6,5 +6,4 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 731fc25..caa7336 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -76,7 +76,6 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL=y
-CONFIG_SYS_VSNPRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_LZ4=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index f59bc00..6e8976f 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -7,10 +7,12 @@
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -21,3 +23,6 @@
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index c0d6913..e31aa71 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -7,10 +7,12 @@
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -21,3 +23,6 @@
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index a4f75e6..65c1197 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -19,3 +19,5 @@
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 382db65..c98d4a1 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -19,3 +19,5 @@
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 03f8eff..59fbb2c 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -23,3 +24,5 @@
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 932f0e8..aaba8cb 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -7,6 +7,7 @@
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
@@ -22,3 +23,5 @@
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 2c75bda..a4f0835 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -6,6 +6,7 @@
CONFIG_TARGET_SOCFPGA_SR1500=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
# CONFIG_CMD_IMLS is not set
@@ -17,3 +18,4 @@
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_MMC=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index d59912c..3f08cc1 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -13,3 +13,4 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/ph1_ld4_defconfig b/configs/uniphier_ld4_sld8_defconfig
similarity index 95%
rename from configs/ph1_ld4_defconfig
rename to configs/uniphier_ld4_sld8_defconfig
index 2ddd1eb..ee3cbad 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_UNIPHIER=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARCH_UNIPHIER_PH1_LD4=y
+CONFIG_ARCH_UNIPHIER_PH1_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
diff --git a/configs/ph1_pro4_defconfig b/configs/uniphier_pro4_defconfig
similarity index 100%
rename from configs/ph1_pro4_defconfig
rename to configs/uniphier_pro4_defconfig
diff --git a/configs/ph1_pro5_defconfig b/configs/uniphier_pro5_defconfig
similarity index 100%
rename from configs/ph1_pro5_defconfig
rename to configs/uniphier_pro5_defconfig
diff --git a/configs/ph1_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
similarity index 88%
rename from configs/ph1_ld6b_defconfig
rename to configs/uniphier_pxs2_ld6b_defconfig
index bbcb344..f8cb794 100644
--- a/configs/ph1_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -1,10 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PROXSTREAM2=y
CONFIG_ARCH_UNIPHIER_PH1_LD6B=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld6b-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/ph1_sld3_defconfig b/configs/uniphier_sld3_defconfig
similarity index 100%
rename from configs/ph1_sld3_defconfig
rename to configs/uniphier_sld3_defconfig
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 1cad3a2..1a9097a 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -1,5 +1,8 @@
CONFIG_ARM=y
CONFIG_TARGET_WORK_92105=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index c68efc8..30995ba 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -11,10 +11,10 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 62eb79f..339e399 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -8,5 +8,5 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 5261b73..065f855 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -10,11 +10,11 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 2e525b4..1059689 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -11,10 +11,10 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 6f2ad17..a9dbda5 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -12,12 +12,12 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQ_QSPI=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index d20b3ed..6ff00c6 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -12,5 +12,5 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 4e963a4..75d6c55 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -10,5 +10,5 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index f2d8f14..dd65929 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -12,5 +12,5 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 2e7c68d..73b17e2 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -11,10 +11,10 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 6f0bd0b..577c5a9 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -11,9 +11,12 @@
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_PHYLIB=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_ZYNQ_QSPI=y
diff --git a/disk/part_amiga.c b/disk/part_amiga.c
index 260a3d5..57c1b9d 100644
--- a/disk/part_amiga.c
+++ b/disk/part_amiga.c
@@ -140,8 +140,7 @@
for (i=0; i<limit; i++)
{
- ulong res = dev_desc->block_read(dev_desc->dev, i, 1,
- (ulong *)block_buffer);
+ ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct rigid_disk_block *trdb = (struct rigid_disk_block *)block_buffer;
@@ -183,7 +182,7 @@
for (i = 0; i < limit; i++)
{
- ulong res = dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)block_buffer);
+ ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer);
if (res == 1)
{
struct bootcode_block *boot = (struct bootcode_block *)block_buffer;
@@ -258,7 +257,7 @@
while (block != 0xFFFFFFFF)
{
- ulong res = dev_desc->block_read(dev_desc->dev, block, 1,
+ ulong res = dev_desc->block_read(dev_desc, block, 1,
(ulong *)block_buffer);
if (res == 1)
{
@@ -354,8 +353,7 @@
PRINTF("Trying to load block #0x%X\n", block);
- res = dev_desc->block_read(dev_desc->dev, block, 1,
- (ulong *)block_buffer);
+ res = dev_desc->block_read(dev_desc, block, 1, (ulong *)block_buffer);
if (res == 1)
{
p = (struct partition_block *)block_buffer;
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 89263d3..08872d6 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -26,7 +26,7 @@
/* Convert char[4] in little endian format to the host format integer
*/
-static inline int le32_to_int(unsigned char *le32)
+static inline unsigned int le32_to_int(unsigned char *le32)
{
return ((le32[3] << 24) +
(le32[2] << 16) +
@@ -47,13 +47,14 @@
return p->boot_ind == 0x80;
}
-static void print_one_part(dos_partition_t *p, int ext_part_sector,
+static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector,
int part_num, unsigned int disksig)
{
- int lba_start = ext_part_sector + le32_to_int (p->start4);
- int lba_size = le32_to_int (p->size4);
+ lbaint_t lba_start = ext_part_sector + le32_to_int (p->start4);
+ lbaint_t lba_size = le32_to_int (p->size4);
- printf("%3d\t%-10d\t%-10d\t%08x-%02x\t%02x%s%s\n",
+ printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength
+ "u\t%08x-%02x\t%02x%s%s\n",
part_num, lba_start, lba_size, disksig, part_num, p->sys_ind,
(is_extended(p->sys_ind) ? " Extd" : ""),
(is_bootable(p) ? " Boot" : ""));
@@ -90,7 +91,7 @@
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
- if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1)
+ if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)buffer) != 1)
return -1;
if (test_block_type(buffer) != DOS_MBR)
@@ -102,15 +103,17 @@
/* Print a partition that is relative to its Extended partition table
*/
static void print_partition_extended(block_dev_desc_t *dev_desc,
- int ext_part_sector, int relative,
+ lbaint_t ext_part_sector,
+ lbaint_t relative,
int part_num, unsigned int disksig)
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
dos_partition_t *pt;
int i;
- if (dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) {
- printf ("** Can't read partition table on %d:%d **\n",
+ if (dev_desc->block_read(dev_desc, ext_part_sector, 1,
+ (ulong *)buffer) != 1) {
+ printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->dev, ext_part_sector);
return;
}
@@ -149,7 +152,8 @@
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if (is_extended (pt->sys_ind)) {
- int lba_start = le32_to_int (pt->start4) + relative;
+ lbaint_t lba_start
+ = le32_to_int (pt->start4) + relative;
print_partition_extended(dev_desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
@@ -163,8 +167,9 @@
/* Print a partition that is relative to its Extended partition table
*/
-static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part_sector,
- int relative, int part_num,
+static int get_partition_info_extended (block_dev_desc_t *dev_desc,
+ lbaint_t ext_part_sector,
+ lbaint_t relative, int part_num,
int which_part, disk_partition_t *info,
unsigned int disksig)
{
@@ -173,8 +178,9 @@
int i;
int dos_type;
- if (dev_desc->block_read (dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) {
- printf ("** Can't read partition table on %d:%d **\n",
+ if (dev_desc->block_read(dev_desc, ext_part_sector, 1,
+ (ulong *)buffer) != 1) {
+ printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->dev, ext_part_sector);
return -1;
}
@@ -231,7 +237,7 @@
break;
}
/* sprintf(info->type, "%d, pt->sys_ind); */
- sprintf ((char *)info->type, "U-Boot");
+ strcpy((char *)info->type, "U-Boot");
info->bootable = is_bootable(pt);
#ifdef CONFIG_PARTITION_UUIDS
sprintf(info->uuid, "%08x-%02x", disksig, part_num);
@@ -250,7 +256,8 @@
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if (is_extended (pt->sys_ind)) {
- int lba_start = le32_to_int (pt->start4) + relative;
+ lbaint_t lba_start
+ = le32_to_int (pt->start4) + relative;
return get_partition_info_extended (dev_desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
@@ -266,7 +273,7 @@
info->size = dev_desc->lba;
info->blksz = DOS_PART_DEFAULT_SECTOR;
info->bootable = 0;
- sprintf ((char *)info->type, "U-Boot");
+ strcpy((char *)info->type, "U-Boot");
#ifdef CONFIG_PARTITION_UUIDS
info->uuid[0] = 0;
#endif
diff --git a/disk/part_efi.c b/disk/part_efi.c
index b1e0155..e1b58c5 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -281,7 +281,7 @@
sprintf((char *)info->name, "%s",
print_efiname(&gpt_pte[part - 1]));
- sprintf((char *)info->type, "U-Boot");
+ strcpy((char *)info->type, "U-Boot");
info->bootable = is_bootable(&gpt_pte[part - 1]);
#ifdef CONFIG_PARTITION_UUIDS
uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
@@ -324,7 +324,7 @@
ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
/* Read legacy MBR from block 0 and validate it */
- if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)legacymbr) != 1)
+ if ((dev_desc->block_read(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
|| (is_pmbr_valid(legacymbr) != 1)) {
return -1;
}
@@ -354,7 +354,7 @@
p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1;
/* Write MBR sector to the MMC device */
- if (dev_desc->block_write(dev_desc->dev, 0, 1, p_mbr) != 1) {
+ if (dev_desc->block_write(dev_desc, 0, 1, p_mbr) != 1) {
printf("** Can't write to device %d **\n",
dev_desc->dev);
return -1;
@@ -386,22 +386,22 @@
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
/* Write the First GPT to the block right after the Legacy MBR */
- if (dev_desc->block_write(dev_desc->dev, 1, 1, gpt_h) != 1)
+ if (dev_desc->block_write(dev_desc, 1, 1, gpt_h) != 1)
goto err;
- if (dev_desc->block_write(dev_desc->dev, 2, pte_blk_cnt, gpt_e)
+ if (dev_desc->block_write(dev_desc, 2, pte_blk_cnt, gpt_e)
!= pte_blk_cnt)
goto err;
prepare_backup_gpt_header(gpt_h);
- if (dev_desc->block_write(dev_desc->dev,
+ if (dev_desc->block_write(dev_desc,
(lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+ 1,
pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
- if (dev_desc->block_write(dev_desc->dev,
+ if (dev_desc->block_write(dev_desc,
(lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
gpt_h) != 1)
goto err;
@@ -737,7 +737,7 @@
/* write MBR */
lba = 0; /* MBR is always at 0 */
cnt = 1; /* MBR (1 block) */
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, buf) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, buf) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "MBR", cnt, lba);
return 1;
@@ -746,7 +746,7 @@
/* write Primary GPT */
lba = GPT_PRIMARY_PARTITION_TABLE_LBA;
cnt = 1; /* GPT Header (1 block) */
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Primary GPT Header", cnt, lba);
return 1;
@@ -754,7 +754,7 @@
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Primary GPT Entries", cnt, lba);
return 1;
@@ -765,7 +765,7 @@
/* write Backup GPT */
lba = le64_to_cpu(gpt_h->partition_entry_lba);
cnt = gpt_e_blk_cnt;
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Backup GPT Entries", cnt, lba);
return 1;
@@ -773,7 +773,7 @@
lba = le64_to_cpu(gpt_h->my_lba);
cnt = 1; /* GPT Header (1 block) */
- if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
+ if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) {
printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
__func__, "Backup GPT Header", cnt, lba);
return 1;
@@ -843,8 +843,7 @@
}
/* Read GPT Header from device */
- if (dev_desc->block_read(dev_desc->dev, (lbaint_t)lba, 1, pgpt_head)
- != 1) {
+ if (dev_desc->block_read(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
printf("*** ERROR: Can't read GPT header ***\n");
return 0;
}
@@ -881,6 +880,7 @@
gpt_header * pgpt_head)
{
size_t count = 0, blk_cnt;
+ lbaint_t blk;
gpt_entry *pte = NULL;
if (!dev_desc || !pgpt_head) {
@@ -909,12 +909,10 @@
}
/* Read GPT Entries from device */
+ blk = le64_to_cpu(pgpt_head->partition_entry_lba);
blk_cnt = BLOCK_CNT(count, dev_desc);
- if (dev_desc->block_read (dev_desc->dev,
- (lbaint_t)le64_to_cpu(pgpt_head->partition_entry_lba),
- (lbaint_t) (blk_cnt), pte)
- != blk_cnt) {
-
+ if (dev_desc->block_read(dev_desc, blk, (lbaint_t)blk_cnt, pte)
+ != blk_cnt) {
printf("*** ERROR: Can't read GPT Entries ***\n");
free(pte);
return NULL;
diff --git a/disk/part_iso.c b/disk/part_iso.c
index 2547c70..5f4bb18 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -62,8 +62,8 @@
/* the first sector (sector 0x10) must be a primary volume desc */
blkaddr=PVD_OFFSET;
- if (dev_desc->block_read (dev_desc->dev, PVD_OFFSET, 1, (ulong *) tmpbuf) != 1)
- return (-1);
+ if (dev_desc->block_read(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
+ return -1;
if(ppr->desctype!=0x01) {
if(verb)
printf ("** First descriptor is NOT a primary desc on %d:%d **\n",
@@ -84,8 +84,8 @@
PRINTF(" Lastsect:%08lx\n",lastsect);
for(i=blkaddr;i<lastsect;i++) {
PRINTF("Reading block %d\n", i);
- if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *) tmpbuf) != 1)
- return (-1);
+ if (dev_desc->block_read(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
+ return -1;
if(ppr->desctype==0x00)
break; /* boot entry found */
if(ppr->desctype==0xff) {
@@ -104,7 +104,7 @@
}
bootaddr=le32_to_int(pbr->pointer);
PRINTF(" Boot Entry at: %08lX\n",bootaddr);
- if (dev_desc->block_read (dev_desc->dev, bootaddr, 1, (ulong *) tmpbuf) != 1) {
+ if (dev_desc->block_read(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
if(verb)
printf ("** Can't read Boot Entry at %lX on %d:%d **\n",
bootaddr,dev_desc->dev, part_num);
@@ -137,7 +137,7 @@
/* the validation entry seems to be ok, now search the "partition" */
entry_num=0;
offset=0x20;
- sprintf ((char *)info->type, "U-Boot");
+ strcpy((char *)info->type, "U-Boot");
switch(dev_desc->if_type) {
case IF_TYPE_IDE:
case IF_TYPE_SATA:
diff --git a/disk/part_mac.c b/disk/part_mac.c
index 099e0a0..f3bc8dd 100644
--- a/disk/part_mac.c
+++ b/disk/part_mac.c
@@ -51,7 +51,8 @@
n = 1; /* assuming at least one partition */
for (i=1; i<=n; ++i) {
- if ((dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)mpart) != 1) ||
+ if ((dev_desc->block_read(dev_desc, i, 1,
+ (ulong *)mpart) != 1) ||
(mpart->signature != MAC_PARTITION_MAGIC) ) {
return (-1);
}
@@ -104,7 +105,7 @@
char c;
printf ("%4ld: ", i);
- if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *)mpart) != 1) {
+ if (dev_desc->block_read(dev_desc, i, 1, (ulong *)mpart) != 1) {
printf ("** Can't read Partition Map on %d:%ld **\n",
dev_desc->dev, i);
return;
@@ -150,7 +151,7 @@
*/
static int part_mac_read_ddb (block_dev_desc_t *dev_desc, mac_driver_desc_t *ddb_p)
{
- if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)ddb_p) != 1) {
+ if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)ddb_p) != 1) {
printf ("** Can't read Driver Desriptor Block **\n");
return (-1);
}
@@ -178,7 +179,7 @@
* partition 1 first since this is the only way to
* know how many partitions we have.
*/
- if (dev_desc->block_read (dev_desc->dev, n, 1, (ulong *)pdb_p) != 1) {
+ if (dev_desc->block_read(dev_desc, n, 1, (ulong *)pdb_p) != 1) {
printf ("** Can't read Partition Map on %d:%d **\n",
dev_desc->dev, n);
return (-1);
diff --git a/doc/README.imx6 b/doc/README.imx6
index 437af2f..e26ab71 100644
--- a/doc/README.imx6
+++ b/doc/README.imx6
@@ -84,3 +84,54 @@
Reading bank 4:
Word 0x00000002: 9f027772 00000004
+
+2. Using imx_usb_loader for first install with SPL
+--------------------------------------------------
+
+imx_usb_loader is a very nice tool by BoundaryDevice that
+allow to install U-Boot without a JTAG debugger, using
+the USB boot mode as described in the manual. It is
+a replacement for Freescale's MFGTOOLS.
+
+The sources can be found here:
+
+ https://github.com/boundarydevices/imx_usb_loader.git
+
+Booting in USB mode, the i.MX6 announces itself to the Linux Host as:
+
+Bus 001 Device 111: ID 15a2:0061 Freescale Semiconductor, Inc.
+
+imx_usb_loader is able to download a single file (u-boot.imx)
+to the board. For boards without SPL support, it is enough to
+issue the command:
+
+ sudo ../imx_usb_loader/imx_usb -v u-boot.imx
+
+Getting U-Boot when SPL support is active, it requires
+two downloads. imx_usb_loader downloads the SPL into
+OCRAM and starts it. SPL will check for a valid u-boot.img, and
+because it is not found, it will wait for it using the y-modem
+protocol via the console.
+
+A first install is then possible by combining imx_usb_loader with
+another tool such as kermit.
+
+sudo ../imx_usb_loader/imx_usb -v SPL
+kermit kermit_uboot
+
+and kermit_uboot contains something like this (set line should be adjusted):
+
+set line /dev/ttyUSB1
+set speed 115200
+SET CARRIER-WATCH OFF
+set flow-control none
+set handshake none
+set prefixing all
+set file type bin
+set protocol ymodem
+send u-boot.img
+c
+
+The last "c" command tells kermit (from ckermit package in most distros)
+to switch from command line mode to communication mode, and when the
+script is finished, the U-Boot prompt is shown in the same shell.
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 874441c..9a2ebca 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -71,7 +71,7 @@
To create a suitable image and write it to the board:
- ./firefly-rk3288/tools/mkimage -T rkimage -d \
+ ./firefly-rk3288/tools/mkimage -n rk3288 -T rkimage -d \
./firefly-rk3288/spl/u-boot-spl-dtb.bin out && \
cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | rkflashtool l
@@ -94,7 +94,7 @@
To write an image that boots from an SD card (assumed to be /dev/sdc):
- ./firefly-rk3288/tools/mkimage -T rksd -d \
+ ./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
firefly-rk3288/spl/u-boot-spl-dtb.bin out && \
sudo dd if=out of=/dev/sdc seek=64 && \
sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256
@@ -123,7 +123,7 @@
=>
For evb_rk3036 board:
- ./evb-rk3036/tools/mkimage -T rksd -d evb-rk3036/spl/u-boot-spl.bin out && \
+ ./evb-rk3036/tools/mkimage -n rk3036 -T rksd -d evb-rk3036/spl/u-boot-spl.bin out && \
cat evb-rk3036/u-boot-dtb.bin >> out && \
sudo dd if=out of=/dev/sdc seek=64
@@ -135,9 +135,10 @@
To write an image that boots from SPI flash (e.g. for the Haier Chromebook):
- ./chromebook_jerry/tools/mkimage -T rkspi -d chromebook_jerry/spl/u-boot-spl-dtb.bin out
- dd if=spl.bin of=out.bin bs=128K conv=sync
- cat chromebook_jerry/u-boot-dtb.img out.bin
+ ./chromebook_jerry/tools/mkimage -n rk3288 -T rkspi \
+ -d chromebook_jerry/spl/u-boot-spl-dtb.bin spl.bin && \
+ dd if=spl.bin of=spl-out.bin bs=128K conv=sync && \
+ cat spl-out.bin chromebook_jerry/u-boot-dtb.img >out.bin && \
dd if=out.bin of=out.bin.pad bs=4M conv=sync
This converts the SPL image to the required SPI format by adding the Rockchip
diff --git a/doc/README.uniphier b/doc/README.uniphier
index 57b947b..bce70cf 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -28,34 +28,38 @@
Compile the source
------------------
-PH1-sLD3:
- $ make ph1_sld3_defconfig
+PH1-sLD3 reference board:
+ $ make uniphier_sld3_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-LD4:
- $ make ph1_ld4_defconfig
+PH1-LD4 reference board:
+ $ make uniphier_ld4_sld8_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-Pro4:
- $ make ph1_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+PH1-sLD8 reference board:
+ $ make uniphier_ld4_sld8_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref
-PH1-sLD8:
- $ make ph1_sld8_defconfig
+PH1-Pro4 reference board:
+ $ make uniphier_pro4_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-Pro5:
- $ make ph1_pro5_defconfig
+PH1-Pro5 4KBOX Board:
+ $ make uniphier_pro5_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-ProXstream2:
- $ make pxs2_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ProXstream2 Gentil board:
+ $ make uniphier_pxs2_ld6b_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-proxstream2-gentil
-PH1-LD6b:
- $ make ph1_ld6b_defconfig
+ProXstream2 Vodka board:
+ $ make uniphier_pxs2_ld6b_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
+PH1-LD6b reference board:
+ $ make uniphier_pxs2_ld6b_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld6b-ref
+
You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
to use your favorite compiler.
@@ -115,7 +119,7 @@
SW8 OFF(1)/ON(0) Description
------------------------------------------
- bit 1 ----> CS1_SPLIT
+ bit 1 <---- CS1_SPLIT
bit 2 <---- CASE9_ON
bit 3 <---- CASE10_ON
bit 4 Don't Care Reserve
diff --git a/doc/README.x86 b/doc/README.x86
index 1271e5e..36aaef0 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -295,9 +295,37 @@
If you want to check both consoles, use '-serial stdio'.
Multicore is also supported by QEMU via '-smp n' where n is the number of cores
-to instantiate. Currently the default U-Boot built for QEMU supports 2 cores.
-In order to support more cores, you need add additional cpu nodes in the device
-tree and change CONFIG_MAX_CPUS accordingly.
+to instantiate. Note, the maximum supported CPU number in QEMU is 255.
+
+The fw_cfg interface in QEMU also provides information about kernel data, initrd,
+command-line arguments and more. U-Boot supports directly accessing these informtion
+from fw_cfg interface, this saves the time of loading them from hard disk or
+network again, through emulated devices. To use it , simply providing them in
+QEMU command line:
+
+$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
+ -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
+
+Note: -initrd and -smp are both optional
+
+Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel:
+
+ => qfw
+qfw - QEMU firmware interface
+
+Usage:
+qfw <command>
+ - list : print firmware(s) currently loaded
+ - cpus : print online cpu number
+ - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
+
+=> qfw load
+loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
+
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot'
+can be used to boot the kernel:
+
+=> zboot 02000000 - 04000000 1b1ab50
CPU Microcode
-------------
diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt
index 76ad629..4706d56 100644
--- a/doc/driver-model/serial-howto.txt
+++ b/doc/driver-model/serial-howto.txt
@@ -4,8 +4,6 @@
About 16 of 33 serial drivers have been converted as at September 2015. It
is time for maintainers to start converting over the remaining serial drivers:
- altera_jtag_uart.c
- altera_uart.c
arm_dcc.c
lpc32xx_hsuart.c
mcfuart.c
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 85bac75..ced7085 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -20,7 +20,6 @@
alias bmeng Bin Meng <bmeng.cn@gmail.com>
alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
alias galak Kumar Gala <galak@kernel.crashing.org>
-alias gruss Graeme Russ <graeme.russ@gmail.com>
alias hs Heiko Schocher <hs@denx.de>
alias ijc Ian Campbell <ijc+uboot@hellion.org.uk>
alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
@@ -112,7 +111,7 @@
alias superh uboot, iwamatsu
alias sh superh
-alias x86 uboot, sjg, gruss, bmeng
+alias x86 uboot, sjg, bmeng
# Subsystem aliases
alias dm uboot, sjg
diff --git a/drivers/Makefile b/drivers/Makefile
index c9031f2..00da40b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -14,8 +14,8 @@
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
-obj-$(CONFIG_SYS_MVEBU_DDR_A38X) += ddr/marvell/a38x/
-obj-$(CONFIG_SYS_MVEBU_DDR_AXP) += ddr/marvell/axp/
+obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
+obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/
obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index f161c01..eb8bda9 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -14,6 +14,7 @@
obj-$(CONFIG_MX51_PATA) += mxc_ata.o
obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
obj-$(CONFIG_SATA_DWC) += sata_dwc.o
+obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_IDE_SIL680) += sil680.o
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 5efa821..d29642b 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
@@ -168,9 +169,14 @@
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ struct udevice *dev = probe_ent->dev;
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+# else
pci_dev_t pdev = probe_ent->dev;
- u16 tmp16;
unsigned short vendor;
+# endif
+ u16 tmp16;
#endif
void __iomem *mmio = probe_ent->mmio_base;
u32 tmp, cap_save, cmd;
@@ -193,6 +199,14 @@
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
+ u16 tmp16;
+
+ dm_pci_read_config16(dev, 0x92, &tmp16);
+ dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
+ }
+# else
pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
if (vendor == PCI_VENDOR_ID_INTEL) {
@@ -201,6 +215,7 @@
tmp16 |= 0xf;
pci_write_config_word(pdev, 0x92, tmp16);
}
+# endif
#endif
probe_ent->cap = readl(mmio + HOST_CAP);
probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
@@ -313,9 +328,15 @@
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
+ tmp |= PCI_COMMAND_MASTER;
+ dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
+# else
pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
tmp |= PCI_COMMAND_MASTER;
pci_write_config_word(pdev, PCI_COMMAND, tmp16);
+# endif
#endif
return 0;
}
@@ -324,7 +345,11 @@
static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ struct udevice *dev = probe_ent->dev;
+# else
pci_dev_t pdev = probe_ent->dev;
+# endif
u16 cc;
#endif
void __iomem *mmio = probe_ent->mmio_base;
@@ -350,7 +375,11 @@
#ifdef CONFIG_SCSI_AHCI_PLAT
scc_s = "SATA";
#else
+# ifdef CONFIG_DM_PCI
+ dm_pci_read_config16(dev, 0x0a, &cc);
+# else
pci_read_config_word(pdev, 0x0a, &cc);
+# endif
if (cc == 0x0101)
scc_s = "IDE";
else if (cc == 0x0106)
@@ -395,7 +424,11 @@
}
#ifndef CONFIG_SCSI_AHCI_PLAT
-static int ahci_init_one(pci_dev_t pdev)
+# ifdef CONFIG_DM_PCI
+static int ahci_init_one(struct udevice *dev)
+# else
+static int ahci_init_one(pci_dev_t dev)
+# endif
{
u16 vendor;
int rc;
@@ -407,7 +440,7 @@
}
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
- probe_ent->dev = pdev;
+ probe_ent->dev = dev;
probe_ent->host_flags = ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
@@ -417,18 +450,31 @@
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
- probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5,
+#ifdef CONFIG_DM_PCI
+ probe_ent->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
+ PCI_REGION_MEM);
+
+ /* Take from kernel:
+ * JMicron-specific fixup:
+ * make sure we're in AHCI mode
+ */
+ dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
+ if (vendor == 0x197b)
+ dm_pci_write_config8(dev, 0x41, 0xa1);
+#else
+ probe_ent->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
PCI_REGION_MEM);
- debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
/* Take from kernel:
* JMicron-specific fixup:
* make sure we're in AHCI mode
*/
- pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
+ pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
if (vendor == 0x197b)
- pci_write_config_byte(pdev, 0x41, 0xa1);
+ pci_write_config_byte(dev, 0x41, 0xa1);
+#endif
+ debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
/* initialize adapter */
rc = ahci_host_init(probe_ent);
if (rc)
@@ -915,7 +961,17 @@
u32 linkmap;
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+ int ret;
+
+ ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
+ if (ret)
+ return;
+ ahci_init_one(dev);
+# else
ahci_init_one(busdevfunc);
+# endif
#endif
linkmap = probe_ent->link_port_map;
diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index 52c1602..2c6d424 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -13,7 +13,7 @@
#include <asm/arch/orion5x.h>
#elif defined(CONFIG_KIRKWOOD)
#include <asm/arch/soc.h>
-#elif defined(CONFIG_ARMADA_XP)
+#elif defined(CONFIG_ARCH_MVEBU)
#include <linux/mbus.h>
#endif
@@ -102,7 +102,7 @@
* Initialize SATA memory windows for Armada XP
*/
-#ifdef CONFIG_ARMADA_XP
+#ifdef CONFIG_ARCH_MVEBU
static void mvsata_ide_conf_mbus_windows(void)
{
const struct mbus_dram_target_info *dram;
@@ -174,7 +174,7 @@
int ret = MVSATA_STATUS_TIMEOUT;
int status;
-#ifdef CONFIG_ARMADA_XP
+#ifdef CONFIG_ARCH_MVEBU
mvsata_ide_conf_mbus_windows();
#endif
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index 73f4c4a..170f0fa 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -22,9 +22,11 @@
return NULL;
}
-static unsigned long host_block_read(int dev, unsigned long start,
- lbaint_t blkcnt, void *buffer)
+static unsigned long host_block_read(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer)
{
+ int dev = block_dev->dev;
struct host_block_dev *host_dev = find_host_device(dev);
if (!host_dev)
@@ -42,9 +44,11 @@
return -1;
}
-static unsigned long host_block_write(int dev, unsigned long start,
- lbaint_t blkcnt, const void *buffer)
+static unsigned long host_block_write(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ const void *buffer)
{
+ int dev = block_dev->dev;
struct host_block_dev *host_dev = find_host_device(dev);
if (os_lseek(host_dev->fd,
start * host_dev->blk_dev.blksz,
diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c
index 9e8b067..b14985a 100644
--- a/drivers/block/sata_dwc.c
+++ b/drivers/block/sata_dwc.c
@@ -626,7 +626,7 @@
if (id[162] & 1)
printf("supports DRM functions and may "
"not be fully accessable.\n");
- sprintf(revbuf, "%s", "CFA");
+ strcpy(revbuf, "CFA");
} else {
if (ata_id_has_tpm(id))
printf("supports DRM functions and may "
@@ -653,7 +653,7 @@
ncq_desc[0] = '\0';
if (ata_dev->horkage & ATA_HORKAGE_NONCQ)
- sprintf(ncq_desc, "%s", "NCQ (not used)");
+ strcpy(ncq_desc, "NCQ (not used)");
if (ap.flags & ATA_FLAG_NCQ)
ata_dev->flags |= ATA_DFLAG_NCQ;
diff --git a/drivers/block/sata_mv.c b/drivers/block/sata_mv.c
new file mode 100644
index 0000000..8824934
--- /dev/null
+++ b/drivers/block/sata_mv.c
@@ -0,0 +1,1045 @@
+/*
+ * Copyright (C) Excito Elektronik i Skåne AB, 2010.
+ * Author: Tor Krill <tor@excito.com>
+ *
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This driver supports the SATA controller of some Mavell SoC's.
+ * Here a (most likely incomplete) list of the supported SoC's:
+ * - Kirkwood
+ * - Armada 370
+ * - Armada XP
+ *
+ * This driver implementation is an alternative to the already available
+ * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
+ * But this driver only supports PIO mode and as this new driver also
+ * supports transfer via DMA, its much faster.
+ *
+ * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
+ * by this driver. As they have an AHCI compatible SATA controller
+ * integrated.
+ */
+
+/*
+ * TODO:
+ * Better error recovery
+ * No support for using PRDs (Thus max 64KB transfers)
+ * No NCQ support
+ * No port multiplier support
+ */
+
+#include <common.h>
+#include <fis.h>
+#include <libata.h>
+#include <malloc.h>
+#include <sata.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <linux/mbus.h>
+
+#if defined(CONFIG_KIRKWOOD)
+#include <asm/arch/kirkwood.h>
+#define SATAHC_BASE KW_SATA_BASE
+#else
+#include <asm/arch/soc.h>
+#define SATAHC_BASE MVEBU_AXP_SATA_BASE
+#endif
+
+#define SATA0_BASE (SATAHC_BASE + 0x2000)
+#define SATA1_BASE (SATAHC_BASE + 0x4000)
+
+/* EDMA registers */
+#define EDMA_CFG 0x000
+#define EDMA_CFG_NCQ (1 << 5)
+#define EDMA_CFG_EQUE (1 << 9)
+#define EDMA_TIMER 0x004
+#define EDMA_IECR 0x008
+#define EDMA_IEMR 0x00c
+#define EDMA_RQBA_HI 0x010
+#define EDMA_RQIPR 0x014
+#define EDMA_RQIPR_IPMASK (0x1f << 5)
+#define EDMA_RQIPR_IPSHIFT 5
+#define EDMA_RQOPR 0x018
+#define EDMA_RQOPR_OPMASK (0x1f << 5)
+#define EDMA_RQOPR_OPSHIFT 5
+#define EDMA_RSBA_HI 0x01c
+#define EDMA_RSIPR 0x020
+#define EDMA_RSIPR_IPMASK (0x1f << 3)
+#define EDMA_RSIPR_IPSHIFT 3
+#define EDMA_RSOPR 0x024
+#define EDMA_RSOPR_OPMASK (0x1f << 3)
+#define EDMA_RSOPR_OPSHIFT 3
+#define EDMA_CMD 0x028
+#define EDMA_CMD_ENEDMA (0x01 << 0)
+#define EDMA_CMD_DISEDMA (0x01 << 1)
+#define EDMA_CMD_ATARST (0x01 << 2)
+#define EDMA_CMD_FREEZE (0x01 << 4)
+#define EDMA_TEST_CTL 0x02c
+#define EDMA_STATUS 0x030
+#define EDMA_IORTO 0x034
+#define EDMA_CDTR 0x040
+#define EDMA_HLTCND 0x060
+#define EDMA_NTSR 0x094
+
+/* Basic DMA registers */
+#define BDMA_CMD 0x224
+#define BDMA_STATUS 0x228
+#define BDMA_DTLB 0x22c
+#define BDMA_DTHB 0x230
+#define BDMA_DRL 0x234
+#define BDMA_DRH 0x238
+
+/* SATA Interface registers */
+#define SIR_ICFG 0x050
+#define SIR_CFG_GEN2EN (0x1 << 7)
+#define SIR_PLL_CFG 0x054
+#define SIR_SSTATUS 0x300
+#define SSTATUS_DET_MASK (0x0f << 0)
+#define SIR_SERROR 0x304
+#define SIR_SCONTROL 0x308
+#define SIR_SCONTROL_DETEN (0x01 << 0)
+#define SIR_LTMODE 0x30c
+#define SIR_LTMODE_NELBE (0x01 << 7)
+#define SIR_PHYMODE3 0x310
+#define SIR_PHYMODE4 0x314
+#define SIR_PHYMODE1 0x32c
+#define SIR_PHYMODE2 0x330
+#define SIR_BIST_CTRL 0x334
+#define SIR_BIST_DW1 0x338
+#define SIR_BIST_DW2 0x33c
+#define SIR_SERR_IRQ_MASK 0x340
+#define SIR_SATA_IFCTRL 0x344
+#define SIR_SATA_TESTCTRL 0x348
+#define SIR_SATA_IFSTATUS 0x34c
+#define SIR_VEND_UNIQ 0x35c
+#define SIR_FIS_CFG 0x360
+#define SIR_FIS_IRQ_CAUSE 0x364
+#define SIR_FIS_IRQ_MASK 0x368
+#define SIR_FIS_DWORD0 0x370
+#define SIR_FIS_DWORD1 0x374
+#define SIR_FIS_DWORD2 0x378
+#define SIR_FIS_DWORD3 0x37c
+#define SIR_FIS_DWORD4 0x380
+#define SIR_FIS_DWORD5 0x384
+#define SIR_FIS_DWORD6 0x388
+#define SIR_PHYM9_GEN2 0x398
+#define SIR_PHYM9_GEN1 0x39c
+#define SIR_PHY_CFG 0x3a0
+#define SIR_PHYCTL 0x3a4
+#define SIR_PHYM10 0x3a8
+#define SIR_PHYM12 0x3b0
+
+/* Shadow registers */
+#define PIO_DATA 0x100
+#define PIO_ERR_FEATURES 0x104
+#define PIO_SECTOR_COUNT 0x108
+#define PIO_LBA_LOW 0x10c
+#define PIO_LBA_MID 0x110
+#define PIO_LBA_HI 0x114
+#define PIO_DEVICE 0x118
+#define PIO_CMD_STATUS 0x11c
+#define PIO_STATUS_ERR (0x01 << 0)
+#define PIO_STATUS_DRQ (0x01 << 3)
+#define PIO_STATUS_DF (0x01 << 5)
+#define PIO_STATUS_DRDY (0x01 << 6)
+#define PIO_STATUS_BSY (0x01 << 7)
+#define PIO_CTRL_ALTSTAT 0x120
+
+/* SATAHC arbiter registers */
+#define SATAHC_CFG 0x000
+#define SATAHC_RQOP 0x004
+#define SATAHC_RQIP 0x008
+#define SATAHC_ICT 0x00c
+#define SATAHC_ITT 0x010
+#define SATAHC_ICR 0x014
+#define SATAHC_ICR_PORT0 (0x01 << 0)
+#define SATAHC_ICR_PORT1 (0x01 << 1)
+#define SATAHC_MIC 0x020
+#define SATAHC_MIM 0x024
+#define SATAHC_LED_CFG 0x02c
+
+#define REQUEST_QUEUE_SIZE 32
+#define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
+
+struct crqb {
+ u32 dtb_low; /* DW0 */
+ u32 dtb_high; /* DW1 */
+ u32 control_flags; /* DW2 */
+ u32 drb_count; /* DW3 */
+ u32 ata_cmd_feat; /* DW4 */
+ u32 ata_addr; /* DW5 */
+ u32 ata_addr_exp; /* DW6 */
+ u32 ata_sect_count; /* DW7 */
+};
+
+#define CRQB_ALIGN 0x400
+
+#define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
+#define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
+#define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
+#define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
+#define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
+#define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
+#define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
+#define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
+
+#define CRQB_CMDFEAT_CMDMASK (0xff << 16)
+#define CRQB_CMDFEAT_CMDSHIFT 16
+#define CRQB_CMDFEAT_FEATMASK (0xff << 16)
+#define CRQB_CMDFEAT_FEATSHIFT 24
+
+#define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
+#define CRQB_ADDR_LBA_LOWSHIFT 0
+#define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
+#define CRQB_ADDR_LBA_MIDSHIFT 8
+#define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
+#define CRQB_ADDR_LBA_HIGHSHIFT 16
+#define CRQB_ADDR_DEVICE_MASK (0xff << 24)
+#define CRQB_ADDR_DEVICE_SHIFT 24
+
+#define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
+#define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
+#define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
+#define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
+#define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
+#define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
+#define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
+#define CRQB_ADDR_FEATURE_EXP_SHIFT 24
+
+#define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
+#define CRQB_SECTCOUNT_COUNT_SHIFT 0
+#define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
+#define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
+
+#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
+#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
+
+struct eprd {
+ u32 phyaddr_low;
+ u32 bytecount_eot;
+ u32 phyaddr_hi;
+ u32 reserved;
+};
+
+#define EPRD_PHYADDR_MASK 0xfffffffe
+#define EPRD_BYTECOUNT_MASK 0x0000ffff
+#define EPRD_EOT (0x01 << 31)
+
+struct crpb {
+ u32 id;
+ u32 flags;
+ u32 timestamp;
+};
+
+#define CRPB_ALIGN 0x100
+
+#define READ_CMD 0
+#define WRITE_CMD 1
+
+/*
+ * Since we don't use PRDs yet max transfer size
+ * is 64KB
+ */
+#define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
+
+/* Keep track if hw is initialized or not */
+static u32 hw_init;
+
+struct mv_priv {
+ char name[12];
+ u32 link;
+ u32 regbase;
+ u32 queue_depth;
+ u16 pio;
+ u16 mwdma;
+ u16 udma;
+
+ void *crqb_alloc;
+ struct crqb *request;
+
+ void *crpb_alloc;
+ struct crpb *response;
+};
+
+static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
+{
+ ulong start;
+
+ start = get_timer(0);
+ do {
+ if ((in_le32(addr) & mask) == val)
+ return 0;
+ } while (get_timer(start) < timeout_msec);
+
+ return -ETIMEDOUT;
+}
+
+/* Cut from sata_mv in linux kernel */
+static int mv_stop_edma_engine(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ int i;
+
+ /* Disable eDMA. The disable bit auto clears. */
+ out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
+
+ /* Wait for the chip to confirm eDMA is off. */
+ for (i = 10000; i > 0; i--) {
+ u32 reg = in_le32(priv->regbase + EDMA_CMD);
+ if (!(reg & EDMA_CMD_ENEDMA)) {
+ debug("EDMA stop on port %d succesful\n", port);
+ return 0;
+ }
+ udelay(10);
+ }
+ debug("EDMA stop on port %d failed\n", port);
+ return -1;
+}
+
+static int mv_start_edma_engine(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ /* Check preconditions */
+ tmp = in_le32(priv->regbase + SIR_SSTATUS);
+ if ((tmp & SSTATUS_DET_MASK) != 0x03) {
+ printf("Device error on port: %d\n", port);
+ return -1;
+ }
+
+ tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
+ if (tmp & (ATA_BUSY | ATA_DRQ)) {
+ printf("Device not ready on port: %d\n", port);
+ return -1;
+ }
+
+ /* Clear interrupt cause */
+ out_le32(priv->regbase + EDMA_IECR, 0x0);
+
+ tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
+ tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
+ out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
+
+ /* Configure edma operation */
+ tmp = in_le32(priv->regbase + EDMA_CFG);
+ tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
+ tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
+ out_le32(priv->regbase + EDMA_CFG, tmp);
+
+ out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
+
+ /* Configure fis, set all to no-wait for now */
+ out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
+
+ /* Setup request queue */
+ out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RQIPR, priv->request);
+ out_le32(priv->regbase + EDMA_RQOPR, 0x0);
+
+ /* Setup response queue */
+ out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RSOPR, priv->response);
+ out_le32(priv->regbase + EDMA_RSIPR, 0x0);
+
+ /* Start edma */
+ out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
+
+ return 0;
+}
+
+static int mv_reset_channel(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ /* Make sure edma is stopped */
+ mv_stop_edma_engine(port);
+
+ out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
+ udelay(25); /* allow reset propagation */
+ out_le32(priv->regbase + EDMA_CMD, 0);
+ mdelay(10);
+
+ return 0;
+}
+
+static void mv_reset_port(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ mv_reset_channel(port);
+
+ out_le32(priv->regbase + EDMA_CMD, 0x0);
+ out_le32(priv->regbase + EDMA_CFG, 0x101f);
+ out_le32(priv->regbase + EDMA_IECR, 0x0);
+ out_le32(priv->regbase + EDMA_IEMR, 0x0);
+ out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RQIPR, 0x0);
+ out_le32(priv->regbase + EDMA_RQOPR, 0x0);
+ out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
+ out_le32(priv->regbase + EDMA_RSIPR, 0x0);
+ out_le32(priv->regbase + EDMA_RSOPR, 0x0);
+ out_le32(priv->regbase + EDMA_IORTO, 0xfa);
+}
+
+static void mv_reset_one_hc(void)
+{
+ out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
+ out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
+ out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
+}
+
+static int probe_port(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ int tries, tries2, set15 = 0;
+ u32 tmp;
+
+ debug("Probe port: %d\n", port);
+
+ for (tries = 0; tries < 2; tries++) {
+ /* Clear SError */
+ out_le32(priv->regbase + SIR_SERROR, 0x0);
+
+ /* trigger com-init */
+ tmp = in_le32(priv->regbase + SIR_SCONTROL);
+ tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
+ out_le32(priv->regbase + SIR_SCONTROL, tmp);
+
+ mdelay(1);
+
+ tmp = in_le32(priv->regbase + SIR_SCONTROL);
+ tries2 = 5;
+ do {
+ tmp = (tmp & 0x0f0) | 0x300;
+ out_le32(priv->regbase + SIR_SCONTROL, tmp);
+ mdelay(10);
+ tmp = in_le32(priv->regbase + SIR_SCONTROL);
+ } while ((tmp & 0xf0f) != 0x300 && tries2--);
+
+ mdelay(10);
+
+ for (tries2 = 0; tries2 < 200; tries2++) {
+ tmp = in_le32(priv->regbase + SIR_SSTATUS);
+ if ((tmp & SSTATUS_DET_MASK) == 0x03) {
+ debug("Found device on port\n");
+ return 0;
+ }
+ mdelay(1);
+ }
+
+ if ((tmp & SSTATUS_DET_MASK) == 0) {
+ debug("No device attached on port %d\n", port);
+ return -ENODEV;
+ }
+
+ if (!set15) {
+ /* Try on 1.5Gb/S */
+ debug("Try 1.5Gb link\n");
+ set15 = 1;
+ out_le32(priv->regbase + SIR_SCONTROL, 0x304);
+
+ tmp = in_le32(priv->regbase + SIR_ICFG);
+ tmp &= ~SIR_CFG_GEN2EN;
+ out_le32(priv->regbase + SIR_ICFG, tmp);
+
+ mv_reset_channel(port);
+ }
+ }
+
+ debug("Failed to probe port\n");
+ return -1;
+}
+
+/* Get request queue in pointer */
+static int get_reqip(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
+ tmp = tmp >> EDMA_RQIPR_IPSHIFT;
+
+ return tmp;
+}
+
+static void set_reqip(int port, int reqin)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
+ tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
+ out_le32(priv->regbase + EDMA_RQIPR, tmp);
+}
+
+/* Get next available slot, ignoring possible overwrite */
+static int get_next_reqip(int port)
+{
+ int slot = get_reqip(port);
+ slot = (slot + 1) % REQUEST_QUEUE_SIZE;
+ return slot;
+}
+
+/* Get response queue in pointer */
+static int get_rspip(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
+ tmp = tmp >> EDMA_RSIPR_IPSHIFT;
+
+ return tmp;
+}
+
+/* Get response queue out pointer */
+static int get_rspop(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
+ tmp = tmp >> EDMA_RSOPR_OPSHIFT;
+ return tmp;
+}
+
+/* Get next response queue pointer */
+static int get_next_rspop(int port)
+{
+ return (get_rspop(port) + 1) % RESPONSE_QUEUE_SIZE;
+}
+
+/* Set response queue pointer */
+static void set_rspop(int port, int reqin)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ u32 tmp;
+
+ tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
+ tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
+
+ out_le32(priv->regbase + EDMA_RSOPR, tmp);
+}
+
+static int wait_dma_completion(int port, int index, u32 timeout_msec)
+{
+ u32 tmp, res;
+
+ tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
+ res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
+ tmp, timeout_msec);
+ if (res)
+ printf("Failed to wait for completion on port %d\n", port);
+
+ return res;
+}
+
+static void process_responses(int port)
+{
+#ifdef DEBUG
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+#endif
+ u32 tmp;
+ u32 outind = get_rspop(port);
+
+ /* Ack interrupts */
+ tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
+ if (port == 0)
+ tmp &= ~(BIT(0) | BIT(8));
+ else
+ tmp &= ~(BIT(1) | BIT(9));
+ tmp &= ~(BIT(4));
+ out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
+
+ while (get_rspip(port) != outind) {
+#ifdef DEBUG
+ debug("Response index %d flags %08x on port %d\n", outind,
+ priv->response[outind].flags, port);
+#endif
+ outind = get_next_rspop(port);
+ set_rspop(port, outind);
+ }
+}
+
+static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
+ u8 *buffer, u32 len, u32 iswrite)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ struct crqb *req;
+ int slot;
+
+ if (len >= 64 * 1024) {
+ printf("We only support <64K transfers for now\n");
+ return -1;
+ }
+
+ /* Initialize request */
+ slot = get_reqip(port);
+ memset(&priv->request[slot], 0, sizeof(struct crqb));
+ req = &priv->request[slot];
+
+ req->dtb_low = (u32)buffer;
+
+ /* Dont use PRDs */
+ req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
+ req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
+ req->control_flags |=
+ ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
+ & CRQB_CNTRLFLAGS_PMPORTMASK);
+
+ req->drb_count = len;
+
+ req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
+ CRQB_CMDFEAT_CMDMASK;
+ req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
+ CRQB_CMDFEAT_FEATMASK;
+
+ req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
+ CRQB_ADDR_LBA_LOWMASK;
+ req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
+ CRQB_ADDR_LBA_MIDMASK;
+ req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
+ CRQB_ADDR_LBA_HIGHMASK;
+ req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
+ CRQB_ADDR_DEVICE_MASK;
+
+ req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
+ CRQB_ADDR_LBA_LOW_EXP_MASK;
+ req->ata_addr_exp |=
+ (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
+ CRQB_ADDR_LBA_MID_EXP_MASK;
+ req->ata_addr_exp |=
+ (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
+ CRQB_ADDR_LBA_HIGH_EXP_MASK;
+ req->ata_addr_exp |=
+ (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
+ CRQB_ADDR_FEATURE_EXP_MASK;
+
+ req->ata_sect_count =
+ (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
+ CRQB_SECTCOUNT_COUNT_MASK;
+ req->ata_sect_count |=
+ (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
+ CRQB_SECTCOUNT_COUNT_EXP_MASK;
+
+ /* Flush data */
+ flush_dcache_range((u32)req, (u32)req + sizeof(*req));
+
+ /* Trigger operation */
+ slot = get_next_reqip(port);
+ set_reqip(port, slot);
+
+ /* Wait for completion */
+ if (wait_dma_completion(port, slot, 10000)) {
+ printf("ATA operation timed out\n");
+ return -1;
+ }
+
+ process_responses(port);
+
+ /* Invalidate data on read */
+ if (buffer && len)
+ invalidate_dcache_range((u32)buffer, (u32)buffer + len);
+
+ return len;
+}
+
+static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt,
+ u8 *buffer, int is_write)
+{
+ struct sata_fis_h2d cfis;
+ u32 res;
+ u64 block;
+
+ block = (u64)start;
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
+
+ cfis.lba_high_exp = (block >> 40) & 0xff;
+ cfis.lba_mid_exp = (block >> 32) & 0xff;
+ cfis.lba_low_exp = (block >> 24) & 0xff;
+ cfis.lba_high = (block >> 16) & 0xff;
+ cfis.lba_mid = (block >> 8) & 0xff;
+ cfis.lba_low = block & 0xff;
+ cfis.device = ATA_LBA;
+ cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
+ cfis.sector_count = blkcnt & 0xff;
+
+ res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
+ is_write);
+
+ return res >= 0 ? blkcnt : res;
+}
+
+static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer,
+ int is_write)
+{
+ struct sata_fis_h2d cfis;
+ lbaint_t block;
+ u32 res;
+
+ block = start;
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
+ cfis.device = ATA_LBA;
+
+ cfis.device |= (block >> 24) & 0xf;
+ cfis.lba_high = (block >> 16) & 0xff;
+ cfis.lba_mid = (block >> 8) & 0xff;
+ cfis.lba_low = block & 0xff;
+ cfis.sector_count = (u8)(blkcnt & 0xff);
+
+ res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
+ is_write);
+
+ return res >= 0 ? blkcnt : res;
+}
+
+static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer, int is_write)
+{
+ lbaint_t start, blks;
+ u8 *addr;
+ int max_blks;
+
+ debug("%s: %ld %ld\n", __func__, blknr, blkcnt);
+
+ start = blknr;
+ blks = blkcnt;
+ addr = (u8 *)buffer;
+
+ max_blks = MV_ATA_MAX_SECTORS;
+ do {
+ if (blks > max_blks) {
+ if (sata_dev_desc[dev].lba48) {
+ mv_sata_rw_cmd_ext(dev, start, max_blks, addr,
+ is_write);
+ } else {
+ mv_sata_rw_cmd(dev, start, max_blks, addr,
+ is_write);
+ }
+ start += max_blks;
+ blks -= max_blks;
+ addr += ATA_SECT_SIZE * max_blks;
+ } else {
+ if (sata_dev_desc[dev].lba48) {
+ mv_sata_rw_cmd_ext(dev, start, blks, addr,
+ is_write);
+ } else {
+ mv_sata_rw_cmd(dev, start, blks, addr,
+ is_write);
+ }
+ start += blks;
+ blks = 0;
+ addr += ATA_SECT_SIZE * blks;
+ }
+ } while (blks != 0);
+
+ return blkcnt;
+}
+
+static int mv_ata_exec_ata_cmd_nondma(int port,
+ struct sata_fis_h2d *cfis, u8 *buffer,
+ u32 len, u32 iswrite)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ int i;
+ u16 *tp;
+
+ debug("%s\n", __func__);
+
+ out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
+ out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
+ out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
+ out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
+ out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
+ out_le32(priv->regbase + PIO_DEVICE, cfis->device);
+ out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
+
+ if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
+ ATA_BUSY, 0x0, 10000)) {
+ debug("Failed to wait for completion\n");
+ return -1;
+ }
+
+ if (len > 0) {
+ tp = (u16 *)buffer;
+ for (i = 0; i < len / 2; i++) {
+ if (iswrite)
+ out_le16(priv->regbase + PIO_DATA, *tp++);
+ else
+ *tp++ = in_le16(priv->regbase + PIO_DATA);
+ }
+ }
+
+ return len;
+}
+
+static int mv_sata_identify(int port, u16 *id)
+{
+ struct sata_fis_h2d h2d;
+
+ memset(&h2d, 0, sizeof(struct sata_fis_h2d));
+
+ h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ h2d.command = ATA_CMD_ID_ATA;
+
+ /* Give device time to get operational */
+ mdelay(10);
+
+ return mv_ata_exec_ata_cmd_nondma(port, &h2d, (u8 *)id,
+ ATA_ID_WORDS * 2, READ_CMD);
+}
+
+static void mv_sata_xfer_mode(int port, u16 *id)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ priv->pio = id[ATA_ID_PIO_MODES];
+ priv->mwdma = id[ATA_ID_MWDMA_MODES];
+ priv->udma = id[ATA_ID_UDMA_MODES];
+ debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
+ priv->udma);
+}
+
+static void mv_sata_set_features(int port)
+{
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+ struct sata_fis_h2d cfis;
+ u8 udma_cap;
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = ATA_CMD_SET_FEATURES;
+ cfis.features = SETFEATURES_XFER;
+
+ /* First check the device capablity */
+ udma_cap = (u8) (priv->udma & 0xff);
+
+ if (udma_cap == ATA_UDMA6)
+ cfis.sector_count = XFER_UDMA_6;
+ if (udma_cap == ATA_UDMA5)
+ cfis.sector_count = XFER_UDMA_5;
+ if (udma_cap == ATA_UDMA4)
+ cfis.sector_count = XFER_UDMA_4;
+ if (udma_cap == ATA_UDMA3)
+ cfis.sector_count = XFER_UDMA_3;
+
+ mv_ata_exec_ata_cmd_nondma(port, &cfis, NULL, 0, READ_CMD);
+}
+
+int mv_sata_spin_down(int dev)
+{
+ struct sata_fis_h2d cfis;
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
+
+ if (priv->link == 0) {
+ debug("No device on port: %d\n", dev);
+ return 1;
+ }
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = ATA_CMD_STANDBY;
+
+ return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
+}
+
+int mv_sata_spin_up(int dev)
+{
+ struct sata_fis_h2d cfis;
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
+
+ if (priv->link == 0) {
+ debug("No device on port: %d\n", dev);
+ return 1;
+ }
+
+ memset(&cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis.command = ATA_CMD_IDLE;
+
+ return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
+}
+
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
+{
+ return ata_low_level_rw(dev, blknr, blkcnt, buffer, READ_CMD);
+}
+
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
+{
+ return ata_low_level_rw(dev, blknr, blkcnt, (void *)buffer, WRITE_CMD);
+}
+
+/*
+ * Initialize SATA memory windows
+ */
+static void mvsata_ide_conf_mbus_windows(void)
+{
+ const struct mbus_dram_target_info *dram;
+ int i;
+
+ dram = mvebu_mbus_dram_info();
+
+ /* Disable windows, Set Size/Base to 0 */
+ for (i = 0; i < 4; i++) {
+ writel(0, MVSATA_WIN_CONTROL(i));
+ writel(0, MVSATA_WIN_BASE(i));
+ }
+
+ for (i = 0; i < dram->num_cs; i++) {
+ const struct mbus_dram_window *cs = dram->cs + i;
+ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1,
+ MVSATA_WIN_CONTROL(i));
+ writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
+ }
+}
+
+int init_sata(int dev)
+{
+ struct mv_priv *priv;
+
+ debug("Initialize sata dev: %d\n", dev);
+
+ if (dev < 0 || dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
+ printf("Invalid sata device %d\n", dev);
+ return -1;
+ }
+
+ priv = (struct mv_priv *)malloc(sizeof(struct mv_priv));
+ if (!priv) {
+ printf("Failed to allocate memory for private sata data\n");
+ return -ENOMEM;
+ }
+
+ memset((void *)priv, 0, sizeof(struct mv_priv));
+
+ /* Allocate and align request buffer */
+ priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
+ CRQB_ALIGN);
+ if (!priv->crqb_alloc) {
+ printf("Unable to allocate memory for request queue\n");
+ return -ENOMEM;
+ }
+ memset(priv->crqb_alloc, 0,
+ sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
+ priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
+ ~(CRQB_ALIGN - 1));
+
+ /* Allocate and align response buffer */
+ priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
+ CRPB_ALIGN);
+ if (!priv->crpb_alloc) {
+ printf("Unable to allocate memory for response queue\n");
+ return -ENOMEM;
+ }
+ memset(priv->crpb_alloc, 0,
+ sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
+ priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
+ ~(CRPB_ALIGN - 1));
+
+ sata_dev_desc[dev].priv = (void *)priv;
+
+ sprintf(priv->name, "SATA%d", dev);
+
+ priv->regbase = dev == 0 ? SATA0_BASE : SATA1_BASE;
+
+ if (!hw_init) {
+ debug("Initialize sata hw\n");
+ hw_init = 1;
+ mv_reset_one_hc();
+ mvsata_ide_conf_mbus_windows();
+ }
+
+ mv_reset_port(dev);
+
+ if (probe_port(dev)) {
+ priv->link = 0;
+ return -ENODEV;
+ }
+ priv->link = 1;
+
+ return 0;
+}
+
+int reset_sata(int dev)
+{
+ return 0;
+}
+
+int scan_sata(int port)
+{
+ unsigned char serial[ATA_ID_SERNO_LEN + 1];
+ unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
+ unsigned char product[ATA_ID_PROD_LEN + 1];
+ u64 n_sectors;
+ u16 *id;
+ struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
+
+ if (!priv->link)
+ return -ENODEV;
+
+ id = (u16 *)malloc(ATA_ID_WORDS * 2);
+ if (!id) {
+ printf("Failed to malloc id data\n");
+ return -ENOMEM;
+ }
+
+ mv_sata_identify(port, id);
+ ata_swap_buf_le16(id, ATA_ID_WORDS);
+#ifdef DEBUG
+ ata_dump_id(id);
+#endif
+
+ /* Serial number */
+ ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
+ memcpy(sata_dev_desc[port].product, serial, sizeof(serial));
+
+ /* Firmware version */
+ ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
+ memcpy(sata_dev_desc[port].revision, firmware, sizeof(firmware));
+
+ /* Product model */
+ ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
+ memcpy(sata_dev_desc[port].vendor, product, sizeof(product));
+
+ /* Total sectors */
+ n_sectors = ata_id_n_sectors(id);
+ sata_dev_desc[port].lba = n_sectors;
+
+ /* Check if support LBA48 */
+ if (ata_id_has_lba48(id)) {
+ sata_dev_desc[port].lba48 = 1;
+ debug("Device support LBA48\n");
+ }
+
+ /* Get the NCQ queue depth from device */
+ priv->queue_depth = ata_id_queue_depth(id);
+
+ /* Get the xfer mode from device */
+ mv_sata_xfer_mode(port, id);
+
+ /* Set the xfer mode to highest speed */
+ mv_sata_set_features(port);
+
+ /* Start up */
+ mv_start_edma_engine(port);
+
+ return 0;
+}
diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index fdf75b5..b974e80 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -69,8 +69,9 @@
return in16(base + off);
}
-static unsigned long systemace_read(int dev, unsigned long start,
- lbaint_t blkcnt, void *buffer);
+static unsigned long systemace_read(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer);
static block_dev_desc_t systemace_dev = { 0 };
@@ -136,8 +137,9 @@
* the dev_desc) to read blocks of data. The return value is the
* number of blocks read. A zero return indicates an error.
*/
-static unsigned long systemace_read(int dev, unsigned long start,
- lbaint_t blkcnt, void *buffer)
+static unsigned long systemace_read(block_dev_desc_t *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer)
{
int retry;
unsigned blk_countdown;
diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c
index e0343f7..d5ce450 100644
--- a/drivers/bootcount/bootcount.c
+++ b/drivers/bootcount/bootcount.c
@@ -31,16 +31,14 @@
#if defined(CONFIG_MPC8260)
#include <asm/cpm_8260.h>
-
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR)
#endif /* defined(CONFIG_MPC8260) */
#if defined(CONFIG_QE)
#include <linux/immap_qe.h>
-
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \
QE_MURAM_SIZE - 2 * sizeof(u32))
-#endif /* defined(CONFIG_MPC8360) */
+#endif /* defined(CONFIG_QE) */
#if defined(CONFIG_4xx)
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_OCM_DATA_ADDR + \
@@ -60,7 +58,7 @@
#else
raw_bootcount_store(reg, a);
raw_bootcount_store(reg + 4, BOOTCOUNT_MAGIC);
-#endif
+#endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD */
}
__weak ulong bootcount_load(void)
@@ -79,6 +77,6 @@
return 0;
else
return raw_bootcount_load(reg);
-#endif
+#endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) */
}
-#endif
+#endif /* defined(CONFIG_SYS_BOOTCOUNT_ADDR) */
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index f332480..c5c9d2a 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -60,6 +60,15 @@
help
Most boards will have a '/aliases' node containing the path to
numbered devices (e.g. serial0 = &serial0). This feature can be
+ disabled if it is not required.
+
+config SPL_DM_SEQ_ALIAS
+ bool "Support numbered aliases in device tree in SPL"
+ depends on DM
+ default n
+ help
+ Most boards will have a '/aliases' node containing the path to
+ numbered devices (e.g. serial0 = &serial0). This feature can be
disabled if it is not required, to save code space in SPL.
config REGMAP
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 758f390..818d03f 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -64,7 +64,7 @@
dev->seq = -1;
dev->req_seq = -1;
- if (CONFIG_IS_ENABLED(OF_CONTROL) && IS_ENABLED(CONFIG_DM_SEQ_ALIAS)) {
+ if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS)) {
/*
* Some devices, such as a SPI bus, I2C bus and serial ports
* are numbered using aliases.
@@ -581,38 +581,65 @@
return dev->uclass->uc_drv->name;
}
-fdt_addr_t dev_get_addr(struct udevice *dev)
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
fdt_addr_t addr;
if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
const fdt32_t *reg;
+ int len = 0;
+ int na, ns;
+
+ na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (na < 1) {
+ debug("bad #address-cells\n");
+ return FDT_ADDR_T_NONE;
+ }
+
+ ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (ns < 0) {
+ debug("bad #size-cells\n");
+ return FDT_ADDR_T_NONE;
+ }
- reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL);
- if (!reg)
+ reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
+ if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) {
+ debug("Req index out of range\n");
return FDT_ADDR_T_NONE;
+ }
+
+ reg += index * (na + ns);
/*
* Use the full-fledged translate function for complex
* bus setups.
*/
- return fdt_translate_address((void *)gd->fdt_blob,
+ addr = fdt_translate_address((void *)gd->fdt_blob,
dev->of_offset, reg);
+ } else {
+ /*
+ * Use the "simple" translate function for less complex
+ * bus setups.
+ */
+ addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+ dev->parent->of_offset,
+ dev->of_offset, "reg",
+ index, NULL);
+ if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
+ if (device_get_uclass_id(dev->parent) ==
+ UCLASS_SIMPLE_BUS)
+ addr = simple_bus_translate(dev->parent, addr);
+ }
}
/*
- * Use the "simple" translate function for less complex
- * bus setups.
+ * Some platforms need a special address translation. Those
+ * platforms (e.g. mvebu in SPL) can configure a translation
+ * offset in the DM by calling dm_set_translation_offset() that
+ * will get added to all addresses returned by dev_get_addr().
*/
- addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- dev->parent->of_offset,
- dev->of_offset, "reg",
- 0, NULL);
- if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
- if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
- addr = simple_bus_translate(dev->parent, addr);
- }
+ addr += dm_get_translation_offset();
return addr;
#else
@@ -620,6 +647,11 @@
#endif
}
+fdt_addr_t dev_get_addr(struct udevice *dev)
+{
+ return dev_get_addr_index(dev, 0);
+}
+
bool device_has_children(struct udevice *dev)
{
return !list_empty(&dev->child_head);
diff --git a/drivers/core/root.c b/drivers/core/root.c
index e7b1f24..13c2713 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -23,6 +23,10 @@
DECLARE_GLOBAL_DATA_PTR;
+struct root_priv {
+ fdt_addr_t translation_offset; /* optional translation offset */
+};
+
static const struct driver_info root_info = {
.name = "root_driver",
};
@@ -37,6 +41,22 @@
return gd->dm_root;
}
+fdt_addr_t dm_get_translation_offset(void)
+{
+ struct udevice *root = dm_root();
+ struct root_priv *priv = dev_get_priv(root);
+
+ return priv->translation_offset;
+}
+
+void dm_set_translation_offset(fdt_addr_t offs)
+{
+ struct udevice *root = dm_root();
+ struct root_priv *priv = dev_get_priv(root);
+
+ priv->translation_offset = offs;
+}
+
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
void fix_drivers(void)
{
@@ -228,6 +248,7 @@
U_BOOT_DRIVER(root_driver) = {
.name = "root_driver",
.id = UCLASS_ROOT,
+ .priv_auto_alloc_size = sizeof(struct root_priv),
};
/* This is the root uclass */
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 1ed2883..2996942 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -218,6 +218,7 @@
readl(&sdr_ctrl->protport_default));
for (rules = 0; rules < 20; rules++) {
+ rule.rule = rules;
sdram_get_rule(&rule);
debug("Rule %d, rules ...\n", rules);
debug(" sdram start %x\n", rule.sdram_start);
diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c
index 7f1c3af..00cdc22 100644
--- a/drivers/ddr/fsl/ddr1_dimm_params.c
+++ b/drivers/ddr/fsl/ddr1_dimm_params.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c
index 49cc1a0..59baf6b 100644
--- a/drivers/ddr/fsl/ddr2_dimm_params.c
+++ b/drivers/ddr/fsl/ddr2_dimm_params.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c
index 6917715..9944dbb 100644
--- a/drivers/ddr/fsl/ddr3_dimm_params.c
+++ b/drivers/ddr/fsl/ddr3_dimm_params.c
@@ -6,9 +6,7 @@
* from ddr3 spd, please refer to the spec
* JEDEC standard No.21-C 4_01_02_11R18.pdf
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index b12eeb9..47ad4e5 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index c686632..139a3a7 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 8dd4a91..c27288d 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
index 988b4a4..898b0cd 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 6752d4d..653b7f0 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c
index 4551ed8..a65eb31 100644
--- a/drivers/ddr/fsl/mpc86xx_ddr.c
+++ b/drivers/ddr/fsl/mpc86xx_ddr.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 1a49b28..9977779 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c
index 1d72bc5..12b5b04 100644
--- a/drivers/ddr/marvell/a38x/ddr3_debug.c
+++ b/drivers/ddr/marvell/a38x/ddr3_debug.c
@@ -165,21 +165,6 @@
}
/*
- * Read training result table
- */
-int hws_ddr3_tip_read_training_result(
- u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
-{
- dev_num = dev_num;
-
- if (result == NULL)
- return MV_BAD_PARAM;
- memcpy(result, training_result, sizeof(result));
-
- return MV_OK;
-}
-
-/*
* Get training result info pointer
*/
enum hws_result *ddr3_tip_get_result_ptr(u32 stage)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
index 76a1b6a0..ed92873 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
@@ -171,8 +171,6 @@
struct hws_topology_map *topology);
int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
-int hws_ddr3_tip_read_training_result(u32 dev_num,
- enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h
index d9e33f7..75d315a 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp.h
@@ -33,7 +33,10 @@
#define SAR1_CPU_CORE_MASK 0x00000018
#define SAR1_CPU_CORE_OFFSET 3
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
#define ECC_SUPPORT
+#endif
#define NEW_FABRIC_TWSI_ADDR 0x4E
#ifdef CONFIG_DB_784MP_GP
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E
diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h
index a672044..8549fe8 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp_config.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h
@@ -44,9 +44,14 @@
* DDR3_TRAINING_DEBUG - Debug prints of internal code
*/
#define DDR_TARGET_FABRIC 5
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
#define DRAM_ECC 1
+#else
+#define DRAM_ECC 0
+#endif
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
#define BUS_WIDTH 32
#else
#define BUS_WIDTH 64
diff --git a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h
index 2c0e9075..71794ad 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h
@@ -8,9 +8,9 @@
#define __AXP_MC_STATIC_H
MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
@@ -66,9 +66,9 @@
};
MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630b800}, /*Dunit Control Low Register */
@@ -124,9 +124,9 @@
};
MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
-#else /* MV_DDR_64BIT */
+#else /* CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630B840}, /*Dunit Control Low Register */
@@ -176,9 +176,9 @@
};
MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
#endif
{0x00001404, 0x3630B040}, /*Dunit Control Low Register */
@@ -233,9 +233,9 @@
};
MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
-#ifdef MV_DDR_32BIT
+#ifdef CONFIG_DDR_32BIT
{0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */
-#else /*MV_DDR_64BIT */
+#else /*CONFIG_DDR_64BIT */
{0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */
/*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */
#endif
diff --git a/drivers/ddr/marvell/axp/ddr3_write_leveling.c b/drivers/ddr/marvell/axp/ddr3_write_leveling.c
index df3a3df..da384f3 100644
--- a/drivers/ddr/marvell/axp/ddr3_write_leveling.c
+++ b/drivers/ddr/marvell/axp/ddr3_write_leveling.c
@@ -22,6 +22,8 @@
DEBUG_WL_FULL_S(s); DEBUG_WL_FULL_D(d, l); DEBUG_WL_FULL_S("\n")
#ifdef MV_DEBUG_WL
+#define DEBUG_WL_S(s) puts(s)
+#define DEBUG_WL_D(d, l) printf("%x", d)
#define DEBUG_RL_S(s) \
debug_cond(ddr3_get_log_level() >= MV_LOG_LEVEL_2, "%s", s)
#define DEBUG_RL_D(d, l) \
@@ -1229,8 +1231,6 @@
DEBUG_WL_FULL_D((u32) phase, 1);
DEBUG_WL_FULL_S(", Delay = ");
DEBUG_WL_FULL_D((u32) delay, 1);
- DEBUG_WL_FULL_S(", Counter = ");
- DEBUG_WL_FULL_D((u32) i, 1);
DEBUG_WL_FULL_S("\n");
/* Drive DQS high for one cycle - All data PUPs */
diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c
index 5a9fb4a..395d472 100644
--- a/drivers/dfu/dfu_mmc.c
+++ b/drivers/dfu/dfu_mmc.c
@@ -20,23 +20,6 @@
static long dfu_file_buf_len;
static long dfu_file_buf_filled;
-static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part)
-{
- int ret;
-
- if (part == mmc->part_num)
- return 0;
-
- ret = mmc_switch_part(dfu->data.mmc.dev_num, part);
- if (ret) {
- error("Cannot switch to partition %d\n", part);
- return ret;
- }
- mmc->part_num = part;
-
- return 0;
-}
-
static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
u64 offset, void *buf, long *len)
{
@@ -66,8 +49,9 @@
}
if (dfu->data.mmc.hw_partition >= 0) {
- part_num_bkp = mmc->part_num;
- ret = mmc_access_part(dfu, mmc, dfu->data.mmc.hw_partition);
+ part_num_bkp = mmc->block_dev.hwpart;
+ ret = mmc_select_hwpart(dfu->data.mmc.dev_num,
+ dfu->data.mmc.hw_partition);
if (ret)
return ret;
}
@@ -77,11 +61,11 @@
dfu->data.mmc.dev_num, blk_start, blk_count, buf);
switch (op) {
case DFU_OP_READ:
- n = mmc->block_dev.block_read(dfu->data.mmc.dev_num, blk_start,
+ n = mmc->block_dev.block_read(&mmc->block_dev, blk_start,
blk_count, buf);
break;
case DFU_OP_WRITE:
- n = mmc->block_dev.block_write(dfu->data.mmc.dev_num, blk_start,
+ n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
blk_count, buf);
break;
default:
@@ -91,12 +75,12 @@
if (n != blk_count) {
error("MMC operation failed");
if (dfu->data.mmc.hw_partition >= 0)
- mmc_access_part(dfu, mmc, part_num_bkp);
+ mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
return -EIO;
}
if (dfu->data.mmc.hw_partition >= 0) {
- ret = mmc_access_part(dfu, mmc, part_num_bkp);
+ ret = mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
if (ret)
return ret;
}
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 4448250..431e159 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -269,7 +269,7 @@
/* Prior programming the FPGA, all bridges need to be shut off */
/* Disable all signals from hps peripheral controller to fpga */
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
+ writel(0, &sysmgr_regs->fpgaintfgrp_gbl);
/* Disable all signals from FPGA to HPS SDRAM */
#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index da0199b..b54a10b 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -114,3 +114,18 @@
{
return 0;
}
+
+int name_to_gpio(const char *name)
+{
+ unsigned bank, pin;
+ char *end;
+
+ bank = simple_strtoul(name, &end, 10);
+
+ if (!*end || *end != ':')
+ return bank;
+
+ pin = simple_strtoul(end + 1, NULL, 10);
+
+ return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
+}
diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index c8c8637..932dfe9 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c
@@ -1,19 +1,7 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index ff7f25a..b56a1c2 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -4,19 +4,7 @@
* 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
* Changes for multibus/multiadapter I2C support.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index f20d1b2..5dc4fbb 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -20,7 +20,7 @@
#if defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
-#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP))
+#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
#include <asm/arch/soc.h>
#elif defined(CONFIG_SUNXI)
#include <asm/arch/i2c.h>
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index fa4c82f..b2d15c9 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -581,8 +581,16 @@
return;
}
- mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
- mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
+ /*
+ * Warning: Be careful to allow the assignment to a static
+ * variable here. This function could be called while U-Boot is
+ * still running in flash memory. So such assignment is equal
+ * to write data to flash without erasing.
+ */
+ if (idle_bus_fn)
+ mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
+ if (idle_bus_data)
+ mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
ret = enable_i2c_clk(1, index);
if (ret < 0) {
diff --git a/drivers/misc/cbmem_console.c b/drivers/misc/cbmem_console.c
index 127121e..2703c34 100644
--- a/drivers/misc/cbmem_console.c
+++ b/drivers/misc/cbmem_console.c
@@ -1,18 +1,7 @@
/*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c
index aa893c3..d7c9bd7 100644
--- a/drivers/misc/ds4510.c
+++ b/drivers/misc/ds4510.c
@@ -1,19 +1,7 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c5054d6..1ccc576 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -502,15 +502,22 @@
clk = (pre_div << 8) | (div << 4);
+#ifdef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
+#else
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
+#endif
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
udelay(10000);
- clk = SYSCTL_PEREN | SYSCTL_CKEN;
+#ifdef CONFIG_FSL_USDHC
+ esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA);
+#else
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
- esdhc_setbits32(®s->sysctl, clk);
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@@ -585,7 +592,9 @@
esdhc_write32(®s->scr, 0x00000040);
#endif
+#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#endif
/* Set the initial clock speed */
mmc_set_clock(mmc, 400000);
@@ -657,8 +666,10 @@
/* First reset the eSDHC controller */
esdhc_reset(regs);
+#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
+#endif
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
memset(&cfg->cfg, 0, sizeof(cfg->cfg));
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index b1cb4b3..301d9b3 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -38,7 +38,8 @@
blk_start = ALIGN(offs, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- err = mmc->block_dev.block_read(0, blk_start, blk_cnt, vdst);
+ err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
+ vdst);
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
hang();
@@ -85,7 +86,8 @@
/*
* Read source addr from sd card
*/
- err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
+ err = mmc->block_dev.block_read(&mmc->block_dev,
+ CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
if (err != 1) {
puts("spl: mmc read failed!!\n");
free(tmp_buf);
@@ -126,7 +128,7 @@
#endif
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
- err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
+ err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
(uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 2a58702..e6028d5 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -234,8 +234,11 @@
return blkcnt;
}
-static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
+static ulong mmc_bread(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, void *dst)
{
+ int dev_num = block_dev->dev;
+ int err;
lbaint_t cur, blocks_todo = blkcnt;
if (blkcnt == 0)
@@ -245,6 +248,10 @@
if (!mmc)
return 0;
+ err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ if (err < 0)
+ return 0;
+
if ((start + blkcnt) > mmc->block_dev.lba) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
@@ -579,7 +586,7 @@
if (!mmc)
return -ENODEV;
- if (mmc->part_num == hwpart)
+ if (mmc->block_dev.hwpart == hwpart)
return 0;
if (mmc->part_config == MMCPART_NOAVAILABLE) {
@@ -591,8 +598,6 @@
if (ret)
return ret;
- mmc->part_num = hwpart;
-
return 0;
}
@@ -613,8 +618,10 @@
* Set the capacity if the switch succeeded or was intended
* to return to representing the raw device.
*/
- if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
+ if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
ret = mmc_set_capacity(mmc, part_num);
+ mmc->block_dev.hwpart = part_num;
+ }
return ret;
}
@@ -1324,7 +1331,7 @@
mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
}
- err = mmc_set_capacity(mmc, mmc->part_num);
+ err = mmc_set_capacity(mmc, mmc->block_dev.hwpart);
if (err)
return err;
@@ -1465,11 +1472,14 @@
/* fill in device description */
mmc->block_dev.lun = 0;
+ mmc->block_dev.hwpart = 0;
mmc->block_dev.type = 0;
mmc->block_dev.blksz = mmc->read_bl_len;
mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_SPL_BUILD) || \
+ (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
+ !defined(CONFIG_USE_TINY_PRINTF))
sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
(mmc->cid[3] >> 16) & 0xffff);
@@ -1622,7 +1632,7 @@
return err;
/* The internal partition reset to user partition(0) at every CMD0*/
- mmc->part_num = 0;
+ mmc->block_dev.hwpart = 0;
/* Test for SD version 2 */
err = mmc_send_if_cond(mmc);
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 447a700..6a70639 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -22,23 +22,24 @@
#ifndef CONFIG_SPL_BUILD
-extern unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt);
+unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt);
-extern ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt,
- const void *src);
+unsigned long mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *src);
#else /* CONFIG_SPL_BUILD */
/* SPL will never write or erase, declare dummies to reduce code size. */
-static inline unsigned long mmc_berase(int dev_num, lbaint_t start,
- lbaint_t blkcnt)
+static inline unsigned long mmc_berase(block_dev_desc_t *block_dev,
+ lbaint_t start, lbaint_t blkcnt)
{
return 0;
}
-static inline ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt,
- const void *src)
+static inline ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *src)
{
return 0;
}
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 7aea7e9..79b8c4d 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -51,7 +51,7 @@
goto err_out;
cmd.cmdidx = MMC_CMD_ERASE;
- cmd.cmdarg = SECURE_ERASE;
+ cmd.cmdarg = MMC_ERASE_ARG;
cmd.resp_type = MMC_RSP_R1b;
err = mmc_send_cmd(mmc, &cmd, NULL);
@@ -65,8 +65,10 @@
return err;
}
-unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt)
+unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start,
+ lbaint_t blkcnt)
{
+ int dev_num = block_dev->dev;
int err = 0;
u32 start_rem, blkcnt_rem;
struct mmc *mmc = find_mmc_device(dev_num);
@@ -76,6 +78,10 @@
if (!mmc)
return -1;
+ err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ if (err < 0)
+ return -1;
+
/*
* We want to see if the requested start or total block count are
* unaligned. We discard the whole numbers and only care about the
@@ -165,14 +171,21 @@
return blkcnt;
}
-ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src)
+ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, lbaint_t blkcnt,
+ const void *src)
{
+ int dev_num = block_dev->dev;
lbaint_t cur, blocks_todo = blkcnt;
+ int err;
struct mmc *mmc = find_mmc_device(dev_num);
if (!mmc)
return 0;
+ err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ if (err < 0)
+ return 0;
+
if (mmc_set_blocklen(mmc, mmc->write_bl_len))
return 0;
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 37171bf..5fb7151 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -11,26 +11,25 @@
#include <sdhci.h>
#include <asm/pci.h>
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
- int num_ids)
+int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported)
{
struct sdhci_host *mmc_host;
- pci_dev_t devbusfn;
u32 iobase;
int ret;
int i;
- for (i = 0; i < num_ids; i++) {
- devbusfn = pci_find_devices(mmc_supported, i);
- if (devbusfn == -1)
- return -ENODEV;
+ for (i = 0; ; i++) {
+ struct udevice *dev;
+ ret = pci_find_device_id(mmc_supported, i, &dev);
+ if (ret)
+ return ret;
mmc_host = malloc(sizeof(struct sdhci_host));
if (!mmc_host)
return -ENOMEM;
mmc_host->name = (char *)name;
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
mmc_host->ioaddr = (void *)iobase;
mmc_host->quirks = 0;
ret = add_sdhci(mmc_host, 0, 0);
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index aeaec6c..9b4268e 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -52,6 +52,8 @@
/* use non-removeable as sdcard and emmc as judgement */
if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
+ host->dev_index = 0;
+ else
host->dev_index = 1;
return 0;
diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c
index f92cf00..001bf18 100644
--- a/drivers/mmc/sh_mmcif.c
+++ b/drivers/mmc/sh_mmcif.c
@@ -3,9 +3,7 @@
*
* Copyright (C) 2011 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <config.h>
diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h
index 4b6752f..2f65f9d 100644
--- a/drivers/mmc/sh_mmcif.h
+++ b/drivers/mmc/sh_mmcif.h
@@ -3,10 +3,7 @@
*
* Copyright (C) 2011 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _SH_MMCIF_H_
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 5b0c3a8..43a7e7e 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -33,6 +33,8 @@
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
+ u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
+ ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
/* Disable SDMMC clock. */
clrbits_le32(&clock_manager_base->per_pll.en,
@@ -40,8 +42,7 @@
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
- writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
- &system_manager_base->sdmmcgrp_ctrl);
+ writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(&system_manager_base->sdmmcgrp_ctrl));
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index e717c44..7b33094 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -454,7 +454,7 @@
panic("Failed to allocate memory\n");
if (mmc_getcd(mmc) && mmc_init(mmc) == 0 &&
- mmc->block_dev.block_read(mmc->block_dev.dev, 16, 1, buf) == 1 &&
+ mmc->block_dev.block_read(&mmc->block_dev, 16, 1, buf) == 1 &&
strncmp(&buf[4], "eGON.BT0", 8) == 0)
valid_signature = 1;
diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c
index 617bf5d..a9148a7 100644
--- a/drivers/mtd/altera_qspi.c
+++ b/drivers/mtd/altera_qspi.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <console.h>
#include <dm.h>
#include <errno.h>
#include <fdt_support.h>
@@ -52,6 +53,7 @@
unsigned long size;
};
+static uint flash_verbose;
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
@@ -74,6 +76,11 @@
putc('\n');
}
+void flash_set_verbose(uint v)
+{
+ flash_verbose = v;
+}
+
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
struct mtd_info *mtd = info->mtd;
@@ -81,12 +88,16 @@
int ret;
memset(&instr, 0, sizeof(instr));
+ instr.mtd = mtd;
instr.addr = mtd->erasesize * s_first;
instr.len = mtd->erasesize * (s_last + 1 - s_first);
+ flash_set_verbose(1);
ret = mtd_erase(mtd, &instr);
+ flash_set_verbose(0);
if (ret)
return ERR_PROTECTED;
+ puts(" done\n");
return 0;
}
@@ -130,23 +141,49 @@
size_t end = addr + len;
u32 sect;
u32 stat;
+ u32 *flash, *last;
instr->state = MTD_ERASING;
addr &= ~(mtd->erasesize - 1); /* get lower aligned address */
while (addr < end) {
- sect = addr / mtd->erasesize;
- sect <<= 8;
- sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
- debug("erase %08x\n", sect);
- writel(sect, ®s->mem_op);
- stat = readl(®s->isr);
- if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
- /* erase failed, sector might be protected */
- debug("erase %08x fail %x\n", sect, stat);
- writel(stat, ®s->isr); /* clear isr */
+ if (ctrlc()) {
+ if (flash_verbose)
+ putc('\n');
+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
instr->state = MTD_ERASE_FAILED;
+ mtd_erase_callback(instr);
return -EIO;
}
+ flash = pdata->base + addr;
+ last = pdata->base + addr + mtd->erasesize;
+ /* skip erase if sector is blank */
+ while (flash < last) {
+ if (readl(flash) != 0xffffffff)
+ break;
+ flash++;
+ }
+ if (flash < last) {
+ sect = addr / mtd->erasesize;
+ sect <<= 8;
+ sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
+ debug("erase %08x\n", sect);
+ writel(sect, ®s->mem_op);
+ stat = readl(®s->isr);
+ if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
+ /* erase failed, sector might be protected */
+ debug("erase %08x fail %x\n", sect, stat);
+ writel(stat, ®s->isr); /* clear isr */
+ instr->fail_addr = addr;
+ instr->state = MTD_ERASE_FAILED;
+ mtd_erase_callback(instr);
+ return -EIO;
+ }
+ if (flash_verbose)
+ putc('.');
+ } else {
+ if (flash_verbose)
+ putc(',');
+ }
addr += mtd->erasesize;
}
instr->state = MTD_ERASE_DONE;
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 4cf4c1c..8f0a921 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -3,22 +3,7 @@
* 2N Telekomunikace, a.s. <www.2n.cz>
* Ladislav Michl <michl@2n.cz>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 06266f3..1faec5e 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -12,10 +12,7 @@
*
* Based on original driver mpc5121_nfc.c.
*
- * This is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*
* Limitations:
* - Untested on MPC5125 and M54418.
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index 72e0f6b..19de964 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -46,7 +46,7 @@
void spi_flash_free(struct spi_flash *flash)
{
- spi_flash_remove(flash->spi->dev);
+ device_remove(flash->spi->dev);
}
int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
@@ -55,11 +55,17 @@
{
struct spi_slave *slave;
struct udevice *bus;
- char name[30], *str;
+ char *str;
int ret;
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_TINY_PRINTF)
+ str = "spi_flash";
+#else
+ char name[30];
+
snprintf(name, sizeof(name), "spi_flash@%d:%d", busnum, cs);
str = strdup(name);
+#endif
ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode,
"spi_flash_std", str, &bus, &slave);
if (ret)
@@ -69,11 +75,6 @@
return 0;
}
-int spi_flash_remove(struct udevice *dev)
-{
- return device_remove(dev);
-}
-
static int spi_flash_post_bind(struct udevice *dev)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index ed5c391..007a5a0 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -16,18 +16,18 @@
/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
enum spi_dual_flash {
SF_SINGLE_FLASH = 0,
- SF_DUAL_STACKED_FLASH = 1 << 0,
- SF_DUAL_PARALLEL_FLASH = 1 << 1,
+ SF_DUAL_STACKED_FLASH = BIT(0),
+ SF_DUAL_PARALLEL_FLASH = BIT(1),
};
/* Enum list - Full read commands */
enum spi_read_cmds {
- ARRAY_SLOW = 1 << 0,
- ARRAY_FAST = 1 << 1,
- DUAL_OUTPUT_FAST = 1 << 2,
- DUAL_IO_FAST = 1 << 3,
- QUAD_OUTPUT_FAST = 1 << 4,
- QUAD_IO_FAST = 1 << 5,
+ ARRAY_SLOW = BIT(0),
+ ARRAY_FAST = BIT(1),
+ DUAL_OUTPUT_FAST = BIT(2),
+ QUAD_OUTPUT_FAST = BIT(3),
+ DUAL_IO_FAST = BIT(4),
+ QUAD_IO_FAST = BIT(5),
};
/* Normal - Extended - Full command set */
@@ -37,20 +37,20 @@
/* sf param flags */
enum {
-#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
- SECT_4K = 1 << 0,
+#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
+ SECT_4K = 0,
#else
- SECT_4K = 0 << 0,
+ SECT_4K = BIT(0),
#endif
- SECT_32K = 1 << 1,
- E_FSR = 1 << 2,
- SST_WR = 1 << 3,
- WR_QPP = 1 << 4,
+ SECT_32K = BIT(1),
+ E_FSR = BIT(2),
+ SST_WR = BIT(3),
+ WR_QPP = BIT(4),
};
enum spi_nor_option_flags {
- SNOR_F_SST_WR = (1 << 0),
- SNOR_F_USE_FSR = (1 << 1),
+ SNOR_F_SST_WR = BIT(0),
+ SNOR_F_USE_FSR = BIT(1),
};
#define SPI_FLASH_3B_ADDR_LEN 3
@@ -75,12 +75,9 @@
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS 0x05
-#define CMD_QUAD_PAGE_PROGRAM 0x32
-#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG 0x35
-#define CMD_FLAG_STATUS 0x70
+#define CMD_QUAD_PAGE_PROGRAM 0x32
+#define CMD_WRITE_EVCR 0x61
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
@@ -90,6 +87,11 @@
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_QUAD_IO_FAST 0xeb
#define CMD_READ_ID 0x9f
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS1 0x35
+#define CMD_READ_CONFIG 0x35
+#define CMD_FLAG_STATUS 0x70
+#define CMD_READ_EVCR 0x65
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
@@ -100,10 +102,11 @@
#endif
/* Common status */
-#define STATUS_WIP (1 << 0)
-#define STATUS_QEB_WINSPAN (1 << 1)
-#define STATUS_QEB_MXIC (1 << 6)
-#define STATUS_PEC (1 << 7)
+#define STATUS_WIP BIT(0)
+#define STATUS_QEB_WINSPAN BIT(1)
+#define STATUS_QEB_MXIC BIT(6)
+#define STATUS_PEC BIT(7)
+#define STATUS_QEB_MICRON BIT(7)
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 0cafc29..daa1d5b 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -128,7 +128,7 @@
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (flash->spi->mode & SPI_TX_BYTE)
return sst_write_bp(flash, offset, len, buf);
else
return sst_write_wp(flash, offset, len, buf);
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7ffa136..a567414 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -29,16 +29,6 @@
cmd[3] = addr >> 0;
}
-/* Read commands array */
-static u8 spi_read_cmds_array[] = {
- CMD_READ_ARRAY_SLOW,
- CMD_READ_ARRAY_FAST,
- CMD_READ_DUAL_OUTPUT_FAST,
- CMD_READ_DUAL_IO_FAST,
- CMD_READ_QUAD_OUTPUT_FAST,
- CMD_READ_QUAD_IO_FAST,
-};
-
static int read_sr(struct spi_flash *flash, u8 *rs)
{
int ret;
@@ -121,6 +111,37 @@
}
#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int read_evcr(struct spi_flash *flash, u8 *evcr)
+{
+ int ret;
+ const u8 cmd = CMD_READ_EVCR;
+
+ ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
+ if (ret < 0) {
+ debug("SF: error reading EVCR\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int write_evcr(struct spi_flash *flash, u8 evcr)
+{
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_WRITE_EVCR;
+ ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
+ if (ret < 0) {
+ debug("SF: error while writing EVCR register\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
{
@@ -149,7 +170,7 @@
int ret;
if (flash->size <= SPI_FLASH_16MB_BOUN)
- goto bank_end;
+ goto bar_end;
switch (idcode0) {
case SPI_FLASH_CFI_MFR_SPANSION:
@@ -168,7 +189,7 @@
return ret;
}
-bank_end:
+bar_end:
flash->bank_curr = curr_bank;
return 0;
}
@@ -177,13 +198,15 @@
#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
{
+ struct spi_slave *spi = flash->spi;
+
switch (flash->dual_flash) {
case SF_DUAL_STACKED_FLASH:
if (*addr >= (flash->size >> 1)) {
*addr -= flash->size >> 1;
- flash->spi->flags |= SPI_XFER_U_PAGE;
+ spi->flags |= SPI_XFER_U_PAGE;
} else {
- flash->spi->flags &= ~SPI_XFER_U_PAGE;
+ spi->flags &= ~SPI_XFER_U_PAGE;
}
break;
case SF_DUAL_PARALLEL_FLASH:
@@ -268,7 +291,7 @@
if (buf == NULL)
timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
@@ -353,6 +376,7 @@
int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
unsigned long byte_addr, page_size;
u32 write_addr;
size_t chunk_len, actual;
@@ -385,9 +409,9 @@
byte_addr = offset % page_size;
chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
- if (flash->spi->max_write_size)
+ if (spi->max_write_size)
chunk_len = min(chunk_len,
- (size_t)flash->spi->max_write_size);
+ (size_t)spi->max_write_size);
spi_flash_addr(write_addr, cmd);
@@ -413,7 +437,7 @@
struct spi_slave *spi = flash->spi;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
@@ -438,6 +462,7 @@
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
+ struct spi_slave *spi = flash->spi;
u8 *cmd, cmdsz;
u32 remain_len, read_len, read_addr;
int bank_sel = 0;
@@ -445,15 +470,15 @@
/* Handle memory-mapped SPI */
if (flash->memory_map) {
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
}
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
spi_flash_copy_mmap(data, flash->memory_map + offset, len);
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
- spi_release_bus(flash->spi);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
+ spi_release_bus(spi);
return 0;
}
@@ -505,6 +530,7 @@
#ifdef CONFIG_SPI_FLASH_SST
static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
int ret;
u8 cmd[4] = {
CMD_SST_BP,
@@ -514,13 +540,13 @@
};
debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
+ spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
ret = spi_flash_cmd_write_enable(flash);
if (ret)
return ret;
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
+ ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
if (ret)
return ret;
@@ -530,11 +556,12 @@
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual, cmd_len;
int ret;
u8 cmd[4];
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
@@ -561,10 +588,10 @@
for (; actual < len - 1; actual += 2) {
debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
+ spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
cmd[0], offset);
- ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
+ ret = spi_flash_cmd_write(spi, cmd, cmd_len,
buf + actual, 2);
if (ret) {
debug("SF: sst word program failed\n");
@@ -590,17 +617,18 @@
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
@@ -621,7 +649,7 @@
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
#endif
@@ -767,8 +795,8 @@
return ret;
/* Cannot unlock; would unlock larger region than requested */
- if (stm_is_locked_sr(flash, status_old, ofs - flash->erase_size,
- flash->erase_size))
+ if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
+ status_old))
return -EINVAL;
/*
* Need largest pow such that:
@@ -803,7 +831,7 @@
#ifdef CONFIG_SPI_FLASH_MACRONIX
-static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+static int macronix_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
@@ -812,12 +840,18 @@
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_MXIC) {
- debug("SF: mxic: QEB is already set\n");
- } else {
- ret = write_sr(flash, STATUS_QEB_MXIC);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_MXIC)
+ return 0;
+
+ ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
+ if (ret < 0)
+ return ret;
+
+ /* read SR and check it */
+ ret = read_sr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
+ printf("SF: Macronix SR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
@@ -825,7 +859,7 @@
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+static int spansion_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
@@ -834,34 +868,67 @@
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_WINSPAN) {
- debug("SF: winspan: QEB is already set\n");
- } else {
- ret = write_cr(flash, STATUS_QEB_WINSPAN);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_WINSPAN)
+ return 0;
+
+ ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
+ if (ret < 0)
+ return ret;
+
+ /* read CR and check it */
+ ret = read_cr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
+ printf("SF: Spansion CR Quad bit not clear\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int micron_quad_enable(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ int ret;
+
+ ret = read_evcr(flash, &qeb_status);
+ if (ret < 0)
+ return ret;
+
+ if (!(qeb_status & STATUS_QEB_MICRON))
+ return 0;
+
+ ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
+ if (ret < 0)
+ return ret;
+
+ /* read EVCR and check it */
+ ret = read_evcr(flash, &qeb_status);
+ if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
+ printf("SF: Micron EVCR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
}
#endif
-static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
+static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
#ifdef CONFIG_SPI_FLASH_MACRONIX
case SPI_FLASH_CFI_MFR_MACRONIX:
- return spi_flash_set_qeb_mxic(flash);
+ return macronix_quad_enable(flash);
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND:
- return spi_flash_set_qeb_winspan(flash);
+ return spansion_quad_enable(flash);
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO:
- debug("SF: QEB is volatile for %02x flash\n", idcode0);
- return 0;
+ return micron_quad_enable(flash);
#endif
default:
printf("SF: Need set QEB func for %02x flash\n", idcode0);
@@ -902,9 +969,15 @@
struct spi_slave *spi = flash->spi;
const struct spi_flash_params *params;
u16 jedec, ext_jedec;
- u8 idcode[5];
- u8 cmd;
+ u8 cmd, idcode[5];
int ret;
+ static u8 spi_read_cmds_array[] = {
+ CMD_READ_ARRAY_SLOW,
+ CMD_READ_ARRAY_FAST,
+ CMD_READ_DUAL_OUTPUT_FAST,
+ CMD_READ_QUAD_OUTPUT_FAST,
+ CMD_READ_DUAL_IO_FAST,
+ CMD_READ_QUAD_IO_FAST };
/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
@@ -950,7 +1023,7 @@
/* Assign spi data */
flash->name = params->name;
flash->memory_map = spi->memory_map;
- flash->dual_flash = flash->spi->option;
+ flash->dual_flash = spi->option;
/* Assign spi flash flags */
if (params->flags & SST_WR)
@@ -961,7 +1034,7 @@
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (spi->mode & SPI_TX_BYTE)
flash->write = sst_write_bp;
else
flash->write = sst_write_wp;
@@ -1025,7 +1098,7 @@
flash->sector_size = flash->erase_size;
/* Look for the fastest read cmd */
- cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
+ cmd = fls(params->e_rd_cmd & spi->mode_rx);
if (cmd) {
cmd = spi_read_cmds_array[cmd - 1];
flash->read_cmd = cmd;
@@ -1035,7 +1108,7 @@
}
/* Not require to look for fastest only two write cmds yet */
- if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+ if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else
/* Go for default supported write cmd */
@@ -1045,7 +1118,7 @@
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- ret = spi_flash_set_qeb(flash, idcode[0]);
+ ret = set_quad_mode(flash, idcode[0]);
if (ret) {
debug("SF: Fail to set QEB for %02x\n", idcode[0]);
return -EINVAL;
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index d1bdec3..0be9c5a 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -1351,7 +1351,6 @@
ubi_err(ubi, "self-check failed for PEB %d:%d, len %d",
pnum, offset, len);
ubi_msg(ubi, "data differ at position %d", i);
- dump_len = max_t(int, 128, len - i);
ubi_msg(ubi, "hex dump of the original buffer from %d to %d",
i, i + dump_len);
print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1,
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6905cc0..de54ca8 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -88,6 +88,7 @@
config ETH_DESIGNWARE
bool "Synopsys Designware Ethernet MAC"
+ select PHYLIB
help
This MAC is present in SoCs from various vendors. It supports
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
@@ -103,8 +104,9 @@
config ZYNQ_GEM
depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP)
+ select PHYLIB
bool "Xilinx Ethernet GEM"
help
- This MAC is presetn in Xilinx Zynq and ZynqMP SoCs.
+ This MAC is present in Xilinx Zynq and ZynqMP SoCs.
endif # NETDEVICES
diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c
index 3eaa270..92a1b64 100644
--- a/drivers/net/altera_tse.c
+++ b/drivers/net/altera_tse.c
@@ -417,7 +417,7 @@
bus->read = tse_mdio_read;
bus->write = tse_mdio_write;
- snprintf(bus->name, sizeof(bus->name), name);
+ snprintf(bus->name, sizeof(bus->name), "%s", name);
bus->priv = (void *)priv;
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index d51e098..2659592 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -490,7 +490,7 @@
memset(emacfix, 0, sizeof(emac_device));
memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "emac");
+ strcpy(dev->name, "emac");
dev->iobase = iobase;
dev->priv = emacfix;
dev->init = at91emac_init;
diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c
index ded9e06..43a67a5 100644
--- a/drivers/net/ax88180.c
+++ b/drivers/net/ax88180.c
@@ -722,7 +722,7 @@
memset (priv, 0, sizeof *priv);
- sprintf (dev->name, "ax88180");
+ strcpy(dev->name, "ax88180");
dev->iobase = AX88180_BASE;
dev->priv = priv;
dev->init = ax88180_init;
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 3dff9df..7104754 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -567,7 +567,7 @@
bus->read = cpsw_mdio_read;
bus->write = cpsw_mdio_write;
- sprintf(bus->name, name);
+ strcpy(bus->name, name);
mdio_register(bus);
}
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 0444795..92c3dca 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -777,7 +777,7 @@
return -1;
memset(dev, 0, sizeof *dev);
- sprintf(dev->name, "DaVinci-EMAC");
+ strcpy(dev->name, "DaVinci-EMAC");
dev->iobase = 0;
dev->init = davinci_eth_open;
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index a6c39c3..68b6548 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -22,10 +22,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_PHYLIB)
-# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
-#endif
-
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
struct eth_mac_regs *mac_p = bus->priv;
@@ -85,7 +81,7 @@
bus->read = dw_mdio_read;
bus->write = dw_mdio_write;
- snprintf(bus->name, sizeof(bus->name), name);
+ snprintf(bus->name, sizeof(bus->name), "%s", name);
bus->priv = (void *)mac_regs_p;
@@ -107,8 +103,8 @@
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
- DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
- DESC_TXSTS_TXCHECKINSCTRL | \
+ DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
+ DESC_TXSTS_TXCHECKINSCTRL |
DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
@@ -155,7 +151,7 @@
desc_p->dmamac_next = &desc_table_p[idx + 1];
desc_p->dmamac_cntl =
- (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
+ (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
DESC_RXCTRL_RXCHAIN;
desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
@@ -321,14 +317,14 @@
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
- desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
+ desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
DESC_TXCTRL_SIZE1MASK;
desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
- desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
- DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
+ desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
+ DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
DESC_TXCTRL_TXFIRST;
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
@@ -368,7 +364,7 @@
/* Check if the owner is the CPU */
if (!(status & DESC_RXSTS_OWNBYDMA)) {
- length = (status & DESC_RXSTS_FRMLENMSK) >> \
+ length = (status & DESC_RXSTS_FRMLENMSK) >>
DESC_RXSTS_FRMLENSHFT;
/* Invalidate received data */
@@ -588,7 +584,7 @@
* or via a PCI bridge, fill in platdata before we probe the hardware.
*/
if (device_is_on_pci_bus(dev)) {
- pci_dev_t bdf = pci_get_bdf(dev);
+ pci_dev_t bdf = dm_pci_get_bdf(dev);
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index 3c41cec..93c6667 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -630,7 +630,7 @@
dev->halt = dm9000_halt;
dev->send = dm9000_send;
dev->recv = dm9000_rx;
- sprintf(dev->name, "dm9000");
+ strcpy(dev->name, "dm9000");
eth_register(dev);
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 2ba03ed..70fc02e 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -551,43 +551,6 @@
eeprom->use_eerd = true;
eeprom->use_eewr = false;
break;
-
- /* ich8lan does not support currently. if needed, please
- * add corresponding code and functions.
- */
-#if 0
- case e1000_ich8lan:
- {
- int32_t i = 0;
-
- eeprom->type = e1000_eeprom_ich8;
- eeprom->use_eerd = false;
- eeprom->use_eewr = false;
- eeprom->word_size = E1000_SHADOW_RAM_WORDS;
- uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
- ICH_FLASH_GFPREG);
- /* Zero the shadow RAM structure. But don't load it from NVM
- * so as to save time for driver init */
- if (hw->eeprom_shadow_ram != NULL) {
- for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
- hw->eeprom_shadow_ram[i].modified = false;
- hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
- }
- }
-
- hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
- ICH_FLASH_SECTOR_SIZE;
-
- hw->flash_bank_size = ((flash_size >> 16)
- & ICH_GFPREG_BASE_MASK) + 1;
- hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
-
- hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
-
- hw->flash_bank_size /= 2 * sizeof(uint16_t);
- break;
- }
-#endif
default:
break;
}
@@ -838,14 +801,6 @@
if (eeprom->use_eerd == true)
return e1000_read_eeprom_eerd(hw, offset, words, data);
- /* ich8lan does not support currently. if needed, please
- * add corresponding code and functions.
- */
-#if 0
- /* ICH EEPROM access is done via the ICH flash controller */
- if (eeprom->type == e1000_eeprom_ich8)
- return e1000_read_eeprom_ich8(hw, offset, words, data);
-#endif
/* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
* acquired the EEPROM at this point, so any returns should relase it */
if (eeprom->type == e1000_eeprom_spi) {
@@ -1732,17 +1687,7 @@
* occuring when accessing our register space */
E1000_WRITE_FLUSH(hw);
}
-#if 0
- /* Set the PCI priority bit correctly in the CTRL register. This
- * determines if the adapter gives priority to receives, or if it
- * gives equal priority to transmits and receives. Valid only on
- * 82542 and 82543 silicon.
- */
- if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
- ctrl = E1000_READ_REG(hw, CTRL);
- E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
- }
-#endif
+
switch (hw->mac_type) {
case e1000_82545_rev_3:
case e1000_82546_rev_3:
@@ -1842,20 +1787,6 @@
break;
}
-#if 0
- /* Clear all of the statistics registers (clear on read). It is
- * important that we do this after we have tried to establish link
- * because the symbol error count will increment wildly if there
- * is no link.
- */
- e1000_clear_hw_cntrs(hw);
-
- /* ICH8 No-snoop bits are opposite polarity.
- * Set to snoop by default after reset. */
- if (hw->mac_type == e1000_ich8lan)
- e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
-#endif
-
if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
@@ -5165,11 +5096,11 @@
inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
invalidate_dcache_range(inval_start, inval_end);
- if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
+ if (!(rd->status & E1000_RXD_STAT_DD))
return 0;
/* DEBUGOUT("recv: packet len=%d\n", rd->length); */
/* Packet received, make sure the data are re-loaded from RAM. */
- len = le32_to_cpu(rd->length);
+ len = le16_to_cpu(rd->length);
invalidate_dcache_range((unsigned long)packet,
(unsigned long)packet +
roundup(len, ARCH_DMA_MINALIGN));
@@ -5230,10 +5161,6 @@
E1000_WRITE_REG(hw, RDH, 0);
E1000_WRITE_REG(hw, RDT, 0);
- /* put the card in its initial state */
-#if 0
- E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
-#endif
mdelay(10);
}
@@ -5359,7 +5286,6 @@
#ifndef CONFIG_E1000_NO_NVM
/* Validate the EEPROM and get chipset information */
-#if !defined(CONFIG_MVBC_1G)
if (e1000_init_eeprom_params(hw)) {
E1000_ERR(hw, "EEPROM is invalid!\n");
return -EINVAL;
@@ -5367,7 +5293,6 @@
if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
e1000_validate_eeprom_checksum(hw))
return -ENXIO;
-#endif
e1000_read_mac_addr(hw, enetaddr);
#endif
e1000_get_bus_type(hw);
@@ -5628,8 +5553,8 @@
int ret;
hw->name = dev->name;
- ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev),
- plat->enetaddr);
+ ret = e1000_init_one(hw, trailing_strtol(dev->name),
+ dm_pci_get_bdf(dev), plat->enetaddr);
if (ret < 0) {
printf(pr_fmt("failed to initialize card: %d\n"), ret);
return ret;
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index c851922..e46edcd 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -1093,11 +1093,6 @@
e1000_media_type media_type;
e1000_fc_type fc;
e1000_bus_type bus_type;
-#if 0
- e1000_bus_speed bus_speed;
- e1000_bus_width bus_width;
- uint32_t io_base;
-#endif
uint32_t asf_firmware_present;
#ifndef CONFIG_E1000_NO_NVM
uint32_t eeprom_semaphore_present;
@@ -1116,29 +1111,11 @@
uint32_t original_fc;
uint32_t txcw;
uint32_t autoneg_failed;
-#if 0
- uint32_t max_frame_size;
- uint32_t min_frame_size;
- uint32_t mc_filter_type;
- uint32_t num_mc_addrs;
- uint32_t collision_delta;
- uint32_t tx_packet_delta;
- uint32_t ledctl_default;
- uint32_t ledctl_mode1;
- uint32_t ledctl_mode2;
-#endif
uint16_t autoneg_advertised;
uint16_t pci_cmd_word;
uint16_t fc_high_water;
uint16_t fc_low_water;
uint16_t fc_pause_time;
-#if 0
- uint16_t current_ifs_val;
- uint16_t ifs_min_val;
- uint16_t ifs_max_val;
- uint16_t ifs_step_size;
- uint16_t ifs_ratio;
-#endif
uint16_t device_id;
uint16_t vendor_id;
uint16_t subsystem_id;
@@ -1149,9 +1126,6 @@
uint8_t forced_speed_duplex;
uint8_t wait_autoneg_complete;
uint8_t dma_fairness;
-#if 0
- uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
-#endif
bool disable_polarity_correction;
bool speed_downgraded;
bool get_link_status;
@@ -1162,11 +1136,6 @@
bool report_tx_early;
bool phy_reset_disable;
bool initialize_hw_bits_disable;
-#if 0
- bool adaptive_ifs;
- bool ifs_params_forced;
- bool in_ifs_mode;
-#endif
e1000_smart_speed smart_speed;
e1000_dsp_config dsp_config_state;
};
diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c
index df72375..576ddb8 100644
--- a/drivers/net/e1000_spi.c
+++ b/drivers/net/e1000_spi.c
@@ -182,22 +182,21 @@
* These have been tested to perform correctly, but they are not used by any
* of the EEPROM commands at this time.
*/
-#if 0
-static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr)
+static __maybe_unused int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw,
+ bool intr)
{
u8 op[] = { SPI_EEPROM_DISABLE_WR };
e1000_standby_eeprom(hw);
return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
}
-static int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
- u8 status, bool intr)
+static __maybe_unused int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
+ u8 status, bool intr)
{
u8 op[] = { SPI_EEPROM_WRITE_STATUS, status };
e1000_standby_eeprom(hw);
return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
}
-#endif
static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr)
{
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 79f6737..3340dd2 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -131,13 +131,25 @@
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
+ *
+ * The i.MX28 and i.MX6 types have another field in the MSCR (aka
+ * MII_SPEED) register that defines the MDIO output hold time. Earlier
+ * versions are RAZ there, so just ignore the difference and write the
+ * register always.
+ * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
+ * HOLDTIME + 1 is the number of clk cycles the fec is holding the
+ * output.
+ * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
+ * Given that ceil(clkrate / 5000000) <= 64, the calculation for
+ * holdtime cannot result in a value greater than 3.
*/
- register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
+ u32 pclk = imx_get_fecclk();
+ u32 speed = DIV_ROUND_UP(pclk, 5000000);
+ u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
#ifdef FEC_QUIRK_ENET_MAC
speed--;
#endif
- speed <<= 1;
- writel(speed, ð->mii_speed);
+ writel(speed << 1 | hold << 8, ð->mii_speed);
debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
}
@@ -1097,6 +1109,7 @@
#ifdef CONFIG_PHYLIB
phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
+ mdio_unregister(bus);
free(bus);
return -ENOMEM;
}
@@ -1108,6 +1121,7 @@
#ifdef CONFIG_PHYLIB
free(phydev);
#endif
+ mdio_unregister(bus);
free(bus);
}
return ret;
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index df5db72..40fbf19 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -395,7 +395,8 @@
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 3a1de59..7e312f1 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -242,8 +242,10 @@
int off;
uint32_t ph;
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
+#ifndef CONFIG_SYS_FMAN_V3
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
+#endif
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
if (off == -FDT_ERR_NOTFOUND)
@@ -295,8 +297,10 @@
/* board code might have caused offset to change */
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
+#ifndef CONFIG_SYS_FMAN_V3
/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
if (paddr != dtsec1_addr)
+#endif
fdt_status_disabled(blob, off); /* disable the MAC node */
/* disable the fsl,dpa-ethernet node that points to the MAC */
diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c
index cf2cc95..93ba318 100644
--- a/drivers/net/fm/ls1043.c
+++ b/drivers/net/fm/ls1043.c
@@ -54,11 +54,8 @@
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
- if (is_device_disabled(port)) {
- printf("%s:%d: port(%d) is disabled\n", __func__,
- __LINE__, port);
+ if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
- }
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
@@ -69,15 +66,11 @@
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
- printf("%s:%d: port(FM1_DTSEC3) is OK\n",
- __func__, __LINE__);
return PHY_INTERFACE_MODE_RGMII;
}
if (port == FM1_DTSEC4)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
- printf("%s:%d: port(FM1_DTSEC4) is OK\n",
- __func__, __LINE__);
return PHY_INTERFACE_MODE_RGMII;
}
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index 4ab78e6..5079342 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -146,7 +146,7 @@
bus->read = memac_mdio_read;
bus->write = memac_mdio_write;
bus->reset = memac_mdio_reset;
- sprintf(bus->name, info->name);
+ strcpy(bus->name, info->name);
bus->priv = info->regs;
diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c
index 24cb17b..f038541 100644
--- a/drivers/net/fm/tgec_phy.c
+++ b/drivers/net/fm/tgec_phy.c
@@ -118,7 +118,7 @@
bus->read = tgec_mdio_read;
bus->write = tgec_mdio_write;
bus->reset = tgec_mdio_reset;
- sprintf(bus->name, info->name);
+ strcpy(bus->name, info->name);
bus->priv = info->regs;
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index e1a02d1..bac4610 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -541,19 +541,6 @@
goto out;
}
- if (MC_VER_MAJOR != mc_ver_info.major) {
- printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
- mc_ver_info.major, MC_VER_MAJOR);
- printf("fsl-mc: Update the Management Complex firmware\n");
-
- error = -ENODEV;
- goto out;
- }
-
- if (MC_VER_MINOR != mc_ver_info.minor)
- printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
- mc_ver_info.minor, MC_VER_MINOR);
-
printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
reg_gsr & GSR_FS_MASK);
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index d6b181b..f48bbc3 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -104,7 +104,7 @@
bus->read = tsec_phy_read;
bus->write = tsec_phy_write;
bus->reset = fsl_pq_mdio_reset;
- sprintf(bus->name, info->name);
+ strcpy(bus->name, info->name);
bus->priv = (void *)info->regs;
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 515f0b2..5ccc4be 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -562,7 +562,7 @@
memset(dev, 0, sizeof(*dev));
memset(priv, 0, sizeof(*priv));
- sprintf(dev->name, "FTGMAC100");
+ strcpy(dev->name, "FTGMAC100");
dev->iobase = CONFIG_FTGMAC100_BASE;
dev->init = ftgmac100_init;
dev->halt = ftgmac100_halt;
diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
index bd94f83..1fc7da9 100644
--- a/drivers/net/ftmac100.c
+++ b/drivers/net/ftmac100.c
@@ -246,7 +246,7 @@
memset (dev, 0, sizeof (*dev));
memset (priv, 0, sizeof (*priv));
- sprintf (dev->name, "FTMAC100");
+ strcpy(dev->name, "FTMAC100");
dev->iobase = CONFIG_FTMAC100_BASE;
dev->init = ftmac100_init;
dev->halt = ftmac100_halt;
diff --git a/drivers/net/greth.c b/drivers/net/greth.c
index 088cb22..aa5d711 100644
--- a/drivers/net/greth.c
+++ b/drivers/net/greth.c
@@ -640,9 +640,9 @@
/* Make descriptor string */
if (greth->gbit_mac) {
- sprintf(dev->name, "GRETH_10/100/GB");
+ strcpy(dev->name, "GRETH_10/100/GB");
} else {
- sprintf(dev->name, "GRETH_10/100");
+ strcpy(dev->name, "GRETH_10/100");
}
/* initiate PHY, select speed/duplex depending on connected PHY */
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index 24ca52e..209fae9 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -586,7 +586,7 @@
mdio_bus->write = keystone2_mdio_write;
mdio_bus->reset = keystone2_mdio_reset;
mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
- sprintf(mdio_bus->name, "ethernet-mdio");
+ strcpy(mdio_bus->name, "ethernet-mdio");
res = mdio_register(mdio_bus);
if (res)
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 69530b1..3857122 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -628,11 +628,11 @@
#endif
memset(&dpmac_endpoint, 0, sizeof(struct dprc_endpoint));
- sprintf(dpmac_endpoint.type, "dpmac");
+ strcpy(dpmac_endpoint.type, "dpmac");
dpmac_endpoint.id = priv->dpmac_id;
memset(&dpni_endpoint, 0, sizeof(struct dprc_endpoint));
- sprintf(dpni_endpoint.type, "dpni");
+ strcpy(dpni_endpoint.type, "dpni");
dpni_endpoint.id = dflt_dpni->dpni_id;
err = dprc_connect(dflt_mc_io, MC_CMD_NO_FLAGS,
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
index e76e9bc..6cc273c 100644
--- a/drivers/net/lpc32xx_eth.c
+++ b/drivers/net/lpc32xx_eth.c
@@ -304,6 +304,13 @@
return -EFAULT;
}
+ /* write the phy and reg addressse into the MII address reg */
+ writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
+ ®s->madr);
+
+ /* write data to the MII write register */
+ writel(data, ®s->mwtd);
+
/* wait till the MII is not busy */
timeout = MII_TIMEOUT;
do {
@@ -319,13 +326,6 @@
return -EFAULT;
}
- /* write the phy and reg addressse into the MII address reg */
- writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
- ®s->madr);
-
- /* write data to the MII write register */
- writel(data, ®s->mwtd);
-
/*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
reg_ofs, data);*/
@@ -582,7 +582,7 @@
}
bus->read = lpc32xx_eth_phy_read;
bus->write = lpc32xx_eth_phy_write;
- sprintf(bus->name, dev->name);
+ strcpy(bus->name, dev->name);
ret = mdio_register(bus);
if (ret) {
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index 22ea114..e850672 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -635,7 +635,7 @@
dev->send = mpc512x_fec_send;
dev->recv = mpc512x_fec_recv;
- sprintf (dev->name, "FEC");
+ strcpy(dev->name, "FEC");
eth_register (dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
index 2ebd176..e13b4cf 100644
--- a/drivers/net/mpc5xxx_fec.c
+++ b/drivers/net/mpc5xxx_fec.c
@@ -913,7 +913,7 @@
dev->send = mpc5xxx_fec_send;
dev->recv = mpc5xxx_fec_recv;
- sprintf(dev->name, "FEC");
+ strcpy(dev->name, "FEC");
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index ab5aa68..b16be92 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -675,7 +675,7 @@
}
bus->read = mvgbe_phy_read;
bus->write = mvgbe_phy_write;
- sprintf(bus->name, dev->name);
+ strcpy(bus->name, dev->name);
ret = mdio_register(bus);
if (ret) {
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 38ad14e..fa20f54 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -2,7 +2,7 @@
* Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
*
* U-Boot version:
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
*
* Based on the Linux version which is:
* Copyright (C) 2012 Marvell
@@ -14,6 +14,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <net.h>
#include <netdev.h>
#include <config.h>
@@ -28,6 +29,8 @@
#include <linux/compat.h>
#include <linux/mbus.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if !defined(CONFIG_PHYLIB)
# error Marvell mvneta requires PHYLIB
#endif
@@ -1115,9 +1118,9 @@
mvneta_port_enable(pp);
}
-static void mvneta_adjust_link(struct eth_device *dev)
+static void mvneta_adjust_link(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
struct phy_device *phydev = pp->phydev;
int status_change = 0;
@@ -1171,9 +1174,9 @@
}
}
-static int mvneta_open(struct eth_device *dev)
+static int mvneta_open(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
int ret;
ret = mvneta_setup_rxqs(pp);
@@ -1192,7 +1195,7 @@
}
/* Initialize hw */
-static int mvneta_init(struct mvneta_port *pp)
+static int mvneta_init2(struct mvneta_port *pp)
{
int queue;
@@ -1314,23 +1317,22 @@
}
/* Device initialization routine */
-static int mvneta_probe(struct eth_device *dev)
+static int mvneta_init(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvneta_port *pp = dev_get_priv(dev);
int err;
pp->tx_ring_size = MVNETA_MAX_TXD;
pp->rx_ring_size = MVNETA_MAX_RXD;
- err = mvneta_init(pp);
+ err = mvneta_init2(pp);
if (err < 0) {
dev_err(&pdev->dev, "can't init eth hal\n");
return err;
}
- mvneta_conf_mbus_windows(pp);
-
- mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def);
+ mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
err = mvneta_port_power_up(pp, pp->phy_interface);
if (err < 0) {
@@ -1367,25 +1369,24 @@
}
/*
- * smi_reg_read - miiphy_read callback function.
+ * mvneta_mdio_read - miiphy_read callback function.
*
* Returns 16bit phy register value, or 0xffff on error
*/
-static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data)
+static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = bus->priv;
u32 smi_reg;
u32 timeout;
/* check parameters */
- if (phy_adr > MVNETA_PHY_ADDR_MASK) {
- printf("Error: Invalid PHY address %d\n", phy_adr);
+ if (addr > MVNETA_PHY_ADDR_MASK) {
+ printf("Error: Invalid PHY address %d\n", addr);
return -EFAULT;
}
- if (reg_ofs > MVNETA_PHY_REG_MASK) {
- printf("Err: Invalid register offset %d\n", reg_ofs);
+ if (reg > MVNETA_PHY_REG_MASK) {
+ printf("Err: Invalid register offset %d\n", reg);
return -EFAULT;
}
@@ -1394,14 +1395,14 @@
return -EFAULT;
/* fill the phy address and regiser offset and read opcode */
- smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS)
+ smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
+ | (reg << MVNETA_SMI_REG_ADDR_OFFS)
| MVNETA_SMI_OPCODE_READ;
/* write the smi register */
mvreg_write(pp, MVNETA_SMI, smi_reg);
- /*wait till read value is ready */
+ /* wait till read value is ready */
timeout = MVNETA_SMI_TIMEOUT;
do {
@@ -1417,31 +1418,29 @@
for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
;
- *data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK);
-
- return 0;
+ return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
}
/*
- * smi_reg_write - imiiphy_write callback function.
+ * mvneta_mdio_write - miiphy_write callback function.
*
* Returns 0 if write succeed, -EINVAL on bad parameters
* -ETIME on timeout
*/
-static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
+static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 value)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = bus->priv;
u32 smi_reg;
/* check parameters */
- if (phy_adr > MVNETA_PHY_ADDR_MASK) {
- printf("Error: Invalid PHY address %d\n", phy_adr);
+ if (addr > MVNETA_PHY_ADDR_MASK) {
+ printf("Error: Invalid PHY address %d\n", addr);
return -EFAULT;
}
- if (reg_ofs > MVNETA_PHY_REG_MASK) {
- printf("Err: Invalid register offset %d\n", reg_ofs);
+ if (reg > MVNETA_PHY_REG_MASK) {
+ printf("Err: Invalid register offset %d\n", reg);
return -EFAULT;
}
@@ -1450,9 +1449,9 @@
return -EFAULT;
/* fill the phy addr and reg offset and write opcode and data */
- smi_reg = (data << MVNETA_SMI_DATA_OFFS);
- smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS);
+ smi_reg = value << MVNETA_SMI_DATA_OFFS;
+ smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
+ | (reg << MVNETA_SMI_REG_ADDR_OFFS);
smi_reg &= ~MVNETA_SMI_OPCODE_READ;
/* write the smi register */
@@ -1461,9 +1460,9 @@
return 0;
}
-static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis)
+static int mvneta_start(struct udevice *dev)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
struct phy_device *phydev;
mvneta_port_power_up(pp, pp->phy_interface);
@@ -1483,7 +1482,7 @@
}
/* Full init on first call */
- mvneta_probe(dev);
+ mvneta_init(dev);
pp->init = 1;
} else {
/* Upon all following calls, this is enough */
@@ -1494,9 +1493,9 @@
return 0;
}
-static int mvneta_send(struct eth_device *dev, void *ptr, int len)
+static int mvneta_send(struct udevice *dev, void *packet, int length)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
struct mvneta_tx_queue *txq = &pp->txqs[0];
struct mvneta_tx_desc *tx_desc;
int sent_desc;
@@ -1505,9 +1504,9 @@
/* Get a descriptor for the first part of the packet */
tx_desc = mvneta_txq_next_desc_get(txq);
- tx_desc->buf_phys_addr = (u32)ptr;
- tx_desc->data_size = len;
- flush_dcache_range((u32)ptr, (u32)ptr + len);
+ tx_desc->buf_phys_addr = (u32)packet;
+ tx_desc->data_size = length;
+ flush_dcache_range((u32)packet, (u32)packet + length);
/* First and Last descriptor */
tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
@@ -1525,28 +1524,25 @@
/* txDone has increased - hw sent packet */
mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
- return 0;
return 0;
}
-static int mvneta_recv(struct eth_device *dev)
+static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct mvneta_port *pp = dev->priv;
+ struct mvneta_port *pp = dev_get_priv(dev);
int rx_done;
- int packets_done;
struct mvneta_rx_queue *rxq;
+ int rx_bytes = 0;
/* get rx queue */
rxq = mvneta_rxq_handle_get(pp, rxq_def);
rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
- packets_done = rx_done;
- while (packets_done--) {
+ if (rx_done) {
struct mvneta_rx_desc *rx_desc;
unsigned char *data;
u32 rx_status;
- int rx_bytes;
/*
* No cache invalidation needed here, since the desc's are
@@ -1559,7 +1555,7 @@
(rx_status & MVNETA_RXD_ERR_SUMMARY)) {
mvneta_rx_error(pp, rx_desc);
/* leave the descriptor untouched */
- continue;
+ return -EIO;
}
/* 2 bytes for marvell header. 4 bytes for crc */
@@ -1571,40 +1567,24 @@
* No cache invalidation needed here, since the rx_buffer's are
* located in a uncached memory region
*/
- net_process_received_packet(data, rx_bytes);
- }
+ *packetp = data;
- /* Update rxq management counters */
- if (rx_done)
mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
-
- return 0;
-}
-
-static void mvneta_halt(struct eth_device *dev)
-{
- struct mvneta_port *pp = dev->priv;
+ }
- mvneta_port_down(pp);
- mvneta_port_disable(pp);
+ return rx_bytes;
}
-int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr)
+static int mvneta_probe(struct udevice *dev)
{
- struct eth_device *dev;
- struct mvneta_port *pp;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvneta_port *pp = dev_get_priv(dev);
+ void *blob = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ struct mii_dev *bus;
+ unsigned long addr;
void *bd_space;
- dev = calloc(1, sizeof(*dev));
- if (dev == NULL)
- return -ENOMEM;
-
- pp = calloc(1, sizeof(*pp));
- if (pp == NULL)
- return -ENOMEM;
-
- dev->priv = pp;
-
/*
* Allocate buffer area for descs and rx_buffers. This is only
* done once for all interfaces. As only one interface can
@@ -1625,28 +1605,82 @@
MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc));
}
- sprintf(dev->name, "neta%d", devnum);
+ pp->base = (void __iomem *)pdata->iobase;
- pp->base = (void __iomem *)base_addr;
- dev->iobase = base_addr;
- dev->init = mvneta_init_u_boot;
- dev->halt = mvneta_halt;
- dev->send = mvneta_send;
- dev->recv = mvneta_recv;
- dev->write_hwaddr = NULL;
+ /* Configure MBUS address windows */
+ mvneta_conf_mbus_windows(pp);
- /*
- * The PHY interface type is configured via the
- * board specific CONFIG_SYS_NETA_INTERFACE_TYPE
- * define.
- */
- pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE;
+ /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
+ pp->phy_interface = pdata->phy_interface;
- eth_register(dev);
+ /* Now read phyaddr from DT */
+ addr = fdtdec_get_int(blob, node, "phy", 0);
+ addr = fdt_node_offset_by_phandle(blob, addr);
+ pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
- pp->phyaddr = phy_addr;
- miiphy_register(dev->name, smi_reg_read, smi_reg_write);
- pp->bus = miiphy_get_dev_by_name(dev->name);
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = mvneta_mdio_read;
+ bus->write = mvneta_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+ bus->priv = (void *)pp;
+ pp->bus = bus;
+
+ return mdio_register(bus);
+}
+
+static void mvneta_stop(struct udevice *dev)
+{
+ struct mvneta_port *pp = dev_get_priv(dev);
+
+ mvneta_port_down(pp);
+ mvneta_port_disable(pp);
+}
+
+static const struct eth_ops mvneta_ops = {
+ .start = mvneta_start,
+ .send = mvneta_send,
+ .recv = mvneta_recv,
+ .stop = mvneta_stop,
+};
+
+static int mvneta_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const char *phy_mode;
+
+ pdata->iobase = dev_get_addr(dev);
+
+ /* Get phy-mode / phy_interface from DT */
+ pdata->phy_interface = -1;
+ phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
- return 1;
+ return 0;
}
+
+static const struct udevice_id mvneta_ids[] = {
+ { .compatible = "marvell,armada-370-neta" },
+ { .compatible = "marvell,armada-xp-neta" },
+ { }
+};
+
+U_BOOT_DRIVER(mvneta) = {
+ .name = "mvneta",
+ .id = UCLASS_ETH,
+ .of_match = mvneta_ids,
+ .ofdata_to_platdata = mvneta_ofdata_to_platdata,
+ .probe = mvneta_probe,
+ .ops = &mvneta_ops,
+ .priv_auto_alloc_size = sizeof(struct mvneta_port),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c
index 07a7cec..887cfd9 100644
--- a/drivers/net/ne2000_base.c
+++ b/drivers/net/ne2000_base.c
@@ -794,7 +794,7 @@
dev->send = ne2k_send;
dev->recv = ne2k_recv;
- sprintf(dev->name, "NE2000");
+ strcpy(dev->name, "NE2000");
return eth_register(dev);
}
diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c
index dfc0100..56d29d4 100644
--- a/drivers/net/pch_gbe.c
+++ b/drivers/net/pch_gbe.c
@@ -386,7 +386,7 @@
bus->read = pch_gbe_mdio_read;
bus->write = pch_gbe_mdio_write;
- sprintf(bus->name, name);
+ strcpy(bus->name, name);
bus->priv = (void *)mac_regs;
@@ -424,7 +424,7 @@
pci_dev_t devno;
u32 iobase;
- devno = pci_get_bdf(dev);
+ devno = dm_pci_get_bdf(dev);
/*
* The priv structure contains the descriptors and frame buffers which
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index cfcb1b4..16a7512 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -134,8 +134,17 @@
static void pcnet_halt (struct eth_device *dev);
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
-#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
-#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
+static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
+ void *addr, bool uncached)
+{
+ pci_dev_t devbusfn = (pci_dev_t)dev->priv;
+ void *virt_addr = addr;
+
+ if (uncached)
+ virt_addr = (void *)CKSEG0ADDR(addr);
+
+ return pci_virt_to_mem(devbusfn, virt_addr);
+}
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
@@ -352,7 +361,8 @@
*/
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
- uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]);
+ addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false);
+ uc->rx_ring[i].base = cpu_to_le32(addr);
uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
uc->rx_ring[i].status = cpu_to_le16(0x8000);
PCNET_DEBUG1
@@ -383,8 +393,10 @@
uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
RX_RING_LEN_BITS);
- uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring);
- uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring);
+ addr = pcnet_virt_to_mem(dev, uc->rx_ring, true);
+ uc->init_block.rx_ring = cpu_to_le32(addr);
+ addr = pcnet_virt_to_mem(dev, uc->tx_ring, true);
+ uc->init_block.tx_ring = cpu_to_le32(addr);
PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
uc->init_block.tlen_rlen,
@@ -394,7 +406,7 @@
* Tell the controller where the Init Block is located.
*/
barrier();
- addr = PCI_TO_MEM(dev, &lp->uc->init_block);
+ addr = pcnet_virt_to_mem(dev, &lp->uc->init_block, true);
pcnet_write_csr(dev, 1, addr & 0xffff);
pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
@@ -424,6 +436,7 @@
static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
{
int i, status;
+ u32 addr;
struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
@@ -451,9 +464,10 @@
* Setup Tx ring. Caution: the write order is important here,
* set the status with the "ownership" bits last.
*/
+ addr = pcnet_virt_to_mem(dev, packet, false);
writew(-pkt_len, &entry->length);
writel(0, &entry->misc);
- writel(PCI_TO_MEM(dev, packet), &entry->base);
+ writel(addr, &entry->base);
writew(0x8300, &entry->status);
/* Trigger an immediate send poll. */
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index d509e30..ba57b1a 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -51,7 +51,7 @@
.uid = 0x4dd074,
.mask = 0xffffffef,
.features = PHY_GBIT_FEATURES,
- .config = ar8021_config,
+ .config = ar8035_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 3a2b3bb..447ecfb 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -174,7 +174,8 @@
printf("MMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 5e49666..19b6bc7 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -9,9 +9,14 @@
*/
#include <config.h>
#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
#include <micrel.h>
#include <phy.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static struct phy_driver KSZ804_driver = {
.name = "Micrel KSZ804",
.uid = 0x221510,
@@ -174,6 +179,73 @@
return 0;
}
+/* Common OF config bits for KSZ9021 and KSZ9031 */
+#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
+#ifdef CONFIG_DM_ETH
+struct ksz90x1_reg_field {
+ const char *name;
+ const u8 size; /* Size of the bitfield, in bits */
+ const u8 off; /* Offset from bit 0 */
+ const u8 dflt; /* Default value */
+};
+
+struct ksz90x1_ofcfg {
+ const u16 reg;
+ const u16 devad;
+ const struct ksz90x1_reg_field *grp;
+ const u16 grpsz;
+};
+
+static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
+ { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
+ { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
+};
+
+static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
+ { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
+ { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
+};
+
+static int ksz90x1_of_config_group(struct phy_device *phydev,
+ struct ksz90x1_ofcfg *ofcfg)
+{
+ struct udevice *dev = phydev->dev;
+ struct phy_driver *drv = phydev->drv;
+ const int ps_to_regval = 200;
+ int val[4];
+ int i, changed = 0, offset, max;
+ u16 regval = 0;
+
+ if (!drv || !drv->writeext)
+ return -EOPNOTSUPP;
+
+ for (i = 0; i < ofcfg->grpsz; i++) {
+ val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ ofcfg->grp[i].name, -1);
+ offset = ofcfg->grp[i].off;
+ if (val[i] == -1) {
+ /* Default register value for KSZ9021 */
+ regval |= ofcfg->grp[i].dflt << offset;
+ } else {
+ changed = 1; /* Value was changed in OF */
+ /* Calculate the register value and fix corner cases */
+ if (val[i] > ps_to_regval * 0xf) {
+ max = (1 << ofcfg->grp[i].size) - 1;
+ regval |= max << offset;
+ } else {
+ regval |= (val[i] / ps_to_regval) << offset;
+ }
+ }
+ }
+
+ if (!changed)
+ return 0;
+
+ return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
+}
+#endif
+#endif
+
#ifdef CONFIG_PHY_MICREL_KSZ9021
/*
* KSZ9021
@@ -188,6 +260,35 @@
#define CTRL1000_CONFIG_MASTER (1 << 11)
#define CTRL1000_MANUAL_CONFIG (1 << 12)
+#ifdef CONFIG_DM_ETH
+static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
+ { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
+ { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
+};
+
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+ struct ksz90x1_ofcfg ofcfg[] = {
+ { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
+ { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
+ { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
+ };
+ int i, ret = 0;
+
+ for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+ ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#else
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+ return 0;
+}
+#endif
+
int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
{
/* extended registers */
@@ -224,6 +325,11 @@
const unsigned master = CTRL1000_PREFER_MASTER |
CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
unsigned features = phydev->drv->features;
+ int ret;
+
+ ret = ksz9021_of_config(phydev);
+ if (ret)
+ return ret;
if (getenv("disable_giga"))
features &= ~(SUPPORTED_1000baseT_Half |
@@ -260,6 +366,36 @@
#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
#define MII_KSZ9031_MMD_REG_DATA 0x0e
+#ifdef CONFIG_DM_ETH
+static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
+ { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
+static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
+ { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
+
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+ struct ksz90x1_ofcfg ofcfg[] = {
+ { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
+ { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
+ { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
+ { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
+ };
+ int i, ret = 0;
+
+ for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+ ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#else
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+ return 0;
+}
+#endif
+
/* Accessors to extended registers*/
int ksz9031_phy_extended_write(struct phy_device *phydev,
int devaddr, int regnum, u16 mode, u16 val)
@@ -304,13 +440,21 @@
MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
};
+static int ksz9031_config(struct phy_device *phydev)
+{
+ int ret;
+ ret = ksz9031_of_config(phydev);
+ if (ret)
+ return ret;
+ return genphy_config(phydev);
+}
static struct phy_driver ksz9031_driver = {
.name = "Micrel ksz9031",
.uid = 0x221620,
.mask = 0xfffff0,
.features = PHY_GBIT_FEATURES,
- .config = &genphy_config,
+ .config = &ksz9031_config,
.startup = &ksz90xx_startup,
.shutdown = &genphy_shutdown,
.writeext = &ksz9031_phy_extwrite,
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 19422c4..9e60adf 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -513,8 +513,13 @@
/**************************************************************************
RECV - Receive a frame
***************************************************************************/
-static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase,
+#ifdef CONFIG_DM_ETH
+static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
+ uchar **packetp)
+#else
+static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
uchar **packetp)
+#endif
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
@@ -545,9 +550,16 @@
else
tpc->RxDescArray[cur_rx].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
+#ifdef CONFIG_DM_ETH
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
- pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)
+ dm_pci_mem_to_phys(dev,
+ (pci_addr_t)(unsigned long)
+ tpc->RxBufferRing[cur_rx]));
+#else
+ tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
+ pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
+#endif
rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
#ifdef CONFIG_DM_ETH
*packetp = rxdata;
@@ -576,7 +588,7 @@
{
struct rtl8169_private *priv = dev_get_priv(dev);
- return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp);
+ return rtl_recv_common(dev, priv->iobase, packetp);
}
#else
static int rtl_recv(struct eth_device *dev)
@@ -590,8 +602,13 @@
/**************************************************************************
SEND - Transmit a frame
***************************************************************************/
-static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase,
+#ifdef CONFIG_DM_ETH
+static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
void *packet, int length)
+#else
+static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
+ void *packet, int length)
+#endif
{
/* send the packet to destination */
@@ -618,8 +635,13 @@
ptxb[len++] = '\0';
tpc->TxDescArray[entry].buf_Haddr = 0;
+#ifdef CONFIG_DM_ETH
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
- pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb));
+ dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
+#else
+ tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
+ pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
+#endif
if (entry != (NUM_TX_DESC - 1)) {
tpc->TxDescArray[entry].status =
cpu_to_le32((OWNbit | FSbit | LSbit) |
@@ -661,7 +683,7 @@
{
struct rtl8169_private *priv = dev_get_priv(dev);
- return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length);
+ return rtl_send_common(dev, priv->iobase, packet, length);
}
#else
@@ -695,7 +717,11 @@
RTL_W32(MAR0 + 4, mc_filter[1]);
}
-static void rtl8169_hw_start(pci_dev_t bdf)
+#ifdef CONFIG_DM_ETH
+static void rtl8169_hw_start(struct udevice *dev)
+#else
+static void rtl8169_hw_start(pci_dev_t dev)
+#endif
{
u32 i;
@@ -740,11 +766,21 @@
tpc->cur_rx = 0;
- RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf,
+#ifdef CONFIG_DM_ETH
+ RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
+#else
+ RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
+ (pci_addr_t)(unsigned long)tpc->TxDescArray));
+#endif
RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
+#ifdef CONFIG_DM_ETH
+ RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
+ dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
+#else
RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
- bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray));
+ dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
+#endif
RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
/* RTL-8169sc/8110sc or later version */
@@ -766,7 +802,11 @@
#endif
}
-static void rtl8169_init_ring(pci_dev_t bdf)
+#ifdef CONFIG_DM_ETH
+static void rtl8169_init_ring(struct udevice *dev)
+#else
+static void rtl8169_init_ring(pci_dev_t dev)
+#endif
{
int i;
@@ -794,8 +834,13 @@
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
+#ifdef CONFIG_DM_ETH
+ tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
+ dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
+#else
tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
- bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
+ dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
+#endif
rtl_flush_rx_desc(&tpc->RxDescArray[i]);
}
@@ -804,7 +849,11 @@
#endif
}
-static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr)
+#ifdef CONFIG_DM_ETH
+static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr)
+#else
+static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr)
+#endif
{
int i;
@@ -813,8 +862,8 @@
printf ("%s\n", __FUNCTION__);
#endif
- rtl8169_init_ring(bdf);
- rtl8169_hw_start(bdf);
+ rtl8169_init_ring(dev);
+ rtl8169_hw_start(dev);
/* Construct a perfect filter frame with the mac address as first match
* and broadcast for all others */
for (i = 0; i < 192; i++)
@@ -837,7 +886,7 @@
{
struct eth_pdata *plat = dev_get_platdata(dev);
- rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr);
+ rtl8169_common_start(dev, plat->enetaddr);
return 0;
}
@@ -1130,10 +1179,9 @@
region = 1;
break;
}
- pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4,
- &iobase);
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
iobase &= ~0xf;
- priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase);
+ priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
if (ret < 0) {
diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c
index 6763a24..d538d37 100644
--- a/drivers/net/sandbox.c
+++ b/drivers/net/sandbox.c
@@ -157,7 +157,7 @@
struct eth_sandbox_priv *priv = dev_get_priv(dev);
if (skip_timeout) {
- sandbox_timer_add_offset(10000UL);
+ sandbox_timer_add_offset(11000UL);
skip_timeout = false;
}
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index a320b4d..443a4da 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -560,7 +560,7 @@
dev->recv = sh_eth_recv;
eth->port_info[eth->port].dev = dev;
- sprintf(dev->name, SHETHER_NAME);
+ strcpy(dev->name, SHETHER_NAME);
/* Register Device to EtherNet subsystem */
eth_register(dev);
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 4bdc188..9b09caf 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -632,7 +632,7 @@
priv->phyaddr = tsec_info->phyaddr;
priv->flags = tsec_info->flags;
- sprintf(dev->name, tsec_info->devname);
+ strcpy(dev->name, tsec_info->devname);
priv->interface = tsec_info->interface;
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
dev->iobase = 0;
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 0a41281..7059c84 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -27,10 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_PHYLIB)
-# error XILINX_GEM_ETHERNET requires PHYLIB
-#endif
-
/* Bit/mask specification */
#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
@@ -532,44 +528,55 @@
static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
{
int frame_len;
+ u32 addr;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
- struct emac_bd *first_bd;
if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
- return 0;
+ return -1;
if (!(current_bd->status &
(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
printf("GEM: SOF or EOF not set for last buffer received!\n");
- return 0;
+ return -1;
}
frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
- if (frame_len) {
- u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
- addr &= ~(ARCH_DMA_MINALIGN - 1);
+ if (!frame_len) {
+ printf("%s: Zero size packet?\n", __func__);
+ return -1;
+ }
- net_process_received_packet((u8 *)(ulong)addr, frame_len);
+ addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
+ addr &= ~(ARCH_DMA_MINALIGN - 1);
+ *packetp = (uchar *)(uintptr_t)addr;
- if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
- priv->rx_first_buf = priv->rxbd_current;
- else {
- current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
- current_bd->status = 0xF0000000; /* FIXME */
- }
+ return frame_len;
+}
- if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
- first_bd = &priv->rx_bd[priv->rx_first_buf];
- first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
- first_bd->status = 0xF0000000;
- }
+static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
+ struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
+ struct emac_bd *first_bd;
- if ((++priv->rxbd_current) >= RX_BUF)
- priv->rxbd_current = 0;
+ if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
+ priv->rx_first_buf = priv->rxbd_current;
+ } else {
+ current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
+ current_bd->status = 0xF0000000; /* FIXME */
}
- return frame_len;
+ if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
+ first_bd = &priv->rx_bd[priv->rx_first_buf];
+ first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
+ first_bd->status = 0xF0000000;
+ }
+
+ if ((++priv->rxbd_current) >= RX_BUF)
+ priv->rxbd_current = 0;
+
+ return 0;
}
static void zynq_gem_halt(struct udevice *dev)
@@ -651,6 +658,7 @@
.start = zynq_gem_init,
.send = zynq_gem_send,
.recv = zynq_gem_recv,
+ .free_pkt = zynq_gem_free_pkt,
.stop = zynq_gem_halt,
.write_hwaddr = zynq_gem_setup_mac,
};
@@ -666,11 +674,12 @@
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->emio = 0;
+ priv->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
"phy-handle");
if (offset > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
+ priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
if (phy_mode)
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 6b761b4..f8be9bf 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -6,15 +6,16 @@
#
ifneq ($(CONFIG_DM_PCI),)
-obj-$(CONFIG_PCI) += pci-uclass.o
+obj-y += pci_rom.o
+obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
obj-$(CONFIG_X86) += pci_x86.o
else
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
endif
-obj-$(CONFIG_PCI) += pci_auto_common.o pci_auto_old.o pci_common.o pci_rom.o
+obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 5fe3072..685df9d 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -11,12 +11,14 @@
#include <fdtdec.h>
#include <inttypes.h>
#include <pci.h>
+#include <asm/io.h>
#include <dm/lists.h>
#include <dm/root.h>
#include <dm/device-internal.h>
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
#include <asm/fsp/fsp_support.h>
#endif
+#include "pci_internal.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -61,7 +63,7 @@
return dev;
}
-pci_dev_t pci_get_bdf(struct udevice *dev)
+pci_dev_t dm_pci_get_bdf(struct udevice *dev)
{
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
struct udevice *bus = dev->parent;
@@ -128,7 +130,7 @@
return -ENODEV;
}
-int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
+int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
{
struct udevice *bus;
int ret;
@@ -194,6 +196,65 @@
return -ENODEV;
}
+static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
+ unsigned int device, int *indexp,
+ struct udevice **devp)
+{
+ struct pci_child_platdata *pplat;
+ struct udevice *dev;
+
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ pplat = dev_get_parent_platdata(dev);
+ if (pplat->vendor == vendor && pplat->device == device) {
+ if (!(*indexp)--) {
+ *devp = dev;
+ return 0;
+ }
+ }
+ }
+
+ return -ENODEV;
+}
+
+int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
+ struct udevice **devp)
+{
+ struct udevice *bus;
+
+ /* Scan all known buses */
+ for (uclass_first_device(UCLASS_PCI, &bus);
+ bus;
+ uclass_next_device(&bus)) {
+ if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
+ return device_probe(*devp);
+ }
+ *devp = NULL;
+
+ return -ENODEV;
+}
+
+int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ /* Scan all known buses */
+ for (pci_find_first_device(&dev);
+ dev;
+ pci_find_next_device(&dev)) {
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+
+ if (pplat->class == find_class && !index--) {
+ *devp = dev;
+ return device_probe(*devp);
+ }
+ }
+ *devp = NULL;
+
+ return -ENODEV;
+}
+
int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
unsigned long value, enum pci_size_t size)
{
@@ -225,7 +286,8 @@
for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
- return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
+ return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
+ size);
}
@@ -290,7 +352,7 @@
for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
- return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
+ return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
size);
}
@@ -403,7 +465,7 @@
int ret;
debug("%s: device %s\n", __func__, dev->name);
- ret = pciauto_config_device(hose, pci_get_bdf(dev));
+ ret = dm_pciauto_config_device(dev);
if (ret < 0)
return ret;
max_bus = ret;
@@ -418,26 +480,16 @@
return sub_bus;
}
-int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
+int dm_pci_hose_probe_bus(struct udevice *bus)
{
- struct udevice *parent, *bus;
int sub_bus;
int ret;
debug("%s\n", __func__);
- parent = hose->bus;
-
- /* Find the bus within the parent */
- ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
- if (ret) {
- debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
- bdf, parent->name, ret);
- return ret;
- }
sub_bus = pci_get_bus_max() + 1;
debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
- pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
+ dm_pciauto_prescan_setup_bridge(bus, sub_bus);
ret = device_probe(bus);
if (ret) {
@@ -451,7 +503,7 @@
return -EPIPE;
}
sub_bus = pci_get_bus_max();
- pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
+ dm_pciauto_postscan_setup_bridge(bus, sub_bus);
return sub_bus;
}
@@ -622,9 +674,7 @@
/* Find this device in the device tree */
ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
- /* Search for a driver */
-
- /* If nothing in the device tree, bind a generic device */
+ /* If nothing in the device tree, bind a device */
if (ret == -ENODEV) {
struct pci_device_id find_id;
ulong val;
@@ -1004,6 +1054,154 @@
return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
}
+u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
+{
+ u32 addr;
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ dm_pci_read_config32(dev, bar, &addr);
+ if (addr & PCI_BASE_ADDRESS_SPACE_IO)
+ return addr & PCI_BASE_ADDRESS_IO_MASK;
+ else
+ return addr & PCI_BASE_ADDRESS_MEM_MASK;
+}
+
+static int _dm_pci_bus_to_phys(struct udevice *ctlr,
+ pci_addr_t bus_addr, unsigned long flags,
+ unsigned long skip_mask, phys_addr_t *pa)
+{
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ struct pci_region *res;
+ int i;
+
+ for (i = 0; i < hose->region_count; i++) {
+ res = &hose->regions[i];
+
+ if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
+ continue;
+
+ if (res->flags & skip_mask)
+ continue;
+
+ if (bus_addr >= res->bus_start &&
+ (bus_addr - res->bus_start) < res->size) {
+ *pa = (bus_addr - res->bus_start + res->phys_start);
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
+ unsigned long flags)
+{
+ phys_addr_t phys_addr = 0;
+ struct udevice *ctlr;
+ int ret;
+
+ /* The root controller has the region information */
+ ctlr = pci_get_controller(dev);
+
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
+ if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
+ ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
+ flags, PCI_REGION_SYS_MEMORY,
+ &phys_addr);
+ if (!ret)
+ return phys_addr;
+ }
+
+ ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
+
+ if (ret)
+ puts("pci_hose_bus_to_phys: invalid physical address\n");
+
+ return phys_addr;
+}
+
+int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
+ unsigned long flags, unsigned long skip_mask,
+ pci_addr_t *ba)
+{
+ struct pci_region *res;
+ struct udevice *ctlr;
+ pci_addr_t bus_addr;
+ int i;
+ struct pci_controller *hose;
+
+ /* The root controller has the region information */
+ ctlr = pci_get_controller(dev);
+ hose = dev_get_uclass_priv(ctlr);
+
+ for (i = 0; i < hose->region_count; i++) {
+ res = &hose->regions[i];
+
+ if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
+ continue;
+
+ if (res->flags & skip_mask)
+ continue;
+
+ bus_addr = phys_addr - res->phys_start + res->bus_start;
+
+ if (bus_addr >= res->bus_start &&
+ (bus_addr - res->bus_start) < res->size) {
+ *ba = bus_addr;
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
+ unsigned long flags)
+{
+ pci_addr_t bus_addr = 0;
+ int ret;
+
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
+ if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
+ ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
+ PCI_REGION_SYS_MEMORY, &bus_addr);
+ if (!ret)
+ return bus_addr;
+ }
+
+ ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
+
+ if (ret)
+ puts("pci_hose_phys_to_bus: invalid physical address\n");
+
+ return bus_addr;
+}
+
+void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
+{
+ pci_addr_t pci_bus_addr;
+ u32 bar_response;
+
+ /* read BAR address */
+ dm_pci_read_config32(dev, bar, &bar_response);
+ pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
+
+ /*
+ * Pass "0" as the length argument to pci_bus_to_virt. The arg
+ * isn't actualy used on any platform because u-boot assumes a static
+ * linear mapping. In the future, this could read the BAR size
+ * and pass that as the size if needed.
+ */
+ return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 645ecd4..4619089 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -9,7 +9,10 @@
*/
/*
- * PCI routines
+ * Old PCI routines
+ *
+ * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
+ * and change pci-uclass.c.
*/
#include <common.h>
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
new file mode 100644
index 0000000..5cfa135
--- /dev/null
+++ b/drivers/pci/pci_auto.c
@@ -0,0 +1,387 @@
+/*
+ * PCI autoconfiguration library
+ *
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pci.h>
+
+/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
+#endif
+
+void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
+ struct pci_region *mem,
+ struct pci_region *prefetch, struct pci_region *io,
+ bool enum_only)
+{
+ u32 bar_response;
+ pci_size_t bar_size;
+ u16 cmdstat = 0;
+ int bar, bar_nr = 0;
+ u8 header_type;
+ int rom_addr;
+ pci_addr_t bar_value;
+ struct pci_region *bar_res;
+ int found_mem64 = 0;
+ u16 class;
+
+ dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+ cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
+ PCI_COMMAND_MASTER;
+
+ for (bar = PCI_BASE_ADDRESS_0;
+ bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
+ /* Tickle the BAR and get the response */
+ if (!enum_only)
+ dm_pci_write_config32(dev, bar, 0xffffffff);
+ dm_pci_read_config32(dev, bar, &bar_response);
+
+ /* If BAR is not implemented go to the next BAR */
+ if (!bar_response)
+ continue;
+
+ found_mem64 = 0;
+
+ /* Check the BAR type and set our address mask */
+ if (bar_response & PCI_BASE_ADDRESS_SPACE) {
+ bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
+ & 0xffff) + 1;
+ if (!enum_only)
+ bar_res = io;
+
+ debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
+ bar_nr, (unsigned long long)bar_size);
+ } else {
+ if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ u32 bar_response_upper;
+ u64 bar64;
+
+ if (!enum_only) {
+ dm_pci_write_config32(dev, bar + 4,
+ 0xffffffff);
+ }
+ dm_pci_read_config32(dev, bar + 4,
+ &bar_response_upper);
+
+ bar64 = ((u64)bar_response_upper << 32) |
+ bar_response;
+
+ bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
+ + 1;
+ if (!enum_only)
+ found_mem64 = 1;
+ } else {
+ bar_size = (u32)(~(bar_response &
+ PCI_BASE_ADDRESS_MEM_MASK) + 1);
+ }
+ if (!enum_only) {
+ if (prefetch && (bar_response &
+ PCI_BASE_ADDRESS_MEM_PREFETCH)) {
+ bar_res = prefetch;
+ } else {
+ bar_res = mem;
+ }
+ }
+
+ debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
+ bar_nr, bar_res == prefetch ? "Prf" : "Mem",
+ (unsigned long long)bar_size);
+ }
+
+ if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
+ &bar_value) == 0) {
+ /* Write it out and update our limit */
+ dm_pci_write_config32(dev, bar, (u32)bar_value);
+
+ if (found_mem64) {
+ bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+ dm_pci_write_config32(dev, bar,
+ (u32)(bar_value >> 32));
+#else
+ /*
+ * If we are a 64-bit decoder then increment to
+ * the upper 32 bits of the bar and force it to
+ * locate in the lower 4GB of memory.
+ */
+ dm_pci_write_config32(dev, bar, 0x00000000);
+#endif
+ }
+ }
+
+ cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
+ PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
+
+ debug("\n");
+
+ bar_nr++;
+ }
+
+ if (!enum_only) {
+ /* Configure the expansion ROM address */
+ dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
+ if (header_type != PCI_HEADER_TYPE_CARDBUS) {
+ rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
+ PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
+ dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
+ dm_pci_read_config32(dev, rom_addr, &bar_response);
+ if (bar_response) {
+ bar_size = -(bar_response & ~1);
+ debug("PCI Autoconfig: ROM, size=%#x, ",
+ (unsigned int)bar_size);
+ if (pciauto_region_allocate(mem, bar_size,
+ &bar_value) == 0) {
+ dm_pci_write_config32(dev, rom_addr,
+ bar_value);
+ }
+ cmdstat |= PCI_COMMAND_MEMORY;
+ debug("\n");
+ }
+ }
+ }
+
+ /* PCI_COMMAND_IO must be set for VGA device */
+ dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+ if (class == PCI_CLASS_DISPLAY_VGA)
+ cmdstat |= PCI_COMMAND_IO;
+
+ dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
+ dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
+ CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
+}
+
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+ u16 cmdstat, prefechable_64;
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+
+ dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+ dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+ /* Configure bus number registers */
+ dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
+ PCI_BUS(dm_pci_get_bdf(dev)));
+ dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus);
+ dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
+
+ if (pci_mem) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_mem, 0x100000);
+
+ /*
+ * Set up memory and I/O filter limits, assume 32-bit
+ * I/O space
+ */
+ dm_pci_write_config16(dev, PCI_MEMORY_BASE,
+ (pci_mem->bus_lower & 0xfff00000) >> 16);
+
+ cmdstat |= PCI_COMMAND_MEMORY;
+ }
+
+ if (pci_prefetch) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ /*
+ * Set up memory and I/O filter limits, assume 32-bit
+ * I/O space
+ */
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
+ (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
+ pci_prefetch->bus_lower >> 32);
+#else
+ dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
+#endif
+
+ cmdstat |= PCI_COMMAND_MEMORY;
+ } else {
+ /* We don't support prefetchable memory for now, so disable */
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
+ dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
+ dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+ }
+ }
+
+ if (pci_io) {
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_region_align(pci_io, 0x1000);
+
+ dm_pci_write_config8(dev, PCI_IO_BASE,
+ (pci_io->bus_lower & 0x0000f000) >> 8);
+ dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
+ (pci_io->bus_lower & 0xffff0000) >> 16);
+
+ cmdstat |= PCI_COMMAND_IO;
+ }
+
+ /* Enable memory and I/O accesses, enable bus master */
+ dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
+}
+
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+
+ /* Configure bus number registers */
+ dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus);
+
+ if (pci_mem) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_mem, 0x100000);
+
+ dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
+ (pci_mem->bus_lower - 1) >> 16);
+ }
+
+ if (pci_prefetch) {
+ u16 prefechable_64;
+
+ dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
+ &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
+ (pci_prefetch->bus_lower - 1) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
+ (pci_prefetch->bus_lower - 1) >> 32);
+#else
+ dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+#endif
+ }
+
+ if (pci_io) {
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_region_align(pci_io, 0x1000);
+
+ dm_pci_write_config8(dev, PCI_IO_LIMIT,
+ ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
+ dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
+ ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
+ }
+}
+
+/*
+ * HJF: Changed this to return int. I think this is required
+ * to get the correct result when scanning bridges
+ */
+int dm_pciauto_config_device(struct udevice *dev)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+ unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
+ unsigned short class;
+ bool enum_only = false;
+ int n;
+
+#ifdef CONFIG_PCI_ENUM_ONLY
+ enum_only = true;
+#endif
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+
+ dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+
+ switch (class) {
+ case PCI_CLASS_BRIDGE_PCI:
+ debug("PCI Autoconfig: Found P2P bridge, device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+
+ dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+
+ n = dm_pci_hose_probe_bus(dev);
+ if (n < 0)
+ return n;
+ sub_bus = (unsigned int)n;
+ break;
+
+ case PCI_CLASS_BRIDGE_CARDBUS:
+ /*
+ * just do a minimal setup of the bridge,
+ * let the OS take care of the rest
+ */
+ dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+
+ debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+
+ break;
+
+#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
+ case PCI_CLASS_BRIDGE_OTHER:
+ debug("PCI Autoconfig: Skipping bridge device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+ break;
+#endif
+#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+ case PCI_CLASS_BRIDGE_OTHER:
+ /*
+ * The host/PCI bridge 1 seems broken in 8349 - it presents
+ * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
+ * device claiming resources io/mem/irq.. we only allow for
+ * the PIMMR window to be allocated (BAR0 - 1MB size)
+ */
+ debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
+ dm_pciauto_setup_device(dev, 0, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io,
+ enum_only);
+ break;
+#endif
+
+ case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+ debug("PCI AutoConfig: Found PowerPC device\n");
+ /* fall through */
+
+ default:
+ dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+ break;
+ }
+
+ return sub_bus;
+}
diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c
index 932eab8..edc9a7b 100644
--- a/drivers/pci/pci_auto_old.c
+++ b/drivers/pci/pci_auto_old.c
@@ -1,7 +1,5 @@
/*
- * arch/powerpc/kernel/pci_auto.c
- *
- * PCI autoconfiguration library
+ * PCI autoconfiguration library (legacy version, do not change)
*
* Author: Matt Porter <mporter@mvista.com>
*
@@ -14,6 +12,11 @@
#include <errno.h>
#include <pci.h>
+/*
+ * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
+ * and change pci_auto.c.
+ */
+
/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
@@ -98,11 +101,11 @@
bar_res = prefetch;
else
bar_res = mem;
-#endif
debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
bar_nr, bar_res == prefetch ? "Prf" : "Mem",
(unsigned long long)bar_size);
+#endif
}
#ifndef CONFIG_PCI_ENUM_ONLY
@@ -177,18 +180,9 @@
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
-#endif
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
@@ -196,15 +190,10 @@
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
/* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
- pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
- pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
-#else
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
PCI_BUS(dev) - hose->first_busno);
pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
sub_bus - hose->first_busno);
-#endif
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem) {
@@ -271,26 +260,13 @@
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
-#endif
/* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
-#else
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
sub_bus - hose->first_busno);
-#endif
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
@@ -350,18 +326,9 @@
unsigned short class;
int n;
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
-#endif
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
@@ -373,12 +340,6 @@
pciauto_setup_device(hose, dev, 2, pci_mem,
pci_prefetch, pci_io);
-#ifdef CONFIG_DM_PCI
- n = dm_pci_hose_probe_bus(hose, dev);
- if (n < 0)
- return n;
- sub_bus = (unsigned int)n;
-#else
/* Passing in current_busno allows for sibling P2P bridges */
hose->current_busno++;
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
@@ -393,7 +354,6 @@
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
sub_bus = hose->current_busno;
-#endif
break;
case PCI_CLASS_BRIDGE_CARDBUS:
@@ -407,9 +367,7 @@
debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
PCI_DEV(dev));
-#ifndef CONFIG_DM_PCI
hose->current_busno++;
-#endif
break;
#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
index 2a14902..1755914 100644
--- a/drivers/pci/pci_common.c
+++ b/drivers/pci/pci_common.c
@@ -79,48 +79,6 @@
};
}
-pci_dev_t pci_find_class(uint find_class, int index)
-{
- int bus;
- int devnum;
- pci_dev_t bdf;
- uint32_t class;
-
- for (bus = 0; bus <= pci_last_busno(); bus++) {
- for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
- pci_read_config_dword(PCI_BDF(bus, devnum, 0),
- PCI_CLASS_REVISION, &class);
- if (class >> 16 == 0xffff)
- continue;
-
- for (bdf = PCI_BDF(bus, devnum, 0);
- bdf <= PCI_BDF(bus, devnum,
- PCI_MAX_PCI_FUNCTIONS - 1);
- bdf += PCI_BDF(0, 0, 1)) {
- pci_read_config_dword(bdf, PCI_CLASS_REVISION,
- &class);
- class >>= 8;
-
- if (class != find_class)
- continue;
- /*
- * Decrement the index. We want to return the
- * correct device, so index is 0 for the first
- * matching device, 1 for the second, etc.
- */
- if (index) {
- index--;
- continue;
- }
- /* Return index'th controller. */
- return bdf;
- }
- }
- }
-
- return -ENODEV;
-}
-
__weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
/*
@@ -141,6 +99,7 @@
return 0;
}
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
/* Get a virtual address associated with a BAR region */
void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
{
@@ -363,3 +322,46 @@
return -1;
}
+
+pci_dev_t pci_find_class(uint find_class, int index)
+{
+ int bus;
+ int devnum;
+ pci_dev_t bdf;
+ uint32_t class;
+
+ for (bus = 0; bus <= pci_last_busno(); bus++) {
+ for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
+ pci_read_config_dword(PCI_BDF(bus, devnum, 0),
+ PCI_CLASS_REVISION, &class);
+ if (class >> 16 == 0xffff)
+ continue;
+
+ for (bdf = PCI_BDF(bus, devnum, 0);
+ bdf <= PCI_BDF(bus, devnum,
+ PCI_MAX_PCI_FUNCTIONS - 1);
+ bdf += PCI_BDF(0, 0, 1)) {
+ pci_read_config_dword(bdf, PCI_CLASS_REVISION,
+ &class);
+ class >>= 8;
+
+ if (class != find_class)
+ continue;
+ /*
+ * Decrement the index. We want to return the
+ * correct device, so index is 0 for the first
+ * matching device, 1 for the second, etc.
+ */
+ if (index) {
+ index--;
+ continue;
+ }
+ /* Return index'th controller. */
+ return bdf;
+ }
+ }
+ }
+
+ return -ENODEV;
+}
+#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c
index 712c48f..dd15eb1 100644
--- a/drivers/pci/pci_compat.c
+++ b/drivers/pci/pci_compat.c
@@ -34,5 +34,5 @@
if (pci_find_device_id(ids, index, &dev))
return -1;
- return pci_get_bdf(dev);
+ return dm_pci_get_bdf(dev);
}
diff --git a/drivers/pci/pci_internal.h b/drivers/pci/pci_internal.h
new file mode 100644
index 0000000..0867575
--- /dev/null
+++ b/drivers/pci/pci_internal.h
@@ -0,0 +1,50 @@
+/*
+ * Internal PCI functions, not exported outside drivers/pci
+ *
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __pci_internal_h
+#define __pci_internal_h
+
+/**
+ * dm_pciauto_prescan_setup_bridge() - Set up a bridge for scanning
+ *
+ * This gets a bridge ready so that its downstream devices can be scanned.
+ * It sets up the bus number and memory range registers. Once the scan is
+ * completed, dm_pciauto_postscan_setup_bridge() should be called.
+ *
+ * @dev: Bridge device to be scanned
+ * @sub_bus: Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_postscan_setup_bridge() - Finish set up of a bridge after scanning
+ *
+ * This should be called after a bus scan is complete. It adjusts the memory
+ * ranges to fit with the devices actually found on the other side (downstream)
+ * of the bridge.
+ *
+ * @dev: Bridge device that was scanned
+ * @sub_bus: Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_config_device() - Configure a PCI device ready for use
+ *
+ * If the device is a bridge, downstream devices will be probed.
+ *
+ * @dev: Device to configure
+ * @return the maximum PCI bus number found by this device. If there are no
+ * bridges, this just returns the device's bus number. If the device is a
+ * bridge then it will return a larger number, depending on the devices on
+ * that bridge. On error, returns a -ve error number.
+ */
+int dm_pciauto_config_device(struct udevice *dev);
+
+#endif
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index fd2744d..4eedfe1 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -155,6 +155,14 @@
}
#endif
+static int mvebu_pex_unit_is_x4(int pex_idx)
+{
+ int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3;
+ u32 mask = (0x0f << (pex_unit * 8));
+
+ return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask;
+}
+
static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
{
u32 val;
@@ -419,5 +427,11 @@
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
bus = hose->last_busno + 1;
+
+ /* need to skip more for X4 links, otherwise scan will hang */
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ if (mvebu_pex_unit_is_x4(i))
+ i += 3;
+ }
}
}
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index ad1167e..ed2f61d 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <bios_emul.h>
+#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <pci.h>
@@ -33,12 +34,12 @@
#include <video_fb.h>
#include <linux/screen_info.h>
-__weak bool board_should_run_oprom(pci_dev_t dev)
+__weak bool board_should_run_oprom(struct udevice *dev)
{
return true;
}
-static bool should_load_oprom(pci_dev_t dev)
+static bool should_load_oprom(struct udevice *dev)
{
if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
return 1;
@@ -53,21 +54,18 @@
return vendev;
}
-static int pci_rom_probe(pci_dev_t dev, uint class,
- struct pci_rom_header **hdrp)
+static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
{
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
struct pci_rom_header *rom_header;
struct pci_rom_data *rom_data;
- u16 vendor, device;
u16 rom_vendor, rom_device;
u32 rom_class;
u32 vendev;
u32 mapped_vendev;
u32 rom_address;
- pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
- pci_read_config_word(dev, PCI_DEVICE_ID, &device);
- vendev = vendor << 16 | device;
+ vendev = pplat->vendor << 16 | pplat->device;
mapped_vendev = board_map_oprom_vendev(vendev);
if (vendev != mapped_vendev)
debug("Device ID mapped to %#08x\n", mapped_vendev);
@@ -76,15 +74,15 @@
rom_address = CONFIG_VGA_BIOS_ADDR;
#else
- pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
+ dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
debug("%s: rom_address=%x\n", __func__, rom_address);
return -ENOENT;
}
/* Enable expansion ROM address decoding. */
- pci_write_config_dword(dev, PCI_ROM_ADDRESS,
- rom_address | PCI_ROM_ADDRESS_ENABLE);
+ dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
+ rom_address | PCI_ROM_ADDRESS_ENABLE);
#endif
debug("Option ROM address %x\n", rom_address);
rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
@@ -98,7 +96,7 @@
le16_to_cpu(rom_header->signature));
#ifndef CONFIG_VGA_BIOS_ADDR
/* Disable expansion ROM address decoding */
- pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address);
+ dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
#endif
return -EINVAL;
}
@@ -111,7 +109,7 @@
rom_vendor, rom_device);
/* If the device id is mapped, a mismatch is expected */
- if ((vendor != rom_vendor || device != rom_device) &&
+ if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
(vendev == mapped_vendev)) {
printf("ID mismatch: vendor ID %04x, device ID %04x\n",
rom_vendor, rom_device);
@@ -122,23 +120,35 @@
debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
rom_class, rom_data->type);
- if (class != rom_class) {
+ if (pplat->class != rom_class) {
debug("Class Code mismatch ROM %06x, dev %06x\n",
- rom_class, class);
+ rom_class, pplat->class);
}
*hdrp = rom_header;
return 0;
}
-int pci_rom_load(struct pci_rom_header *rom_header,
- struct pci_rom_header **ram_headerp)
+/**
+ * pci_rom_load() - Load a ROM image and return a pointer to it
+ *
+ * @rom_header: Pointer to ROM image
+ * @ram_headerp: Returns a pointer to the image in RAM
+ * @allocedp: Returns true if @ram_headerp was allocated and needs
+ * to be freed
+ * @return 0 if OK, -ve on error. Note that @allocedp is set up regardless of
+ * the error state. Even if this function returns an error, it may have
+ * allocated memory.
+ */
+static int pci_rom_load(struct pci_rom_header *rom_header,
+ struct pci_rom_header **ram_headerp, bool *allocedp)
{
struct pci_rom_data *rom_data;
unsigned int rom_size;
unsigned int image_size = 0;
void *target;
+ *allocedp = false;
do {
/* Get next image, until we see an x86 version */
rom_header = (struct pci_rom_header *)((void *)rom_header +
@@ -161,6 +171,7 @@
target = (void *)malloc(rom_size);
if (!target)
return -ENOMEM;
+ *allocedp = true;
#endif
if (target != rom_header) {
ulong start = get_timer(0);
@@ -251,36 +262,37 @@
screen_info->rsvd_pos = vesa->reserved_mask_pos;
}
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method)
+int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
+ int exec_method)
{
- struct pci_rom_header *rom, *ram;
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct pci_rom_header *rom, *ram = NULL;
int vesa_mode = -1;
- uint class;
- bool emulate;
+ bool emulate, alloced;
int ret;
/* Only execute VGA ROMs */
- pci_read_config_dword(dev, PCI_REVISION_ID, &class);
- if (((class >> 16) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
- debug("%s: Class %#x, should be %#x\n", __func__, class,
+ if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
+ debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
PCI_CLASS_DISPLAY_VGA);
return -ENODEV;
}
- class >>= 8;
if (!should_load_oprom(dev))
return -ENXIO;
- ret = pci_rom_probe(dev, class, &rom);
+ ret = pci_rom_probe(dev, &rom);
if (ret)
return ret;
- ret = pci_rom_load(rom, &ram);
+ ret = pci_rom_load(rom, &ram, &alloced);
if (ret)
- return ret;
+ goto err;
- if (!board_should_run_oprom(dev))
- return -ENXIO;
+ if (!board_should_run_oprom(dev)) {
+ ret = -ENXIO;
+ goto err;
+ }
#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
defined(CONFIG_FRAMEBUFFER_VESA_MODE)
@@ -294,7 +306,8 @@
#else
if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
printf("BIOS native execution is only available on x86\n");
- return -ENOSYS;
+ ret = -ENOSYS;
+ goto err;
}
emulate = true;
#endif
@@ -304,7 +317,8 @@
#else
if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
- return -ENOSYS;
+ ret = -ENOSYS;
+ goto err;
}
emulate = false;
#endif
@@ -314,14 +328,14 @@
#ifdef CONFIG_BIOSEMU
BE_VGAInfo *info;
- ret = biosemu_setup(dev, &info);
+ ret = biosemu_setup(dm_pci_get_bdf(dev), &info);
if (ret)
- return ret;
+ goto err;
biosemu_set_interrupt_handler(0x15, int15_handler);
- ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true,
- vesa_mode, &mode_info);
+ ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16,
+ info, true, vesa_mode, &mode_info);
if (ret)
- return ret;
+ goto err;
#endif
} else {
#ifdef CONFIG_X86
@@ -332,6 +346,10 @@
#endif
}
debug("Final vesa mode %#x\n", mode_info.video_mode);
+ ret = 0;
- return 0;
+err:
+ if (alloced)
+ free(ram);
+ return ret;
}
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index f1e189e..c14bb0a 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -381,7 +381,7 @@
ret = imx_pcie_addr_valid(d);
if (ret) {
*val = 0xffffffff;
- return ret;
+ return 0;
}
va_address = get_bus_address(d, where);
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 58e88ae..99f9c83 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -314,7 +314,7 @@
if (ls_pcie_addr_valid(hose, d)) {
*val = 0xffffffff;
- return -EINVAL;
+ return 0;
}
if (PCI_BUS(d) == hose->first_busno) {
diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c
index 71678b6..7479af7 100644
--- a/drivers/power/regulator/max77686.c
+++ b/drivers/power/regulator/max77686.c
@@ -515,25 +515,19 @@
switch (on_off) {
case OPMODE_OFF:
- *enable = 0;
+ *enable = false;
break;
case OPMODE_ON:
- *enable = 1;
+ *enable = true;
break;
default:
return -EINVAL;
}
} else if (op == PMIC_OP_SET) {
- switch (*enable) {
- case 0:
- on_off = OPMODE_OFF;
- break;
- case 1:
+ if (*enable)
on_off = OPMODE_ON;
- break;
- default:
- return -EINVAL;
- }
+ else
+ on_off = OPMODE_OFF;
ret = max77686_ldo_mode(dev, op, &on_off);
if (ret)
@@ -651,16 +645,10 @@
return -EINVAL;
}
} else if (op == PMIC_OP_SET) {
- switch (*enable) {
- case 0:
- on_off = OPMODE_OFF;
- break;
- case 1:
+ if (*enable)
on_off = OPMODE_ON;
- break;
- default:
- return -EINVAL;
- }
+ else
+ on_off = OPMODE_OFF;
ret = max77686_buck_mode(dev, op, &on_off);
if (ret)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fc287e..04541c9 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -15,6 +15,26 @@
during serial port initialization (default y). Set this to n on
boards which have no debug serial port whatsoever.
+config SERIAL_PRESENT
+ bool "Provide a serial driver"
+ depends on DM_SERIAL
+ default y
+ help
+ In very space-constrained devices even the full UART driver is too
+ large. In this case the debug UART can still be used in some cases.
+ This option enables the full UART in U-Boot, so if is it disabled,
+ the full UART driver will be omitted, thus saving space.
+
+config SPL_SERIAL_PRESENT
+ bool "Provide a serial driver in SPL"
+ depends on DM_SERIAL
+ default y
+ help
+ In very space-constrained devices even the full UART driver is too
+ large. In this case the debug UART can still be used in some cases.
+ This option enables the full UART in SPL, so if is it disabled,
+ the full UART driver will be omitted, thus saving space.
+
config DM_SERIAL
bool "Enable Driver Model for serial drivers"
depends on DM
diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c
index df7eb05..4624666 100644
--- a/drivers/serial/arm_dcc.c
+++ b/drivers/serial/arm_dcc.c
@@ -2,18 +2,7 @@
* Copyright (C) 2004-2007 ARM Limited.
* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*
* As a special exception, if other files instantiate templates or use macros
* or inline functions from this file, or you compile this file and link it
diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c
index c8926a8..b425375 100644
--- a/drivers/serial/lpc32xx_hsuart.c
+++ b/drivers/serial/lpc32xx_hsuart.c
@@ -1,89 +1,114 @@
/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/uart.h>
-#include <asm/io.h>
+#include <dm.h>
#include <serial.h>
+#include <dm/platform_data/lpc32xx_hsuart.h>
+
+#include <asm/arch/uart.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
-static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
+struct lpc32xx_hsuart_priv {
+ struct hsuart_regs *hsuart;
+};
-static void lpc32xx_serial_setbrg(void)
+static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate)
{
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
u32 div;
/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
- div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
+ div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1;
if (div > 255)
div = 255;
writel(div, &hsuart->rate);
+
+ return 0;
}
-static int lpc32xx_serial_getc(void)
+static int lpc32xx_serial_getc(struct udevice *dev)
{
- while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
- /* NOP */;
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
+
+ if (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
+ return -EAGAIN;
return readl(&hsuart->rx) & HSUART_RX_DATA;
}
-static void lpc32xx_serial_putc(const char c)
+static int lpc32xx_serial_putc(struct udevice *dev, const char c)
{
- if (c == '\n')
- serial_putc('\r');
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
+
+ /* Wait for empty FIFO */
+ if (readl(&hsuart->level) & HSUART_LEVEL_TX)
+ return -EAGAIN;
writel(c, &hsuart->tx);
- /* Wait for character to be sent */
- while (readl(&hsuart->level) & HSUART_LEVEL_TX)
- /* NOP */;
+ return 0;
}
-static int lpc32xx_serial_tstc(void)
+static int lpc32xx_serial_pending(struct udevice *dev, bool input)
{
- if (readl(&hsuart->level) & HSUART_LEVEL_RX)
- return 1;
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+ struct hsuart_regs *hsuart = priv->hsuart;
+
+ if (input) {
+ if (readl(&hsuart->level) & HSUART_LEVEL_RX)
+ return 1;
+ } else {
+ if (readl(&hsuart->level) & HSUART_LEVEL_TX)
+ return 1;
+ }
return 0;
}
-static int lpc32xx_serial_init(void)
+static int lpc32xx_serial_init(struct hsuart_regs *hsuart)
{
- lpc32xx_serial_setbrg();
-
/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
&hsuart->ctrl);
+
return 0;
}
+static int lpc32xx_hsuart_probe(struct udevice *dev)
+{
+ struct lpc32xx_hsuart_platdata *platdata = dev_get_platdata(dev);
+ struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
+
-static struct serial_device lpc32xx_serial_drv = {
- .name = "lpc32xx_serial",
- .start = lpc32xx_serial_init,
- .stop = NULL,
+ priv->hsuart = (struct hsuart_regs *)platdata->base;
+
+ lpc32xx_serial_init(priv->hsuart);
+
+ return 0;
+}
+
+static const struct dm_serial_ops lpc32xx_hsuart_ops = {
.setbrg = lpc32xx_serial_setbrg,
- .putc = lpc32xx_serial_putc,
- .puts = default_serial_puts,
.getc = lpc32xx_serial_getc,
- .tstc = lpc32xx_serial_tstc,
+ .putc = lpc32xx_serial_putc,
+ .pending = lpc32xx_serial_pending,
};
-void lpc32xx_serial_initialize(void)
-{
- serial_register(&lpc32xx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &lpc32xx_serial_drv;
-}
+U_BOOT_DRIVER(lpc32xx_hsuart) = {
+ .name = "lpc32xx_hsuart",
+ .id = UCLASS_SERIAL,
+ .probe = lpc32xx_hsuart_probe,
+ .ops = &lpc32xx_hsuart_ops,
+ .priv_auto_alloc_size = sizeof(struct lpc32xx_hsuart_priv),
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3fab3f1..021b211 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -368,7 +368,7 @@
/* try Processor Local Bus device first */
addr = dev_get_addr(dev);
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
struct fdt_pci_addr pci_addr;
@@ -389,8 +389,7 @@
return ret;
}
- ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset,
- &pci_addr, &bar);
+ ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar);
if (ret)
return ret;
@@ -440,6 +439,7 @@
};
#endif
+#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
U_BOOT_DRIVER(ns16550_serial) = {
.name = "ns16550_serial",
.id = UCLASS_SERIAL,
@@ -453,4 +453,5 @@
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+#endif
#endif /* CONFIG_DM_SERIAL */
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 4bf9a5c..1c447ff 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -204,7 +204,7 @@
{
}
-#ifdef CONFIG_DM_STDIO
+#if defined(CONFIG_DM_STDIO) && CONFIG_IS_ENABLED(SERIAL_PRESENT)
static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
{
_serial_putc(sdev->priv, ch);
@@ -287,6 +287,7 @@
}
U_BOOT_ENV_CALLBACK(baudrate, on_baudrate);
+#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
static int serial_post_probe(struct udevice *dev)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
@@ -356,3 +357,4 @@
.pre_remove = serial_pre_remove,
.per_device_auto_alloc_size = sizeof(struct serial_dev_priv),
};
+#endif
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index d6cf1d8..51485c0 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -75,6 +75,7 @@
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
#define USR1_RTSS (1<<14) /* RTS pin status */
@@ -135,6 +136,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#define TXTL 2 /* reset default */
+#define RXTL 1 /* reset default */
+#define RFDIV 4 /* divide input clock by 2 */
+
static void mxc_serial_setbrg(void)
{
u32 clk = imx_get_uartclk();
@@ -142,7 +147,9 @@
if (!gd->baudrate)
gd->baudrate = CONFIG_BAUDRATE;
- __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
+ __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
+ | (TXTL << UFCR_TXTL_SHF)
+ | (RXTL << UFCR_RXTL_SHF);
__REG(UART_PHYS + UBIR) = 0xf;
__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index b2b98de..3430482 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -192,7 +192,7 @@
};
#ifdef CONFIG_DEBUG_UART_ZYNQ
-void _debug_uart_init(void)
+static inline void _debug_uart_init(void)
{
struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index feec3e8..542b6cf 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -25,7 +25,7 @@
#define TX_BUFFER_SIZE 0x40
#endif
-#define OFFSET_BITS_MASK GENMASK(24, 0)
+#define OFFSET_BITS_MASK GENMASK(23, 0)
#define FLASH_STATUS_WEL 0x02
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index f85af9c..59eaaea 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -752,8 +752,8 @@
* and byte program command for SST flash
*/
if (plat->ich_version == 7) {
- slave->op_mode_rx = SPI_OPM_RX_AS;
- slave->op_mode_tx = SPI_OPM_TX_BP;
+ slave->mode_rx = SPI_RX_SLOW;
+ slave->mode = SPI_TX_BYTE;
}
return 0;
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index e7b0982..7890796 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
@@ -18,6 +19,83 @@
#endif
#include <asm/arch-mvebu/spi.h>
+static void _spi_cs_activate(struct kwspi_registers *reg)
+{
+ setbits_le32(®->ctrl, KWSPI_CSN_ACT);
+}
+
+static void _spi_cs_deactivate(struct kwspi_registers *reg)
+{
+ clrbits_le32(®->ctrl, KWSPI_CSN_ACT);
+}
+
+static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ unsigned int tmpdout, tmpdin;
+ int tm, isread = 0;
+
+ debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
+
+ if (flags & SPI_XFER_BEGIN)
+ _spi_cs_activate(reg);
+
+ /*
+ * handle data in 8-bit chunks
+ * TBD: 2byte xfer mode to be enabled
+ */
+ clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
+
+ while (bitlen > 4) {
+ debug("loopstart bitlen %d\n", bitlen);
+ tmpdout = 0;
+
+ /* Shift data so it's msb-justified */
+ if (dout)
+ tmpdout = *(u32 *)dout & 0xff;
+
+ clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ);
+ writel(tmpdout, ®->dout); /* Write the data out */
+ debug("*** spi_xfer: ... %08x written, bitlen %d\n",
+ tmpdout, bitlen);
+
+ /*
+ * Wait for SPI transmit to get out
+ * or time out (1 second = 1000 ms)
+ * The NE event must be read and cleared first
+ */
+ for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
+ if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) {
+ isread = 1;
+ tmpdin = readl(®->din);
+ debug("spi_xfer: din %p..%08x read\n",
+ din, tmpdin);
+
+ if (din) {
+ *((u8 *)din) = (u8)tmpdin;
+ din += 1;
+ }
+ if (dout)
+ dout += 1;
+ bitlen -= 8;
+ }
+ if (isread)
+ break;
+ }
+ if (tm >= KWSPI_TIMEOUT)
+ printf("*** spi_xfer: Time out during SPI transfer\n");
+
+ debug("loopend bitlen %d\n", bitlen);
+ }
+
+ if (flags & SPI_XFER_END)
+ _spi_cs_deactivate(reg);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_SPI
+
static struct kwspi_registers *spireg =
(struct kwspi_registers *)MVEBU_SPI_BASE;
@@ -147,76 +225,109 @@
void spi_cs_activate(struct spi_slave *slave)
{
- setbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
+ _spi_cs_activate(spireg);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
- clrbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
+ _spi_cs_deactivate(spireg);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
- unsigned int tmpdout, tmpdin;
- int tm, isread = 0;
+ return _spi_xfer(spireg, bitlen, dout, din, flags);
+}
- debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
- slave->bus, slave->cs, dout, din, bitlen);
+#else
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+/* Here now the DM part */
- /*
- * handle data in 8-bit chunks
- * TBD: 2byte xfer mode to be enabled
- */
- clrsetbits_le32(&spireg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
+struct mvebu_spi_platdata {
+ struct kwspi_registers *spireg;
+};
- while (bitlen > 4) {
- debug("loopstart bitlen %d\n", bitlen);
- tmpdout = 0;
+struct mvebu_spi_priv {
+ struct kwspi_registers *spireg;
+};
- /* Shift data so it's msb-justified */
- if (dout)
- tmpdout = *(u32 *)dout & 0xff;
+static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+ u32 data;
- clrbits_le32(&spireg->irq_cause, KWSPI_SMEMRDIRQ);
- writel(tmpdout, &spireg->dout); /* Write the data out */
- debug("*** spi_xfer: ... %08x written, bitlen %d\n",
- tmpdout, bitlen);
+ /* calculate spi clock prescaller using max_hz */
+ data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
+ data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
+ data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
- /*
- * Wait for SPI transmit to get out
- * or time out (1 second = 1000 ms)
- * The NE event must be read and cleared first
- */
- for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
- if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) {
- isread = 1;
- tmpdin = readl(&spireg->din);
- debug("spi_xfer: din %p..%08x read\n",
- din, tmpdin);
+ /* program spi clock prescaler using max_hz */
+ writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
+ debug("data = 0x%08x\n", data);
- if (din) {
- *((u8 *)din) = (u8)tmpdin;
- din += 1;
- }
- if (dout)
- dout += 1;
- bitlen -= 8;
- }
- if (isread)
- break;
- }
- if (tm >= KWSPI_TIMEOUT)
- printf("*** spi_xfer: Time out during SPI transfer\n");
+ return 0;
+}
- debug("loopend bitlen %d\n", bitlen);
- }
+static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+ return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
+}
+
+static int mvebu_spi_probe(struct udevice *bus)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ struct kwspi_registers *reg = plat->spireg;
+
+ writel(KWSPI_SMEMRDY, ®->ctrl);
+ writel(KWSPI_SMEMRDIRQ, ®->irq_cause);
+ writel(KWSPI_IRQMASK, ®->irq_mask);
+
+ return 0;
+}
+
+static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+ plat->spireg = (struct kwspi_registers *)dev_get_addr(bus);
return 0;
}
+
+static const struct dm_spi_ops mvebu_spi_ops = {
+ .xfer = mvebu_spi_xfer,
+ .set_speed = mvebu_spi_set_speed,
+ .set_mode = mvebu_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id mvebu_spi_ids[] = {
+ { .compatible = "marvell,armada-380-spi" },
+ { .compatible = "marvell,armada-xp-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mvebu_spi) = {
+ .name = "mvebu_spi",
+ .id = UCLASS_SPI,
+ .of_match = mvebu_spi_ids,
+ .ops = &mvebu_spi_ops,
+ .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
+ .probe = mvebu_spi_probe,
+};
+#endif
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 5e0c6ad..242a83b 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -135,7 +135,7 @@
50000000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
- debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ debug("%s: base=%lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
__func__, plat->base, plat->periph_id, plat->frequency,
plat->deactivate_delay_us);
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
index 1384385..fe394e3 100644
--- a/drivers/spi/sh_spi.c
+++ b/drivers/spi/sh_spi.c
@@ -3,19 +3,7 @@
*
* Copyright (C) 2011-2012 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/spi/sh_spi.h b/drivers/spi/sh_spi.h
index 96b4b68..a0e949f 100644
--- a/drivers/spi/sh_spi.h
+++ b/drivers/spi/sh_spi.h
@@ -3,19 +3,7 @@
*
* Copyright (C) 2011 Renesas Solutions Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __SH_SPI_H__
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index e0f6b25..677c020 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -157,6 +157,7 @@
slave->max_hz = plat->max_hz;
slave->mode = plat->mode;
+ slave->mode_rx = plat->mode_rx;
return 0;
}
@@ -368,7 +369,8 @@
int spi_slave_ofdata_to_platdata(const void *blob, int node,
struct dm_spi_slave_platdata *plat)
{
- int mode = 0;
+ int mode = 0, mode_rx = 0;
+ int value;
plat->cs = fdtdec_get_int(blob, node, "reg", -1);
plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
@@ -382,8 +384,42 @@
mode |= SPI_3WIRE;
if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
mode |= SPI_PREAMBLE;
+
+ /* Device DUAL/QUAD mode */
+ value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode |= SPI_TX_DUAL;
+ break;
+ case 4:
+ mode |= SPI_TX_QUAD;
+ break;
+ default:
+ error("spi-tx-bus-width %d not supported\n", value);
+ break;
+ }
+
plat->mode = mode;
+ value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode_rx |= SPI_RX_DUAL;
+ break;
+ case 4:
+ mode_rx |= SPI_RX_QUAD;
+ break;
+ default:
+ error("spi-rx-bus-width %d not supported\n", value);
+ break;
+ }
+
+ plat->mode_rx = mode_rx;
+
return 0;
}
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 98a062c..509afba 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -3,22 +3,7 @@
*
* Copyright (c) 2010-2013 NVIDIA Corporation
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 43054f1..238edec 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -3,22 +3,7 @@
*
* Copyright (c) 2010-2013 NVIDIA Corporation
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 5747ed1..78d8b13 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -11,11 +11,14 @@
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
+#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT 2000000
#define QSPI_FCLK 192000000
@@ -41,19 +44,21 @@
#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE QSPI_WC
#define MM_SWITCH 0x01
-#define MEM_CS 0x100
+#define MEM_CS(cs) ((cs + 1) << 8)
#define MEM_CS_UNSELECT 0xfffff0ff
#define MMAP_START_ADDR_DRA 0x5c000000
#define MMAP_START_ADDR_AM43x 0x30000000
#define CORE_CTRL_IO 0x4a002558
#define QSPI_CMD_READ (0x3 << 0)
+#define QSPI_CMD_READ_DUAL (0x6b << 0)
#define QSPI_CMD_READ_QUAD (0x6b << 0)
#define QSPI_CMD_READ_FAST (0x0b << 0)
#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
+#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
#define QSPI_CMD_WRITE (0x2 << 16)
#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
@@ -85,50 +90,24 @@
u32 data3;
};
-/* ti qspi slave */
-struct ti_qspi_slave {
+/* ti qspi priv */
+struct ti_qspi_priv {
+#ifndef CONFIG_DM_SPI
struct spi_slave slave;
+#else
+ void *memory_map;
+ uint max_hz;
+ u32 num_cs;
+#endif
struct ti_qspi_regs *base;
+ void *ctrl_mod_mmap;
unsigned int mode;
u32 cmd;
u32 dc;
};
-static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct ti_qspi_slave, slave);
-}
-
-static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
-{
- struct spi_slave *slave = &qslave->slave;
- u32 memval = 0;
-
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- slave->memory_map = (void *)MMAP_START_ADDR_DRA;
-#else
- slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
-#endif
-
-#ifdef CONFIG_QSPI_QUAD_SUPPORT
- memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_8_BITS |
- QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS);
- slave->op_mode_rx = SPI_OPM_RX_QOF;
-#else
- memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
- QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS;
-#endif
-
- writel(memval, &qslave->base->setup0);
-}
-
-static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
+static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
uint clk_div;
debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
@@ -139,8 +118,8 @@
clk_div = (QSPI_FCLK / hz) - 1;
/* disable SCLK */
- writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
- &qslave->base->clk_ctrl);
+ writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
+ &priv->base->clk_ctrl);
/* assign clk_div values */
if (clk_div < 0)
@@ -149,135 +128,80 @@
clk_div = QSPI_CLK_DIV_MAX;
/* enable SCLK */
- writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
+ writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
}
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
{
- return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* CS handled in xfer */
- return;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
-
- debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
-
- writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+ writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
/* dummy readl to ensure bus sync */
- readl(&qslave->base->cmd);
+ readl(&priv->base->cmd);
}
-void spi_init(void)
+static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
{
- /* nothing to do */
-}
+ priv->dc = 0;
+ if (mode & SPI_CPHA)
+ priv->dc |= QSPI_CKPHA(0);
+ if (mode & SPI_CPOL)
+ priv->dc |= QSPI_CKPOL(0);
+ if (mode & SPI_CS_HIGH)
+ priv->dc |= QSPI_CSPOL(0);
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct ti_qspi_slave *qslave;
-
-#ifdef CONFIG_AM43XX
- gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
- gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
-#endif
-
- qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
- if (!qslave) {
- printf("SPI_error: Fail to allocate ti_qspi_slave\n");
- return NULL;
- }
-
- qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
- qslave->mode = mode;
-
- ti_spi_set_speed(&qslave->slave, max_hz);
-
-#ifdef CONFIG_TI_SPI_MMAP
- ti_spi_setup_spi_register(qslave);
-#endif
-
- return &qslave->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
- free(qslave);
+ return 0;
}
-int spi_claim_bus(struct spi_slave *slave)
+static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+ writel(priv->dc, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
- debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
-
- qslave->dc = 0;
- if (qslave->mode & SPI_CPHA)
- qslave->dc |= QSPI_CKPHA(slave->cs);
- if (qslave->mode & SPI_CPOL)
- qslave->dc |= QSPI_CKPOL(slave->cs);
- if (qslave->mode & SPI_CS_HIGH)
- qslave->dc |= QSPI_CSPOL(slave->cs);
-
- writel(qslave->dc, &qslave->base->dc);
- writel(0, &qslave->base->cmd);
- writel(0, &qslave->base->data);
+ priv->dc <<= cs * 8;
+ writel(priv->dc, &priv->base->dc);
return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+ writel(0, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
+}
- debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
+static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
+{
+ u32 val;
- writel(0, &qslave->base->dc);
- writel(0, &qslave->base->cmd);
- writel(0, &qslave->base->data);
+ val = readl(ctrl_mod_mmap);
+ if (enable)
+ val |= MEM_CS(cs);
+ else
+ val &= MEM_CS_UNSELECT;
+ writel(val, ctrl_mod_mmap);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags,
+ u32 cs)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
uint words = bitlen >> 3; /* fixed 8-bit word length */
const uchar *txp = dout;
uchar *rxp = din;
uint status;
int timeout;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- int val;
-#endif
-
- debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
- slave->bus, slave->cs, bitlen, words, flags);
-
/* Setup mmap flags */
if (flags & SPI_XFER_MMAP) {
- writel(MM_SWITCH, &qslave->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- val = readl(CORE_CTRL_IO);
- val |= MEM_CS;
- writel(val, CORE_CTRL_IO);
-#endif
+ writel(MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
return 0;
} else if (flags & SPI_XFER_MMAP_END) {
- writel(~MM_SWITCH, &qslave->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- val = readl(CORE_CTRL_IO);
- val &= MEM_CS_UNSELECT;
- writel(val, CORE_CTRL_IO);
-#endif
+ writel(~MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
return 0;
}
@@ -290,12 +214,12 @@
}
/* Setup command reg */
- qslave->cmd = 0;
- qslave->cmd |= QSPI_WLEN(8);
- qslave->cmd |= QSPI_EN_CS(slave->cs);
- if (qslave->mode & SPI_3WIRE)
- qslave->cmd |= QSPI_3_PIN;
- qslave->cmd |= 0xfff;
+ priv->cmd = 0;
+ priv->cmd |= QSPI_WLEN(8);
+ priv->cmd |= QSPI_EN_CS(cs);
+ if (priv->mode & SPI_3WIRE)
+ priv->cmd |= QSPI_3_PIN;
+ priv->cmd |= 0xfff;
/* FIXME: This delay is required for successfull
* completion of read/write/erase. Once its root
@@ -307,39 +231,39 @@
while (words--) {
if (txp) {
debug("tx cmd %08x dc %08x data %02x\n",
- qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
- writel(*txp++, &qslave->base->data);
- writel(qslave->cmd | QSPI_WR_SNGL,
- &qslave->base->cmd);
- status = readl(&qslave->base->status);
+ priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
+ writel(*txp++, &priv->base->data);
+ writel(priv->cmd | QSPI_WR_SNGL,
+ &priv->base->cmd);
+ status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout < 0) {
printf("spi_xfer: TX timeout!\n");
return -1;
}
- status = readl(&qslave->base->status);
+ status = readl(&priv->base->status);
}
debug("tx done, status %08x\n", status);
}
if (rxp) {
- qslave->cmd |= QSPI_RD_SNGL;
+ priv->cmd |= QSPI_RD_SNGL;
debug("rx cmd %08x dc %08x\n",
- qslave->cmd, qslave->dc);
+ priv->cmd, priv->dc);
#ifdef CONFIG_DRA7XX
udelay(500);
#endif
- writel(qslave->cmd, &qslave->base->cmd);
- status = readl(&qslave->base->status);
+ writel(priv->cmd, &priv->base->cmd);
+ status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout < 0) {
printf("spi_xfer: RX timeout!\n");
return -1;
}
- status = readl(&qslave->base->status);
+ status = readl(&priv->base->status);
}
- *rxp++ = readl(&qslave->base->data);
+ *rxp++ = readl(&priv->base->data);
debug("rx done, status %08x, read %02x\n",
status, *(rxp-1));
}
@@ -347,7 +271,7 @@
/* Terminate frame */
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ ti_qspi_cs_deactivate(priv);
return 0;
}
@@ -374,3 +298,293 @@
*((unsigned int *)offset) += len;
}
#endif
+
+#ifndef CONFIG_DM_SPI
+
+static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
+{
+ return container_of(slave, struct ti_qspi_priv, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+ ti_qspi_cs_deactivate(priv);
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
+{
+ u32 memval = 0;
+
+#ifdef CONFIG_QSPI_QUAD_SUPPORT
+ struct spi_slave *slave = &priv->slave;
+ memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_8_BITS |
+ QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS);
+ slave->mode_rx = SPI_RX_QUAD;
+#else
+ memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
+ QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS;
+#endif
+
+ writel(memval, &priv->base->setup0);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct ti_qspi_priv *priv;
+
+#ifdef CONFIG_AM43XX
+ gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
+ gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
+ priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
+ if (!priv) {
+ printf("SPI_error: Fail to allocate ti_qspi_priv\n");
+ return NULL;
+ }
+
+ priv->base = (struct ti_qspi_regs *)QSPI_BASE;
+ priv->mode = mode;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+ priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
+ priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+ priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
+#endif
+
+ ti_spi_set_speed(priv, max_hz);
+
+#ifdef CONFIG_TI_SPI_MMAP
+ ti_spi_setup_spi_register(priv);
+#endif
+
+ return &priv->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+ free(priv);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+ __ti_qspi_set_mode(priv, priv->mode);
+ return __ti_qspi_claim_bus(priv, priv->slave.cs);
+}
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+ __ti_qspi_release_bus(priv);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
+ priv->slave.bus, priv->slave.cs, bitlen, flags);
+ return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
+}
+
+#else /* CONFIG_DM_SPI */
+
+static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
+ struct spi_slave *slave,
+ bool enable)
+{
+ u32 memval;
+ u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
+
+ if (!enable) {
+ writel(0, &priv->base->setup0);
+ return;
+ }
+
+ memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
+
+ switch (mode) {
+ case SPI_RX_QUAD:
+ memval |= QSPI_CMD_READ_QUAD;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ memval |= QSPI_SETUP0_READ_QUAD;
+ slave->mode_rx = SPI_RX_QUAD;
+ break;
+ case SPI_RX_DUAL:
+ memval |= QSPI_CMD_READ_DUAL;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ memval |= QSPI_SETUP0_READ_DUAL;
+ break;
+ default:
+ memval |= QSPI_CMD_READ;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
+ memval |= QSPI_SETUP0_READ_NORMAL;
+ break;
+ }
+
+ writel(memval, &priv->base->setup0);
+}
+
+
+static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+ ti_spi_set_speed(priv, max_hz);
+
+ return 0;
+}
+
+static int ti_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+ return __ti_qspi_set_mode(priv, mode);
+}
+
+static int ti_qspi_claim_bus(struct udevice *dev)
+{
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (slave_plat->cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
+ }
+
+ __ti_qspi_setup_memorymap(priv, slave, true);
+
+ return __ti_qspi_claim_bus(priv, slave_plat->cs);
+}
+
+static int ti_qspi_release_bus(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ __ti_qspi_setup_memorymap(priv, slave, false);
+ __ti_qspi_release_bus(priv);
+
+ return 0;
+}
+
+static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (slave->cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
+ }
+
+ return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
+}
+
+static int ti_qspi_probe(struct udevice *bus)
+{
+ /* Nothing to do in probe */
+ return 0;
+}
+
+static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
+ fdt_addr_t addr;
+
+ priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
+ priv->memory_map = (void *)dev_get_addr_index(bus, 1);
+ addr = dev_get_addr_index(bus, 2);
+ priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
+
+ priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
+ if (priv->max_hz < 0) {
+ debug("Error: Max frequency missing\n");
+ return -ENODEV;
+ }
+ priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
+
+ debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
+ (int)priv->base, priv->max_hz);
+
+ return 0;
+}
+
+static int ti_qspi_child_pre_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+ slave->memory_map = priv->memory_map;
+ return 0;
+}
+
+static const struct dm_spi_ops ti_qspi_ops = {
+ .claim_bus = ti_qspi_claim_bus,
+ .release_bus = ti_qspi_release_bus,
+ .xfer = ti_qspi_xfer,
+ .set_speed = ti_qspi_set_speed,
+ .set_mode = ti_qspi_set_mode,
+};
+
+static const struct udevice_id ti_qspi_ids[] = {
+ { .compatible = "ti,dra7xxx-qspi" },
+ { .compatible = "ti,am4372-qspi" },
+ { }
+};
+
+U_BOOT_DRIVER(ti_qspi) = {
+ .name = "ti_qspi",
+ .id = UCLASS_SPI,
+ .of_match = ti_qspi_ids,
+ .ops = &ti_qspi_ops,
+ .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
+ .probe = ti_qspi_probe,
+ .child_pre_probe = ti_qspi_child_pre_probe,
+};
+#endif /* CONFIG_DM_SPI */
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 5825c6d..b98663c 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -30,6 +30,7 @@
#define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
#define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
+#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
/* zynq qspi Transmit Data Register */
#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
@@ -68,6 +69,9 @@
u32 txd1r; /* 0x80 */
u32 txd2r; /* 0x84 */
u32 txd3r; /* 0x88 */
+ u32 reserved1[5];
+ u32 lqspicfg; /* 0xA0 */
+ u32 lqspists; /* 0xA4 */
};
/* zynq qspi platform data */
@@ -143,6 +147,11 @@
ZYNQ_QSPI_CR_MSTREN_MASK;
writel(confr, ®s->cr);
+ /* Disable the LQSPI feature */
+ confr = readl(®s->lqspicfg);
+ confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
+ writel(confr, ®s->lqspicfg);
+
/* Enable SPI */
writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
}
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 09a3c52..0509094 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -130,7 +130,7 @@
#elif defined(CONFIG_MX7)
static int read_cpu_temperature(struct udevice *dev)
{
- unsigned int reg, tmp, start;
+ unsigned int reg, tmp;
unsigned int raw_25c, te1;
int temperature;
unsigned int *priv = dev_get_priv(dev);
@@ -169,18 +169,25 @@
writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
- start = get_timer(0);
- /* Wait max 100ms */
- do {
+ if (soc_rev() >= CHIP_REV_1_1) {
+ while ((readl(&ccm_anatop->tempsense1) &
+ TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0)
+ ;
+ reg = readl(&ccm_anatop->tempsense1);
+ tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
+ >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
+ } else {
/*
- * Since we can not rely on finish bit, use 1ms delay to get
- * temperature. From RM, 17us is enough to get data, but
- * to gurantee to get the data, delay 100ms here.
+ * Since we can not rely on finish bit, use 10ms
+ * delay to get temperature. From RM, 17us is
+ * enough to get data, but to gurantee to get
+ * the data, delay 10ms here.
*/
+ udelay(10000);
reg = readl(&ccm_anatop->tempsense1);
tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
>> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
- } while (get_timer(0) < (start + 100));
+ }
writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c
index bbdad8b..9d6cf8c 100644
--- a/drivers/usb/eth/mcs7830.c
+++ b/drivers/usb/eth/mcs7830.c
@@ -11,6 +11,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <linux/mii.h>
#include <malloc.h>
@@ -83,19 +84,23 @@
* @mchash: shadow for the network adapter's multicast hash registers
*/
struct mcs7830_private {
+#ifdef CONFIG_DM_ETH
+ uint8_t rx_buf[MCS7830_RX_URB_SIZE];
+ struct ueth_data ueth;
+#endif
uint8_t config;
uint8_t mchash[8];
};
/*
* mcs7830_read_reg() - read a register of the network adapter
- * @dev: network device to read from
+ * @udev: network device to read from
* @idx: index of the register to start reading from
* @size: number of bytes to read
* @data: buffer to read into
* Return: zero upon success, negative upon error
*/
-static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx,
+static int mcs7830_read_reg(struct usb_device *udev, uint8_t idx,
uint16_t size, void *data)
{
int len;
@@ -103,8 +108,8 @@
debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
- len = usb_control_msg(dev->pusb_dev,
- usb_rcvctrlpipe(dev->pusb_dev, 0),
+ len = usb_control_msg(udev,
+ usb_rcvctrlpipe(udev, 0),
MCS7830_RD_BREQ,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, idx, buf, size,
@@ -119,13 +124,13 @@
/*
* mcs7830_write_reg() - write a register of the network adapter
- * @dev: network device to write to
+ * @udev: network device to write to
* @idx: index of the register to start writing to
* @size: number of bytes to write
* @data: buffer holding the data to write
* Return: zero upon success, negative upon error
*/
-static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx,
+static int mcs7830_write_reg(struct usb_device *udev, uint8_t idx,
uint16_t size, void *data)
{
int len;
@@ -134,8 +139,8 @@
debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
memcpy(buf, data, size);
- len = usb_control_msg(dev->pusb_dev,
- usb_sndctrlpipe(dev->pusb_dev, 0),
+ len = usb_control_msg(udev,
+ usb_sndctrlpipe(udev, 0),
MCS7830_WR_BREQ,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, idx, buf, size,
@@ -149,12 +154,12 @@
/*
* mcs7830_phy_emit_wait() - emit PHY read/write access, wait for its execution
- * @dev: network device to talk to
+ * @udev: network device to talk to
* @rwflag: PHY_CMD1_READ or PHY_CMD1_WRITE opcode
* @index: number of the PHY register to read or write
* Return: zero upon success, negative upon error
*/
-static int mcs7830_phy_emit_wait(struct ueth_data *dev,
+static int mcs7830_phy_emit_wait(struct usb_device *udev,
uint8_t rwflag, uint8_t index)
{
int rc;
@@ -164,14 +169,14 @@
/* send the PHY read/write request */
cmd[0] = rwflag | PHY_CMD1_PHYADDR;
cmd[1] = PHY_CMD2_PEND | (index & 0x1f);
- rc = mcs7830_write_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+ rc = mcs7830_write_reg(udev, REG_PHY_CMD, sizeof(cmd), cmd);
if (rc < 0)
return rc;
/* wait for the response to become available (usually < 1ms) */
retry = 10;
do {
- rc = mcs7830_read_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+ rc = mcs7830_read_reg(udev, REG_PHY_CMD, sizeof(cmd), cmd);
if (rc < 0)
return rc;
if (cmd[1] & PHY_CMD2_READY)
@@ -185,50 +190,51 @@
/*
* mcs7830_read_phy() - read a PHY register of the network adapter
- * @dev: network device to read from
+ * @udev: network device to read from
* @index: index of the PHY register to read from
* Return: non-negative 16bit register content, negative upon error
*/
-static int mcs7830_read_phy(struct ueth_data *dev, uint8_t index)
+static int mcs7830_read_phy(struct usb_device *udev, uint8_t index)
{
int rc;
uint16_t val;
/* issue the PHY read request and wait for its execution */
- rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_READ, index);
+ rc = mcs7830_phy_emit_wait(udev, PHY_CMD1_READ, index);
if (rc < 0)
return rc;
/* fetch the PHY data which was read */
- rc = mcs7830_read_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+ rc = mcs7830_read_reg(udev, REG_PHY_DATA, sizeof(val), &val);
if (rc < 0)
return rc;
rc = le16_to_cpu(val);
- debug("%s(%s, %d) => 0x%04X\n", __func__, dev->eth_dev.name, index, rc);
+ debug("%s(%d) => 0x%04X\n", __func__, index, rc);
return rc;
}
/*
* mcs7830_write_phy() - write a PHY register of the network adapter
- * @dev: network device to write to
+ * @udev: network device to write to
* @index: index of the PHY register to write to
* @val: value to write to the PHY register
* Return: zero upon success, negative upon error
*/
-static int mcs7830_write_phy(struct ueth_data *dev, uint8_t index, uint16_t val)
+static int mcs7830_write_phy(struct usb_device *udev, uint8_t index,
+ uint16_t val)
{
int rc;
- debug("%s(%s, %d, 0x%04X)\n", __func__, dev->eth_dev.name, index, val);
+ debug("%s(%d, 0x%04X)\n", __func__, index, val);
/* setup the PHY data which is to get written */
val = cpu_to_le16(val);
- rc = mcs7830_write_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+ rc = mcs7830_write_reg(udev, REG_PHY_DATA, sizeof(val), &val);
if (rc < 0)
return rc;
/* issue the PHY write request and wait for its execution */
- rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_WRITE, index);
+ rc = mcs7830_phy_emit_wait(udev, PHY_CMD1_WRITE, index);
if (rc < 0)
return rc;
@@ -237,21 +243,21 @@
/*
* mcs7830_write_config() - write to the network adapter's config register
- * @eth: network device to write to
+ * @udev: network device to write to
+ * @priv: private data
* Return: zero upon success, negative upon error
*
* the data which gets written is taken from the shadow config register
* within the device driver's private data
*/
-static int mcs7830_write_config(struct ueth_data *dev)
+static int mcs7830_write_config(struct usb_device *udev,
+ struct mcs7830_private *priv)
{
- struct mcs7830_private *priv;
int rc;
debug("%s()\n", __func__);
- priv = dev->dev_priv;
- rc = mcs7830_write_reg(dev, REG_CONFIG,
+ rc = mcs7830_write_reg(udev, REG_CONFIG,
sizeof(priv->config), &priv->config);
if (rc < 0) {
debug("writing config to adapter failed\n");
@@ -263,21 +269,21 @@
/*
* mcs7830_write_mchash() - write the network adapter's multicast filter
- * @eth: network device to write to
+ * @udev: network device to write to
+ * @priv: private data
* Return: zero upon success, negative upon error
*
* the data which gets written is taken from the shadow multicast hashes
* within the device driver's private data
*/
-static int mcs7830_write_mchash(struct ueth_data *dev)
+static int mcs7830_write_mchash(struct usb_device *udev,
+ struct mcs7830_private *priv)
{
- struct mcs7830_private *priv;
int rc;
debug("%s()\n", __func__);
- priv = dev->dev_priv;
- rc = mcs7830_write_reg(dev, REG_MULTICAST_HASH,
+ rc = mcs7830_write_reg(udev, REG_MULTICAST_HASH,
sizeof(priv->mchash), &priv->mchash);
if (rc < 0) {
debug("writing multicast hash to adapter failed\n");
@@ -289,12 +295,12 @@
/*
* mcs7830_set_autoneg() - setup and trigger ethernet link autonegotiation
- * @eth: network device to run link negotiation on
+ * @udev: network device to run link negotiation on
* Return: zero upon success, negative upon error
*
* the routine advertises available media and starts autonegotiation
*/
-static int mcs7830_set_autoneg(struct ueth_data *dev)
+static int mcs7830_set_autoneg(struct usb_device *udev)
{
int adv, flg;
int rc;
@@ -310,39 +316,39 @@
*/
adv = ADVERTISE_PAUSE_CAP | ADVERTISE_ALL | ADVERTISE_CSMA;
- rc = mcs7830_write_phy(dev, MII_ADVERTISE, adv);
+ rc = mcs7830_write_phy(udev, MII_ADVERTISE, adv);
flg = 0;
if (!rc)
- rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+ rc = mcs7830_write_phy(udev, MII_BMCR, flg);
flg |= BMCR_ANENABLE;
if (!rc)
- rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+ rc = mcs7830_write_phy(udev, MII_BMCR, flg);
flg |= BMCR_ANRESTART;
if (!rc)
- rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+ rc = mcs7830_write_phy(udev, MII_BMCR, flg);
return rc;
}
/*
* mcs7830_get_rev() - identify a network adapter's chip revision
- * @eth: network device to identify
+ * @udev: network device to identify
* Return: non-negative number, reflecting the revision number
*
* currently, only "rev C and higher" and "below rev C" are needed, so
* the return value is #1 for "below rev C", and #2 for "rev C and above"
*/
-static int mcs7830_get_rev(struct ueth_data *dev)
+static int mcs7830_get_rev(struct usb_device *udev)
{
uint8_t buf[2];
int rc;
int rev;
/* register 22 is readable in rev C and higher */
- rc = mcs7830_read_reg(dev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf);
+ rc = mcs7830_read_reg(udev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf);
if (rc < 0)
rev = 1;
else
@@ -353,19 +359,19 @@
/*
* mcs7830_apply_fixup() - identify an adapter and potentially apply fixups
- * @eth: network device to identify and apply fixups to
+ * @udev: network device to identify and apply fixups to
* Return: zero upon success (no errors emitted from here)
*
* this routine identifies the network adapter's chip revision, and applies
* fixups for known issues
*/
-static int mcs7830_apply_fixup(struct ueth_data *dev)
+static int mcs7830_apply_fixup(struct usb_device *udev)
{
int rev;
int i;
uint8_t thr;
- rev = mcs7830_get_rev(dev);
+ rev = mcs7830_get_rev(udev);
debug("%s() rev=%d\n", __func__, rev);
/*
@@ -374,10 +380,10 @@
* exactly", the introductory comment says "rev C and above")
*/
if (rev == 2) {
- debug("%s: applying rev C fixup\n", dev->eth_dev.name);
+ debug("%s: applying rev C fixup\n", __func__);
thr = PAUSE_THRESHOLD_DEFAULT;
for (i = 0; i < 2; i++) {
- (void)mcs7830_write_reg(dev, REG_PAUSE_THRESHOLD,
+ (void)mcs7830_write_reg(udev, REG_PAUSE_THRESHOLD,
sizeof(thr), &thr);
mdelay(1);
}
@@ -395,13 +401,12 @@
* of the interface callbacks can exchange ethernet frames; link negotiation is
* triggered from here already and continues in background
*/
-static int mcs7830_basic_reset(struct ueth_data *dev)
+static int mcs7830_basic_reset(struct usb_device *udev,
+ struct mcs7830_private *priv)
{
- struct mcs7830_private *priv;
int rc;
debug("%s()\n", __func__);
- priv = dev->dev_priv;
/*
* comment from the respective Linux driver, which
@@ -411,25 +416,25 @@
priv->config = CONF_TXENABLE;
priv->config |= CONF_ALLMULTICAST;
- rc = mcs7830_set_autoneg(dev);
+ rc = mcs7830_set_autoneg(udev);
if (rc < 0) {
error("setting autoneg failed\n");
return rc;
}
- rc = mcs7830_write_mchash(dev);
+ rc = mcs7830_write_mchash(udev, priv);
if (rc < 0) {
error("failed to set multicast hash\n");
return rc;
}
- rc = mcs7830_write_config(dev);
+ rc = mcs7830_write_config(udev, priv);
if (rc < 0) {
error("failed to set configuration\n");
return rc;
}
- rc = mcs7830_apply_fixup(dev);
+ rc = mcs7830_apply_fixup(udev);
if (rc < 0) {
error("fixup application failed\n");
return rc;
@@ -440,51 +445,38 @@
/*
* mcs7830_read_mac() - read an ethernet adapter's MAC address
- * @eth: network device to read from
+ * @udev: network device to read from
+ * @enetaddr: place to put ethernet MAC address
* Return: zero upon success, negative upon error
*
* this routine fetches the MAC address stored within the ethernet adapter,
* and stores it in the ethernet interface's data structure
*/
-static int mcs7830_read_mac(struct eth_device *eth)
+static int mcs7830_read_mac(struct usb_device *udev, unsigned char enetaddr[])
{
- struct ueth_data *dev;
int rc;
uint8_t buf[ETH_ALEN];
debug("%s()\n", __func__);
- dev = eth->priv;
- rc = mcs7830_read_reg(dev, REG_ETHER_ADDR, ETH_ALEN, buf);
+ rc = mcs7830_read_reg(udev, REG_ETHER_ADDR, ETH_ALEN, buf);
if (rc < 0) {
debug("reading MAC from adapter failed\n");
return rc;
}
- memcpy(ð->enetaddr[0], buf, ETH_ALEN);
+ memcpy(enetaddr, buf, ETH_ALEN);
return 0;
}
-/*
- * mcs7830_write_mac() - write an ethernet adapter's MAC address
- * @eth: network device to write to
- * Return: zero upon success, negative upon error
- *
- * this routine takes the MAC address from the ethernet interface's data
- * structure, and writes it into the ethernet adapter such that subsequent
- * exchange of ethernet frames uses this address
- */
-static int mcs7830_write_mac(struct eth_device *eth)
+static int mcs7830_write_mac_common(struct usb_device *udev,
+ unsigned char enetaddr[])
{
- struct ueth_data *dev;
int rc;
debug("%s()\n", __func__);
- dev = eth->priv;
- if (sizeof(eth->enetaddr) != ETH_ALEN)
- return -EINVAL;
- rc = mcs7830_write_reg(dev, REG_ETHER_ADDR, ETH_ALEN, eth->enetaddr);
+ rc = mcs7830_write_reg(udev, REG_ETHER_ADDR, ETH_ALEN, enetaddr);
if (rc < 0) {
debug("writing MAC to adapter failed\n");
return rc;
@@ -492,28 +484,16 @@
return 0;
}
-/*
- * mcs7830_init() - network interface's init callback
- * @eth: network device to initialize
- * @bd: board information
- * Return: zero upon success, negative upon error
- *
- * after initial setup during probe() and get_info(), this init() callback
- * ensures that the link is up and subsequent send() and recv() calls can
- * exchange ethernet frames
- */
-static int mcs7830_init(struct eth_device *eth, bd_t *bd)
+static int mcs7830_init_common(struct usb_device *udev)
{
- struct ueth_data *dev;
int timeout;
int have_link;
debug("%s()\n", __func__);
- dev = eth->priv;
timeout = 0;
do {
- have_link = mcs7830_read_phy(dev, MII_BMSR) & BMSR_LSTATUS;
+ have_link = mcs7830_read_phy(udev, MII_BMSR) & BMSR_LSTATUS;
if (have_link)
break;
udelay(LINKSTATUS_TIMEOUT_RES * 1000);
@@ -526,28 +506,18 @@
return 0;
}
-/*
- * mcs7830_send() - network interface's send callback
- * @eth: network device to send the frame from
- * @packet: ethernet frame content
- * @length: ethernet frame length
- * Return: zero upon success, negative upon error
- *
- * this routine send an ethernet frame out of the network interface
- */
-static int mcs7830_send(struct eth_device *eth, void *packet, int length)
+static int mcs7830_send_common(struct ueth_data *ueth, void *packet,
+ int length)
{
- struct ueth_data *dev;
+ struct usb_device *udev = ueth->pusb_dev;
int rc;
int gotlen;
/* there is a status byte after the ethernet frame */
ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, PKTSIZE + sizeof(uint8_t));
- dev = eth->priv;
-
memcpy(buf, packet, length);
- rc = usb_bulk_msg(dev->pusb_dev,
- usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
+ rc = usb_bulk_msg(udev,
+ usb_sndbulkpipe(udev, ueth->ep_out),
&buf[0], length, &gotlen,
USBCALL_TIMEOUT);
debug("%s() TX want len %d, got len %d, rc %d\n",
@@ -555,28 +525,17 @@
return rc;
}
-/*
- * mcs7830_recv() - network interface's recv callback
- * @eth: network device to receive frames from
- * Return: zero upon success, negative upon error
- *
- * this routine checks for available ethernet frames that the network
- * interface might have received, and notifies the network stack
- */
-static int mcs7830_recv(struct eth_device *eth)
+static int mcs7830_recv_common(struct ueth_data *ueth, uint8_t *buf)
{
- struct ueth_data *dev;
- ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
int rc, wantlen, gotlen;
uint8_t sts;
debug("%s()\n", __func__);
- dev = eth->priv;
/* fetch input data from the adapter */
wantlen = MCS7830_RX_URB_SIZE;
- rc = usb_bulk_msg(dev->pusb_dev,
- usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
+ rc = usb_bulk_msg(ueth->pusb_dev,
+ usb_rcvbulkpipe(ueth->pusb_dev, ueth->ep_in),
&buf[0], wantlen, &gotlen,
USBCALL_TIMEOUT);
debug("%s() RX want len %d, got len %d, rc %d\n",
@@ -601,8 +560,7 @@
if (sts == STAT_RX_FRAME_CORRECT) {
debug("%s() got a frame, len=%d\n", __func__, gotlen);
- net_process_received_packet(buf, gotlen);
- return 0;
+ return gotlen;
}
debug("RX: frame error (sts 0x%02X, %s %s %s %s %s)\n",
@@ -615,7 +573,62 @@
return -EIO;
}
+#ifndef CONFIG_DM_ETH
+/*
+ * mcs7830_init() - network interface's init callback
+ * @udev: network device to initialize
+ * @bd: board information
+ * Return: zero upon success, negative upon error
+ *
+ * after initial setup during probe() and get_info(), this init() callback
+ * ensures that the link is up and subsequent send() and recv() calls can
+ * exchange ethernet frames
+ */
+static int mcs7830_init(struct eth_device *eth, bd_t *bd)
+{
+ struct ueth_data *dev = eth->priv;
+
+ return mcs7830_init_common(dev->pusb_dev);
+}
+
+/*
+ * mcs7830_send() - network interface's send callback
+ * @eth: network device to send the frame from
+ * @packet: ethernet frame content
+ * @length: ethernet frame length
+ * Return: zero upon success, negative upon error
+ *
+ * this routine send an ethernet frame out of the network interface
+ */
+static int mcs7830_send(struct eth_device *eth, void *packet, int length)
+{
+ struct ueth_data *dev = eth->priv;
+
+ return mcs7830_send_common(dev, packet, length);
+}
+
/*
+ * mcs7830_recv() - network interface's recv callback
+ * @eth: network device to receive frames from
+ * Return: zero upon success, negative upon error
+ *
+ * this routine checks for available ethernet frames that the network
+ * interface might have received, and notifies the network stack
+ */
+static int mcs7830_recv(struct eth_device *eth)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
+ struct ueth_data *ueth = eth->priv;
+ int len;
+
+ len = mcs7830_recv_common(ueth, buf);
+ if (len <= 0)
+ net_process_received_packet(buf, len);
+
+ return 0;
+}
+
+/*
* mcs7830_halt() - network interface's halt callback
* @eth: network device to cease operation of
* Return: none
@@ -629,6 +642,22 @@
}
/*
+ * mcs7830_write_mac() - write an ethernet adapter's MAC address
+ * @eth: network device to write to
+ * Return: zero upon success, negative upon error
+ *
+ * this routine takes the MAC address from the ethernet interface's data
+ * structure, and writes it into the ethernet adapter such that subsequent
+ * exchange of ethernet frames uses this address
+ */
+static int mcs7830_write_mac(struct eth_device *eth)
+{
+ struct ueth_data *ueth = eth->priv;
+
+ return mcs7830_write_mac_common(ueth->pusb_dev, eth->enetaddr);
+}
+
+/*
* mcs7830_iface_idx - index of detected network interfaces
*
* this counter keeps track of identified supported interfaces,
@@ -802,12 +831,111 @@
eth->write_hwaddr = mcs7830_write_mac;
eth->priv = ss;
- if (mcs7830_basic_reset(ss))
+ if (mcs7830_basic_reset(ss->pusb_dev, ss->dev_priv))
return 0;
- if (mcs7830_read_mac(eth))
+ if (mcs7830_read_mac(ss->pusb_dev, eth->enetaddr))
return 0;
debug("MAC %pM\n", eth->enetaddr);
return 1;
}
+#endif
+
+
+#ifdef CONFIG_DM_ETH
+static int mcs7830_eth_start(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+
+ return mcs7830_init_common(udev);
+}
+
+void mcs7830_eth_stop(struct udevice *dev)
+{
+ debug("** %s()\n", __func__);
+}
+
+int mcs7830_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct mcs7830_private *priv = dev_get_priv(dev);
+ struct ueth_data *ueth = &priv->ueth;
+
+ return mcs7830_send_common(ueth, packet, length);
+}
+
+int mcs7830_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct mcs7830_private *priv = dev_get_priv(dev);
+ struct ueth_data *ueth = &priv->ueth;
+ int len;
+
+ len = mcs7830_recv_common(ueth, priv->rx_buf);
+ *packetp = priv->rx_buf;
+
+ return len;
+}
+
+static int mcs7830_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
+{
+ struct mcs7830_private *priv = dev_get_priv(dev);
+
+ packet_len = ALIGN(packet_len, 4);
+ usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
+
+ return 0;
+}
+
+int mcs7830_write_hwaddr(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ return mcs7830_write_mac_common(udev, pdata->enetaddr);
+}
+
+static int mcs7830_eth_probe(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ struct mcs7830_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ueth_data *ueth = &priv->ueth;
+
+ if (mcs7830_basic_reset(udev, priv))
+ return 0;
+
+ if (mcs7830_read_mac(udev, pdata->enetaddr))
+ return 0;
+
+ return usb_ether_register(dev, ueth, MCS7830_RX_URB_SIZE);
+}
+
+static const struct eth_ops mcs7830_eth_ops = {
+ .start = mcs7830_eth_start,
+ .send = mcs7830_eth_send,
+ .recv = mcs7830_eth_recv,
+ .free_pkt = mcs7830_free_pkt,
+ .stop = mcs7830_eth_stop,
+ .write_hwaddr = mcs7830_write_hwaddr,
+};
+
+U_BOOT_DRIVER(mcs7830_eth) = {
+ .name = "mcs7830_eth",
+ .id = UCLASS_ETH,
+ .probe = mcs7830_eth_probe,
+ .ops = &mcs7830_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct mcs7830_private),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static const struct usb_device_id mcs7830_eth_id_table[] = {
+ { USB_DEVICE(0x9710, 0x7832) }, /* Moschip 7832 */
+ { USB_DEVICE(0x9710, 0x7830), }, /* Moschip 7830 */
+ { USB_DEVICE(0x9710, 0x7730), }, /* Moschip 7730 */
+ { USB_DEVICE(0x0df6, 0x0021), }, /* Sitecom LN 30 */
+ { } /* Terminating entry */
+};
+
+U_BOOT_USB_DEVICE(mcs7830_eth, mcs7830_eth_id_table);
+#endif
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 6288ecf..c915c79 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -13,8 +13,8 @@
obj-$(CONFIG_USB_GADGET_AT91) += at91_udc.o
obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o
-obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
-obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o
+obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o
+obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
obj-$(CONFIG_CI_UDC) += ci_udc.o
obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o
diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h
index 3d8752e..240bc14 100644
--- a/drivers/usb/gadget/at91_udc.h
+++ b/drivers/usb/gadget/at91_udc.h
@@ -3,10 +3,7 @@
* Copyright (C) 2005 by Ivan Kokshaysky
* Copyright (C) 2006 by SAN People
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef AT91_UDC_H
diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c b/drivers/usb/gadget/bcm_udc_otg_phy.c
index f8690b0..10b2e13 100644
--- a/drivers/usb/gadget/bcm_udc_otg_phy.c
+++ b/drivers/usb/gadget/bcm_udc_otg_phy.c
@@ -9,10 +9,10 @@
#include <asm/io.h>
#include <asm/arch/sysmap.h>
-#include <usb/s3c_udc.h>
+#include "dwc2_udc_otg_priv.h"
#include "bcm_udc_otg.h"
-void otg_phy_init(struct s3c_udc *dev)
+void otg_phy_init(struct dwc2_udc *dev)
{
/* set Phy to driving mode */
wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
@@ -37,7 +37,7 @@
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
}
-void otg_phy_off(struct s3c_udc *dev)
+void otg_phy_off(struct dwc2_udc *dev)
{
/* Soft Disconnect */
wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 1ba5054..d36bcf6 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -1018,18 +1018,10 @@
return ret;
ret = ci_udc_probe();
-#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS)
- /*
- * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all
- * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection
- */
- if (!ret) {
- struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
-
- /* select ULPI phy */
- writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
+ if (ret) {
+ DBG("udc probe failed, returned %d\n", ret);
+ return ret;
}
-#endif
ret = driver->bind(&controller.gadget);
if (ret) {
diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
similarity index 77%
rename from drivers/usb/gadget/s3c_udc_otg.c
rename to drivers/usb/gadget/dwc2_udc_otg.c
index 7a2d1e7..ffe2952 100644
--- a/drivers/usb/gadget/s3c_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -1,6 +1,6 @@
/*
- * drivers/usb/gadget/s3c_udc_otg.c
- * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
+ * drivers/usb/gadget/dwc2_udc_otg.c
+ * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
*
* Copyright (C) 2008 for Samsung Electronics
*
@@ -32,7 +32,8 @@
#include <asm/mach-types.h>
-#include "regs-otg.h"
+#include "dwc2_udc_otg_regs.h"
+#include "dwc2_udc_otg_priv.h"
#include <usb/lin_gadget_compat.h>
/***********************************************************/
@@ -45,7 +46,7 @@
#define DEBUG_OUT_EP 0
#define DEBUG_IN_EP 0
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
#define EP0_CON 0
#define EP_MASK 0xF
@@ -62,12 +63,12 @@
"WAIT_FOR_NULL_COMPLETE",
};
-#define DRIVER_DESC "S3C HS USB OTG Device Driver, (c) Samsung Electronics"
+#define DRIVER_DESC "DWC2 HS USB OTG Device Driver, (c) Samsung Electronics"
#define DRIVER_VERSION "15 March 2009"
-struct s3c_udc *the_controller;
+struct dwc2_udc *the_controller;
-static const char driver_name[] = "s3c-udc";
+static const char driver_name[] = "dwc2-udc";
static const char driver_desc[] = DRIVER_DESC;
static const char ep0name[] = "ep0-control";
@@ -83,32 +84,32 @@
/*
Local declarations.
*/
-static int s3c_ep_enable(struct usb_ep *ep,
+static int dwc2_ep_enable(struct usb_ep *ep,
const struct usb_endpoint_descriptor *);
-static int s3c_ep_disable(struct usb_ep *ep);
-static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
+static int dwc2_ep_disable(struct usb_ep *ep);
+static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
gfp_t gfp_flags);
-static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
+static void dwc2_free_request(struct usb_ep *ep, struct usb_request *);
-static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
-static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
-static int s3c_fifo_status(struct usb_ep *ep);
-static void s3c_fifo_flush(struct usb_ep *ep);
-static void s3c_ep0_read(struct s3c_udc *dev);
-static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
-static void s3c_handle_ep0(struct s3c_udc *dev);
-static int s3c_ep0_write(struct s3c_udc *dev);
-static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req);
-static void done(struct s3c_ep *ep, struct s3c_request *req, int status);
-static void stop_activity(struct s3c_udc *dev,
+static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
+static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *);
+static int dwc2_fifo_status(struct usb_ep *ep);
+static void dwc2_fifo_flush(struct usb_ep *ep);
+static void dwc2_ep0_read(struct dwc2_udc *dev);
+static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep);
+static void dwc2_handle_ep0(struct dwc2_udc *dev);
+static int dwc2_ep0_write(struct dwc2_udc *dev);
+static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req);
+static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status);
+static void stop_activity(struct dwc2_udc *dev,
struct usb_gadget_driver *driver);
-static int udc_enable(struct s3c_udc *dev);
-static void udc_set_address(struct s3c_udc *dev, unsigned char address);
-static void reconfig_usbd(struct s3c_udc *dev);
-static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
-static void nuke(struct s3c_ep *ep, int status);
-static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
-static void s3c_udc_set_nak(struct s3c_ep *ep);
+static int udc_enable(struct dwc2_udc *dev);
+static void udc_set_address(struct dwc2_udc *dev, unsigned char address);
+static void reconfig_usbd(struct dwc2_udc *dev);
+static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed);
+static void nuke(struct dwc2_ep *ep, int status);
+static int dwc2_udc_set_halt(struct usb_ep *_ep, int value);
+static void dwc2_udc_set_nak(struct dwc2_ep *ep);
void set_udc_gadget_private_data(void *p)
{
@@ -123,19 +124,19 @@
return gadget->dev.device_data;
}
-static struct usb_ep_ops s3c_ep_ops = {
- .enable = s3c_ep_enable,
- .disable = s3c_ep_disable,
+static struct usb_ep_ops dwc2_ep_ops = {
+ .enable = dwc2_ep_enable,
+ .disable = dwc2_ep_disable,
- .alloc_request = s3c_alloc_request,
- .free_request = s3c_free_request,
+ .alloc_request = dwc2_alloc_request,
+ .free_request = dwc2_free_request,
- .queue = s3c_queue,
- .dequeue = s3c_dequeue,
+ .queue = dwc2_queue,
+ .dequeue = dwc2_dequeue,
- .set_halt = s3c_udc_set_halt,
- .fifo_status = s3c_fifo_status,
- .fifo_flush = s3c_fifo_flush,
+ .set_halt = dwc2_udc_set_halt,
+ .fifo_status = dwc2_fifo_status,
+ .fifo_flush = dwc2_fifo_flush,
};
#define create_proc_files() do {} while (0)
@@ -144,24 +145,24 @@
/***********************************************************/
void __iomem *regs_otg;
-struct s3c_usbotg_reg *reg;
+struct dwc2_usbotg_reg *reg;
bool dfu_usb_get_reset(void)
{
return !!(readl(®->gintsts) & INT_RESET);
}
-__weak void otg_phy_init(struct s3c_udc *dev) {}
-__weak void otg_phy_off(struct s3c_udc *dev) {}
+__weak void otg_phy_init(struct dwc2_udc *dev) {}
+__weak void otg_phy_off(struct dwc2_udc *dev) {}
/***********************************************************/
-#include "s3c_udc_otg_xfer_dma.c"
+#include "dwc2_udc_otg_xfer_dma.c"
/*
* udc_disable - disable USB device controller
*/
-static void udc_disable(struct s3c_udc *dev)
+static void udc_disable(struct dwc2_udc *dev)
{
debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
@@ -177,7 +178,7 @@
/*
* udc_reinit - initialize software state
*/
-static void udc_reinit(struct s3c_udc *dev)
+static void udc_reinit(struct dwc2_udc *dev)
{
unsigned int i;
@@ -189,8 +190,8 @@
dev->ep0state = WAIT_FOR_SETUP;
/* basic endpoint records init */
- for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
- struct s3c_ep *ep = &dev->ep[i];
+ for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
+ struct dwc2_ep *ep = &dev->ep[i];
if (i != 0)
list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
@@ -210,7 +211,7 @@
/* until it's enabled, this UDC should be completely invisible
* to any USB host.
*/
-static int udc_enable(struct s3c_udc *dev)
+static int udc_enable(struct dwc2_udc *dev)
{
debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
@@ -218,7 +219,7 @@
reconfig_usbd(dev);
debug_cond(DEBUG_SETUP != 0,
- "S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
+ "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n",
readl(®->gintmsk));
dev->gadget.speed = USB_SPEED_UNKNOWN;
@@ -231,7 +232,7 @@
*/
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
{
- struct s3c_udc *dev = the_controller;
+ struct dwc2_udc *dev = the_controller;
int retval = 0;
unsigned long flags = 0;
@@ -280,7 +281,7 @@
*/
int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
{
- struct s3c_udc *dev = the_controller;
+ struct dwc2_udc *dev = the_controller;
unsigned long flags = 0;
if (!dev)
@@ -304,7 +305,7 @@
/*
* done - retire a request; caller blocked irqs
*/
-static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
+static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status)
{
unsigned int stopped = ep->stopped;
@@ -355,20 +356,20 @@
/*
* nuke - dequeue ALL requests
*/
-static void nuke(struct s3c_ep *ep, int status)
+static void nuke(struct dwc2_ep *ep, int status)
{
- struct s3c_request *req;
+ struct dwc2_request *req;
debug("%s: %s %p\n", __func__, ep->ep.name, ep);
/* called with irqs blocked */
while (!list_empty(&ep->queue)) {
- req = list_entry(ep->queue.next, struct s3c_request, queue);
+ req = list_entry(ep->queue.next, struct dwc2_request, queue);
done(ep, req, status);
}
}
-static void stop_activity(struct s3c_udc *dev,
+static void stop_activity(struct dwc2_udc *dev,
struct usb_gadget_driver *driver)
{
int i;
@@ -379,8 +380,8 @@
dev->gadget.speed = USB_SPEED_UNKNOWN;
/* prevent new request submissions, kill any outstanding requests */
- for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
- struct s3c_ep *ep = &dev->ep[i];
+ for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
+ struct dwc2_ep *ep = &dev->ep[i];
ep->stopped = 1;
nuke(ep, -ESHUTDOWN);
}
@@ -396,7 +397,7 @@
udc_reinit(dev);
}
-static void reconfig_usbd(struct s3c_udc *dev)
+static void reconfig_usbd(struct dwc2_udc *dev)
{
/* 2. Soft-reset OTG Core and then unreset again. */
int i;
@@ -447,7 +448,7 @@
writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[EP0_CON].doepctl);
writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[EP0_CON].diepctl);
- for (i = 1; i < S3C_MAX_ENDPOINTS; i++) {
+ for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) {
writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[i].doepctl);
writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[i].diepctl);
}
@@ -469,7 +470,7 @@
writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
®->gnptxfsiz);
- for (i = 1; i < S3C_MAX_HW_ENDPOINTS; i++)
+ for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
writel((PTX_FIFO_SIZE >> 2) << 16 |
((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
@@ -478,13 +479,13 @@
/* Flush the RX FIFO */
writel(RX_FIFO_FLUSH, ®->grstctl);
while (readl(®->grstctl) & RX_FIFO_FLUSH)
- debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
+ debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
/* Flush all the Tx FIFO's */
writel(TX_FIFO_FLUSH_ALL, ®->grstctl);
writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, ®->grstctl);
while (readl(®->grstctl) & TX_FIFO_FLUSH)
- debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
+ debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
/* 13. Clear NAK bit of EP0, EP1, EP2*/
/* For Slave mode*/
@@ -496,7 +497,7 @@
writel(GAHBCFG_INIT, ®->gahbcfg);
}
-static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed)
+static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed)
{
unsigned int ep_ctrl;
int i;
@@ -514,7 +515,7 @@
}
dev->ep[0].ep.maxpacket = ep0_fifo_size;
- for (i = 1; i < S3C_MAX_ENDPOINTS; i++)
+ for (i = 1; i < DWC2_MAX_ENDPOINTS; i++)
dev->ep[i].ep.maxpacket = ep_fifo_size;
/* EP0 - Control IN (64 bytes)*/
@@ -526,16 +527,16 @@
writel(ep_ctrl|(0<<0), ®->out_endp[EP0_CON].doepctl);
}
-static int s3c_ep_enable(struct usb_ep *_ep,
+static int dwc2_ep_enable(struct usb_ep *_ep,
const struct usb_endpoint_descriptor *desc)
{
- struct s3c_ep *ep;
- struct s3c_udc *dev;
+ struct dwc2_ep *ep;
+ struct dwc2_udc *dev;
unsigned long flags = 0;
debug("%s: %p\n", __func__, _ep);
- ep = container_of(_ep, struct s3c_ep, ep);
+ ep = container_of(_ep, struct dwc2_ep, ep);
if (!_ep || !desc || ep->desc || _ep->name == ep0name
|| desc->bDescriptorType != USB_DT_ENDPOINT
|| ep->bEndpointAddress != desc->bEndpointAddress
@@ -577,11 +578,11 @@
ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
/* Reset halt state */
- s3c_udc_set_nak(ep);
- s3c_udc_set_halt(_ep, 0);
+ dwc2_udc_set_nak(ep);
+ dwc2_udc_set_halt(_ep, 0);
spin_lock_irqsave(&ep->dev->lock, flags);
- s3c_udc_ep_activate(ep);
+ dwc2_udc_ep_activate(ep);
spin_unlock_irqrestore(&ep->dev->lock, flags);
debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
@@ -592,14 +593,14 @@
/*
* Disable EP
*/
-static int s3c_ep_disable(struct usb_ep *_ep)
+static int dwc2_ep_disable(struct usb_ep *_ep)
{
- struct s3c_ep *ep;
+ struct dwc2_ep *ep;
unsigned long flags = 0;
debug("%s: %p\n", __func__, _ep);
- ep = container_of(_ep, struct s3c_ep, ep);
+ ep = container_of(_ep, struct dwc2_ep, ep);
if (!_ep || !ep->desc) {
debug("%s: %s not enabled\n", __func__,
_ep ? ep->ep.name : NULL);
@@ -620,10 +621,10 @@
return 0;
}
-static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
+static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
gfp_t gfp_flags)
{
- struct s3c_request *req;
+ struct dwc2_request *req;
debug("%s: %s %p\n", __func__, ep->name, ep);
@@ -637,27 +638,27 @@
return &req->req;
}
-static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
+static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req)
{
- struct s3c_request *req;
+ struct dwc2_request *req;
debug("%s: %p\n", __func__, ep);
- req = container_of(_req, struct s3c_request, req);
+ req = container_of(_req, struct dwc2_request, req);
WARN_ON(!list_empty(&req->queue));
kfree(req);
}
/* dequeue JUST ONE request */
-static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req)
{
- struct s3c_ep *ep;
- struct s3c_request *req;
+ struct dwc2_ep *ep;
+ struct dwc2_request *req;
unsigned long flags = 0;
debug("%s: %p\n", __func__, _ep);
- ep = container_of(_ep, struct s3c_ep, ep);
+ ep = container_of(_ep, struct dwc2_ep, ep);
if (!_ep || ep->ep.name == ep0name)
return -EINVAL;
@@ -682,12 +683,12 @@
/*
* Return bytes in EP FIFO
*/
-static int s3c_fifo_status(struct usb_ep *_ep)
+static int dwc2_fifo_status(struct usb_ep *_ep)
{
int count = 0;
- struct s3c_ep *ep;
+ struct dwc2_ep *ep;
- ep = container_of(_ep, struct s3c_ep, ep);
+ ep = container_of(_ep, struct dwc2_ep, ep);
if (!_ep) {
debug("%s: bad ep\n", __func__);
return -ENODEV;
@@ -705,11 +706,11 @@
/*
* Flush EP FIFO
*/
-static void s3c_fifo_flush(struct usb_ep *_ep)
+static void dwc2_fifo_flush(struct usb_ep *_ep)
{
- struct s3c_ep *ep;
+ struct dwc2_ep *ep;
- ep = container_of(_ep, struct s3c_ep, ep);
+ ep = container_of(_ep, struct dwc2_ep, ep);
if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
debug("%s: bad ep\n", __func__);
return;
@@ -718,14 +719,14 @@
debug("%s: %d\n", __func__, ep_index(ep));
}
-static const struct usb_gadget_ops s3c_udc_ops = {
+static const struct usb_gadget_ops dwc2_udc_ops = {
/* current versions must always be self-powered */
};
-static struct s3c_udc memory = {
+static struct dwc2_udc memory = {
.usb_address = 0,
.gadget = {
- .ops = &s3c_udc_ops,
+ .ops = &dwc2_udc_ops,
.ep0 = &memory.ep[0].ep,
.name = driver_name,
},
@@ -734,7 +735,7 @@
.ep[0] = {
.ep = {
.name = ep0name,
- .ops = &s3c_ep_ops,
+ .ops = &dwc2_ep_ops,
.maxpacket = EP0_FIFO_SIZE,
},
.dev = &memory,
@@ -749,7 +750,7 @@
.ep[1] = {
.ep = {
.name = "ep1in-bulk",
- .ops = &s3c_ep_ops,
+ .ops = &dwc2_ep_ops,
.maxpacket = EP_FIFO_SIZE,
},
.dev = &memory,
@@ -764,7 +765,7 @@
.ep[2] = {
.ep = {
.name = "ep2out-bulk",
- .ops = &s3c_ep_ops,
+ .ops = &dwc2_ep_ops,
.maxpacket = EP_FIFO_SIZE,
},
.dev = &memory,
@@ -779,7 +780,7 @@
.ep[3] = {
.ep = {
.name = "ep3in-int",
- .ops = &s3c_ep_ops,
+ .ops = &dwc2_ep_ops,
.maxpacket = EP_FIFO_SIZE,
},
.dev = &memory,
@@ -796,16 +797,16 @@
* probe - binds to the platform device
*/
-int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
+int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata)
{
- struct s3c_udc *dev = &memory;
+ struct dwc2_udc *dev = &memory;
int retval = 0;
debug("%s: %p\n", __func__, pdata);
dev->pdata = pdata;
- reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
+ reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
/* regs_otg = (void *)pdata->regs_otg; */
@@ -839,6 +840,6 @@
u32 gintmsk = readl(®->gintmsk);
if (intr_status & gintmsk)
- return s3c_udc_irq(1, (void *)the_controller);
+ return dwc2_udc_irq(1, (void *)the_controller);
return 0;
}
diff --git a/drivers/usb/gadget/s3c_udc_otg_phy.c b/drivers/usb/gadget/dwc2_udc_otg_phy.c
similarity index 83%
rename from drivers/usb/gadget/s3c_udc_otg_phy.c
rename to drivers/usb/gadget/dwc2_udc_otg_phy.c
index f13cb89..e0cbbc0 100644
--- a/drivers/usb/gadget/s3c_udc_otg_phy.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_phy.c
@@ -1,6 +1,6 @@
/*
- * drivers/usb/gadget/s3c_udc_otg.c
- * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
+ * drivers/usb/gadget/dwc2_udc_otg.c
+ * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
*
* Copyright (C) 2008 for Samsung Electronics
*
@@ -32,16 +32,17 @@
#include <asm/mach-types.h>
-#include "regs-otg.h"
+#include "dwc2_udc_otg_regs.h"
+#include "dwc2_udc_otg_priv.h"
#include <usb/lin_gadget_compat.h>
-#include <usb/s3c_udc.h>
+#include <usb/dwc2_udc.h>
-void otg_phy_init(struct s3c_udc *dev)
+void otg_phy_init(struct dwc2_udc *dev)
{
unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
- struct s3c_usbotg_phy *phy =
- (struct s3c_usbotg_phy *)dev->pdata->regs_phy;
+ struct dwc2_usbotg_phy *phy =
+ (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
dev->pdata->phy_control(1);
@@ -75,11 +76,11 @@
udelay(10);
}
-void otg_phy_off(struct s3c_udc *dev)
+void otg_phy_off(struct dwc2_udc *dev)
{
unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
- struct s3c_usbotg_phy *phy =
- (struct s3c_usbotg_phy *)dev->pdata->regs_phy;
+ struct dwc2_usbotg_phy *phy =
+ (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
/* reset controller just in case */
writel(PHY_SW_RST0, &phy->rstcon);
diff --git a/include/usb/s3c_udc.h b/drivers/usb/gadget/dwc2_udc_otg_priv.h
similarity index 67%
rename from include/usb/s3c_udc.h
rename to drivers/usb/gadget/dwc2_udc_otg_priv.h
index 7f49a4e..b2c1fc4 100644
--- a/include/usb/s3c_udc.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_priv.h
@@ -1,13 +1,12 @@
/*
- * drivers/usb/gadget/s3c_udc.h
- * Samsung S3C on-chip full/high speed USB device controllers
+ * Designware DWC2 on-chip full/high speed USB device controllers
* Copyright (C) 2005 for Samsung Electronics
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __S3C_USB_GADGET
-#define __S3C_USB_GADGET
+#ifndef __DWC2_UDC_OTG_PRIV__
+#define __DWC2_UDC_OTG_PRIV__
#include <asm/errno.h>
#include <linux/sizes.h>
@@ -15,8 +14,7 @@
#include <linux/usb/gadget.h>
#include <linux/list.h>
#include <usb/lin_gadget_compat.h>
-
-#define PHY0_SLEEP (1 << 5)
+#include <usb/dwc2_udc.h>
/*-------------------------------------------------------------------------*/
/* DMA bounce buffer size, 16K is enough even for mass storage */
@@ -26,8 +24,8 @@
#define EP_FIFO_SIZE 512
#define EP_FIFO_SIZE2 1024
/* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */
-#define S3C_MAX_ENDPOINTS 4
-#define S3C_MAX_HW_ENDPOINTS 16
+#define DWC2_MAX_ENDPOINTS 4
+#define DWC2_MAX_HW_ENDPOINTS 16
#define WAIT_FOR_SETUP 0
#define DATA_STATE_XMIT 1
@@ -53,9 +51,9 @@
ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
};
-struct s3c_ep {
+struct dwc2_ep {
struct usb_ep ep;
- struct s3c_udc *dev;
+ struct dwc2_udc *dev;
const struct usb_endpoint_descriptor *desc;
struct list_head queue;
@@ -71,43 +69,30 @@
int fifo_num;
};
-struct s3c_request {
+struct dwc2_request {
struct usb_request req;
struct list_head queue;
};
-struct s3c_udc {
+struct dwc2_udc {
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
- struct s3c_plat_otg_data *pdata;
+ struct dwc2_plat_otg_data *pdata;
int ep0state;
- struct s3c_ep ep[S3C_MAX_ENDPOINTS];
+ struct dwc2_ep ep[DWC2_MAX_ENDPOINTS];
unsigned char usb_address;
unsigned req_pending:1, req_std:1;
};
-extern struct s3c_udc *the_controller;
-
#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN) == USB_DIR_IN)
#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
-extern void otg_phy_init(struct s3c_udc *dev);
-extern void otg_phy_off(struct s3c_udc *dev);
+void otg_phy_init(struct dwc2_udc *dev);
+void otg_phy_off(struct dwc2_udc *dev);
-extern void s3c_udc_ep_set_stall(struct s3c_ep *ep);
-extern int s3c_udc_probe(struct s3c_plat_otg_data *pdata);
-
-struct s3c_plat_otg_data {
- int (*phy_control)(int on);
- unsigned int regs_phy;
- unsigned int regs_otg;
- unsigned int usb_phy_ctrl;
- unsigned int usb_flags;
- unsigned int usb_gusbcfg;
-};
-#endif
+#endif /* __DWC2_UDC_OTG_PRIV__ */
diff --git a/drivers/usb/gadget/regs-otg.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h
similarity index 92%
rename from drivers/usb/gadget/regs-otg.h
rename to drivers/usb/gadget/dwc2_udc_otg_regs.h
index ac5d112..78ec90e 100644
--- a/drivers/usb/gadget/regs-otg.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h
@@ -12,14 +12,14 @@
#define __ASM_ARCH_REGS_USB_OTG_HS_H
/* USB2.0 OTG Controller register */
-struct s3c_usbotg_phy {
+struct dwc2_usbotg_phy {
u32 phypwr;
u32 phyclk;
u32 rstcon;
};
/* Device Logical IN Endpoint-Specific Registers */
-struct s3c_dev_in_endp {
+struct dwc2_dev_in_endp {
u32 diepctl;
u8 res1[4];
u32 diepint;
@@ -31,7 +31,7 @@
};
/* Device Logical OUT Endpoint-Specific Registers */
-struct s3c_dev_out_endp {
+struct dwc2_dev_out_endp {
u32 doepctl;
u8 res1[4];
u32 doepint;
@@ -48,7 +48,7 @@
};
/* USB2.0 OTG Controller register */
-struct s3c_usbotg_reg {
+struct dwc2_usbotg_reg {
/* Core Global Registers */
u32 gotgctl; /* OTG Control & Status */
u32 gotgint; /* OTG Interrupt */
@@ -74,8 +74,8 @@
u32 daint; /* Device All Endpoints Interrupt */
u32 daintmsk; /* Device All Endpoints Interrupt Mask */
u8 res4[224];
- struct s3c_dev_in_endp in_endp[16];
- struct s3c_dev_out_endp out_endp[16];
+ struct dwc2_dev_in_endp in_endp[16];
+ struct dwc2_dev_out_endp out_endp[16];
u8 res5[768];
struct ep_fifo ep[16];
};
@@ -83,11 +83,11 @@
/*===================================================================== */
/*definitions related to CSR setting */
-/* S3C_UDC_OTG_GOTGCTL */
+/* DWC2_UDC_OTG_GOTGCTL */
#define B_SESSION_VALID (0x1<<19)
#define A_SESSION_VALID (0x1<<18)
-/* S3C_UDC_OTG_GAHBCFG */
+/* DWC2_UDC_OTG_GAHBCFG */
#define PTXFE_HALF (0<<8)
#define PTXFE_ZERO (1<<8)
#define NPTXFE_HALF (0<<7)
@@ -102,11 +102,11 @@
#define GBL_INT_UNMASK (1<<0)
#define GBL_INT_MASK (0<<0)
-/* S3C_UDC_OTG_GRSTCTL */
+/* DWC2_UDC_OTG_GRSTCTL */
#define AHB_MASTER_IDLE (1u<<31)
#define CORE_SOFT_RESET (0x1<<0)
-/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
+/* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
#define INT_RESUME (1u<<31)
#define INT_DISCONN (0x1<<29)
#define INT_CONN_ID_STS_CNG (0x1<<28)
@@ -146,22 +146,22 @@
#define USB_LOW_6MHZ (0x2<<1)
#define USB_FULL_48MHZ (0x3<<1)
-/* S3C_UDC_OTG_GRXSTSP STATUS */
+/* DWC2_UDC_OTG_GRXSTSP STATUS */
#define OUT_PKT_RECEIVED (0x2<<17)
#define OUT_TRANSFER_COMPLELTED (0x3<<17)
#define SETUP_TRANSACTION_COMPLETED (0x4<<17)
#define SETUP_PKT_RECEIVED (0x6<<17)
#define GLOBAL_OUT_NAK (0x1<<17)
-/* S3C_UDC_OTG_DCTL device control register */
+/* DWC2_UDC_OTG_DCTL device control register */
#define NORMAL_OPERATION (0x1<<0)
#define SOFT_DISCONNECT (0x1<<1)
-/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
+/* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */
#define DAINT_OUT_BIT (16)
#define DAINT_MASK (0xFFFF)
-/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device
+/* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device
control IN/OUT endpoint 0 control register */
#define DEPCTL_EPENA (0x1<<31)
#define DEPCTL_EPDIS (0x1<<30)
@@ -191,9 +191,9 @@
#define DIEPCTL0_NEXT_EP_BIT (11)
-/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
+/* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
common interrupt mask register */
-/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
+/* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
#define INTKNEPMIS (0x1<<5)
#define INTKN_TXFEMP (0x1<<4)
diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
similarity index 88%
rename from drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
rename to drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index 7e7a2c2..bce9c30 100644
--- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -1,6 +1,6 @@
/*
- * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
- * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
+ * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+ * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
*
* Copyright (C) 2009 for Samsung Electronics
*
@@ -25,7 +25,7 @@
#define GET_MAX_LUN_REQUEST 0xFE
#define BOT_RESET_REQUEST 0xFF
-static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
+static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
{
u32 ep_ctrl;
@@ -41,7 +41,7 @@
dev->ep0state = WAIT_FOR_IN_COMPLETE;
}
-void s3c_udc_pre_setup(void)
+static void dwc2_udc_pre_setup(void)
{
u32 ep_ctrl;
@@ -62,7 +62,7 @@
}
-static inline void s3c_ep0_complete_out(void)
+static inline void dwc2_ep0_complete_out(void)
{
u32 ep_ctrl;
@@ -90,7 +90,7 @@
}
-static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
+static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
{
u32 *buf, ctrl;
u32 length, pktcnt;
@@ -128,7 +128,7 @@
}
-int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
+static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
{
u32 *buf, ctrl = 0;
u32 length, pktcnt;
@@ -186,10 +186,10 @@
return length;
}
-static void complete_rx(struct s3c_udc *dev, u8 ep_num)
+static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
{
- struct s3c_ep *ep = &dev->ep[ep_num];
- struct s3c_request *req = NULL;
+ struct dwc2_ep *ep = &dev->ep[ep_num];
+ struct dwc2_request *req = NULL;
u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
if (list_empty(&ep->queue)) {
@@ -200,7 +200,7 @@
}
- req = list_entry(ep->queue.next, struct s3c_request, queue);
+ req = list_entry(ep->queue.next, struct dwc2_request, queue);
ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
if (ep_num == EP0_CON)
@@ -240,7 +240,7 @@
if (is_short || req->req.actual == req->req.length) {
if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
- s3c_udc_ep0_zlp(dev);
+ dwc2_udc_ep0_zlp(dev);
/* packet will be completed in complete_tx() */
dev->ep0state = WAIT_FOR_IN_COMPLETE;
} else {
@@ -248,7 +248,7 @@
if (!list_empty(&ep->queue)) {
req = list_entry(ep->queue.next,
- struct s3c_request, queue);
+ struct dwc2_request, queue);
debug_cond(DEBUG_OUT_EP != 0,
"%s: Next Rx request start...\n",
__func__);
@@ -259,16 +259,16 @@
setdma_rx(ep, req);
}
-static void complete_tx(struct s3c_udc *dev, u8 ep_num)
+static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
{
- struct s3c_ep *ep = &dev->ep[ep_num];
- struct s3c_request *req;
+ struct dwc2_ep *ep = &dev->ep[ep_num];
+ struct dwc2_request *req;
u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
u32 last;
if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
dev->ep0state = WAIT_FOR_OUT_COMPLETE;
- s3c_ep0_complete_out();
+ dwc2_ep0_complete_out();
return;
}
@@ -280,7 +280,7 @@
}
- req = list_entry(ep->queue.next, struct s3c_request, queue);
+ req = list_entry(ep->queue.next, struct dwc2_request, queue);
ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
@@ -315,7 +315,7 @@
__func__, ep_num);
done(ep, req, 0);
dev->ep0state = WAIT_FOR_OUT_COMPLETE;
- s3c_ep0_complete_out();
+ dwc2_ep0_complete_out();
} else {
debug_cond(DEBUG_IN_EP,
"%s: ep_num = %d, invalid ep state\n",
@@ -328,23 +328,23 @@
done(ep, req, 0);
if (!list_empty(&ep->queue)) {
- req = list_entry(ep->queue.next, struct s3c_request, queue);
+ req = list_entry(ep->queue.next, struct dwc2_request, queue);
debug_cond(DEBUG_IN_EP,
"%s: Next Tx request start...\n", __func__);
setdma_tx(ep, req);
}
}
-static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
+static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
{
- struct s3c_ep *ep = &dev->ep[ep_num];
- struct s3c_request *req;
+ struct dwc2_ep *ep = &dev->ep[ep_num];
+ struct dwc2_request *req;
debug_cond(DEBUG_IN_EP,
"%s: Check queue, ep_num = %d\n", __func__, ep_num);
if (!list_empty(&ep->queue)) {
- req = list_entry(ep->queue.next, struct s3c_request, queue);
+ req = list_entry(ep->queue.next, struct dwc2_request, queue);
debug_cond(DEBUG_IN_EP,
"%s: Next Tx request(0x%p) start...\n",
__func__, req);
@@ -362,7 +362,7 @@
}
-static void process_ep_in_intr(struct s3c_udc *dev)
+static void process_ep_in_intr(struct dwc2_udc *dev)
{
u32 ep_intr, ep_intr_status;
u8 ep_num = 0;
@@ -392,12 +392,12 @@
dev->ep0state = WAIT_FOR_SETUP;
if (dev->ep0state == WAIT_FOR_SETUP)
- s3c_udc_pre_setup();
+ dwc2_udc_pre_setup();
/* continue transfer after
set_clear_halt for DMA mode */
if (clear_feature_flag == 1) {
- s3c_udc_check_tx_queue(dev,
+ dwc2_udc_check_tx_queue(dev,
clear_feature_num);
clear_feature_flag = 0;
}
@@ -409,7 +409,7 @@
}
}
-static void process_ep_out_intr(struct s3c_udc *dev)
+static void process_ep_out_intr(struct dwc2_udc *dev)
{
u32 ep_intr, ep_intr_status;
u8 ep_num = 0;
@@ -438,7 +438,7 @@
complete_rx(dev, ep_num);
else {
dev->ep0state = WAIT_FOR_SETUP;
- s3c_udc_pre_setup();
+ dwc2_udc_pre_setup();
}
}
@@ -446,7 +446,7 @@
CTRL_OUT_EP_SETUP_PHASE_DONE) {
debug_cond(DEBUG_OUT_EP != 0,
"SETUP packet arrived\n");
- s3c_handle_ep0(dev);
+ dwc2_handle_ep0(dev);
}
} else {
if (ep_intr_status & TRANSFER_DONE)
@@ -461,9 +461,9 @@
/*
* usb client interrupt handler.
*/
-static int s3c_udc_irq(int irq, void *_dev)
+static int dwc2_udc_irq(int irq, void *_dev)
{
- struct s3c_udc *dev = _dev;
+ struct dwc2_udc *dev = _dev;
u32 intr_status;
u32 usb_status, gintmsk;
unsigned long flags = 0;
@@ -554,7 +554,7 @@
reconfig_usbd(dev);
dev->ep0state = WAIT_FOR_SETUP;
reset_available = 0;
- s3c_udc_pre_setup();
+ dwc2_udc_pre_setup();
} else
reset_available = 1;
@@ -579,16 +579,16 @@
/** Queue one request
* Kickstart transfer if needed
*/
-static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
+static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
gfp_t gfp_flags)
{
- struct s3c_request *req;
- struct s3c_ep *ep;
- struct s3c_udc *dev;
+ struct dwc2_request *req;
+ struct dwc2_ep *ep;
+ struct dwc2_udc *dev;
unsigned long flags = 0;
u32 ep_num, gintsts;
- req = container_of(_req, struct s3c_request, req);
+ req = container_of(_req, struct dwc2_request, req);
if (unlikely(!_req || !_req->complete || !_req->buf
|| !list_empty(&req->queue))) {
@@ -596,7 +596,7 @@
return -EINVAL;
}
- ep = container_of(_ep, struct s3c_ep, ep);
+ ep = container_of(_ep, struct dwc2_ep, ep);
if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
@@ -646,20 +646,20 @@
if (ep_num == 0) {
/* EP0 */
list_add_tail(&req->queue, &ep->queue);
- s3c_ep0_kick(dev, ep);
+ dwc2_ep0_kick(dev, ep);
req = 0;
} else if (ep_is_in(ep)) {
gintsts = readl(®->gintsts);
debug_cond(DEBUG_IN_EP,
- "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
+ "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
__func__, gintsts);
setdma_tx(ep, req);
} else {
gintsts = readl(®->gintsts);
debug_cond(DEBUG_OUT_EP != 0,
- "%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
+ "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
__func__, gintsts);
setdma_rx(ep, req);
@@ -680,7 +680,7 @@
/****************************************************************/
/* return: 0 = still running, 1 = completed, negative = errno */
-static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
+static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
{
u32 max;
unsigned count;
@@ -718,7 +718,7 @@
return 0;
}
-int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
+static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max)
{
invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
@@ -737,12 +737,12 @@
* Called from control endpoint function
* after it decodes a set address setup packet.
*/
-static void udc_set_address(struct s3c_udc *dev, unsigned char address)
+static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
{
u32 ctrl = readl(®->dcfg);
writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
- s3c_udc_ep0_zlp(dev);
+ dwc2_udc_ep0_zlp(dev);
debug_cond(DEBUG_EP0 != 0,
"%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
@@ -751,9 +751,9 @@
dev->usb_address = address;
}
-static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
+static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
{
- struct s3c_udc *dev;
+ struct dwc2_udc *dev;
u32 ep_ctrl = 0;
dev = ep->dev;
@@ -776,16 +776,16 @@
*/
dev->ep0state = WAIT_FOR_SETUP;
- s3c_udc_pre_setup();
+ dwc2_udc_pre_setup();
}
-static void s3c_ep0_read(struct s3c_udc *dev)
+static void dwc2_ep0_read(struct dwc2_udc *dev)
{
- struct s3c_request *req;
- struct s3c_ep *ep = &dev->ep[0];
+ struct dwc2_request *req;
+ struct dwc2_ep *ep = &dev->ep[0];
if (!list_empty(&ep->queue)) {
- req = list_entry(ep->queue.next, struct s3c_request, queue);
+ req = list_entry(ep->queue.next, struct dwc2_request, queue);
} else {
debug("%s: ---> BUG\n", __func__);
@@ -802,7 +802,7 @@
* or Bulk-Only mass storge reset */
ep->len = 0;
- s3c_udc_ep0_zlp(dev);
+ dwc2_udc_ep0_zlp(dev);
debug_cond(DEBUG_EP0 != 0,
"%s: req.length = 0, bRequest = %d\n",
@@ -816,16 +816,16 @@
/*
* DATA_STATE_XMIT
*/
-static int s3c_ep0_write(struct s3c_udc *dev)
+static int dwc2_ep0_write(struct dwc2_udc *dev)
{
- struct s3c_request *req;
- struct s3c_ep *ep = &dev->ep[0];
+ struct dwc2_request *req;
+ struct dwc2_ep *ep = &dev->ep[0];
int ret, need_zlp = 0;
if (list_empty(&ep->queue))
req = 0;
else
- req = list_entry(ep->queue.next, struct s3c_request, queue);
+ req = list_entry(ep->queue.next, struct dwc2_request, queue);
if (!req) {
debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
@@ -859,7 +859,7 @@
return 1;
}
-int s3c_udc_get_status(struct s3c_udc *dev,
+static int dwc2_udc_get_status(struct dwc2_udc *dev,
struct usb_ctrlrequest *crq)
{
u8 ep_num = crq->wIndex & 0x7F;
@@ -920,7 +920,7 @@
return 0;
}
-static void s3c_udc_set_nak(struct s3c_ep *ep)
+static void dwc2_udc_set_nak(struct dwc2_ep *ep)
{
u8 ep_num;
u32 ep_ctrl = 0;
@@ -946,7 +946,7 @@
}
-void s3c_udc_ep_set_stall(struct s3c_ep *ep)
+static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
{
u8 ep_num;
u32 ep_ctrl = 0;
@@ -981,7 +981,7 @@
return;
}
-void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
+static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
{
u8 ep_num;
u32 ep_ctrl = 0;
@@ -1029,14 +1029,14 @@
return;
}
-static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
+static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
{
- struct s3c_ep *ep;
- struct s3c_udc *dev;
+ struct dwc2_ep *ep;
+ struct dwc2_udc *dev;
unsigned long flags = 0;
u8 ep_num;
- ep = container_of(_ep, struct s3c_ep, ep);
+ ep = container_of(_ep, struct dwc2_ep, ep);
ep_num = ep_index(ep);
if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
@@ -1050,7 +1050,7 @@
if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
debug("%s: %s queue not empty, req = %p\n",
__func__, ep->ep.name,
- list_entry(ep->queue.next, struct s3c_request, queue));
+ list_entry(ep->queue.next, struct dwc2_request, queue));
return -EAGAIN;
}
@@ -1062,13 +1062,13 @@
if (value == 0) {
ep->stopped = 0;
- s3c_udc_ep_clear_stall(ep);
+ dwc2_udc_ep_clear_stall(ep);
} else {
if (ep_num == 0)
dev->ep0state = WAIT_FOR_SETUP;
ep->stopped = 1;
- s3c_udc_ep_set_stall(ep);
+ dwc2_udc_ep_set_stall(ep);
}
spin_unlock_irqrestore(&dev->lock, flags);
@@ -1076,7 +1076,7 @@
return 0;
}
-void s3c_udc_ep_activate(struct s3c_ep *ep)
+static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
{
u8 ep_num;
u32 ep_ctrl = 0, daintmsk = 0;
@@ -1123,13 +1123,13 @@
}
-static int s3c_udc_clear_feature(struct usb_ep *_ep)
+static int dwc2_udc_clear_feature(struct usb_ep *_ep)
{
- struct s3c_udc *dev;
- struct s3c_ep *ep;
+ struct dwc2_udc *dev;
+ struct dwc2_ep *ep;
u8 ep_num;
- ep = container_of(_ep, struct s3c_ep, ep);
+ ep = container_of(_ep, struct dwc2_ep, ep);
ep_num = ep_index(ep);
dev = ep->dev;
@@ -1158,7 +1158,7 @@
break;
}
- s3c_udc_ep0_zlp(dev);
+ dwc2_udc_ep0_zlp(dev);
break;
case USB_RECIP_ENDPOINT:
@@ -1168,14 +1168,14 @@
if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
if (ep_num == 0) {
- s3c_udc_ep0_set_stall(ep);
+ dwc2_udc_ep0_set_stall(ep);
return 0;
}
- s3c_udc_ep0_zlp(dev);
+ dwc2_udc_ep0_zlp(dev);
- s3c_udc_ep_clear_stall(ep);
- s3c_udc_ep_activate(ep);
+ dwc2_udc_ep_clear_stall(ep);
+ dwc2_udc_ep_activate(ep);
ep->stopped = 0;
clear_feature_num = ep_num;
@@ -1187,13 +1187,13 @@
return 0;
}
-static int s3c_udc_set_feature(struct usb_ep *_ep)
+static int dwc2_udc_set_feature(struct usb_ep *_ep)
{
- struct s3c_udc *dev;
- struct s3c_ep *ep;
+ struct dwc2_udc *dev;
+ struct dwc2_ep *ep;
u8 ep_num;
- ep = container_of(_ep, struct s3c_ep, ep);
+ ep = container_of(_ep, struct dwc2_ep, ep);
ep_num = ep_index(ep);
dev = ep->dev;
@@ -1232,7 +1232,7 @@
break;
}
- s3c_udc_ep0_zlp(dev);
+ dwc2_udc_ep0_zlp(dev);
return 0;
case USB_RECIP_INTERFACE:
@@ -1245,14 +1245,14 @@
"\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
if (ep_num == 0) {
- s3c_udc_ep0_set_stall(ep);
+ dwc2_udc_ep0_set_stall(ep);
return 0;
}
ep->stopped = 1;
- s3c_udc_ep_set_stall(ep);
+ dwc2_udc_ep_set_stall(ep);
}
- s3c_udc_ep0_zlp(dev);
+ dwc2_udc_ep0_zlp(dev);
return 0;
}
@@ -1262,9 +1262,9 @@
/*
* WAIT_FOR_SETUP (OUT_PKT_RDY)
*/
-void s3c_ep0_setup(struct s3c_udc *dev)
+static void dwc2_ep0_setup(struct dwc2_udc *dev)
{
- struct s3c_ep *ep = &dev->ep[0];
+ struct dwc2_ep *ep = &dev->ep[0];
int i;
u8 ep_num;
@@ -1272,7 +1272,7 @@
nuke(ep, -EPROTO);
/* read control req from fifo (8 bytes) */
- s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
+ dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8);
debug_cond(DEBUG_SETUP != 0,
"%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
@@ -1306,7 +1306,7 @@
"wLength = %d, setup returned\n",
usb_ctrl->wLength);
- s3c_udc_ep0_set_stall(ep);
+ dwc2_udc_ep0_set_stall(ep);
dev->ep0state = WAIT_FOR_SETUP;
return;
@@ -1317,7 +1317,7 @@
"%s:BOT Rest:invalid wLength =%d, setup returned\n",
__func__, usb_ctrl->wLength);
- s3c_udc_ep0_set_stall(ep);
+ dwc2_udc_ep0_set_stall(ep);
dev->ep0state = WAIT_FOR_SETUP;
return;
@@ -1384,7 +1384,7 @@
break;
case USB_REQ_GET_STATUS:
- if (!s3c_udc_get_status(dev, usb_ctrl))
+ if (!dwc2_udc_get_status(dev, usb_ctrl))
return;
break;
@@ -1392,7 +1392,7 @@
case USB_REQ_CLEAR_FEATURE:
ep_num = usb_ctrl->wIndex & 0x7f;
- if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
+ if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
return;
break;
@@ -1400,7 +1400,7 @@
case USB_REQ_SET_FEATURE:
ep_num = usb_ctrl->wIndex & 0x7f;
- if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
+ if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
return;
break;
@@ -1427,7 +1427,7 @@
if (i < 0) {
/* setup processing failed, force stall */
- s3c_udc_ep0_set_stall(ep);
+ dwc2_udc_ep0_set_stall(ep);
dev->ep0state = WAIT_FOR_SETUP;
debug_cond(DEBUG_SETUP != 0,
@@ -1451,12 +1451,12 @@
/*
* handle ep0 interrupt
*/
-static void s3c_handle_ep0(struct s3c_udc *dev)
+static void dwc2_handle_ep0(struct dwc2_udc *dev)
{
if (dev->ep0state == WAIT_FOR_SETUP) {
debug_cond(DEBUG_OUT_EP != 0,
"%s: WAIT_FOR_SETUP\n", __func__);
- s3c_ep0_setup(dev);
+ dwc2_ep0_setup(dev);
} else {
debug_cond(DEBUG_OUT_EP != 0,
@@ -1465,16 +1465,16 @@
}
}
-static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
+static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
{
debug_cond(DEBUG_EP0 != 0,
"%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
if (ep_is_in(ep)) {
dev->ep0state = DATA_STATE_XMIT;
- s3c_ep0_write(dev);
+ dwc2_ep0_write(dev);
} else {
dev->ep0state = DATA_STATE_RECV;
- s3c_ep0_read(dev);
+ dwc2_ep0_read(dev);
}
}
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 20b6c18..87e54eb 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -477,7 +477,7 @@
req->complete = rx_handler_command;
req->length = EP_BUFFER_SIZE;
- sprintf(response, "OKAY");
+ strcpy(response, "OKAY");
fastboot_tx_write_str(response);
printf("\ndownloading of %d bytes finished\n", download_bytes);
@@ -506,10 +506,10 @@
printf("Starting download of %d bytes\n", download_size);
if (0 == download_size) {
- sprintf(response, "FAILdata invalid size");
+ strcpy(response, "FAILdata invalid size");
} else if (download_size > CONFIG_FASTBOOT_BUF_SIZE) {
download_size = 0;
- sprintf(response, "FAILdata too large");
+ strcpy(response, "FAILdata too large");
} else {
sprintf(response, "DATA%08x", download_size);
req->complete = rx_handler_dl_image;
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index ec1f23a..1ecb92a 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -444,8 +444,9 @@
/*-------------------------------------------------------------------------*/
-struct ums *ums;
-struct fsg_common *the_fsg_common;
+static struct ums *ums;
+static int ums_count;
+static struct fsg_common *the_fsg_common;
static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
{
@@ -772,7 +773,7 @@
}
/* Perform the read */
- rc = ums->read_sector(ums,
+ rc = ums[common->lun].read_sector(&ums[common->lun],
file_offset / SECTOR_SIZE,
amount / SECTOR_SIZE,
(char __user *)bh->buf);
@@ -946,7 +947,7 @@
amount = bh->outreq->actual;
/* Perform the write */
- rc = ums->write_sector(ums,
+ rc = ums[common->lun].write_sector(&ums[common->lun],
file_offset / SECTOR_SIZE,
amount / SECTOR_SIZE,
(char __user *)bh->buf);
@@ -1062,7 +1063,7 @@
}
/* Perform the read */
- rc = ums->read_sector(ums,
+ rc = ums[common->lun].read_sector(&ums[common->lun],
file_offset / SECTOR_SIZE,
amount / SECTOR_SIZE,
(char __user *)bh->buf);
@@ -1117,7 +1118,7 @@
buf[4] = 31; /* Additional length */
/* No special options */
sprintf((char *) (buf + 8), "%-8s%-16s%04x", (char*) vendor_id ,
- ums->name, (u16) 0xffff);
+ ums[common->lun].name, (u16) 0xffff);
return 36;
}
@@ -2456,7 +2457,7 @@
int nluns, i, rc;
/* Find out how many LUNs there should be */
- nluns = 1;
+ nluns = ums_count;
if (nluns < 1 || nluns > FSG_MAX_LUNS) {
printf("invalid number of LUNs: %u\n", nluns);
return ERR_PTR(-EINVAL);
@@ -2501,7 +2502,7 @@
for (i = 0; i < nluns; i++) {
common->luns[i].removable = 1;
- rc = fsg_lun_open(&common->luns[i], "");
+ rc = fsg_lun_open(&common->luns[i], ums[i].num_sectors, "");
if (rc)
goto error_luns;
}
@@ -2775,9 +2776,10 @@
return fsg_bind_config(c->cdev, c, fsg_common);
}
-int fsg_init(struct ums *ums_dev)
+int fsg_init(struct ums *ums_devs, int count)
{
- ums = ums_dev;
+ ums = ums_devs;
+ ums_count = count;
return 0;
}
diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c
index 62c9b2e..48463db 100644
--- a/drivers/usb/gadget/rndis.c
+++ b/drivers/usb/gadget/rndis.c
@@ -4,10 +4,6 @@
* Authors: Benedikt Spranger, Pengutronix
* Robert Schwebel, Pengutronix
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2, as published by the Free Software Foundation.
- *
* This software was originally developed in conformance with
* Microsoft's Remote NDIS Specification License Agreement.
*
@@ -19,6 +15,8 @@
*
* Copyright (C) 2004 by David Brownell
* updates to merge with Linux 2.6, better match RNDIS spec
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/usb/gadget/rndis.h b/drivers/usb/gadget/rndis.h
index d9e3a75..7a389a5 100644
--- a/drivers/usb/gadget/rndis.h
+++ b/drivers/usb/gadget/rndis.h
@@ -4,12 +4,10 @@
* Authors: Benedikt Spranger, Pengutronix
* Robert Schwebel, Pengutronix
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2, as published by the Free Software Foundation.
- *
* This software was originally developed in conformance with
* Microsoft's Remote NDIS Specification License Agreement.
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _USBGADGET_RNDIS_H
diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c
index b55e40b..b6df130 100644
--- a/drivers/usb/gadget/storage_common.c
+++ b/drivers/usb/gadget/storage_common.c
@@ -564,7 +564,8 @@
* the caller must own fsg->filesem for writing.
*/
-static int fsg_lun_open(struct fsg_lun *curlun, const char *filename)
+static int fsg_lun_open(struct fsg_lun *curlun, unsigned int num_sectors,
+ const char *filename)
{
int ro;
@@ -572,8 +573,8 @@
ro = curlun->initially_ro;
curlun->ro = ro;
- curlun->file_length = ums->num_sectors << 9;
- curlun->num_sectors = ums->num_sectors;
+ curlun->file_length = num_sectors << 9;
+ curlun->num_sectors = num_sectors;
debug("open backing file: %s\n", filename);
return 0;
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 0096a2f..39f7185 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -26,6 +26,14 @@
endif
+config USB_OHCI_GENERIC
+ bool "Support for generic OHCI USB controller"
+ depends on OF_CONTROL
+ depends on DM_USB
+ default n
+ ---help---
+ Enables support for generic OHCI controller.
+
config USB_EHCI_HCD
bool "EHCI HCD (USB 2.0) support"
---help---
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 0b4b458..6183b80 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -21,6 +21,7 @@
obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o
obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
+obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
# echi
obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 541c0f9..5ef6deb 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -823,12 +823,13 @@
(*pid << DWC2_HCTSIZ_PID_OFFSET),
&hc_regs->hctsiz);
- if (!in) {
- memcpy(priv->aligned_buffer, (char *)buffer + done, len);
+ if (!in && xfer_len) {
+ memcpy(priv->aligned_buffer, (char *)buffer + done,
+ xfer_len);
flush_dcache_range((unsigned long)priv->aligned_buffer,
(unsigned long)((void *)priv->aligned_buffer +
- roundup(len, ARCH_DMA_MINALIGN)));
+ roundup(xfer_len, ARCH_DMA_MINALIGN)));
}
writel(phys_to_bus((unsigned long)priv->aligned_buffer),
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index 18e9251..bede04b 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -219,14 +219,14 @@
ctx->hcd = (struct ehci_hccr *)plat->hcd_base;
ctx->usb = (struct exynos_usb_phy *)plat->phy_base;
- hcor = (struct ehci_hcor *)((uint32_t)ctx->hcd +
- HC_LENGTH(ehci_readl(&ctx->hcd->cr_capbase)));
/* setup the Vbus gpio here */
if (dm_gpio_is_valid(&plat->vbus_gpio))
dm_gpio_set_value(&plat->vbus_gpio, 1);
setup_usb_phy(ctx->usb);
+ hcor = (struct ehci_hcor *)((uint32_t)ctx->hcd +
+ HC_LENGTH(ehci_readl(&ctx->hcd->cr_capbase)));
return ehci_register(dev, ctx->hcd, hcor, NULL, 0, USB_INIT_HOST);
}
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index c85dbce..c664b16 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -279,56 +279,16 @@
static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
struct QH *qh)
{
- struct usb_device *ttdev;
- int parent_devnum;
+ uint8_t portnr = 0;
+ uint8_t hubaddr = 0;
if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
return;
- /*
- * For full / low speed devices we need to get the devnum and portnr of
- * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs
- * in the tree before that one!
- */
-#ifdef CONFIG_DM_USB
- /*
- * When called from usb-uclass.c: usb_scan_device() udev->dev points
- * to the parent udevice, not the actual udevice belonging to the
- * udev as the device is not instantiated yet. So when searching
- * for the first usb-2 parent start with udev->dev not
- * udev->dev->parent .
- */
- struct udevice *parent;
- struct usb_device *uparent;
-
- ttdev = udev;
- parent = udev->dev;
- uparent = dev_get_parent_priv(parent);
-
- while (uparent->speed != USB_SPEED_HIGH) {
- struct udevice *dev = parent;
-
- if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
- printf("ehci: Error cannot find high-speed parent of usb-1 device\n");
- return;
- }
-
- ttdev = dev_get_parent_priv(dev);
- parent = dev->parent;
- uparent = dev_get_parent_priv(parent);
- }
- parent_devnum = uparent->devnum;
-#else
- ttdev = udev;
- while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH)
- ttdev = ttdev->parent;
- if (!ttdev->parent)
- return;
- parent_devnum = ttdev->parent->devnum;
-#endif
+ usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
- qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) |
- QH_ENDPT2_HUBADDR(parent_devnum));
+ qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
+ QH_ENDPT2_HUBADDR(hubaddr));
}
static int
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 0cb9fcc..cda1c6d 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -18,32 +18,34 @@
struct ehci_ctrl ehci;
};
-static void ehci_pci_common_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr,
- struct ehci_hcor **ret_hcor)
+#ifdef CONFIG_DM_USB
+
+static void ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr,
+ struct ehci_hcor **ret_hcor)
{
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
- uint32_t cmd;
+ u32 cmd;
- hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+ hccr = (struct ehci_hccr *)dm_pci_map_bar(dev,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
+ hcor = (struct ehci_hcor *)((uintptr_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (u32)hccr, (u32)hcor,
+ (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
*ret_hccr = hccr;
*ret_hcor = hcor;
/* enable busmaster */
- pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
+ dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER;
- pci_write_config_dword(pdev, PCI_COMMAND, cmd);
+ dm_pci_write_config32(dev, PCI_COMMAND, cmd);
}
-#ifndef CONFIG_DM_USB
+#else
#ifdef CONFIG_PCI_EHCI_DEVICE
static struct pci_device_id ehci_pci_ids[] = {
@@ -55,6 +57,31 @@
};
#endif
+static void ehci_pci_legacy_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr,
+ struct ehci_hcor **ret_hcor)
+{
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ u32 cmd;
+
+ hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+ PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ hcor = (struct ehci_hcor *)((uintptr_t) hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
+ (u32)hccr, (u32)hcor,
+ (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ *ret_hccr = hccr;
+ *ret_hcor = hcor;
+
+ /* enable busmaster */
+ pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER;
+ pci_write_config_dword(pdev, PCI_COMMAND, cmd);
+}
+
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
@@ -73,7 +100,7 @@
printf("EHCI host controller not found\n");
return -1;
}
- ehci_pci_common_init(pdev, ret_hccr, ret_hcor);
+ ehci_pci_legacy_init(pdev, ret_hccr, ret_hcor);
return 0;
}
@@ -94,7 +121,7 @@
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
- ehci_pci_common_init(pci_get_bdf(dev), &hccr, &hcor);
+ ehci_pci_init(dev, &hccr, &hcor);
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}
diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c
index 98e0fc6..335e303 100644
--- a/drivers/usb/host/ehci-vf.c
+++ b/drivers/usb/host/ehci-vf.c
@@ -121,6 +121,11 @@
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
}
+int __weak board_usb_phy_mode(int port)
+{
+ return 0;
+}
+
int __weak board_ehci_hcd_init(int port)
{
return 0;
@@ -130,15 +135,11 @@
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
+ enum usb_init_type type;
if (index >= ARRAY_SIZE(nc_reg_bases))
return -EINVAL;
- if (init == USB_INIT_DEVICE && index == 1)
- return -ENODEV;
- if (init == USB_INIT_HOST && index == 0)
- return -ENODEV;
-
ehci = (struct usb_ehci *)nc_reg_bases[index];
/* Do board specific initialisation */
@@ -153,6 +154,10 @@
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+ type = board_usb_phy_mode(index);
+ if (type != init)
+ return -ENODEV;
+
if (init == USB_INIT_DEVICE) {
setbits_le32(&ehci->usbmode, CM_DEVICE);
writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
new file mode 100644
index 0000000..f3307f4
--- /dev/null
+++ b/drivers/usb/host/ohci-generic.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Alexey Brodkin <abrodkin@synopsys.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include "ohci.h"
+
+#if !defined(CONFIG_USB_OHCI_NEW)
+# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
+#endif
+
+struct generic_ohci {
+ ohci_t ohci;
+};
+
+static int ohci_usb_probe(struct udevice *dev)
+{
+ struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev);
+
+ return ohci_register(dev, regs);
+}
+
+static int ohci_usb_remove(struct udevice *dev)
+{
+ return ohci_deregister(dev);
+}
+
+static const struct udevice_id ohci_usb_ids[] = {
+ { .compatible = "generic-ohci" },
+ { }
+};
+
+U_BOOT_DRIVER(ohci_generic) = {
+ .name = "ohci_generic",
+ .id = UCLASS_USB,
+ .of_match = ohci_usb_ids,
+ .probe = ohci_usb_probe,
+ .remove = ohci_usb_remove,
+ .ops = &ohci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct generic_ohci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/usb/musb-new/am35x.c b/drivers/usb/musb-new/am35x.c
index d158454..b8791dd 100644
--- a/drivers/usb/musb-new/am35x.c
+++ b/drivers/usb/musb-new/am35x.c
@@ -8,21 +8,7 @@
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*
*/
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index d1b6d15..a6d6af6 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -5,31 +5,7 @@
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
diff --git a/drivers/usb/musb-new/musb_core.h b/drivers/usb/musb-new/musb_core.h
index c818040..2fe4ed5 100644
--- a/drivers/usb/musb-new/musb_core.h
+++ b/drivers/usb/musb-new/musb_core.h
@@ -5,31 +5,7 @@
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_CORE_H__
diff --git a/drivers/usb/musb-new/musb_debug.h b/drivers/usb/musb-new/musb_debug.h
index 27ba8f7..3befaa2 100644
--- a/drivers/usb/musb-new/musb_debug.h
+++ b/drivers/usb/musb-new/musb_debug.h
@@ -5,31 +5,7 @@
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_LINUX_DEBUG_H__
diff --git a/drivers/usb/musb-new/musb_dma.h b/drivers/usb/musb-new/musb_dma.h
index 17fe89f..30e39f5 100644
--- a/drivers/usb/musb-new/musb_dma.h
+++ b/drivers/usb/musb-new/musb_dma.h
@@ -5,31 +5,7 @@
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_DMA_H__
diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c
index 8959397..bb7c952 100644
--- a/drivers/usb/musb-new/musb_dsps.c
+++ b/drivers/usb/musb-new/musb_dsps.c
@@ -7,21 +7,7 @@
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*
* musb_dsps.c will be a common file for all the TI DSPS platforms
* such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c
index 309dc7f..c704e6f 100644
--- a/drivers/usb/musb-new/musb_gadget.c
+++ b/drivers/usb/musb-new/musb_gadget.c
@@ -6,31 +6,7 @@
* Copyright (C) 2006-2007 Nokia Corporation
* Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __UBOOT__
diff --git a/drivers/usb/musb-new/musb_gadget.h b/drivers/usb/musb-new/musb_gadget.h
index 392f701..ddd567b 100644
--- a/drivers/usb/musb-new/musb_gadget.h
+++ b/drivers/usb/musb-new/musb_gadget.h
@@ -5,31 +5,7 @@
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_GADGET_H
diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c
index 415a9f2..3cfcb22 100644
--- a/drivers/usb/musb-new/musb_gadget_ep0.c
+++ b/drivers/usb/musb-new/musb_gadget_ep0.c
@@ -6,31 +6,7 @@
* Copyright (C) 2006-2007 Nokia Corporation
* Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __UBOOT__
diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c
index 40b9c66..ce5b6a7 100644
--- a/drivers/usb/musb-new/musb_host.c
+++ b/drivers/usb/musb-new/musb_host.c
@@ -6,31 +6,7 @@
* Copyright (C) 2006-2007 Nokia Corporation
* Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __UBOOT__
@@ -2092,9 +2068,13 @@
}
#else
if (tt_needed(musb, urb->dev)) {
- u16 hub_port = find_tt(urb->dev);
- qh->h_addr_reg = (u8) (hub_port >> 8);
- qh->h_port_reg = (u8) (hub_port & 0xff);
+ uint8_t portnr = 0;
+ uint8_t hubaddr = 0;
+ usb_find_usb2_hub_address_port(urb->dev,
+ &hubaddr,
+ &portnr);
+ qh->h_addr_reg = hubaddr;
+ qh->h_port_reg = portnr;
}
#endif
}
diff --git a/drivers/usb/musb-new/musb_host.h b/drivers/usb/musb-new/musb_host.h
index 546b4a2..c1cee8b 100644
--- a/drivers/usb/musb-new/musb_host.h
+++ b/drivers/usb/musb-new/musb_host.h
@@ -5,31 +5,7 @@
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _MUSB_HOST_H
diff --git a/drivers/usb/musb-new/musb_io.h b/drivers/usb/musb-new/musb_io.h
index 51730ae..ea8efb3 100644
--- a/drivers/usb/musb-new/musb_io.h
+++ b/drivers/usb/musb-new/musb_io.h
@@ -9,27 +9,7 @@
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_LINUX_PLATFORM_ARCH_H__
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h
index 90288c4..4dc9abb 100644
--- a/drivers/usb/musb-new/musb_regs.h
+++ b/drivers/usb/musb-new/musb_regs.h
@@ -5,31 +5,7 @@
* Copyright (C) 2005-2006 by Texas Instruments
* Copyright (C) 2006-2007 Nokia Corporation
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_REGS_H__
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index 77273a4..9f307e9 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -7,22 +7,7 @@
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __UBOOT__
#include <linux/module.h>
diff --git a/drivers/usb/musb-new/omap2430.h b/drivers/usb/musb-new/omap2430.h
index 3b795c2..56998c7 100644
--- a/drivers/usb/musb-new/omap2430.h
+++ b/drivers/usb/musb-new/omap2430.h
@@ -1,10 +1,7 @@
/*
* Copyright (C) 2005-2006 by Texas Instruments
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MUSB_OMAP243X_H__
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 5eb8d19..be1d2ec 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -14,11 +14,7 @@
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/arch/cpu.h>
diff --git a/drivers/usb/musb-new/usb-compat.h b/drivers/usb/musb-new/usb-compat.h
index 1c41e2a..760bd78 100644
--- a/drivers/usb/musb-new/usb-compat.h
+++ b/drivers/usb/musb-new/usb-compat.h
@@ -68,38 +68,6 @@
}
#ifdef CONFIG_DM_USB
-static inline u16 find_tt(struct usb_device *udev)
-{
- struct udevice *parent;
- struct usb_device *uparent, *ttdev;
-
- /*
- * When called from usb-uclass.c: usb_scan_device() udev->dev points
- * to the parent udevice, not the actual udevice belonging to the
- * udev as the device is not instantiated yet. So when searching
- * for the first usb-2 parent start with udev->dev not
- * udev->dev->parent .
- */
- ttdev = udev;
- parent = udev->dev;
- uparent = dev_get_parent_priv(parent);
-
- while (uparent->speed != USB_SPEED_HIGH) {
- struct udevice *dev = parent;
-
- if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
- printf("musb: Error cannot find high speed parent of usb-1 device\n");
- return 0;
- }
-
- ttdev = dev_get_parent_priv(dev);
- parent = dev->parent;
- uparent = dev_get_parent_priv(parent);
- }
-
- return (uparent->devnum << 8) | (ttdev->portnr - 1);
-}
-
static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev)
{
struct udevice *parent = udev->dev->parent;
@@ -129,27 +97,6 @@
return NULL;
}
#else
-static inline u16 find_tt(struct usb_device *dev)
-{
- u8 chid;
- u8 hub;
-
- /* Find out the nearest parent which is high speed */
- while (dev->parent->parent != NULL)
- if (dev->parent->speed != USB_SPEED_HIGH)
- dev = dev->parent;
- else
- break;
-
- /* determine the port address at that hub */
- hub = dev->parent->devnum;
- for (chid = 0; chid < USB_MAXCHILDREN; chid++)
- if (dev->parent->children[chid] == dev)
- break;
-
- return (hub << 8) | chid;
-}
-
static inline struct usb_device *usb_dev_get_parent(struct usb_device *dev)
{
return dev->parent;
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index ec8a038..dc863bd 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -4,31 +4,7 @@
*
* This file is part of the Inventra Controller Driver for Linux.
*
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
- *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- * License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA 02111-1307 USA
- *
- * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
- * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
- * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
- * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
- * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
- * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
- * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
- * GRAPHICS SUPPORT CUSTOMER.
+ * SPDX-License-Identifier: GPL-2.0
******************************************************************/
#ifndef __MUSB_HDRC_DEFS_H__
diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c
index 4db7fa4..63151aa 100644
--- a/drivers/usb/ulpi/omap-ulpi-viewport.c
+++ b/drivers/usb/ulpi/omap-ulpi-viewport.c
@@ -5,17 +5,7 @@
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/usb/ulpi/ulpi-viewport.c b/drivers/usb/ulpi/ulpi-viewport.c
index b4974ed..72a06de 100644
--- a/drivers/usb/ulpi/ulpi-viewport.c
+++ b/drivers/usb/ulpi/ulpi-viewport.c
@@ -11,15 +11,7 @@
* Original Copyright follow:
* Copyright (C) 2011 Google, Inc.
*
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
index a19651f..021c1d6 100644
--- a/drivers/video/vesa_fb.c
+++ b/drivers/video/vesa_fb.c
@@ -19,8 +19,8 @@
void *video_hw_init(void)
{
GraphicDevice *gdev = &ctfb;
+ struct udevice *dev;
int bits_per_pixel;
- pci_dev_t dev;
int ret;
printf("Video: ");
@@ -33,14 +33,14 @@
return NULL;
}
if (vbe_get_video_info(gdev)) {
- dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
- if (dev < 0) {
+ ret = dm_pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0, &dev);
+ if (ret) {
printf("no card detected\n");
return NULL;
}
bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
- ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
+ ret = dm_pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
+ PCI_ROM_ALLOW_FALLBACK);
bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
if (ret) {
printf("failed to run video BIOS: %d\n", ret);
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 0d77595..f9f8175 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -43,7 +43,7 @@
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- clrsetbits_le16(&wdog->wcr, 0, WCR_WDE);
+ clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
writew(0x5555, &wdog->wsr);
writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
diff --git a/dts/Makefile b/dts/Makefile
index d3122aa..c4ac153 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -45,4 +45,4 @@
clean-files := dt.dtb.S
# Let clean descend into dts directories
-subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts
+subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts
diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c
index 20f5256..9fd10de 100644
--- a/fs/ext4/dev.c
+++ b/fs/ext4/dev.c
@@ -76,10 +76,10 @@
if (byte_offset != 0) {
int readlen;
/* read first part which isn't aligned with start of sector */
- if (ext4fs_block_dev_desc->
- block_read(ext4fs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf(" ** ext2fs_devread() read error **\n");
return 0;
}
@@ -101,18 +101,18 @@
ALLOC_CACHE_ALIGN_BUFFER(u8, p, ext4fs_block_dev_desc->blksz);
block_len = ext4fs_block_dev_desc->blksz;
- ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
+ ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
part_info->start + sector,
- 1, (unsigned long *)p);
+ 1, (void *)p);
memcpy(buf, p, byte_len);
return 1;
}
- if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev,
- part_info->start + sector,
- block_len >> log2blksz,
- (unsigned long *) buf) !=
- block_len >> log2blksz) {
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
+ part_info->start + sector,
+ block_len >> log2blksz,
+ (void *)buf) !=
+ block_len >> log2blksz) {
printf(" ** %s read error - block\n", __func__);
return 0;
}
@@ -123,10 +123,10 @@
if (byte_len != 0) {
/* read rest of data which are not in whole sector */
- if (ext4fs_block_dev_desc->
- block_read(ext4fs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
+ if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf("* %s read error - last part\n", __func__);
return 0;
}
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index e73223a..294a46e 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -82,26 +82,26 @@
if (remainder) {
if (fs->dev_desc->block_read) {
- fs->dev_desc->block_read(fs->dev_desc->dev,
+ fs->dev_desc->block_read(fs->dev_desc,
startblock, 1, sec_buf);
temp_ptr = sec_buf;
memcpy((temp_ptr + remainder),
(unsigned char *)buf, size);
- fs->dev_desc->block_write(fs->dev_desc->dev,
+ fs->dev_desc->block_write(fs->dev_desc,
startblock, 1, sec_buf);
}
} else {
if (size >> log2blksz != 0) {
- fs->dev_desc->block_write(fs->dev_desc->dev,
+ fs->dev_desc->block_write(fs->dev_desc,
startblock,
size >> log2blksz,
(unsigned long *)buf);
} else {
- fs->dev_desc->block_read(fs->dev_desc->dev,
+ fs->dev_desc->block_read(fs->dev_desc,
startblock, 1, sec_buf);
temp_ptr = sec_buf;
memcpy(temp_ptr, buf, size);
- fs->dev_desc->block_write(fs->dev_desc->dev,
+ fs->dev_desc->block_write(fs->dev_desc,
startblock, 1,
(unsigned long *)sec_buf);
}
@@ -1287,11 +1287,11 @@
ti_gp_blockno = ext4fs_get_new_blk_no();
if (ti_gp_blockno == -1) {
printf("no block left to assign\n");
- goto fail;
+ return;
}
ti_gp_buff = zalloc(fs->blksz);
if (!ti_gp_buff)
- goto fail;
+ return;
ti_gp_buff_start_addr = ti_gp_buff;
(*no_blks_reqd)++;
@@ -1321,11 +1321,11 @@
ti_child_blockno = ext4fs_get_new_blk_no();
if (ti_child_blockno == -1) {
printf("no block left assign\n");
- goto fail;
+ goto fail1;
}
ti_child_buff = zalloc(fs->blksz);
if (!ti_child_buff)
- goto fail;
+ goto fail1;
ti_cbuff_start_addr = ti_child_buff;
*ti_parent_buff = ti_child_blockno;
@@ -1341,7 +1341,8 @@
ext4fs_get_new_blk_no();
if (actual_block_no == -1) {
printf("no block left\n");
- goto fail;
+ free(ti_cbuff_start_addr);
+ goto fail1;
}
*ti_child_buff = actual_block_no;
debug("TIAB %ld: %u\n", actual_block_no,
@@ -1373,7 +1374,11 @@
put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)),
ti_gp_buff_start_addr, fs->blksz);
file_inode->b.blocks.triple_indir_block = ti_gp_blockno;
+ free(ti_gp_buff_start_addr);
+ return;
}
+fail1:
+ free(ti_pbuff_start_addr);
fail:
free(ti_gp_buff_start_addr);
}
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index f939bc5..472a63e 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -51,8 +51,8 @@
if (!cur_dev || !cur_dev->block_read)
return -1;
- ret = cur_dev->block_read(cur_dev->dev,
- cur_part_info.start + block, nr_blocks, buf);
+ ret = cur_dev->block_read(cur_dev, cur_part_info.start + block,
+ nr_blocks, buf);
if (nr_blocks && ret == 0)
return -1;
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index af828d0..5ed324c 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -41,8 +41,7 @@
return -1;
}
- ret = cur_dev->block_write(cur_dev->dev,
- cur_part_info.start + block,
+ ret = cur_dev->block_write(cur_dev, cur_part_info.start + block,
nr_blocks, buf);
if (nr_blocks && ret == 0)
return -1;
diff --git a/fs/fs.c b/fs/fs.c
index b2d6a53..d123d29 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <config.h>
@@ -427,6 +417,7 @@
}
puts("\n");
+ setenv_hex("fileaddr", addr);
setenv_hex("filesize", len_read);
return 0;
diff --git a/fs/reiserfs/dev.c b/fs/reiserfs/dev.c
index 6825545..7b24d6a 100644
--- a/fs/reiserfs/dev.c
+++ b/fs/reiserfs/dev.c
@@ -59,9 +59,11 @@
if (byte_offset != 0) {
/* read first part which isn't aligned with start of sector */
- if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *)sec_buf) != 1) {
+ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
+ part_info->start +
+ sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf (" ** reiserfs_devread() read error\n");
return 0;
}
@@ -73,9 +75,11 @@
/* read sector aligned part */
block_len = byte_len & ~(SECTOR_SIZE-1);
- if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev,
- part_info->start + sector, block_len/SECTOR_SIZE,
- (unsigned long *)buf) != block_len/SECTOR_SIZE) {
+ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
+ part_info->start + sector,
+ block_len / SECTOR_SIZE,
+ (void *)buf)
+ != block_len/SECTOR_SIZE) {
printf (" ** reiserfs_devread() read error - block\n");
return 0;
}
@@ -85,9 +89,11 @@
if ( byte_len != 0 ) {
/* read rest of data which are not in whole sector */
- if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *)sec_buf) != 1) {
+ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
+ part_info->start +
+ sector,
+ 1, (void *)sec_buf)
+ != 1) {
printf (" ** reiserfs_devread() read error - last part\n");
return 0;
}
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index 50355e9..a992a00 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -6,21 +6,10 @@
* (C) Copyright 2008-2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 51
- * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
* Authors: Artem Bityutskiy (ĐĐžŃŃŃĐșĐžĐč ĐŃŃŃĐŒ)
* Adrian Hunter
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/fs/zfs/dev.c b/fs/zfs/dev.c
index 3a1fa56..67d1265 100644
--- a/fs/zfs/dev.c
+++ b/fs/zfs/dev.c
@@ -55,9 +55,10 @@
if (byte_offset != 0) {
/* read first part which isn't aligned with start of sector */
- if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *)sec_buf) != 1) {
+ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector, 1,
+ (void *)sec_buf)
+ != 1) {
printf(" ** zfs_devread() read error **\n");
return 1;
}
@@ -78,16 +79,18 @@
u8 p[SECTOR_SIZE];
block_len = SECTOR_SIZE;
- zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev,
- part_info->start + sector,
- 1, (unsigned long *)p);
+ zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)p);
memcpy(buf, p, byte_len);
return 0;
}
- if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev,
- part_info->start + sector, block_len / SECTOR_SIZE,
- (unsigned long *) buf) != block_len / SECTOR_SIZE) {
+ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector,
+ block_len / SECTOR_SIZE,
+ (void *)buf)
+ != block_len / SECTOR_SIZE) {
printf(" ** zfs_devread() read error - block\n");
return 1;
}
@@ -99,10 +102,9 @@
if (byte_len != 0) {
/* read rest of data which are not in whole sector */
- if (zfs_block_dev_desc->
- block_read(zfs_block_dev_desc->dev,
- part_info->start + sector, 1,
- (unsigned long *) sec_buf) != 1) {
+ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
+ part_info->start + sector,
+ 1, (void *)sec_buf) != 1) {
printf(" ** zfs_devread() read error - last part\n");
return 1;
}
diff --git a/include/addr_map.h b/include/addr_map.h
index dda4d6e..63b24cd 100644
--- a/include/addr_map.h
+++ b/include/addr_map.h
@@ -4,19 +4,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <asm/types.h>
diff --git a/include/ahci.h b/include/ahci.h
index 0bdedac..a956c6f 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -145,7 +145,11 @@
};
struct ahci_probe_ent {
+#ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+#else
pci_dev_t dev;
+#endif
struct ahci_ioports port[AHCI_MAX_PORTS];
u32 n_ports;
u32 hard_port_no;
diff --git a/include/bios_emul.h b/include/bios_emul.h
index 3643b82..80979ed 100644
--- a/include/bios_emul.h
+++ b/include/bios_emul.h
@@ -42,7 +42,7 @@
int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp);
/* Run a BIOS ROM natively (only supported on x86 machines) */
-void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
struct vbe_mode_info *mode_info);
/**
diff --git a/include/command.h b/include/command.h
index 2ae9b6c..0524c0b 100644
--- a/include/command.h
+++ b/include/command.h
@@ -110,6 +110,7 @@
char *const argv[]);
extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/*
* Error codes that commands return to cmd_process(). We use the standard 0
diff --git a/include/common.h b/include/common.h
index 75c78d5..7bed0cc 100644
--- a/include/common.h
+++ b/include/common.h
@@ -224,32 +224,26 @@
void board_init_r(gd_t *, ulong) __attribute__ ((noreturn));
/**
- * board_init_f_mem() - Allocate global data and set stack position
+ * ulong board_init_f_alloc_reserve - allocate reserved area
*
* This function is called by each architecture very early in the start-up
- * code to set up the environment for board_init_f(). It allocates space for
- * global_data (see include/asm-generic/global_data.h) and places the stack
- * below this.
+ * code to allow the C runtime to reserve space on the stack for writable
+ * 'globals' such as GD and the malloc arena.
*
- * This function requires a stack[1] Normally this is at @top. The function
- * starts allocating space from 64 bytes below @top. First it creates space
- * for global_data. Then it calls arch_setup_gd() which sets gd to point to
- * the global_data space and can reserve additional bytes of space if
- * required). Finally it allocates early malloc() memory
- * (CONFIG_SYS_MALLOC_F_LEN). The new top of the stack is just below this,
- * and it returned by this function.
+ * @top: top of the reserve area, growing down.
+ * @return: bottom of reserved area
+ */
+ulong board_init_f_alloc_reserve(ulong top);
+
+/**
+ * board_init_f_init_reserve - initialize the reserved area(s)
*
- * [1] Strictly speaking it would be possible to implement this function
- * in C on many archs such that it does not require a stack. However this
- * does not seem hugely important as only 64 byte are wasted. The 64 bytes
- * are used to handle the calling standard which generally requires pushing
- * addresses or registers onto the stack. We should be able to get away with
- * less if this becomes important.
+ * This function is called once the C runtime has allocated the reserved
+ * area on the stack. It must initialize the GD at the base of that area.
*
- * @top: Top of available memory, also normally the top of the stack
- * @return: New stack location
+ * @base: top from which reservation was done
*/
-ulong board_init_f_mem(ulong top);
+void board_init_f_init_reserve(ulong base);
/**
* arch_setup_gd() - Set up the global_data pointer
diff --git a/include/common_timing_params.h b/include/common_timing_params.h
index 821de21..b97147d 100644
--- a/include/common_timing_params.h
+++ b/include/common_timing_params.h
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef COMMON_TIMING_PARAMS_H
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h
index 6e299f6..3b198ae 100644
--- a/include/config_uncmd_spl.h
+++ b/include/config_uncmd_spl.h
@@ -29,7 +29,6 @@
#endif
#undef CONFIG_DM_WARN
-#undef CONFIG_DM_SEQ_ALIAS
#undef CONFIG_DM_STDIO
#endif /* CONFIG_SPL_BUILD */
diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index 8a91cdb..8dfe2a8 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -54,19 +54,6 @@
#define CONFIG_LMB
/*
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- */
-#define CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
-#define CONFIG_ENV_ADDR 0xf4040000
-
-/*
* MEMORY ORGANIZATION
* -Monitor at top of sdram.
* -The heap is placed below the monitor
@@ -76,13 +63,26 @@
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
+#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MALLOC_LEN 0x20000
/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
+#define CONFIG_ENV_ADDR (0xf4000000 + CONFIG_SYS_MONITOR_LEN)
+
+/*
* MISC
*/
#define CONFIG_SYS_LONGHELP /* Provide extended help */
@@ -92,12 +92,15 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + \
16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
CONFIG_ENV_SIZE - \
CONFIG_SYS_MALLOC_LEN - \
0x10000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#endif /* __CONFIG_H */
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index 2ecdd5d..2e94b69 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -57,19 +57,6 @@
#define CONFIG_LMB
/*
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- */
-#define CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
-#define CONFIG_ENV_ADDR 0xe2840000
-
-/*
* MEMORY ORGANIZATION
* -Monitor at top of sdram.
* -The heap is placed below the monitor
@@ -79,13 +66,26 @@
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
+#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MALLOC_LEN 0x20000
/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
+#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
+#define CONFIG_ENV_ADDR (0xe2800000 + CONFIG_SYS_MONITOR_LEN)
+
+/*
* MISC
*/
#define CONFIG_SYS_LONGHELP /* Provide extended help */
@@ -95,12 +95,15 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + \
16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
CONFIG_ENV_SIZE - \
CONFIG_SYS_MALLOC_LEN - \
0x10000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 8160b28..f8aef2e 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -1,9 +1,7 @@
/*
* Copyright 2007-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index c51db8c..cf6a606 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -18,10 +18,6 @@
#include <configs/ti_am335x_common.h>
-/* Don't override the distro default bootdelay */
-#undef CONFIG_BOOTDELAY
-#include <config_distro_defaults.h>
-
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_FIT
# define CONFIG_FIT
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index aac550a..de7538f 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -142,6 +142,8 @@
*/
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
#endif
#ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 650d97d..98fff63 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -95,14 +95,14 @@
/*
* Ethernet PHY configuration
*/
-#define CONFIG_PHYLIB
#define CONFIG_MII
#define CONFIG_PHY_GIGE
/*
- * Ethernet configuration
+ * USB 1.1 configuration
*/
-#define CONFIG_DW_AUTONEG
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
/*
* Commands still not supported in Kconfig
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index 131f613..a257084 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -142,7 +142,7 @@
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 0
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USBID_ADDR 0x34052c46
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index 3bed9a4..89c7446 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 0e353b9..b5d4847 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -75,7 +75,6 @@
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_CMD_MII
#define CONFIG_MII
-#define CONFIG_PHYLIB
/* i2c Settings */
#define CONFIG_SYS_I2C
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index c26a25c..fc2dc5a 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
diff --git a/include/configs/chromebook_jerry.h b/include/configs/chromebook_jerry.h
index 058325c..e29d776 100644
--- a/include/configs/chromebook_jerry.h
+++ b/include/configs/chromebook_jerry.h
@@ -13,5 +13,6 @@
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPI_FLASH_GIGADEVICE
#endif
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
new file mode 100644
index 0000000..f0de827
--- /dev/null
+++ b/include/configs/clearfog.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_CLEARFOG_H
+#define _CONFIG_CLEARFOG_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SDHCI
+#define CONFIG_MV_SDHCI
+#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
+
+/* Partition support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_ENV_MIN_ENTRIES 128
+
+/* Environment in MMC */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SECT_SIZE 0x200
+#define CONFIG_ENV_SIZE 0x10000
+/*
+ * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC
+ * boot image starts @ LBA-0.
+ * As result in MMC/eMMC case it will be a 1 sector gap between u-boot
+ * image and environment
+ */
+#define CONFIG_ENV_OFFSET 0xf0000
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
+ * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
+ */
+#define SPL_BOOT_SPI_NOR_FLASH 1
+#define SPL_BOOT_SDIO_MMC_CARD 2
+#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE (140 << 10)
+#define CONFIG_SPL_TEXT_BASE 0x40000030
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+/* SPL related MMC defines */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR ((CONFIG_SYS_U_BOOT_OFFS / 512)\
+ + 1)
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
+#endif
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_CLEARFOG_H */
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index bc7cac4..99b3aef 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -476,6 +476,7 @@
#define CONFIG_CMD_EXT2
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL
/* _VIA_CONTROL_EP */
#define CONFIG_CONSOLE_MUX
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index 944e82f..fdfda6b 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 3673e5e..ef14132 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -10,15 +10,7 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_ARMADA_XP /* SOC Family Name */
-#define CONFIG_ARMADA_38X
-#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
-#define CONFIG_SYS_L2_PL310
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
@@ -99,16 +91,15 @@
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 1, 0 }
-#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_E1000 /* enable Intel E1000 support for testing */
+#endif
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
@@ -139,9 +130,9 @@
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
@@ -158,7 +149,7 @@
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
@@ -176,10 +167,6 @@
#endif
#endif
-/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR_A38X
-#define CONFIG_DDR3
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index ab6e5a5..c8b0344 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -10,12 +10,8 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_ARMADA_XP /* SOC Family Name */
#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
@@ -30,13 +26,18 @@
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
+#define CONFIG_CMD_SATA
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT
@@ -64,48 +65,29 @@
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 }
-#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_RESET_PHY_R
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
/* SATA support */
-#ifdef CONFIG_CMD_IDE
-#define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE
-
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
-
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS
-
-/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
-
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA_MV
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_EFI_PARTITION
#define CONFIG_DOS_PARTITION
-#endif /* CONFIG_CMD_IDE */
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_E1000 /* enable Intel E1000 support for testing */
+#endif
/* NAND */
#define CONFIG_SYS_NAND_USE_FLASH_BBT
@@ -139,9 +121,9 @@
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
@@ -161,7 +143,7 @@
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_SPD_EEPROM 0x4e
+#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index d89e661..99d9148 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -33,7 +33,7 @@
#define CONFIG_SYS_MALLOC_LEN SZ_1M
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M
-#define CONFIG_SYS_TEXT_BASE 0x83FA0000
+#define CONFIG_SYS_TEXT_BASE 0x83F00000
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
@@ -49,6 +49,13 @@
#define CONFIG_BAUDRATE 115200
/*
+ * DMA
+ */
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_DMA_LPC32XX
+#endif
+
+/*
* I2C
*/
#define CONFIG_SYS_I2C
@@ -114,9 +121,19 @@
#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
/*
+ * USB
+ */
+#define CONFIG_USB_OHCI_LPC32XX
+#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+/*
* U-Boot General Configurations
*/
#define CONFIG_SYS_LONGHELP
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 81070b1..9d62421 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -142,6 +142,11 @@
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
#define CONFIG_QSPI_QUAD_SUPPORT
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#endif
+
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x010000 : QSPI.SPL (64KiB)
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
new file mode 100644
index 0000000..e3c7087
--- /dev/null
+++ b/include/configs/ds414.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_SYNOLOGY_DS414_H
+#define _CONFIG_SYNOLOGY_DS414_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_USB
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define CONFIG_PHY_ADDR { 0x1, 0x0 }
+#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* USB/EHCI/XHCI configuration */
+
+#define CONFIG_DM_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* FIXME: broken XHCI support
+ * Below defines should enable support for the two rear USB3 ports. Sadly, this
+ * does not work because:
+ * - xhci-pci seems to not support DM_USB, so with that enabled it is not
+ * found.
+ * - USB init fails, controller does not respond in time */
+#if 0
+#undef CONFIG_DM_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_PCI
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if !defined(CONFIG_USB_XHCI)
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif
+
+/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_SYS_MVFS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
+ * 0x4000.4030 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
+ * 0x4007.fffc BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40004030
+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
+
+/* DS414 bus width is 32bits */
+#define CONFIG_DDR_32BIT
+
+/* Use random ethernet address if not configured */
+#define CONFIG_LIB_RAND
+#define CONFIG_NET_RANDOM_ETHADDR
+
+/* Default Environment */
+#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+#define CONFIG_LOADADDR 0x80000
+#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */
+#define CONFIG_PREBOOT "usb start; sf probe"
+
+#endif /* _CONFIG_SYNOLOGY_DS414_H */
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index ec1f882..d101a77 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -51,8 +51,8 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_USB_GADGET_DWC2_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index eb16a5e..14a42b1 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -45,7 +45,6 @@
/* 10/100M Ethernet support */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_PHYLIB
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h
new file mode 100644
index 0000000..aa07889
--- /dev/null
+++ b/include/configs/kylin_rk3036.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rk3036_common.h>
+
+#endif
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 3faac37..aecc8ce 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -7,9 +7,6 @@
#ifndef _MALTA_CONFIG_H
#define _MALTA_CONFIG_H
-#include <asm/addrspace.h>
-#include <asm/malta.h>
-
/*
* System configuration
*/
@@ -83,14 +80,14 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (115200 * 16)
-#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE)
-#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
+#define CONFIG_SYS_NS16550_COM1 0xb80003f8
+#define CONFIG_SYS_NS16550_COM2 0xbb0003f8
#define CONFIG_CONS_INDEX 1
/*
* Flash configuration
*/
-#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE)
+#define CONFIG_SYS_FLASH_BASE 0xbe000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_CFI
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index da49243..43d7fd0 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -10,10 +10,6 @@
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_ARMADA_XP /* SOC Family Name */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
@@ -55,10 +51,7 @@
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 }
-#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_RESET_PHY_R
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
@@ -91,9 +84,9 @@
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
- CONFIG_SPL_BSS_MAX_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
@@ -112,7 +105,7 @@
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
+#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 06f6ed1..f93861d 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -68,10 +68,6 @@
# define CONFIG_XILINX_EMACLITE 1
# define CONFIG_SYS_ENET
#endif
-#if defined(XILINX_LLTEMAC_BASEADDR)
-# define CONFIG_XILINX_LL_TEMAC 1
-# define CONFIG_SYS_ENET
-#endif
#if defined(XILINX_AXIEMAC_BASEADDR)
# define CONFIG_XILINX_AXIEMAC 1
# define CONFIG_SYS_ENET
@@ -101,8 +97,10 @@
#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
-# define CONFIG_HW_WATCHDOG
-# define CONFIG_XILINX_TB_WATCHDOG
+# ifndef CONFIG_SPL_BUILD
+# define CONFIG_HW_WATCHDOG
+# define CONFIG_XILINX_TB_WATCHDOG
+# endif
#endif
#if !defined(CONFIG_OF_CONTROL) || \
@@ -113,15 +111,10 @@
#endif
#define CONFIG_SYS_MALLOC_LEN 0xC0000
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_SYS_MALLOC_F_LEN 1024
-#else
-# define CONFIG_SYS_MALLOC_SIMPLE
-# define CONFIG_SYS_MALLOC_F_LEN 0x150
-#endif
/* Stack location before relocation */
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
+ CONFIG_SYS_MALLOC_F_LEN)
/*
* CFI flash memory layout - Example
@@ -360,7 +353,7 @@
#define CONFIG_FIT 1
#define CONFIG_OF_LIBFDT 1
-#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
+#if defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII 1
# define CONFIG_CMD_MII 1
# define CONFIG_PHY_GIGE 1
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 1fd7ce3..174ea08 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __MX6_COMMON_H
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 2712b27..c946176 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -241,6 +241,7 @@
#define CONFIG_IMX_THERMAL
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
@@ -257,5 +258,6 @@
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
+#endif
#endif
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 870e12e..d507fb4 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -36,6 +36,8 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_FSL_CLK
+
#define CONFIG_LOADADDR 0x80800000
#define CONFIG_SYS_TEXT_BASE 0x87800000
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 4b4f2d7..5f0a230 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -16,6 +16,7 @@
#define CONFIG_FIT
#define CONFIG_KEYBOARD
+#include <config_distro_defaults.h>
#include "mx6_common.h"
/* U-Boot Commands */
@@ -58,7 +59,7 @@
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttymxc1,115200 "
-#define CONFIG_BOOTCOMMAND "run net_nfs"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run net_nfs"
#define CONFIG_HOSTNAME novena
/* Physical Memory Map */
@@ -190,6 +191,7 @@
#endif
/* Extra U-Boot environment. */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
@@ -199,6 +201,11 @@
"rootdev=/dev/mmcblk0p2\0" \
"netdev=eth0\0" \
"kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \
+ "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \
+ "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \
+ "ramdisk_addr_r=0x28000000\0" \
+ "fdt_addr_r=0x18000000\0" \
+ "fdtfile=imx6q-novena.dtb\0" \
"addcons=" \
"setenv bootargs ${bootargs} " \
"console=${consdev},${baudrate}\0" \
@@ -242,5 +249,19 @@
"fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\
"fi ; " \
"fi\0" \
+ BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(SATA, sata, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS
+#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_H */
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 4633fec..bce4fad 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -5,19 +5,7 @@
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 8eac81a..d9dd9bd 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -4,14 +4,7 @@
* See file CREDITS for list of people who contributed to this
* project.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index f753e68..d22ea74 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -24,6 +24,8 @@
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CONFIG_SPL_SERIAL_SUPPORT
+
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 2877e19..8f65d7e 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -269,8 +269,8 @@
#define CONFIG_SYS_MAX_I2C_BUS 7
#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_USB_GADGET_DWC2_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_USB_MASS_STORAGE
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 35fef2b..7bb62ca 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -177,8 +177,8 @@
#define CONFIG_POWER_MAX8998
#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_USB_GADGET_DWC2_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
/*
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 217cfc0..2492f99 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -13,8 +13,8 @@
#undef CONFIG_BOARD_COMMON
#undef CONFIG_USB_GADGET
-#undef CONFIG_USB_GADGET_S3C_UDC_OTG
-#undef CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
+#undef CONFIG_USB_GADGET_DWC2_OTG
+#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
#undef CONFIG_CMD_USB_MASS_STORAGE
#undef CONFIG_REVISION_TAG
#undef CONFIG_CMD_THOR_DOWNLOAD
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 08046b5..a995415 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -126,21 +126,9 @@
*/
#define CONFIG_PARTITION_UUIDS
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
#define CONFIG_CMD_PART
/*
- * Filesystems
- */
-
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-
-/*
* SPL
*/
@@ -257,16 +245,24 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0x82000000\0" \
+ "loadaddr=0x82000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "fdtaddr=0x88000000\0" \
+ "ramdisk_addr_r=0x88080000\0" \
+ "pxefile_addr_r=0x80100000\0" \
+ "scriptaddr=0x80000000\0" \
+ "bootm_size=0x10000000\0" \
"boot_mmc_dev=0\0" \
"kernel_mmc_part=3\0" \
"recovery_mmc_part=4\0" \
+ "fdtfile=omap3-sniper.dtb\0" \
+ "bootfile=/boot/extlinux/extlinux.conf\0" \
"bootargs=console=ttyO2 vram=5M,0x9FA00000 omapfb.vram=0:5M\0"
/*
- * ATAGs / Device Tree
+ * ATAGs
*/
-#define CONFIG_OF_LIBFDT
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
@@ -278,7 +274,6 @@
*/
#define CONFIG_SYS_LOAD_ADDR 0x82000000
-#define CONFIG_BOOTDELAY 1
#define CONFIG_ANDROID_BOOT_IMAGE
@@ -299,5 +294,6 @@
*/
#include <config_defaults.h>
+#include <config_distro_defaults.h>
#endif
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index ebb6ed5..a0161bc 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -47,30 +47,13 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Altera"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_arria5
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
@@ -87,11 +70,13 @@
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index b3f65b6..8de0ab9 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
-#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#ifndef __CONFIG_SOCFPGA_COMMON_H__
+#define __CONFIG_SOCFPGA_COMMON_H__
/* Virtual target or real hardware */
@@ -69,6 +69,10 @@
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
+#ifndef CONFIG_SYS_HOSTNAME
+#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
+#endif
+
/*
* Cache
*/
@@ -105,7 +109,6 @@
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
-#define CONFIG_PHYLIB
#define CONFIG_PHY_GIGE
#endif
@@ -158,6 +161,19 @@
#endif
/*
+ * NAND Support
+ */
+#ifdef CONFIG_NAND_DENALI
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_DENALI_ECC_SIZE 512
+#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
+#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
+#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
+#endif
+
+/*
* I2C support
*/
#define CONFIG_SYS_I2C
@@ -193,7 +209,7 @@
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT "nor0=ff705000.spi"
+#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
@@ -229,13 +245,6 @@
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2
#define CONFIG_USB_STORAGE
-/*
- * NOTE: User must define either of the following to select which
- * of the two USB controllers available on SoCFPGA to use.
- * The DWC2 driver doesn't support multiple USB controllers.
- * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
- * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
- */
#endif
/*
@@ -243,7 +252,7 @@
*/
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
@@ -252,7 +261,9 @@
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_FUNCTION_DFU
+#ifdef CONFIG_DM_MMC
#define CONFIG_DFU_MMC
+#endif
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300
@@ -262,7 +273,7 @@
#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
#ifndef CONFIG_G_DNL_MANUFACTURER
-#define CONFIG_G_DNL_MANUFACTURER "Altera"
+#define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR
#endif
#endif
@@ -274,6 +285,43 @@
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_ENV_SIZE 4096
+/* Environment for SDMMC boot */
+#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+#endif
+
+/*
+ * mtd partitioning for serial NOR flash
+ *
+ * device nor0 <ff705000.spi.0>, # parts = 6
+ * #: name size offset mask_flags
+ * 0: u-boot 0x00100000 0x00000000 0
+ * 1: env1 0x00040000 0x00100000 0
+ * 2: env2 0x00040000 0x00140000 0
+ * 3: UBI 0x03e80000 0x00180000 0
+ * 4: boot 0x00e80000 0x00180000 0
+ * 5: rootfs 0x01000000 0x01000000 0
+ *
+ */
+#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
+#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\
+ "1m(u-boot)," \
+ "256k(env1)," \
+ "256k(env2)," \
+ "14848k(boot)," \
+ "16m(rootfs)," \
+ "-@1536k(UBI)\0"
+#endif
+
+/* UBI and UBIFS support */
+#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#endif
+
/*
* SPL
*
@@ -297,8 +345,15 @@
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_DM_MMC
#define CONFIG_SPL_MMC_SUPPORT
+#endif
+#ifdef CONFIG_DM_SPI
#define CONFIG_SPL_SPI_SUPPORT
+#endif
+#ifdef CONFIG_SPL_NAND_DENALI
+#define CONFIG_SPL_NAND_SUPPORT
+#endif
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
@@ -315,15 +370,21 @@
/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_DM_SEQ_ALIAS 1
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#endif
+/* SPL NAND boot support */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#endif
+
/*
* Stack setup
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
+#endif /* __CONFIG_SOCFPGA_COMMON_H__ */
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index 67bb35f..c4c4ecb 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -47,30 +47,13 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Altera"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_cyclone5
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
@@ -87,11 +70,13 @@
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index 16e146c..cbc7396 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -37,36 +37,19 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9031
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Terasic"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_de0_nano_soc
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index d051eec..e7b5675 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -45,18 +45,8 @@
/* Environment is in MMC */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "DENX"
/* Extra Environment */
-#define CONFIG_HOSTNAME mcvevk
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttyS0\0" \
"baudrate=115200\0" \
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 5bcee05..95e7ba6 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -37,40 +37,19 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Terasic"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_sockit
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
@@ -87,6 +66,13 @@
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index 16a2a86..c32a40a 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -43,30 +43,13 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "EBV"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_socrates
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index bccb235..fdf67ca 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -53,9 +53,6 @@
#define CONFIG_PHY_MARVELL
#define PHY_ANEG_TIMEOUT 8000
-/* Extra Environment */
-#define CONFIG_HOSTNAME sr1500
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
@@ -73,11 +70,13 @@
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* Environment */
#define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 1d69477..d2630f4 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -17,7 +17,6 @@
/* Ethernet driver configuration */
#define CONFIG_MII
-#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 14c6a9e..f421321 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -53,7 +53,6 @@
/* GMAC related configs */
#define CONFIG_MII
-#define CONFIG_PHYLIB
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_PHY_MICREL
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index da6ab61..790e704 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -309,11 +309,9 @@
#endif
#ifdef CONFIG_SUNXI_GMAC
-#define CONFIG_DW_AUTONEG
#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
-#define CONFIG_PHYLIB
#endif
#ifdef CONFIG_USB_EHCI_HCD
@@ -419,8 +417,14 @@
#ifdef CONFIG_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
+#define BOOT_TARGET_DEVICES_MMC_EXTRA(func) func(MMC, mmc, 1)
+#else
+#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
+#endif
#else
#define BOOT_TARGET_DEVICES_MMC(func)
+#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
#endif
#ifdef CONFIG_AHCI
@@ -448,6 +452,7 @@
#define BOOT_TARGET_DEVICES(func) \
func(FEL, fel, na) \
BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_MMC_EXTRA(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index ec0a812..2d941ca 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -384,7 +384,7 @@
if (i) \
sprintf(ethname, "eth%daddr", i); \
else \
- sprintf(ethname, "ethaddr"); \
+ strcpy(ethname, "ethaddr"); \
printf("Setting %s from EEPROM with %s\n", ethname, buf);\
setenv(ethname, buf); \
} \
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 8660ed4..e06484f 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -42,7 +42,6 @@
/*
* Ethernet PHY configuration
*/
-#define CONFIG_PHYLIB
#define CONFIG_PHY_GIGE
/*
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 671071b..21454d4 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA114_COMMON_H_
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 2087eb1..199612b 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -283,5 +283,6 @@
#endif
#include <config_distro_defaults.h>
+#define CONFIG_CMD_EXT4_WRITE
#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 08130eb..8b6c065 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -82,6 +82,32 @@
/*
* Environment setup
*/
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "setenv mmcdev " #instance"; "\
+ "setenv bootpart " #instance":2 ; "\
+ "run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(LEGACY_MMC, legacy_mmc, 1) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
@@ -120,30 +146,7 @@
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadbootenv; then " \
- "run importbootenv; " \
- "fi;" \
- "if test -n ${uenvcmd}; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "fi;" \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcboot; " \
- "fi; " \
- "if run loaduimage; then " \
- "run uimageboot;" \
- "fi; " \
- "fi"
+ BOOTENV
/*
* Defines for SPL
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 0562598..463c687 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -188,14 +188,14 @@
"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
"bootm $fit_addr_r\0"
#else
-#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_BOOTFILE "zImage"
#define LINUXBOOT_ENV_SETTINGS \
"fdt_addr=0x00100000\0" \
"fdt_addr_r=0x84100000\0" \
"fdt_size=0x00008000\0" \
- "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"kernel_addr=0x00200000\0" \
- "kernel_addr_r=0x84200000\0" \
+ "kernel_addr_r=0x80208000\0" \
"kernel_size=0x00800000\0" \
"ramdisk_addr=0x00a00000\0" \
"ramdisk_addr_r=0x84a00000\0" \
@@ -204,15 +204,15 @@
"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
"setexpr fdt_addr $nor_base + $fdt_addr &&" \
- "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
+ "bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \
"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
- "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
+ "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
"tftpboot $fdt_addr_r $fdt_file &&" \
- "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
+ "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index c767f90..814934a 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -189,7 +189,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_name=norkern\0" \
"kernel_alt_name=Image\0" \
- "kernel_addr=0x80000000\0" \
+ "kernel_addr=0x80080000\0" \
"initrd_name=ramdisk.img\0" \
"initrd_addr=0x84000000\0" \
"fdt_name=board.dtb\0" \
@@ -233,7 +233,7 @@
#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_name=Image\0" \
- "kernel_addr=0x80000000\0" \
+ "kernel_addr=0x80080000\0" \
"initrd_name=ramdisk.img\0" \
"initrd_addr=0x88000000\0" \
"fdt_name=devtree.dtb\0" \
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 58f1aca..0263c50 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -77,7 +77,6 @@
/* Ethernet config options */
#define CONFIG_MII
-#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 70ec103..4182a3b 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -208,6 +208,7 @@
#define CONFIG_HOSTNAME x86
#define CONFIG_BOOTFILE "bzImage"
#define CONFIG_LOADADDR 0x1000000
+#define CONFIG_RAMDISK_ADDR 0x4000000
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_STD_DEVICES_SETTINGS \
@@ -215,7 +216,7 @@
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"othbootargs=acpi=off\0" \
- "ramdiskaddr=0x2000000\0" \
+ "ramdiskaddr=0x4000000\0" \
"ramdiskfile=initramfs.gz\0"
#define CONFIG_RAMBOOTCOMMAND \
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 50ac5f5..03f7450 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -188,7 +188,6 @@
# define CONFIG_NET_MULTI
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_PHYLIB
# define CONFIG_PHY_MARVELL
# define CONFIG_PHY_TI
#endif
diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h
index 5d1a9d5..c53ba79 100644
--- a/include/configs/zynq_zybo.h
+++ b/include/configs/zynq_zybo.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ZYNQ_USB
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_BOOT_FREEBSD
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index cf2aac6..d71cd9a 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _DDR_SPD_H_
diff --git a/include/dm/device.h b/include/dm/device.h
index 7fb9935..1cf8150 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -454,6 +454,17 @@
fdt_addr_t dev_get_addr(struct udevice *dev);
/**
+ * dev_get_addr_index() - Get the indexed reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return addr
+ */
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);
+
+/**
* device_has_children() - check if a device has any children
*
* @dev: Device to check
@@ -776,4 +787,25 @@
#endif /* ! CONFIG_DEVRES */
+/**
+ * dm_set_translation_offset() - Set translation offset
+ * @offs: Translation offset
+ *
+ * Some platforms need a special address translation. Those
+ * platforms (e.g. mvebu in SPL) can configure a translation
+ * offset in the DM by calling this function. It will be
+ * added to all addresses returned in dev_get_addr().
+ */
+void dm_set_translation_offset(fdt_addr_t offs);
+
+/**
+ * dm_get_translation_offset() - Get translation offset
+ *
+ * This function returns the translation offset that can
+ * be configured by calling dm_set_translation_offset().
+ *
+ * @return translation offset for the device address (0 as default).
+ */
+fdt_addr_t dm_get_translation_offset(void);
+
#endif
diff --git a/include/dm/platform_data/lpc32xx_hsuart.h b/include/dm/platform_data/lpc32xx_hsuart.h
new file mode 100644
index 0000000..fd191b5
--- /dev/null
+++ b/include/dm/platform_data/lpc32xx_hsuart.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _LPC32XX_HSUART_PLAT_H
+#define _LPC32XX_HSUART_PLAT_H
+
+/**
+ * struct lpc32xx_hsuart_platdata - NXP LPC32xx HSUART platform data
+ *
+ * @base: Base register address
+ */
+struct lpc32xx_hsuart_platdata {
+ unsigned long base;
+};
+
+#endif
diff --git a/include/ds4510.h b/include/ds4510.h
index 40480af..e54db35 100644
--- a/include/ds4510.h
+++ b/include/ds4510.h
@@ -1,19 +1,7 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __DS4510_H_
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
index ebafa49..638b114 100644
--- a/include/dt-bindings/pinctrl/pinctrl-tegra.h
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h
@@ -5,14 +5,7 @@
*
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 7fe657d..27b350e 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -167,8 +167,10 @@
COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */
COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
+ COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
+ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_COUNT,
};
@@ -444,32 +446,15 @@
/**
* Look at the pci address of a device node that represents a PCI device
- * and parse the bus, device and function number from it. For some cases
- * like the bus number encoded in reg property is not correct after pci
- * enumeration, this function looks through the node's compatible strings
- * to get these numbers extracted instead.
- *
- * @param blob FDT blob
- * @param node node to examine
- * @param addr pci address in the form of fdt_pci_addr
- * @param bdf returns bus, device, function triplet
- * @return 0 if ok, negative on error
- */
-int fdtdec_get_pci_bdf(const void *blob, int node,
- struct fdt_pci_addr *addr, pci_dev_t *bdf);
-
-/**
- * Look at the pci address of a device node that represents a PCI device
* and return base address of the pci device's registers.
*
- * @param blob FDT blob
- * @param node node to examine
+ * @param dev device to examine
* @param addr pci address in the form of fdt_pci_addr
* @param bar returns base address of the pci device's registers
* @return 0 if ok, negative on error
*/
-int fdtdec_get_pci_bar32(const void *blob, int node,
- struct fdt_pci_addr *addr, u32 *bar);
+int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr,
+ u32 *bar);
/**
* Look up a 32-bit integer property in a node and return it. The property
diff --git a/include/fs.h b/include/fs.h
index 059a395..2f2aca8 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _FS_H
#define _FS_H
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 9aaf6b3..3351acd 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef FSL_DDR_MAIN_H
diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h
index 751e935..12a1944 100644
--- a/include/fsl_ddr_dimm_params.h
+++ b/include/fsl_ddr_dimm_params.h
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef DDR2_DIMM_PARAMS_H
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 4b022d4..9ea8b63 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -1,9 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef FSL_DDR_MEMCTL_H
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index aa1b4cf..073048f 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -25,10 +25,12 @@
#define SYSCTL_INITA 0x08000000
#define SYSCTL_TIMEOUT_MASK 0x000f0000
#define SYSCTL_CLOCK_MASK 0x0000fff0
+#if !defined(CONFIG_FSL_USDHC)
#define SYSCTL_CKEN 0x00000008
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
+#endif
#define SYSCTL_RSTA 0x01000000
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000
diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h
index d15a70c..f698d4d 100644
--- a/include/fsl_wdog.h
+++ b/include/fsl_wdog.h
@@ -16,3 +16,4 @@
#define WCR_WDT 0x08
#define WCR_SRS 0x10
#define SET_WCR_WT(x) (x << 8)
+#define WCR_WT_MSK SET_WCR_WT(0xFF)
diff --git a/include/hash.h b/include/hash.h
index e6d0f1d..d814337 100644
--- a/include/hash.h
+++ b/include/hash.h
@@ -114,21 +114,6 @@
int hash_block(const char *algo_name, const void *data, unsigned int len,
uint8_t *output, int *output_size);
-/**
- * hash_show() - Print out a hash algorithm and value
- *
- * You will get a message like this (without a newline at the end):
- *
- * "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257"
- *
- * @algo: Algorithm used for hash
- * @addr: Address of data that was hashed
- * @len: Length of data that was hashed
- * @output: Hash value to display
- */
-void hash_show(struct hash_algo *algo, ulong addr, ulong len,
- uint8_t *output);
-
#endif /* !USE_HOSTCC */
/**
diff --git a/include/ide.h b/include/ide.h
index d5e05e9..f9357be 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -28,21 +28,23 @@
#ifdef CONFIG_SYS_64BIT_LBA
typedef uint64_t lbaint_t;
-#define LBAF "%llx"
-#define LBAFU "%llu"
+#define LBAFlength "ll"
#else
typedef ulong lbaint_t;
-#define LBAF "%lx"
-#define LBAFU "%lu"
+#define LBAFlength "l"
#endif
+#define LBAF "%" LBAFlength "x"
+#define LBAFU "%" LBAFlength "u"
/*
* Function Prototypes
*/
void ide_init(void);
-ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer);
-ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt,
+typedef struct block_dev_desc block_dev_desc_t;
+ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer);
+ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer);
#ifdef CONFIG_IDE_PREINIT
diff --git a/include/linux/bch.h b/include/linux/bch.h
index 295b4ef..28da402 100644
--- a/include/linux/bch.h
+++ b/include/linux/bch.h
@@ -1,18 +1,7 @@
/*
* Generic binary BCH encoding/decoding library
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 51
- * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: GPL-2.0
*
* Copyright © 2011 Parrot S.A.
*
diff --git a/include/linux/edd.h b/include/linux/edd.h
index 4cbd0fe..a83742f 100644
--- a/include/linux/edd.h
+++ b/include/linux/edd.h
@@ -17,15 +17,7 @@
* information is used to identify BIOS boot disk. The code in setup.S
* is very sensitive to the size of these structures.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2.0 as published by
- * the Free Software Foundation
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _LINUX_EDD_H
#define _LINUX_EDD_H
diff --git a/include/linux/input.h b/include/linux/input.h
index 44aec76..3662c9f 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -1,9 +1,7 @@
/*
* Copyright (c) 1999-2002 Vojtech Pavlik
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _LINUX_INPUT_H
diff --git a/include/misc.h b/include/misc.h
index 7e9badf..2b78814 100644
--- a/include/misc.h
+++ b/include/misc.h
@@ -32,7 +32,7 @@
*
* @dev: the device
* @request: command to be sent to the device
- * @buf: pointer to buffer related to the requset
+ * @buf: pointer to buffer related to the request
* @return: 0 if OK, -ve on error
*/
int misc_ioctl(struct udevice *dev, unsigned long request, void *buf);
@@ -70,7 +70,7 @@
*
* @dev: the device
* @request: command to be sent to the device
- * @buf: pointer to buffer related to the requset
+ * @buf: pointer to buffer related to the request
* @return: 0 if OK, -ve on error
*/
int (*ioctl)(struct udevice *dev, unsigned long request, void *buf);
diff --git a/include/mmc.h b/include/mmc.h
index cda9a19..465daeb 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -121,7 +121,12 @@
#define OCR_VOLTAGE_MASK 0x007FFF80
#define OCR_ACCESS_MODE 0x60000000
-#define SECURE_ERASE 0x80000000
+#define MMC_ERASE_ARG 0x00000000
+#define MMC_SECURE_ERASE_ARG 0x80000000
+#define MMC_TRIM_ARG 0x00000001
+#define MMC_DISCARD_ARG 0x00000003
+#define MMC_SECURE_TRIM1_ARG 0x80000001
+#define MMC_SECURE_TRIM2_ARG 0x80008000
#define MMC_STATUS_MASK (~0x0206BF7F)
#define MMC_STATUS_SWITCH_ERROR (1 << 7)
@@ -359,7 +364,6 @@
u8 part_attr;
u8 wr_rel_set;
char part_config;
- char part_num;
uint tran_speed;
uint read_bl_len;
uint write_bl_len;
@@ -484,11 +488,9 @@
* This finds all the matching PCI IDs and sets them up as MMC devices.
*
* @name: Name to use for devices
- * @mmc_supported: PCI IDs to search for
- * @num_ids: Number of elements in @mmc_supported
+ * @mmc_supported: PCI IDs to search for, terminated by {0, 0}
*/
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
- int num_ids);
+int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
diff --git a/include/nand.h b/include/nand.h
index d2a53ab..7cbbbd3 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -3,12 +3,7 @@
* 2N Telekomunikace, a.s. <www.2n.cz>
* Ladislav Michl <michl@2n.cz>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _NAND_H_
diff --git a/include/net.h b/include/net.h
index ebed29a..ac44d61 100644
--- a/include/net.h
+++ b/include/net.h
@@ -181,8 +181,7 @@
extern struct eth_device *eth_current;
-static inline __attribute__((always_inline))
-struct eth_device *eth_get_dev(void)
+static __always_inline struct eth_device *eth_get_dev(void)
{
return eth_current;
}
@@ -200,14 +199,14 @@
/* Used only when NetConsole is enabled */
int eth_is_active(struct eth_device *dev); /* Test device for active state */
/* Set active state */
-static inline __attribute__((always_inline)) int eth_init_state_only(void)
+static __always_inline int eth_init_state_only(void)
{
eth_get_dev()->state = ETH_STATE_ACTIVE;
return 0;
}
/* Set passive state */
-static inline __attribute__((always_inline)) void eth_halt_state_only(void)
+static __always_inline void eth_halt_state_only(void)
{
eth_get_dev()->state = ETH_STATE_PASSIVE;
}
@@ -657,7 +656,7 @@
unsigned src_port, unsigned len);
#endif
-static inline __attribute__((always_inline)) int eth_is_on_demand_init(void)
+static __always_inline int eth_is_on_demand_init(void)
{
#ifdef CONFIG_NETCONSOLE
extern enum proto_t net_loop_last_protocol;
diff --git a/include/part.h b/include/part.h
index 720a867..4d00e22 100644
--- a/include/part.h
+++ b/include/part.h
@@ -10,12 +10,15 @@
#include <ide.h>
#include <common.h>
-typedef struct block_dev_desc {
+typedef struct block_dev_desc block_dev_desc_t;
+
+struct block_dev_desc {
int if_type; /* type of the interface */
int dev; /* device number */
unsigned char part_type; /* partition type */
unsigned char target; /* target SCSI ID */
unsigned char lun; /* target LUN */
+ unsigned char hwpart; /* HW partition, e.g. for eMMC */
unsigned char type; /* device type */
unsigned char removable; /* removable device */
#ifdef CONFIG_LBA48
@@ -27,19 +30,19 @@
char vendor [40+1]; /* IDE model, SCSI Vendor */
char product[20+1]; /* IDE Serial no, SCSI product */
char revision[8+1]; /* firmware revision */
- unsigned long (*block_read)(int dev,
+ unsigned long (*block_read)(block_dev_desc_t *block_dev,
lbaint_t start,
lbaint_t blkcnt,
void *buffer);
- unsigned long (*block_write)(int dev,
+ unsigned long (*block_write)(block_dev_desc_t *block_dev,
lbaint_t start,
lbaint_t blkcnt,
const void *buffer);
- unsigned long (*block_erase)(int dev,
+ unsigned long (*block_erase)(block_dev_desc_t *block_dev,
lbaint_t start,
lbaint_t blkcnt);
void *priv; /* driver private struct pointer */
-}block_dev_desc_t;
+};
#define BLOCK_CNT(size, block_dev_desc) (PAD_COUNT(size, block_dev_desc->blksz))
#define PAD_TO_BLOCKSIZE(size, block_dev_desc) \
diff --git a/include/pca953x.h b/include/pca953x.h
index 6c2b58c..8ed2d18 100644
--- a/include/pca953x.h
+++ b/include/pca953x.h
@@ -1,19 +1,7 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __PCA953X_H_
diff --git a/include/pci.h b/include/pci.h
index 2adca85..cb2562f 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -621,6 +621,7 @@
extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
#endif
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
pci_addr_t addr, unsigned long flags);
extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
@@ -656,7 +657,6 @@
pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
/* For driver model these are defined in macros in pci_compat.c */
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word(struct pci_controller *hose,
@@ -862,12 +862,12 @@
#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
/**
- * pci_get_bdf() - Get the BDF value for a device
+ * dm_pci_get_bdf() - Get the BDF value for a device
*
* @dev: Device to check
* @return bus/device/function value (see PCI_BDF())
*/
-pci_dev_t pci_get_bdf(struct udevice *dev);
+pci_dev_t dm_pci_get_bdf(struct udevice *dev);
/**
* pci_bind_bus_devices() - scan a PCI bus and bind devices
@@ -902,13 +902,13 @@
int pci_auto_config_devices(struct udevice *bus);
/**
- * pci_bus_find_bdf() - Find a device given its PCI bus address
+ * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
*
* @bdf: PCI device address: bus, device and function -see PCI_BDF()
* @devp: Returns the device for this address, if found
* @return 0 if OK, -ENODEV if not found
*/
-int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
+int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
/**
* pci_bus_find_devfn() - Find a device on a bus
@@ -995,7 +995,7 @@
* @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
* @return 0 if OK, -ve on error
*/
-int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf);
+int dm_pci_hose_probe_bus(struct udevice *bus);
/**
* pci_bus_read_config() - Read a configuration value from a device
@@ -1167,6 +1167,96 @@
struct pci_region **memp, struct pci_region **prefp);
/**
+ * dm_pci_read_bar32() - read a base address register from a device
+ *
+ * @dev: Device to check
+ * @barnum: Bar number to read (numbered from 0)
+ * @return: value of BAR
+ */
+u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
+
+/**
+ * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
+ *
+ * @dev: Device containing the PCI address
+ * @addr: PCI address to convert
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return physical address corresponding to that PCI bus address
+ */
+phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
+ unsigned long flags);
+
+/**
+ * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
+ *
+ * @dev: Device containing the bus address
+ * @addr: Physical address to convert
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return PCI bus address corresponding to that physical address
+ */
+pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
+ unsigned long flags);
+
+/**
+ * dm_pci_map_bar() - get a virtual address associated with a BAR region
+ *
+ * Looks up a base address register and finds the physical memory address
+ * that corresponds to it
+ *
+ * @dev: Device to check
+ * @bar: Bar number to read (numbered from 0)
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return: pointer to the virtual address to use
+ */
+void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
+
+#define dm_pci_virt_to_bus(dev, addr, flags) \
+ dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
+#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
+ map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
+ (len), (map_flags))
+
+#define dm_pci_phys_to_mem(dev, addr) \
+ dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_phys(dev, addr) \
+ dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_phys_to_io(dev, addr) \
+ dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_phys(dev, addr) \
+ dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+#define dm_pci_virt_to_mem(dev, addr) \
+ dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
+ dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
+#define dm_pci_virt_to_io(dev, addr) \
+ dm_dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
+ dm_dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+
+/**
+ * dm_pci_find_device() - find a device by vendor/device ID
+ *
+ * @vendor: Vendor ID
+ * @device: Device ID
+ * @index: 0 to find the first match, 1 for second, etc.
+ * @devp: Returns pointer to the device, if found
+ * @return 0 if found, -ve on error
+ */
+int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
+ struct udevice **devp);
+
+/**
+ * dm_pci_find_class() - find a device by class
+ *
+ * @find_class: 3-byte (24-bit) class value to find
+ * @index: 0 to find the first match, 1 for second, etc.
+ * @devp: Returns pointer to the device, if found
+ * @return 0 if found, -ve on error
+ */
+int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
+
+/**
* struct dm_pci_emul_ops - PCI device emulator operations
*/
struct dm_pci_emul_ops {
diff --git a/include/pci_rom.h b/include/pci_rom.h
index 2f1665d..95c6d07 100644
--- a/include/pci_rom.h
+++ b/include/pci_rom.h
@@ -44,14 +44,14 @@
};
/**
- * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
+ * dm_pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
*
* @dev: Video device containing the BIOS
* @int15_handler: Function to call to handle int 0x15
* @exec_method: flags from enum pci_rom_emul
*/
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void),
- int exec_method);
+int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
+ int exec_method);
/**
* board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
diff --git a/include/power/pmic.h b/include/power/pmic.h
index 6ba4b6e..e0b2e12 100644
--- a/include/power/pmic.h
+++ b/include/power/pmic.h
@@ -12,7 +12,6 @@
#define __CORE_PMIC_H_
#include <i2c.h>
-#include <spi.h>
#include <linux/list.h>
#include <power/power_chrg.h>
diff --git a/include/spi.h b/include/spi.h
index b4d2723..4b88d39 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -11,41 +11,27 @@
#define _SPI_H_
/* SPI mode flags */
-#define SPI_CPHA 0x01 /* clock phase */
-#define SPI_CPOL 0x02 /* clock polarity */
-#define SPI_MODE_0 (0|0) /* (original MicroWire) */
-#define SPI_MODE_1 (0|SPI_CPHA)
-#define SPI_MODE_2 (SPI_CPOL|0)
-#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
-#define SPI_CS_HIGH 0x04 /* CS active high */
-#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
-#define SPI_3WIRE 0x10 /* SI/SO signals shared */
-#define SPI_LOOP 0x20 /* loopback mode */
-#define SPI_SLAVE 0x40 /* slave mode */
-#define SPI_PREAMBLE 0x80 /* Skip preamble bytes */
+#define SPI_CPHA BIT(0) /* clock phase */
+#define SPI_CPOL BIT(1) /* clock polarity */
+#define SPI_MODE_0 (0|0) /* (original MicroWire) */
+#define SPI_MODE_1 (0|SPI_CPHA)
+#define SPI_MODE_2 (SPI_CPOL|0)
+#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
+#define SPI_CS_HIGH BIT(2) /* CS active high */
+#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
+#define SPI_3WIRE BIT(4) /* SI/SO signals shared */
+#define SPI_LOOP BIT(5) /* loopback mode */
+#define SPI_SLAVE BIT(6) /* slave mode */
+#define SPI_PREAMBLE BIT(7) /* Skip preamble bytes */
+#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */
+#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */
+#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */
-/* SPI transfer flags */
-#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
-#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
-#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
-#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
-#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE (1 << 5)
-
-/* SPI TX operation modes */
-#define SPI_OPM_TX_QPP (1 << 0)
-#define SPI_OPM_TX_BP (1 << 1)
-
-/* SPI RX operation modes */
-#define SPI_OPM_RX_AS (1 << 0)
-#define SPI_OPM_RX_AF (1 << 1)
-#define SPI_OPM_RX_DOUT (1 << 2)
-#define SPI_OPM_RX_DIO (1 << 3)
-#define SPI_OPM_RX_QOF (1 << 4)
-#define SPI_OPM_RX_QIOF (1 << 5)
-#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \
- SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
- SPI_OPM_RX_QIOF)
+/* SPI mode_rx flags */
+#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */
+#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */
+#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */
+#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */
/* SPI bus connection options - see enum spi_dual_flash */
#define SPI_CONN_DUAL_SHARED (1 << 0)
@@ -75,11 +61,13 @@
* @cs: Chip select number (0..n-1)
* @max_hz: Maximum bus speed that this slave can tolerate
* @mode: SPI mode to use for this device (see SPI mode flags)
+ * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
*/
struct dm_spi_slave_platdata {
unsigned int cs;
uint max_hz;
uint mode;
+ u8 mode_rx;
};
#endif /* CONFIG_DM_SPI */
@@ -99,15 +87,14 @@
*
* @dev: SPI slave device
* @max_hz: Maximum speed for this slave
- * @mode: SPI mode to use for this slave (see SPI mode flags)
* @speed: Current bus speed. This is 0 until the bus is first
* claimed.
* @bus: ID of the bus that the slave is attached to. For
* driver model this is the sequence number of the SPI
* bus (bus->seq) so does not need to be stored
* @cs: ID of the chip select connected to the slave.
- * @op_mode_rx: SPI RX operation mode.
- * @op_mode_tx: SPI TX operation mode.
+ * @mode: SPI mode to use for this slave (see SPI mode flags)
+ * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
* @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes.
@@ -120,18 +107,24 @@
struct udevice *dev; /* struct spi_slave is dev->parentdata */
uint max_hz;
uint speed;
- uint mode;
#else
unsigned int bus;
unsigned int cs;
#endif
- u8 op_mode_rx;
- u8 op_mode_tx;
+ uint mode;
+ u8 mode_rx;
unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
u8 option;
+
u8 flags;
+#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
+#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
+#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+#define SPI_XFER_MMAP BIT(2) /* Memory Mapped start */
+#define SPI_XFER_MMAP_END BIT(3) /* Memory Mapped End */
+#define SPI_XFER_U_PAGE BIT(4)
};
/**
diff --git a/include/spi_flash.h b/include/spi_flash.h
index f25b3e7..d0ce9e7 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -4,12 +4,7 @@
* Copyright (C) 2008 Atmel Corporation
* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _SPI_FLASH_H_
@@ -170,8 +165,6 @@
/* Compatibility function - this is the old U-Boot API */
void spi_flash_free(struct spi_flash *flash);
-int spi_flash_remove(struct udevice *flash);
-
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
{
diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h
index da09dab..b0d9ce9 100644
--- a/include/u-boot/sha1.h
+++ b/include/u-boot/sha1.h
@@ -5,19 +5,7 @@
*
* Copyright (C) 2003-2006 Christophe Devine
*
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License, version 2.1 as published by the Free Software Foundation.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier: LGPL-2.1
*/
/*
* The SHA-1 standard was published by NIST in 1993.
diff --git a/include/usb.h b/include/usb.h
index 55b9268..0b410b6 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -227,7 +227,7 @@
#ifdef CONFIG_USB_STORAGE
-#define USB_MAX_STOR_DEV 5
+#define USB_MAX_STOR_DEV 7
block_dev_desc_t *usb_stor_get_dev(int index);
int usb_stor_scan(int mode);
int usb_stor_info(void);
@@ -266,8 +266,9 @@
void *buffer, int transfer_len, int interval);
int usb_disable_asynch(int disable);
int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
-int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer,
- int cfgno);
+int usb_get_configuration_no(struct usb_device *dev, int cfgno,
+ unsigned char *buffer, int length);
+int usb_get_configuration_len(struct usb_device *dev, int cfgno);
int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type,
unsigned char id, void *buf, int size);
int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
@@ -874,6 +875,18 @@
int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat);
+/*
+ * usb_find_usb2_hub_address_port() - Get hub address and port for TT setting
+ *
+ * Searches for the first HS hub above the given device. If a
+ * HS hub is found, the hub address and the port the device is
+ * connected to is return, as required for SPLIT transactions
+ *
+ * @param: udev full speed or low speed device
+ */
+void usb_find_usb2_hub_address_port(struct usb_device *udev,
+ uint8_t *hub_address, uint8_t *hub_port);
+
/**
* usb_alloc_new_device() - Allocate a new device
*
diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
new file mode 100644
index 0000000..302e9a3
--- /dev/null
+++ b/include/usb/dwc2_udc.h
@@ -0,0 +1,25 @@
+/*
+ * drivers/usb/gadget/dwc2_udc.h
+ * Designware DWC2 on-chip full/high speed USB device controllers
+ * Copyright (C) 2005 for Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DWC2_USB_GADGET
+#define __DWC2_USB_GADGET
+
+#define PHY0_SLEEP (1 << 5)
+
+struct dwc2_plat_otg_data {
+ int (*phy_control)(int on);
+ unsigned int regs_phy;
+ unsigned int regs_otg;
+ unsigned int usb_phy_ctrl;
+ unsigned int usb_flags;
+ unsigned int usb_gusbcfg;
+};
+
+int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata);
+
+#endif /* __DWC2_USB_GADGET */
diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h
index 99166c4..4fa765b 100644
--- a/include/usb/ulpi.h
+++ b/include/usb/ulpi.h
@@ -13,9 +13,7 @@
* Original Copyrights follow:
* Copyright (C) 2010 Nokia Corporation
*
- * This software is distributed under the terms of the GNU General
- * Public License ("GPL") as published by the Free Software Foundation,
- * version 2 of that License.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __USB_ULPI_H__
diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
index 69b80cd..5804b70 100644
--- a/include/usb_mass_storage.h
+++ b/include/usb_mass_storage.h
@@ -23,12 +23,10 @@
unsigned int start_sector;
unsigned int num_sectors;
const char *name;
- block_dev_desc_t *block_dev;
+ block_dev_desc_t block_dev;
};
-extern struct ums *ums;
-
-int fsg_init(struct ums *);
+int fsg_init(struct ums *ums_devs, int count);
void fsg_cleanup(void);
int fsg_main_thread(void *);
int fsg_add(struct usb_configuration *c);
diff --git a/include/vsprintf.h b/include/vsprintf.h
index b5bc9c1..376f5dd 100644
--- a/include/vsprintf.h
+++ b/include/vsprintf.h
@@ -124,7 +124,6 @@
int vsprintf(char *buf, const char *fmt, va_list args);
char *simple_itoa(ulong i);
-#ifdef CONFIG_SYS_VSNPRINTF
/**
* Format a string and place it in a buffer
*
@@ -199,17 +198,6 @@
* See the vsprintf() documentation for format string extensions over C99.
*/
int vscnprintf(char *buf, size_t size, const char *fmt, va_list args);
-#else
-/*
- * Use macros to silently drop the size parameter. Note that the 'cn'
- * versions are the same as the 'n' versions since the functions assume
- * there is always enough buffer space when !CONFIG_SYS_VSNPRINTF
- */
-#define snprintf(buf, size, fmt, args...) sprintf(buf, fmt, ##args)
-#define scnprintf(buf, size, fmt, args...) sprintf(buf, fmt, ##args)
-#define vsnprintf(buf, size, fmt, args...) vsprintf(buf, fmt, ##args)
-#define vscnprintf(buf, size, fmt, args...) vsprintf(buf, fmt, ##args)
-#endif /* CONFIG_SYS_VSNPRINTF */
/**
* print_grouped_ull() - print a value with digits grouped by ','
diff --git a/lib/Kconfig b/lib/Kconfig
index 9d580e4..46d7034 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -27,15 +27,6 @@
get_timer() must operate in milliseconds and this option must be
set to 1000.
-config SYS_VSNPRINTF
- bool "Enable safe version of sprintf()"
- help
- Since sprintf() can overflow its buffer, it is common to use
- snprintf() instead, which knows the buffer size and can avoid
- overflow. However, this does increase code size slightly (for
- Thumb-2, about 420 bytes). Enable this option for safety when
- using sprintf() with data you do not control.
-
config USE_TINY_PRINTF
bool "Enable tiny printf() version"
help
diff --git a/lib/Makefile b/lib/Makefile
index 1f1ff6f..dd36f25 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -85,13 +85,13 @@
ifdef CONFIG_SPL_BUILD
# SPL U-Boot may use full-printf, tiny-printf or none at all
ifdef CONFIG_USE_TINY_PRINTF
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += tiny-printf.o
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += tiny-printf.o panic.o strto.o
else
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o panic.o strto.o
endif
else
# Main U-Boot always uses the full printf support
-obj-y += vsprintf.o
+obj-y += vsprintf.o panic.o strto.o
endif
subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
diff --git a/lib/addr_map.c b/lib/addr_map.c
index 31384d1..403640b 100644
--- a/lib/addr_map.c
+++ b/lib/addr_map.c
@@ -1,19 +1,7 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/lib/bch.c b/lib/bch.c
index 7f4ca92..147715a 100644
--- a/lib/bch.c
+++ b/lib/bch.c
@@ -1,18 +1,7 @@
/*
* Generic binary BCH encoding/decoding library
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 51
- * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: GPL-2.0
*
* Copyright © 2011 Parrot S.A.
*
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 82d0090..b50d105 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -5,6 +5,7 @@
#ifndef USE_HOSTCC
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <serial.h>
#include <libfdt.h>
@@ -71,8 +72,10 @@
COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
+ COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
+ COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
@@ -189,7 +192,7 @@
return fdtdec_get_addr_size(blob, node, prop_name, NULL);
}
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
const char *prop_name, struct fdt_pci_addr *addr)
{
@@ -282,58 +285,10 @@
return -ENOENT;
}
-int fdtdec_get_pci_bdf(const void *blob, int node,
- struct fdt_pci_addr *addr, pci_dev_t *bdf)
+int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr,
+ u32 *bar)
{
- u16 dt_vendor, dt_device, vendor, device;
- int ret;
-
- /* get vendor id & device id from the compatible string */
- ret = fdtdec_get_pci_vendev(blob, node, &dt_vendor, &dt_device);
- if (ret)
- return ret;
-
- /* extract the bdf from fdt_pci_addr */
- *bdf = addr->phys_hi & 0xffff00;
-
- /* read vendor id & device id based on bdf */
- pci_read_config_word(*bdf, PCI_VENDOR_ID, &vendor);
- pci_read_config_word(*bdf, PCI_DEVICE_ID, &device);
-
- /*
- * Note there are two places in the device tree to fully describe
- * a pci device: one is via compatible string with a format of
- * "pciVVVV,DDDD" and the other one is the bdf numbers encoded in
- * the device node's reg address property. We read the vendor id
- * and device id based on bdf and compare the values with the
- * "VVVV,DDDD". If they are the same, then we are good to use bdf
- * to read device's bar. But if they are different, we have to rely
- * on the vendor id and device id extracted from the compatible
- * string and locate the real bdf by pci_find_device(). This is
- * because normally we may only know device's device number and
- * function number when writing device tree. The bus number is
- * dynamically assigned during the pci enumeration process.
- */
- if ((dt_vendor != vendor) || (dt_device != device)) {
- *bdf = pci_find_device(dt_vendor, dt_device, 0);
- if (*bdf == -1)
- return -ENODEV;
- }
-
- return 0;
-}
-
-int fdtdec_get_pci_bar32(const void *blob, int node,
- struct fdt_pci_addr *addr, u32 *bar)
-{
- pci_dev_t bdf;
int barnum;
- int ret;
-
- /* get pci devices's bdf */
- ret = fdtdec_get_pci_bdf(blob, node, addr, &bdf);
- if (ret)
- return ret;
/* extract the bar number from fdt_pci_addr */
barnum = addr->phys_hi & 0xff;
@@ -341,7 +296,7 @@
return -EINVAL;
barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
- *bar = pci_read_bar32(pci_bus_to_hose(PCI_BUS(bdf)), bdf, barnum);
+ *bar = dm_pci_read_bar32(dev, barnum);
return 0;
}
diff --git a/lib/gunzip.c b/lib/gunzip.c
index bdd85c4..80b157f 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -70,6 +70,7 @@
return zunzip(dst, dstlen, src, lenp, 1, i);
}
+#ifdef CONFIG_CMD_UNZIP
__weak
void gzwrite_progress_init(u64 expectedsize)
{
@@ -231,8 +232,7 @@
gzwrite_progress(iteration++,
totalfilled,
szexpected);
- blocks_written = dev->block_write(dev->dev,
- outblock,
+ blocks_written = dev->block_write(dev, outblock,
writeblocks,
writebuf);
outblock += blocks_written;
@@ -259,6 +259,7 @@
return r;
}
+#endif
/*
* Uncompress blocks compressed with zlib without headers
diff --git a/lib/panic.c b/lib/panic.c
new file mode 100644
index 0000000..e2b8b74
--- /dev/null
+++ b/lib/panic.c
@@ -0,0 +1,45 @@
+/*
+ * linux/lib/vsprintf.c
+ *
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ */
+
+/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */
+/*
+ * Wirzenius wrote this portably, Torvalds fucked it up :-)
+ */
+
+#include <common.h>
+#if !defined(CONFIG_PANIC_HANG)
+#include <command.h>
+#endif
+
+static void panic_finish(void) __attribute__ ((noreturn));
+
+static void panic_finish(void)
+{
+ putc('\n');
+#if defined(CONFIG_PANIC_HANG)
+ hang();
+#else
+ udelay(100000); /* allow messages to go out */
+ do_reset(NULL, 0, 0, NULL);
+#endif
+ while (1)
+ ;
+}
+
+void panic_str(const char *str)
+{
+ puts(str);
+ panic_finish();
+}
+
+void panic(const char *fmt, ...)
+{
+ va_list args;
+ va_start(args, fmt);
+ vprintf(fmt, args);
+ va_end(args);
+ panic_finish();
+}
diff --git a/lib/sha1.c b/lib/sha1.c
index 05b17a2..72c5dea 100644
--- a/lib/sha1.c
+++ b/lib/sha1.c
@@ -5,19 +5,7 @@
*
* Copyright (C) 2003-2006 Christophe Devine
*
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License, version 2.1 as published by the Free Software Foundation.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier: LGPL-2.1
*/
/*
* The SHA-1 standard was published by NIST in 1993.
diff --git a/lib/strto.c b/lib/strto.c
new file mode 100644
index 0000000..a6c0157
--- /dev/null
+++ b/lib/strto.c
@@ -0,0 +1,174 @@
+/*
+ * linux/lib/vsprintf.c
+ *
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ */
+
+/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */
+/*
+ * Wirzenius wrote this portably, Torvalds fucked it up :-)
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/ctype.h>
+
+unsigned long simple_strtoul(const char *cp, char **endp,
+ unsigned int base)
+{
+ unsigned long result = 0;
+ unsigned long value;
+
+ if (*cp == '0') {
+ cp++;
+ if ((*cp == 'x') && isxdigit(cp[1])) {
+ base = 16;
+ cp++;
+ }
+
+ if (!base)
+ base = 8;
+ }
+
+ if (!base)
+ base = 10;
+
+ while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
+ ? toupper(*cp) : *cp)-'A'+10) < base) {
+ result = result*base + value;
+ cp++;
+ }
+
+ if (endp)
+ *endp = (char *)cp;
+
+ return result;
+}
+
+int strict_strtoul(const char *cp, unsigned int base, unsigned long *res)
+{
+ char *tail;
+ unsigned long val;
+ size_t len;
+
+ *res = 0;
+ len = strlen(cp);
+ if (len == 0)
+ return -EINVAL;
+
+ val = simple_strtoul(cp, &tail, base);
+ if (tail == cp)
+ return -EINVAL;
+
+ if ((*tail == '\0') ||
+ ((len == (size_t)(tail - cp) + 1) && (*tail == '\n'))) {
+ *res = val;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+long simple_strtol(const char *cp, char **endp, unsigned int base)
+{
+ if (*cp == '-')
+ return -simple_strtoul(cp + 1, endp, base);
+
+ return simple_strtoul(cp, endp, base);
+}
+
+unsigned long ustrtoul(const char *cp, char **endp, unsigned int base)
+{
+ unsigned long result = simple_strtoul(cp, endp, base);
+ switch (**endp) {
+ case 'G':
+ result *= 1024;
+ /* fall through */
+ case 'M':
+ result *= 1024;
+ /* fall through */
+ case 'K':
+ case 'k':
+ result *= 1024;
+ if ((*endp)[1] == 'i') {
+ if ((*endp)[2] == 'B')
+ (*endp) += 3;
+ else
+ (*endp) += 2;
+ }
+ }
+ return result;
+}
+
+unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base)
+{
+ unsigned long long result = simple_strtoull(cp, endp, base);
+ switch (**endp) {
+ case 'G':
+ result *= 1024;
+ /* fall through */
+ case 'M':
+ result *= 1024;
+ /* fall through */
+ case 'K':
+ case 'k':
+ result *= 1024;
+ if ((*endp)[1] == 'i') {
+ if ((*endp)[2] == 'B')
+ (*endp) += 3;
+ else
+ (*endp) += 2;
+ }
+ }
+ return result;
+}
+
+unsigned long long simple_strtoull(const char *cp, char **endp,
+ unsigned int base)
+{
+ unsigned long long result = 0, value;
+
+ if (*cp == '0') {
+ cp++;
+ if ((*cp == 'x') && isxdigit(cp[1])) {
+ base = 16;
+ cp++;
+ }
+
+ if (!base)
+ base = 8;
+ }
+
+ if (!base)
+ base = 10;
+
+ while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp - '0'
+ : (islower(*cp) ? toupper(*cp) : *cp) - 'A' + 10) < base) {
+ result = result * base + value;
+ cp++;
+ }
+
+ if (endp)
+ *endp = (char *) cp;
+
+ return result;
+}
+
+long trailing_strtoln(const char *str, const char *end)
+{
+ const char *p;
+
+ if (!end)
+ end = str + strlen(str);
+ for (p = end - 1; p > str; p--) {
+ if (!isdigit(*p))
+ return simple_strtoul(p + 1, NULL, 10);
+ }
+
+ return -1;
+}
+
+long trailing_strtol(const char *str)
+{
+ return trailing_strtoln(str, NULL);
+}
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 6766a8f..403b134 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -40,17 +40,14 @@
out_dgt(dgt);
}
-int printf(const char *fmt, ...)
+int vprintf(const char *fmt, va_list va)
{
- va_list va;
char ch;
char *p;
unsigned int num;
char buf[12];
unsigned int div;
- va_start(va, fmt);
-
while ((ch = *(fmt++))) {
if (ch != '%') {
putc(ch);
@@ -117,6 +114,17 @@
}
abort:
- va_end(va);
return 0;
}
+
+int printf(const char *fmt, ...)
+{
+ va_list va;
+ int ret;
+
+ va_start(va, fmt);
+ ret = vprintf(fmt, va);
+ va_end(va);
+
+ return ret;
+}
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index dd8380b..874a295 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -15,176 +15,12 @@
#include <linux/types.h>
#include <linux/string.h>
#include <linux/ctype.h>
-#include <errno.h>
#include <common.h>
-#if !defined(CONFIG_PANIC_HANG)
-#include <command.h>
-#endif
#include <div64.h>
#define noinline __attribute__((noinline))
-unsigned long simple_strtoul(const char *cp, char **endp,
- unsigned int base)
-{
- unsigned long result = 0;
- unsigned long value;
-
- if (*cp == '0') {
- cp++;
- if ((*cp == 'x') && isxdigit(cp[1])) {
- base = 16;
- cp++;
- }
-
- if (!base)
- base = 8;
- }
-
- if (!base)
- base = 10;
-
- while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
- ? toupper(*cp) : *cp)-'A'+10) < base) {
- result = result*base + value;
- cp++;
- }
-
- if (endp)
- *endp = (char *)cp;
-
- return result;
-}
-
-int strict_strtoul(const char *cp, unsigned int base, unsigned long *res)
-{
- char *tail;
- unsigned long val;
- size_t len;
-
- *res = 0;
- len = strlen(cp);
- if (len == 0)
- return -EINVAL;
-
- val = simple_strtoul(cp, &tail, base);
- if (tail == cp)
- return -EINVAL;
-
- if ((*tail == '\0') ||
- ((len == (size_t)(tail - cp) + 1) && (*tail == '\n'))) {
- *res = val;
- return 0;
- }
-
- return -EINVAL;
-}
-
-long simple_strtol(const char *cp, char **endp, unsigned int base)
-{
- if (*cp == '-')
- return -simple_strtoul(cp + 1, endp, base);
-
- return simple_strtoul(cp, endp, base);
-}
-
-unsigned long ustrtoul(const char *cp, char **endp, unsigned int base)
-{
- unsigned long result = simple_strtoul(cp, endp, base);
- switch (**endp) {
- case 'G':
- result *= 1024;
- /* fall through */
- case 'M':
- result *= 1024;
- /* fall through */
- case 'K':
- case 'k':
- result *= 1024;
- if ((*endp)[1] == 'i') {
- if ((*endp)[2] == 'B')
- (*endp) += 3;
- else
- (*endp) += 2;
- }
- }
- return result;
-}
-
-unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base)
-{
- unsigned long long result = simple_strtoull(cp, endp, base);
- switch (**endp) {
- case 'G':
- result *= 1024;
- /* fall through */
- case 'M':
- result *= 1024;
- /* fall through */
- case 'K':
- case 'k':
- result *= 1024;
- if ((*endp)[1] == 'i') {
- if ((*endp)[2] == 'B')
- (*endp) += 3;
- else
- (*endp) += 2;
- }
- }
- return result;
-}
-
-unsigned long long simple_strtoull(const char *cp, char **endp,
- unsigned int base)
-{
- unsigned long long result = 0, value;
-
- if (*cp == '0') {
- cp++;
- if ((*cp == 'x') && isxdigit(cp[1])) {
- base = 16;
- cp++;
- }
-
- if (!base)
- base = 8;
- }
-
- if (!base)
- base = 10;
-
- while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp - '0'
- : (islower(*cp) ? toupper(*cp) : *cp) - 'A' + 10) < base) {
- result = result * base + value;
- cp++;
- }
-
- if (endp)
- *endp = (char *) cp;
-
- return result;
-}
-
-long trailing_strtoln(const char *str, const char *end)
-{
- const char *p;
-
- if (!end)
- end = str + strlen(str);
- for (p = end - 1; p > str; p--) {
- if (!isdigit(*p))
- return simple_strtoul(p + 1, NULL, 10);
- }
-
- return -1;
-}
-
-long trailing_strtol(const char *str)
-{
- return trailing_strtoln(str, NULL);
-}
-
/* we use this so that we can do without the ctype library */
#define is_digit(c) ((c) >= '0' && (c) <= '9')
@@ -305,7 +141,6 @@
#define SMALL 32 /* Must be 32 == 0x20 */
#define SPECIAL 64 /* 0x */
-#ifdef CONFIG_SYS_VSNPRINTF
/*
* Macro to add a new character to our output string, but only if it will
* fit. The macro moves to the next character position in the output string.
@@ -315,9 +150,6 @@
*(str) = (ch); \
++str; \
} while (0)
-#else
-#define ADDCH(str, ch) (*(str)++ = (ch))
-#endif
static char *number(char *buf, char *end, u64 num,
int base, int size, int precision, int type)
@@ -605,13 +437,11 @@
/* 't' added for ptrdiff_t */
char *end = buf + size;
-#ifdef CONFIG_SYS_VSNPRINTF
/* Make sure end is always >= buf - do we want this in U-Boot? */
if (end < buf) {
end = ((void *)-1);
size = end - buf;
}
-#endif
str = buf;
for (; *fmt ; ++fmt) {
@@ -773,21 +603,16 @@
flags);
}
-#ifdef CONFIG_SYS_VSNPRINTF
if (size > 0) {
ADDCH(str, '\0');
if (str > end)
end[-1] = '\0';
--str;
}
-#else
- *str = '\0';
-#endif
/* the trailing null byte doesn't count towards the total */
return str - buf;
}
-#ifdef CONFIG_SYS_VSNPRINTF
int vsnprintf(char *buf, size_t size, const char *fmt,
va_list args)
{
@@ -830,7 +655,6 @@
return i;
}
-#endif /* CONFIG_SYS_VSNPRINT */
/**
* Format a string and place it in a buffer (va_list version)
@@ -897,35 +721,6 @@
return i;
}
-static void panic_finish(void) __attribute__ ((noreturn));
-
-static void panic_finish(void)
-{
- putc('\n');
-#if defined(CONFIG_PANIC_HANG)
- hang();
-#else
- udelay(100000); /* allow messages to go out */
- do_reset(NULL, 0, 0, NULL);
-#endif
- while (1)
- ;
-}
-
-void panic_str(const char *str)
-{
- puts(str);
- panic_finish();
-}
-
-void panic(const char *fmt, ...)
-{
- va_list args;
- va_start(args, fmt);
- vprintf(fmt, args);
- va_end(args);
- panic_finish();
-}
void __assert_fail(const char *assertion, const char *file, unsigned line,
const char *function)
diff --git a/net/eth.c b/net/eth.c
index c542f4a..45fe6e3 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -337,14 +337,30 @@
int eth_init(void)
{
- struct udevice *current;
+ char *ethact = getenv("ethact");
+ char *ethrotate = getenv("ethrotate");
+ struct udevice *current = NULL;
struct udevice *old_current;
int ret = -ENODEV;
- current = eth_get_dev();
+ /*
+ * When 'ethrotate' variable is set to 'no' and 'ethact' variable
+ * is already set to an ethernet device, we should stick to 'ethact'.
+ */
+ if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0)) {
+ if (ethact) {
+ current = eth_get_dev_by_name(ethact);
+ if (!current)
+ return -EINVAL;
+ }
+ }
+
if (!current) {
- printf("No ethernet found.\n");
- return -ENODEV;
+ current = eth_get_dev();
+ if (!current) {
+ printf("No ethernet found.\n");
+ return -ENODEV;
+ }
}
old_current = current;
@@ -541,6 +557,34 @@
struct eth_pdata *pdata = dev->platdata;
unsigned char env_enetaddr[6];
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+ struct eth_ops *ops = eth_get_ops(dev);
+ static int reloc_done;
+
+ if (!reloc_done) {
+ if (ops->start)
+ ops->start += gd->reloc_off;
+ if (ops->send)
+ ops->send += gd->reloc_off;
+ if (ops->recv)
+ ops->recv += gd->reloc_off;
+ if (ops->free_pkt)
+ ops->free_pkt += gd->reloc_off;
+ if (ops->stop)
+ ops->stop += gd->reloc_off;
+#ifdef CONFIG_MCAST_TFTP
+ if (ops->mcast)
+ ops->mcast += gd->reloc_off;
+#endif
+ if (ops->write_hwaddr)
+ ops->write_hwaddr += gd->reloc_off;
+ if (ops->read_rom_hwaddr)
+ ops->read_rom_hwaddr += gd->reloc_off;
+
+ reloc_done++;
+ }
+#endif
+
priv->state = ETH_STATE_INIT;
/* Check if the device has a MAC address in ROM */
@@ -733,8 +777,6 @@
} else if (is_valid_ethaddr(dev->enetaddr)) {
eth_setenv_enetaddr_by_index(base_name, eth_number,
dev->enetaddr);
- printf("\nWarning: %s using MAC address from net device\n",
- dev->name);
} else if (is_zero_ethaddr(dev->enetaddr)) {
#ifdef CONFIG_NET_RANDOM_ETHADDR
net_random_ethaddr(dev->enetaddr);
@@ -1011,6 +1053,17 @@
static void eth_current_changed(void)
{
char *act = getenv("ethact");
+ char *ethrotate;
+
+ /*
+ * The call to eth_get_dev() below has a side effect of rotating
+ * ethernet device if uc_priv->current == NULL. This is not what
+ * we want when 'ethrotate' variable is 'no'.
+ */
+ ethrotate = getenv("ethrotate");
+ if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0))
+ return;
+
/* update current ethernet name */
if (eth_get_dev()) {
if (act == NULL || strcmp(act, eth_get_name()) != 0)
diff --git a/net/net.c b/net/net.c
index 4d5746a..fba111e 100644
--- a/net/net.c
+++ b/net/net.c
@@ -542,6 +542,9 @@
#ifdef CONFIG_SHOW_ACTIVITY
show_activity(1);
#endif
+ if (arp_timeout_check() > 0)
+ time_start = get_timer(0);
+
/*
* Check the ethernet for a new packet. The ethernet
* receive routine will process it.
@@ -570,10 +573,6 @@
goto done;
}
- if (arp_timeout_check() > 0) {
- time_start = get_timer(0);
- }
-
/*
* Check for a timeout, and run the timeout handler
* if we have one.
diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf
index d668982..01a739d 100644
--- a/scripts/Makefile.autoconf
+++ b/scripts/Makefile.autoconf
@@ -6,6 +6,9 @@
# When our migration to Kconfig is done
# (= When we move all CONFIGs from header files to Kconfig)
# this makefile can be deleted.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
__all: include/autoconf.mk include/autoconf.mk.dep
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index de818ae..06e5c20 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -1,6 +1,9 @@
# ==========================================================================
# Building
# ==========================================================================
+#
+# SPDX-License-Identifier: GPL-2.0
+#
# Modified for U-Boot
prefix := tpl
diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean
index 4853631..b69533d 100644
--- a/scripts/Makefile.clean
+++ b/scripts/Makefile.clean
@@ -1,6 +1,9 @@
# ==========================================================================
# Cleaning up
# ==========================================================================
+#
+# SPDX-License-Identifier: GPL-2.0
+#
src := $(obj)
diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn
index 0ec0d24..6547e57 100644
--- a/scripts/Makefile.extrawarn
+++ b/scripts/Makefile.extrawarn
@@ -9,6 +9,9 @@
# $(call cc-option, -W...) handles gcc -W.. options which
# are not supported by all versions of the compiler
# ==========================================================================
+#
+# SPDX-License-Identifier: GPL-2.0
+#
ifeq ("$(origin W)", "command line")
export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W)
diff --git a/scripts/Makefile.host b/scripts/Makefile.host
index 133edfa..bff8b5b 100644
--- a/scripts/Makefile.host
+++ b/scripts/Makefile.host
@@ -19,6 +19,9 @@
# qconf-objs := menu.o
# Will compile qconf as a C++ program, and menu as a C program.
# They are linked as C++ code to the executable qconf
+#
+# SPDX-License-Identifier: GPL-2.0
+#
__hostprogs := $(sort $(hostprogs-y) $(hostprogs-m))
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index ed30bf5..1644f8c 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -1,3 +1,6 @@
+#
+# SPDX-License-Identifier: GPL-2.0
+#
# Backward compatibility
asflags-y += $(EXTRA_AFLAGS)
ccflags-y += $(EXTRA_CFLAGS)
diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl
index 4003546..15d0836 100644
--- a/scripts/Makefile.uncmd_spl
+++ b/scripts/Makefile.uncmd_spl
@@ -1,5 +1,7 @@
# Makefile version of include/config_uncmd_spl.h
#
+# SPDX-License-Identifier: GPL-2.0+
+#
# TODO: Invent a better way
ifdef CONFIG_SPL_BUILD
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 74db2e2..24831b3 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2825,8 +2825,8 @@
# function brace can't be on same line, except for #defines of do while,
# or if closed on same line
- if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and
- !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) {
+ if (($line=~/$Type\s*$Ident\(.*\).*\s\{/) and
+ !($line=~/\#\s*define.*do\s\{/) and !($line=~/}/)) {
ERROR("OPEN_BRACE",
"open brace '{' following function declarations go on the next line\n" . $herecurr);
}
@@ -3259,8 +3259,8 @@
## }
#need space before brace following if, while, etc
- if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) ||
- $line =~ /do{/) {
+ if (($line =~ /\(.*\)\{/ && $line !~ /\($Type\){/) ||
+ $line =~ /do\{/) {
if (ERROR("SPACING",
"space required before the open brace '{'\n" . $herecurr) &&
$fix) {
@@ -3633,7 +3633,7 @@
$dstat !~ /^for\s*$Constant$/ && # for (...)
$dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar()
$dstat !~ /^do\s*{/ && # do {...
- $dstat !~ /^\({/ && # ({...
+ $dstat !~ /^\(\{/ && # ({...
$ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/)
{
$ctx =~ s/\n*$//;
diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl
index 4707dfd..83a4e5b 100755
--- a/scripts/get_maintainer.pl
+++ b/scripts/get_maintainer.pl
@@ -298,7 +298,7 @@
while (<$maint>) {
my $line = $_;
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
@@ -533,7 +533,7 @@
for (my $i = $start; $i < $end; $i++) {
my $line = $typevalue[$i];
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
if ($type eq 'S') {
@@ -551,7 +551,7 @@
for (my $i = $start; $i < $end; $i++) {
my $line = $typevalue[$i];
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
if ($type eq 'M') {
@@ -600,7 +600,7 @@
for ($i = $start; $i < $end; $i++) {
my $line = $typevalue[$i];
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
if ($type eq 'X') {
@@ -615,7 +615,7 @@
if (!$exclude) {
for ($i = $start; $i < $end; $i++) {
my $line = $typevalue[$i];
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
if ($type eq 'F') {
@@ -917,7 +917,7 @@
while ($index < @typevalue) {
my $tv = $typevalue[$index];
- if (($tv =~ m/^(\C):\s*(.*)/)) {
+ if (($tv =~ m/^([A-Z]):\s*(.*)/)) {
last;
}
$index++;
@@ -931,7 +931,7 @@
while ($index > 0) {
my $tv = $typevalue[$index];
- if (!($tv =~ m/^(\C):\s*(.*)/)) {
+ if (!($tv =~ m/^([A-Z]):\s*(.*)/)) {
last;
}
$index--;
@@ -945,7 +945,7 @@
while ($index < @typevalue) {
my $tv = $typevalue[$index];
- if (!($tv =~ m/^(\C):\s*(.*)/)) {
+ if (!($tv =~ m/^([A-Z]):\s*(.*)/)) {
last;
}
$index++;
@@ -971,7 +971,7 @@
for ($i = $start + 1; $i < $end; $i++) {
my $tv = $typevalue[$i];
- if ($tv =~ m/^(\C):\s*(.*)/) {
+ if ($tv =~ m/^([A-Z]):\s*(.*)/) {
my $ptype = $1;
my $pvalue = $2;
if ($ptype eq "S") {
@@ -1030,7 +1030,7 @@
for ($i = $start + 1; $i < $end; $i++) {
my $tv = $typevalue[$i];
- if ($tv =~ m/^(\C):\s*(.*)/) {
+ if ($tv =~ m/^([A-Z]):\s*(.*)/) {
my $ptype = $1;
my $pvalue = $2;
if ($ptype eq "L") {
@@ -1072,7 +1072,7 @@
if ($name eq "") {
if ($i > 0) {
my $tv = $typevalue[$i - 1];
- if ($tv =~ m/^(\C):\s*(.*)/) {
+ if ($tv =~ m/^([A-Z]):\s*(.*)/) {
if ($1 eq "P") {
$name = $2;
$pvalue = format_email($name, $address, $email_usename);
diff --git a/scripts/kconfig/lxdialog/checklist.c b/scripts/kconfig/lxdialog/checklist.c
index 8d016fa..09938ae 100644
--- a/scripts/kconfig/lxdialog/checklist.c
+++ b/scripts/kconfig/lxdialog/checklist.c
@@ -6,19 +6,7 @@
* Alessandro Rubini - rubini@ipvvis.unipv.it: merged the two
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "dialog.h"
diff --git a/scripts/kconfig/lxdialog/dialog.h b/scripts/kconfig/lxdialog/dialog.h
index fcffd5b..cff73a6 100644
--- a/scripts/kconfig/lxdialog/dialog.h
+++ b/scripts/kconfig/lxdialog/dialog.h
@@ -3,19 +3,7 @@
*
* AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <sys/types.h>
diff --git a/scripts/kconfig/lxdialog/inputbox.c b/scripts/kconfig/lxdialog/inputbox.c
index d58de1d..f8b7ef7 100644
--- a/scripts/kconfig/lxdialog/inputbox.c
+++ b/scripts/kconfig/lxdialog/inputbox.c
@@ -4,19 +4,7 @@
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "dialog.h"
diff --git a/scripts/kconfig/lxdialog/menubox.c b/scripts/kconfig/lxdialog/menubox.c
index 11ae9ad..99f923e 100644
--- a/scripts/kconfig/lxdialog/menubox.c
+++ b/scripts/kconfig/lxdialog/menubox.c
@@ -4,19 +4,7 @@
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
diff --git a/scripts/kconfig/lxdialog/textbox.c b/scripts/kconfig/lxdialog/textbox.c
index 1773319..d3ad43f 100644
--- a/scripts/kconfig/lxdialog/textbox.c
+++ b/scripts/kconfig/lxdialog/textbox.c
@@ -4,19 +4,7 @@
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "dialog.h"
diff --git a/scripts/kconfig/lxdialog/util.c b/scripts/kconfig/lxdialog/util.c
index f7abdeb..a6dec28 100644
--- a/scripts/kconfig/lxdialog/util.c
+++ b/scripts/kconfig/lxdialog/util.c
@@ -4,19 +4,7 @@
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <stdarg.h>
diff --git a/scripts/kconfig/lxdialog/yesno.c b/scripts/kconfig/lxdialog/yesno.c
index 676fb2f..a732e24 100644
--- a/scripts/kconfig/lxdialog/yesno.c
+++ b/scripts/kconfig/lxdialog/yesno.c
@@ -4,19 +4,7 @@
* ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)
* MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "dialog.h"
diff --git a/scripts/kconfig/mconf.c b/scripts/kconfig/mconf.c
index 315ce2c..953d5c7 100644
--- a/scripts/kconfig/mconf.c
+++ b/scripts/kconfig/mconf.c
@@ -379,7 +379,7 @@
data->targets[k] = pos->target;
k++;
} else {
- sprintf(header, " ");
+ strcpy(header, " ");
}
memcpy(buf + pos->offset, header, sizeof(header) - 1);
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 681c6ae..3ff1b75 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -27,8 +27,8 @@
obj-$(CONFIG_REMOTEPROC) += remoteproc.o
obj-$(CONFIG_RESET) += reset.o
obj-$(CONFIG_DM_RTC) += rtc.o
-obj-$(CONFIG_DM_SPI_FLASH) += sf.o
-obj-$(CONFIG_DM_SPI) += spi.o
+#obj-$(CONFIG_DM_SPI_FLASH) += sf.o
+#obj-$(CONFIG_DM_SPI) += spi.o
obj-y += syscon.o
obj-$(CONFIG_DM_USB) += usb.o
obj-$(CONFIG_DM_PMIC) += pmic.o
diff --git a/test/dm/pci.c b/test/dm/pci.c
index 3ab4ba8..a5b1290 100644
--- a/test/dm/pci.c
+++ b/test/dm/pci.c
@@ -35,20 +35,17 @@
/* Test that we can use the swapcase device correctly */
static int dm_test_pci_swapcase(struct unit_test_state *uts)
{
- pci_dev_t pci_dev = PCI_BDF(0, 0x1f, 0);
- struct pci_controller *hose;
- struct udevice *bus, *swap;
+ struct udevice *emul, *swap;
ulong io_addr, mem_addr;
char *ptr;
/* Check that asking for the device automatically fires up PCI */
- ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &swap));
-
- ut_assertok(uclass_get_device(UCLASS_PCI, 0, &bus));
- hose = dev_get_uclass_priv(bus);
+ ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &emul));
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
+ ut_assert(device_active(swap));
/* First test I/O */
- io_addr = pci_read_bar32(hose, pci_dev, 0);
+ io_addr = dm_pci_read_bar32(swap, 0);
outb(2, io_addr);
ut_asserteq(2, inb(io_addr));
@@ -56,7 +53,7 @@
* Now test memory mapping - note we must unmap and remap to cause
* the swapcase emulation to see our data and response.
*/
- mem_addr = pci_read_bar32(hose, pci_dev, 1);
+ mem_addr = dm_pci_read_bar32(swap, 1);
ptr = map_sysmem(mem_addr, 20);
strcpy(ptr, "This is a TesT");
unmap_sysmem(ptr);
diff --git a/test/dm/usb.c b/test/dm/usb.c
index 7d6b644..3a2e52b 100644
--- a/test/dm/usb.c
+++ b/test/dm/usb.c
@@ -50,7 +50,7 @@
/* Read a few blocks and look for the string we expect */
ut_asserteq(512, dev_desc->blksz);
memset(cmp, '\0', sizeof(cmp));
- ut_asserteq(2, dev_desc->block_read(dev_desc->dev, 0, 2, cmp));
+ ut_asserteq(2, dev_desc->block_read(dev_desc, 0, 2, cmp));
ut_assertok(strcmp(cmp, "this is a test"));
return 0;
@@ -108,9 +108,9 @@
ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 1, &dev));
ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
- ut_asserteq(5, count_usb_devices());
+ ut_asserteq(6, count_usb_devices());
ut_assertok(usb_stop());
- ut_asserteq(5, count_usb_devices());
+ ut_asserteq(6, count_usb_devices());
/* Remove the second emulation device */
ut_assertok(uclass_find_device_by_name(UCLASS_USB_EMUL, "flash-stick@1",
@@ -128,9 +128,9 @@
ut_asserteq(-ENODEV, uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
- ut_asserteq(4, count_usb_devices());
+ ut_asserteq(5, count_usb_devices());
ut_assertok(usb_stop());
- ut_asserteq(4, count_usb_devices());
+ ut_asserteq(5, count_usb_devices());
return 0;
}
@@ -147,7 +147,10 @@
" | sandbox flash flash-stick@1\n"
" | \n"
" |\b+-4 Mass Storage (12 Mb/s, 100mA)\n"
-" sandbox flash flash-stick@2\n"
+" | sandbox flash flash-stick@2\n"
+" | \n"
+" |\b+-5 Human Interface (12 Mb/s, 100mA)\n"
+" sandbox keyboard keyb@3\n"
" \n";
/* test that the 'usb tree' command output looks correct */
@@ -178,7 +181,10 @@
" | sandbox flash flash-stick@0\n"
" | \n"
" |\b+-3 Mass Storage (12 Mb/s, 100mA)\n"
-" sandbox flash flash-stick@2\n"
+" | sandbox flash flash-stick@2\n"
+" | \n"
+" |\b+-4 Human Interface (12 Mb/s, 100mA)\n"
+" sandbox keyboard keyb@3\n"
" \n";
/*
@@ -220,7 +226,10 @@
" |\b+-3 Mass Storage (12 Mb/s, 100mA)\n"
" | sandbox flash flash-stick@2\n"
" | \n"
-" |\b+-4 Mass Storage (12 Mb/s, 100mA)\n"
+" |\b+-4 Human Interface (12 Mb/s, 100mA)\n"
+" | sandbox keyboard keyb@3\n"
+" | \n"
+" |\b+-5 Mass Storage (12 Mb/s, 100mA)\n"
" sandbox flash flash-stick@1\n"
" \n";
diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
index fc41c04..043e5d0 100755
--- a/test/fs/fs-test.sh
+++ b/test/fs/fs-test.sh
@@ -100,7 +100,7 @@
# We save time by not deleting and recreating the file system images
function prepare_env() {
rm -f ${MD5_FILE}.* ${OUT}.*
- mkdir ${OUT_DIR}
+ mkdir -p ${OUT_DIR}
}
# 1st parameter is the name of the image file to be created
@@ -115,11 +115,23 @@
fi
if [ ! -f "$1" ]; then
fallocate -l 3G "$1" &> /dev/null
+ if [ $? -ne 0 ]; then
+ echo fallocate failed - using dd instead
+ dd if=/dev/zero of=$1 bs=1024 count=$((3 * 1024 * 1024))
+ if [ $? -ne 0 ]; then
+ echo Could not create empty disk image
+ exit $?
+ fi
+ fi
mkfs -t "$2" $MKFS_OPTION "$1" &> /dev/null
if [ $? -ne 0 -a "$2" = "fat" ]; then
# If we fail and we did fat, try vfat.
mkfs -t vfat $MKFS_OPTION "$1" &> /dev/null
fi
+ if [ $? -ne 0 ]; then
+ echo Could not create filesystem
+ exit $?
+ fi
fi
}
diff --git a/tools/Makefile b/tools/Makefile
index 7b4cd3f..1382b05 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -64,7 +64,7 @@
rsa-sign.o rsa-verify.o rsa-checksum.o \
rsa-mod-exp.o)
-ROCKCHIP_OBS = $(if $(CONFIG_ARCH_ROCKCHIP),lib/rc4.o rkcommon.o rkimage.o rksd.o,)
+ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
@@ -109,12 +109,6 @@
# TODO(sjg@chromium.org): Is this correct on Mac OS?
-ifneq ($(CONFIG_ARCH_ROCKCHIP),)
-HOST_EXTRACFLAGS += \
- -DCONFIG_ROCKCHIP_MAX_SPL_SIZE=$(CONFIG_ROCKCHIP_MAX_SPL_SIZE) \
- -DCONFIG_ROCKCHIP_SPL_HDR="\"$(CONFIG_ROCKCHIP_SPL_HDR)\""
-endif
-
ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# the mxsimage support within tools/mxsimage.c .
@@ -162,7 +156,7 @@
HOSTCFLAGS_ubsha1.o := -pedantic
hostprogs-$(CONFIG_KIRKWOOD) += kwboot
-hostprogs-$(CONFIG_ARMADA_XP) += kwboot
+hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot
hostprogs-y += proftool
hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
diff --git a/tools/kwboot.c b/tools/kwboot.c
index c5f4492..905ade3 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -9,10 +9,14 @@
* 2008. Chapter 24.2 "BootROM Firmware".
*/
+#include "kwbimage.h"
+#include "mkimage.h"
+
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
+#include <image.h>
#include <libgen.h>
#include <fcntl.h>
#include <errno.h>
@@ -22,8 +26,6 @@
#include <sys/mman.h>
#include <sys/stat.h>
-#include "kwbimage.h"
-
#ifdef __GNUC__
#define PACKED __attribute((packed))
#else
@@ -652,6 +654,14 @@
hdr->blockid = IBR_HDR_UART_ID;
+ /*
+ * Subtract mkimage header size from destination address
+ * as this header is not expected by the Marvell BootROM.
+ * This way, the execution address is identical to the
+ * one the image is compiled for (TEXT_BASE).
+ */
+ hdr->destaddr = hdr->destaddr - sizeof(struct image_header);
+
if (image_ver == 0) {
struct main_hdr_v0 *hdr_v0 = img;
diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
index 71c2e91..790c27e 100755
--- a/tools/microcode-tool.py
+++ b/tools/microcode-tool.py
@@ -95,9 +95,23 @@
name = os.path.splitext(name)[0]
data = []
with open(fname) as fd:
+ license_start = False
+ license_end = False
for line in fd:
line = line.rstrip()
+ if len(line) >= 2:
+ if line[0] == '/' and line[1] == '*':
+ license_start = True
+ continue
+ if line[0] == '*' and line[1] == '/':
+ license_end = True
+ continue
+ if license_start and not license_end:
+ # Ignore blank line
+ if len(line) > 0:
+ license_text.append(line)
+ continue
# Omit anything after the last comma
words = line.split(',')[:-1]
data += [word + ',' for word in words]
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 249c862..72621fd 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -40,16 +40,84 @@
uint8_t reserved2[2];
};
+/**
+ * struct spl_info - spl info for each chip
+ *
+ * @imagename: Image name(passed by "mkimage -n")
+ * @spl_hdr: Boot ROM requires a 4-bytes spl header
+ * @spl_size: Spl size(include extra 4-bytes spl header)
+ */
+struct spl_info {
+ const char *imagename;
+ const char *spl_hdr;
+ const uint32_t spl_size;
+};
+
+static struct spl_info spl_infos[] = {
+ { "rk3036", "RK30", 0x1000 },
+ { "rk3288", "RK32", 0x8000 },
+};
+
static unsigned char rc4_key[16] = {
124, 78, 3, 4, 85, 5, 9, 7,
45, 44, 123, 56, 23, 13, 23, 17
};
+static struct spl_info *rkcommon_get_spl_info(char *imagename)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(spl_infos); i++)
+ if (!strncmp(imagename, spl_infos[i].imagename, 6))
+ return spl_infos + i;
+
+ return NULL;
+}
+
+int rkcommon_check_params(struct image_tool_params *params)
+{
+ int i;
+
-int rkcommon_set_header(void *buf, uint file_size)
+ if (rkcommon_get_spl_info(params->imagename) != NULL)
+ return 0;
+
+ fprintf(stderr, "ERROR: imagename (%s) is not supported!\n",
+ strlen(params->imagename) > 0 ? params->imagename : "NULL");
+
+ fprintf(stderr, "Available imagename:");
+ for (i = 0; i < ARRAY_SIZE(spl_infos); i++)
+ fprintf(stderr, "\t%s", spl_infos[i].imagename);
+ fprintf(stderr, "\n");
+
+ return -1;
+}
+
+const char *rkcommon_get_spl_hdr(struct image_tool_params *params)
+{
+ struct spl_info *info = rkcommon_get_spl_info(params->imagename);
+
+ /*
+ * info would not be NULL, because of we checked params before.
+ */
+ return info->spl_hdr;
+}
+
+int rkcommon_get_spl_size(struct image_tool_params *params)
+{
+ struct spl_info *info = rkcommon_get_spl_info(params->imagename);
+
+ /*
+ * info would not be NULL, because of we checked params before.
+ */
+ return info->spl_size;
+}
+
+int rkcommon_set_header(void *buf, uint file_size,
+ struct image_tool_params *params)
{
struct header0_info *hdr;
- if (file_size > CONFIG_ROCKCHIP_MAX_SPL_SIZE)
+ if (file_size > rkcommon_get_spl_size(params))
return -ENOSPC;
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
diff --git a/tools/rkcommon.h b/tools/rkcommon.h
index 0fc1e96..c69540f 100644
--- a/tools/rkcommon.h
+++ b/tools/rkcommon.h
@@ -12,9 +12,38 @@
RK_BLK_SIZE = 512,
RK_INIT_OFFSET = 4,
RK_MAX_BOOT_SIZE = 512 << 10,
+ RK_SPL_HDR_START = RK_INIT_OFFSET * RK_BLK_SIZE,
+ RK_SPL_HDR_SIZE = 4,
+ RK_SPL_START = RK_SPL_HDR_START + RK_SPL_HDR_SIZE,
+ RK_IMAGE_HEADER_LEN = RK_SPL_START,
};
/**
+ * rkcommon_check_params() - check params
+ *
+ * @return 0 if OK, -1 if ERROR.
+ */
+int rkcommon_check_params(struct image_tool_params *params);
+
+/**
+ * rkcommon_get_spl_hdr() - get 4-bytes spl hdr for a Rockchip boot image
+ *
+ * Rockchip's bootrom requires the spl loader to start with a 4-bytes
+ * header. The content of this header depends on the chip type.
+ */
+const char *rkcommon_get_spl_hdr(struct image_tool_params *params);
+
+/**
+ * rkcommon_get_spl_size() - get spl size for a Rockchip boot image
+ *
+ * Different chip may have different sram size. And if we want to jump
+ * back to the bootrom after spl, we may need to reserve some sram space
+ * for the bootrom.
+ * The spl loader size should be sram size minus reserved size(if needed)
+ */
+int rkcommon_get_spl_size(struct image_tool_params *params);
+
+/**
* rkcommon_set_header() - set up the header for a Rockchip boot image
*
* This sets up a 2KB header which can be interpreted by the Rockchip boot ROM.
@@ -23,6 +52,7 @@
* @file_size: Size of the file we want the boot ROM to load, in bytes
* @return 0 if OK, -ENOSPC if too large
*/
-int rkcommon_set_header(void *buf, uint file_size);
+int rkcommon_set_header(void *buf, uint file_size,
+ struct image_tool_params *params);
#endif
diff --git a/tools/rkimage.c b/tools/rkimage.c
index 73634e3..f9fdcfa 100644
--- a/tools/rkimage.c
+++ b/tools/rkimage.c
@@ -9,6 +9,7 @@
#include "imagetool.h"
#include <image.h>
+#include "rkcommon.h"
static uint32_t header;
@@ -30,7 +31,8 @@
static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
- memcpy(buf, CONFIG_ROCKCHIP_SPL_HDR, 4);
+ memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params),
+ RK_SPL_HDR_SIZE);
}
static int rkimage_extract_subimage(void *buf, struct image_tool_params *params)
diff --git a/tools/rksd.c b/tools/rksd.c
index f660d56..a2baa74 100644
--- a/tools/rksd.c
+++ b/tools/rksd.c
@@ -13,18 +13,7 @@
#include "mkimage.h"
#include "rkcommon.h"
-enum {
- RKSD_SPL_HDR_START = RK_INIT_OFFSET * RK_BLK_SIZE,
- RKSD_SPL_START = RKSD_SPL_HDR_START + 4,
- RKSD_HEADER_LEN = RKSD_SPL_START,
-};
-
-static char dummy_hdr[RKSD_HEADER_LEN];
-
-static int rksd_check_params(struct image_tool_params *params)
-{
- return 0;
-}
+static char dummy_hdr[RK_IMAGE_HEADER_LEN];
static int rksd_verify_header(unsigned char *buf, int size,
struct image_tool_params *params)
@@ -42,15 +31,16 @@
unsigned int size;
int ret;
- size = params->file_size - RKSD_SPL_HDR_START;
- ret = rkcommon_set_header(buf, size);
+ size = params->file_size - RK_SPL_HDR_START;
+ ret = rkcommon_set_header(buf, size, params);
if (ret) {
/* TODO(sjg@chromium.org): This method should return an error */
printf("Warning: SPL image is too large (size %#x) and will not boot\n",
size);
}
- memcpy(buf + RKSD_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4);
+ memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params),
+ RK_SPL_HDR_SIZE);
}
static int rksd_extract_subimage(void *buf, struct image_tool_params *params)
@@ -72,7 +62,7 @@
{
int pad_size;
- pad_size = RKSD_SPL_HDR_START + CONFIG_ROCKCHIP_MAX_SPL_SIZE;
+ pad_size = RK_SPL_HDR_START + rkcommon_get_spl_size(params);
debug("pad_size %x\n", pad_size);
return pad_size - params->file_size;
@@ -84,9 +74,9 @@
U_BOOT_IMAGE_TYPE(
rksd,
"Rockchip SD Boot Image support",
- RKSD_HEADER_LEN,
+ RK_IMAGE_HEADER_LEN,
dummy_hdr,
- rksd_check_params,
+ rkcommon_check_params,
rksd_verify_header,
rksd_print_header,
rksd_set_header,
diff --git a/tools/rkspi.c b/tools/rkspi.c
index 69a12f0..a0b0051 100644
--- a/tools/rkspi.c
+++ b/tools/rkspi.c
@@ -14,18 +14,10 @@
#include "rkcommon.h"
enum {
- RKSPI_SPL_HDR_START = RK_INIT_OFFSET * RK_BLK_SIZE,
- RKSPI_SPL_START = RKSPI_SPL_HDR_START + 4,
- RKSPI_HEADER_LEN = RKSPI_SPL_START,
RKSPI_SECT_LEN = RK_BLK_SIZE * 4,
};
-static char dummy_hdr[RKSPI_HEADER_LEN];
-
-static int rkspi_check_params(struct image_tool_params *params)
-{
- return 0;
-}
+static char dummy_hdr[RK_IMAGE_HEADER_LEN];
static int rkspi_verify_header(unsigned char *buf, int size,
struct image_tool_params *params)
@@ -45,7 +37,7 @@
int ret;
size = params->orig_file_size;
- ret = rkcommon_set_header(buf, size);
+ ret = rkcommon_set_header(buf, size, params);
debug("size %x\n", size);
if (ret) {
/* TODO(sjg@chromium.org): This method should return an error */
@@ -53,7 +45,8 @@
size);
}
- memcpy(buf + RKSPI_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4);
+ memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params),
+ RK_SPL_HDR_SIZE);
/*
* Spread the image out so we only use the first 2KB of each 4KB
@@ -61,7 +54,7 @@
* boot ROM. Its rationale is unknown.
*/
for (sector = size / RKSPI_SECT_LEN - 1; sector >= 0; sector--) {
- printf("sector %u\n", sector);
+ debug("sector %u\n", sector);
memmove(buf + sector * RKSPI_SECT_LEN * 2,
buf + sector * RKSPI_SECT_LEN,
RKSPI_SECT_LEN);
@@ -89,12 +82,12 @@
{
int pad_size;
- pad_size = (CONFIG_ROCKCHIP_MAX_SPL_SIZE + 0x7ff) / 0x800 * 0x800;
+ pad_size = (rkcommon_get_spl_size(params) + 0x7ff) / 0x800 * 0x800;
params->orig_file_size = pad_size;
/* We will double the image size due to the SPI format */
pad_size *= 2;
- pad_size += RKSPI_SPL_HDR_START;
+ pad_size += RK_SPL_HDR_START;
debug("pad_size %x\n", pad_size);
return pad_size - params->file_size;
@@ -106,9 +99,9 @@
U_BOOT_IMAGE_TYPE(
rkspi,
"Rockchip SPI Boot Image support",
- RKSPI_HEADER_LEN,
+ RK_IMAGE_HEADER_LEN,
dummy_hdr,
- rkspi_check_params,
+ rkcommon_check_params,
rkspi_verify_header,
rkspi_print_header,
rkspi_set_header,
diff --git a/tools/zynqimage.c b/tools/zynqimage.c
index 25f558d..c43bd5d 100644
--- a/tools/zynqimage.c
+++ b/tools/zynqimage.c
@@ -212,8 +212,7 @@
return -1;
}
- return !((params->lflag || params->dflag) ||
- (params->dflag && params->eflag));
+ return !(params->lflag || params->dflag);
}
static int zynqimage_check_image_types(uint8_t type)