* Fix PCI support for MPC5200 / IceCube Board
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 2a455f8..bf09b01 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -37,7 +37,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
@@ -49,10 +49,41 @@
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#define CONFIG_PCI_SCAN_SHOW 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_EEPRO100 1
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+
+#define ADD_PCI_CMD CFG_CMD_PCI
+
+#else /* MPC5100 */
+
+#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
+
+#endif
+
/*
* Supported commands
*/
-#define CONFIG_COMMANDS CONFIG_CMD_DFL
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -83,17 +114,17 @@
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
+#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
/*
* Environment settings
*/
-#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
-#define CFG_ENV_SECT_SIZE 0x10000
-
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
+#define CFG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_OVERWRITE 1
/*
* Memory map
@@ -112,7 +143,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT 1
+# define CFG_RAMBOOT 1
#endif
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index e0f2367..b803d03 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -61,6 +61,10 @@
#if defined(CONFIG_MGT5100)
#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
+#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
+#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
+#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
+#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
#elif defined(CONFIG_MPC5200)
#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
@@ -75,6 +79,7 @@
#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
+#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
@@ -136,6 +141,33 @@
/* GPIO registers */
#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
+/* PCI registers */
+#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
+#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
+#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
+#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
+#if defined(CONFIG_MGT5100)
+#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
+#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
+#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
+#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
+#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
+#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
+#elif defined(CONFIG_MPC5200)
+#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
+#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
+#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
+#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
+#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
+#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
+#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
+#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
+#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
+#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
+#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
+#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
+#endif
+
/* Interrupt Controller registers */
#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)