diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3b5fd25..6b7589b 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -163,6 +163,7 @@
 #define CHIP_REV_1_0                 0x10
 #define IRAM_SIZE                    0x00040000
 #define IMX_IIM_BASE                 OCOTP_BASE_ADDR
+#define FEC_QUIRK_ENET_MAC
 
 #define GPIO_NUMBER(port, index)		((((port)-1)*32)+((index)&31))
 #define GPIO_TO_PORT(number)		(((number)/32)+1)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ed73353..db8ebfa 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -379,13 +379,14 @@
 static int fec_open(struct eth_device *edev)
 {
 	struct fec_priv *fec = (struct fec_priv *)edev->priv;
+	int speed;
 
 	debug("fec_open: fec_open(dev)\n");
 	/* full-duplex, heartbeat disabled */
 	writel(1 << 2, &fec->eth->x_cntrl);
 	fec->rbd_index = 0;
 
-#if defined(CONFIG_MX6Q)
+#ifdef FEC_QUIRK_ENET_MAC
 	/* Enable ENET HW endian SWAP */
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
 		&fec->eth->ecntrl);
@@ -428,9 +429,25 @@
 #endif
 
 	miiphy_wait_aneg(edev);
-	miiphy_speed(edev->name, fec->phy_id);
+	speed = miiphy_speed(edev->name, fec->phy_id);
 	miiphy_duplex(edev->name, fec->phy_id);
 
+#ifdef FEC_QUIRK_ENET_MAC
+	{
+		u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
+		u32 rcr = (readl(&fec->eth->r_cntrl) &
+				~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
+				FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+		if (speed == _1000BASET)
+			ecr |= FEC_ECNTRL_SPEED;
+		else if (speed != _100BASET)
+			rcr |= FEC_RCNTRL_RMII_10T;
+		writel(ecr, &fec->eth->ecntrl);
+		writel(rcr, &fec->eth->r_cntrl);
+	}
+#endif
+	debug("%s:Speed=%i\n", __func__, speed);
+
 	/*
 	 * Enable SmartDMA receive task
 	 */
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 9825eab..af33d21 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -198,6 +198,7 @@
 #define FEC_RCNTRL_FCE			0x00000020
 #define FEC_RCNTRL_RGMII		0x00000040
 #define FEC_RCNTRL_RMII			0x00000100
+#define FEC_RCNTRL_RMII_10T		0x00000200
 
 #define FEC_TCNTRL_GTS			0x00000001
 #define FEC_TCNTRL_HBC			0x00000002
@@ -207,6 +208,7 @@
 
 #define FEC_ECNTRL_RESET		0x00000001	/* reset the FEC */
 #define FEC_ECNTRL_ETHER_EN		0x00000002	/* enable the FEC */
+#define FEC_ECNTRL_SPEED		0x00000020
 #define FEC_ECNTRL_DBSWAP		0x00000100
 
 #define FEC_X_WMRK_STRFWD		0x00000100