clk: rockchip: rk3308: Fix ordering between masking and shifting
As per definitions of masks and shift offsets in cru_rk3308.h, values
read from registers must be first masked and then shifted. By the way,
this fix is binary invariant, because in all of fixed cases the shift
offset is zero.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index 64f3358..d27673c 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -150,7 +150,7 @@
}
con = readl(&cru->clksel_con[con_id]);
- div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
+ div = (con & CLK_I2C_DIV_CON_MASK) >> CLK_I2C_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->dpll_hz, div);
}
@@ -314,7 +314,7 @@
u32 div, con;
con = readl(&cru->clksel_con[34]);
- div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
+ div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
return DIV_TO_RATE(OSC_HZ, div);
}
@@ -342,7 +342,7 @@
u32 div, con;
con = readl(&cru->clksel_con[33]);
- div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
+ div = (con & CLK_SARADC_DIV_CON_MASK) >> CLK_SARADC_DIV_CON_SHIFT;
return DIV_TO_RATE(OSC_HZ, div);
}
@@ -385,7 +385,7 @@
}
con = readl(&cru->clksel_con[con_id]);
- div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
+ div = (con & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->dpll_hz, div);
}
@@ -429,7 +429,7 @@
u32 div, con;
con = readl(&cru->clksel_con[29]);
- div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
+ div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->dpll_hz, div);
}