commit 008e43cb9bf652fb594ce97871bac4598b11d8b5
author Hugh Cole-Baker <sigmaris@gmail.com> Sun Nov 22 13:03:44 2020 +0000
committer Tom Rini <trini@konsulko.com> Fri Jan 08 08:40:43 2021 -0500
tree 621f02fa10533bf76cabc0b63c6b59b0fe1c1f15
parent 37ea9a8811752d8f454364cd05f2f4b9d44bb739

rockchip: pinebook-pro: default to SPI bus 1 for SPI-flash

SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")

configs/pinebook-pro-rk3399_defconfig

diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig
index 8fbd728..a471c3e 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -37,6 +37,7 @@
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_DM_KEYBOARD=y
@@ -49,6 +50,7 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y