arm: imx: imx8m: Map RAM as NS if PSCI provider
In case U-Boot is a PSCI provider, map RAM explicitly as NS,
otherwise secondary cores crash with SError when attempting
to access RAM mapped as secure in EL2.
Signed-off-by: Marek Vasut <marex@denx.de>
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 93e10bf..cad9200 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -100,6 +100,12 @@
setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
}
+#ifdef CONFIG_ARMV8_PSCI
+#define PTE_MAP_NS PTE_BLOCK_NS
+#else
+#define PTE_MAP_NS 0
+#endif
+
static struct mm_region imx8m_mem_map[] = {
{
/* ROM */
@@ -122,7 +128,7 @@
.phys = 0x180000UL,
.size = 0x8000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE
+ PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
}, {
/* TCM */
.virt = 0x7C0000UL,
@@ -130,14 +136,14 @@
.size = 0x80000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS
}, {
/* OCRAM */
.virt = 0x900000UL,
.phys = 0x900000UL,
.size = 0x200000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE
+ PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
}, {
/* AIPS */
.virt = 0xB00000UL,
@@ -152,7 +158,7 @@
.phys = 0x40000000UL,
.size = PHYS_SDRAM_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE
+ PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
#ifdef PHYS_SDRAM_2_SIZE
}, {
/* DRAM2 */
@@ -160,7 +166,7 @@
.phys = 0x100000000UL,
.size = PHYS_SDRAM_2_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_OUTER_SHARE
+ PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
#endif
}, {
/* empty entrie to split table entry 5 if needed when TEEs are used */