blob: d39e83d769ddcee92c23c460264c2a334c1b3e04 [file] [log] [blame]
developer3262bf82022-07-12 11:37:54 +08001From 9c76671cd831d28e5b270baa23c71dfc4aaf8410 Mon Sep 17 00:00:00 2001
developer42b63282022-06-16 13:33:13 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Thu, 21 Apr 2022 15:43:19 +0800
developer3262bf82022-07-12 11:37:54 +08004Subject: [PATCH] mt76: testmode: additional supports
developer42b63282022-06-16 13:33:13 +08005
6Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
7---
developeraace7f52022-06-24 13:40:42 +08008 dma.c | 3 +-
9 mac80211.c | 12 +
10 mt76.h | 111 ++++-
11 mt76_connac_mcu.c | 4 +
12 mt76_connac_mcu.h | 2 +
13 mt7915/init.c | 2 +-
14 mt7915/mac.c | 37 +-
15 mt7915/main.c | 2 +-
16 mt7915/mcu.c | 10 +-
17 mt7915/mcu.h | 28 +-
18 mt7915/mmio.c | 2 +
19 mt7915/mt7915.h | 14 +-
20 mt7915/regs.h | 3 +
21 mt7915/testmode.c | 1171 ++++++++++++++++++++++++++++++++++++++++++---
22 mt7915/testmode.h | 278 +++++++++++
developer3262bf82022-07-12 11:37:54 +080023 testmode.c | 275 +++++++++--
developeraace7f52022-06-24 13:40:42 +080024 testmode.h | 75 +++
25 tools/fields.c | 80 ++++
26 tx.c | 3 +-
developer3262bf82022-07-12 11:37:54 +080027 19 files changed, 1963 insertions(+), 149 deletions(-)
developer42b63282022-06-16 13:33:13 +080028
29diff --git a/dma.c b/dma.c
developer3262bf82022-07-12 11:37:54 +080030index f22273cd..03ee9109 100644
developer42b63282022-06-16 13:33:13 +080031--- a/dma.c
32+++ b/dma.c
33@@ -426,8 +426,7 @@ free:
34 if (mt76_is_testmode_skb(dev, skb, &hw)) {
35 struct mt76_phy *phy = hw->priv;
36
37- if (tx_info.skb == phy->test.tx_skb)
38- phy->test.tx_done--;
39+ phy->test.tx_done--;
40 }
41 #endif
42
43diff --git a/mac80211.c b/mac80211.c
developer3262bf82022-07-12 11:37:54 +080044index a7e082f7..9984def5 100644
developer42b63282022-06-16 13:33:13 +080045--- a/mac80211.c
46+++ b/mac80211.c
47@@ -55,6 +55,13 @@ static const struct ieee80211_channel mt76_channels_5ghz[] = {
48 CHAN5G(60, 5300),
49 CHAN5G(64, 5320),
50
51+ CHAN5G(68, 5340),
52+ CHAN5G(80, 5400),
53+ CHAN5G(84, 5420),
54+ CHAN5G(88, 5440),
55+ CHAN5G(92, 5460),
56+ CHAN5G(96, 5480),
57+
58 CHAN5G(100, 5500),
59 CHAN5G(104, 5520),
60 CHAN5G(108, 5540),
61@@ -75,6 +82,11 @@ static const struct ieee80211_channel mt76_channels_5ghz[] = {
62 CHAN5G(165, 5825),
63 CHAN5G(169, 5845),
64 CHAN5G(173, 5865),
65+
66+ CHAN5G(184, 4920),
67+ CHAN5G(188, 4940),
68+ CHAN5G(192, 4960),
69+ CHAN5G(196, 4980),
70 };
71
72 static const struct ieee80211_channel mt76_channels_6ghz[] = {
73diff --git a/mt76.h b/mt76.h
developer3262bf82022-07-12 11:37:54 +080074index 8325409a..4c8a671f 100644
developer42b63282022-06-16 13:33:13 +080075--- a/mt76.h
76+++ b/mt76.h
77@@ -602,6 +602,21 @@ struct mt76_testmode_ops {
78 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
79 enum mt76_testmode_state new_state);
80 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
81+ int (*set_eeprom)(struct mt76_phy *phy, u32 offset, u8 *val, u8 action);
82+};
83+
84+struct mt76_testmode_entry_data {
85+ struct sk_buff *tx_skb;
86+
87+ u16 tx_mpdu_len;
88+ u8 tx_rate_idx;
89+ u8 tx_rate_nss;
90+ u8 tx_rate_ldpc;
91+
92+ u8 addr[3][ETH_ALEN];
93+ u8 aid;
94+ u8 ru_alloc;
95+ u8 ru_idx;
96 };
97
98 #define MT_TM_FW_RX_COUNT BIT(0)
99@@ -610,16 +625,11 @@ struct mt76_testmode_data {
100 enum mt76_testmode_state state;
101
102 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
103- struct sk_buff *tx_skb;
104
105 u32 tx_count;
106- u16 tx_mpdu_len;
107
108 u8 tx_rate_mode;
109- u8 tx_rate_idx;
110- u8 tx_rate_nss;
111 u8 tx_rate_sgi;
112- u8 tx_rate_ldpc;
113 u8 tx_rate_stbc;
114 u8 tx_ltf;
115
116@@ -635,10 +645,37 @@ struct mt76_testmode_data {
117 u8 tx_power[4];
118 u8 tx_power_control;
119
120- u8 addr[3][ETH_ALEN];
121+ struct list_head tm_entry_list;
122+ struct mt76_wcid *cur_entry;
123+ u8 entry_num;
124+ union {
125+ struct mt76_testmode_entry_data ed;
126+ struct {
127+ /* must be the same as mt76_testmode_entry_data */
128+ struct sk_buff *tx_skb;
129+
130+ u16 tx_mpdu_len;
131+ u8 tx_rate_idx;
132+ u8 tx_rate_nss;
133+ u8 tx_rate_ldpc;
134+
135+ u8 addr[3][ETH_ALEN];
136+ u8 aid;
137+ u8 ru_alloc;
138+ u8 ru_idx;
139+ };
140+ };
141
142 u8 flag;
143
144+ struct {
145+ u8 type;
146+ u8 enable;
147+ } cfg;
148+
149+ u8 txbf_act;
150+ u16 txbf_param[8];
151+
152 u32 tx_pending;
153 u32 tx_queued;
154 u16 tx_queued_limit;
155@@ -1120,14 +1157,69 @@ static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
156 #endif
157 }
158
159+#ifdef CONFIG_NL80211_TESTMODE
160+static inline struct mt76_wcid *
161+mt76_testmode_first_entry(struct mt76_phy *phy)
162+{
163+ if (list_empty(&phy->test.tm_entry_list) && !phy->test.aid)
164+ return &phy->dev->global_wcid;
165+
166+ return list_first_entry(&phy->test.tm_entry_list,
167+ typeof(struct mt76_wcid),
168+ list);
169+}
170+
171+static inline struct mt76_testmode_entry_data *
172+mt76_testmode_entry_data(struct mt76_phy *phy, struct mt76_wcid *wcid)
173+{
174+ if (!wcid)
175+ return NULL;
176+ if (wcid == &phy->dev->global_wcid)
177+ return &phy->test.ed;
178+
179+ return (struct mt76_testmode_entry_data *)((u8 *)wcid +
180+ phy->hw->sta_data_size);
181+}
182+
183+#define mt76_tm_for_each_entry(phy, wcid, ed) \
184+ for (wcid = mt76_testmode_first_entry(phy), \
185+ ed = mt76_testmode_entry_data(phy, wcid); \
186+ ((phy->test.aid && \
187+ !list_entry_is_head(wcid, &phy->test.tm_entry_list, list)) || \
188+ (!phy->test.aid && wcid == &phy->dev->global_wcid)) && ed; \
189+ wcid = list_next_entry(wcid, list), \
190+ ed = mt76_testmode_entry_data(phy, wcid))
191+#endif
192+
193+static inline bool __mt76_is_testmode_skb(struct mt76_phy *phy,
194+ struct sk_buff *skb)
195+{
196+#ifdef CONFIG_NL80211_TESTMODE
197+ struct mt76_testmode_entry_data *ed = &phy->test.ed;
198+ struct mt76_wcid *wcid;
199+
200+ if (skb == ed->tx_skb)
201+ return true;
202+
203+ mt76_tm_for_each_entry(phy, wcid, ed)
204+ if (skb == ed->tx_skb)
205+ return true;
206+ return false;
207+#else
208+ return false;
209+#endif
210+}
211+
212 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
213 struct sk_buff *skb,
214 struct ieee80211_hw **hw)
215 {
216 #ifdef CONFIG_NL80211_TESTMODE
217- if (skb == dev->phy.test.tx_skb)
218+ if (mt76_testmode_enabled(&dev->phy) &&
219+ __mt76_is_testmode_skb(&dev->phy, skb))
220 *hw = dev->phy.hw;
221- else if (dev->phy2 && skb == dev->phy2->test.tx_skb)
222+ else if (dev->phy2 && mt76_testmode_enabled(dev->phy2) &&
223+ __mt76_is_testmode_skb(dev->phy2, skb))
224 *hw = dev->phy2->hw;
225 else
226 return false;
227@@ -1227,7 +1319,8 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
228 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
229 struct netlink_callback *cb, void *data, int len);
230 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
231-int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
232+int mt76_testmode_init_skb(struct mt76_phy *phy, u32 len,
233+ struct sk_buff **tx_skb, u8 (*addr)[ETH_ALEN]);
234
235 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
236 {
237diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developer3262bf82022-07-12 11:37:54 +0800238index 261181dc..cd350689 100644
developer42b63282022-06-16 13:33:13 +0800239--- a/mt76_connac_mcu.c
240+++ b/mt76_connac_mcu.c
developeraace7f52022-06-24 13:40:42 +0800241@@ -391,6 +391,7 @@ void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
developer42b63282022-06-16 13:33:13 +0800242 switch (vif->type) {
243 case NL80211_IFTYPE_MESH_POINT:
244 case NL80211_IFTYPE_AP:
245+ case NL80211_IFTYPE_MONITOR:
246 if (vif->p2p)
247 conn_type = CONNECTION_P2P_GC;
248 else
developeraace7f52022-06-24 13:40:42 +0800249@@ -572,6 +573,9 @@ void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev,
developer42b63282022-06-16 13:33:13 +0800250 rx->rca2 = 1;
251 rx->rv = 1;
252
253+ if (vif->type == NL80211_IFTYPE_MONITOR)
254+ rx->rca1 = 0;
255+
256 if (!is_connac_v1(dev))
257 return;
258
259diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developer3262bf82022-07-12 11:37:54 +0800260index 32e540cc..a0e6fa6e 100644
developer42b63282022-06-16 13:33:13 +0800261--- a/mt76_connac_mcu.h
262+++ b/mt76_connac_mcu.h
developeraace7f52022-06-24 13:40:42 +0800263@@ -967,6 +967,7 @@ enum {
developer42b63282022-06-16 13:33:13 +0800264 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
265 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
266 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
267+ MCU_EXT_EVENT_BF_STATUS_READ = 0x35,
268 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
269 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
270 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
developeraace7f52022-06-24 13:40:42 +0800271@@ -1144,6 +1145,7 @@ enum {
developer42b63282022-06-16 13:33:13 +0800272 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
273 /* for vendor csi and air monitor */
274 MCU_EXT_CMD_SMESH_CTRL = 0xae,
275+ MCU_EXT_CMD_RX_STAT_USER_CTRL = 0xb3,
276 MCU_EXT_CMD_CERT_CFG = 0xb7,
277 MCU_EXT_CMD_CSI_CTRL = 0xc2,
278 };
279diff --git a/mt7915/init.c b/mt7915/init.c
developer3262bf82022-07-12 11:37:54 +0800280index 0d5109a3..b549fa04 100644
developer42b63282022-06-16 13:33:13 +0800281--- a/mt7915/init.c
282+++ b/mt7915/init.c
developeraace7f52022-06-24 13:40:42 +0800283@@ -576,7 +576,7 @@ static void mt7915_init_work(struct work_struct *work)
developer42b63282022-06-16 13:33:13 +0800284 struct mt7915_dev *dev = container_of(work, struct mt7915_dev,
285 init_work);
286
287- mt7915_mcu_set_eeprom(dev);
288+ mt7915_mcu_set_eeprom(dev, dev->flash_mode);
289 mt7915_mac_init(dev);
290 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband);
291 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband);
292diff --git a/mt7915/mac.c b/mt7915/mac.c
developer3262bf82022-07-12 11:37:54 +0800293index f13456bf..5e5df23d 100644
developer42b63282022-06-16 13:33:13 +0800294--- a/mt7915/mac.c
295+++ b/mt7915/mac.c
developeraace7f52022-06-24 13:40:42 +0800296@@ -565,17 +565,39 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
developer42b63282022-06-16 13:33:13 +0800297 {
298 #ifdef CONFIG_NL80211_TESTMODE
299 struct mt76_testmode_data *td = &phy->mt76->test;
300+ struct mt76_testmode_entry_data *ed;
301+ struct mt76_wcid *wcid;
302 const struct ieee80211_rate *r;
303- u8 bw, mode, nss = td->tx_rate_nss;
304- u8 rate_idx = td->tx_rate_idx;
305+ u8 bw, mode, nss, rate_idx, ldpc;
306 u16 rateval = 0;
307 u32 val;
308 bool cck = false;
309 int band;
310
311- if (skb != phy->mt76->test.tx_skb)
312+ txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
313+ txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
314+ phy->test.spe_idx));
315+
316+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU) {
317+ txwi[1] |= cpu_to_le32(BIT(18));
318+ txwi[2] = 0;
319+ txwi[3] &= ~cpu_to_le32(MT_TXD3_NO_ACK);
320+ le32p_replace_bits(&txwi[3], 0x1f, MT_TXD3_REM_TX_COUNT);
321+
322+ return;
323+ }
324+
325+ mt76_tm_for_each_entry(phy->mt76, wcid, ed)
326+ if (ed->tx_skb == skb)
327+ break;
328+
329+ if (!ed)
330 return;
331
332+ nss = ed->tx_rate_nss;
333+ rate_idx = ed->tx_rate_idx;
334+ ldpc = ed->tx_rate_ldpc;
335+
336 switch (td->tx_rate_mode) {
337 case MT76_TM_TX_MODE_HT:
338 nss = 1 + (rate_idx >> 3);
developeraace7f52022-06-24 13:40:42 +0800339@@ -664,14 +686,13 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
developer42b63282022-06-16 13:33:13 +0800340 if (mode >= MT_PHY_TYPE_HE_SU)
341 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf);
342
343- if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
344+ if (ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
345 val |= MT_TXD6_LDPC;
346
347- txwi[1] &= ~cpu_to_le32(MT_TXD1_VTA);
348- txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
349+ if (phy->test.bf_en)
350+ val |= MT_TXD6_TX_IBF | MT_TXD6_TX_EBF;
351+
352 txwi[6] |= cpu_to_le32(val);
353- txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
354- phy->test.spe_idx));
355 #endif
356 }
357
358diff --git a/mt7915/main.c b/mt7915/main.c
developer3262bf82022-07-12 11:37:54 +0800359index dc5e4b0f..e4b20766 100644
developer42b63282022-06-16 13:33:13 +0800360--- a/mt7915/main.c
361+++ b/mt7915/main.c
developeraace7f52022-06-24 13:40:42 +0800362@@ -224,7 +224,7 @@ static int mt7915_add_interface(struct ieee80211_hw *hw,
developer42b63282022-06-16 13:33:13 +0800363 mvif->phy = phy;
364 mvif->mt76.band_idx = phy->band_idx;
365
366- mvif->mt76.wmm_idx = vif->type != NL80211_IFTYPE_AP;
367+ mvif->mt76.wmm_idx = (vif->type != NL80211_IFTYPE_AP && vif->type != NL80211_IFTYPE_MONITOR);
368 if (ext_phy)
369 mvif->mt76.wmm_idx += 2;
370
371diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer3262bf82022-07-12 11:37:54 +0800372index fa8f51da..41a8e7e2 100644
developer42b63282022-06-16 13:33:13 +0800373--- a/mt7915/mcu.c
374+++ b/mt7915/mcu.c
developeraace7f52022-06-24 13:40:42 +0800375@@ -434,6 +434,11 @@ mt7915_mcu_rx_ext_event(struct mt7915_dev *dev, struct sk_buff *skb)
developer42b63282022-06-16 13:33:13 +0800376 case MCU_EXT_EVENT_BCC_NOTIFY:
377 mt7915_mcu_rx_bcc_notify(dev, skb);
378 break;
379+#ifdef CONFIG_NL80211_TESTMODE
380+ case MCU_EXT_EVENT_BF_STATUS_READ:
381+ mt7915_tm_txbf_status_read(dev, skb);
382+ break;
383+#endif
384 default:
385 break;
386 }
developeraace7f52022-06-24 13:40:42 +0800387@@ -465,6 +470,7 @@ void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb)
developer42b63282022-06-16 13:33:13 +0800388 rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP ||
389 rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC ||
390 rxd->ext_eid == MCU_EXT_EVENT_BCC_NOTIFY ||
391+ rxd->ext_eid == MCU_EXT_EVENT_BF_STATUS_READ ||
392 !rxd->seq)
393 mt7915_mcu_rx_unsolicited_event(dev, skb);
394 else
developer3262bf82022-07-12 11:37:54 +0800395@@ -2809,14 +2815,14 @@ static int mt7915_mcu_set_eeprom_flash(struct mt7915_dev *dev)
developer42b63282022-06-16 13:33:13 +0800396 return 0;
397 }
398
399-int mt7915_mcu_set_eeprom(struct mt7915_dev *dev)
400+int mt7915_mcu_set_eeprom(struct mt7915_dev *dev, bool flash_mode)
401 {
402 struct mt7915_mcu_eeprom req = {
403 .buffer_mode = EE_MODE_EFUSE,
404 .format = EE_FORMAT_WHOLE,
405 };
406
407- if (dev->flash_mode)
408+ if (flash_mode)
409 return mt7915_mcu_set_eeprom_flash(dev);
410
411 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(EFUSE_BUFFER_MODE),
412diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer3262bf82022-07-12 11:37:54 +0800413index 15b74732..1b147421 100644
developer42b63282022-06-16 13:33:13 +0800414--- a/mt7915/mcu.h
415+++ b/mt7915/mcu.h
developeraace7f52022-06-24 13:40:42 +0800416@@ -8,10 +8,15 @@
developer42b63282022-06-16 13:33:13 +0800417
418 enum {
419 MCU_ATE_SET_TRX = 0x1,
420+ MCU_ATE_SET_TSSI = 0x5,
421+ MCU_ATE_SET_DPD = 0x6,
422+ MCU_ATE_SET_RATE_POWER_OFFSET = 0x7,
423+ MCU_ATE_SET_THERMAL_COMP = 0x8,
424 MCU_ATE_SET_FREQ_OFFSET = 0xa,
425 MCU_ATE_SET_PHY_COUNT = 0x11,
426 MCU_ATE_SET_SLOT_TIME = 0x13,
427 MCU_ATE_CLEAN_TXQUEUE = 0x1c,
428+ MCU_ATE_SET_MU_RX_AID = 0x1e,
429 };
430
developeraace7f52022-06-24 13:40:42 +0800431 struct mt7915_mcu_thermal_ctrl {
432@@ -431,6 +436,12 @@ enum {
developer42b63282022-06-16 13:33:13 +0800433
434 enum {
435 MT_BF_SOUNDING_ON = 1,
436+ MT_BF_DATA_PACKET_APPLY = 2,
437+ MT_BF_PFMU_TAG_READ = 5,
438+ MT_BF_PFMU_TAG_WRITE = 6,
439+ MT_BF_PHASE_CAL = 14,
440+ MT_BF_IBF_PHASE_COMP = 15,
441+ MT_BF_PROFILE_WRITE_ALL = 17,
442 MT_BF_TYPE_UPDATE = 20,
443 MT_BF_MODULE_UPDATE = 25
444 };
developer3262bf82022-07-12 11:37:54 +0800445@@ -664,10 +675,19 @@ struct mt7915_muru {
developer42b63282022-06-16 13:33:13 +0800446 #define MURU_OFDMA_SCH_TYPE_UL BIT(1)
447
developeraace7f52022-06-24 13:40:42 +0800448 /* Common Config */
developer42b63282022-06-16 13:33:13 +0800449-#define MURU_COMM_PPDU_FMT BIT(0)
450-#define MURU_COMM_SCH_TYPE BIT(1)
451-#define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_SCH_TYPE)
developer42b63282022-06-16 13:33:13 +0800452-/* DL&UL User config*/
developer42b63282022-06-16 13:33:13 +0800453+/* #define MURU_COMM_PPDU_FMT BIT(0) */
454+/* #define MURU_COMM_SCH_TYPE BIT(1) */
455+/* #define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_SCH_TYPE) */
developeraace7f52022-06-24 13:40:42 +0800456+#define MURU_COMM_PPDU_FMT BIT(0)
457+#define MURU_COMM_SCH_TYPE BIT(1)
458+#define MURU_COMM_BAND BIT(2)
459+#define MURU_COMM_WMM BIT(3)
460+#define MURU_COMM_SPE_IDX BIT(4)
461+#define MURU_COMM_PROC_TYPE BIT(5)
462+#define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_BAND | \
463+ MURU_COMM_WMM | MURU_COMM_SPE_IDX)
developer42b63282022-06-16 13:33:13 +0800464+
465+/* DL&UL User config */
466 #define MURU_USER_CNT BIT(4)
467
468 enum {
469diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developer3262bf82022-07-12 11:37:54 +0800470index 6e140e2d..6d1dbdbd 100644
developer42b63282022-06-16 13:33:13 +0800471--- a/mt7915/mmio.c
472+++ b/mt7915/mmio.c
developeraace7f52022-06-24 13:40:42 +0800473@@ -76,6 +76,7 @@ static const u32 mt7915_offs[] = {
developer42b63282022-06-16 13:33:13 +0800474 [ARB_DRNGR0] = 0x194,
475 [ARB_SCR] = 0x080,
476 [RMAC_MIB_AIRTIME14] = 0x3b8,
477+ [AGG_AALCR0] = 0x048,
478 [AGG_AWSCR0] = 0x05c,
479 [AGG_PCR0] = 0x06c,
480 [AGG_ACR0] = 0x084,
developeraace7f52022-06-24 13:40:42 +0800481@@ -150,6 +151,7 @@ static const u32 mt7916_offs[] = {
developer42b63282022-06-16 13:33:13 +0800482 [ARB_DRNGR0] = 0x1e0,
483 [ARB_SCR] = 0x000,
484 [RMAC_MIB_AIRTIME14] = 0x0398,
485+ [AGG_AALCR0] = 0x028,
486 [AGG_AWSCR0] = 0x030,
487 [AGG_PCR0] = 0x040,
488 [AGG_ACR0] = 0x054,
489diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer3262bf82022-07-12 11:37:54 +0800490index 07a1c9ce..7c7d6bd3 100644
developer42b63282022-06-16 13:33:13 +0800491--- a/mt7915/mt7915.h
492+++ b/mt7915/mt7915.h
developeraace7f52022-06-24 13:40:42 +0800493@@ -303,6 +303,9 @@ struct mt7915_phy {
developer42b63282022-06-16 13:33:13 +0800494 u8 last_snr;
495
496 u8 spe_idx;
497+
498+ bool bf_en;
499+ bool bf_ever_en;
500 } test;
501 #endif
502
developeraace7f52022-06-24 13:40:42 +0800503@@ -394,6 +397,14 @@ struct mt7915_dev {
developer42b63282022-06-16 13:33:13 +0800504 void __iomem *dcm;
505 void __iomem *sku;
506
507+#ifdef CONFIG_NL80211_TESTMODE
508+ struct {
509+ void *txbf_phase_cal;
510+ void *txbf_pfmu_data;
511+ void *txbf_pfmu_tag;
512+ } test;
513+#endif
514+
515 #ifdef MTK_DEBUG
516 u16 wlan_idx;
517 struct {
developeraace7f52022-06-24 13:40:42 +0800518@@ -571,7 +582,7 @@ int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev,
developer42b63282022-06-16 13:33:13 +0800519 struct ieee80211_vif *vif,
520 struct ieee80211_sta *sta,
521 void *data, u32 field);
522-int mt7915_mcu_set_eeprom(struct mt7915_dev *dev);
523+int mt7915_mcu_set_eeprom(struct mt7915_dev *dev, bool flash_mode);
524 int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset);
525 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num);
526 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable,
developeraace7f52022-06-24 13:40:42 +0800527@@ -604,6 +615,7 @@ int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl);
developer42b63282022-06-16 13:33:13 +0800528 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);
529 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);
530 void mt7915_mcu_exit(struct mt7915_dev *dev);
531+int mt7915_tm_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb);
532
533 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
534 {
535diff --git a/mt7915/regs.h b/mt7915/regs.h
developer3262bf82022-07-12 11:37:54 +0800536index 47bae86e..444440e1 100644
developer42b63282022-06-16 13:33:13 +0800537--- a/mt7915/regs.h
538+++ b/mt7915/regs.h
developeraace7f52022-06-24 13:40:42 +0800539@@ -51,6 +51,7 @@ enum offs_rev {
developer42b63282022-06-16 13:33:13 +0800540 ARB_DRNGR0,
541 ARB_SCR,
542 RMAC_MIB_AIRTIME14,
543+ AGG_AALCR0,
544 AGG_AWSCR0,
545 AGG_PCR0,
546 AGG_ACR0,
developeraace7f52022-06-24 13:40:42 +0800547@@ -467,6 +468,8 @@ enum offs_rev {
developer42b63282022-06-16 13:33:13 +0800548 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
549 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
550
551+#define MT_AGG_AALCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AALCR0) + \
552+ (_n) * 4))
553 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \
554 (_n) * 4))
555 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \
556diff --git a/mt7915/testmode.c b/mt7915/testmode.c
developer3262bf82022-07-12 11:37:54 +0800557index 123ceaf9..a0a9f7be 100644
developer42b63282022-06-16 13:33:13 +0800558--- a/mt7915/testmode.c
559+++ b/mt7915/testmode.c
560@@ -9,6 +9,9 @@
561 enum {
562 TM_CHANGED_TXPOWER,
563 TM_CHANGED_FREQ_OFFSET,
564+ TM_CHANGED_AID,
565+ TM_CHANGED_CFG,
566+ TM_CHANGED_TXBF_ACT,
567
568 /* must be last */
569 NUM_TM_CHANGED
570@@ -17,6 +20,9 @@ enum {
571 static const u8 tm_change_map[] = {
572 [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER,
573 [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET,
574+ [TM_CHANGED_AID] = MT76_TM_ATTR_AID,
575+ [TM_CHANGED_CFG] = MT76_TM_ATTR_CFG,
576+ [TM_CHANGED_TXBF_ACT] = MT76_TM_ATTR_TXBF_ACT,
577 };
578
579 struct reg_band {
580@@ -33,6 +39,38 @@ struct reg_band {
581 #define TM_REG_MAX_ID 20
582 static struct reg_band reg_backup_list[TM_REG_MAX_ID];
583
584+static void mt7915_tm_update_entry(struct mt7915_phy *phy);
585+
586+static u8 mt7915_tm_chan_bw(enum nl80211_chan_width width)
587+{
588+ static const u8 width_to_bw[] = {
589+ [NL80211_CHAN_WIDTH_40] = TM_CBW_40MHZ,
590+ [NL80211_CHAN_WIDTH_80] = TM_CBW_80MHZ,
591+ [NL80211_CHAN_WIDTH_80P80] = TM_CBW_8080MHZ,
592+ [NL80211_CHAN_WIDTH_160] = TM_CBW_160MHZ,
593+ [NL80211_CHAN_WIDTH_5] = TM_CBW_5MHZ,
594+ [NL80211_CHAN_WIDTH_10] = TM_CBW_10MHZ,
595+ [NL80211_CHAN_WIDTH_20] = TM_CBW_20MHZ,
596+ [NL80211_CHAN_WIDTH_20_NOHT] = TM_CBW_20MHZ,
597+ };
598+
599+ if (width >= ARRAY_SIZE(width_to_bw))
600+ return 0;
601+
602+ return width_to_bw[width];
603+}
604+
605+static void
606+mt7915_tm_update_channel(struct mt7915_phy *phy)
607+{
608+ mutex_unlock(&phy->dev->mt76.mutex);
609+ mt7915_set_channel(phy);
610+ mutex_lock(&phy->dev->mt76.mutex);
611+
612+ mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH));
613+
614+ mt7915_tm_update_entry(phy);
615+}
616
617 static int
618 mt7915_tm_set_tx_power(struct mt7915_phy *phy)
619@@ -119,18 +157,28 @@ mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en)
620 }
621
622 static int
623-mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid)
624+mt7915_tm_clean_hwq(struct mt7915_phy *phy)
625 {
626+ struct mt76_testmode_entry_data *ed;
627+ struct mt76_wcid *wcid;
628 struct mt7915_dev *dev = phy->dev;
629 struct mt7915_tm_cmd req = {
630 .testmode_en = 1,
631 .param_idx = MCU_ATE_CLEAN_TXQUEUE,
632- .param.clean.wcid = wcid,
633 .param.clean.band = phy != &dev->phy,
634 };
635
636- return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
637- sizeof(req), false);
638+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
639+ int ret;
640+
641+ req.param.clean.wcid = wcid->idx;
642+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL),
643+ &req, sizeof(req), false);
644+ if (ret)
645+ return ret;
646+ }
647+
648+ return 0;
649 }
650
651 static int
developeraace7f52022-06-24 13:40:42 +0800652@@ -182,12 +230,738 @@ mt7915_tm_set_tam_arb(struct mt7915_phy *phy, bool enable, bool mu)
developer42b63282022-06-16 13:33:13 +0800653 return mt7915_mcu_set_muru_ctrl(dev, MURU_SET_ARB_OP_MODE, op_mode);
654 }
655
656+static int
657+mt7915_tm_set_cfg(struct mt7915_phy *phy)
658+{
659+ static const u8 cfg_cmd[] = {
660+ [MT76_TM_CFG_TSSI] = MCU_ATE_SET_TSSI,
661+ [MT76_TM_CFG_DPD] = MCU_ATE_SET_DPD,
662+ [MT76_TM_CFG_RATE_POWER_OFFSET] = MCU_ATE_SET_RATE_POWER_OFFSET,
663+ [MT76_TM_CFG_THERMAL_COMP] = MCU_ATE_SET_THERMAL_COMP,
664+ };
665+ struct mt76_testmode_data *td = &phy->mt76->test;
666+ struct mt7915_dev *dev = phy->dev;
667+ struct mt7915_tm_cmd req = {
668+ .testmode_en = !(phy->mt76->test.state == MT76_TM_STATE_OFF),
669+ .param_idx = cfg_cmd[td->cfg.type],
670+ .param.cfg.enable = td->cfg.enable,
671+ .param.cfg.band = phy->band_idx,
672+ };
673+
674+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
675+ sizeof(req), false);
676+}
677+
678+static int
679+mt7915_tm_add_txbf(struct mt7915_phy *phy, struct ieee80211_vif *vif,
680+ struct ieee80211_sta *sta, u8 pfmu_idx, u8 nr,
681+ u8 nc, bool ebf)
682+{
683+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
684+ struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
685+ struct mt7915_dev *dev = phy->dev;
686+ struct sk_buff *skb;
687+ struct sta_rec_bf *bf;
688+ struct tlv *tlv;
689+ u8 ndp_rate;
690+
691+ if (nr == 1)
692+ ndp_rate = 8;
693+ else if (nr == 2)
694+ ndp_rate = 16;
695+ else
696+ ndp_rate = 24;
697+
698+ skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
699+ &msta->wcid);
700+ if (IS_ERR(skb))
701+ return PTR_ERR(skb);
702+
703+ tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_BF, sizeof(*bf));
704+ bf = (struct sta_rec_bf *)tlv;
705+
706+ bf->pfmu = cpu_to_le16(pfmu_idx);
707+ bf->sounding_phy = 1;
708+ bf->bf_cap = ebf;
709+ bf->ncol = nc;
710+ bf->nrow = nr;
711+ bf->ndp_rate = ndp_rate;
712+ bf->ibf_timeout = 0xff;
713+ bf->tx_mode = MT_PHY_TYPE_HT;
714+
715+ if (ebf) {
716+ bf->mem[0].row = 0;
717+ bf->mem[1].row = 1;
718+ bf->mem[2].row = 2;
719+ bf->mem[3].row = 3;
720+ } else {
721+ bf->mem[0].row = 4;
722+ bf->mem[1].row = 5;
723+ bf->mem[2].row = 6;
724+ bf->mem[3].row = 7;
725+ }
726+
727+ return mt76_mcu_skb_send_msg(&dev->mt76, skb,
728+ MCU_EXT_CMD(STA_REC_UPDATE), true);
729+}
730+
731+static int
732+mt7915_tm_entry_add(struct mt7915_phy *phy, u8 aid)
733+{
734+ struct mt76_testmode_data *td = &phy->mt76->test;
735+ struct mt76_testmode_entry_data *ed;
736+ struct ieee80211_sband_iftype_data *sdata;
737+ struct ieee80211_supported_band *sband;
738+ struct ieee80211_sta *sta;
739+ struct mt7915_sta *msta;
740+ int tid, ret;
741+
742+ if (td->entry_num >= MT76_TM_MAX_ENTRY_NUM)
743+ return -EINVAL;
744+
745+ sta = kzalloc(sizeof(*sta) + phy->mt76->hw->sta_data_size +
746+ sizeof(*ed), GFP_KERNEL);
747+ if (!sta)
748+ return -ENOMEM;
749+
750+ msta = (struct mt7915_sta *)sta->drv_priv;
751+ ed = mt76_testmode_entry_data(phy->mt76, &msta->wcid);
752+ memcpy(ed, &td->ed, sizeof(*ed));
753+
754+ if (phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ) {
755+ sband = &phy->mt76->sband_5g.sband;
756+ sdata = phy->iftype[NL80211_BAND_5GHZ];
757+ } else if (phy->mt76->chandef.chan->band == NL80211_BAND_6GHZ) {
758+ sband = &phy->mt76->sband_6g.sband;
759+ sdata = phy->iftype[NL80211_BAND_6GHZ];
760+ } else {
761+ sband = &phy->mt76->sband_2g.sband;
762+ sdata = phy->iftype[NL80211_BAND_2GHZ];
763+ }
764+
765+ memcpy(sta->addr, ed->addr[0], ETH_ALEN);
766+ if (phy->test.bf_en) {
767+ u8 addr[ETH_ALEN] = {0x00, 0x11, 0x11, 0x11, 0x11, 0x11};
768+
769+ memcpy(sta->addr, addr, ETH_ALEN);
770+ }
771+
772+ if (td->tx_rate_mode >= MT76_TM_TX_MODE_HT)
773+ memcpy(&sta->ht_cap, &sband->ht_cap, sizeof(sta->ht_cap));
774+ if (td->tx_rate_mode >= MT76_TM_TX_MODE_VHT)
775+ memcpy(&sta->vht_cap, &sband->vht_cap, sizeof(sta->vht_cap));
776+ if (td->tx_rate_mode >= MT76_TM_TX_MODE_HE_SU)
777+ memcpy(&sta->he_cap, &sdata[NL80211_IFTYPE_STATION].he_cap,
778+ sizeof(sta->he_cap));
779+ sta->aid = aid;
780+ sta->wme = 1;
781+
782+ ret = mt7915_mac_sta_add(&phy->dev->mt76, phy->monitor_vif, sta);
783+ if (ret) {
784+ kfree(sta);
785+ return ret;
786+ }
787+
788+ /* prevent from starting tx ba session */
789+ for (tid = 0; tid < 8; tid++)
790+ set_bit(tid, &msta->ampdu_state);
791+
792+ list_add_tail(&msta->wcid.list, &td->tm_entry_list);
793+ td->entry_num++;
794+
795+ return 0;
796+}
797+
798+static void
799+mt7915_tm_entry_remove(struct mt7915_phy *phy, u8 aid)
800+{
801+ struct mt76_testmode_data *td = &phy->mt76->test;
802+ struct mt76_wcid *wcid, *tmp;
803+
804+ if (list_empty(&td->tm_entry_list))
805+ return;
806+
807+ list_for_each_entry_safe(wcid, tmp, &td->tm_entry_list, list) {
808+ struct mt76_testmode_entry_data *ed;
809+ struct mt7915_dev *dev = phy->dev;
810+ struct ieee80211_sta *sta;
811+
812+ ed = mt76_testmode_entry_data(phy->mt76, wcid);
813+ if (aid && ed->aid != aid)
814+ continue;
815+
816+ sta = wcid_to_sta(wcid);
817+ mt7915_mac_sta_remove(&dev->mt76, phy->monitor_vif, sta);
818+ mt76_wcid_mask_clear(dev->mt76.wcid_mask, wcid->idx);
819+
820+ list_del_init(&wcid->list);
821+ kfree(sta);
822+ phy->mt76->test.entry_num--;
823+ }
824+}
825+
826+static int
827+mt7915_tm_set_entry(struct mt7915_phy *phy)
828+{
829+ struct mt76_testmode_data *td = &phy->mt76->test;
830+ struct mt76_testmode_entry_data *ed;
831+ struct mt76_wcid *wcid;
832+
833+ if (!td->aid) {
834+ if (td->state > MT76_TM_STATE_IDLE)
835+ mt76_testmode_set_state(phy->mt76, MT76_TM_STATE_IDLE);
836+ mt7915_tm_entry_remove(phy, td->aid);
837+ return 0;
838+ }
839+
840+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
841+ if (ed->aid == td->aid) {
842+ struct sk_buff *skb;
843+
844+ local_bh_disable();
845+ skb = ed->tx_skb;
846+ memcpy(ed, &td->ed, sizeof(*ed));
847+ ed->tx_skb = skb;
848+ local_bh_enable();
849+
850+ return 0;
851+ }
852+ }
853+
854+ return mt7915_tm_entry_add(phy, td->aid);
855+}
856+
857+static void
858+mt7915_tm_update_entry(struct mt7915_phy *phy)
859+{
860+ struct mt76_testmode_data *td = &phy->mt76->test;
861+ struct mt76_testmode_entry_data *ed, tmp;
862+ struct mt76_wcid *wcid, *last;
863+
864+ if (!td->aid || phy->test.bf_en)
865+ return;
866+
867+ memcpy(&tmp, &td->ed, sizeof(tmp));
868+ last = list_last_entry(&td->tm_entry_list,
869+ struct mt76_wcid, list);
870+
871+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
872+ memcpy(&td->ed, ed, sizeof(td->ed));
873+ mt7915_tm_entry_remove(phy, td->aid);
874+ mt7915_tm_entry_add(phy, td->aid);
875+ if (wcid == last)
876+ break;
877+ }
878+
879+ memcpy(&td->ed, &tmp, sizeof(td->ed));
880+}
881+
882+static int
883+mt7915_tm_txbf_init(struct mt7915_phy *phy, u16 *val)
884+{
885+ struct mt76_testmode_data *td = &phy->mt76->test;
886+ struct mt7915_dev *dev = phy->dev;
887+ bool enable = val[0];
888+ void *phase_cal, *pfmu_data, *pfmu_tag;
889+ u8 addr[ETH_ALEN] = {0x00, 0x22, 0x22, 0x22, 0x22, 0x22};
890+
891+ if (!enable) {
892+ phy->test.bf_en = 0;
893+ return 0;
894+ }
895+
896+ if (!dev->test.txbf_phase_cal) {
897+ phase_cal = devm_kzalloc(dev->mt76.dev,
898+ sizeof(struct mt7915_tm_txbf_phase) *
899+ MAX_PHASE_GROUP_NUM,
900+ GFP_KERNEL);
901+ if (!phase_cal)
902+ return -ENOMEM;
903+
904+ dev->test.txbf_phase_cal = phase_cal;
905+ }
906+
907+ if (!dev->test.txbf_pfmu_data) {
908+ pfmu_data = devm_kzalloc(dev->mt76.dev, 512, GFP_KERNEL);
909+ if (!pfmu_data)
910+ return -ENOMEM;
911+
912+ dev->test.txbf_pfmu_data = pfmu_data;
913+ }
914+
915+ if (!dev->test.txbf_pfmu_tag) {
916+ pfmu_tag = devm_kzalloc(dev->mt76.dev,
917+ sizeof(struct mt7915_tm_pfmu_tag), GFP_KERNEL);
918+ if (!pfmu_tag)
919+ return -ENOMEM;
920+
921+ dev->test.txbf_pfmu_tag = pfmu_tag;
922+ }
923+
924+ memcpy(phy->monitor_vif->addr, addr, ETH_ALEN);
925+ mt7915_mcu_add_dev_info(phy, phy->monitor_vif, true);
926+
927+ td->tx_rate_mode = MT76_TM_TX_MODE_HT;
928+ td->tx_mpdu_len = 1024;
929+ td->tx_rate_sgi = 0;
930+ td->tx_ipg = 100;
931+ phy->test.bf_en = 1;
932+
933+ return mt7915_tm_set_trx(phy, TM_MAC_TX, true);
934+}
935+
936+static int
937+mt7915_tm_txbf_phase_comp(struct mt7915_phy *phy, u16 *val)
938+{
939+ struct mt7915_dev *dev = phy->dev;
940+ struct {
941+ u8 category;
942+ u8 wlan_idx_lo;
943+ u8 bw;
944+ u8 jp_band;
945+ u8 dbdc_idx;
946+ bool read_from_e2p;
947+ bool disable;
948+ u8 wlan_idx_hi;
949+ u8 buf[40];
950+ } __packed req = {
951+ .category = MT_BF_IBF_PHASE_COMP,
952+ .bw = val[0],
953+ .jp_band = (val[2] == 1) ? 1 : 0,
954+ .dbdc_idx = phy->band_idx,
955+ .read_from_e2p = val[3],
956+ .disable = val[4],
957+ };
958+ struct mt7915_tm_txbf_phase *phase =
959+ (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
960+
961+ wait_event_timeout(dev->mt76.tx_wait, phase[val[2]].status != 0, HZ);
962+ memcpy(req.buf, &phase[val[2]].phase, sizeof(req.buf));
963+
964+ pr_info("ibf cal process: phase comp info\n");
965+ print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1,
966+ &req, sizeof(req), 0);
967+
968+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
969+ sizeof(req), true);
970+}
971+
972+static int
973+mt7915_tm_txbf_profile_tag_read(struct mt7915_phy *phy, u8 pfmu_idx)
974+{
975+ struct mt7915_dev *dev = phy->dev;
976+ struct {
977+ u8 format_id;
978+ u8 pfmu_idx;
979+ bool bfer;
980+ u8 dbdc_idx;
981+ } __packed req = {
982+ .format_id = MT_BF_PFMU_TAG_READ,
983+ .pfmu_idx = pfmu_idx,
984+ .bfer = 1,
985+ .dbdc_idx = phy != &dev->phy,
986+ };
987+ struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
988+
989+ tag->t1.pfmu_idx = 0;
990+
991+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
992+ sizeof(req), true);
993+}
994+
995+static int
996+mt7915_tm_txbf_profile_tag_write(struct mt7915_phy *phy, u8 pfmu_idx,
997+ struct mt7915_tm_pfmu_tag *tag)
998+{
999+ struct mt7915_dev *dev = phy->dev;
1000+ struct {
1001+ u8 format_id;
1002+ u8 pfmu_idx;
1003+ bool bfer;
1004+ u8 dbdc_idx;
1005+ u8 buf[64];
1006+ } __packed req = {
1007+ .format_id = MT_BF_PFMU_TAG_WRITE,
1008+ .pfmu_idx = pfmu_idx,
1009+ .bfer = 1,
1010+ .dbdc_idx = phy != &dev->phy,
1011+ };
1012+
1013+ memcpy(req.buf, tag, sizeof(*tag));
1014+ wait_event_timeout(dev->mt76.tx_wait, tag->t1.pfmu_idx != 0, HZ);
1015+
1016+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1017+ sizeof(req), false);
1018+}
1019+
1020+static int
1021+mt7915_tm_txbf_apply_tx(struct mt7915_phy *phy, u16 wlan_idx, bool ebf,
1022+ bool ibf, bool phase_cal)
1023+{
1024+#define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1025+#define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
1026+ struct mt7915_dev *dev = phy->dev;
1027+ struct {
1028+ u8 category;
1029+ u8 wlan_idx_lo;
1030+ bool ebf;
1031+ bool ibf;
1032+ bool mu_txbf;
1033+ bool phase_cal;
1034+ u8 wlan_idx_hi;
1035+ u8 _rsv;
1036+ } __packed req = {
1037+ .category = MT_BF_DATA_PACKET_APPLY,
1038+ .wlan_idx_lo = to_wcid_lo(wlan_idx),
1039+ .ebf = ebf,
1040+ .ibf = ibf,
1041+ .phase_cal = phase_cal,
1042+ .wlan_idx_hi = to_wcid_hi(wlan_idx),
1043+ };
1044+
1045+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1046+ sizeof(req), false);
1047+}
1048+
1049+static int mt7915_tm_txbf_set_rate(struct mt7915_phy *phy,
1050+ struct mt76_wcid *wcid)
1051+{
1052+ struct mt7915_dev *dev = phy->dev;
1053+ struct mt76_testmode_entry_data *ed = mt76_testmode_entry_data(phy->mt76, wcid);
1054+ struct ieee80211_sta *sta = wcid_to_sta(wcid);
1055+ struct sta_phy rate = {};
1056+
1057+ if (!sta)
1058+ return 0;
1059+
1060+ rate.type = MT_PHY_TYPE_HT;
1061+ rate.bw = mt7915_tm_chan_bw(phy->mt76->chandef.width);
1062+ rate.nss = ed->tx_rate_nss;
1063+ rate.mcs = ed->tx_rate_idx;
1064+ rate.ldpc = (rate.bw || ed->tx_rate_ldpc) * GENMASK(2, 0);
1065+
1066+ return mt7915_mcu_set_fixed_rate_ctrl(dev, phy->monitor_vif, sta,
1067+ &rate, RATE_PARAM_FIXED);
1068+}
1069+
1070+static int
1071+mt7915_tm_txbf_set_tx(struct mt7915_phy *phy, u16 *val)
1072+{
1073+ bool bf_on = val[0], update = val[3];
1074+ /* u16 wlan_idx = val[2]; */
1075+ struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1076+ struct mt76_testmode_data *td = &phy->mt76->test;
1077+ struct mt76_wcid *wcid;
1078+
1079+ if (bf_on) {
1080+ mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1081+ mt7915_tm_txbf_profile_tag_read(phy, 2);
1082+ tag->t1.invalid_prof = false;
1083+ mt7915_tm_txbf_profile_tag_write(phy, 2, tag);
1084+
1085+ phy->test.bf_ever_en = true;
1086+
1087+ if (update)
1088+ mt7915_tm_txbf_apply_tx(phy, 1, 0, 1, 1);
1089+ } else {
1090+ if (!phy->test.bf_ever_en) {
1091+ if (update)
1092+ mt7915_tm_txbf_apply_tx(phy, 1, 0, 0, 0);
1093+ } else {
1094+ phy->test.bf_ever_en = false;
1095+
1096+ mt7915_tm_txbf_profile_tag_read(phy, 2);
1097+ tag->t1.invalid_prof = true;
1098+ mt7915_tm_txbf_profile_tag_write(phy, 2, tag);
1099+ }
1100+ }
1101+
1102+ wcid = list_first_entry(&td->tm_entry_list, struct mt76_wcid, list);
1103+ mt7915_tm_txbf_set_rate(phy, wcid);
1104+
1105+ return 0;
1106+}
1107+
1108+static int
1109+mt7915_tm_txbf_profile_update(struct mt7915_phy *phy, u16 *val, bool ebf)
1110+{
1111+ static const u8 mode_to_lm[] = {
1112+ [MT76_TM_TX_MODE_CCK] = 0,
1113+ [MT76_TM_TX_MODE_OFDM] = 0,
1114+ [MT76_TM_TX_MODE_HT] = 1,
1115+ [MT76_TM_TX_MODE_VHT] = 2,
1116+ [MT76_TM_TX_MODE_HE_SU] = 3,
1117+ [MT76_TM_TX_MODE_HE_EXT_SU] = 3,
1118+ [MT76_TM_TX_MODE_HE_TB] = 3,
1119+ [MT76_TM_TX_MODE_HE_MU] = 3,
1120+ };
1121+ struct mt76_testmode_data *td = &phy->mt76->test;
1122+ struct mt76_wcid *wcid;
1123+ struct ieee80211_vif *vif = phy->monitor_vif;
1124+ struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1125+ u8 pfmu_idx = val[0], nc = val[2], nr;
1126+ int ret;
1127+
1128+ if (td->tx_antenna_mask == 3)
1129+ nr = 1;
1130+ else if (td->tx_antenna_mask == 7)
1131+ nr = 2;
1132+ else
1133+ nr = 3;
1134+
1135+ memset(tag, 0, sizeof(*tag));
1136+ tag->t1.pfmu_idx = pfmu_idx;
1137+ tag->t1.ebf = ebf;
1138+ tag->t1.nr = nr;
1139+ tag->t1.nc = nc;
1140+ tag->t1.invalid_prof = true;
1141+
1142+ tag->t1.snr_sts4 = 0xc0;
1143+ tag->t1.snr_sts5 = 0xff;
1144+ tag->t1.snr_sts6 = 0xff;
1145+ tag->t1.snr_sts7 = 0xff;
1146+
1147+ if (ebf) {
1148+ tag->t1.row_id1 = 0;
1149+ tag->t1.row_id2 = 1;
1150+ tag->t1.row_id3 = 2;
1151+ tag->t1.row_id4 = 3;
1152+ tag->t1.lm = mode_to_lm[MT76_TM_TX_MODE_HT];
1153+ } else {
1154+ tag->t1.row_id1 = 4;
1155+ tag->t1.row_id2 = 5;
1156+ tag->t1.row_id3 = 6;
1157+ tag->t1.row_id4 = 7;
1158+ tag->t1.lm = mode_to_lm[MT76_TM_TX_MODE_OFDM];
1159+
1160+ tag->t2.ibf_timeout = 0xff;
1161+ tag->t2.ibf_nr = nr;
1162+ }
1163+
1164+ ret = mt7915_tm_txbf_profile_tag_write(phy, pfmu_idx, tag);
1165+ if (ret)
1166+ return ret;
1167+
1168+ wcid = list_first_entry(&td->tm_entry_list, struct mt76_wcid, list);
1169+ ret = mt7915_tm_add_txbf(phy, vif, wcid_to_sta(wcid), pfmu_idx, nr, nc, ebf);
1170+ if (ret)
1171+ return ret;
1172+
1173+ if (!ebf)
1174+ return mt7915_tm_txbf_apply_tx(phy, 1, false, true, true);
1175+
1176+ return 0;
1177+}
1178+
1179+static int
1180+mt7915_tm_txbf_phase_cal(struct mt7915_phy *phy, u16 *val)
1181+{
1182+#define GROUP_L 0
1183+#define GROUP_M 1
1184+#define GROUP_H 2
1185+ struct mt7915_dev *dev = phy->dev;
1186+ struct {
1187+ u8 category;
1188+ u8 group_l_m_n;
1189+ u8 group;
1190+ bool sx2;
1191+ u8 cal_type;
1192+ u8 lna_gain_level;
1193+ u8 _rsv[2];
1194+ } __packed req = {
1195+ .category = MT_BF_PHASE_CAL,
1196+ .group = val[0],
1197+ .group_l_m_n = val[1],
1198+ .sx2 = val[2],
1199+ .cal_type = val[3],
1200+ .lna_gain_level = 0, /* for test purpose */
1201+ };
1202+ struct mt7915_tm_txbf_phase *phase =
1203+ (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1204+
1205+ phase[req.group].status = 0;
1206+
1207+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1208+ sizeof(req), true);
1209+}
1210+
1211+int mt7915_tm_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb)
1212+{
1213+#define BF_PFMU_TAG 16
1214+#define BF_CAL_PHASE 21
1215+ u8 format_id;
1216+
developeraace7f52022-06-24 13:40:42 +08001217+ skb_pull(skb, sizeof(struct mt76_connac2_mcu_rxd));
developer42b63282022-06-16 13:33:13 +08001218+ format_id = *(u8 *)skb->data;
1219+
1220+ if (format_id == BF_PFMU_TAG) {
1221+ struct mt7915_tm_pfmu_tag *tag = dev->test.txbf_pfmu_tag;
1222+
1223+ skb_pull(skb, 8);
1224+ memcpy(tag, skb->data, sizeof(struct mt7915_tm_pfmu_tag));
1225+ } else if (format_id == BF_CAL_PHASE) {
1226+ struct mt7915_tm_ibf_cal_info *cal;
1227+ struct mt7915_tm_txbf_phase *phase =
1228+ (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1229+
1230+ cal = (struct mt7915_tm_ibf_cal_info *)skb->data;
1231+ switch (cal->cal_type) {
1232+ case IBF_PHASE_CAL_NORMAL:
1233+ case IBF_PHASE_CAL_NORMAL_INSTRUMENT:
1234+ if (cal->group_l_m_n != GROUP_M)
1235+ break;
1236+ phase = &phase[cal->group];
1237+ memcpy(&phase->phase, cal->buf + 16, sizeof(phase->phase));
1238+ phase->status = cal->status;
1239+ break;
1240+ case IBF_PHASE_CAL_VERIFY:
1241+ case IBF_PHASE_CAL_VERIFY_INSTRUMENT:
1242+ break;
1243+ default:
1244+ break;
1245+ }
1246+ }
1247+
1248+ wake_up(&dev->mt76.tx_wait);
1249+
1250+ return 0;
1251+}
1252+
1253+static int
1254+mt7915_tm_txbf_profile_update_all(struct mt7915_phy *phy, u16 *val)
1255+{
1256+ struct mt76_testmode_data *td = &phy->mt76->test;
1257+ u16 pfmu_idx = val[0];
1258+ u16 subc_id = val[1];
1259+ u16 angle11 = val[2];
1260+ u16 angle21 = val[3];
1261+ u16 angle31 = val[4];
1262+ u16 angle41 = val[5];
1263+ s16 phi11 = 0, phi21 = 0, phi31 = 0;
1264+ struct mt7915_tm_pfmu_data *pfmu_data;
1265+
1266+ if (subc_id > 63)
1267+ return -EINVAL;
1268+
1269+ if (td->tx_antenna_mask == 2) {
1270+ phi11 = (s16)(angle21 - angle11);
1271+ } else if (td->tx_antenna_mask == 3) {
1272+ phi11 = (s16)(angle31 - angle11);
1273+ phi21 = (s16)(angle31 - angle21);
1274+ } else {
1275+ phi11 = (s16)(angle41 - angle11);
1276+ phi21 = (s16)(angle41 - angle21);
1277+ phi31 = (s16)(angle41 - angle31);
1278+ }
1279+
1280+ pfmu_data = (struct mt7915_tm_pfmu_data *)phy->dev->test.txbf_pfmu_data;
1281+ pfmu_data = &pfmu_data[subc_id];
1282+
1283+ if (subc_id < 32)
1284+ pfmu_data->subc_idx = cpu_to_le16(subc_id + 224);
1285+ else
1286+ pfmu_data->subc_idx = cpu_to_le16(subc_id - 32);
1287+ pfmu_data->phi11 = cpu_to_le16(phi11);
1288+ pfmu_data->phi21 = cpu_to_le16(phi21);
1289+ pfmu_data->phi31 = cpu_to_le16(phi31);
1290+
1291+ if (subc_id == 63) {
1292+ struct mt7915_dev *dev = phy->dev;
1293+ struct {
1294+ u8 format_id;
1295+ u8 pfmu_idx;
1296+ u8 dbdc_idx;
1297+ u8 _rsv;
1298+ u8 buf[512];
1299+ } __packed req = {
1300+ .format_id = MT_BF_PROFILE_WRITE_ALL,
1301+ .pfmu_idx = pfmu_idx,
1302+ .dbdc_idx = phy != &dev->phy,
1303+ };
1304+
1305+ memcpy(req.buf, dev->test.txbf_pfmu_data, 512);
1306+
1307+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION),
1308+ &req, sizeof(req), true);
1309+ }
1310+
1311+ return 0;
1312+}
1313+
1314+static int
1315+mt7915_tm_txbf_e2p_update(struct mt7915_phy *phy)
1316+{
1317+ struct mt7915_tm_txbf_phase *phase, *p;
1318+ struct mt7915_dev *dev = phy->dev;
1319+ u8 *eeprom = dev->mt76.eeprom.data;
1320+ u16 offset;
1321+ bool is_7976;
1322+ int i;
1323+
1324+ is_7976 = mt7915_check_adie(dev, false) || is_mt7916(&dev->mt76);
1325+ offset = is_7976 ? 0x60a : 0x651;
1326+
1327+ phase = (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1328+ for (i = 0; i < MAX_PHASE_GROUP_NUM; i++) {
1329+ p = &phase[i];
1330+
1331+ if (!p->status)
1332+ continue;
1333+
1334+ /* copy phase cal data to eeprom */
1335+ memcpy(eeprom + offset + i * sizeof(p->phase), &p->phase,
1336+ sizeof(p->phase));
1337+ }
1338+
1339+ return 0;
1340+}
1341+
1342+static int
1343+mt7915_tm_set_txbf(struct mt7915_phy *phy)
1344+{
1345+ struct mt76_testmode_data *td = &phy->mt76->test;
1346+ u16 *val = td->txbf_param;
1347+
1348+ pr_info("ibf cal process: act = %u, val = %u, %u, %u, %u, %u\n",
1349+ td->txbf_act, val[0], val[1], val[2], val[3], val[4]);
1350+
1351+ switch (td->txbf_act) {
1352+ case MT76_TM_TXBF_ACT_INIT:
1353+ return mt7915_tm_txbf_init(phy, val);
1354+ case MT76_TM_TXBF_ACT_UPDATE_CH:
1355+ mt7915_tm_update_channel(phy);
1356+ break;
1357+ case MT76_TM_TXBF_ACT_PHASE_COMP:
1358+ return mt7915_tm_txbf_phase_comp(phy, val);
1359+ case MT76_TM_TXBF_ACT_TX_PREP:
1360+ return mt7915_tm_txbf_set_tx(phy, val);
1361+ case MT76_TM_TXBF_ACT_IBF_PROF_UPDATE:
1362+ return mt7915_tm_txbf_profile_update(phy, val, false);
1363+ case MT76_TM_TXBF_ACT_EBF_PROF_UPDATE:
1364+ return mt7915_tm_txbf_profile_update(phy, val, true);
1365+ case MT76_TM_TXBF_ACT_PHASE_CAL:
1366+ return mt7915_tm_txbf_phase_cal(phy, val);
1367+ case MT76_TM_TXBF_ACT_PROF_UPDATE_ALL:
1368+ return mt7915_tm_txbf_profile_update_all(phy, val);
1369+ case MT76_TM_TXBF_ACT_E2P_UPDATE:
1370+ return mt7915_tm_txbf_e2p_update(phy);
1371+ default:
1372+ break;
1373+ };
1374+
1375+ return 0;
1376+}
1377+
1378 static int
developeraace7f52022-06-24 13:40:42 +08001379 mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min,
developer42b63282022-06-16 13:33:13 +08001380- u16 cw_max, u16 txop)
1381+ u16 cw_max, u16 txop, u8 tx_cmd)
1382 {
developeraace7f52022-06-24 13:40:42 +08001383 struct mt7915_vif *mvif = (struct mt7915_vif *)phy->monitor_vif->drv_priv;
developer42b63282022-06-16 13:33:13 +08001384- struct mt7915_mcu_tx req = { .total = 1 };
1385+ struct mt7915_mcu_tx req = {
1386+ .valid = true,
1387+ .mode = tx_cmd,
1388+ .total = 1,
1389+ };
1390 struct edca *e = &req.edca[0];
1391
developeraace7f52022-06-24 13:40:42 +08001392 e->queue = qid + mvif->mt76.wmm_idx * MT76_CONNAC_MAX_WMM_SETS;
1393@@ -262,7 +1036,8 @@ done:
developer42b63282022-06-16 13:33:13 +08001394
developeraace7f52022-06-24 13:40:42 +08001395 return mt7915_tm_set_wmm_qid(phy,
developer42b63282022-06-16 13:33:13 +08001396 mt76_connac_lmac_mapping(IEEE80211_AC_BE),
1397- aifsn, cw, cw, 0);
1398+ aifsn, cw, cw, 0,
1399+ mode == MT76_TM_TX_MODE_HE_MU);
1400 }
1401
1402 static int
developeraace7f52022-06-24 13:40:42 +08001403@@ -338,7 +1113,7 @@ mt7915_tm_set_tx_len(struct mt7915_phy *phy, u32 tx_time)
developer42b63282022-06-16 13:33:13 +08001404 bitrate = cfg80211_calculate_bitrate(&rate);
1405 tx_len = bitrate * tx_time / 10 / 8;
1406
1407- ret = mt76_testmode_alloc_skb(phy->mt76, tx_len);
1408+ ret = mt76_testmode_init_skb(phy->mt76, tx_len, &td->tx_skb, td->addr);
1409 if (ret)
1410 return ret;
1411
developeraace7f52022-06-24 13:40:42 +08001412@@ -456,18 +1231,180 @@ mt7915_tm_init(struct mt7915_phy *phy, bool en)
developer42b63282022-06-16 13:33:13 +08001413
1414 phy->mt76->test.flag |= MT_TM_FW_RX_COUNT;
1415
1416- if (!en)
1417+ if (!en) {
1418 mt7915_tm_set_tam_arb(phy, en, 0);
1419+
1420+ phy->mt76->test.aid = 0;
1421+ phy->mt76->test.tx_mpdu_len = 0;
1422+ phy->test.bf_en = 0;
1423+ mt7915_tm_set_entry(phy);
1424+ }
1425+}
1426+
1427+static bool
1428+mt7915_tm_check_skb(struct mt7915_phy *phy)
1429+{
1430+ struct mt76_testmode_entry_data *ed;
1431+ struct mt76_wcid *wcid;
1432+
1433+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
1434+ struct ieee80211_tx_info *info;
1435+
1436+ if (!ed->tx_skb)
1437+ return false;
1438+
1439+ info = IEEE80211_SKB_CB(ed->tx_skb);
1440+ info->control.vif = phy->monitor_vif;
1441+ }
1442+
1443+ return true;
1444+}
1445+
1446+static int
1447+mt7915_tm_set_ba(struct mt7915_phy *phy)
1448+{
1449+ struct mt7915_dev *dev = phy->dev;
1450+ struct mt76_testmode_data *td = &phy->mt76->test;
1451+ struct mt76_wcid *wcid;
1452+ struct ieee80211_vif *vif = phy->monitor_vif;
1453+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1454+ struct ieee80211_ampdu_params params = { .buf_size = 256 };
1455+
1456+ list_for_each_entry(wcid, &td->tm_entry_list, list) {
1457+ int tid, ret;
1458+
1459+ params.sta = wcid_to_sta(wcid);
1460+ for (tid = 0; tid < 8; tid++) {
1461+ params.tid = tid;
1462+ ret = mt7915_mcu_add_tx_ba(phy->dev, &params, true);
1463+ if (ret)
1464+ return ret;
1465+ }
1466+ }
1467+
1468+ mt76_wr(dev, MT_AGG_AALCR0(mvif->mt76.band_idx, mvif->mt76.wmm_idx),
1469+ 0x01010101);
1470+
1471+ return 0;
1472+}
1473+
1474+static int
1475+mt7915_tm_set_muru_cfg(struct mt7915_phy *phy, struct mt7915_tm_muru *muru)
1476+{
1477+/* #define MURU_SET_MANUAL_CFG 100 */
1478+ struct mt7915_dev *dev = phy->dev;
1479+ struct {
1480+ __le32 cmd;
1481+ struct mt7915_tm_muru muru;
1482+ } __packed req = {
1483+ .cmd = cpu_to_le32(MURU_SET_MANUAL_CFG),
1484+ };
1485+
1486+ memcpy(&req.muru, muru, sizeof(struct mt7915_tm_muru));
1487+
1488+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
1489+ sizeof(req), false);
1490+}
1491+
1492+static int
1493+mt7915_tm_set_muru_dl(struct mt7915_phy *phy)
1494+{
1495+ struct mt76_testmode_data *td = &phy->mt76->test;
1496+ struct mt76_testmode_entry_data *ed;
1497+ struct mt76_wcid *wcid;
1498+ struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1499+ struct ieee80211_vif *vif = phy->monitor_vif;
1500+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1501+ struct mt7915_tm_muru muru = {};
1502+ struct mt7915_tm_muru_comm *comm = &muru.comm;
1503+ struct mt7915_tm_muru_dl *dl = &muru.dl;
1504+ int i;
1505+
1506+ comm->ppdu_format = MURU_PPDU_HE_MU;
1507+ comm->band = mvif->mt76.band_idx;
1508+ comm->wmm_idx = mvif->mt76.wmm_idx;
1509+ comm->spe_idx = phy->test.spe_idx;
1510+
1511+ dl->bw = mt7915_tm_chan_bw(chandef->width);
1512+ dl->gi = td->tx_rate_sgi;;
1513+ dl->ltf = td->tx_ltf;
1514+ dl->tx_mode = MT_PHY_TYPE_HE_MU;
1515+
1516+ for (i = 0; i < sizeof(dl->ru); i++)
1517+ dl->ru[i] = 0x71;
1518+
1519+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
1520+ struct mt7915_tm_muru_dl_usr *dl_usr = &dl->usr[dl->user_num];
1521+
1522+ dl_usr->wlan_idx = cpu_to_le16(wcid->idx);
1523+ dl_usr->ru_alloc_seg = ed->aid < 8 ? 0 : 1;
1524+ dl_usr->ru_idx = ed->ru_idx;
1525+ dl_usr->mcs = ed->tx_rate_idx;
1526+ dl_usr->nss = ed->tx_rate_nss - 1;
1527+ dl_usr->ldpc = ed->tx_rate_ldpc;
1528+ dl->ru[dl->user_num] = ed->ru_alloc;
1529+
1530+ dl->user_num++;
1531+ }
1532+
1533+ muru.cfg_comm = cpu_to_le32(MURU_COMM_SET);
1534+ muru.cfg_dl = cpu_to_le32(MURU_DL_SET);
1535+
1536+ return mt7915_tm_set_muru_cfg(phy, &muru);
1537+}
1538+
1539+static int
1540+mt7915_tm_set_muru_pkt_cnt(struct mt7915_phy *phy, bool enable, u32 tx_count)
1541+{
1542+#define MURU_SET_TX_PKT_CNT 105
1543+#define MURU_SET_TX_EN 106
1544+ struct mt7915_dev *dev = phy->dev;
1545+ struct {
1546+ __le32 cmd;
1547+ u8 band;
1548+ u8 enable;
1549+ u8 _rsv[2];
1550+ __le32 tx_count;
1551+ } __packed req = {
1552+ .band = phy != &dev->phy,
1553+ .enable = enable,
1554+ .tx_count = enable ? cpu_to_le32(tx_count) : 0,
1555+ };
1556+ int ret;
1557+
1558+ req.cmd = enable ? cpu_to_le32(MURU_SET_TX_PKT_CNT) :
1559+ cpu_to_le32(MURU_SET_TX_EN);
1560+
1561+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
1562+ sizeof(req), false);
1563+ if (ret)
1564+ return ret;
1565+
1566+ req.cmd = enable ? cpu_to_le32(MURU_SET_TX_EN) :
1567+ cpu_to_le32(MURU_SET_TX_PKT_CNT);
1568+
1569+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
1570+ sizeof(req), false);
1571 }
1572
1573 static void
1574-mt7915_tm_update_channel(struct mt7915_phy *phy)
1575+mt7915_tm_tx_frames_mu(struct mt7915_phy *phy, bool enable)
1576 {
1577- mutex_unlock(&phy->dev->mt76.mutex);
1578- mt7915_set_channel(phy);
1579- mutex_lock(&phy->dev->mt76.mutex);
1580+ struct mt76_testmode_data *td = &phy->mt76->test;
1581
1582- mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH));
1583+ if (enable) {
1584+ struct mt7915_dev *dev = phy->dev;
1585+
1586+ mt7915_tm_set_ba(phy);
1587+ mt7915_tm_set_muru_dl(phy);
1588+ mt76_rr(dev, MT_MIB_DR8(phy != &dev->phy));
1589+ } else {
1590+ /* set to zero for counting real tx free num */
1591+ td->tx_done = 0;
1592+ }
1593+
1594+ mt7915_tm_set_muru_pkt_cnt(phy, enable, td->tx_count);
1595+ usleep_range(100000, 200000);
1596 }
1597
1598 static void
developeraace7f52022-06-24 13:40:42 +08001599@@ -476,47 +1413,48 @@ mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
developer42b63282022-06-16 13:33:13 +08001600 static const u8 spe_idx_map[] = {0, 0, 1, 0, 3, 2, 4, 0,
1601 9, 8, 6, 10, 16, 12, 18, 0};
1602 struct mt76_testmode_data *td = &phy->mt76->test;
1603- struct mt7915_dev *dev = phy->dev;
1604- struct ieee80211_tx_info *info;
1605- u8 duty_cycle = td->tx_duty_cycle;
1606- u32 tx_time = td->tx_time;
1607- u32 ipg = td->tx_ipg;
1608
1609 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1610- mt7915_tm_clean_hwq(phy, dev->mt76.global_wcid.idx);
1611+ mt7915_tm_set_trx(phy, TM_MAC_TX, false);
1612
1613 if (en) {
1614- mt7915_tm_update_channel(phy);
1615+ u32 tx_time = td->tx_time, ipg = td->tx_ipg;
1616+ u8 duty_cycle = td->tx_duty_cycle;
1617+
1618+ if (!phy->test.bf_en)
1619+ mt7915_tm_update_channel(phy);
1620
1621 if (td->tx_spe_idx) {
1622 phy->test.spe_idx = td->tx_spe_idx;
1623 } else {
1624 phy->test.spe_idx = spe_idx_map[td->tx_antenna_mask];
1625 }
1626- }
1627
1628- mt7915_tm_set_tam_arb(phy, en,
1629- td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU);
1630+ /* if all three params are set, duty_cycle will be ignored */
1631+ if (duty_cycle && tx_time && !ipg) {
1632+ ipg = tx_time * 100 / duty_cycle - tx_time;
1633+ } else if (duty_cycle && !tx_time && ipg) {
1634+ if (duty_cycle < 100)
1635+ tx_time = duty_cycle * ipg / (100 - duty_cycle);
1636+ }
1637
1638- /* if all three params are set, duty_cycle will be ignored */
1639- if (duty_cycle && tx_time && !ipg) {
1640- ipg = tx_time * 100 / duty_cycle - tx_time;
1641- } else if (duty_cycle && !tx_time && ipg) {
1642- if (duty_cycle < 100)
1643- tx_time = duty_cycle * ipg / (100 - duty_cycle);
1644- }
1645+ mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
1646+ mt7915_tm_set_tx_len(phy, tx_time);
1647
1648- mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
1649- mt7915_tm_set_tx_len(phy, tx_time);
1650+ if (ipg)
1651+ td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;
1652
1653- if (ipg)
1654- td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;
1655+ if (!mt7915_tm_check_skb(phy))
1656+ return;
1657+ } else {
1658+ mt7915_tm_clean_hwq(phy);
1659+ }
1660
1661- if (!en || !td->tx_skb)
1662- return;
1663+ mt7915_tm_set_tam_arb(phy, en,
1664+ td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU);
1665
1666- info = IEEE80211_SKB_CB(td->tx_skb);
1667- info->control.vif = phy->monitor_vif;
1668+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
1669+ mt7915_tm_tx_frames_mu(phy, en);
1670
1671 mt7915_tm_set_trx(phy, TM_MAC_TX, en);
1672 }
developeraace7f52022-06-24 13:40:42 +08001673@@ -545,10 +1483,6 @@ mt7915_tm_get_rx_stats(struct mt7915_phy *phy, bool clear)
developer42b63282022-06-16 13:33:13 +08001674 return ret;
1675
1676 rs_band = (struct mt7915_tm_rx_stat_band *)skb->data;
1677- /* pr_info("mdrdy_cnt = %d\n", le32_to_cpu(rs_band->mdrdy_cnt)); */
1678- /* pr_info("fcs_err = %d\n", le16_to_cpu(rs_band->fcs_err)); */
1679- /* pr_info("len_mismatch = %d\n", le16_to_cpu(rs_band->len_mismatch)); */
1680- /* pr_info("fcs_ok = %d\n", le16_to_cpu(rs_band->fcs_succ)); */
1681
1682 if (!clear) {
1683 enum mt76_rxq_id q = req.band ? MT_RXQ_EXT : MT_RXQ_MAIN;
developeraace7f52022-06-24 13:40:42 +08001684@@ -563,13 +1497,61 @@ mt7915_tm_get_rx_stats(struct mt7915_phy *phy, bool clear)
developer42b63282022-06-16 13:33:13 +08001685 return 0;
1686 }
1687
1688+static int
1689+mt7915_tm_set_rx_user_idx(struct mt7915_phy *phy, u8 aid)
1690+{
1691+ struct mt7915_dev *dev = phy->dev;
1692+ struct mt76_wcid *wcid = NULL;
1693+ struct mt76_testmode_entry_data *ed;
1694+ struct {
1695+ u8 band;
1696+ u8 _rsv;
1697+ __le16 wlan_idx;
1698+ } __packed req = {
1699+ .band = phy->band_idx,
1700+ };
1701+
1702+ mt76_tm_for_each_entry(phy->mt76, wcid, ed)
1703+ if (ed->aid == aid)
1704+ break;
1705+
1706+ if (!wcid)
1707+ return -EINVAL;
1708+
1709+ req.wlan_idx = cpu_to_le16(wcid->idx);
1710+
1711+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_STAT_USER_CTRL),
1712+ &req, sizeof(req), false);
1713+}
1714+
1715+static int
1716+mt7915_tm_set_muru_aid(struct mt7915_phy *phy, u16 aid)
1717+{
1718+ struct mt7915_dev *dev = phy->dev;
1719+ struct mt7915_tm_cmd req = {
1720+ .testmode_en = 1,
1721+ .param_idx = MCU_ATE_SET_MU_RX_AID,
1722+ .param.rx_aid.band = cpu_to_le32(phy->band_idx),
1723+ .param.rx_aid.aid = cpu_to_le16(aid),
1724+ };
1725+
1726+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
1727+ sizeof(req), false);
1728+}
1729+
1730 static void
1731 mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
1732 {
1733+ struct mt76_testmode_data *td = &phy->mt76->test;
1734+
1735+ mt7915_tm_set_trx(phy, TM_MAC_TX, false);
1736 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1737
1738 if (en) {
1739- mt7915_tm_update_channel(phy);
1740+ if (!phy->test.bf_en)
1741+ mt7915_tm_update_channel(phy);
1742+ if (td->aid)
1743+ mt7915_tm_set_rx_user_idx(phy, td->aid);
1744
1745 /* read-clear */
1746 mt7915_tm_get_rx_stats(phy, true);
developeraace7f52022-06-24 13:40:42 +08001747@@ -577,9 +1559,12 @@ mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
developer42b63282022-06-16 13:33:13 +08001748 /* clear fw count */
1749 mt7915_tm_set_phy_count(phy, 0);
1750 mt7915_tm_set_phy_count(phy, 1);
1751-
1752- mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
1753 }
1754+
1755+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
1756+ mt7915_tm_set_muru_aid(phy, en ? td->aid : 0xf800);
1757+
1758+ mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
1759 }
1760
1761 static int
developeraace7f52022-06-24 13:40:42 +08001762@@ -616,35 +1601,7 @@ mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en)
developer42b63282022-06-16 13:33:13 +08001763 tx_cont->center_ch = freq1;
1764 tx_cont->tx_ant = td->tx_antenna_mask;
1765 tx_cont->band = phy != &dev->phy;
1766-
1767- switch (chandef->width) {
1768- case NL80211_CHAN_WIDTH_40:
1769- tx_cont->bw = CMD_CBW_40MHZ;
1770- break;
1771- case NL80211_CHAN_WIDTH_80:
1772- tx_cont->bw = CMD_CBW_80MHZ;
1773- break;
1774- case NL80211_CHAN_WIDTH_80P80:
1775- tx_cont->bw = CMD_CBW_8080MHZ;
1776- break;
1777- case NL80211_CHAN_WIDTH_160:
1778- tx_cont->bw = CMD_CBW_160MHZ;
1779- break;
1780- case NL80211_CHAN_WIDTH_5:
1781- tx_cont->bw = CMD_CBW_5MHZ;
1782- break;
1783- case NL80211_CHAN_WIDTH_10:
1784- tx_cont->bw = CMD_CBW_10MHZ;
1785- break;
1786- case NL80211_CHAN_WIDTH_20:
1787- tx_cont->bw = CMD_CBW_20MHZ;
1788- break;
1789- case NL80211_CHAN_WIDTH_20_NOHT:
1790- tx_cont->bw = CMD_CBW_20MHZ;
1791- break;
1792- default:
1793- return -EINVAL;
1794- }
1795+ tx_cont->bw = mt7915_tm_chan_bw(chandef->width);
1796
1797 if (!en) {
1798 req.op.rf.param.func_data = cpu_to_le32(phy != &dev->phy);
developeraace7f52022-06-24 13:40:42 +08001799@@ -728,6 +1685,12 @@ mt7915_tm_update_params(struct mt7915_phy *phy, u32 changed)
developer42b63282022-06-16 13:33:13 +08001800 mt7915_tm_set_freq_offset(phy, en, en ? td->freq_offset : 0);
1801 if (changed & BIT(TM_CHANGED_TXPOWER))
1802 mt7915_tm_set_tx_power(phy);
1803+ if (changed & BIT(TM_CHANGED_AID))
1804+ mt7915_tm_set_entry(phy);
1805+ if (changed & BIT(TM_CHANGED_CFG))
1806+ mt7915_tm_set_cfg(phy);
1807+ if (changed & BIT(TM_CHANGED_TXBF_ACT))
1808+ mt7915_tm_set_txbf(phy);
1809 }
1810
1811 static int
developeraace7f52022-06-24 13:40:42 +08001812@@ -801,6 +1764,7 @@ static int
developer42b63282022-06-16 13:33:13 +08001813 mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
1814 {
1815 struct mt7915_phy *phy = mphy->priv;
1816+ struct mt7915_dev *dev = phy->dev;
1817 void *rx, *rssi;
1818 int i;
1819
developeraace7f52022-06-24 13:40:42 +08001820@@ -846,11 +1810,68 @@ mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
developer42b63282022-06-16 13:33:13 +08001821
1822 nla_nest_end(msg, rx);
1823
1824+ if (mphy->test.tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
1825+ mphy->test.tx_done += mt76_rr(dev, MT_MIB_DR8(phy != &dev->phy));
1826+
1827 return mt7915_tm_get_rx_stats(phy, false);
1828 }
1829
1830+static int
1831+mt7915_tm_write_back_to_efuse(struct mt7915_dev *dev)
1832+{
1833+ struct mt7915_mcu_eeprom_info req = {};
1834+ u8 *eeprom = dev->mt76.eeprom.data;
1835+ int i, ret = -EINVAL;
1836+
1837+ /* prevent from damaging chip id in efuse */
1838+ if (mt76_chip(&dev->mt76) != get_unaligned_le16(eeprom))
1839+ goto out;
1840+
1841+ for (i = 0; i < mt7915_eeprom_size(dev); i += MT76_TM_EEPROM_BLOCK_SIZE) {
1842+ req.addr = cpu_to_le32(i);
1843+ memcpy(&req.data, eeprom + i, MT76_TM_EEPROM_BLOCK_SIZE);
1844+
1845+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(EFUSE_ACCESS),
1846+ &req, sizeof(req), true);
1847+ if (ret)
1848+ return ret;
1849+ }
1850+
1851+out:
1852+ return ret;
1853+}
1854+
1855+static int
1856+mt7915_tm_set_eeprom(struct mt76_phy *mphy, u32 offset, u8 *val, u8 action)
1857+{
1858+ struct mt7915_phy *phy = mphy->priv;
1859+ struct mt7915_dev *dev = phy->dev;
1860+ u8 *eeprom = dev->mt76.eeprom.data;
1861+ int ret = 0;
1862+
1863+ if (offset >= mt7915_eeprom_size(dev))
1864+ return -EINVAL;
1865+
1866+ switch (action) {
1867+ case MT76_TM_EEPROM_ACTION_UPDATE_DATA:
1868+ memcpy(eeprom + offset, val, MT76_TM_EEPROM_BLOCK_SIZE);
1869+ break;
1870+ case MT76_TM_EEPROM_ACTION_UPDATE_BUFFER_MODE:
1871+ ret = mt7915_mcu_set_eeprom(dev, true);
1872+ break;
1873+ case MT76_TM_EEPROM_ACTION_WRITE_TO_EFUSE:
1874+ ret = mt7915_tm_write_back_to_efuse(dev);
1875+ break;
1876+ default:
1877+ break;
1878+ }
1879+
1880+ return ret;
1881+}
1882+
1883 const struct mt76_testmode_ops mt7915_testmode_ops = {
1884 .set_state = mt7915_tm_set_state,
1885 .set_params = mt7915_tm_set_params,
1886 .dump_stats = mt7915_tm_dump_stats,
1887+ .set_eeprom = mt7915_tm_set_eeprom,
1888 };
1889diff --git a/mt7915/testmode.h b/mt7915/testmode.h
developer3262bf82022-07-12 11:37:54 +08001890index a1c54c89..01b08e9e 100644
developer42b63282022-06-16 13:33:13 +08001891--- a/mt7915/testmode.h
1892+++ b/mt7915/testmode.h
1893@@ -4,6 +4,8 @@
1894 #ifndef __MT7915_TESTMODE_H
1895 #define __MT7915_TESTMODE_H
1896
1897+#include "mcu.h"
1898+
1899 struct mt7915_tm_trx {
1900 u8 type;
1901 u8 enable;
1902@@ -39,6 +41,11 @@ struct mt7915_tm_cfg {
1903 u8 _rsv[2];
1904 };
1905
1906+struct mt7915_tm_mu_rx_aid {
1907+ __le32 band;
1908+ __le16 aid;
1909+};
1910+
1911 struct mt7915_tm_cmd {
1912 u8 testmode_en;
1913 u8 param_idx;
1914@@ -50,6 +57,7 @@ struct mt7915_tm_cmd {
1915 struct mt7915_tm_slot_time slot;
1916 struct mt7915_tm_clean_txq clean;
1917 struct mt7915_tm_cfg cfg;
1918+ struct mt7915_tm_mu_rx_aid rx_aid;
1919 u8 test[72];
1920 } param;
1921 } __packed;
1922@@ -109,6 +117,16 @@ enum {
1923 TAM_ARB_OP_MODE_FORCE_SU = 5,
1924 };
1925
1926+enum {
1927+ TM_CBW_20MHZ,
1928+ TM_CBW_40MHZ,
1929+ TM_CBW_80MHZ,
1930+ TM_CBW_10MHZ,
1931+ TM_CBW_5MHZ,
1932+ TM_CBW_160MHZ,
1933+ TM_CBW_8080MHZ,
1934+};
1935+
1936 struct mt7915_tm_rx_stat_band {
1937 u8 category;
1938
1939@@ -130,4 +148,264 @@ struct mt7915_tm_rx_stat_band {
1940 __le16 mdrdy_cnt_ofdm;
1941 };
1942
1943+struct mt7915_tm_muru_comm {
1944+ u8 ppdu_format;
1945+ u8 sch_type;
1946+ u8 band;
1947+ u8 wmm_idx;
1948+ u8 spe_idx;
1949+ u8 proc_type;
1950+};
1951+
1952+struct mt7915_tm_muru_dl_usr {
1953+ __le16 wlan_idx;
1954+ u8 ru_alloc_seg;
1955+ u8 ru_idx;
1956+ u8 ldpc;
1957+ u8 nss;
1958+ u8 mcs;
1959+ u8 mu_group_idx;
1960+ u8 vht_groud_id;
1961+ u8 vht_up;
1962+ u8 he_start_stream;
1963+ u8 he_mu_spatial;
1964+ u8 ack_policy;
1965+ __le16 tx_power_alpha;
1966+};
1967+
1968+struct mt7915_tm_muru_dl {
1969+ u8 user_num;
1970+ u8 tx_mode;
1971+ u8 bw;
1972+ u8 gi;
1973+ u8 ltf;
1974+ /* sigB */
1975+ u8 mcs;
1976+ u8 dcm;
1977+ u8 cmprs;
1978+
1979+ u8 tx_power;
1980+ u8 ru[8];
1981+ u8 c26[2];
1982+ u8 ack_policy;
1983+
1984+ struct mt7915_tm_muru_dl_usr usr[16];
1985+};
1986+
1987+struct mt7915_tm_muru_ul_usr {
1988+ __le16 wlan_idx;
1989+ u8 ru_alloc;
1990+ u8 ru_idx;
1991+ u8 ldpc;
1992+ u8 nss;
1993+ u8 mcs;
1994+ u8 target_rssi;
1995+ __le32 trig_pkt_size;
1996+};
1997+
1998+struct mt7915_tm_muru_ul {
1999+ u8 user_num;
2000+
2001+ /* UL TX */
2002+ u8 trig_type;
2003+ __le16 trig_cnt;
2004+ __le16 trig_intv;
2005+ u8 bw;
2006+ u8 gi_ltf;
2007+ __le16 ul_len;
2008+ u8 pad;
2009+ u8 trig_ta[ETH_ALEN];
2010+ u8 ru[8];
2011+ u8 c26[2];
2012+
2013+ struct mt7915_tm_muru_ul_usr usr[16];
2014+ /* HE TB RX Debug */
2015+ __le32 rx_hetb_nonsf_en_bitmap;
2016+ __le32 rx_hetb_cfg[2];
2017+
2018+ /* DL TX */
2019+ u8 ba_type;
2020+};
2021+
2022+struct mt7915_tm_muru {
2023+ __le32 cfg_comm;
2024+ __le32 cfg_dl;
2025+ __le32 cfg_ul;
2026+
2027+ struct mt7915_tm_muru_comm comm;
2028+ struct mt7915_tm_muru_dl dl;
2029+ struct mt7915_tm_muru_ul ul;
2030+};
2031+
2032+#define MURU_PPDU_HE_MU BIT(3)
2033+
2034+/* Common Config */
2035+/* #define MURU_COMM_PPDU_FMT BIT(0) */
2036+/* #define MURU_COMM_SCH_TYPE BIT(1) */
2037+/* #define MURU_COMM_BAND BIT(2) */
2038+/* #define MURU_COMM_WMM BIT(3) */
2039+/* #define MURU_COMM_SPE_IDX BIT(4) */
2040+/* #define MURU_COMM_PROC_TYPE BIT(5) */
2041+/* #define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_BAND | \ */
2042+/* MURU_COMM_WMM | MURU_COMM_SPE_IDX) */
2043+/* DL Config */
2044+#define MURU_DL_BW BIT(0)
2045+#define MURU_DL_GI BIT(1)
2046+#define MURU_DL_TX_MODE BIT(2)
2047+#define MURU_DL_TONE_PLAN BIT(3)
2048+#define MURU_DL_USER_CNT BIT(4)
2049+#define MURU_DL_LTF BIT(5)
2050+#define MURU_DL_SIGB_MCS BIT(6)
2051+#define MURU_DL_SIGB_DCM BIT(7)
2052+#define MURU_DL_SIGB_CMPRS BIT(8)
2053+#define MURU_DL_ACK_POLICY BIT(9)
2054+#define MURU_DL_TXPOWER BIT(10)
2055+/* DL Per User Config */
2056+#define MURU_DL_USER_WLAN_ID BIT(16)
2057+#define MURU_DL_USER_COD BIT(17)
2058+#define MURU_DL_USER_MCS BIT(18)
2059+#define MURU_DL_USER_NSS BIT(19)
2060+#define MURU_DL_USER_RU_ALLOC BIT(20)
2061+#define MURU_DL_USER_MUMIMO_GRP BIT(21)
2062+#define MURU_DL_USER_MUMIMO_VHT BIT(22)
2063+#define MURU_DL_USER_ACK_POLICY BIT(23)
2064+#define MURU_DL_USER_MUMIMO_HE BIT(24)
2065+#define MURU_DL_USER_PWR_ALPHA BIT(25)
2066+#define MURU_DL_SET (GENMASK(7, 0) | GENMASK(20, 16) | BIT(25))
2067+
2068+#define MAX_PHASE_GROUP_NUM 9
2069+
2070+struct mt7915_tm_txbf_phase {
2071+ u8 status;
2072+ struct {
2073+ u8 r0_uh;
2074+ u8 r0_h;
2075+ u8 r0_m;
2076+ u8 r0_l;
2077+ u8 r0_ul;
2078+ u8 r1_uh;
2079+ u8 r1_h;
2080+ u8 r1_m;
2081+ u8 r1_l;
2082+ u8 r1_ul;
2083+ u8 r2_uh;
2084+ u8 r2_h;
2085+ u8 r2_m;
2086+ u8 r2_l;
2087+ u8 r2_ul;
2088+ u8 r3_uh;
2089+ u8 r3_h;
2090+ u8 r3_m;
2091+ u8 r3_l;
2092+ u8 r3_ul;
2093+ u8 r2_uh_sx2;
2094+ u8 r2_h_sx2;
2095+ u8 r2_m_sx2;
2096+ u8 r2_l_sx2;
2097+ u8 r2_ul_sx2;
2098+ u8 r3_uh_sx2;
2099+ u8 r3_h_sx2;
2100+ u8 r3_m_sx2;
2101+ u8 r3_l_sx2;
2102+ u8 r3_ul_sx2;
2103+ u8 m_t0_h;
2104+ u8 m_t1_h;
2105+ u8 m_t2_h;
2106+ u8 m_t2_h_sx2;
2107+ u8 r0_reserved;
2108+ u8 r1_reserved;
2109+ u8 r2_reserved;
2110+ u8 r3_reserved;
2111+ u8 r2_sx2_reserved;
2112+ u8 r3_sx2_reserved;
2113+ } phase;
2114+};
2115+
2116+struct mt7915_tm_pfmu_tag1 {
2117+ __le32 pfmu_idx:10;
2118+ __le32 ebf:1;
2119+ __le32 data_bw:2;
2120+ __le32 lm:2;
2121+ __le32 is_mu:1;
2122+ __le32 nr:3, nc:3;
2123+ __le32 codebook:2;
2124+ __le32 ngroup:2;
2125+ __le32 _rsv:2;
2126+ __le32 invalid_prof:1;
2127+ __le32 rmsd:3;
2128+
2129+ __le32 col_id1:6, row_id1:10;
2130+ __le32 col_id2:6, row_id2:10;
2131+ __le32 col_id3:6, row_id3:10;
2132+ __le32 col_id4:6, row_id4:10;
2133+
2134+ __le32 ru_start_id:7;
2135+ __le32 _rsv1:1;
2136+ __le32 ru_end_id:7;
2137+ __le32 _rsv2:1;
2138+ __le32 mob_cal_en:1;
2139+ __le32 _rsv3:15;
2140+
2141+ __le32 snr_sts0:8, snr_sts1:8, snr_sts2:8, snr_sts3:8;
2142+ __le32 snr_sts4:8, snr_sts5:8, snr_sts6:8, snr_sts7:8;
2143+
2144+ __le32 _rsv4;
2145+} __packed;
2146+
2147+struct mt7915_tm_pfmu_tag2 {
2148+ __le32 smart_ant:24;
2149+ __le32 se_idx:5;
2150+ __le32 _rsv:3;
2151+
2152+ __le32 _rsv1:8;
2153+ __le32 rmsd_thres:3;
2154+ __le32 _rsv2:5;
2155+ __le32 ibf_timeout:8;
2156+ __le32 _rsv3:8;
2157+
2158+ __le32 _rsv4:16;
2159+ __le32 ibf_data_bw:2;
2160+ __le32 ibf_nc:3;
2161+ __le32 ibf_nr:3;
2162+ __le32 ibf_ru:8;
2163+
2164+ __le32 mob_delta_t:8;
2165+ __le32 mob_lq_result:7;
2166+ __le32 _rsv5:1;
2167+ __le32 _rsv6:16;
2168+
2169+ __le32 _rsv7;
2170+} __packed;
2171+
2172+struct mt7915_tm_pfmu_tag {
2173+ struct mt7915_tm_pfmu_tag1 t1;
2174+ struct mt7915_tm_pfmu_tag2 t2;
2175+};
2176+
2177+struct mt7915_tm_pfmu_data {
2178+ __le16 subc_idx;
2179+ __le16 phi11;
2180+ __le16 phi21;
2181+ __le16 phi31;
2182+};
2183+
2184+struct mt7915_tm_ibf_cal_info {
2185+ u8 format_id;
2186+ u8 group_l_m_n;
2187+ u8 group;
2188+ bool sx2;
2189+ u8 status;
2190+ u8 cal_type;
2191+ u8 _rsv[2];
2192+ u8 buf[1000];
2193+} __packed;
2194+
2195+enum {
2196+ IBF_PHASE_CAL_UNSPEC,
2197+ IBF_PHASE_CAL_NORMAL,
2198+ IBF_PHASE_CAL_VERIFY,
2199+ IBF_PHASE_CAL_NORMAL_INSTRUMENT,
2200+ IBF_PHASE_CAL_VERIFY_INSTRUMENT,
2201+};
2202+
2203 #endif
2204diff --git a/testmode.c b/testmode.c
developer3262bf82022-07-12 11:37:54 +08002205index 4a24f6c9..690e9a7d 100644
developer42b63282022-06-16 13:33:13 +08002206--- a/testmode.c
2207+++ b/testmode.c
developer3262bf82022-07-12 11:37:54 +08002208@@ -25,28 +25,16 @@ const struct nla_policy mt76_tm_policy[NUM_MT76_TM_ATTRS] = {
developer42b63282022-06-16 13:33:13 +08002209 };
2210 EXPORT_SYMBOL_GPL(mt76_tm_policy);
2211
2212-void mt76_testmode_tx_pending(struct mt76_phy *phy)
2213+static void
2214+mt76_testmode_queue_tx(struct mt76_phy *phy, struct mt76_wcid *wcid,
developer3262bf82022-07-12 11:37:54 +08002215+ struct sk_buff *skb, struct mt76_queue *q, int qid,
2216+ u16 limit)
developer42b63282022-06-16 13:33:13 +08002217 {
2218 struct mt76_testmode_data *td = &phy->test;
2219 struct mt76_dev *dev = phy->dev;
2220- struct mt76_wcid *wcid = &dev->global_wcid;
2221- struct sk_buff *skb = td->tx_skb;
2222- struct mt76_queue *q;
2223- u16 tx_queued_limit;
2224- int qid;
2225-
2226- if (!skb || !td->tx_pending)
2227- return;
2228+ u16 count = limit;
2229
2230- qid = skb_get_queue_mapping(skb);
2231- q = phy->q_tx[qid];
2232-
2233- tx_queued_limit = td->tx_queued_limit ? td->tx_queued_limit : 1000;
2234-
2235- spin_lock_bh(&q->lock);
2236-
2237- while (td->tx_pending > 0 &&
2238- td->tx_queued - td->tx_done < tx_queued_limit &&
2239+ while (td->tx_pending > 0 && count &&
2240 q->queued < q->ndesc / 2) {
2241 int ret;
2242
developer3262bf82022-07-12 11:37:54 +08002243@@ -55,13 +43,65 @@ void mt76_testmode_tx_pending(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002244 if (ret < 0)
2245 break;
2246
2247+ count--;
2248 td->tx_pending--;
2249 td->tx_queued++;
2250+
2251+ if (td->tx_rate_mode != MT76_TM_TX_MODE_HE_MU)
2252+ if (td->tx_queued - td->tx_done >= limit)
2253+ break;
2254 }
2255
2256 dev->queue_ops->kick(dev, q);
2257+}
2258+
2259+void mt76_testmode_tx_pending(struct mt76_phy *phy)
2260+{
2261+ struct mt76_testmode_data *td = &phy->test;
2262+ struct mt76_testmode_entry_data *ed;
2263+ struct mt76_queue *q;
2264+ int qid;
2265+ u16 tx_queued_limit;
2266+ u32 remain;
2267+ bool is_mu;
2268+
2269+ if (!td->tx_pending)
2270+ return;
2271+
2272+ /* tx_queued_limit = td->tx_queued_limit ?: 100; */
2273+ tx_queued_limit = 100;
2274+
2275+ if (!td->aid) {
2276+ qid = skb_get_queue_mapping(td->tx_skb);
2277+ q = phy->q_tx[qid];
2278+ spin_lock_bh(&q->lock);
2279+ mt76_testmode_queue_tx(phy, &phy->dev->global_wcid,
developer3262bf82022-07-12 11:37:54 +08002280+ td->tx_skb, q, qid, tx_queued_limit);
developer42b63282022-06-16 13:33:13 +08002281+ spin_unlock_bh(&q->lock);
2282+
2283+ return;
2284+ }
2285+
2286+ is_mu = td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU;
2287+ ed = mt76_testmode_entry_data(phy, td->cur_entry);
2288+ qid = skb_get_queue_mapping(ed->tx_skb);
2289+ q = phy->q_tx[qid];
2290+
2291+ spin_lock_bh(&q->lock);
2292+
2293+ remain = is_mu ? 1 : (td->tx_pending % td->tx_count) ?: td->tx_count;
2294+ if (remain < tx_queued_limit)
2295+ tx_queued_limit = remain;
2296+
developer3262bf82022-07-12 11:37:54 +08002297+ mt76_testmode_queue_tx(phy, td->cur_entry, ed->tx_skb, q, qid, tx_queued_limit);
developer42b63282022-06-16 13:33:13 +08002298+
2299+ if (td->tx_pending % td->tx_count == 0 || is_mu)
2300+ td->cur_entry = list_next_entry(td->cur_entry, list);
2301
2302 spin_unlock_bh(&q->lock);
2303+
2304+ if (is_mu && td->tx_pending)
2305+ mt76_worker_schedule(&phy->dev->tx_worker);
2306 }
2307
2308 static u32
developer3262bf82022-07-12 11:37:54 +08002309@@ -87,15 +127,31 @@ mt76_testmode_max_mpdu_len(struct mt76_phy *phy, u8 tx_rate_mode)
developer42b63282022-06-16 13:33:13 +08002310 }
2311
2312 static void
2313-mt76_testmode_free_skb(struct mt76_phy *phy)
2314+mt76_testmode_free_skb(struct sk_buff **tx_skb)
2315+{
2316+ if (!(*tx_skb))
2317+ return;
2318+
2319+ dev_kfree_skb(*tx_skb);
2320+ *tx_skb = NULL;
2321+}
2322+
2323+static void
2324+mt76_testmode_free_skb_all(struct mt76_phy *phy)
2325 {
2326 struct mt76_testmode_data *td = &phy->test;
2327+ struct mt76_testmode_entry_data *ed = &td->ed;
2328+ struct mt76_wcid *wcid;
2329+
2330+ mt76_testmode_free_skb(&ed->tx_skb);
2331
2332- dev_kfree_skb(td->tx_skb);
2333- td->tx_skb = NULL;
2334+ mt76_tm_for_each_entry(phy, wcid, ed)
2335+ mt76_testmode_free_skb(&ed->tx_skb);
2336 }
2337
2338-int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
2339+static int
2340+mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len,
2341+ struct sk_buff **tx_skb, u8 (*addr)[ETH_ALEN])
2342 {
2343 #define MT_TXP_MAX_LEN 4095
2344 u16 fc = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_DATA |
developer3262bf82022-07-12 11:37:54 +08002345@@ -117,7 +173,8 @@ int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
developer42b63282022-06-16 13:33:13 +08002346 nfrags = len / MT_TXP_MAX_LEN;
2347 head_len = nfrags ? MT_TXP_MAX_LEN : len;
2348
2349- if (len > IEEE80211_MAX_FRAME_LEN)
2350+ if (len > IEEE80211_MAX_FRAME_LEN ||
2351+ td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
2352 fc |= IEEE80211_STYPE_QOS_DATA;
2353
2354 head = alloc_skb(head_len, GFP_KERNEL);
developer3262bf82022-07-12 11:37:54 +08002355@@ -126,9 +183,9 @@ int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
developer42b63282022-06-16 13:33:13 +08002356
2357 hdr = __skb_put_zero(head, head_len);
2358 hdr->frame_control = cpu_to_le16(fc);
2359- memcpy(hdr->addr1, td->addr[0], ETH_ALEN);
2360- memcpy(hdr->addr2, td->addr[1], ETH_ALEN);
2361- memcpy(hdr->addr3, td->addr[2], ETH_ALEN);
2362+ memcpy(hdr->addr1, addr[0], ETH_ALEN);
2363+ memcpy(hdr->addr2, addr[1], ETH_ALEN);
2364+ memcpy(hdr->addr3, addr[2], ETH_ALEN);
2365 skb_set_queue_mapping(head, IEEE80211_AC_BE);
2366
2367 info = IEEE80211_SKB_CB(head);
developer3262bf82022-07-12 11:37:54 +08002368@@ -152,7 +209,7 @@ int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
developer42b63282022-06-16 13:33:13 +08002369
2370 frag = alloc_skb(frag_len, GFP_KERNEL);
2371 if (!frag) {
2372- mt76_testmode_free_skb(phy);
2373+ mt76_testmode_free_skb(tx_skb);
2374 dev_kfree_skb(head);
2375 return -ENOMEM;
2376 }
developer3262bf82022-07-12 11:37:54 +08002377@@ -165,15 +222,14 @@ int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len)
developer42b63282022-06-16 13:33:13 +08002378 frag_tail = &(*frag_tail)->next;
2379 }
2380
2381- mt76_testmode_free_skb(phy);
2382- td->tx_skb = head;
2383+ mt76_testmode_free_skb(tx_skb);
2384+ *tx_skb = head;
2385
2386 return 0;
2387 }
2388-EXPORT_SYMBOL(mt76_testmode_alloc_skb);
2389
2390-static int
2391-mt76_testmode_tx_init(struct mt76_phy *phy)
2392+int mt76_testmode_init_skb(struct mt76_phy *phy, u32 len,
2393+ struct sk_buff **tx_skb, u8 (*addr)[ETH_ALEN])
2394 {
2395 struct mt76_testmode_data *td = &phy->test;
2396 struct ieee80211_tx_info *info;
developer3262bf82022-07-12 11:37:54 +08002397@@ -181,7 +237,7 @@ mt76_testmode_tx_init(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002398 u8 max_nss = hweight8(phy->antenna_mask);
2399 int ret;
2400
2401- ret = mt76_testmode_alloc_skb(phy, td->tx_mpdu_len);
2402+ ret = mt76_testmode_alloc_skb(phy, len, tx_skb, addr);
2403 if (ret)
2404 return ret;
2405
developer3262bf82022-07-12 11:37:54 +08002406@@ -191,7 +247,7 @@ mt76_testmode_tx_init(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002407 if (td->tx_antenna_mask)
2408 max_nss = min_t(u8, max_nss, hweight8(td->tx_antenna_mask));
2409
2410- info = IEEE80211_SKB_CB(td->tx_skb);
2411+ info = IEEE80211_SKB_CB(*tx_skb);
2412 rate = &info->control.rates[0];
2413 rate->count = 1;
2414 rate->idx = td->tx_rate_idx;
developer3262bf82022-07-12 11:37:54 +08002415@@ -263,6 +319,25 @@ mt76_testmode_tx_init(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002416 out:
2417 return 0;
2418 }
2419+EXPORT_SYMBOL(mt76_testmode_init_skb);
2420+
2421+static int
2422+mt76_testmode_tx_init(struct mt76_phy *phy)
2423+{
2424+ struct mt76_testmode_entry_data *ed;
2425+ struct mt76_wcid *wcid;
2426+
2427+ mt76_tm_for_each_entry(phy, wcid, ed) {
2428+ int ret;
2429+
2430+ ret = mt76_testmode_init_skb(phy, ed->tx_mpdu_len,
2431+ &ed->tx_skb, ed->addr);
2432+ if (ret)
2433+ return ret;
2434+ }
2435+
2436+ return 0;
2437+}
2438
2439 static void
2440 mt76_testmode_tx_start(struct mt76_phy *phy)
developer3262bf82022-07-12 11:37:54 +08002441@@ -273,6 +348,14 @@ mt76_testmode_tx_start(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002442 td->tx_queued = 0;
2443 td->tx_done = 0;
2444 td->tx_pending = td->tx_count;
2445+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
2446+ td->tx_pending = 1;
2447+ if (td->entry_num) {
2448+ td->tx_pending *= td->entry_num;
2449+ td->cur_entry = list_first_entry(&td->tm_entry_list,
2450+ struct mt76_wcid, list);
2451+ }
2452+
2453 mt76_worker_schedule(&dev->tx_worker);
2454 }
2455
developer3262bf82022-07-12 11:37:54 +08002456@@ -291,7 +374,7 @@ mt76_testmode_tx_stop(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002457 wait_event_timeout(dev->tx_wait, td->tx_done == td->tx_queued,
2458 MT76_TM_TIMEOUT * HZ);
2459
2460- mt76_testmode_free_skb(phy);
2461+ mt76_testmode_free_skb_all(phy);
2462 }
2463
2464 static inline void
developer3262bf82022-07-12 11:37:54 +08002465@@ -322,6 +405,8 @@ mt76_testmode_init_defaults(struct mt76_phy *phy)
developer42b63282022-06-16 13:33:13 +08002466 memcpy(td->addr[0], phy->macaddr, ETH_ALEN);
2467 memcpy(td->addr[1], phy->macaddr, ETH_ALEN);
2468 memcpy(td->addr[2], phy->macaddr, ETH_ALEN);
2469+
2470+ INIT_LIST_HEAD(&phy->test.tm_entry_list);
2471 }
2472
2473 static int
developer3262bf82022-07-12 11:37:54 +08002474@@ -331,8 +416,12 @@ __mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state)
developer42b63282022-06-16 13:33:13 +08002475 struct mt76_dev *dev = phy->dev;
2476 int err;
2477
2478- if (prev_state == MT76_TM_STATE_TX_FRAMES)
2479+ if (prev_state == MT76_TM_STATE_TX_FRAMES) {
2480+ /* MU needs to clean hwq for free done event */
2481+ if (phy->test.tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
2482+ dev->test_ops->set_state(phy, MT76_TM_STATE_IDLE);
2483 mt76_testmode_tx_stop(phy);
2484+ }
2485
2486 if (state == MT76_TM_STATE_TX_FRAMES) {
2487 err = mt76_testmode_tx_init(phy);
developer3262bf82022-07-12 11:37:54 +08002488@@ -402,6 +491,44 @@ mt76_tm_get_u8(struct nlattr *attr, u8 *dest, u8 min, u8 max)
developer42b63282022-06-16 13:33:13 +08002489 return 0;
2490 }
2491
2492+static int
2493+mt76_testmode_set_eeprom(struct mt76_phy *phy, struct nlattr **tb)
2494+{
2495+ struct mt76_dev *dev = phy->dev;
2496+ u8 action, val[MT76_TM_EEPROM_BLOCK_SIZE];
2497+ u32 offset = 0;
2498+ int err = -EINVAL;
2499+
2500+ if (!dev->test_ops->set_eeprom)
2501+ return -EOPNOTSUPP;
2502+
2503+ if (mt76_tm_get_u8(tb[MT76_TM_ATTR_EEPROM_ACTION], &action,
2504+ 0, MT76_TM_EEPROM_ACTION_MAX))
2505+ goto out;
2506+
2507+ if (tb[MT76_TM_ATTR_EEPROM_OFFSET]) {
2508+ struct nlattr *cur;
2509+ int rem, idx = 0;
2510+
2511+ offset = nla_get_u32(tb[MT76_TM_ATTR_EEPROM_OFFSET]);
2512+ if (!!(offset % MT76_TM_EEPROM_BLOCK_SIZE) ||
2513+ !tb[MT76_TM_ATTR_EEPROM_VAL])
2514+ goto out;
2515+
2516+ nla_for_each_nested(cur, tb[MT76_TM_ATTR_EEPROM_VAL], rem) {
2517+ if (nla_len(cur) != 1 || idx >= ARRAY_SIZE(val))
2518+ goto out;
2519+
2520+ val[idx++] = nla_get_u8(cur);
2521+ }
2522+ }
2523+
2524+ err = dev->test_ops->set_eeprom(phy, offset, val, action);
2525+
2526+out:
2527+ return err;
2528+}
2529+
2530 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2531 void *data, int len)
2532 {
developer3262bf82022-07-12 11:37:54 +08002533@@ -425,6 +552,11 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer42b63282022-06-16 13:33:13 +08002534
2535 mutex_lock(&dev->mutex);
2536
2537+ if (tb[MT76_TM_ATTR_EEPROM_ACTION]) {
2538+ err = mt76_testmode_set_eeprom(phy, tb);
2539+ goto out;
2540+ }
2541+
2542 if (tb[MT76_TM_ATTR_RESET]) {
2543 mt76_testmode_set_state(phy, MT76_TM_STATE_OFF);
2544 memset(td, 0, sizeof(*td));
developer3262bf82022-07-12 11:37:54 +08002545@@ -452,7 +584,10 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer42b63282022-06-16 13:33:13 +08002546 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_DUTY_CYCLE],
2547 &td->tx_duty_cycle, 0, 99) ||
2548 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_POWER_CONTROL],
2549- &td->tx_power_control, 0, 1))
2550+ &td->tx_power_control, 0, 1) ||
2551+ mt76_tm_get_u8(tb[MT76_TM_ATTR_AID], &td->aid, 0, 16) ||
2552+ mt76_tm_get_u8(tb[MT76_TM_ATTR_RU_ALLOC], &td->ru_alloc, 0, 0xff) ||
2553+ mt76_tm_get_u8(tb[MT76_TM_ATTR_RU_IDX], &td->ru_idx, 0, 68))
2554 goto out;
2555
2556 if (tb[MT76_TM_ATTR_TX_LENGTH]) {
developer3262bf82022-07-12 11:37:54 +08002557@@ -484,8 +619,7 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer42b63282022-06-16 13:33:13 +08002558
2559 if (tb[MT76_TM_ATTR_TX_POWER]) {
2560 struct nlattr *cur;
2561- int idx = 0;
2562- int rem;
2563+ int rem, idx = 0;
2564
2565 nla_for_each_nested(cur, tb[MT76_TM_ATTR_TX_POWER], rem) {
2566 if (nla_len(cur) != 1 ||
developer3262bf82022-07-12 11:37:54 +08002567@@ -505,11 +639,45 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer42b63282022-06-16 13:33:13 +08002568 if (nla_len(cur) != ETH_ALEN || idx >= 3)
2569 goto out;
2570
2571- memcpy(td->addr[idx], nla_data(cur), ETH_ALEN);
2572+ memcpy(td->addr[idx++], nla_data(cur), ETH_ALEN);
2573+ }
2574+ }
2575+
2576+ if (tb[MT76_TM_ATTR_CFG]) {
2577+ struct nlattr *cur;
2578+ int rem, idx = 0;
2579+
2580+ nla_for_each_nested(cur, tb[MT76_TM_ATTR_CFG], rem) {
2581+ if (nla_len(cur) != 1 || idx >= 2)
2582+ goto out;
2583+
2584+ if (idx == 0)
2585+ td->cfg.type = nla_get_u8(cur);
2586+ else
2587+ td->cfg.enable = nla_get_u8(cur);
2588 idx++;
2589 }
2590 }
2591
2592+ if (tb[MT76_TM_ATTR_TXBF_ACT]) {
2593+ struct nlattr *cur;
2594+ int rem, idx = 0;
2595+
2596+ if (!tb[MT76_TM_ATTR_TXBF_PARAM] ||
2597+ mt76_tm_get_u8(tb[MT76_TM_ATTR_TXBF_ACT], &td->txbf_act,
2598+ 0, MT76_TM_TXBF_ACT_MAX))
2599+ goto out;
2600+
2601+ memset(td->txbf_param, 0, sizeof(td->txbf_param));
2602+ nla_for_each_nested(cur, tb[MT76_TM_ATTR_TXBF_PARAM], rem) {
2603+ if (nla_len(cur) != 2 ||
2604+ idx >= ARRAY_SIZE(td->txbf_param))
2605+ goto out;
2606+
2607+ td->txbf_param[idx++] = nla_get_u16(cur);
2608+ }
2609+ }
2610+
2611 if (dev->test_ops->set_params) {
2612 err = dev->test_ops->set_params(phy, tb, state);
2613 if (err)
developer3262bf82022-07-12 11:37:54 +08002614@@ -574,6 +742,7 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
developer42b63282022-06-16 13:33:13 +08002615 struct mt76_phy *phy = hw->priv;
2616 struct mt76_dev *dev = phy->dev;
2617 struct mt76_testmode_data *td = &phy->test;
2618+ struct mt76_testmode_entry_data *ed = &td->ed;
2619 struct nlattr *tb[NUM_MT76_TM_ATTRS] = {};
2620 int err = 0;
2621 void *a;
developer3262bf82022-07-12 11:37:54 +08002622@@ -606,6 +775,19 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
developer42b63282022-06-16 13:33:13 +08002623 goto out;
2624 }
2625
2626+ if (tb[MT76_TM_ATTR_AID]) {
2627+ struct mt76_wcid *wcid;
2628+ u8 aid;
2629+
2630+ err = mt76_tm_get_u8(tb[MT76_TM_ATTR_AID], &aid, 1, 16);
2631+ if (err)
2632+ goto out;
2633+
2634+ mt76_tm_for_each_entry(phy, wcid, ed)
2635+ if (ed->aid == aid)
2636+ ed = mt76_testmode_entry_data(phy, wcid);
2637+ }
2638+
2639 mt76_testmode_init_defaults(phy);
2640
2641 err = -EMSGSIZE;
developer3262bf82022-07-12 11:37:54 +08002642@@ -618,12 +800,8 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
developer42b63282022-06-16 13:33:13 +08002643 goto out;
2644
2645 if (nla_put_u32(msg, MT76_TM_ATTR_TX_COUNT, td->tx_count) ||
2646- nla_put_u32(msg, MT76_TM_ATTR_TX_LENGTH, td->tx_mpdu_len) ||
2647 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_MODE, td->tx_rate_mode) ||
2648- nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_NSS, td->tx_rate_nss) ||
2649- nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_IDX, td->tx_rate_idx) ||
2650 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_SGI, td->tx_rate_sgi) ||
2651- nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_LDPC, td->tx_rate_ldpc) ||
2652 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_STBC, td->tx_rate_stbc) ||
2653 (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_LTF) &&
2654 nla_put_u8(msg, MT76_TM_ATTR_TX_LTF, td->tx_ltf)) ||
developer3262bf82022-07-12 11:37:54 +08002655@@ -643,6 +821,15 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg,
developer42b63282022-06-16 13:33:13 +08002656 nla_put_u8(msg, MT76_TM_ATTR_FREQ_OFFSET, td->freq_offset)))
2657 goto out;
2658
2659+ if (nla_put_u32(msg, MT76_TM_ATTR_TX_LENGTH, ed->tx_mpdu_len) ||
2660+ nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_NSS, ed->tx_rate_nss) ||
2661+ nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_IDX, ed->tx_rate_idx) ||
2662+ nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_LDPC, ed->tx_rate_ldpc) ||
2663+ nla_put_u8(msg, MT76_TM_ATTR_AID, ed->aid) ||
2664+ nla_put_u8(msg, MT76_TM_ATTR_RU_ALLOC, ed->ru_alloc) ||
2665+ nla_put_u8(msg, MT76_TM_ATTR_RU_IDX, ed->ru_idx))
2666+ goto out;
2667+
2668 if (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_POWER)) {
2669 a = nla_nest_start(msg, MT76_TM_ATTR_TX_POWER);
2670 if (!a)
2671diff --git a/testmode.h b/testmode.h
developer3262bf82022-07-12 11:37:54 +08002672index 89613266..57949f2b 100644
developer42b63282022-06-16 13:33:13 +08002673--- a/testmode.h
2674+++ b/testmode.h
2675@@ -6,6 +6,8 @@
2676 #define __MT76_TESTMODE_H
2677
2678 #define MT76_TM_TIMEOUT 10
2679+#define MT76_TM_MAX_ENTRY_NUM 16
2680+#define MT76_TM_EEPROM_BLOCK_SIZE 16
2681
2682 /**
2683 * enum mt76_testmode_attr - testmode attributes inside NL80211_ATTR_TESTDATA
2684@@ -47,6 +49,15 @@
2685 * @MT76_TM_ATTR_DRV_DATA: driver specific netlink attrs (nested)
2686 *
2687 * @MT76_TM_ATTR_MAC_ADDRS: array of nested MAC addresses (nested)
2688+ *
2689+ * @MT76_TM_ATTR_EEPROM_ACTION: eeprom setting actions
2690+ * (u8, see &enum mt76_testmode_eeprom_action)
2691+ * @MT76_TM_ATTR_EEPROM_OFFSET: offset of eeprom data block for writing (u32)
2692+ * @MT76_TM_ATTR_EEPROM_VAL: values for writing into a 16-byte data block
2693+ * (nested, u8 attrs)
2694+ *
2695+ * @MT76_TM_ATTR_CFG: config testmode rf feature (nested, see &mt76_testmode_cfg)
2696+ *
2697 */
2698 enum mt76_testmode_attr {
2699 MT76_TM_ATTR_UNSPEC,
2700@@ -84,6 +95,17 @@ enum mt76_testmode_attr {
2701 MT76_TM_ATTR_DRV_DATA,
2702
2703 MT76_TM_ATTR_MAC_ADDRS,
2704+ MT76_TM_ATTR_AID,
2705+ MT76_TM_ATTR_RU_ALLOC,
2706+ MT76_TM_ATTR_RU_IDX,
2707+
2708+ MT76_TM_ATTR_EEPROM_ACTION,
2709+ MT76_TM_ATTR_EEPROM_OFFSET,
2710+ MT76_TM_ATTR_EEPROM_VAL,
2711+
2712+ MT76_TM_ATTR_CFG,
2713+ MT76_TM_ATTR_TXBF_ACT,
2714+ MT76_TM_ATTR_TXBF_PARAM,
2715
2716 /* keep last */
2717 NUM_MT76_TM_ATTRS,
2718@@ -198,4 +220,57 @@ enum mt76_testmode_tx_mode {
2719
2720 extern const struct nla_policy mt76_tm_policy[NUM_MT76_TM_ATTRS];
2721
2722+/**
2723+ * enum mt76_testmode_eeprom_action - eeprom setting actions
2724+ *
2725+ * @MT76_TM_EEPROM_ACTION_UPDATE_DATA: update rf values to specific
2726+ * eeprom data block
2727+ * @MT76_TM_EEPROM_ACTION_UPDATE_BUFFER_MODE: send updated eeprom data to fw
2728+ * @MT76_TM_EEPROM_ACTION_WRITE_TO_EFUSE: write eeprom data back to efuse
2729+ */
2730+enum mt76_testmode_eeprom_action {
2731+ MT76_TM_EEPROM_ACTION_UPDATE_DATA,
2732+ MT76_TM_EEPROM_ACTION_UPDATE_BUFFER_MODE,
2733+ MT76_TM_EEPROM_ACTION_WRITE_TO_EFUSE,
2734+
2735+ /* keep last */
2736+ NUM_MT76_TM_EEPROM_ACTION,
2737+ MT76_TM_EEPROM_ACTION_MAX = NUM_MT76_TM_EEPROM_ACTION - 1,
2738+};
2739+
2740+/**
2741+ * enum mt76_testmode_cfg - packet tx phy mode
2742+ *
2743+ * @MT76_TM_EEPROM_ACTION_UPDATE_DATA: update rf values to specific
2744+ * eeprom data block
2745+ * @MT76_TM_EEPROM_ACTION_UPDATE_BUFFER_MODE: send updated eeprom data to fw
2746+ * @MT76_TM_EEPROM_ACTION_WRITE_TO_EFUSE: write eeprom data back to efuse
2747+ */
2748+enum mt76_testmode_cfg {
2749+ MT76_TM_CFG_TSSI,
2750+ MT76_TM_CFG_DPD,
2751+ MT76_TM_CFG_RATE_POWER_OFFSET,
2752+ MT76_TM_CFG_THERMAL_COMP,
2753+
2754+ /* keep last */
2755+ NUM_MT76_TM_CFG,
2756+ MT76_TM_CFG_MAX = NUM_MT76_TM_CFG - 1,
2757+};
2758+
2759+enum mt76_testmode_txbf_act {
2760+ MT76_TM_TXBF_ACT_INIT,
2761+ MT76_TM_TXBF_ACT_UPDATE_CH,
2762+ MT76_TM_TXBF_ACT_PHASE_COMP,
2763+ MT76_TM_TXBF_ACT_TX_PREP,
2764+ MT76_TM_TXBF_ACT_IBF_PROF_UPDATE,
2765+ MT76_TM_TXBF_ACT_EBF_PROF_UPDATE,
2766+ MT76_TM_TXBF_ACT_PHASE_CAL,
2767+ MT76_TM_TXBF_ACT_PROF_UPDATE_ALL,
2768+ MT76_TM_TXBF_ACT_E2P_UPDATE,
2769+
2770+ /* keep last */
2771+ NUM_MT76_TM_TXBF_ACT,
2772+ MT76_TM_TXBF_ACT_MAX = NUM_MT76_TM_TXBF_ACT - 1,
2773+};
2774+
2775 #endif
2776diff --git a/tools/fields.c b/tools/fields.c
developer3262bf82022-07-12 11:37:54 +08002777index e3f69089..6e36ab27 100644
developer42b63282022-06-16 13:33:13 +08002778--- a/tools/fields.c
2779+++ b/tools/fields.c
2780@@ -10,6 +10,7 @@ static const char * const testmode_state[] = {
2781 [MT76_TM_STATE_IDLE] = "idle",
2782 [MT76_TM_STATE_TX_FRAMES] = "tx_frames",
2783 [MT76_TM_STATE_RX_FRAMES] = "rx_frames",
2784+ [MT76_TM_STATE_TX_CONT] = "tx_cont",
2785 };
2786
2787 static const char * const testmode_tx_mode[] = {
2788@@ -201,6 +202,63 @@ static void print_extra_stats(const struct tm_field *field, struct nlattr **tb)
2789 printf("%srx_per=%.02f%%\n", prefix, 100 * failed / total);
2790 }
2791
2792+static bool parse_mac(const struct tm_field *field, int idx,
2793+ struct nl_msg *msg, const char *val)
2794+{
2795+#define ETH_ALEN 6
2796+ bool ret = true;
2797+ char *str, *cur, *ap;
2798+ void *a;
2799+
2800+ ap = str = strdup(val);
2801+
2802+ a = nla_nest_start(msg, idx);
2803+
2804+ idx = 0;
2805+ while ((cur = strsep(&ap, ",")) != NULL) {
2806+ unsigned char addr[ETH_ALEN];
2807+ char *val, *tmp = cur;
2808+ int i = 0;
2809+
2810+ while ((val = strsep(&tmp, ":")) != NULL) {
2811+ if (i >= ETH_ALEN)
2812+ break;
2813+
2814+ addr[i++] = strtoul(val, NULL, 16);
2815+ }
2816+
2817+ nla_put(msg, idx, ETH_ALEN, addr);
2818+
2819+ idx++;
2820+ }
2821+
2822+ nla_nest_end(msg, a);
2823+
2824+ free(str);
2825+
2826+ return ret;
2827+}
2828+
2829+static void print_mac(const struct tm_field *field, struct nlattr *attr)
2830+{
2831+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
2832+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
2833+ unsigned char addr[3][6];
2834+ struct nlattr *cur;
2835+ int idx = 0;
2836+ int rem;
2837+
2838+ nla_for_each_nested(cur, attr, rem) {
2839+ if (nla_len(cur) != 6)
2840+ continue;
2841+ memcpy(addr[idx++], nla_data(cur), 6);
2842+ }
2843+
2844+ printf("" MACSTR "," MACSTR "," MACSTR "",
2845+ MAC2STR(addr[0]), MAC2STR(addr[1]), MAC2STR(addr[2]));
2846+
2847+ return;
2848+}
2849
2850 #define FIELD_GENERIC(_field, _name, ...) \
2851 [FIELD_NAME(_field)] = { \
2852@@ -250,6 +308,13 @@ static void print_extra_stats(const struct tm_field *field, struct nlattr **tb)
2853 ##__VA_ARGS__ \
2854 )
2855
2856+#define FIELD_MAC(_field, _name) \
2857+ [FIELD_NAME(_field)] = { \
2858+ .name = _name, \
2859+ .parse = parse_mac, \
2860+ .print = print_mac \
2861+ }
2862+
2863 #define FIELD_NAME(_field) MT76_TM_RX_ATTR_##_field
2864 static const struct tm_field rx_fields[NUM_MT76_TM_RX_ATTRS] = {
2865 FIELD_RO(s32, FREQ_OFFSET, "freq_offset"),
2866@@ -300,10 +365,18 @@ static const struct tm_field testdata_fields[NUM_MT76_TM_ATTRS] = {
2867 FIELD(u8, TX_RATE_LDPC, "tx_rate_ldpc"),
2868 FIELD(u8, TX_RATE_STBC, "tx_rate_stbc"),
2869 FIELD(u8, TX_LTF, "tx_ltf"),
2870+ FIELD(u8, TX_DUTY_CYCLE, "tx_duty_cycle"),
2871+ FIELD(u32, TX_IPG, "tx_ipg"),
2872+ FIELD(u32, TX_TIME, "tx_time"),
2873 FIELD(u8, TX_POWER_CONTROL, "tx_power_control"),
2874 FIELD_ARRAY(u8, TX_POWER, "tx_power"),
2875 FIELD(u8, TX_ANTENNA, "tx_antenna"),
2876+ FIELD(u8, TX_SPE_IDX, "tx_spe_idx"),
2877 FIELD(u32, FREQ_OFFSET, "freq_offset"),
2878+ FIELD(u8, AID, "aid"),
2879+ FIELD(u8, RU_ALLOC, "ru_alloc"),
2880+ FIELD(u8, RU_IDX, "ru_idx"),
2881+ FIELD_MAC(MAC_ADDRS, "mac_addrs"),
2882 FIELD_NESTED_RO(STATS, stats, "",
2883 .print_extra = print_extra_stats),
2884 };
2885@@ -322,9 +395,16 @@ static struct nla_policy testdata_policy[NUM_MT76_TM_ATTRS] = {
2886 [MT76_TM_ATTR_TX_RATE_LDPC] = { .type = NLA_U8 },
2887 [MT76_TM_ATTR_TX_RATE_STBC] = { .type = NLA_U8 },
2888 [MT76_TM_ATTR_TX_LTF] = { .type = NLA_U8 },
2889+ [MT76_TM_ATTR_TX_DUTY_CYCLE] = { .type = NLA_U8 },
2890+ [MT76_TM_ATTR_TX_IPG] = { .type = NLA_U32 },
2891+ [MT76_TM_ATTR_TX_TIME] = { .type = NLA_U32 },
2892 [MT76_TM_ATTR_TX_POWER_CONTROL] = { .type = NLA_U8 },
2893 [MT76_TM_ATTR_TX_ANTENNA] = { .type = NLA_U8 },
2894+ [MT76_TM_ATTR_TX_SPE_IDX] = { .type = NLA_U8 },
2895 [MT76_TM_ATTR_FREQ_OFFSET] = { .type = NLA_U32 },
2896+ [MT76_TM_ATTR_AID] = { .type = NLA_U8 },
2897+ [MT76_TM_ATTR_RU_ALLOC] = { .type = NLA_U8 },
2898+ [MT76_TM_ATTR_RU_IDX] = { .type = NLA_U8 },
2899 [MT76_TM_ATTR_STATS] = { .type = NLA_NESTED },
2900 };
2901
2902diff --git a/tx.c b/tx.c
developer3262bf82022-07-12 11:37:54 +08002903index 6c8d50d3..ae44afe0 100644
developer42b63282022-06-16 13:33:13 +08002904--- a/tx.c
2905+++ b/tx.c
2906@@ -245,8 +245,7 @@ void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid_idx, struct sk_buff *
2907 if (mt76_is_testmode_skb(dev, skb, &hw)) {
2908 struct mt76_phy *phy = hw->priv;
2909
2910- if (skb == phy->test.tx_skb)
2911- phy->test.tx_done++;
2912+ phy->test.tx_done++;
2913 if (phy->test.tx_queued == phy->test.tx_done)
2914 wake_up(&dev->tx_wait);
2915
2916--
developeraace7f52022-06-24 13:40:42 +080029172.18.0
developer42b63282022-06-16 13:33:13 +08002918