blob: 1ad2d4af8e716dc606cf100439683de78d497074 [file] [log] [blame]
developere35b8e42023-10-16 11:04:00 +08001From db7a7f8f00bf19913b153a377a7808900bafeb20 Mon Sep 17 00:00:00 2001
developer6a1998b2022-12-08 18:09:45 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Mon, 6 Jun 2022 19:46:26 +0800
developere35b8e42023-10-16 11:04:00 +08004Subject: [PATCH 1008/1040] wifi: mt76: testmode: rework testmode init
developer78848c62023-04-06 13:44:00 +08005 registers
developer6a1998b2022-12-08 18:09:45 +08006
7---
8 mac80211.c | 3 +-
9 mt76.h | 5 ++
10 mt76_connac_mcu.h | 1 +
11 mt7915/mcu.h | 1 +
12 mt7915/mmio.c | 2 +
13 mt7915/regs.h | 16 +++++-
14 mt7915/testmode.c | 134 +++++++++++++++++++++++++++++++++++-----------
15 mt7915/testmode.h | 28 ++++++++++
16 testmode.c | 6 ++-
17 testmode.h | 3 ++
18 10 files changed, 164 insertions(+), 35 deletions(-)
19
20diff --git a/mac80211.c b/mac80211.c
developere35b8e42023-10-16 11:04:00 +080021index 647f74c..430ed1c 100644
developer6a1998b2022-12-08 18:09:45 +080022--- a/mac80211.c
23+++ b/mac80211.c
developere35b8e42023-10-16 11:04:00 +080024@@ -793,7 +793,8 @@ void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb)
developer6a1998b2022-12-08 18:09:45 +080025 }
26
27 #ifdef CONFIG_NL80211_TESTMODE
28- if (phy->test.state == MT76_TM_STATE_RX_FRAMES) {
29+ if (!(phy->test.flag & MT_TM_FW_RX_COUNT) &&
30+ phy->test.state == MT76_TM_STATE_RX_FRAMES) {
31 phy->test.rx_stats.packets[q]++;
32 if (status->flag & RX_FLAG_FAILED_FCS_CRC)
33 phy->test.rx_stats.fcs_error[q]++;
34diff --git a/mt76.h b/mt76.h
developere35b8e42023-10-16 11:04:00 +080035index 97ced84..d66f4d0 100644
developer6a1998b2022-12-08 18:09:45 +080036--- a/mt76.h
37+++ b/mt76.h
developere35b8e42023-10-16 11:04:00 +080038@@ -672,6 +672,8 @@ struct mt76_testmode_ops {
developer6a1998b2022-12-08 18:09:45 +080039 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
40 };
41
42+#define MT_TM_FW_RX_COUNT BIT(0)
43+
44 struct mt76_testmode_data {
45 enum mt76_testmode_state state;
46
developere35b8e42023-10-16 11:04:00 +080047@@ -703,6 +705,8 @@ struct mt76_testmode_data {
developer6a1998b2022-12-08 18:09:45 +080048
49 u8 addr[3][ETH_ALEN];
50
51+ u8 flag;
52+
53 u32 tx_pending;
54 u32 tx_queued;
55 u16 tx_queued_limit;
developere35b8e42023-10-16 11:04:00 +080056@@ -710,6 +714,7 @@ struct mt76_testmode_data {
developer6a1998b2022-12-08 18:09:45 +080057 struct {
58 u64 packets[__MT_RXQ_MAX];
59 u64 fcs_error[__MT_RXQ_MAX];
60+ u64 len_mismatch;
61 } rx_stats;
62 };
63
64diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developere35b8e42023-10-16 11:04:00 +080065index 9b065f3..cb68141 100644
developer6a1998b2022-12-08 18:09:45 +080066--- a/mt76_connac_mcu.h
67+++ b/mt76_connac_mcu.h
developere35b8e42023-10-16 11:04:00 +080068@@ -1204,6 +1204,7 @@ enum {
developer6a1998b2022-12-08 18:09:45 +080069 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
70 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
71 MCU_EXT_CMD_MURU_CTRL = 0x9f,
72+ MCU_EXT_CMD_RX_STAT = 0xa4,
73 MCU_EXT_CMD_SET_SPR = 0xa8,
74 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
75 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
76diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developere35b8e42023-10-16 11:04:00 +080077index b6e2136..c15b4b7 100644
developer6a1998b2022-12-08 18:09:45 +080078--- a/mt7915/mcu.h
79+++ b/mt7915/mcu.h
80@@ -9,6 +9,7 @@
81 enum {
82 MCU_ATE_SET_TRX = 0x1,
83 MCU_ATE_SET_FREQ_OFFSET = 0xa,
84+ MCU_ATE_SET_PHY_COUNT = 0x11,
85 MCU_ATE_SET_SLOT_TIME = 0x13,
86 MCU_ATE_CLEAN_TXQUEUE = 0x1c,
87 };
88diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developere35b8e42023-10-16 11:04:00 +080089index 10f4e66..10c2c7d 100644
developer6a1998b2022-12-08 18:09:45 +080090--- a/mt7915/mmio.c
91+++ b/mt7915/mmio.c
developerf3f5d9b2023-02-07 15:24:34 +080092@@ -120,6 +120,7 @@ static const u32 mt7986_reg[] = {
developer6a1998b2022-12-08 18:09:45 +080093 };
94
95 static const u32 mt7915_offs[] = {
96+ [TMAC_TCR2] = 0x05c,
97 [TMAC_CDTR] = 0x090,
98 [TMAC_ODTR] = 0x094,
99 [TMAC_ATCR] = 0x098,
developerf3f5d9b2023-02-07 15:24:34 +0800100@@ -194,6 +195,7 @@ static const u32 mt7915_offs[] = {
developer6a1998b2022-12-08 18:09:45 +0800101 };
102
103 static const u32 mt7916_offs[] = {
104+ [TMAC_TCR2] = 0x004,
105 [TMAC_CDTR] = 0x0c8,
106 [TMAC_ODTR] = 0x0cc,
107 [TMAC_ATCR] = 0x00c,
108diff --git a/mt7915/regs.h b/mt7915/regs.h
developere35b8e42023-10-16 11:04:00 +0800109index 7515b23..2a9e50b 100644
developer6a1998b2022-12-08 18:09:45 +0800110--- a/mt7915/regs.h
111+++ b/mt7915/regs.h
112@@ -48,6 +48,7 @@ enum reg_rev {
113 };
114
115 enum offs_rev {
116+ TMAC_TCR2,
117 TMAC_CDTR,
118 TMAC_ODTR,
119 TMAC_ATCR,
developere35b8e42023-10-16 11:04:00 +0800120@@ -202,6 +203,12 @@ enum offs_rev {
developer6a1998b2022-12-08 18:09:45 +0800121 #define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16)
122 #define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0)
123
124+#define MT_MDP_TOP_DBG_WDT_CTRL MT_MDP(0x0d0)
125+#define MT_MDP_TOP_DBG_WDT_CTRL_TDP_DIS_BLK BIT(7)
126+
127+#define MT_MDP_TOP_DBG_CTRL MT_MDP(0x0dc)
128+#define MT_MDP_TOP_DBG_CTRL_ENQ_MODE BIT(30)
129+
130 /* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
131 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
132 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
developere35b8e42023-10-16 11:04:00 +0800133@@ -210,6 +217,9 @@ enum offs_rev {
developer6a1998b2022-12-08 18:09:45 +0800134 #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)
135 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
136
137+#define MT_TMAC_TCR2(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TCR2))
138+#define MT_TMAC_TCR2_SCH_DET_DIS BIT(19)
139+
140 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR))
141 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR))
142 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
developere35b8e42023-10-16 11:04:00 +0800143@@ -489,8 +499,10 @@ enum offs_rev {
developer6a1998b2022-12-08 18:09:45 +0800144 #define MT_AGG_PCR0_VHT_PROT BIT(13)
145 #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15)
146
147-#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23)
148-#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
149+#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23)
150+#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
151+#define MT_AGG_PCR1_RTS0_NUM_THRES_MT7916 GENMASK(29, 24)
152+#define MT_AGG_PCR1_RTS0_LEN_THRES_MT7916 GENMASK(22, 0)
153
154 #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR0))
155 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
156diff --git a/mt7915/testmode.c b/mt7915/testmode.c
developere35b8e42023-10-16 11:04:00 +0800157index 0d76ae3..4693919 100644
developer6a1998b2022-12-08 18:09:45 +0800158--- a/mt7915/testmode.c
159+++ b/mt7915/testmode.c
160@@ -30,7 +30,7 @@ struct reg_band {
161 { _list.band[0] = MT_##_reg(0, _idx); \
162 _list.band[1] = MT_##_reg(1, _idx); }
163
164-#define TM_REG_MAX_ID 17
165+#define TM_REG_MAX_ID 20
166 static struct reg_band reg_backup_list[TM_REG_MAX_ID];
167
168
169@@ -133,6 +133,21 @@ mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid)
170 sizeof(req), false);
171 }
172
173+static int
174+mt7915_tm_set_phy_count(struct mt7915_phy *phy, u8 control)
175+{
176+ struct mt7915_dev *dev = phy->dev;
177+ struct mt7915_tm_cmd req = {
178+ .testmode_en = 1,
179+ .param_idx = MCU_ATE_SET_PHY_COUNT,
180+ .param.cfg.enable = control,
181+ .param.cfg.band = phy != &dev->phy,
182+ };
183+
184+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
185+ sizeof(req), false);
186+}
187+
188 static int
189 mt7915_tm_set_slot_time(struct mt7915_phy *phy, u8 slot_time, u8 sifs)
190 {
developer79e690d2022-12-13 17:05:25 +0800191@@ -336,7 +351,7 @@ mt7915_tm_reg_backup_restore(struct mt7915_phy *phy)
developer6a1998b2022-12-08 18:09:45 +0800192 {
193 int n_regs = ARRAY_SIZE(reg_backup_list);
194 struct mt7915_dev *dev = phy->dev;
195- u32 *b = phy->test.reg_backup;
196+ u32 *b = phy->test.reg_backup, val;
developer79e690d2022-12-13 17:05:25 +0800197 u8 band = phy->mt76->band_idx;
developer6a1998b2022-12-08 18:09:45 +0800198 int i;
199
developer79e690d2022-12-13 17:05:25 +0800200@@ -349,18 +364,28 @@ mt7915_tm_reg_backup_restore(struct mt7915_phy *phy)
developer6a1998b2022-12-08 18:09:45 +0800201 REG_BAND(reg_backup_list[6], AGG_MRCR);
202 REG_BAND(reg_backup_list[7], TMAC_TFCR0);
203 REG_BAND(reg_backup_list[8], TMAC_TCR0);
204- REG_BAND(reg_backup_list[9], AGG_ATCR1);
205- REG_BAND(reg_backup_list[10], AGG_ATCR3);
206- REG_BAND(reg_backup_list[11], TMAC_TRCR0);
207- REG_BAND(reg_backup_list[12], TMAC_ICR0);
208- REG_BAND_IDX(reg_backup_list[13], ARB_DRNGR0, 0);
209- REG_BAND_IDX(reg_backup_list[14], ARB_DRNGR0, 1);
210- REG_BAND(reg_backup_list[15], WF_RFCR);
211- REG_BAND(reg_backup_list[16], WF_RFCR1);
212+ REG_BAND(reg_backup_list[9], TMAC_TCR2);
213+ REG_BAND(reg_backup_list[10], AGG_ATCR1);
214+ REG_BAND(reg_backup_list[11], AGG_ATCR3);
215+ REG_BAND(reg_backup_list[12], TMAC_TRCR0);
216+ REG_BAND(reg_backup_list[13], TMAC_ICR0);
217+ REG_BAND_IDX(reg_backup_list[14], ARB_DRNGR0, 0);
218+ REG_BAND_IDX(reg_backup_list[15], ARB_DRNGR0, 1);
219+ REG_BAND(reg_backup_list[16], WF_RFCR);
220+ REG_BAND(reg_backup_list[17], WF_RFCR1);
221+
222+ if (is_mt7916(&dev->mt76)) {
developer79e690d2022-12-13 17:05:25 +0800223+ reg_backup_list[18].band[band] = MT_MDP_TOP_DBG_WDT_CTRL;
224+ reg_backup_list[19].band[band] = MT_MDP_TOP_DBG_CTRL;
developer6a1998b2022-12-08 18:09:45 +0800225+ }
226
227 if (phy->mt76->test.state == MT76_TM_STATE_OFF) {
228- for (i = 0; i < n_regs; i++)
developer79e690d2022-12-13 17:05:25 +0800229- mt76_wr(dev, reg_backup_list[i].band[band], b[i]);
developer6a1998b2022-12-08 18:09:45 +0800230+ for (i = 0; i < n_regs; i++) {
developer79e690d2022-12-13 17:05:25 +0800231+ u8 reg = reg_backup_list[i].band[band];
developer6a1998b2022-12-08 18:09:45 +0800232+
233+ if (reg)
234+ mt76_wr(dev, reg, b[i]);
235+ }
236 return;
237 }
238
developer79e690d2022-12-13 17:05:25 +0800239@@ -380,8 +405,13 @@ mt7915_tm_reg_backup_restore(struct mt7915_phy *phy)
developer6a1998b2022-12-08 18:09:45 +0800240 MT_AGG_PCR0_BW40_PROT | MT_AGG_PCR0_BW80_PROT);
developer79e690d2022-12-13 17:05:25 +0800241 mt76_set(dev, MT_AGG_PCR0(band, 0), MT_AGG_PCR0_PTA_WIN_DIS);
developer6a1998b2022-12-08 18:09:45 +0800242
developer79e690d2022-12-13 17:05:25 +0800243- mt76_wr(dev, MT_AGG_PCR0(band, 1), MT_AGG_PCR1_RTS0_NUM_THRES |
developer6a1998b2022-12-08 18:09:45 +0800244- MT_AGG_PCR1_RTS0_LEN_THRES);
245+ if (is_mt7915(&dev->mt76))
246+ val = MT_AGG_PCR1_RTS0_NUM_THRES | MT_AGG_PCR1_RTS0_LEN_THRES;
247+ else
248+ val = MT_AGG_PCR1_RTS0_NUM_THRES_MT7916 |
249+ MT_AGG_PCR1_RTS0_LEN_THRES_MT7916;
250+
developer79e690d2022-12-13 17:05:25 +0800251+ mt76_wr(dev, MT_AGG_PCR0(band, 1), val);
developer6a1998b2022-12-08 18:09:45 +0800252
developer79e690d2022-12-13 17:05:25 +0800253 mt76_clear(dev, MT_AGG_MRCR(band), MT_AGG_MRCR_BAR_CNT_LIMIT |
developer6a1998b2022-12-08 18:09:45 +0800254 MT_AGG_MRCR_LAST_RTS_CTS_RN | MT_AGG_MRCR_RTS_FAIL_LIMIT |
developer79e690d2022-12-13 17:05:25 +0800255@@ -394,10 +424,19 @@ mt7915_tm_reg_backup_restore(struct mt7915_phy *phy)
developer6a1998b2022-12-08 18:09:45 +0800256
developer79e690d2022-12-13 17:05:25 +0800257 mt76_wr(dev, MT_TMAC_TFCR0(band), 0);
258 mt76_clear(dev, MT_TMAC_TCR0(band), MT_TMAC_TCR0_TBTT_STOP_CTRL);
259+ mt76_set(dev, MT_TMAC_TCR2(band), MT_TMAC_TCR2_SCH_DET_DIS);
developer6a1998b2022-12-08 18:09:45 +0800260
261 /* config rx filter for testmode rx */
developer79e690d2022-12-13 17:05:25 +0800262 mt76_wr(dev, MT_WF_RFCR(band), 0xcf70a);
263 mt76_wr(dev, MT_WF_RFCR1(band), 0);
developer6a1998b2022-12-08 18:09:45 +0800264+
265+ if (is_mt7916(&dev->mt76)) {
266+ /* enable MDP Tx block mode */
267+ mt76_clear(dev, MT_MDP_TOP_DBG_WDT_CTRL,
268+ MT_MDP_TOP_DBG_WDT_CTRL_TDP_DIS_BLK);
269+ mt76_clear(dev, MT_MDP_TOP_DBG_CTRL,
270+ MT_MDP_TOP_DBG_CTRL_ENQ_MODE);
271+ }
272 }
273
274 static void
developer79e690d2022-12-13 17:05:25 +0800275@@ -417,6 +456,8 @@ mt7915_tm_init(struct mt7915_phy *phy, bool en)
developer6a1998b2022-12-08 18:09:45 +0800276 mt7915_mcu_add_bss_info(phy, phy->monitor_vif, en);
277 mt7915_mcu_add_sta(dev, phy->monitor_vif, NULL, en);
278
279+ phy->mt76->test.flag |= MT_TM_FW_RX_COUNT;
280+
281 if (!en)
282 mt7915_tm_set_tam_arb(phy, en, 0);
283 }
developer79e690d2022-12-13 17:05:25 +0800284@@ -479,18 +520,63 @@ mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
developer6a1998b2022-12-08 18:09:45 +0800285 mt7915_tm_set_trx(phy, TM_MAC_TX, en);
286 }
287
288+static int
289+mt7915_tm_get_rx_stats(struct mt7915_phy *phy, bool clear)
290+{
291+#define CMD_RX_STAT_BAND 0x3
292+ struct mt76_testmode_data *td = &phy->mt76->test;
293+ struct mt7915_tm_rx_stat_band *rs_band;
294+ struct mt7915_dev *dev = phy->dev;
295+ struct sk_buff *skb;
296+ struct {
297+ u8 format_id;
298+ u8 band;
299+ u8 _rsv[2];
300+ } __packed req = {
301+ .format_id = CMD_RX_STAT_BAND,
developer79e690d2022-12-13 17:05:25 +0800302+ .band = phy->mt76->band_idx,
developer6a1998b2022-12-08 18:09:45 +0800303+ };
304+ int ret;
305+
306+ ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_EXT_CMD(RX_STAT),
307+ &req, sizeof(req), true, &skb);
308+ if (ret)
309+ return ret;
310+
311+ rs_band = (struct mt7915_tm_rx_stat_band *)skb->data;
312+ /* pr_info("mdrdy_cnt = %d\n", le32_to_cpu(rs_band->mdrdy_cnt)); */
313+ /* pr_info("fcs_err = %d\n", le16_to_cpu(rs_band->fcs_err)); */
314+ /* pr_info("len_mismatch = %d\n", le16_to_cpu(rs_band->len_mismatch)); */
315+ /* pr_info("fcs_ok = %d\n", le16_to_cpu(rs_band->fcs_succ)); */
316+
317+ if (!clear) {
318+ enum mt76_rxq_id q = req.band ? MT_RXQ_BAND1 : MT_RXQ_MAIN;
319+
320+ td->rx_stats.packets[q] += le32_to_cpu(rs_band->mdrdy_cnt);
321+ td->rx_stats.fcs_error[q] += le16_to_cpu(rs_band->fcs_err);
322+ td->rx_stats.len_mismatch += le16_to_cpu(rs_band->len_mismatch);
323+ }
324+
325+ dev_kfree_skb(skb);
326+
327+ return 0;
328+}
329+
330 static void
331 mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
332 {
333 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
334
335 if (en) {
336- struct mt7915_dev *dev = phy->dev;
337-
338 mt7915_tm_update_channel(phy);
339
340 /* read-clear */
developer79e690d2022-12-13 17:05:25 +0800341- mt76_rr(dev, MT_MIB_SDR3(phy->mt76->band_idx));
developer6a1998b2022-12-08 18:09:45 +0800342+ mt7915_tm_get_rx_stats(phy, true);
343+
344+ /* clear fw count */
345+ mt7915_tm_set_phy_count(phy, 0);
346+ mt7915_tm_set_phy_count(phy, 1);
347+
348 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
349 }
350 }
developer79e690d2022-12-13 17:05:25 +0800351@@ -721,12 +807,8 @@ static int
developer6a1998b2022-12-08 18:09:45 +0800352 mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
353 {
354 struct mt7915_phy *phy = mphy->priv;
355- struct mt7915_dev *dev = phy->dev;
356- enum mt76_rxq_id q;
357 void *rx, *rssi;
358- u16 fcs_err;
359 int i;
360- u32 cnt;
361
362 rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX);
363 if (!rx)
developer79e690d2022-12-13 17:05:25 +0800364@@ -770,15 +852,7 @@ mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
developer6a1998b2022-12-08 18:09:45 +0800365
366 nla_nest_end(msg, rx);
367
developer79e690d2022-12-13 17:05:25 +0800368- cnt = mt76_rr(dev, MT_MIB_SDR3(phy->mt76->band_idx));
developer6a1998b2022-12-08 18:09:45 +0800369- fcs_err = is_mt7915(&dev->mt76) ? FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) :
370- FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt);
371-
developer79e690d2022-12-13 17:05:25 +0800372- q = phy->mt76->band_idx ? MT_RXQ_BAND1 : MT_RXQ_MAIN;
developer6a1998b2022-12-08 18:09:45 +0800373- mphy->test.rx_stats.packets[q] += fcs_err;
374- mphy->test.rx_stats.fcs_error[q] += fcs_err;
375-
376- return 0;
377+ return mt7915_tm_get_rx_stats(phy, false);
378 }
379
380 const struct mt76_testmode_ops mt7915_testmode_ops = {
381diff --git a/mt7915/testmode.h b/mt7915/testmode.h
developere35b8e42023-10-16 11:04:00 +0800382index 5573ac3..a1c54c8 100644
developer6a1998b2022-12-08 18:09:45 +0800383--- a/mt7915/testmode.h
384+++ b/mt7915/testmode.h
385@@ -33,6 +33,12 @@ struct mt7915_tm_clean_txq {
386 u8 rsv;
387 };
388
389+struct mt7915_tm_cfg {
390+ u8 enable;
391+ u8 band;
392+ u8 _rsv[2];
393+};
394+
395 struct mt7915_tm_cmd {
396 u8 testmode_en;
397 u8 param_idx;
398@@ -43,6 +49,7 @@ struct mt7915_tm_cmd {
399 struct mt7915_tm_freq_offset freq;
400 struct mt7915_tm_slot_time slot;
401 struct mt7915_tm_clean_txq clean;
402+ struct mt7915_tm_cfg cfg;
403 u8 test[72];
404 } param;
405 } __packed;
406@@ -102,4 +109,25 @@ enum {
407 TAM_ARB_OP_MODE_FORCE_SU = 5,
408 };
409
410+struct mt7915_tm_rx_stat_band {
411+ u8 category;
412+
413+ /* mac */
414+ __le16 fcs_err;
415+ __le16 len_mismatch;
416+ __le16 fcs_succ;
417+ __le32 mdrdy_cnt;
418+ /* phy */
419+ __le16 fcs_err_cck;
420+ __le16 fcs_err_ofdm;
421+ __le16 pd_cck;
422+ __le16 pd_ofdm;
423+ __le16 sig_err_cck;
424+ __le16 sfd_err_cck;
425+ __le16 sig_err_ofdm;
426+ __le16 tag_err_ofdm;
427+ __le16 mdrdy_cnt_cck;
428+ __le16 mdrdy_cnt_ofdm;
429+};
430+
431 #endif
432diff --git a/testmode.c b/testmode.c
developere35b8e42023-10-16 11:04:00 +0800433index 4644dac..1b37392 100644
developer6a1998b2022-12-08 18:09:45 +0800434--- a/testmode.c
435+++ b/testmode.c
developer2b96a9e2023-08-09 10:28:15 +0800436@@ -448,8 +448,7 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer6a1998b2022-12-08 18:09:45 +0800437 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_LDPC], &td->tx_rate_ldpc, 0, 1) ||
438 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_STBC], &td->tx_rate_stbc, 0, 1) ||
439 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_LTF], &td->tx_ltf, 0, 2) ||
440- mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_ANTENNA],
441- &td->tx_antenna_mask, 0, 0xff) ||
442+ mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_ANTENNA], &td->tx_antenna_mask, 1, 0xff) ||
443 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_SPE_IDX], &td->tx_spe_idx, 0, 27) ||
444 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_DUTY_CYCLE],
445 &td->tx_duty_cycle, 0, 99) ||
developer2b96a9e2023-08-09 10:28:15 +0800446@@ -561,6 +560,9 @@ mt76_testmode_dump_stats(struct mt76_phy *phy, struct sk_buff *msg)
developer6a1998b2022-12-08 18:09:45 +0800447 nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_PACKETS, rx_packets,
448 MT76_TM_STATS_ATTR_PAD) ||
449 nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_FCS_ERROR, rx_fcs_error,
450+ MT76_TM_STATS_ATTR_PAD) ||
451+ nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_LEN_MISMATCH,
452+ td->rx_stats.len_mismatch,
453 MT76_TM_STATS_ATTR_PAD))
454 return -EMSGSIZE;
455
456diff --git a/testmode.h b/testmode.h
developere35b8e42023-10-16 11:04:00 +0800457index 5e2792d..8961326 100644
developer6a1998b2022-12-08 18:09:45 +0800458--- a/testmode.h
459+++ b/testmode.h
460@@ -101,6 +101,8 @@ enum mt76_testmode_attr {
461 * @MT76_TM_STATS_ATTR_RX_FCS_ERROR: number of rx packets with FCS error (u64)
462 * @MT76_TM_STATS_ATTR_LAST_RX: information about the last received packet
463 * see &enum mt76_testmode_rx_attr
464+ * @MT76_TM_STATS_ATTR_RX_LEN_MISMATCH: number of rx packets with length
465+ * mismatch error (u64)
466 */
467 enum mt76_testmode_stats_attr {
468 MT76_TM_STATS_ATTR_UNSPEC,
469@@ -113,6 +115,7 @@ enum mt76_testmode_stats_attr {
470 MT76_TM_STATS_ATTR_RX_PACKETS,
471 MT76_TM_STATS_ATTR_RX_FCS_ERROR,
472 MT76_TM_STATS_ATTR_LAST_RX,
473+ MT76_TM_STATS_ATTR_RX_LEN_MISMATCH,
474
475 /* keep last */
476 NUM_MT76_TM_STATS_ATTRS,
477--
developere35b8e42023-10-16 11:04:00 +08004782.18.0
developer6a1998b2022-12-08 18:09:45 +0800479