blob: 599e1613944e6764731ba1369576fb8e5d437151 [file] [log] [blame]
developerd0c89452024-10-11 16:53:27 +08001From 161b4dc2bb1f3d69b57f195fbab8fc8f6dfbe2bc Mon Sep 17 00:00:00 2001
developer66e89bc2024-04-23 14:50:01 +08002From: "sujuan.chen" <sujuan.chen@mediatek.com>
3Date: Fri, 6 Oct 2023 14:01:41 +0800
developerd0c89452024-10-11 16:53:27 +08004Subject: [PATCH 054/223] mtk: mt76: change pcie0 R5 to pcie1 to get 6G ICS
developer66e89bc2024-04-23 14:50:01 +08005
developerd0c89452024-10-11 16:53:27 +08006Change-Id: I23a94e3e4b797b513a303b13e4c50e0a0d72bffb
developer66e89bc2024-04-23 14:50:01 +08007---
8 mt7996/dma.c | 4 ++++
9 mt7996/init.c | 6 ++----
10 mt7996/mmio.c | 5 ++++-
11 3 files changed, 10 insertions(+), 5 deletions(-)
12
13diff --git a/mt7996/dma.c b/mt7996/dma.c
developer05f3b2b2024-08-19 19:17:34 +080014index 759a58e8..5d85e9ea 100644
developer66e89bc2024-04-23 14:50:01 +080015--- a/mt7996/dma.c
16+++ b/mt7996/dma.c
17@@ -538,6 +538,10 @@ int mt7996_dma_init(struct mt7996_dev *dev)
18 if (mt7996_band_valid(dev, MT_BAND2)) {
19 /* rx data queue for mt7996 band2 */
20 rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs;
21+ if (mtk_wed_device_active(wed_hif2) && mtk_wed_get_rx_capa(wed_hif2)) {
22+ dev->mt76.q_rx[MT_RXQ_BAND2].flags = MT_WED_Q_RX(0);
23+ dev->mt76.q_rx[MT_RXQ_BAND2].wed = wed_hif2;
24+ }
25 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2],
26 MT_RXQ_ID(MT_RXQ_BAND2),
27 MT7996_RX_RING_SIZE,
28diff --git a/mt7996/init.c b/mt7996/init.c
developerd0c89452024-10-11 16:53:27 +080029index eac00df0..f493a373 100644
developer66e89bc2024-04-23 14:50:01 +080030--- a/mt7996/init.c
31+++ b/mt7996/init.c
developer05f3b2b2024-08-19 19:17:34 +080032@@ -651,10 +651,8 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy,
developer66e89bc2024-04-23 14:50:01 +080033 goto error;
34
35 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) {
36- u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2;
37-
38- mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask);
39- mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask);
40+ mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT);
41+ mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, MT_INT_TX_RX_DONE_EXT);
42 }
43
44 return 0;
45diff --git a/mt7996/mmio.c b/mt7996/mmio.c
developerd0c89452024-10-11 16:53:27 +080046index 40e45fb2..11470645 100644
developer66e89bc2024-04-23 14:50:01 +080047--- a/mt7996/mmio.c
48+++ b/mt7996/mmio.c
49@@ -527,12 +527,15 @@ static void mt7996_irq_tasklet(struct tasklet_struct *t)
50 dev->mt76.mmio.irqmask);
51 if (intr1 & MT_INT_RX_TXFREE_EXT)
52 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]);
53+
54+ if (intr1 & MT_INT_RX_DONE_BAND2_EXT)
55+ napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]);
56 }
57
58 if (mtk_wed_device_active(wed)) {
59 mtk_wed_device_irq_set_mask(wed, 0);
60 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
61- intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT);
62+ intr |= (intr1 & ~MT_INT_TX_RX_DONE_EXT);
63 } else {
64 mt76_wr(dev, MT_INT_MASK_CSR, 0);
65 if (dev->hif2)
66--
developerd0c89452024-10-11 16:53:27 +0800672.45.2
developer66e89bc2024-04-23 14:50:01 +080068