| developer | d0c8945 | 2024-10-11 16:53:27 +0800 | [diff] [blame] | 1 | From 9c8447672f6bb36113eccf7064f91b11ea980825 Mon Sep 17 00:00:00 2001 |
| 2 | From: StanleyYP Wang <StanleyYP.Wang@mediatek.com> |
| 3 | Date: Tue, 5 Dec 2023 16:48:33 +0800 |
| 4 | Subject: [PATCH 045/223] mtk: mt76: mt7996: add Eagle 2adie TBTC (BE14000) |
| 5 | support |
| 6 | |
| 7 | Add fwdl/default eeprom load support for Eagle 2 adie TBTC |
| 8 | |
| 9 | Add Eagle 2adie TBTC efuse merge |
| 10 | Add Eagle 2adie TBTC group prek size |
| 11 | |
| 12 | Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> |
| 13 | Change-Id: I53479ad22aec81ba3f3028aa0aada86b175379f8 |
| 14 | --- |
| 15 | mt7996/eeprom.c | 6 ++++-- |
| 16 | mt7996/eeprom.h | 12 ++++++++++++ |
| 17 | mt7996/mt7996.h | 1 + |
| 18 | 3 files changed, 17 insertions(+), 2 deletions(-) |
| 19 | |
| 20 | diff --git a/mt7996/eeprom.c b/mt7996/eeprom.c |
| 21 | index be87afe8..f1c29e8d 100644 |
| 22 | --- a/mt7996/eeprom.c |
| 23 | +++ b/mt7996/eeprom.c |
| 24 | @@ -500,6 +500,8 @@ static void mt7996_eeprom_init_precal(struct mt7996_dev *dev) |
| 25 | switch (mt76_chip(&dev->mt76)) { |
| 26 | case 0x7990: |
| 27 | dev->prek.rev = mt7996_prek_rev; |
| 28 | + if (dev->chip_sku == MT7996_VAR_TYPE_233) |
| 29 | + dev->prek.rev = mt7996_prek_rev_233; |
| 30 | /* 5g & 6g bw 80 dpd channel list is not used */ |
| 31 | dev->prek.dpd_ch_num[DPD_CH_NUM_BW320_6G] = ARRAY_SIZE(dpd_6g_ch_list_bw320); |
| 32 | break; |
| 33 | @@ -603,7 +605,7 @@ static int mt7996_apply_cal_free_data(struct mt7996_dev *dev) |
| 34 | case 0x7990: |
| 35 | adie_base = adie_base_7996; |
| 36 | /* adie 0 */ |
| 37 | - if (dev->fem_type == MT7996_FEM_INT) |
| 38 | + if (dev->fem_type == MT7996_FEM_INT && dev->chip_sku != MT7996_VAR_TYPE_233) |
| 39 | adie_id = ADIE_7975; |
| 40 | else |
| 41 | adie_id = ADIE_7976; |
| 42 | @@ -611,7 +613,7 @@ static int mt7996_apply_cal_free_data(struct mt7996_dev *dev) |
| 43 | eep_offs[0] = eep_offs_list[adie_id]; |
| 44 | |
| 45 | /* adie 1 */ |
| 46 | - if (dev->chip_sku != MT7996_VAR_TYPE_404) { |
| 47 | + if (dev->chip_sku == MT7996_VAR_TYPE_444) { |
| 48 | adie_offs[1] = adie_offs_list[ADIE_7977]; |
| 49 | eep_offs[1] = eep_offs_list[ADIE_7977]; |
| 50 | } |
| 51 | diff --git a/mt7996/eeprom.h b/mt7996/eeprom.h |
| 52 | index c3c248ca..788c33c8 100644 |
| 53 | --- a/mt7996/eeprom.h |
| 54 | +++ b/mt7996/eeprom.h |
| 55 | @@ -70,6 +70,18 @@ static const u32 mt7996_prek_rev[] = { |
| 56 | [DPD_OTFG0_SIZE] = 2 * MT_EE_CAL_UNIT, |
| 57 | }; |
| 58 | |
| 59 | +static const u32 mt7996_prek_rev_233[] = { |
| 60 | + [GROUP_SIZE_2G] = 4 * MT_EE_CAL_UNIT, |
| 61 | + [GROUP_SIZE_5G] = 44 * MT_EE_CAL_UNIT, |
| 62 | + [GROUP_SIZE_6G] = 100 * MT_EE_CAL_UNIT, |
| 63 | + [ADCDCOC_SIZE_2G] = 4 * 4, |
| 64 | + [ADCDCOC_SIZE_5G] = 4 * 4, |
| 65 | + [ADCDCOC_SIZE_6G] = 4 * 5, |
| 66 | + [DPD_LEGACY_SIZE] = 4 * MT_EE_CAL_UNIT, |
| 67 | + [DPD_MEM_SIZE] = 13 * MT_EE_CAL_UNIT, |
| 68 | + [DPD_OTFG0_SIZE] = 2 * MT_EE_CAL_UNIT, |
| 69 | +}; |
| 70 | + |
| 71 | /* kite 2/5g config */ |
| 72 | static const u32 mt7992_prek_rev[] = { |
| 73 | [GROUP_SIZE_2G] = 4 * MT_EE_CAL_UNIT, |
| 74 | diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h |
| 75 | index f6e7fbdd..81639a45 100644 |
| 76 | --- a/mt7996/mt7996.h |
| 77 | +++ b/mt7996/mt7996.h |
| 78 | @@ -38,6 +38,7 @@ |
| 79 | #define MT7996_FIRMWARE_WA_233 "mediatek/mt7996/mt7996_wa_233.bin" |
| 80 | #define MT7996_FIRMWARE_WM_233 "mediatek/mt7996/mt7996_wm_233.bin" |
| 81 | #define MT7996_FIRMWARE_DSP_233 MT7996_FIRMWARE_DSP |
| 82 | +#define MT7996_FIRMWARE_WM_TM_233 "mediatek/mt7996/mt7996_wm_tm_233.bin" |
| 83 | #define MT7996_ROM_PATCH_233 "mediatek/mt7996/mt7996_rom_patch_233.bin" |
| 84 | |
| 85 | #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin" |
| 86 | -- |
| 87 | 2.45.2 |
| 88 | |