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developer05f3b2b2024-08-19 19:17:34 +08001From 343d81213790ba2a9928ee104067f5a18bbeacca Mon Sep 17 00:00:00 2001
developer66e89bc2024-04-23 14:50:01 +08002From: Rex Lu <rex.lu@mediatek.com>
3Date: Tue, 19 Mar 2024 13:16:12 +0800
developer05f3b2b2024-08-19 19:17:34 +08004Subject: [PATCH 085/199] mtk: mt76: mt7996: add kite two pcie with two wed
5 support
developer66e89bc2024-04-23 14:50:01 +08006
developer66e89bc2024-04-23 14:50:01 +08007Signed-off-by: Rex Lu <rex.lu@mediatek.com>
8---
9 mt7996/dma.c | 68 ++++++++++++++++++++++++++++++++++++++-------------
10 mt7996/init.c | 54 +++++++++++++++++++++++-----------------
11 mt7996/main.c | 5 ++--
12 mt7996/mmio.c | 15 ++++++++++--
13 mt7996/pci.c | 5 ++--
14 mt7996/regs.h | 1 +
15 6 files changed, 101 insertions(+), 47 deletions(-)
16
17diff --git a/mt7996/dma.c b/mt7996/dma.c
developer05f3b2b2024-08-19 19:17:34 +080018index 3dc0e8a1..a2490fa7 100644
developer66e89bc2024-04-23 14:50:01 +080019--- a/mt7996/dma.c
20+++ b/mt7996/dma.c
21@@ -108,8 +108,8 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
22 }
23
24 /* data tx queue */
25- TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
26 if (is_mt7996(&dev->mt76)) {
27+ TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
28 if (dev->hif2) {
29 if (dev->option_type == 2) {
30 /* bn1:ring21 bn2:ring19 */
31@@ -125,7 +125,15 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
32 TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
33 }
34 } else {
35- TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
36+ if (dev->hif2) {
37+ /* bn0:ring18 bn1:ring21 */
38+ TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
39+ TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);
40+ } else {
41+ /* single pcie bn0:ring18 bn1:ring19 */
42+ TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
43+ TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
44+ }
45 }
46
47 /* mcu tx queue */
48@@ -285,8 +293,11 @@ void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset)
49 if (mt7996_band_valid(dev, MT_BAND0))
50 irq_mask |= MT_INT_BAND0_RX_DONE;
51
52- if (mt7996_band_valid(dev, MT_BAND1))
53+ if (mt7996_band_valid(dev, MT_BAND1)) {
54 irq_mask |= MT_INT_BAND1_RX_DONE;
55+ if (is_mt7992(&dev->mt76) && dev->hif2)
56+ irq_mask |= MT_INT_RX_TXFREE_BAND1_EXT;
57+ }
58
59 if (mt7996_band_valid(dev, MT_BAND2))
60 irq_mask |= MT_INT_BAND2_RX_DONE;
61@@ -379,27 +390,46 @@ static void mt7996_dma_enable(struct mt7996_dev *dev, bool reset)
62 MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 |
63 MT_WFDMA_HOST_CONFIG_BAND2_PCIE1);
64
65- if (dev->option_type == 2)
66- mt76_set(dev, MT_WFDMA_HOST_CONFIG,
67- MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 |
68- MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
69- else
70- mt76_set(dev, MT_WFDMA_HOST_CONFIG,
71- MT_WFDMA_HOST_CONFIG_BAND2_PCIE1);
72-
73- if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
74- is_mt7992(&dev->mt76)) {
75+ switch (dev->option_type) {
76+ case 2:
77+ /* eagle + 7988d */
78+ if (is_mt7996(&dev->mt76))
79+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
80+ MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 |
81+ MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
82+ else
83+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
84+ MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
85+ break;
86+ case 3:
87 mt76_set(dev, MT_WFDMA_HOST_CONFIG,
88- MT_WFDMA_HOST_CONFIG_PDMA_BAND |
89- MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
90+ MT_WFDMA_HOST_CONFIG_BAND0_PCIE1);
91+
92+ break;
93+ default:
94+ if (is_mt7996(&dev->mt76))
95+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
96+ MT_WFDMA_HOST_CONFIG_BAND2_PCIE1);
97+ else
98+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
99+ MT_WFDMA_HOST_CONFIG_BAND1_PCIE1);
100+ break;
101 }
102
103 /* AXI read outstanding number */
104 mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL,
105 MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK, 0x14);
106
107- if (dev->hif2->speed < PCIE_SPEED_8_0GT ||
108- (dev->hif2->speed == PCIE_SPEED_8_0GT && dev->hif2->width < 2)) {
109+ if (dev->hif2->speed < PCIE_SPEED_5_0GT ||
110+ (dev->hif2->speed == PCIE_SPEED_5_0GT && dev->hif2->width < 2)) {
111+ mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
112+ WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK,
113+ FIELD_PREP(WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 0x1));
114+ mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL2,
115+ MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK,
116+ FIELD_PREP(MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 0x1));
117+ } else if (dev->hif2->speed < PCIE_SPEED_8_0GT ||
118+ (dev->hif2->speed == PCIE_SPEED_8_0GT && dev->hif2->width < 2)) {
119 mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
120 WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK,
121 FIELD_PREP(WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 0x3));
122@@ -648,6 +678,10 @@ int mt7996_dma_init(struct mt7996_dev *dev)
123
124 /* tx free notify event from WA for mt7992 band1 */
125 rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs;
126+ if (mtk_wed_device_active(wed_hif2)) {
127+ dev->mt76.q_rx[MT_RXQ_BAND1_WA].flags = MT_WED_Q_TXFREE;
128+ dev->mt76.q_rx[MT_RXQ_BAND1_WA].wed = wed_hif2;
129+ }
130 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],
131 MT_RXQ_ID(MT_RXQ_BAND1_WA),
132 MT7996_RX_MCU_RING_SIZE,
133diff --git a/mt7996/init.c b/mt7996/init.c
developer05f3b2b2024-08-19 19:17:34 +0800134index 910ffccf..1e4e6e78 100644
developer66e89bc2024-04-23 14:50:01 +0800135--- a/mt7996/init.c
136+++ b/mt7996/init.c
developer05f3b2b2024-08-19 19:17:34 +0800137@@ -527,39 +527,46 @@ void mt7996_mac_init(struct mt7996_dev *dev)
developer66e89bc2024-04-23 14:50:01 +0800138 }
139
140 /* rro module init */
141+ rx_path_type = is_mt7996(&dev->mt76) ? 2 : 7;
142+ rro_bypass = is_mt7996(&dev->mt76) ? 1 : 2;
143+ txfree_path = is_mt7996(&dev->mt76) ? 0: 1;
144+
145 switch (dev->option_type) {
146 case 2:
147- /* eagle + 7988d */
148- rx_path_type = 3;
149- rro_bypass = dev->has_rro ? 1 : 3;
150- txfree_path = dev->has_rro ? 0 : 1;
151+ if (is_mt7996(&dev->mt76)) {
152+ /* eagle + 7988d */
153+ rx_path_type = 3;
154+ rro_bypass = 1;
155+ txfree_path = 0;
156+ }
157 break;
158 case 3:
159- /* eagle + Airoha */
160- rx_path_type = 6;
161- rro_bypass = dev->has_rro ? 1 : 3;
162- txfree_path = dev->has_rro ? 0 : 1;
163+ /* Airoha */
164+ if (is_mt7996(&dev->mt76)) {
165+ rx_path_type = 6;
166+ rro_bypass = 1;
167+ txfree_path = 0;
168+ } else {
169+ rx_path_type = 8;
170+ rro_bypass = 2;
171+ txfree_path = 1;
172+ }
173 break;
174 case 4:
175- /* Bollinger */
176- rx_path_type = 2;
177- rro_bypass = dev->has_rro ? 1 : 3;
178- txfree_path = dev->has_rro ? 0 : 1;
179+ if (is_mt7996(&dev->mt76)) {
180+ /* Bollinger */
181+ rx_path_type = 2;
182+ rro_bypass = 1;
183+ txfree_path = 0;
184+ }
185 break;
186 default:
187- if (is_mt7996(&dev->mt76))
188- rx_path_type = 2;
189- else
190- rx_path_type = 7;
191-
192- rro_bypass = dev->has_rro ? 1 : 3;
193- txfree_path = dev->has_rro ? 0 : 1;
194 break;
195 }
196
197 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, dev->hif2 ? rx_path_type : 0);
198- mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, rro_bypass);
199- mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, txfree_path);
200+ mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, dev->has_rro ? rro_bypass : 3);
201+ mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, dev->has_rro ? txfree_path : 1);
202
203 if (dev->has_rro) {
204 u16 timeout;
developer05f3b2b2024-08-19 19:17:34 +0800205@@ -643,7 +650,7 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy,
developer66e89bc2024-04-23 14:50:01 +0800206 if (phy)
207 return 0;
208
209- if (is_mt7996(&dev->mt76) && dev->hif2) {
210+ if (dev->hif2) {
211 switch (dev->option_type) {
212 case 2:
213 /* eagle + 7988d */
developer05f3b2b2024-08-19 19:17:34 +0800214@@ -653,7 +660,8 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy,
developer66e89bc2024-04-23 14:50:01 +0800215 }
216 break;
217 default:
218- if (band == MT_BAND2) {
219+ if ((is_mt7996(&dev->mt76) && band == MT_BAND2) ||
220+ (is_mt7992(&dev->mt76) && band == MT_BAND1)) {
221 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
222 wed = &dev->mt76.mmio.wed_hif2;
223 }
224diff --git a/mt7996/main.c b/mt7996/main.c
developer05f3b2b2024-08-19 19:17:34 +0800225index 8c93297a..a37aac43 100644
developer66e89bc2024-04-23 14:50:01 +0800226--- a/mt7996/main.c
227+++ b/mt7996/main.c
developer05f3b2b2024-08-19 19:17:34 +0800228@@ -1611,7 +1611,7 @@ mt7996_net_fill_forward_path(struct ieee80211_hw *hw,
developer66e89bc2024-04-23 14:50:01 +0800229 struct mt7996_phy *phy = mt7996_hw_phy(hw);
230 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
231
232- if (phy != &dev->phy && dev->hif2) {
233+ if (dev->hif2) {
234 switch (dev->option_type) {
235 case 2:
236 /* eagle + 7988d */
developer05f3b2b2024-08-19 19:17:34 +0800237@@ -1619,7 +1619,8 @@ mt7996_net_fill_forward_path(struct ieee80211_hw *hw,
developer66e89bc2024-04-23 14:50:01 +0800238 wed = &dev->mt76.mmio.wed_hif2;
239 break;
240 default:
241- if (phy->mt76->band_idx == MT_BAND2)
242+ if ((is_mt7996(&dev->mt76) && phy->mt76->band_idx == MT_BAND2) ||
243+ (is_mt7992(&dev->mt76) && phy->mt76->band_idx == MT_BAND1))
244 wed = &dev->mt76.mmio.wed_hif2;
245 break;
246 }
247diff --git a/mt7996/mmio.c b/mt7996/mmio.c
developer05f3b2b2024-08-19 19:17:34 +0800248index 4baae0e9..d4739fea 100644
developer66e89bc2024-04-23 14:50:01 +0800249--- a/mt7996/mmio.c
250+++ b/mt7996/mmio.c
251@@ -336,10 +336,16 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
252 MT_TXQ_RING_BASE(0) +
253 MT7996_TXQ_BAND2 * MT_RING_SIZE;
254 if (dev->has_rro) {
255+ u8 rxq_id = is_mt7996(&dev->mt76) ?
256+ MT7996_RXQ_TXFREE2 : MT7996_RXQ_MCU_WA_EXT;
257+
258 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs +
259 MT_RXQ_RING_BASE(0) +
260- MT7996_RXQ_TXFREE2 * MT_RING_SIZE;
261- wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1;
262+ rxq_id * MT_RING_SIZE;
263+ if (is_mt7996(&dev->mt76))
264+ wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1;
265+ else
266+ wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_BAND1_EXT) - 1;
267 } else {
268 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs +
269 MT_RXQ_RING_BASE(0) +
270@@ -423,6 +429,8 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
271 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE;
272 }
273 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE + wed->wlan.rx_npkt;
274+ if(dev->hif2 && is_mt7992(&dev->mt76))
275+ wed->wlan.id = 0x7992;
276 }
277
278 wed->wlan.nbuf = MT7996_TOKEN_SIZE;
279@@ -553,6 +561,9 @@ static void mt7996_irq_tasklet(struct tasklet_struct *t)
280
281 if (intr1 & MT_INT_RX_DONE_BAND2_EXT)
282 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]);
283+
284+ if (is_mt7992(&dev->mt76) && (intr1 & MT_INT_RX_TXFREE_BAND1_EXT))
285+ napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]);
286 }
287
288 if (mtk_wed_device_active(wed)) {
289diff --git a/mt7996/pci.c b/mt7996/pci.c
developer05f3b2b2024-08-19 19:17:34 +0800290index 24d69d4d..382b6a89 100644
developer66e89bc2024-04-23 14:50:01 +0800291--- a/mt7996/pci.c
292+++ b/mt7996/pci.c
293@@ -110,7 +110,7 @@ static int mt7996_pci_probe(struct pci_dev *pdev,
294 int irq, ret;
295 struct mt76_dev *mdev;
296
297- hif2_enable |= (id->device == 0x7990 || id->device == 0x7991);
298+ hif2_enable |= (id->device == 0x7990 || id->device == 0x7991 || id->device == 0x799a);
299
300 ret = pcim_enable_device(pdev);
301 if (ret)
302@@ -171,8 +171,7 @@ static int mt7996_pci_probe(struct pci_dev *pdev,
303 hif2_dev = container_of(hif2->dev, struct pci_dev, dev);
304 ret = 0;
305
306- if (is_mt7996(&dev->mt76))
307- ret = mt7996_mmio_wed_init(dev, hif2_dev, true, &irq);
308+ ret = mt7996_mmio_wed_init(dev, hif2_dev, true, &irq);
309
310 if (ret < 0)
311 goto free_wed_or_irq_vector;
312diff --git a/mt7996/regs.h b/mt7996/regs.h
developer05f3b2b2024-08-19 19:17:34 +0800313index a0e4b3e1..e1893517 100644
developer66e89bc2024-04-23 14:50:01 +0800314--- a/mt7996/regs.h
315+++ b/mt7996/regs.h
316@@ -525,6 +525,7 @@ enum offs_rev {
317 #define MT_INT_RX_TXFREE_MAIN BIT(17)
318 #define MT_INT_RX_TXFREE_BAND1 BIT(15)
319 #define MT_INT_RX_TXFREE_TRI BIT(15)
320+#define MT_INT_RX_TXFREE_BAND1_EXT BIT(19) /* for mt7992 two PCIE*/
321 #define MT_INT_RX_DONE_BAND2_EXT BIT(23)
322 #define MT_INT_RX_TXFREE_EXT BIT(26)
323 #define MT_INT_MCU_CMD BIT(29)
324--
developer9237f442024-06-14 17:13:04 +08003252.18.0
developer66e89bc2024-04-23 14:50:01 +0800326