[Add meta-filogic bsp for rdkb development]
[Description]
Add meta-filogic bsp for rdkb development
1. rdkb base on dunfell rdkb-next (> 2022q1)
2. arm64/arm 32bit bsp both can run on rdkb
[Release-log]
N/A
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch
new file mode 100644
index 0000000..d40cbfb
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch
@@ -0,0 +1,258 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -53,6 +53,13 @@
+ };
+ };
+
++ gsw: gsw@0 {
++ compatible = "mediatek,mt753x";
++ mediatek,ethsys = <ðsys>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
+ leds {
+ compatible = "gpio-leds";
+
+@@ -146,6 +153,36 @@
+ };
+ };
+
++&gsw {
++ mediatek,mdio = <&mdio>;
++ mediatek,portmap = "wllll";
++ mediatek,mdio_master_pinmux = <0>;
++ reset-gpios = <&pio 54 0>;
++ interrupt-parent = <&pio>;
++ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
++ status = "okay";
++
++ port5: port@5 {
++ compatible = "mediatek,mt753x-port";
++ reg = <5>;
++ phy-mode = "rgmii";
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++
++ port6: port@6 {
++ compatible = "mediatek,mt753x-port";
++ reg = <6>;
++ phy-mode = "sgmii";
++ fixed-link {
++ speed = <2500>;
++ full-duplex;
++ };
++ };
++};
++
+ &i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -1,7 +1,6 @@
+ /*
+- * Copyright (c) 2017 MediaTek Inc.
+- * Author: Ming Huang <ming.huang@mediatek.com>
+- * Sean Wang <sean.wang@mediatek.com>
++ * Copyright (c) 2018 MediaTek Inc.
++ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+@@ -14,7 +13,7 @@
+ #include "mt6380.dtsi"
+
+ / {
+- model = "MediaTek MT7622 RFB1 board";
++ model = "MT7622_MT7531 RFB";
+ compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+
+ aliases {
+@@ -23,7 +22,7 @@
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
++ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
+ };
+
+ cpus {
+@@ -40,23 +39,36 @@
+
+ gpio-keys {
+ compatible = "gpio-keys";
+- poll-interval = <100>;
+
+ factory {
+ label = "factory";
+ linux,code = <BTN_0>;
+- gpios = <&pio 0 0>;
++ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+- gpios = <&pio 102 0>;
++ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ green {
++ label = "bpi-r64:pio:green";
++ gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
++ };
++
++ red {
++ label = "bpi-r64:pio:red";
++ gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory {
+- reg = <0 0x40000000 0 0x20000000>;
++ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+@@ -101,23 +113,82 @@
+ };
+
+ ð {
+- pinctrl-names = "default";
+- pinctrl-0 = <ð_pins>;
+ status = "okay";
++ gmac0: mac@0 {
++ compatible = "mediatek,eth-mac";
++ reg = <0>;
++ phy-mode = "2500base-x";
++
++ fixed-link {
++ speed = <2500>;
++ full-duplex;
++ pause;
++ };
++ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+- phy-handle = <&phy5>;
++ phy-mode = "rgmii";
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ pause;
++ };
+ };
+
+- mdio-bus {
++ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- phy5: ethernet-phy@5 {
+- reg = <5>;
+- phy-mode = "sgmii";
++ switch@0 {
++ compatible = "mediatek,mt7531";
++ reg = <0>;
++ reset-gpios = <&pio 54 0>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@6 {
++ reg = <6>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ phy-mode = "2500base-x";
++
++ fixed-link {
++ speed = <2500>;
++ full-duplex;
++ pause;
++ };
++ };
++ };
+ };
+ };
+ };
+@@ -185,15 +256,28 @@
+
+ &pcie {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pcie0_pins>;
++ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+ status = "okay";
+
+ pcie@0,0 {
+ status = "okay";
+ };
++
++ pcie@1,0 {
++ status = "okay";
++ };
+ };
+
+ &pio {
++ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
++ * SATA functions. i.e. output-high: PCIe, output-low: SATA
++ */
++ asm_sel {
++ gpio-hog;
++ gpios = <90 GPIO_ACTIVE_HIGH>;
++ output-high;
++ };
++
+ /* eMMC is shared pin with parallel NAND */
+ emmc_pins_default: emmc-pins-default {
+ mux {
+@@ -460,11 +544,11 @@
+ };
+
+ &sata {
+- status = "okay";
++ status = "disable";
+ };
+
+ &sata_phy {
+- status = "okay";
++ status = "disable";
+ };
+
+ &spi0 {