[rdk-b][common][bsp][Refactor and sync kernel/wifi from Openwrt]
[Description]
Refactor and sync kernel/wifi from Openwrt
[Release-log]
N/A
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
index a4d3f2f..604f5aa 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -397,6 +397,11 @@
<0 0x0f0f0000 0 0x200>;
};
+ boottrap: boottrap@1001f6f0 {
+ compatible = "mediatek,boottrap";
+ reg = <0 0x1001f6f0 0 0x20>;
+ };
+
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts
index 21eab01..373fdc3 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-emmc.dts
@@ -210,21 +210,29 @@
port@0 {
reg = <0>;
label = "lan0";
+ phy-mode = "gmii";
+ phy-handle = <&sphy0>;
};
port@1 {
reg = <1>;
label = "lan1";
+ phy-mode = "gmii";
+ phy-handle = <&sphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "gmii";
+ phy-handle = <&sphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-mode = "gmii";
+ phy-handle = <&sphy3>;
};
port@6 {
@@ -240,6 +248,52 @@
};
};
};
+
+ mdio {
+ compatible = "mediatek,dsa-slave-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sphy0: switch_phy0@0 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <0>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy1: switch_phy1@1 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <1>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy2: switch_phy2@2 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <2>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy3: switch_phy3@3 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <3>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+ };
};
};
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts
index bc2d427..2b20e0b 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-sd.dts
@@ -201,21 +201,29 @@
port@0 {
reg = <0>;
label = "lan0";
+ phy-mode = "gmii";
+ phy-handle = <&sphy0>;
};
port@1 {
reg = <1>;
label = "lan1";
+ phy-mode = "gmii";
+ phy-handle = <&sphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "gmii";
+ phy-handle = <&sphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-mode = "gmii";
+ phy-handle = <&sphy3>;
};
port@6 {
@@ -231,6 +239,52 @@
};
};
};
+
+ mdio {
+ compatible = "mediatek,dsa-slave-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sphy0: switch_phy0@0 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <0>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy1: switch_phy1@1 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <1>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy2: switch_phy2@2 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <2>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy3: switch_phy3@3 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <3>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+ };
};
};
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts
index 15d38ec..8e49212 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-snfi-nand.dts
@@ -236,21 +236,29 @@
port@0 {
reg = <0>;
label = "lan0";
+ phy-mode = "gmii";
+ phy-handle = <&sphy0>;
};
port@1 {
reg = <1>;
label = "lan1";
+ phy-mode = "gmii";
+ phy-handle = <&sphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "gmii";
+ phy-handle = <&sphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-mode = "gmii";
+ phy-handle = <&sphy3>;
};
port@6 {
@@ -266,6 +274,52 @@
};
};
};
+
+ mdio {
+ compatible = "mediatek,dsa-slave-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sphy0: switch_phy0@0 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <0>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy1: switch_phy1@1 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <1>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy2: switch_phy2@2 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <2>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy3: switch_phy3@3 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <3>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+ };
};
};
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
index 6a289ff..c707291 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
@@ -249,21 +249,29 @@
port@0 {
reg = <0>;
label = "lan0";
+ phy-mode = "gmii";
+ phy-handle = <&sphy0>;
};
port@1 {
reg = <1>;
label = "lan1";
+ phy-mode = "gmii";
+ phy-handle = <&sphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "gmii";
+ phy-handle = <&sphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-mode = "gmii";
+ phy-handle = <&sphy3>;
};
port@6 {
@@ -279,6 +287,52 @@
};
};
};
+
+ mdio {
+ compatible = "mediatek,dsa-slave-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sphy0: switch_phy0@0 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <0>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy1: switch_phy1@1 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <1>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy2: switch_phy2@2 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <2>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy3: switch_phy3@3 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <3>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+ };
};
};
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
index 4edf1f0..8e832f3 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
@@ -226,21 +226,29 @@
port@0 {
reg = <0>;
label = "lan0";
+ phy-mode = "gmii";
+ phy-handle = <&sphy0>;
};
port@1 {
reg = <1>;
label = "lan1";
+ phy-mode = "gmii";
+ phy-handle = <&sphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "gmii";
+ phy-handle = <&sphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-mode = "gmii";
+ phy-handle = <&sphy3>;
};
port@6 {
@@ -256,6 +264,52 @@
};
};
};
+
+ mdio {
+ compatible = "mediatek,dsa-slave-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sphy0: switch_phy0@0 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <0>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy1: switch_phy1@1 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <1>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy2: switch_phy2@2 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <2>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy3: switch_phy3@3 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <3>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+ };
};
};
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts
index ed60643..8f0d5c9 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-e2p5g-spim-nand.dts
@@ -322,21 +322,29 @@
port@0 {
reg = <0>;
label = "lan0";
+ phy-mode = "gmii";
+ phy-handle = <&sphy0>;
};
port@1 {
reg = <1>;
label = "lan1";
+ phy-mode = "gmii";
+ phy-handle = <&sphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "gmii";
+ phy-handle = <&sphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-mode = "gmii";
+ phy-handle = <&sphy3>;
};
port@6 {
@@ -352,6 +360,52 @@
};
};
};
+
+ mdio {
+ compatible = "mediatek,dsa-slave-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sphy0: switch_phy0@0 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <0>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy1: switch_phy1@1 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <1>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy2: switch_phy2@2 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <2>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy3: switch_phy3@3 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <3>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+ };
};
};
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts
index d07634b..e0ffe52 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts
@@ -239,21 +239,29 @@
port@0 {
reg = <0>;
label = "lan0";
+ phy-mode = "gmii";
+ phy-handle = <&sphy0>;
};
port@1 {
reg = <1>;
label = "lan1";
+ phy-mode = "gmii";
+ phy-handle = <&sphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "gmii";
+ phy-handle = <&sphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-mode = "gmii";
+ phy-handle = <&sphy3>;
};
port@6 {
@@ -269,6 +277,52 @@
};
};
};
+
+ mdio {
+ compatible = "mediatek,dsa-slave-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sphy0: switch_phy0@0 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <0>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy1: switch_phy1@1 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <1>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy2: switch_phy2@2 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <2>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+
+ sphy3: switch_phy3@3 {
+ compatible = "ethernet-phy-id03a2.9481";
+ reg = <3>;
+ phy-mode = "gmii";
+ rext = "efuse";
+ tx_r50 = "efuse";
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+ };
};
};
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c
index b86c1b9..8221cbc 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/hnat_nf_hook.c
@@ -1357,7 +1357,7 @@
if (hnat_priv->data->per_flow_accounting)
entry.ipv4_dslite.iblk2.mibf = 1;
/* Map-E LAN->WAN record inner IPv4 header info. */
-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
if (mape_toggle) {
entry.ipv4_dslite.iblk2.dscp = foe->ipv4_dslite.iblk2.dscp;
entry.ipv4_mape.new_sip = foe->ipv4_mape.new_sip;
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_usxgmii.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_usxgmii.c
index aaefa80..363de90 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_usxgmii.c
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_usxgmii.c
@@ -316,7 +316,7 @@
break;
}
- udelay(100);
+ mdelay(1);
}
int mtk_usxgmii_setup_mode_an(struct mtk_xgmii *ss, int mac_id, int max_speed)
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
index 50729d6..fd3022f 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
@@ -2,6 +2,7 @@
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
+#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
@@ -177,6 +178,30 @@
/* Registers on MDIO_MMD_VEND2 */
+#define MTK_PHY_LED0_ON_CTRL (0x24)
+#define MTK_PHY_LED0_ON_MASK GENMASK(6, 0)
+#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
+#define MTK_PHY_LED0_ON_LINK100 BIT(1)
+#define MTK_PHY_LED0_ON_LINK10 BIT(2)
+#define MTK_PHY_LED0_ON_LINKDOWN BIT(3)
+#define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */
+#define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */
+#define MTK_PHY_LED0_FORCE_ON BIT(6)
+#define MTK_PHY_LED0_POLARITY BIT(14)
+#define MTK_PHY_LED0_ENABLE BIT(15)
+
+#define MTK_PHY_LED0_BLINK_CTRL (0x25)
+#define MTK_PHY_LED0_1000TX BIT(0)
+#define MTK_PHY_LED0_1000RX BIT(1)
+#define MTK_PHY_LED0_100TX BIT(2)
+#define MTK_PHY_LED0_100RX BIT(3)
+#define MTK_PHY_LED0_10TX BIT(4)
+#define MTK_PHY_LED0_10RX BIT(5)
+#define MTK_PHY_LED0_COLLISION BIT(6)
+#define MTK_PHY_LED0_RX_CRC_ERR BIT(7)
+#define MTK_PHY_LED0_RX_IDLE_ERR BIT(8)
+#define MTK_PHY_LED0_FORCE_BLINK BIT(9)
+
#define MTK_PHY_ANA_TEST_BUS_CTRL_RG (0x100)
#define MTK_PHY_ANA_TEST_MODE_MASK GENMASK(15, 8)
@@ -217,6 +242,13 @@
PAIR_D,
} phy_cal_pair_t;
+enum {
+ GPHY_PORT0,
+ GPHY_PORT1,
+ GPHY_PORT2,
+ GPHY_PORT3,
+};
+
const u8 mt798x_zcal_to_r50[64] = {
7, 8, 9, 9, 10, 10, 11, 11,
12, 13, 13, 14, 14, 15, 16, 16,
@@ -958,6 +990,38 @@
static int mt7988_phy_config_init(struct phy_device *phydev)
{
+ struct device_node *np;
+ void __iomem *boottrap;
+ u32 reg;
+ int port;
+
+ /* Setup LED polarity according to boottrap's polarity */
+ np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap");
+ if (!np)
+ return -ENOENT;
+ boottrap = of_iomap(np, 0);
+ if (!boottrap)
+ return -ENOMEM;
+ reg = readl(boottrap);
+ port = phydev->mdio.addr;
+ if ((port == GPHY_PORT0 && reg & BIT(8)) ||
+ (port == GPHY_PORT1 && reg & BIT(9)) ||
+ (port == GPHY_PORT2 && reg & BIT(10)) ||
+ (port == GPHY_PORT3 && reg & BIT(11))) {
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
+ MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_ON_LINK10 |
+ MTK_PHY_LED0_ON_LINK100 | MTK_PHY_LED0_ON_LINK1000);
+ } else {
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
+ MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY |
+ MTK_PHY_LED0_ON_LINK10 | MTK_PHY_LED0_ON_LINK100 |
+ MTK_PHY_LED0_ON_LINK1000);
+ }
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
+ MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX |
+ MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX |
+ MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX);
+
mt7988_phy_finetune(phydev);
return mt798x_phy_calibration(phydev);
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/pinctrl/mediatek/pinctrl-mt7988.c
index 3be91dd..7521c14 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/pinctrl/mediatek/pinctrl-mt7988.c
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/pinctrl/mediatek/pinctrl-mt7988.c
@@ -1026,9 +1026,13 @@
static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
+/* i2s */
+static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 };
+static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 };
+
/* pcm */
-static int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 };
+static int mt7988_pcm_pins[] = { 50, 51, 52, 53 };
+static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 };
/* led */
static int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 };
@@ -1179,7 +1183,9 @@
PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
/* @GPIO(30,31) gbe_ext_mdio */
PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
- /* @GPIO(50,51,52,53,54) pcm */
+ /* @GPIO(50,51,52,53,54) i2s */
+ PINCTRL_PIN_GROUP("i2s", mt7988_i2s),
+ /* @GPIO(50,51,52,53) pcm */
PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
/* @GPIO(55,56) uart0 */
PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
@@ -1373,8 +1379,8 @@
static const char * const mt7988_udi_groups[] = {
"udi",
};
-static const char * const mt7988_pcm_groups[] = {
- "pcm",
+static const char * const mt7988_audio_groups[] = {
+ "i2s", "pcm",
};
static const char * const mt7988_led_groups[] = {
"gbe_led1", "2p5gbe_led1", "gbe_led0",
@@ -1386,6 +1392,7 @@
};
static const struct function_desc mt7988_functions[] = {
+ { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) },
{ "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) },
{ "int_usxgmii", mt7988_int_usxgmii_groups,
ARRAY_SIZE(mt7988_int_usxgmii_groups) },
@@ -1400,7 +1407,6 @@
{ "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) },
{ "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) },
{ "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) },
- { "pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups) },
{ "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) },
{ "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) },
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7986.cfg b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7986.cfg
index a8ecb3d..22f75b1 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7986.cfg
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7986.cfg
@@ -101,6 +101,7 @@
# CONFIG_COMMON_CLK_MT7622_HIFSYS is not set
# CONFIG_COMMON_CLK_MT7981 is not set
CONFIG_COMMON_CLK_MT7986=y
+# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8173 is not set
CONFIG_COMMON_CLK_MT8183=y
# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set
@@ -298,6 +299,7 @@
CONFIG_MD=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
+# CONFIG_MEDIATEK_2P5GE_PHY is not set
# CONFIG_MEDIATEK_GE_PHY is not set
CONFIG_MEDIATEK_MT6577_AUXADC=y
CONFIG_MEDIATEK_NETSYS_V2=y
@@ -335,6 +337,7 @@
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_SCPSYS=y
+# CONFIG_MTK_SOC_THERMAL_LVTS is not set
CONFIG_MTK_SPI_NAND=y
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
@@ -408,6 +411,7 @@
# CONFIG_PINCTRL_MT7622 is not set
# CONFIG_PINCTRL_MT7981 is not set
CONFIG_PINCTRL_MT7986=y
+CONFIG_PINCTRL_MT7988=y
# CONFIG_PINCTRL_MT8173 is not set
# CONFIG_PINCTRL_MT8183 is not set
CONFIG_PINCTRL_MT8516=y
@@ -434,12 +438,12 @@
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_REALTEK_PHY=y
-CONFIG_REFCOUNT_FULL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MT6380=y
+# CONFIG_REGULATOR_RT5190A is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_TI_SYSCON=y
CONFIG_RFS_ACCEL=y
@@ -532,7 +536,3 @@
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y
-# CONFIG_BPF_KPROBE_OVERRIDE is not set
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
-# CONFIG_HIST_TRIGGERS is not set
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0491-mtd-spinand-macronix-suppress-mx35lf1ge4ab-warning-log.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0491-mtd-spinand-macronix-suppress-mx35lf1ge4ab-warning-log.patch
new file mode 100644
index 0000000..7951d63
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0491-mtd-spinand-macronix-suppress-mx35lf1ge4ab-warning-log.patch
@@ -0,0 +1,11 @@
+--- a/drivers/mtd/nand/spi/macronix.c
++++ b/drivers/mtd/nand/spi/macronix.c
+@@ -86,7 +86,7 @@ static int mx35lf1ge4ab_ecc_get_status(s
+ if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr))
+ return nand->eccreq.strength;
+
+- if (WARN_ON(eccsr > nand->eccreq.strength || !eccsr))
++ if (eccsr > nand->eccreq.strength || !eccsr)
+ return nand->eccreq.strength;
+
+ return eccsr;
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc
index d63d381..01c12d3 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc
@@ -35,6 +35,7 @@
file://0401-sound-refine-hw-params-and-hw-prepare.patch \
file://0402-sound-add-mt7986-driver.patch \
file://0490-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch \
+ file://0491-mtd-spinand-macronix-suppress-mx35lf1ge4ab-warning-log.patch \
file://0500-v5.6-crypto-backport-inside-secure.patch \
file://0501-crypto-add-eip97-inside-secure-support.patch \
file://0502-dts-mt7623-eip97-inside-secure-support.patch \