tree b861d35b14fc6ca3aeef741930a1057a6921cd73
parent 9a58788609f0dcd653458b9a220025f9dd4c8a65
author developer <developer@mediatek.com> 1690771012 +0800
committer developer <developer@mediatek.com> 1690771012 +0800

[rdkb][common][bsp][Refactor and sync kernel from openwrt]

[Description]
c94cd6df [kernel][mt7981][eth][Enable Maxlinear GPHY driver]
9c2ed502 [openwrt][common][emmc][Change and load loop kernel module at early stage during kernel startup]
ae6acab8 [kernel][mt7988][eth][Change XGAMC force-link control flow and add XGMAC reset flow]
118dc32f [[openwrt][mt7988][config][refine adma rx hang detect condition]]
ea9d072f [Kernel][hnat][Fix API clear BIND entries for WIFI]
dec786dc [kernel][common][Change reserved memory size for BL31/BL32]
3bdb1914 [kernel][common][spinor][Add EN25QX256A]
97606068 [Kernel][hnat][Fix the conditions for adding vlan info]
e4e3ae91 [kernel][common][eth][Add gangload timeout mechanism for the Aquantia PHY driver]

[Release-log]

Change-Id: I6e58fec0e34affa8568a53bc14d7b46d3750d0eb