| From 1de98ecb4505e3f99759caf4e9df9e263dfa403a Mon Sep 17 00:00:00 2001 |
| From: "Allen.Ye" <allen.ye@mediatek.com> |
| Date: Fri, 11 Aug 2023 16:46:53 +0800 |
| Subject: [PATCH 1033/1051] wifi: mt76: mt7915: Disable RegDB when enable |
| single sku |
| |
| --- |
| mt7915/debugfs.c | 49 +++++++++++++++++++++++++++++++++++++++++++----- |
| mt7915/init.c | 11 +++++++++-- |
| mt7915/regs.h | 8 ++++---- |
| 3 files changed, 57 insertions(+), 11 deletions(-) |
| |
| diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c |
| index 24e88f7..502b493 100644 |
| --- a/mt7915/debugfs.c |
| +++ b/mt7915/debugfs.c |
| @@ -1020,10 +1020,16 @@ mt7915_rate_txpower_get(struct file *file, char __user *user_buf, |
| { |
| struct mt7915_phy *phy = file->private_data; |
| struct mt7915_dev *dev = phy->dev; |
| + struct ieee80211_channel *chan = phy->mt76->chandef.chan; |
| + struct ieee80211_supported_band sband; |
| s8 txpwr[MT7915_SKU_RATE_NUM]; |
| - static const size_t sz = 2048; |
| + static const size_t sz = 4096; |
| u8 band = phy->mt76->band_idx; |
| int i, offs = 0, len = 0; |
| + u32 target_power = 0; |
| + int n_chains = hweight16(phy->mt76->chainmask); |
| + int nss_delta = mt76_tx_power_nss_delta(n_chains); |
| + int pwr_delta; |
| ssize_t ret; |
| char *buf; |
| u32 reg; |
| @@ -1082,11 +1088,38 @@ mt7915_rate_txpower_get(struct file *file, char __user *user_buf, |
| len += scnprintf(buf + len, sz - len, "BW160/"); |
| mt7915_txpower_puts(HE_RU2x996, 17); |
| |
| - reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_TPC_CTRL_STAT(band) : |
| - MT_WF_PHY_TPC_CTRL_STAT_MT7916(band); |
| + reg = is_mt7915(&dev->mt76) ? MT_WF_IRPI_TPC_CTRL_STAT(band) : |
| + MT_WF_IRPI_TPC_CTRL_STAT_MT7916(band); |
| |
| - len += scnprintf(buf + len, sz - len, "\nTx power (bbp) : %6ld\n", |
| - mt76_get_field(dev, reg, MT_WF_PHY_TPC_POWER)); |
| + len += scnprintf(buf + len, sz - len, "\nTx power (bbp) : %6ld [0.5 dBm]\n", |
| + mt76_get_field(dev, reg, MT_WF_IRPI_TPC_POWER)); |
| + |
| + len += scnprintf(buf + len, sz - len, "RegDB maximum power:\t%d [dBm]\n", |
| + chan->max_reg_power); |
| + |
| + if (chan->band == NL80211_BAND_2GHZ) |
| + sband = phy->mt76->sband_2g.sband; |
| + else if (chan->band == NL80211_BAND_5GHZ) |
| + sband = phy->mt76->sband_5g.sband; |
| + else if (chan->band == NL80211_BAND_6GHZ) |
| + sband = phy->mt76->sband_6g.sband; |
| + |
| + pwr_delta = mt7915_eeprom_get_power_delta(dev, sband.band); |
| + |
| + for (i = 0; i < n_chains; i++) { |
| + u32 val; |
| + |
| + val = mt7915_eeprom_get_target_power(dev, chan, i); |
| + target_power = max(target_power, val); |
| + } |
| + |
| + target_power += pwr_delta + nss_delta; |
| + target_power = DIV_ROUND_UP(target_power, 2); |
| + len += scnprintf(buf + len, sz - len, "eeprom maximum power:\t%d [dBm]\n", |
| + target_power); |
| + |
| + len += scnprintf(buf + len, sz - len, "nss_delta:\t%d [0.5 dBm]\n", |
| + nss_delta); |
| |
| ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
| |
| @@ -1263,6 +1296,8 @@ static int |
| mt7915_txpower_info_show(struct seq_file *file, void *data) |
| { |
| struct mt7915_phy *phy = file->private; |
| + struct mt76_phy *mphy = phy->mt76; |
| + struct mt76_dev *dev = mphy->dev; |
| struct { |
| u8 category; |
| u8 rsv1; |
| @@ -1304,6 +1339,7 @@ mt7915_txpower_info_show(struct seq_file *file, void *data) |
| s8 mu_tx_power_manual; |
| u8 rsv3; |
| } __packed basic_info = {}; |
| + struct device_node *np; |
| int ret; |
| |
| ret = mt7915_mcu_get_txpower_sku(phy, (s8 *)&basic_info, sizeof(basic_info), |
| @@ -1338,6 +1374,9 @@ mt7915_txpower_info_show(struct seq_file *file, void *data) |
| seq_printf(file, " Theraml Compensation Value: %d\n", |
| basic_info.thermal_compensate_value); |
| |
| + np = mt76_find_power_limits_node(dev); |
| + seq_printf(file, " RegDB: %s\n", !np ? "enable" : "disable"); |
| + |
| out: |
| return ret; |
| } |
| diff --git a/mt7915/init.c b/mt7915/init.c |
| index 20d6efd..4fa48fb 100644 |
| --- a/mt7915/init.c |
| +++ b/mt7915/init.c |
| @@ -283,9 +283,11 @@ static void __mt7915_init_txpower(struct mt7915_phy *phy, |
| int nss_delta = mt76_tx_power_nss_delta(n_chains); |
| int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); |
| struct mt76_power_limits limits; |
| + struct device_node *np; |
| |
| phy->sku_limit_en = true; |
| phy->sku_path_en = true; |
| + np = mt76_find_power_limits_node(&dev->mt76); |
| for (i = 0; i < sband->n_channels; i++) { |
| struct ieee80211_channel *chan = &sband->channels[i]; |
| u32 target_power = 0; |
| @@ -309,8 +311,13 @@ static void __mt7915_init_txpower(struct mt7915_phy *phy, |
| |
| target_power += nss_delta; |
| target_power = DIV_ROUND_UP(target_power, 2); |
| - chan->max_power = min_t(int, chan->max_reg_power, |
| - target_power); |
| + |
| + /* can NOT find country node in dts */ |
| + if (!np) |
| + chan->max_power = min_t(int, chan->max_reg_power, |
| + target_power); |
| + else |
| + chan->max_power = target_power; |
| chan->orig_mpwr = target_power; |
| } |
| } |
| diff --git a/mt7915/regs.h b/mt7915/regs.h |
| index 4d05e39..ca355d1 100644 |
| --- a/mt7915/regs.h |
| +++ b/mt7915/regs.h |
| @@ -1215,6 +1215,10 @@ enum offs_rev { |
| #define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16)) |
| #define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16)) |
| |
| +#define MT_WF_IRPI_TPC_CTRL_STAT(_phy) MT_WF_IRPI(0xc794 + ((_phy) << 16)) |
| +#define MT_WF_IRPI_TPC_CTRL_STAT_MT7916(_phy) MT_WF_IRPI(0xc794 + ((_phy) << 20)) |
| +#define MT_WF_IRPI_TPC_POWER GENMASK(31, 24) |
| + |
| #define MT_WF_IPI_RESET 0x831a3008 |
| |
| /* PHY */ |
| @@ -1231,10 +1235,6 @@ enum offs_rev { |
| #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18) |
| #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29) |
| |
| -#define MT_WF_PHY_TPC_CTRL_STAT(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 16)) |
| -#define MT_WF_PHY_TPC_CTRL_STAT_MT7916(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 20)) |
| -#define MT_WF_PHY_TPC_POWER GENMASK(15, 8) |
| - |
| #define MT_MCU_WM_CIRQ_BASE 0x89010000 |
| #define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs)) |
| #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80) |
| -- |
| 2.18.0 |
| |