[rdkb][common][bsp][Refactor and sync kernel from openwrt]
[Description]
7a58a57 [kernel][mt7988][cpu][Fix syntax error for the PMU node]
1d8c40e [kernel][mt7988][eth][phy: mediatek-2p5ge: Fix duplex detection]
8e0e0a0 [kernel][mt798x][spim-nand][mtd: spinand: Fix W25N02/04KVZEIR ECCREQ]
22e03cd [kernel][mt7988][eth][Remove phy init config in mt753x driver]
1169881 [mt7988][gps][Add uart1 for Airoha gnss server anld]
[Release-log]
Change-Id: I58ccda4e6a262760af57d1c0e9c130edd62f8f0c
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
index 364deef..bae7604 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -115,7 +115,7 @@
pmu {
compatible = "arm,cortex-a73-pmu";
interrupt-parent = <&gic>;
- interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
thermal-zones {
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
index e4630ae..c4a9288 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
@@ -110,6 +110,12 @@
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@@ -336,6 +342,13 @@
groups = "pcm";
};
};
+
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";
+ groups = "uart1_2";
+ };
+ };
};
&watchdog {
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c
index f5964c3..32ae8ea 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c
@@ -22,6 +22,10 @@
#define PHY_AUX_DPX_MASK GENMASK(5, 5)
#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
+/* Registers on MDIO_MMD_VEND1 */
+#define MTK_PHY_LINK_STATUS_MISC (0xa2)
+#define MTK_PHY_FDX_ENABLE BIT(5)
+
/* Registers on MDIO_MMD_VEND2 */
#define MTK_PHY_LED0_ON_CTRL (0x24)
#define MTK_PHY_LED0_POLARITY BIT(14)
@@ -190,8 +194,6 @@
if (ret < 0)
return ret;
- /* Actually this phy supports only FDX */
- phydev->duplex = (ret & PHY_AUX_DPX_MASK) ? DUPLEX_FULL : DUPLEX_HALF;
switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
case PHY_AUX_SPD_10:
phydev->speed = SPEED_10;
@@ -204,10 +206,14 @@
break;
case PHY_AUX_SPD_2500:
phydev->speed = SPEED_2500;
- phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
break;
}
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
+ if (ret < 0)
+ return ret;
+ phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
+
return 0;
}
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c
index 04e6b4e..b27c679 100755
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mtk/mt753x/mt7531.c
@@ -832,8 +832,7 @@
u32 val;
for (i = 0; i < MT753X_NUM_PHYS; i++) {
- if (!gsw->direct_access)
- mt7531_phy_100m_eye_diag_setting(gsw, i);
+ mt7531_phy_100m_eye_diag_setting(gsw, i);
/* Enable HW auto downshift */
gsw->mii_write(gsw, i, 0x1f, 0x1);
@@ -857,14 +856,12 @@
val |= PHY_LINKDOWN_POWER_SAVING_EN;
gsw->mii_write(gsw, i, PHY_EXT_REG_17, val);
- if (!gsw->direct_access) {
- val = gsw->mmd_read(gsw, i, PHY_DEV1E,
- PHY_DEV1E_REG_0C6);
- val &= ~PHY_POWER_SAVING_M;
- val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
- gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6,
- val);
- }
+ val = gsw->mmd_read(gsw, i, PHY_DEV1E,
+ PHY_DEV1E_REG_0C6);
+ val &= ~PHY_POWER_SAVING_M;
+ val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
+ gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6,
+ val);
/* Timing Recovery for GbE slave mode */
mt753x_tr_write(gsw, i, PMA_CH, PMA_NOD, PMA_01, 0x6fb90a);
@@ -898,8 +895,7 @@
gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_273, 0x3000);
/* Adjust RX Echo path filter */
- if (!gsw->direct_access)
- gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_0FE, 0x2);
+ gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_0FE, 0x2);
/* Adjust RX HVGA bias current */
gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_41, 0x3333);
@@ -1071,12 +1067,6 @@
gsw->mmd_read = mt753x_mmd_read;
gsw->mmd_write = mt753x_mmd_write;
- for (i = 0; i < MT753X_NUM_PHYS; i++) {
- val = gsw->mii_read(gsw, i, MII_BMCR);
- val |= BMCR_ISOLATE;
- gsw->mii_write(gsw, i, MII_BMCR, val);
- }
-
speed = MAC_SPD_1000;
pmcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
MAC_MODE | MAC_TX_EN | MAC_RX_EN | BKOFF_EN |
@@ -1103,12 +1093,6 @@
/* Disable AFIFO reset for extra short IPG */
mt7531_afifo_reset(gsw, 0);
- /* PHY force slave 1G*/
- for (i = 0; i < MT753X_NUM_PHYS; i++) {
- gsw->mii_write(gsw, i, MII_CTRL1000, 0x1200);
- gsw->mii_write(gsw, i, MII_BMCR, 0x140);
- }
-
return 0;
}
@@ -1129,8 +1113,7 @@
val |= POWER_ON_OFF;
gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);
- if (!gsw->direct_access)
- mt7531_phy_pll_setup(gsw);
+ mt7531_phy_pll_setup(gsw);
/* Enable Internal PHYs before phy setting */
val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403);
@@ -1155,8 +1138,7 @@
for (i = 0; i < MT753X_NUM_PHYS; i++)
gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_141, 0x0);
- if (!gsw->direct_access)
- mt7531_internal_phy_calibration(gsw);
+ mt7531_internal_phy_calibration(gsw);
/* PHY force slave disable, restart AN*/
for (i = 0; i < MT753X_NUM_PHYS; i++) {
@@ -1178,7 +1160,6 @@
.model = MT7988,
.detect = mt7988_sw_detect,
.init = mt7988_sw_init,
- .post_init = mt7531_sw_post_init
};
MODULE_LICENSE("GPL");
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0490-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0490-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch
index 860a8d9..6d2a4b8 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0490-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0490-mtd-spinand-winbond-Support-for-W25MxxGV-W25NxxKV-series.patch
@@ -144,7 +144,7 @@
+ SPINAND_INFO("W25N02KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
-+ NAND_ECCREQ(4, 512),
++ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
@@ -157,7 +157,7 @@
+ SPINAND_INFO("W25N04KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
-+ NAND_ECCREQ(4, 512),
++ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),