diff --git a/conf/machine/filogic.conf b/conf/machine/filogic.conf
index ba34a68..22711e7 100644
--- a/conf/machine/filogic.conf
+++ b/conf/machine/filogic.conf
@@ -32,7 +32,9 @@
 KERNEL_DEVICETREE_mt7988_bpi4 = " \
     mediatek/mt7988a-bananapi-bpi-r4-nand.dtb \
     "
-
+KERNEL_DEVICETREE_mt7987 = " \
+    mediatek/mt7987a-spim-nand.dtb \
+    "
 KERNEL_DEVICETREE_mt7986_gsw = " \
     mediatek/mt7986a-2500wan-gsw-spim-nand-rfb.dtb \
     mediatek/mt7986b-2500wan-gsw-spim-nand-rfb.dtb \
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-clkitg.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-clkitg.dtsi
new file mode 100644
index 0000000..c90f4ec
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-clkitg.dtsi
@@ -0,0 +1,265 @@
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+&clkitg {
+	status = "okay";
+	bringup {
+		compatible = "mediatek,clk-bring-up";
+		clocks =
+			<&apmixedsys CK_APMIXED_MPLL>,
+			<&apmixedsys CK_APMIXED_APLL2>,
+			<&apmixedsys CK_APMIXED_NET1PLL>,
+			<&apmixedsys CK_APMIXED_NET2PLL>,
+			<&apmixedsys CK_APMIXED_WEDMCUPLL>,
+			<&apmixedsys CK_APMIXED_SGMPLL>,
+			<&apmixedsys CK_APMIXED_ARM_LL>,
+			<&apmixedsys CK_APMIXED_MSDCPLL>,
+			<&topckgen CK_TOP_CB_M_D2>,
+			<&topckgen CK_TOP_CB_M_D3>,
+			<&topckgen CK_TOP_M_D3_D2>,
+			<&topckgen CK_TOP_CB_M_D4>,
+			<&topckgen CK_TOP_CB_M_D8>,
+			<&topckgen CK_TOP_M_D8_D2>,
+			<&topckgen CK_TOP_CB_APLL2_196M>,
+			<&topckgen CK_TOP_CB_APLL2_D4>,
+			<&topckgen CK_TOP_CB_NET1_D3>,
+			<&topckgen CK_TOP_CB_NET1_D4>,
+			<&topckgen CK_TOP_CB_NET1_D5>,
+			<&topckgen CK_TOP_NET1_D5_D2>,
+			<&topckgen CK_TOP_NET1_D5_D4>,
+			<&topckgen CK_TOP_CB_NET1_D7>,
+			<&topckgen CK_TOP_NET1_D7_D2>,
+			<&topckgen CK_TOP_NET1_D7_D4>,
+			<&topckgen CK_TOP_NET1_D8_D2>,
+			<&topckgen CK_TOP_NET1_D8_D4>,
+			<&topckgen CK_TOP_NET1_D8_D8>,
+			<&topckgen CK_TOP_NET1_D8_D16>,
+			<&topckgen CK_TOP_CB_NET2_800M>,
+			<&topckgen CK_TOP_CB_NET2_D2>,
+			<&topckgen CK_TOP_CB_NET2_D4>,
+			<&topckgen CK_TOP_NET2_D4_D4>,
+			<&topckgen CK_TOP_NET2_D4_D8>,
+			<&topckgen CK_TOP_CB_NET2_D6>,
+			<&topckgen CK_TOP_NET2_D7_D2>,
+			<&topckgen CK_TOP_CB_NET2_D8>,
+			<&topckgen CK_TOP_CB_WEDMCU_208M>,
+			<&topckgen CK_TOP_CB_SGM_325M>,
+			<&topckgen CK_TOP_CB_MSDC_416M>,
+			<&topckgen CK_TOP_MSDC_D2>,
+			<&topckgen CK_TOP_CB_CKSQ_40M>,
+			<&topckgen CK_TOP_CKSQ_40M_D2>,
+			<&topckgen CK_TOP_CB_RTC_32K>,
+			<&topckgen CK_TOP_CB_RTC_32P7K>,
+			<&topckgen CK_TOP_NETSYS_2X>,
+			<&topckgen CK_TOP_EMMC_250M>,
+			<&topckgen CK_TOP_EMMC_400M>,
+			<&topckgen CK_TOP_NFI_BCK>,
+			<&topckgen CK_TOP_I2C_BCK>,
+			<&topckgen CK_TOP_USB_SYS_P1>,
+			<&topckgen CK_TOP_USB_XHCI_P1>,
+			<&topckgen CK_TOP_AUD>,
+			<&topckgen CK_TOP_A1SYS>,
+			<&topckgen CK_TOP_AUD_L>,
+			<&topckgen CK_TOP_A_TUNER>,
+			<&topckgen CK_TOP_SYSAXI>,
+			<&topckgen CK_TOP_INFRA_F26M>,
+			<&topckgen CK_TOP_EMMC_200M>,
+			<&topckgen CK_TOP_USB_FRMCNT_P1>,
+			<&topckgen CK_TOP_USB_CK_P1>,
+			<&topckgen CK_TOP_AUD_I2S_M>,
+			<&topckgen CK_TOP_NETSYS_SEL>,
+			<&topckgen CK_TOP_NETSYS_500M_SEL>,
+			<&topckgen CK_TOP_NETSYS_2X_SEL>,
+			<&topckgen CK_TOP_ETH_GMII_SEL>,
+			<&topckgen CK_TOP_EIP_SEL>,
+			<&topckgen CK_TOP_AXI_INFRA_SEL>,
+			<&topckgen CK_TOP_UART_SEL>,
+			<&topckgen CK_TOP_EMMC_250M_SEL>,
+			<&topckgen CK_TOP_EMMC_400M_SEL>,
+			<&topckgen CK_TOP_SPI_SEL>,
+			<&topckgen CK_TOP_SPIM_MST_SEL>,
+			<&topckgen CK_TOP_NFI_SEL>,
+			<&topckgen CK_TOP_PWM_SEL>,
+			<&topckgen CK_TOP_I2C_SEL>,
+			<&topckgen CK_TOP_PCIE_MBIST_250M_SEL>,
+			<&topckgen CK_TOP_PEXTP_TL_SEL>,
+			<&topckgen CK_TOP_PEXTP_TL_P1_SEL>,
+			<&topckgen CK_TOP_USB_SYS_P1_SEL>,
+			<&topckgen CK_TOP_USB_XHCI_P1_SEL>,
+			<&topckgen CK_TOP_AUD_SEL>,
+			<&topckgen CK_TOP_A1SYS_SEL>,
+			<&topckgen CK_TOP_AUD_L_SEL>,
+			<&topckgen CK_TOP_A_TUNER_SEL>,
+			<&topckgen CK_TOP_USB_PHY_SEL>,
+			<&topckgen CK_TOP_SGM_0_SEL>,
+			<&topckgen CK_TOP_SGM_SBUS_0_SEL>,
+			<&topckgen CK_TOP_SGM_1_SEL>,
+			<&topckgen CK_TOP_SGM_SBUS_1_SEL>,
+			<&topckgen CK_TOP_SYSAXI_SEL>,
+			<&topckgen CK_TOP_SYSAPB_SEL>,
+			<&topckgen CK_TOP_ETH_REFCK_50M_SEL>,
+			<&topckgen CK_TOP_ETH_SYS_200M_SEL>,
+			<&topckgen CK_TOP_ETH_SYS_SEL>,
+			<&topckgen CK_TOP_ETH_XGMII_SEL>,
+			<&topckgen CK_TOP_DRAMC_SEL>,
+			<&topckgen CK_TOP_DRAMC_MD32_SEL>,
+			<&topckgen CK_TOP_INFRA_F26M_SEL>,
+			<&topckgen CK_TOP_PEXTP_P0_SEL>,
+			<&topckgen CK_TOP_PEXTP_P1_SEL>,
+			<&topckgen CK_TOP_DA_XTP_GLB_P0_SEL>,
+			<&topckgen CK_TOP_DA_XTP_GLB_P1_SEL>,
+			<&topckgen CK_TOP_CKM_SEL>,
+			<&topckgen CK_TOP_DA_CKM_XTAL_SEL>,
+			<&topckgen CK_TOP_PEXTP_SEL>,
+			<&topckgen CK_TOP_ETH_MII_SEL>,
+			<&topckgen CK_TOP_EMMC_200M_SEL>,
+			<&infracfg_ao CK_INFRA_CK_F26M>,
+			<&infracfg_ao CK_INFRA_PWM_O>,
+			<&infracfg_ao CK_INFRA_INFRA_F32K>,
+			<&infracfg_ao CK_INFRA_PCIE_OCC_P0>,
+			<&infracfg_ao CK_INFRA_PCIE_OCC_P1>,
+			<&infracfg_ao CK_INFRA_133M_HCK>,
+			<&infracfg_ao CK_INFRA_133M_PHCK>,
+			<&infracfg_ao CK_INFRA_66M_PHCK>,
+			<&infracfg_ao CK_INFRA_FAUD_L_O>,
+			<&infracfg_ao CK_INFRA_FAUD_AUD_O>,
+			<&infracfg_ao CK_INFRA_FAUD_EG2_O>,
+			<&infracfg_ao CK_INFRA_I2C_O>,
+			<&infracfg_ao CK_INFRA_UART_O0>,
+			<&infracfg_ao CK_INFRA_UART_O1>,
+			<&infracfg_ao CK_INFRA_UART_O2>,
+			<&infracfg_ao CK_INFRA_NFI_O>,
+			<&infracfg_ao CK_INFRA_SPI0_O>,
+			<&infracfg_ao CK_INFRA_SPI1_O>,
+			<&infracfg_ao CK_INFRA_SPI2_O>,
+			<&infracfg_ao CK_INFRA_LB_MUX_FRTC>,
+			<&infracfg_ao CK_INFRA_FRTC>,
+			<&infracfg_ao CK_INFRA_FMSDC200_SRC_O>,
+			<&infracfg_ao CK_INFRA_FMSDC400_O>,
+			<&infracfg_ao CK_INFRA_FMSDC2_HCK_OCC>,
+			<&infracfg_ao CK_INFRA_PERI_133M>,
+			<&infracfg_ao CK_INFRA_USB_O_P1>,
+			<&infracfg_ao CK_INFRA_USB_FRMCNT_O_P1>,
+			<&infracfg_ao CK_INFRA_USB_XHCI_O_P1>,
+			<&infracfg_ao CK_INFRA_USB_PIPE_O_P1>,
+			<&infracfg_ao CK_INFRA_USB_UTMI_O_P1>,
+			<&infracfg_ao CK_INFRA_PCIE_PIPE_OCC_P0>,
+			<&infracfg_ao CK_INFRA_PCIE_PIPE_OCC_P1>,
+			<&infracfg_ao CK_INFRA_F26M_O0>,
+			<&infracfg_ao CK_INFRA_F26M_O1>,
+			<&infracfg_ao CK_INFRA_133M_MCK>,
+			<&infracfg_ao CK_INFRA_66M_MCK>,
+			<&infracfg_ao CK_INFRA_PERI_66M_O>,
+			<&infracfg_ao CK_INFRA_USB_SYS_O_P1>,
+			<&infracfg_ao CK_INFRA_66M_GPT_BCK>,
+			<&infracfg_ao CK_INFRA_66M_PWM_HCK>,
+			<&infracfg_ao CK_INFRA_66M_PWM_BCK>,
+			<&infracfg_ao CK_INFRA_133M_CQDMA_BCK>,
+			<&infracfg_ao CK_INFRA_66M_AUD_SLV_BCK>,
+			<&infracfg_ao CK_INFRA_AUD_26M>,
+			<&infracfg_ao CK_INFRA_AUD_L>,
+			<&infracfg_ao CK_INFRA_AUD_AUD>,
+			<&infracfg_ao CK_INFRA_AUD_EG2>,
+			<&infracfg_ao CK_INFRA_DRAMC_F26M>,
+			<&infracfg_ao CK_INFRA_133M_DBG_ACKM>,
+			<&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>,
+			<&infracfg_ao CK_INFRA_MSDC200_SRC>,
+			<&infracfg_ao CK_INFRA_66M_SEJ_BCK>,
+			<&infracfg_ao CK_INFRA_PRE_CK_SEJ_F13M>,
+			<&infracfg_ao CK_INFRA_66M_TRNG>,
+			<&infracfg_ao CK_INFRA_26M_THERM_SYSTEM>,
+			<&infracfg_ao CK_INFRA_I2C_BCK>,
+			<&infracfg_ao CK_INFRA_66M_UART0_PCK>,
+			<&infracfg_ao CK_INFRA_66M_UART1_PCK>,
+			<&infracfg_ao CK_INFRA_66M_UART2_PCK>,
+			<&infracfg_ao CK_INFRA_52M_UART0_CK>,
+			<&infracfg_ao CK_INFRA_52M_UART1_CK>,
+			<&infracfg_ao CK_INFRA_52M_UART2_CK>,
+			<&infracfg_ao CK_INFRA_NFI>,
+			<&infracfg_ao CK_INFRA_66M_NFI_HCK>,
+			<&infracfg_ao CK_INFRA_104M_SPI0>,
+			<&infracfg_ao CK_INFRA_104M_SPI1>,
+			<&infracfg_ao CK_INFRA_104M_SPI2_BCK>,
+			<&infracfg_ao CK_INFRA_66M_SPI0_HCK>,
+			<&infracfg_ao CK_INFRA_66M_SPI1_HCK>,
+			<&infracfg_ao CK_INFRA_66M_SPI2_HCK>,
+			<&infracfg_ao CK_INFRA_66M_FLASHIF_AXI>,
+			<&infracfg_ao CK_INFRA_RTC>,
+			<&infracfg_ao CK_INFRA_26M_ADC_BCK>,
+			<&infracfg_ao CK_INFRA_RC_ADC>,
+			<&infracfg_ao CK_INFRA_MSDC400>,
+			<&infracfg_ao CK_INFRA_MSDC2_HCK>,
+			<&infracfg_ao CK_INFRA_133M_MSDC_0_HCK>,
+			<&infracfg_ao CK_INFRA_66M_MSDC_0_HCK>,
+			<&infracfg_ao CK_INFRA_133M_CPUM_BCK>,
+			<&infracfg_ao CK_INFRA_BIST2FPC>,
+			<&infracfg_ao CK_INFRA_I2C_X16W_MCK_CK_P1>,
+			<&infracfg_ao CK_INFRA_I2C_X16W_PCK_CK_P1>,
+			<&infracfg_ao CK_INFRA_133M_USB_HCK>,
+			<&clk40m>,
+			<&infracfg_ao CK_INFRA_66M_USB_HCK>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&infracfg_ao CK_INFRA_USB_FRMCNT_CK_P1>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&clk40m>,
+			<&infracfg_ao CK_INFRA_MUX_UART0_SEL>,
+			<&infracfg_ao CK_INFRA_MUX_UART1_SEL>,
+			<&infracfg_ao CK_INFRA_MUX_UART2_SEL>,
+			<&infracfg_ao CK_INFRA_MUX_SPI0_SEL>,
+			<&infracfg_ao CK_INFRA_MUX_SPI1_SEL>,
+			<&infracfg_ao CK_INFRA_MUX_SPI2_BCK_SEL>,
+			<&infracfg_ao CK_INFRA_PWM_BCK_SEL>,
+			<&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL>,
+			<&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL>,
+			<&ethsys CK_ETHDMA_FE_EN>,
+			<&sgmiisys0 CK_SGM0_TX_EN>,
+			<&sgmiisys0 CK_SGM0_RX_EN>,
+			<&sgmiisys1 CK_SGM1_TX_EN>,
+			<&sgmiisys1 CK_SGM1_RX_EN>;
+
+		clock-names = "0", "1", "2", "3", "4", "5", "6", "7", "8", "9",
+			      "10", "11", "12", "13", "14", "15", "16", "17",
+			      "18", "19", "20", "21", "22", "23", "24", "25",
+			      "26", "27", "28", "29", "30", "31", "32", "33",
+			      "34", "35", "36", "37", "38", "39", "40", "41",
+			      "42", "43", "44", "45", "46", "47", "48", "49",
+			      "50", "51", "52", "53", "54", "55", "56", "57",
+			      "58", "59", "60", "61", "62", "63", "64", "65",
+			      "66", "67", "68", "69", "70", "71", "72", "73",
+			      "74", "75", "76", "77", "78", "79", "80", "81",
+			      "82", "83", "84", "85", "86", "87", "88", "89",
+			      "90", "91", "92", "93", "94", "95", "96", "97",
+			      "98", "99", "100", "101", "102", "103", "104",
+			      "105", "106", "107", "108", "109", "110", "111",
+			      "112", "113", "114", "115", "116", "117", "118",
+			      "119", "120", "121", "122", "123", "124", "125",
+			      "126", "127", "128", "129", "130", "131", "132",
+			      "133", "134", "135", "136", "137", "138", "139",
+			      "140", "141", "142", "143", "144", "145", "146",
+			      "147", "148", "149", "150", "151", "152", "153",
+			      "154", "155", "156", "157", "158", "159", "160",
+			      "161", "162", "163", "164", "165", "166", "167",
+			      "168", "169", "170", "171", "172", "173", "174",
+			      "175", "176", "177", "178", "179", "180", "181",
+			      "182", "183", "184", "185", "186", "187", "188",
+			      "189", "190", "191", "192", "193", "194", "195",
+			      "196", "197", "198", "199", "200", "201", "202",
+			      "203", "204", "205", "206", "207", "208", "209",
+			      "210", "211", "212", "213", "214", "215", "216",
+			      "217", "218", "219", "220";
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-emmc.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-emmc.dtsi
new file mode 100644
index 0000000..19ab2dd
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-emmc.dtsi
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#include "mt7987-pinctrl.dtsi"
+
+/ {
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+/* Disable spi1 node since MSDC and spi1 share pins on MT7987. */
+&spi1 {
+	status = "disabled";
+};
+
+&mmc0 {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc_pins_default>;
+	pinctrl-1 = <&mmc_pins_uhs>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	cap-mmc-highspeed;
+	vqmmc-supply = <&reg_3p3v>;
+	vmmc-supply = <&reg_3p3v>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	status = "okay";
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-emmc.dtso b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-emmc.dtso
new file mode 100644
index 0000000..dc21385
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-emmc.dtso
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	fragment@0 {
+		target = <&mmc0>;
+		__overlay__ {
+			pinctrl-names = "default", "state_uhs";
+			pinctrl-0 = <&mmc_pins_default>;
+			pinctrl-1 = <&mmc_pins_uhs>;
+			bus-width = <8>;
+			max-frequency = <200000000>;
+			cap-mmc-highspeed;
+			vqmmc-supply = <&reg_3p3v>;
+			vmmc-supply = <&reg_3p3v>;
+			non-removable;
+			no-sd;
+			no-sdio;
+			status = "okay";
+		};
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-netsys-evb.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-netsys-evb.dtsi
new file mode 100644
index 0000000..9d22714
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-netsys-evb.dtsi
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "mt7987-netsys.dtsi"
+
+&mdio {
+	phy12: phy@12 {
+		compatible = "ethernet-phy-id03a2.a411";
+		reg = <12>;
+		reset-gpios = <&pio 49 1>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <10000>;
+		phy-mode = "2500base-x";
+		full-duplex;
+		pause;
+		airoha,polarity = <3>;
+		airoha,surge = <0>;
+	};
+
+	/delete-node/ switch@1;
+	switch31: switch@31 {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		reset-gpios = <&pio 42 0>;
+	};
+
+};
+
+&switch31 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan0";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan1";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan2";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan3";
+		};
+
+		port@5 {
+			reg = <5>;
+			label = "lan5";
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+
+		port@6 {
+			reg = <6>;
+			label = "cpu";
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};
\ No newline at end of file
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-netsys.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-netsys.dtsi
new file mode 100644
index 0000000..9d39336
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-netsys.dtsi
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+#include <dt-bindings/clock/mt7987-clk.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+&netsys {
+	ethwarp: syscon@15031000 {
+		compatible = "mediatek,mt7988-ethwarp", "syscon";
+		reg = <0 0x15031000 0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	eth: ethernet@15100000 {
+		compatible = "mediatek,mt7987-eth";
+		reg = <0 0x15100000 0 0x80000>,
+		      <0 0x15400000 0 0x20000>;
+		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&ethsys CK_ETHDMA_FE_EN>,
+		         <&ethsys CK_ETHDMA_GP2_EN>,
+			 <&ethsys CK_ETHDMA_GP1_EN>,
+			 <&ethsys CK_ETHDMA_GP3_EN>,
+			 <&sgmiisys0 CK_SGM0_TX_EN>,
+			 <&sgmiisys0 CK_SGM0_RX_EN>,
+			 <&sgmiisys1 CK_SGM1_TX_EN>,
+			 <&sgmiisys1 CK_SGM1_RX_EN>,
+			 <&topckgen CK_TOP_SGM_0_SEL>,
+			 <&topckgen CK_TOP_SGM_1_SEL>,
+			 <&topckgen CK_TOP_ETH_GMII_SEL>,
+			 <&topckgen CK_TOP_ETH_REFCK_50M_SEL>,
+			 <&topckgen CK_TOP_ETH_SYS_200M_SEL>,
+			 <&topckgen CK_TOP_ETH_SYS_SEL>,
+			 <&topckgen CK_TOP_ETH_XGMII_SEL>,
+			 <&topckgen CK_TOP_ETH_MII_SEL>,
+			 <&topckgen CK_TOP_NETSYS_SEL>,
+			 <&topckgen CK_TOP_NETSYS_500M_SEL>,
+			 <&topckgen CK_TOP_NETSYS_2X_SEL>;
+		clock-names = "fe", "gp2", "gp1", "gp3", "sgmii_tx250m",
+			      "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
+			      "top_sgm0_sel", "top_sgm1_sel", "top_eth_gmii_sel",
+			      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
+			      "top_eth_sys_sel", "top_eth_xgmii_sel",
+			      "top_eth_mii_sel", "top_netsys_sel",
+			      "top_netsys_500m_sel", "top_netsys_pao_2x_sel";
+		assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
+				  <&topckgen CK_TOP_SGM_0_SEL>,
+				  <&topckgen CK_TOP_SGM_1_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>,
+					 <&topckgen CK_TOP_CB_SGM_325M>,
+					 <&topckgen CK_TOP_CB_SGM_325M>;
+		mediatek,ethsys = <&ethsys>;
+		mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
+		mediatek,infracfg = <&topmisc>;
+		#reset-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		gmac0: mac@0 {
+			compatible = "mediatek,eth-mac";
+			reg = <0>;
+			mac-type = "gdm";
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+
+		gmac1: mac@1 {
+			compatible = "mediatek,eth-mac";
+			reg = <1>;
+			mac-type = "xgdm";
+			phy-mode = "internal";
+			phy-handle = <&phy15>;
+		};
+
+		gmac2: mac@2 {
+			compatible = "mediatek,eth-mac";
+			reg = <2>;
+			mac-type = "gdm";
+			phy-mode = "2500base-x";
+			phy-handle = <&phy11>;
+		};
+
+		mdio: mdio-bus {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reset-gpios = <&pio 48 1>;
+			reset-delay-us = <10000>;
+
+			phy11: phy@11 {
+				compatible = "ethernet-phy-id03a2.a411";
+				reg = <11>;
+				phy-mode = "2500base-x";
+				airoha,polarity = <1>;
+				airoha,surge = <0>;
+			};
+
+			phy15: phy@15 {
+				pinctrl-names = "i2p5gbe-led";
+				pinctrl-0 = <&i2p5gbe_led0_pins>;
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <15>;
+				phy-mode = "internal";
+			};
+
+			switch1: switch@1 {
+				compatible = "airoha,an8855";
+				reg = <1>;
+				airoha,extSurge = <1>;
+				reset-gpios = <&pio 42 0>;
+			};
+		};
+	};
+
+	hnat: hnat@15000000 {
+		compatible = "mediatek,mtk-hnat_v5";
+		reg = <0 0x15100000 0 0x80000>;
+		resets = <&ethsys 0>;
+		reset-names = "mtketh";
+		status = "disabled";
+	};
+
+	crypto: crypto@15600000 {
+		compatible = "inside-secure,safexcel-eip197b",
+			     "security-ip-197-srv";
+		reg = <0 0x15600000 0 0x180000>;
+		interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "ring0", "ring1", "ring2", "ring3";
+		eth = <&eth>;
+		status = "disabled";
+	};
+};
+
+&crypto {
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+};
+
+&hnat {
+	mtketh-wan = "eth1";
+	mtketh-lan = "lan";
+	mtketh-lan2 = "eth2";
+	mtketh-max-gmac = <3>;
+	mtketh-ppe-num = <2>;
+	status = "okay";
+};
+
+&switch1 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan0";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan1";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan2";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan3";
+		};
+
+		port@5 {
+			reg = <5>;
+			label = "cpu";
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-pinctrl.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-pinctrl.dtsi
new file mode 100644
index 0000000..afd2d96
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-pinctrl.dtsi
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+&pio {
+	mmc_pins_default: mmc-pins-default {
+		mux {
+			function = "flash";
+			groups = "emmc_45";
+		};
+		conf-cmd-dat {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+			       "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
+			       "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+			input-enable;
+			drive-strength = <MTK_DRIVE_4mA>;
+			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
+		};
+		conf-clk {
+			pins = "SPI1_CS";
+			drive-strength = <MTK_DRIVE_6mA>;
+			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
+		};
+		conf-rst {
+			pins = "USB_VBUS";
+			drive-strength = <MTK_DRIVE_4mA>;
+			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
+		};
+	};
+
+	mmc_pins_uhs: mmc-pins-uhs {
+		mux {
+			function = "flash";
+			groups = "emmc_45";
+		};
+		conf-cmd-dat {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+			       "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
+			       "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+			input-enable;
+			drive-strength = <MTK_DRIVE_4mA>;
+			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
+		};
+		conf-clk {
+			pins = "SPI1_CS";
+			drive-strength = <MTK_DRIVE_6mA>;
+			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
+		};
+		conf-rst {
+			pins = "USB_VBUS";
+			drive-strength = <MTK_DRIVE_4mA>;
+			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
+		};
+	};
+
+	sd_pins_default: sd-pins-default {
+		mux {
+			function = "flash";
+			groups = "sd";
+		};
+		conf-cmd-dat {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+			       "SPI0_CS", "SPI1_MISO";
+			input-enable;
+			drive-strength = <MTK_DRIVE_4mA>;
+			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
+		};
+		conf-clk {
+			pins = "SPI1_CS";
+			drive-strength = <MTK_DRIVE_6mA>;
+			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
+		};
+	};
+
+	sd_pins_uhs: sd-pins-uhs {
+		mux {
+			function = "flash";
+			groups = "sd";
+		};
+		conf-cmd-dat {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
+			       "SPI0_CS", "SPI1_MISO";
+			input-enable;
+			drive-strength = <MTK_DRIVE_4mA>;
+			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
+		};
+		conf-clk {
+			pins = "SPI1_CS";
+			drive-strength = <MTK_DRIVE_6mA>;
+			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
+		};
+	};
+
+	mdio0_pins: mdio0-pins {
+		mux {
+			function = "mdio";
+			groups = "mdc_mdio";
+		};
+
+		conf {
+			groups = "mdc_mdio";
+			drive-strength = <MTK_DRIVE_10mA>;
+		};
+	};
+
+	i2p5gbe_led0_pins: i2p5gbe0-pins {
+		mux {
+			function = "led";
+			groups = "2p5gbe_led0";
+		};
+	};
+
+	i2p5gbe_led1_0_pins: i2p5gbe1-pins {
+		mux {
+			function = "led";
+			groups = "2p5gbe_led1_0";
+		};
+	};
+
+	i2p5gbe_led1_1_pins: i2p5gbe2-pins {
+		mux {
+			function = "led";
+			groups = "2p5gbe_led1_1";
+		};
+	};
+
+	i2c0_pins: i2c0-pins-g2 {
+		mux {
+			function = "i2c";
+			groups = "i2c0_2";
+		};
+	};
+
+	pcie0_pins: pcie0-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie0_pereset", "pcie0_clkreq",
+				 "pcie0_wake";
+		};
+	};
+
+	pcie1_pins: pcie1-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie1_pereset", "pcie1_clkreq",
+				 "pcie1_wake";
+		};
+	};
+
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+	};
+
+	spic_pins: spi1-pins {
+		mux {
+			function = "spi";
+			groups = "spi1";
+		};
+	};
+
+	spi2_flash_pins: spi2-pins {
+		mux {
+			function = "spi";
+			groups = "spi2", "spi2_wp_hold";
+		};
+	};
+
+	i2c1_pins: i2c1-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c0_2";
+		};
+	};
+
+	i2s_pins: i2s-pins {
+		mux {
+			function = "i2s";
+			groups = "pcm0_1";
+		};
+	};
+
+	pcm_pins: pcm-pins {
+		mux {
+			function = "pcm";
+			groups = "pcm0_1";
+		};
+	};
+
+	uart1_pins: uart1-pins {
+		mux {
+			function = "uart";
+			groups = "uart1_2";
+		};
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-sd.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-sd.dtsi
new file mode 100644
index 0000000..fe8592e
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-sd.dtsi
@@ -0,0 +1,31 @@
+#include "mt7987-pinctrl.dtsi"
+
+/ {
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+/* Disable spi1 node since MSDC and spi1 share pins on MT7987. */
+&spi1 {
+	status = "disabled";
+};
+
+&mmc0 {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&sd_pins_default>;
+	pinctrl-1 = <&sd_pins_uhs>;
+	bus-width = <4>;
+	max-frequency = <50000000>;
+	cap-sd-highspeed;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	no-mmc;
+	no-sdio;
+	status = "okay";
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-sd.dtso b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-sd.dtso
new file mode 100644
index 0000000..5891fe0
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-sd.dtso
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	fragment@0 {
+		target = <&mmc0>;
+		__overlay__ {
+			pinctrl-names = "default", "state_uhs";
+			pinctrl-0 = <&sd_pins_default>;
+			pinctrl-1 = <&sd_pins_uhs>;
+			bus-width = <4>;
+			max-frequency = <52000000>;
+			cap-sd-highspeed;
+			vmmc-supply = <&reg_3p3v>;
+			vqmmc-supply = <&reg_3p3v>;
+			no-mmc;
+			no-sdio;
+			status = "okay";
+		};
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nand.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nand.dtsi
new file mode 100644
index 0000000..dc591f1
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nand.dtsi
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#include "mt7987-pinctrl.dtsi"
+
+/ {
+	nmbm_spim_nand {
+		compatible = "generic,nmbm";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		lower-mtd-device = <&spi_nand>;
+		forced-create;
+
+		partitions: partitions@0 {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+	};
+};
+
+&partitions {
+	partition@0 {
+		label = "BL2";
+		reg = <0x00000 0x0100000>;
+		read-only;
+	};
+	partition@100000 {
+		label = "u-boot-env";
+		reg = <0x0100000 0x0080000>;
+	};
+	factory: partition@180000 {
+		label = "Factory";
+		reg = <0x180000 0x0400000>;
+	};
+	partition@580000 {
+		label = "FIP";
+		reg = <0x580000 0x0200000>;
+	};
+	partition@780000 {
+		label = "ubi";
+		reg = <0x780000 0x7080000>;
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	spi_nand: spi_nand@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-cal-enable;
+		spi-cal-mode = "read-data";
+		spi-cal-datalen = <7>;
+		spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+		spi-cal-addrlen = <5>;
+		spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nand.dtso b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nand.dtso
new file mode 100644
index 0000000..4cf8289
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nand.dtso
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	nmbm_spim_nand {
+		compatible = "generic,nmbm";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		lower-mtd-device = <&spi_nand>;
+		forced-create;
+
+		partitions: partitions@0 {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "BL2";
+				reg = <0x00000 0x0100000>;
+				read-only;
+			};
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x0100000 0x0080000>;
+			};
+			factory: partition@180000 {
+				label = "Factory";
+				reg = <0x180000 0x0400000>;
+			};
+			partition@580000 {
+				label = "FIP";
+				reg = <0x580000 0x0200000>;
+			};
+			partition@780000 {
+				label = "ubi";
+				reg = <0x780000 0x7080000>;
+			};
+		};
+	};
+
+	fragment@0 {
+		target = <&spi0>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi0_flash_pins>;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		
+			spi_nand: spi_nand@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spi-nand";
+				spi-cal-enable;
+				spi-cal-mode = "read-data";
+				spi-cal-datalen = <7>;
+				spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+				spi-cal-addrlen = <5>;
+				spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+				reg = <0>;
+				spi-max-frequency = <52000000>;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+			};
+		};
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nor.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nor.dtsi
new file mode 100644
index 0000000..c4a656d
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nor.dtsi
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+
+#include "mt7987-pinctrl.dtsi"
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_flash_pins>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	spi_nor@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-cal-enable;
+		spi-cal-mode = "read-data";
+		spi-cal-datalen = <7>;
+		spi-cal-data = /bits/ 8 <
+			0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
+		spi-cal-addrlen = <1>;
+		spi-cal-addr = /bits/ 32 <0x0>;
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partition@00000 {
+			label = "BL2";
+			reg = <0x00000 0x0040000>;
+		};
+		partition@40000 {
+			label = "u-boot-env";
+			reg = <0x40000 0x0010000>;
+		};
+		factory: partition@50000 {
+			label = "Factory";
+			reg = <0x50000 0x0200000>;
+		};
+		partition@250000 {
+			label = "FIP";
+			reg = <0x250000 0x0080000>;
+		};
+		partition@2D0000 {
+			label = "firmware";
+			reg = <0x2D0000 0x1D30000>;
+		};
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nor.dtso b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nor.dtso
new file mode 100644
index 0000000..b078c88
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987-spim-nor.dtso
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment@0 {
+		target = <&spi2>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi2_flash_pins>;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		
+			spi_nor@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "jedec,spi-nor";
+				spi-cal-enable;
+				spi-cal-mode = "read-data";
+				spi-cal-datalen = <7>;
+				spi-cal-data = /bits/ 8 <
+					0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>;
+					/* SF_BOOT */
+				spi-cal-addrlen = <1>;
+				spi-cal-addr = /bits/ 32 <0x0>;
+				reg = <0>;
+				spi-max-frequency = <52000000>;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+		
+				partition@00000 {
+					label = "BL2";
+					reg = <0x00000 0x0040000>;
+				};
+				partition@40000 {
+					label = "u-boot-env";
+					reg = <0x40000 0x0010000>;
+				};
+				factory: partition@50000 {
+					label = "Factory";
+					reg = <0x50000 0x0200000>;
+				};
+				partition@250000 {
+					label = "FIP";
+					reg = <0x250000 0x0080000>;
+				};
+				partition@2D0000 {
+					label = "firmware";
+					reg = <0x2D0000 0x1D30000>;
+				};
+			};
+		};
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987.dtsi
new file mode 100644
index 0000000..69f79be
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987.dtsi
@@ -0,0 +1,675 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+#include <dt-bindings/clock/mt7987-clk.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+/ {
+	compatible = "mediatek,mt7987";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clkxtal: oscillator@0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <40000000>;
+		clock-output-names = "clkxtal";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			enable-method = "psci";
+			next-level-cache = <&l2_cache>;
+			reg = <0x0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			enable-method = "psci";
+			next-level-cache = <&l2_cache>;
+			reg = <0x1>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			enable-method = "psci";
+			next-level-cache = <&l2_cache>;
+			reg = <0x2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			enable-method = "psci";
+			next-level-cache = <&l2_cache>;
+			reg = <0x3>;
+		};
+
+		l2_cache: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+	};
+
+	clk40m: clk40m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <40000000>;
+	};
+
+	clkitg: clkitg {
+		compatible = "simple-bus";
+	};
+
+	clksys: soc_clksys {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		infracfg_ao: infracfg_ao@10001000 {
+			compatible = "mediatek,mt7987-infracfg_ao", "syscon";
+			reg = <0 0x10001000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		topckgen: topckgen@1001b000 {
+			compatible = "mediatek,mt7987-topckgen", "syscon";
+			reg = <0 0x1001b000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		apmixedsys: apmixedsys@1001e000 {
+			compatible = "mediatek,mt7987-apmixedsys", "syscon";
+			reg = <0 0x1001e000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		sgmiisys0: syscon@10060000 {
+			compatible = "mediatek,mt7987-sgmiisys",
+				     "mediatek,mt7987-sgmiisys_0",
+				     "syscon";
+			reg = <0 0x10060000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		sgmiisys1: syscon@10070000 {
+			compatible = "mediatek,mt7987-sgmiisys",
+				     "mediatek,mt7987-sgmiisys_1",
+				     "syscon";
+			reg = <0 0x10070000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		mcusys: mcusys@10400000 {
+			compatible = "mediatek,mt7987-mcusys", "syscon";
+			reg = <0 10400000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		infracfg: infracfg@10209000 {
+			compatible = "mediatek,mt7987-infracfg", "syscon";
+			reg = <0 0x10209000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		ethsys: syscon@15000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "mediatek,mt7987-ethdma",
+				     "mediatek,mt7987-ethsys",
+				     "syscon";
+			reg = <0 0x15000000 0 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			ethsysrst: reset-controller {
+				compatible = "ti,syscon-reset";
+				#reset-cells = <1>;
+				ti,reset-bits =
+					<0x34 4 0x34 4 0x34 4
+					(ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>;
+			};
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 128 255>;
+		#cooling-cells = <2>;
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	psci {
+		compatible  = "arm,psci-0.2";
+		method      = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		wmcpu_emi: wmcpu-reserved@4f000000 {
+			compatible = "mediatek,wmcpu-reserved";
+			no-map;
+			reg = <0 0x4f000000 0 0x00100000>;
+		};
+	};
+
+	thermal-zones {
+		thermal_zone0: soc_thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+			thermal-sensors = <&lvts 0>;
+			trips {
+				cpu_trip_crit: crit {
+					temperature = <125000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+
+				cpu_trip_hot: hot {
+					temperature = <120000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpu_trip_active1: active1 {
+					temperature = <115000>;
+					hysteresis = <2000>;
+					type = "active";
+				};
+
+				cpu_trip_active0: active0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "active";
+				};
+
+				cpu_trip_passive: passive {
+					temperature = <40000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				cpu-active-high {
+					cooling-device = <&fan 2 2>;
+					trip = <&cpu_trip_active1>;
+				};
+
+				cpu-active-low {
+					cooling-device = <&fan 1 1>;
+					trip = <&cpu_trip_active0>;
+				};
+
+				cpu-passive {
+					cooling-device = <&fan 0 0>;
+					trip = <&cpu_trip_passive>;
+				};
+			};
+		};
+
+		thermal_zone1: mcusys_thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+			thermal-sensors = <&lvts 1>;
+		};
+
+		thermal_zone2: eth2p5g_thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+			thermal-sensors = <&lvts 2>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	soc: soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		hwver: hwver@8000000 {
+			compatible = "mediatek,hwver", "syscon";
+			reg = <0 0x8000000 0 0x1000>;
+		};
+
+		gic: interrupt-controller@c000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
+			      <0 0x0c080000 0 0x200000>, /* GICR */
+			      <0 0x0c400000 0 0x2000>,   /* GICC */
+			      <0 0x0c410000 0 0x1000>,   /* GICH */
+			      <0 0x0c420000 0 0x2000>;   /* GICV */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		infra_bus_prot: infra_bus_prot@1000310c {
+			compatible = "mediatek,infracfg_ao_bus_hang_prot";
+			reg = <0 0x1000310c 0 0x14>;
+			status = "disabled";
+		};
+
+		watchdog: watchdog@1001c000 {
+			compatible = "mediatek,mt7622-wdt",
+				     "mediatek,mt6589-wdt",
+				     "syscon";
+			reg = <0 0x1001c000 0 0x1000>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			#reset-cells = <1>;
+			status = "disabled";
+		};
+
+		pio: pinctrl@1001f000 {
+			compatible = "mediatek,mt7987-pinctrl";
+			reg = <0 0x1001f000 0 0x1000>,
+			      <0 0x11d00000 0 0x1000>,
+			      <0 0x11e00000 0 0x1000>,
+			      <0 0x11f00000 0 0x1000>,
+			      <0 0x11f40000 0 0x1000>,
+			      <0 0x11f60000 0 0x1000>,
+			      <0 0x1000b000 0 0x1000>;
+			reg-names = "gpio_base", "iocfg_rb_base",
+				    "iocfg_lb_base", "iocfg_rt1_base",
+				    "iocfg_rt2_base", "iocfg_tl_base", "eint";
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pio 0 0 50>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <2>;
+
+			pcie1pereset {
+				gpio-hog;
+			    	gpios = <36 GPIO_ACTIVE_HIGH>;
+				output-high;
+			};
+		};
+
+		boottrap: boottrap@1001f6f0 {
+			compatible = "mediatek,boottrap";
+			reg = <0 0x1001f6f0 0 0x20>;
+			status = "disabled";
+		};
+
+		trng: trng@1020f000 {
+			compatible = "mediatek,mt7988-rng";
+			status = "disabled";
+		};
+
+		pwm: pwm@10048000 {
+			compatible = "mediatek,mt7988-pwm";
+			reg = <0 0x10048000 0 0x1000>;
+			#pwm-cells = <2>;
+			clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
+				 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
+				 <&clkxtal>,
+				 <&clkxtal>,
+				 <&clkxtal>,
+				 <&clkxtal>,
+				 <&clkxtal>,
+				 <&clkxtal>,
+				 <&clkxtal>,
+				 <&clkxtal>;
+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+				      "pwm4","pwm5","pwm6","pwm7","pwm8";
+			status = "disabled";
+		};
+
+		uart0: serial@11000000 {
+			compatible = "mediatek,mt7986-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11000000 0 0x100>;
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg_ao CK_INFRA_52M_UART0_CK>;
+			clock-names = "bus";
+			assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+					  <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
+			assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+						 <&infracfg CK_INFRA_UART_O0>;
+			status = "disabled";
+		};
+
+		uart1: serial@11000100 {
+			compatible = "mediatek,mt7986-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11000100 0 0x100>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg_ao CK_INFRA_52M_UART1_CK>;
+			clock-names = "bus";
+			assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+					  <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
+			assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+						 <&infracfg CK_INFRA_UART_O1>;
+			status = "disabled";
+		};
+
+		uart2: serial@11000200 {
+			compatible = "mediatek,mt7986-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11000200 0 0x100>;
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg_ao CK_INFRA_52M_UART2_CK>;
+			clock-names = "bus";
+			assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+					  <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
+			assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+						 <&infracfg CK_INFRA_UART_O2>;
+			status = "disabled";
+		};
+
+
+		i2c0: i2c@11003000 {
+			compatible = "mediatek,mt7988-i2c",
+				     "mediatek,mt7981-i2c";
+			reg = <0 0x11003000 0 0x1000>,
+			<0 0x10217080 0 0x80>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
+			clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+				 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi0: spi@11007800 {
+			compatible = "mediatek,ipm-spi-quad";
+			reg = <0 0x11007800 0 0x100>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CK_TOP_CB_M_D2>,
+				 <&topckgen CK_TOP_SPI_SEL>,
+				 <&infracfg_ao CK_INFRA_104M_SPI0>,
+				 <&infracfg_ao CK_INFRA_66M_SPI0_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
+			status = "disabled";
+		};
+
+		spi1: spi@11008800 {
+			compatible = "mediatek,ipm-spi-single";
+			reg = <0 0x11008800 0 0x100>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CK_TOP_CB_M_D2>,
+				 <&topckgen CK_TOP_SPI_SEL>,
+				 <&infracfg_ao CK_INFRA_104M_SPI1>,
+				 <&infracfg_ao CK_INFRA_66M_SPI1_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
+			status = "disabled";
+		};
+
+		spi2: spi@11009800 {
+			compatible = "mediatek,ipm-spi-quad";
+			reg = <0 0x11009800 0 0x100>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CK_TOP_CB_M_D2>,
+				<&topckgen CK_TOP_SPI_SEL>,
+				<&infracfg_ao CK_INFRA_104M_SPI2_BCK>,
+				<&infracfg_ao CK_INFRA_66M_SPI2_HCK>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
+			status = "disabled";
+		};
+
+		lvts: lvts@1100a000 {
+			compatible = "mediatek,mt7987-lvts";
+			#thermal-sensor-cells = <1>;
+			reg = <0 0x1100a000 0 0x1000>;
+			clocks = <&infracfg_ao CK_INFRA_26M_THERM_SYSTEM>;
+			clock-names = "lvts_clk";
+			nvmem-cells = <&lvts_calibration>;
+			nvmem-cell-names = "e_data1";
+			status = "disabled";
+		};
+
+		xhci: xhci@11200000 {
+			compatible = "mediatek,mt7987-xhci",
+				"mediatek,mtk-xhci";
+			reg = <0 0x11200000 0 0x2e00>,
+			<0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+			usb2-lpm-disable;
+			status = "disabled";
+		};
+
+		afe: audio-controller@11210000 {
+			compatible = "mediatek,mt79xx-audio";
+			reg = <0 0x11210000 0 0x9000>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg_ao CK_INFRA_66M_AUD_SLV_BCK>,
+				 <&infracfg_ao CK_INFRA_AUD_26M>,
+				 <&infracfg_ao CK_INFRA_AUD_L>,
+				 <&infracfg_ao CK_INFRA_AUD_AUD>,
+				 <&infracfg_ao CK_INFRA_AUD_EG2>,
+				 <&topckgen CK_TOP_AUD_SEL>,
+				 <&topckgen CK_TOP_AUD_I2S_M>;
+			clock-names = "aud_bus_ck",
+				      "aud_26m_ck",
+				      "aud_l_ck",
+				      "aud_aud_ck",
+				      "aud_eg2_ck",
+				      "aud_sel",
+				      "aud_i2s_m";
+			assigned-clocks = <&topckgen CK_TOP_AUD_SEL>,
+					  <&topckgen CK_TOP_A1SYS_SEL>,
+					  <&topckgen CK_TOP_AUD_L_SEL>,
+					  <&topckgen CK_TOP_A_TUNER_SEL>;
+			assigned-clock-parents = <&topckgen CK_TOP_CB_APLL2_196M>,
+						 <&topckgen CK_TOP_CB_APLL2_D4>,
+						 <&topckgen CK_TOP_CB_APLL2_196M>,
+						 <&topckgen CK_TOP_CB_APLL2_D4>;
+			status = "disabled";
+		};
+
+		mmc0: mmc@11230000 {
+			compatible = "mediatek,mt7986-mmc";
+			reg = <0 0x11230000 0 0x1000>,
+				<0 0x11f50000 0 0x1000>;
+			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&topckgen CK_TOP_EMMC_200M_SEL>,
+				 <&infracfg_ao CK_INFRA_133M_MSDC_0_HCK>,
+				 <&infracfg_ao CK_INFRA_MSDC2_HCK>,
+				 <&infracfg_ao CK_INFRA_MSDC200_SRC>,
+				 <&infracfg_ao CK_INFRA_66M_MSDC_0_HCK>;
+			clock-names = "source", "axi_cg", "hclk", "source_cg", "ahb_cg";
+			status = "disabled";
+		};
+
+		wed: wed {
+			compatible = "mediatek,wed";
+			wed_num = <1>;
+		};
+
+		wed0: wed0@15010000 {
+			compatible = "mediatek,wed0";
+			/* add this property for wed get the pci slot number. */
+			pci_slot_map = <0>;
+			reg = <0 0x15010000 0 0x2000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		wdma: wdma@15104800 {
+			compatible = "mediatek,wed-wdma";
+			reg = <0 0x15104800 0 0x400>;
+		};
+
+		pcie0: pcie@11280000 {
+			compatible = "mediatek,mt7988-pcie",
+				     "mediatek,mt7987-pcie",
+				     "mediatek,mt7986-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11280000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <0>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x20000000 0x00
+				  0x20000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x20200000 0x00
+				  0x20200000 0x00 0x0fe00000>;
+			clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P0>,
+				 <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P0>,
+				 <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P0>,
+				 <&infracfg_ao CK_INFRA_133M_PCIE_CK_P0>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			status = "disabled";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+					<0 0 0 2 &pcie_intc2 1>,
+					<0 0 0 3 &pcie_intc2 2>,
+					<0 0 0 4 &pcie_intc2 3>;
+			pcie_intc2: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie1: pcie@11290000 {
+			compatible = "mediatek,mt7988-pcie",
+				     "mediatek,mt7987-pcie",
+				     "mediatek,mt7986-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11290000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <1>;
+			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x30000000 0x00
+				  0x30000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x30200000 0x00
+				  0x30200000 0x00 0x0fe00000>;
+			clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P1>,
+				 <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P1>,
+				 <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P1>,
+				 <&infracfg_ao CK_INFRA_133M_PCIE_CK_P1>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			status = "disabled";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+					<0 0 0 2 &pcie_intc1 1>,
+					<0 0 0 3 &pcie_intc1 2>,
+					<0 0 0 4 &pcie_intc1 3>;
+			pcie_intc1: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+			slot1: pcie@0,0 {
+				reg = <0x0000 0 0 0 0>;
+			};
+		};
+
+		topmisc: topmisc@10021000 {
+			compatible = "mediatek,mt7987-topmisc", "syscon",
+				     "mediatek,mt7987-power-controller";
+			reg = <0 0x10021000 0 0x10000>;
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			/* power domain of the SoC */
+			/* eth2p5@MT7988_POWER_DOMAIN_ETH2P5 {
+				reg = <MT7988_POWER_DOMAIN_ETH2P5>;
+				#power-domain-cells = <0>;
+			}; */
+		};
+
+		efuse: efuse@11d30000 {
+			compatible = "mediatek,efuse";
+			reg = <0 0x11d30000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			lvts_calibration: calib@918 {
+				reg = <0x918 0x10>;
+			};
+
+			comb_auto_load_valid: usb3-alv-imp@8ee {
+				reg = <0x8ee 1>;
+				bits = <0 1>;
+			};
+
+			comb_rx_imp_p0: usb3-rx-imp@8ec {
+				reg = <0x8ec 1>;
+				bits = <0 5>;
+			};
+
+			comb_tx_imp_p0: usb3-tx-imp@8ec {
+				reg = <0x8ec 2>;
+				bits = <5 5>;
+			};
+
+			comb_intr_p0: usb3-intr@8ec {
+				reg = <0x8ec 2>;
+				bits = <10 6>;
+			};
+
+			u2_auto_load_valid_p0: usb2-alv-p0@8cc {
+				reg  = <0x8cc 1>;
+				bits = <0 1>;
+			};
+
+			u2_intr_p0: usb2-intr-p0@8cc {
+				reg  = <0x8cc 1>;
+				bits = <1 5>;
+			};
+		};
+	};
+
+	netsys: soc_netsys {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};
+
+#include "mt7987-clkitg.dtsi"
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-emmc.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-emmc.dts
new file mode 100644
index 0000000..e203b00
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-emmc.dts
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys.dtsi"
+#include "mt7987-emmc.dtsi"
+
+/ {
+	model = "MediaTek MT7987 EMMC RFB";
+	compatible = "mediatek,mt7987a-emmc",
+		     "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    root=PARTLABEL=rootfs rootwait \
+			    rootfstype=squashfs,f2fs pci=pcie_bus_perf";
+	};
+};
\ No newline at end of file
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-rfb.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-rfb.dts
new file mode 100644
index 0000000..f4d6a68
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-rfb.dts
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys.dtsi"
+
+/ {
+	model = "MediaTek MT7987A RFB";
+	compatible = "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-sd.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-sd.dts
new file mode 100644
index 0000000..b138439
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-sd.dts
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys.dtsi"
+#include "mt7987-sd.dtsi"
+
+/ {
+	model = "MediaTek MT7987 SD RFB";
+	compatible = "mediatek,mt7987a-sd",
+		     "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    root=PARTLABEL=rootfs rootwait \
+			    rootfstype=squashfs,f2fs pci=pcie_bus_perf";
+	};
+};
\ No newline at end of file
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-an8801sb.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-an8801sb.dts
new file mode 100644
index 0000000..ada03e0
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-an8801sb.dts
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys.dtsi"
+#include "mt7987-spim-nand.dtsi"
+
+/ {
+	model = "MediaTek MT7987A SPIM-NAND AN8801SB";
+	compatible = "mediatek,mt7987a-spim-snand-an8801sb",
+		     "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+};
+
+&gmac2 {
+	mac-type = "gdm";
+	phy-mode = "sgmii";
+	phy-handle = <&phy31>;
+};
+
+&mdio {
+	/delete-property/ reset-gpios;
+	/delete-property/ reset-delay-us;
+	/delete-node/ phy@11;
+	phy31: phy@31 {
+		compatible = "ethernet-phy-idc0ff.0421";
+		reg = <31>;
+		reset-gpios = <&pio 48 1>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <10000>;
+		phy-mode = "sgmii";
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-evb-gsw.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-evb-gsw.dts
new file mode 100644
index 0000000..d907b10
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-evb-gsw.dts
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys-evb.dtsi"
+#include "mt7987-spim-nand.dtsi"
+
+/ {
+	model = "MediaTek MT7987A SPIM-NAND EVB GSW";
+	compatible = "mediatek,mt7987a-spim-snand-evb-gsw",
+		     "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+
+	gsw_mt753x: gsw@0 {
+		compatible = "mediatek,mt753x";
+		mediatek,ethsys = <&ethsys>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
+
+&gsw_mt753x {
+	mediatek,mdio = <&mdio>;
+	mediatek,portmap = "lllll";
+	mediatek,mdio_master_pinmux = <1>;
+	reset-gpios = <&pio 42 0>;
+	interrupt-parent = <&pio>;
+	interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+	status = "okay";
+
+	port5: port@5 {
+		compatible = "mediatek,mt753x-port";
+		reg = <5>;
+		phy-mode = "2500base-x";
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+		};
+	};
+
+	port6: port@6 {
+		compatible = "mediatek,mt753x-port";
+		reg = <6>;
+		phy-mode = "2500base-x";
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+		};
+	};
+};
+
+&mdio {
+	/delete-node/ switch@31;
+};
+
+&hnat {
+	mtketh-lan = "eth0";
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-evb.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-evb.dts
new file mode 100644
index 0000000..b5c7685
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-evb.dts
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys-evb.dtsi"
+#include "mt7987-spim-nand.dtsi"
+
+/ {
+	model = "MediaTek MT7987A SPIM-NAND EVB";
+	compatible = "mediatek,mt7987a-spim-snand-evb",
+		     "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-gsw.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-gsw.dts
new file mode 100644
index 0000000..cffd774
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-gsw.dts
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys.dtsi"
+#include "mt7987-spim-nand.dtsi"
+
+/ {
+	model = "MediaTek MT7987A SPIM-NAND RFB GSW";
+	compatible = "mediatek,mt7987a-spim-snand-gsw",
+		     "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+
+	gsw_an8855: gsw@1 {
+		compatible = "airoha,an8855";
+		#mediatek,ethsys = <&ethsys>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
+
+&gsw_an8855 {
+	airoha,mdio = <&mdio>;
+	airoha,portmap = "lllll";
+	airoha,intr = <6>;
+	airoha,extSurge = <1>;
+	reset-gpios = <&pio 42 0>;
+	interrupt-parent = <&pio>;
+	interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+	status = "okay";
+
+	port5: port@5 {
+		compatible = "airoha,an8855-port";
+		reg = <5>;
+		phy-mode = "2500base-x";
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+		};
+	};
+};
+
+&mdio {
+	/delete-node/ switch@1;
+};
+
+&hnat {
+	mtketh-lan = "eth0";
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-sfp.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-sfp.dts
new file mode 100644
index 0000000..c25d016
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand-sfp.dts
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys.dtsi"
+#include "mt7987-spim-nand.dtsi"
+
+/ {
+	model = "MediaTek MT7987A SPIM-NAND SFP";
+	compatible = "mediatek,mt7987a-spim-snand",
+		     "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+
+	sfp_cage0: sfp@0 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c0>;
+		mod-def0-gpios = <&pio 49 1>;
+		los-gpios = <&pio 46 0>;
+		tx-disable-gpios = <&pio 48 0>;
+		maximum-power-milliwatt = <3000>;
+	};
+};
+
+&gmac2 {
+	mac-type = "gdm";
+	phy-mode = "2500base-x";
+	/delete-property/ phy-handle;
+	managed = "in-band-status";
+	sfp = <&sfp_cage0>;
+};
+
+&mdio {
+	/delete-property/ reset-gpios;
+	/delete-property/ reset-delay-us;
+	/delete-node/ phy@11;
+};
+
+&uart1 {
+	status = "disabled";
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand.dts
new file mode 100644
index 0000000..47dd19c
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nand.dts
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys.dtsi"
+#include "mt7987-spim-nand.dtsi"
+
+/ {
+	model = "MediaTek MT7987A SPIM-NAND RFB";
+	compatible = "mediatek,mt7987a-spim-snand",
+		     "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nor.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nor.dts
new file mode 100644
index 0000000..8772b3b
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a-spim-nor.dts
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+#include "mt7987-netsys.dtsi"
+#include "mt7987-spim-nor.dtsi"
+
+/ {
+	model = "MediaTek MT7987 NOR RFB";
+	compatible = "mediatek,mt7987a-spim-nor",
+		     "mediatek,mt7987a", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+};
\ No newline at end of file
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a.dtsi
new file mode 100644
index 0000000..e222bf3
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987a.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7987.dtsi"
+#include "mt7987-pinctrl.dtsi"
+
+/ {
+	compatible = "mediatek,mt7987a", "mediatek,mt7987";
+
+	memory {
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+};
+
+&afe {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcm_pins>;
+	status = "okay";
+};
+
+&boottrap {
+	status = "okay";
+};
+
+&fan {
+	pwms = <&pwm 0 50000 0>;
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+};
+
+&infra_bus_prot {
+	status = "okay";
+};
+
+&lvts {
+	status = "okay";
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_pins>;
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "disabled";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&soc {
+	usbtphy: usb-phy@11c50000 {
+		compatible = "mediatek,mt7987",
+			     "mediatek,generic-tphy-v2";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "okay";
+
+		tphyu2port0: usb-phy@11c50000 {
+			reg = <0 0x11c50000 0 0x700>;
+			clocks = <&infracfg_ao CK_INFRA_USB_UTMI_CK_P1>;
+			clock-names = "ref";
+			#phy-cells = <1>;
+
+			auto_load_valid;
+			nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>;
+			nvmem-cell-names = "intr", "auto_load_valid";
+
+			status = "okay";
+		};
+
+		tphyu3port0: usb-phy@11c50700 {
+			reg = <0 0x11c50700 0 0x900>;
+			clocks = <&infracfg_ao CK_INFRA_USB_PIPE_CK_P1>;
+			clock-names = "ref";
+			#phy-cells = <1>;
+
+			auto_load_valid;
+			nvmem-cells = <&comb_intr_p0>,
+			      <&comb_rx_imp_p0>,
+			      <&comb_tx_imp_p0>,
+			      <&comb_auto_load_valid>;
+			nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid";
+
+			/* MT7987: 4'b0010 default USB30 Don't change the '0' */
+			mediatek,syscon-type = <&topmisc 0x218 0>;
+
+			status = "disabled";
+		};
+	};
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spic_pins>;
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&uart0 {
+	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&clkxtal>;
+	clock-names = "bus";
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&xhci {
+	mediatek,u3p-dis-msk = <0x00000001>;
+	phys = <&tphyu2port0 PHY_TYPE_USB2>;
+
+	clocks = <&infracfg_ao CK_INFRA_USB_SYS_CK_P1>,
+		 <&infracfg_ao CK_INFRA_USB_XHCI_CK_P1>,
+		 <&infracfg_ao CK_INFRA_USB_CK_P1>,
+		 <&infracfg_ao CK_INFRA_66M_USB_HCK_CK_P1>,
+		 <&infracfg_ao CK_INFRA_133M_USB_HCK_CK_P1>;
+	clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck",
+		      "dma_ck";
+
+	status = "okay";
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987b-netsys.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987b-netsys.dtsi
new file mode 100644
index 0000000..8ad933d
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987b-netsys.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "mt7987-netsys.dtsi"
+
+&eth {
+	/delete-node/ mac@2;
+};
+
+&hnat {
+	mtketh-max-gmac = <2>;
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987b-spim-nand.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987b-spim-nand.dts
new file mode 100644
index 0000000..d164c6d
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987b-spim-nand.dts
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+/dts-v1/;
+#include "mt7987b.dtsi"
+#include "mt7987b-netsys.dtsi"
+#include "mt7987-spim-nand.dtsi"
+
+/ {
+	model = "MediaTek MT7987B SPIM-NAND RFB";
+	compatible = "mediatek,mt7987b-spim-snand",
+		     "mediatek,mt7987b", "mediatek,mt7987";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1 loglevel=8  \
+			    earlycon=uart8250,mmio32,0x11000000 \
+			    pci=pcie_bus_perf";
+	};
+};
\ No newline at end of file
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987b.dtsi b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987b.dtsi
new file mode 100644
index 0000000..9a6ddff
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7987b.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7987a.dtsi"
+
+/ {
+	compatible = "mediatek,mt7987b", "mediatek,mt7987";
+
+	memory {
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+	cpus {
+		/delete-node/ cpu@2;
+		/delete-node/ cpu@3;
+	};
+};
+
+&tphyu3port0 {
+	status = "okay";
+};
+
+&xhci {
+	mediatek,u3p-dis-msk=<0>;
+
+	phys = <&tphyu2port0 PHY_TYPE_USB2>,
+	       <&tphyu3port0 PHY_TYPE_USB3>;
+};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7987.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7987.c
new file mode 100644
index 0000000..30ad64b
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7987.c
@@ -0,0 +1,855 @@
+/*
+ * Copyright (c) 2024 MediaTek Inc.
+ * Author: Lu Tang <Lu.Tang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt7987-clk.h>
+
+static DEFINE_SPINLOCK(mt7987_clk_lock);
+
+static const struct mtk_fixed_factor top_divs[] __initconst = {
+	FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
+	FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
+	FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 6),
+	FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
+	FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
+	FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
+	FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
+	FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", "apll2", 1, 4),
+	FACTOR(CK_TOP_CB_NET1_D3, "cb_net1_d3", "net1pll", 1, 3),
+	FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
+	FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
+	FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
+	FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
+	FACTOR(CK_TOP_CB_NET1_D7, "cb_net1_d7", "net1pll", 1, 7),
+	FACTOR(CK_TOP_NET1_D7_D2, "net1_d7_d2", "net1pll", 1, 14),
+	FACTOR(CK_TOP_NET1_D7_D4, "net1_d7_d4", "net1pll", 1, 28),
+	FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
+	FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
+	FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", "net1pll", 1, 64),
+	FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", "net1pll", 1, 128),
+	FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
+	FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
+	FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
+	FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
+	FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", "net2pll", 1, 32),
+	FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
+	FACTOR(CK_TOP_NET2_D7_D2, "net2_d7_d2", "net2pll", 1, 14),
+	FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", "net2pll", 1, 8),
+	FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
+	FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
+	FACTOR(CK_TOP_CB_MSDC_416M, "cb_msdc_416m", "msdcpll", 1, 1),
+	FACTOR(CK_TOP_MSDC_D2, "msdc_d2", "msdcpll", 1, 2),
+	FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
+	FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
+	FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
+	FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1221),
+	FACTOR(CK_TOP_NETSYS_500m, "netsys_500m", "netsys_500m_sel", 1, 1),
+	FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
+	FACTOR(CK_TOP_EMMC_250M, "emmc_250m", "emmc_250m_sel", 1, 1),
+	FACTOR(CK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
+	FACTOR(CK_TOP_NFI_BCK, "nfi_bck", "nfi_sel", 1, 1),
+	FACTOR(CK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
+	FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", "usb_sys_p1_sel", 1, 1),
+	FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", "usb_xhci_p1_sel", 1, 1),
+	FACTOR(CK_TOP_AUD, "aud", "aud_sel", 1, 1),
+	FACTOR(CK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
+	FACTOR(CK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
+	FACTOR(CK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
+	FACTOR(CK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
+	FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", "csw_infra_f26m_sel", 1, 1),
+	FACTOR(CK_TOP_EMMC_200M, "emmc_200m", "emmc_200m_sel", 1, 1),
+	FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1", "cksq_40m_d2", 1, 1),
+	FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", "cb_cksq_40m", 1, 1),
+};
+
+static const struct mtk_fixed_factor infra_divs[] __initconst = {
+	FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", "csw_infra_f26m_sel", 1, 1),
+	FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", "pwm_sel", 1, 1),
+	FACTOR(CK_INFRA_INFRA_F32K, "infra_infra_f32k", "cb_rtc_32p7k", 1, 1),
+	FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0", "pextp_tl_ck_sel",
+	       1, 1),
+	FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
+	       "pextp_tl_ck_p1_sel", 1, 1),
+	FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", "sysaxi", 1, 1),
+	FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", "infra_133m_hck", 1, 1),
+	FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", "infra_133m_hck", 1, 1),
+	FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", "aud_l", 1, 1),
+	FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", "a1sys", 1, 1),
+	FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", "a_tuner", 1, 1),
+	FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", "i2c_bck", 1, 1),
+	FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", "uart_sel", 1, 1),
+	FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", "uart_sel", 1, 1),
+	FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", "uart_sel", 1, 1),
+	FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", "nfi_bck", 1, 1),
+	FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", "spi_sel", 1, 1),
+	FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", "spim_mst_sel", 1, 1),
+	FACTOR(CK_INFRA_SPI2_O, "infra_spi2_o", "spi_sel", 1, 1),
+	FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", "infra_frtc", 1, 1),
+	FACTOR(CK_INFRA_FRTC, "infra_frtc", "cb_rtc_32k", 1, 1),
+	FACTOR(CK_INFRA_FMSDC200_SRC_O, "infra_fmsdc200_src_o", "emmc_200m", 1,
+	       1),
+	FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", "emmc_400m", 1, 1),
+	FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ", "emmc_250m", 1,
+	       1),
+	FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", "sysaxi", 1, 1),
+	FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", "usb_ck_p1", 1, 1),
+	FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
+	       "usb_frmcnt_p1", 1, 1),
+	FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1", "usb_xhci_p1", 1,
+	       1),
+	FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", "clkxtal", 1, 1),
+	FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", "clkxtal", 1, 1),
+	FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
+	       "clkxtal", 1, 1),
+	FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
+	       "clkxtal", 1, 1),
+	FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", "csw_infra_f26m", 1, 1),
+	FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", "csw_infra_f26m", 1, 1),
+	FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", "sysaxi", 1, 1),
+	FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi", 1, 1),
+	FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", "sysaxi", 1, 1),
+	FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1", "usb_sys_p1", 1, 1),
+};
+
+static const char *const netsys_parents[] = { "cb_cksq_40m", "cb_net2_d2" };
+
+static const char *const netsys_500m_parents[] = { "cb_cksq_40m", "cb_net1_d5",
+						   "net1_d5_d2" };
+
+static const char *const netsys_2x_parents[] = { "cb_cksq_40m",
+						 "cb_net2_800m" };
+
+static const char *const eth_gmii_parents[] = { "cb_cksq_40m", "net1_d5_d4" };
+
+static const char *const eip_parents[] = { "cb_cksq_40m", "cb_net1_d3",
+					   "cb_net2_800m", "cb_net1_d4",
+					   "cb_net1_d5" };
+
+static const char *const axi_infra_parents[] = { "cb_cksq_40m", "net1_d8_d2" };
+
+static const char *const uart_parents[] = { "cb_cksq_40m", "cb_m_d8",
+					    "m_d8_d2" };
+
+static const char *const emmc_250m_parents[] = { "cb_cksq_40m", "net1_d5_d2",
+						 "net1_d7_d2" };
+
+static const char *const emmc_400m_parents[] = { "cb_cksq_40m", "cb_msdc_416m",
+						 "cb_net1_d7",	"cb_m_d2",
+						 "net1_d7_d2",	"cb_net2_d6" };
+
+static const char *const spi_parents[] = { "cb_cksq_40m", "cb_m_d2",
+					   "net1_d7_d2",  "net1_d8_d2",
+					   "cb_net2_d6",  "net1_d5_d4",
+					   "cb_m_d4",	  "net1_d8_d4" };
+
+static const char *const nfi_parents[] = {
+	"cksq_40m_d2", "net1_d8_d2", "cb_m_d3", "net1_d5_d4", "cb_m_d4",
+	"net1_d7_d4",  "net1_d8_d4", "m_d3_d2", "net2_d7_d2", "cb_m_d8"
+};
+
+static const char *const pwm_parents[] = { "cb_cksq_40m", "net1_d8_d2",
+					   "net1_d5_d4",  "cb_m_d4",
+					   "m_d8_d2",	  "cb_rtc_32k" };
+
+static const char *const i2c_parents[] = { "cb_cksq_40m", "net1_d5_d4",
+					   "cb_m_d4", "net1_d8_d4" };
+
+static const char *const pcie_mbist_250m_parents[] = { "cb_cksq_40m",
+						       "net1_d5_d2" };
+
+static const char *const pextp_tl_ck_parents[] = { "cb_cksq_40m", "cb_net2_d6",
+						   "net1_d7_d4", "m_d8_d2",
+						   "cb_rtc_32k" };
+
+static const char *const aud_parents[] = { "cb_cksq_40m", "cb_apll2_196m" };
+
+static const char *const a1sys_parents[] = { "cb_cksq_40m", "cb_apll2_d4" };
+
+static const char *const aud_l_parents[] = { "cb_cksq_40m", "cb_apll2_196m",
+					     "m_d8_d2" };
+
+static const char *const usb_phy_parents[] = { "cksq_40m_d2", "m_d8_d2" };
+
+static const char *const sgm_0_parents[] = { "cb_cksq_40m", "cb_sgm_325m" };
+
+static const char *const sgm_sbus_0_parents[] = { "cb_cksq_40m", "net1_d8_d4" };
+
+static const char *const sysapb_parents[] = { "cb_cksq_40m", "m_d3_d2" };
+
+static const char *const eth_refck_50m_parents[] = { "cb_cksq_40m",
+						     "net2_d4_d4" };
+
+static const char *const eth_sys_200m_parents[] = { "cb_cksq_40m",
+						    "cb_net2_d4" };
+
+static const char *const eth_xgmii_parents[] = { "cksq_40m_d2", "net1_d8_d8",
+						 "net1_d8_d16" };
+
+static const char *const dramc_md32_parents[] = { "cb_cksq_40m", "cb_m_d2",
+						  "cb_wedmcu_208m" };
+
+static const char *const da_xtp_glb_p0_parents[] = { "cb_cksq_40m",
+						     "cb_net2_d8" };
+
+static const char *const da_ckm_xtal_parents[] = { "cb_cksq_40m", "m_d8_d2" };
+
+static const char *const eth_mii_parents[] = { "cksq_40m_d2", "net2_d4_d8" };
+
+static const char *const emmc_200m_parents[] = { "cb_cksq_40m", "msdc_d2",
+						 "net1_d7_d2", "cb_net2_d6",
+						 "net1_d7_d4" };
+
+static struct mtk_mux top_muxes[] = {
+	/* CLK_CFG_0 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
+			     0x000, 0x004, 0x008, 0, 1, 7, 0x1C0, 0),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
+			     netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, 15,
+			     0x1C0, 1),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
+			     netsys_2x_parents, 0x000, 0x004, 0x008, 16, 1, 23,
+			     0x1C0, 2),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
+			     eth_gmii_parents, 0x000, 0x004, 0x008, 24, 1, 31,
+			     0x1C0, 3),
+	/* CLK_CFG_1 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_EIP_SEL, "eip_sel", eip_parents, 0x010,
+			     0x014, 0x018, 0, 3, 7, 0x1C0, 4),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
+			     axi_infra_parents, 0x010, 0x014, 0x018, 8, 1, 15,
+			     0x1C0, 5),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
+			     0x014, 0x018, 16, 2, 23, 0x1C0, 6),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
+			     emmc_250m_parents, 0x010, 0x014, 0x018, 24, 2, 31,
+			     0x1C0, 7),
+	/* CLK_CFG_2 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
+			     emmc_400m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
+			     0x1C0, 8),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x020,
+			     0x024, 0x028, 8, 3, 15, 0x1C0, 9),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
+			     0x020, 0x024, 0x028, 16, 3, 23, 0x1C0, 10),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_NFI_SEL, "nfi_sel", nfi_parents, 0x020,
+			     0x024, 0x028, 24, 4, 31, 0x1C0, 11),
+	/* CLK_CFG_3 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x030,
+			     0x034, 0x038, 0, 3, 7, 0x1C0, 12),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x030,
+			     0x034, 0x038, 8, 2, 15, 0x1C0, 13),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
+			     pcie_mbist_250m_parents, 0x030, 0x034, 0x038, 16,
+			     1, 23, 0x1C0, 14),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
+			     pextp_tl_ck_parents, 0x030, 0x034, 0x038, 24, 3,
+			     31, 0x1C0, 15),
+	/* CLK_CFG_4 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
+			     pextp_tl_ck_parents, 0x040, 0x044, 0x048, 0, 3, 7,
+			     0x1C0, 16),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
+			     eth_gmii_parents, 0x040, 0x044, 0x048, 8, 1, 15,
+			     0x1C0, 17),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
+			     eth_gmii_parents, 0x040, 0x044, 0x048, 16, 1, 23,
+			     0x1C0, 18),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x040,
+			     0x044, 0x048, 24, 1, 31, 0x1C0, 19),
+	/* CLK_CFG_5 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
+			     0x050, 0x054, 0x058, 0, 1, 7, 0x1C0, 20),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
+			     0x050, 0x054, 0x058, 8, 2, 15, 0x1C0, 21),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
+			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_USB_PHY_SEL, "usb_phy_sel", usb_phy_parents,
+			     0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
+	/* CLK_CFG_6 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
+			     0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
+				   sgm_sbus_0_parents, 0x060, 0x064, 0x068, 8,
+				   1, 15, 0x1C0, 25, CLK_IS_CRITICAL),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
+			     0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
+				   sgm_sbus_0_parents, 0x060, 0x064, 0x068, 24,
+				   1, 31, 0x1C0, 27, CLK_IS_CRITICAL),
+	/* CLK_CFG_7 */
+	MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SYSAXI_SEL, "sysaxi_sel",
+				   axi_infra_parents, 0x070, 0x074, 0x078, 0, 1,
+				   7, 0x1C0, 28, CLK_IS_CRITICAL),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_SYSAPB_SEL, "sysapb_sel",
+				   sysapb_parents, 0x070, 0x074, 0x078, 8, 1,
+				   15, 0x1C0, 29, CLK_IS_CRITICAL),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
+			     eth_refck_50m_parents, 0x070, 0x074, 0x078, 16, 1,
+			     23, 0x1C0, 30),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
+			     eth_sys_200m_parents, 0x070, 0x074, 0x078, 24, 1,
+			     31, 0x1C4, 0),
+	/* CLK_CFG_8 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_SYS_SEL, "eth_sys_sel",
+			     pcie_mbist_250m_parents, 0x080, 0x084, 0x088, 0, 1,
+			     7, 0x1C4, 1),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
+			     eth_xgmii_parents, 0x080, 0x084, 0x088, 8, 2, 15,
+			     0x1C4, 2),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_DRAMC_SEL, "dramc_sel",
+				   usb_phy_parents, 0x080, 0x084, 0x088, 16, 1,
+				   23, 0x1C4, 3, CLK_IS_CRITICAL),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
+				   dramc_md32_parents, 0x080, 0x084, 0x088, 24,
+				   2, 31, 0x1C4, 4, CLK_IS_CRITICAL),
+	/* CLK_CFG_9 */
+	MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel",
+				   usb_phy_parents, 0x090, 0x094, 0x098, 0, 1,
+				   7, 0x1C4, 5, CLK_IS_CRITICAL),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
+				   usb_phy_parents, 0x090, 0x094, 0x098, 8, 1,
+				   15, 0x1C4, 6, CLK_IS_CRITICAL),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
+				   usb_phy_parents, 0x090, 0x094, 0x098, 16, 1,
+				   23, 0x1C4, 7, CLK_IS_CRITICAL),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
+			     da_xtp_glb_p0_parents, 0x090, 0x094, 0x098, 24, 1,
+			     31, 0x1C4, 8),
+	/* CLK_CFG_10 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
+			     da_xtp_glb_p0_parents, 0x0A0, 0x0A4, 0x0A8, 0, 1,
+			     7, 0x1C4, 9),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_CKM_SEL, "ckm_sel", usb_phy_parents, 0x0A0,
+			     0x0A4, 0x0A8, 8, 1, 15, 0x1C4, 10),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_DA_CKM_XTAL_SEL, "da_ckm_xtal_sel",
+			     da_ckm_xtal_parents, 0x0A0, 0x0A4, 0x0A8, 16, 1,
+			     23, 0x1C4, 11),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_SEL, "pextp_sel", usb_phy_parents,
+			     0x0A0, 0x0A4, 0x0A8, 24, 1, 31, 0x1C4, 12),
+	/* CLK_CFG_11 */
+	MUX_GATE_CLR_SET_UPD(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents,
+			     0x0B0, 0x0B4, 0x0B8, 0, 1, 7, 0x1C4, 13),
+	MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_200M_SEL, "emmc_200m_sel",
+			     emmc_200m_parents, 0x0B0, 0x0B4, 0x0B8, 8, 3, 15,
+			     0x1C4, 14),
+};
+
+static const char *const infra_mux_uart0_parents[] = { "infra_ck_f26m",
+						       "infra_uart_o0" };
+
+static const char *const infra_mux_uart1_parents[] = { "infra_ck_f26m",
+						       "infra_uart_o1" };
+
+static const char *const infra_mux_uart2_parents[] = { "infra_ck_f26m",
+						       "infra_uart_o2" };
+
+static const char *const infra_mux_spi0_parents[] = { "infra_i2c_o",
+						      "infra_spi0_o" };
+
+static const char *const infra_mux_spi1_parents[] = { "infra_i2c_o",
+						      "infra_spi1_o" };
+
+static const char *const infra_mux_spi2_bck_parents[] = { "infra_i2c_o",
+							  "infra_spi0_o" };
+
+static const char *const infra_pwm_bck_parents[] = {
+	"infra_infra_f32k", "infra_ck_f26m", "infra_66m_mck", "infra_pwm_o"
+};
+
+static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
+	"infra_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
+	"infra_pcie_ck_occ_p0"
+};
+
+static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
+	"infra_infra_f32k", "infra_ck_f26m", "infra_ck_f26m",
+	"infra_pcie_ck_occ_p1"
+};
+
+static struct mtk_mux infra_muxes[] = {
+	/* MODULE_CLK_SEL_0 */
+	MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
+			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0,
+			     1, -1, -1, -1),
+	MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
+			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1,
+			     1, -1, -1, -1),
+	MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
+			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2,
+			     1, -1, -1, -1),
+	MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
+			     infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
+			     1, -1, -1, -1),
+	MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
+			     infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
+			     1, -1, -1, -1),
+	MUX_GATE_CLR_SET_UPD(CK_INFRA_MUX_SPI2_BCK_SEL,
+			     "infra_mux_spi2_bck_sel",
+			     infra_mux_spi2_bck_parents, 0x0018, 0x0010, 0x0014,
+			     6, 1, -1, -1, -1),
+	MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel",
+			     infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
+			     2, -1, -1, -1),
+	/* MODULE_CLK_SEL_1 */
+	MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
+			     "infra_pcie_gfmux_tl_ck_o_p0_sel",
+			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
+			     0x0020, 0x0024, 0, 2, -1, -1, -1),
+	MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
+			     "infra_pcie_gfmux_tl_ck_o_p1_sel",
+			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
+			     0x0020, 0x0024, 2, 2, -1, -1, -1),
+};
+
+static const struct mtk_composite top_adj_divs[] = {
+	DIV_GATE(CK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", 0x0420, 0, 0x0420, 8, 8),
+};
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+	.set_ofs = 0x10,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+	.set_ofs = 0x40,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x48,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+	.set_ofs = 0x50,
+	.clr_ofs = 0x54,
+	.sta_ofs = 0x58,
+};
+
+static const struct mtk_gate_regs infra3_cg_regs = {
+	.set_ofs = 0x60,
+	.clr_ofs = 0x64,
+	.sta_ofs = 0x68,
+};
+
+#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .name = _name, .parent_name = _parent,              \
+		.regs = &infra0_cg_regs, .shift = _shift,                      \
+		.ops = &mtk_clk_gate_ops_setclr,                               \
+	}
+
+#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .name = _name, .parent_name = _parent,              \
+		.regs = &infra1_cg_regs, .shift = _shift,                      \
+		.ops = &mtk_clk_gate_ops_setclr,                               \
+	}
+
+#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .name = _name, .parent_name = _parent,              \
+		.regs = &infra2_cg_regs, .shift = _shift,                      \
+		.ops = &mtk_clk_gate_ops_setclr,                               \
+	}
+
+#define GATE_INFRA3(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .name = _name, .parent_name = _parent,              \
+		.regs = &infra3_cg_regs, .shift = _shift,                      \
+		.ops = &mtk_clk_gate_ops_setclr,                               \
+	}
+
+#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift)                      \
+	{                                                                      \
+		.id = _id, .name = _name, .parent_name = _parent,              \
+		.regs = _regs, .shift = _shift, .flags = CLK_IS_CRITICAL,      \
+		.ops = &mtk_clk_gate_ops_setclr,                               \
+	}
+
+static const struct mtk_gate infra_clks[] __initconst = {
+	/* INFRA1 */
+	GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
+		    "infra_66m_mck", 0),
+	GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
+		    "infra_66m_mck", 1),
+	GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
+		    "infra_pwm_bck_sel", 2),
+	GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
+		    "infra_133m_mck", 12),
+	GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
+		    "infra_66m_phck", 13),
+	GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", "infra_ck_f26m", 14),
+	GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", "infra_faud_l_o", 15),
+	GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", "infra_faud_aud_o",
+		    16),
+	GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", "infra_faud_eg2_o",
+		    18),
+	GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "infra_ck_f26m",
+		    19),
+	GATE_CRITICAL(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
+		      "infra_133m_mck", &infra1_cg_regs, 20),
+	GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
+		    "infra_66m_mck", 21),
+	GATE_INFRA1(CK_INFRA_MSDC200_SRC, "infra_f_fmsdc200_src",
+		    "infra_fmsdc200_src_o", 28),
+	GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
+		    "infra_66m_mck", 29),
+	GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
+		    "infra_ck_f26m", 30),
+	GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", "infra_peri_66m_o",
+		    31),
+	/* INFRA2 */
+	GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
+		    "infra_ck_f26m", 0),
+	GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", "infra_i2c_o", 1),
+	GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
+		    "infra_66m_mck", 3),
+	GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
+		    "infra_66m_mck", 4),
+	GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
+		    "infra_66m_mck", 5),
+	GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
+		    "infra_mux_uart0_sel", 3),
+	GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
+		    "infra_mux_uart1_sel", 4),
+	GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
+		    "infra_mux_uart2_sel", 5),
+	GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", "infra_nfi_o", 9),
+	GATE_CRITICAL(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
+		      "infra_66m_mck", &infra2_cg_regs, 11),
+	GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
+		    "infra_mux_spi0_sel", 12),
+	GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
+		    "infra_mux_spi1_sel", 13),
+	GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
+		    "infra_mux_spi2_bck_sel", 14),
+	GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
+		    "infra_66m_mck", 15),
+	GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
+		    "infra_66m_mck", 16),
+	GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
+		    "infra_66m_mck", 17),
+	GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
+		    "infra_66m_mck", 18),
+	GATE_CRITICAL(CK_INFRA_RTC, "infra_f_frtc", "infra_lb_mux_frtc",
+		      &infra2_cg_regs, 19),
+	GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
+		    "infra_f26m_o1", 20),
+	GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
+		    21),
+	GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", "infra_fmsdc400_o",
+		    22),
+	GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
+		    "infra_fmsdc2_hck_occ", 23),
+	GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
+		    "infra_peri_133m", 24),
+	GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
+		    "infra_66m_phck", 25),
+	GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
+		    "infra_133m_mck", 26),
+	GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "infra_nfi_o", 27),
+	GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
+		    "infra_133m_mck", 29),
+	GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
+		    "infra_66m_phck", 31),
+	/* INFRA3 */
+	GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
+		    "infra_133m_phck", 0),
+	GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
+		    "infra_133m_phck", 1),
+	GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "infra_66m_phck",
+		    2),
+	GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
+		    "infra_66m_phck", 3),
+	GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
+		    "infra_usb_sys_o_p1", 5),
+	GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "infra_usb_o_p1", 7),
+	GATE_CRITICAL(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
+		      "infra_usb_frmcnt_o_p1", &infra3_cg_regs, 9),
+	GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
+		    "infra_usb_pipe_o_p1", 11),
+	GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
+		    "infra_usb_utmi_o_p1", 13),
+	GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
+		    "infra_usb_xhci_o_p1", 15),
+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
+		    "infra_pcie_gfmux_tl_ck_o_p0_sel", 20),
+	GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
+		    "infra_pcie_gfmux_tl_ck_o_p1_sel", 21),
+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
+		    "infra_pcie_pipe_ck_occ_p0", 24),
+	GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
+		    "infra_pcie_pipe_ck_occ_p1", 25),
+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
+		    "infra_133m_phck", 28),
+	GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
+		    "infra_133m_phck", 29),
+	/* INFRA0 */
+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
+		    "infra_pcie_peri_ck_26m_ck_p0", "infra_f26m_o0", 7),
+	GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
+		    "infra_pcie_peri_ck_26m_ck_p1", "infra_f26m_o0", 8),
+};
+
+static const struct mtk_gate_regs sgmii0_cg_regs = {
+	.set_ofs = 0xE4,
+	.clr_ofs = 0xE4,
+	.sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII0(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .name = _name, .parent_name = _parent,              \
+		.regs = &sgmii0_cg_regs, .shift = _shift,                      \
+		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
+	}
+
+static const struct mtk_gate sgmii0_clks[] __initconst = {
+	GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", "clkxtal", 2),
+	GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", "clkxtal", 3),
+};
+
+static const struct mtk_gate_regs sgmii1_cg_regs = {
+	.set_ofs = 0xE4,
+	.clr_ofs = 0xE4,
+	.sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII1(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .name = _name, .parent_name = _parent,              \
+		.regs = &sgmii1_cg_regs, .shift = _shift,                      \
+		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
+	}
+
+static const struct mtk_gate sgmii1_clks[] __initconst = {
+	GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", "clkxtal", 2),
+	GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", "clkxtal", 3),
+};
+
+static const struct mtk_gate_regs ethdma_cg_regs = {
+	.set_ofs = 0x30,
+	.clr_ofs = 0x30,
+	.sta_ofs = 0x30,
+};
+
+#define GATE_ETHDMA(_id, _name, _parent, _shift)                               \
+	{                                                                      \
+		.id = _id, .name = _name, .parent_name = _parent,              \
+		.regs = &ethdma_cg_regs, .shift = _shift,                      \
+		.ops = &mtk_clk_gate_ops_no_setclr_inv,                        \
+	}
+
+static const struct mtk_gate ethdma_clks[] __initconst = {
+	GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x", 6),
+	GATE_ETHDMA(CK_ETHDMA_GP2_EN, "ethdma_gp2_en", "netsys_500m", 7),
+	GATE_ETHDMA(CK_ETHDMA_GP1_EN, "ethdma_gp1_en", "netsys_500m", 8),
+	GATE_ETHDMA(CK_ETHDMA_GP3_EN, "ethdma_gp3_en", "netsys_500m", 10),
+};
+
+#define MT7987_PLL_FMAX	     (2500UL * MHZ)
+#define MT7987_PCW_CHG_SHIFT 2
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,     \
+	      _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,         \
+	      _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, _div_table,   \
+	      _parent_name)                                                    \
+	{                                                                      \
+		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
+		.en_mask = _en_mask, .flags = _flags,                          \
+		.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7987_PLL_FMAX,   \
+		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
+		.tuner_reg = _tuner_reg, .tuner_en_reg = _tuner_en_reg,        \
+		.tuner_en_bit = _tuner_en_bit, .pcw_reg = _pcw_reg,            \
+		.pcw_shift = _pcw_shift, .pcw_chg_reg = _pcw_chg_reg,          \
+		.pcw_chg_shift = MT7987_PCW_CHG_SHIFT,                         \
+		.div_table = _div_table, .parent_name = _parent_name,          \
+	}
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,       \
+	    _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,           \
+	    _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, _parent_name)   \
+	PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask,     \
+	      _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,         \
+	      _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL,         \
+	      _parent_name)
+
+static const struct mtk_pll_data plls[] = {
+	PLL(CK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
+	    23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114, "clkxtal"),
+	PLL(CK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
+	    0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134, "clkxtal"),
+	PLL(CK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
+	    HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144,
+	    "clkxtal"),
+	PLL(CK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
+	    HAVE_RST_BAR | PLL_AO, 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
+	    0x0154, "clkxtal"),
+	PLL(CK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0,
+	    32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164, "clkxtal"),
+	PLL(CK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
+	    0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174, "clkxtal"),
+	PLL(CK_APMIXED_ARM_LL, "arm_ll", 0x0104, 0x0110, 0x00000001, 0, 0, 32,
+	    0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104, "clkxtal"),
+	PLL(CK_APMIXED_MSDCPLL, "msdcpll", 0x0124, 0x0130, 0x00000001, 0, 0, 32,
+	    0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124, "clkxtal"),
+};
+
+static struct clk_onecell_data *mt7987_top_clk_data __initdata;
+static struct clk_onecell_data *mt7987_pll_clk_data __initdata;
+
+static void __init mtk_infracfg_ao_init(struct device_node *node)
+{
+	struct clk_onecell_data *clk_data;
+	int r;
+	void __iomem *base;
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s(): ioremap failed\n", __func__);
+		return;
+	}
+
+	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs),
+				 mt7987_top_clk_data);
+	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
+			       &mt7987_clk_lock, clk_data);
+	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+			       clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+	if (r)
+		pr_err("%s(): could not register clock provider: %d\n",
+		       __func__, r);
+}
+CLK_OF_DECLARE(mtk_infracfg_ao, "mediatek,mt7987-infracfg_ao",
+	       mtk_infracfg_ao_init);
+
+static void __init mtk_topckgen_init(struct device_node *node)
+{
+	int r;
+	void __iomem *base;
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s(): ioremap failed\n", __func__);
+		return;
+	}
+
+	mt7987_top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+				 mt7987_top_clk_data);
+	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
+			       &mt7987_clk_lock, mt7987_top_clk_data);
+	mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+				    base, &mt7987_clk_lock,
+				    mt7987_top_clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get,
+				mt7987_top_clk_data);
+
+	if (r)
+		pr_err("%s(): could not register clock provider: %d\n",
+		       __func__, r);
+}
+CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt7987-topckgen", mtk_topckgen_init);
+
+static void __init mtk_apmixedsys_init(struct device_node *node)
+{
+	int r;
+
+	mt7987_pll_clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+
+	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+			      mt7987_pll_clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get,
+				mt7987_pll_clk_data);
+
+	if (r)
+		pr_err("%s(): could not register clock provider: %d\n",
+		       __func__, r);
+}
+CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt7987-apmixedsys",
+	       mtk_apmixedsys_init);
+
+static void __init mtk_sgmiisys_0_init(struct device_node *node)
+{
+	struct clk_onecell_data *clk_data;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_SGMII0_NR_CLK);
+
+	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
+			       clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+	if (r)
+		pr_err("%s(): could not register clock provider: %d\n",
+		       __func__, r);
+}
+CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7987-sgmiisys_0",
+	       mtk_sgmiisys_0_init);
+
+static void __init mtk_sgmiisys_1_init(struct device_node *node)
+{
+	struct clk_onecell_data *clk_data;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_SGMII1_NR_CLK);
+
+	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
+			       clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+	if (r)
+		pr_err("%s(): could not register clock provider: %d\n",
+		       __func__, r);
+}
+CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7987-sgmiisys_1",
+	       mtk_sgmiisys_1_init);
+
+static void __init mtk_ethdma_init(struct device_node *node)
+{
+	struct clk_onecell_data *clk_data;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_ETHDMA_NR_CLK);
+
+	mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks),
+			       clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+	if (r)
+		pr_err("%s(): could not register clock provider: %d\n",
+		       __func__, r);
+}
+CLK_OF_DECLARE(mtk_ethdma, "mediatek,mt7987-ethdma", mtk_ethdma_init);
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 5626a2d..ea5ecc1 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -6493,7 +6493,7 @@
 	.ana_rgc3 = 0x128,
 	.caps = MT7987_CAPS,
 	.hw_features = MTK_HW_FEATURES,
-	.required_clks = MT7988_CLKS_BITMAP,
+	.required_clks = MT7987_CLKS_BITMAP,
 	.required_pctl = false,
 	.has_sram = false,
 	.rss_num = 4,
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 02feeaf..732d694 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1488,6 +1488,24 @@
 				 BIT(MTK_CLK_TOP_NETSYS_WARP_SEL) | \
 				 BIT(MTK_CLK_TOP_MACSEC_SEL))
 
+#define MT7987_CLKS_BITMAP	(BIT(MTK_CLK_FE) |  BIT(MTK_CLK_GP1) | \
+				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP3) | \
+				 BIT(MTK_CLK_SGMII_TX_250M) | \
+				 BIT(MTK_CLK_SGMII_RX_250M) | \
+				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+				 BIT(MTK_CLK_TOP_SGM_0_SEL) | \
+				 BIT(MTK_CLK_TOP_SGM_1_SEL) | \
+				 BIT(MTK_CLK_TOP_ETH_GMII_SEL) | \
+				 BIT(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
+				 BIT(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
+				 BIT(MTK_CLK_TOP_ETH_SYS_SEL) | \
+				 BIT(MTK_CLK_TOP_ETH_XGMII_SEL) | \
+				 BIT(MTK_CLK_TOP_ETH_MII_SEL) | \
+				 BIT(MTK_CLK_TOP_NETSYS_SEL) | \
+				 BIT(MTK_CLK_TOP_NETSYS_500M_SEL) | \
+				 BIT(MTK_CLK_TOP_NETSYS_PAO_2X_SEL))
+
 enum mtk_dev_state {
 	MTK_HW_INIT,
 	MTK_RESETTING
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/pinctrl/mediatek/pinctrl-mt7987.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/pinctrl/mediatek/pinctrl-mt7987.c
new file mode 100644
index 0000000..eac230f
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/pinctrl/mediatek/pinctrl-mt7987.c
@@ -0,0 +1,769 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * The MT7987 driver based on Linux generic pinctrl binding.
+ *
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Tim.Kuo <Tim.Kuo@mediatek.com>
+ */
+
+#include "pinctrl-moore.h"
+
+enum MT7987_PINCTRL_REG_PAGE {
+	GPIO_BASE,
+	IOCFG_RB_BASE,
+	IOCFG_LB_BASE,
+	IOCFG_RT1_BASE,
+	IOCFG_RT2_BASE,
+	IOCFG_TL_BASE,
+};
+
+#define MT7987_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
+
+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
+		       _x_bits)                                                \
+	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
+		       _x_bits, 32, 0)
+
+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
+		       _x_bits)                                                \
+	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
+		       _x_bits, 32, 0)
+
+
+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,    \
+			_x_bits)                                               \
+	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
+		       _x_bits, 32, 1)
+
+static const struct mtk_pin_field_calc mt7987_pin_mode_range[] = {
+	PIN_FIELD(0, 49, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_dir_range[] = {
+	PIN_FIELD(0, 49, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_di_range[] = {
+	PIN_FIELD(0, 49, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_do_range[] = {
+	PIN_FIELD(0, 49, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_ies_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x20, 0x10, 3, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x20, 0x10, 2, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x20, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x20, 0x10, 2, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x20, 0x10, 1, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x20, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x20, 0x10, 0, 1),
+	PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x20, 0x10, 4, 1),
+	PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x10, 0x10, 2, 1),
+	PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x10, 0x10, 1, 1),
+	PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x10, 0x10, 0, 1),
+	PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x10, 0x10, 3, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x10, 0x10, 4, 1),
+	PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x20, 0x10, 0, 1),
+	PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x20, 0x10, 15, 1),
+	PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x20, 0x10, 3, 1),
+	PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x20, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x20, 0x10, 6, 1),
+	PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x20, 0x10, 4, 1),
+	PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x20, 0x10, 5, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x20, 0x10, 8, 1),
+	PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x20, 0x10, 9, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x20, 0x10, 12, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x20, 0x10, 11, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x20, 0x10, 10, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x20, 0x10, 13, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x20, 0x10, 14, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x20, 0x10, 9, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x20, 0x10, 7, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x20, 0x10, 8, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x20, 0x10, 10, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x20, 0x10, 5, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x20, 0x10, 6, 1),
+	PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
+	PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
+	PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x20, 0x10, 4, 1),
+	PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x20, 0x10, 3, 1),
+	PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x20, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x20, 0x10, 5, 1),
+	PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x20, 0x10, 1, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x20, 0x10, 2, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x20, 0x10, 0, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x20, 0x10, 1, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x20, 0x10, 4, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x20, 0x10, 5, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x20, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x20, 0x10, 9, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x20, 0x10, 10, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x20, 0x10, 7, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x20, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_smt_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x90, 0x10, 3, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x90, 0x10, 2, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x90, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x90, 0x10, 2, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x90, 0x10, 1, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x90, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x90, 0x10, 0, 1),
+	PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x90, 0x10, 4, 1),
+	PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
+	PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
+	PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
+	PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
+	PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0xA0, 0x10, 0, 1),
+	PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0xA0, 0x10, 15, 1),
+	PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0xA0, 0x10, 3, 1),
+	PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0xA0, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0xA0, 0x10, 6, 1),
+	PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0xA0, 0x10, 4, 1),
+	PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0xA0, 0x10, 5, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0xA0, 0x10, 8, 1),
+	PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0xA0, 0x10, 9, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0xA0, 0x10, 12, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0xA0, 0x10, 11, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0xA0, 0x10, 10, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0xA0, 0x10, 13, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0xA0, 0x10, 14, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x90, 0x10, 9, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x90, 0x10, 7, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x90, 0x10, 8, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x90, 0x10, 10, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x90, 0x10, 5, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x90, 0x10, 6, 1),
+	PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
+	PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
+	PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
+	PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
+	PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x60, 0x10, 5, 1),
+	PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0xA0, 0x10, 1, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0xA0, 0x10, 2, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x90, 0x10, 0, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x90, 0x10, 1, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x90, 0x10, 4, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x90, 0x10, 5, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x90, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x90, 0x10, 9, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x90, 0x10, 10, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x90, 0x10, 7, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x90, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_pu_range[] = {
+	PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
+	PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
+	PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
+	PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x40, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_pd_range[] = {
+	PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x30, 0x10, 2, 1),
+	PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x30, 0x10, 0, 1),
+	PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x30, 0x10, 4, 1),
+	PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x30, 0x10, 3, 1),
+	PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x30, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x30, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_drv_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x0, 0x10, 9, 3),
+	PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x0, 0x10, 6, 3),
+	PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x10, 0x10, 3, 3),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x0, 0x10, 6, 3),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x0, 0x10, 3, 3),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x0, 0x10, 9, 3),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x0, 0x10, 0, 3),
+	PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x0, 0x10, 12, 3),
+	PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x0, 0x10, 6, 3),
+	PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x0, 0x10, 3, 3),
+	PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x0, 0x10, 0, 3),
+	PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x0, 0x10, 9, 3),
+	PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x0, 0x10, 12, 3),
+	PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x0, 0x10, 0, 3),
+	PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x10, 0x10, 15, 3),
+	PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x0, 0x10, 9, 3),
+	PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x0, 0x10, 21, 3),
+	PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x0, 0x10, 18, 3),
+	PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x0, 0x10, 12, 3),
+	PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x0, 0x10, 15, 3),
+	PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x0, 0x10, 24, 3),
+	PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x0, 0x10, 27, 3),
+	PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x10, 0x10, 6, 3),
+	PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x10, 0x10, 3, 3),
+	PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x10, 0x10, 0, 3),
+	PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x10, 0x10, 9, 3),
+	PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x10, 0x10, 12, 3),
+	PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x0, 0x10, 27, 3),
+	PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x0, 0x10, 21, 3),
+	PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x0, 0x10, 24, 3),
+	PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x10, 0x10, 0, 3),
+	PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x0, 0x10, 15, 3),
+	PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x0, 0x10, 18, 3),
+	PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x0, 0x10, 6, 3),
+	PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x0, 0x10, 0, 3),
+	PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x0, 0x10, 12, 3),
+	PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x0, 0x10, 9, 3),
+	PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x0, 0x10, 3, 3),
+	PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x0, 0x10, 15, 3),
+	PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x0, 0x10, 3, 3),
+	PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x0, 0x10, 6, 3),
+	PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x0, 0x10, 0, 3),
+	PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x0, 0x10, 3, 3),
+	PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x0, 0x10, 12, 3),
+	PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x0, 0x10, 15, 3),
+	PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x0, 0x10, 18, 3),
+	PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x0, 0x10, 27, 3),
+	PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x10, 0x10, 0, 3),
+	PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x0, 0x10, 21, 3),
+	PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x0, 0x10, 24, 3),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_pupd_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x30, 0x10, 3, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x30, 0x10, 2, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x30, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
+	PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
+	PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x20, 0x10, 2, 1),
+	PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x20, 0x10, 1, 1),
+	PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x20, 0x10, 0, 1),
+	PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x20, 0x10, 3, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x20, 0x10, 4, 1),
+	PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x30, 0x10, 0, 1),
+	PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x30, 0x10, 15, 1),
+	PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x30, 0x10, 3, 1),
+	PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x30, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x30, 0x10, 6, 1),
+	PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x30, 0x10, 4, 1),
+	PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x30, 0x10, 5, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x30, 0x10, 8, 1),
+	PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x30, 0x10, 9, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x30, 0x10, 12, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x30, 0x10, 11, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x30, 0x10, 10, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x30, 0x10, 13, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x30, 0x10, 14, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x30, 0x10, 9, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x30, 0x10, 7, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x30, 0x10, 8, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x30, 0x10, 10, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
+
+	PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x30, 0x10, 1, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x30, 0x10, 2, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x30, 0x10, 0, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x30, 0x10, 1, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x30, 0x10, 4, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x30, 0x10, 5, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x30, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_r0_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x40, 0x10, 3, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x40, 0x10, 2, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x40, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
+	PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x30, 0x10, 2, 1),
+	PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x30, 0x10, 1, 1),
+	PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x30, 0x10, 0, 1),
+	PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x30, 0x10, 3, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x30, 0x10, 4, 1),
+	PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x40, 0x10, 0, 1),
+	PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x40, 0x10, 15, 1),
+	PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x40, 0x10, 3, 1),
+	PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x40, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x40, 0x10, 6, 1),
+	PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x40, 0x10, 5, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x40, 0x10, 8, 1),
+	PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x40, 0x10, 9, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x40, 0x10, 12, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x40, 0x10, 11, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x40, 0x10, 10, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x40, 0x10, 13, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x40, 0x10, 14, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x40, 0x10, 9, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x40, 0x10, 7, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x40, 0x10, 8, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x40, 0x10, 10, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x40, 0x10, 6, 1),
+
+	PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x40, 0x10, 1, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x40, 0x10, 2, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x40, 0x10, 0, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x40, 0x10, 1, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x40, 0x10, 5, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x40, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x40, 0x10, 9, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x40, 0x10, 10, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x40, 0x10, 7, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7987_pin_r1_range[] = {
+	PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x50, 0x10, 3, 1),
+	PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x50, 0x10, 2, 1),
+	PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x50, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
+	PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
+	PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
+	PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
+	PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
+	PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
+	PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x40, 0x10, 1, 1),
+	PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
+	PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 3, 1),
+	PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 4, 1),
+	PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x50, 0x10, 0, 1),
+	PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x50, 0x10, 15, 1),
+	PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x50, 0x10, 3, 1),
+	PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x50, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x50, 0x10, 6, 1),
+	PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x50, 0x10, 4, 1),
+	PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x50, 0x10, 5, 1),
+	PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x50, 0x10, 8, 1),
+	PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x50, 0x10, 9, 1),
+	PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x50, 0x10, 12, 1),
+	PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x50, 0x10, 11, 1),
+	PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x50, 0x10, 10, 1),
+	PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x50, 0x10, 13, 1),
+	PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x50, 0x10, 14, 1),
+	PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x50, 0x10, 9, 1),
+	PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x50, 0x10, 7, 1),
+	PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x50, 0x10, 8, 1),
+	PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x50, 0x10, 10, 1),
+	PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
+	PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
+
+	PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x50, 0x10, 1, 1),
+	PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x50, 0x10, 2, 1),
+	PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x50, 0x10, 0, 1),
+	PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x50, 0x10, 1, 1),
+	PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x50, 0x10, 4, 1),
+	PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x50, 0x10, 5, 1),
+	PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x50, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x50, 0x10, 9, 1),
+	PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x50, 0x10, 10, 1),
+	PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
+	PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
+};
+
+static const unsigned int mt7987_pull_type[] = {
+	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/
+	MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/
+	MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/
+	MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
+	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
+};
+
+static const struct mtk_pin_reg_calc mt7987_reg_cals[] = {
+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range),
+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range),
+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7987_pin_di_range),
+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7987_pin_do_range),
+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7987_pin_smt_range),
+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7987_pin_ies_range),
+	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7987_pin_pu_range),
+	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7987_pin_pd_range),
+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7987_pin_drv_range),
+	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7987_pin_pupd_range),
+	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7987_pin_r0_range),
+	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7987_pin_r1_range),
+};
+
+static const struct mtk_pin_desc mt7987_pins[] = {
+	MT7987_PIN(0, "GPIO_WPS"),
+	MT7987_PIN(1, "GPIO_RESET"),
+	MT7987_PIN(2, "SYS_WATCHDOG"),
+	MT7987_PIN(3, "JTAG_JTDO"),
+	MT7987_PIN(4, "JTAG_JTDI"),
+	MT7987_PIN(5, "JTAG_JTMS"),
+	MT7987_PIN(6, "JTAG_JTCLK"),
+	MT7987_PIN(7, "JTAG_JTRST_N"),
+	MT7987_PIN(8, "PCM_DTX_I2S_DOUT"),
+	MT7987_PIN(9, "PCM_DRX_I2S_DIN"),
+	MT7987_PIN(10, "PCM_CLK_I2S_BCLK"),
+	MT7987_PIN(11, "PCM_FS_I2S_LRCK"),
+	MT7987_PIN(12, "PCM_MCK_I2S_MCLK"),
+	MT7987_PIN(13, "PWM0"),
+	MT7987_PIN(14, "USB_VBUS"),
+	MT7987_PIN(15, "SPI0_CLK"),
+	MT7987_PIN(16, "SPI0_MOSI"),
+	MT7987_PIN(17, "SPI0_MISO"),
+	MT7987_PIN(18, "SPI0_CS"),
+	MT7987_PIN(19, "SPI0_HOLD"),
+	MT7987_PIN(20, "SPI0_WP"),
+	MT7987_PIN(21, "SPI1_CLK"),
+	MT7987_PIN(22, "SPI1_MOSI"),
+	MT7987_PIN(23, "SPI1_MISO"),
+	MT7987_PIN(24, "SPI1_CS"),
+	MT7987_PIN(25, "SPI2_CLK"),
+	MT7987_PIN(26, "SPI2_MOSI"),
+	MT7987_PIN(27, "SPI2_MISO"),
+	MT7987_PIN(28, "SPI2_CS"),
+	MT7987_PIN(29, "SPI2_HOLD"),
+	MT7987_PIN(30, "SPI2_WP"),
+	MT7987_PIN(31, "UART0_RXD"),
+	MT7987_PIN(32, "UART0_TXD"),
+	MT7987_PIN(33, "PCIE_PERESET_N_0"),
+	MT7987_PIN(34, "PCIE_CLK_REQ_0"),
+	MT7987_PIN(35, "PCIE_WAKE_N_0"),
+	MT7987_PIN(36, "PCIE_PERESET_N_1"),
+	MT7987_PIN(37, "PCIE_CLK_REQ_1"),
+	MT7987_PIN(38, "PCIE_WAKE_N_1"),
+	MT7987_PIN(39, "SMI_MDC"),
+	MT7987_PIN(40, "SMI_MDIO"),
+	MT7987_PIN(41, "GBE_INT"),
+	MT7987_PIN(42, "GBE_RESET"),
+	MT7987_PIN(43, "I2C_SCLK"),
+	MT7987_PIN(44, "I2C_SDATA"),
+	MT7987_PIN(45, "2P5G_LED0"),
+	MT7987_PIN(46, "UART1_RXD"),
+	MT7987_PIN(47, "UART1_TXD"),
+	MT7987_PIN(48, "UART1_CTS"),
+	MT7987_PIN(49, "UART1_RTS"),
+};
+
+/* watchdog */
+static const int mt7987_watchdog_pins[] = {2};
+static const int mt7987_watchdog_funcs[] = {1};
+
+/* jtag */
+static const int mt7987_jtag_pins[] = {3, 4, 5, 6, 7};
+static const int mt7987_jtag_funcs[] = {1, 1, 1, 1, 1};
+
+/* pcm */
+static const int mt7987_pcm0_0_pins[] = {3, 4, 5, 6, 7};
+static const int mt7987_pcm0_0_funcs[] = {2, 2, 2, 2, 2};
+
+static const int mt7987_pcm0_1_pins[] = {8, 9, 10, 11, 12};
+static const int mt7987_pcm0_1_funcs[] = {1, 1, 1, 1, 1};
+
+/* uart */
+static const int mt7987_uart0_pins[] = {31, 32};
+static const int mt7987_uart0_funcs[] = {1, 1};
+
+static const int mt7987_uart1_0_pins[] = {3, 4, 5, 6};
+static const int mt7987_uart1_0_funcs[] = {3, 3, 3, 3};
+
+static const int mt7987_uart1_1_pins[] = {21, 22, 23, 24};
+static const int mt7987_uart1_1_funcs[] = {3, 3, 3, 3};
+
+static const int mt7987_uart1_2_pins[] = {46, 47, 48, 49};
+static const int mt7987_uart1_2_funcs[] = {1, 1, 1, 1};
+
+static const int mt7987_uart2_0_pins[] = {8, 9, 10, 11};
+static const int mt7987_uart2_0_funcs[] = {2, 2, 2, 2};
+
+static const int mt7987_uart2_1_pins[] = {25, 26, 27, 28};
+static const int mt7987_uart2_1_funcs[] = {2, 2, 2, 2};
+
+/* pwm */
+static const int mt7987_pwm0_pins[] = {13};
+static const int mt7987_pwm0_funcs[] = {1};
+
+static const int mt7987_pwm1_0_pins[] = {7};
+static const int mt7987_pwm1_0_funcs[] = {3};
+
+static const int mt7987_pwm1_1_pins[] = {43};
+static const int mt7987_pwm1_1_funcs[] = {2};
+
+static const int mt7987_pwm2_0_pins[] = {12};
+static const int mt7987_pwm2_0_funcs[] = {2};
+
+static const int mt7987_pwm2_1_pins[] = {44};
+static const int mt7987_pwm2_1_funcs[] = {2};
+
+/* vbus */
+static const int mt7987_drv_vbus_p1_pins[] = {14};
+static const int mt7987_drv_vbus_p1_funcs[] = {1};
+
+static const int mt7987_drv_vbus_pins[] = {48};
+static const int mt7987_drv_vbus_funcs[] = {3};
+
+/* 2p5gbe_led */
+static const int mt7987_2p5gbe_led0_pins[] = {45};
+static const int mt7987_2p5gbe_led0_funcs[] = {1};
+
+static const int mt7987_2p5gbe_led1_0_pins[] = {13};
+static const int mt7987_2p5gbe_led1_0_funcs[] = {2};
+
+static const int mt7987_2p5gbe_led1_1_pins[] = {49};
+static const int mt7987_2p5gbe_led1_1_funcs[] = {3};
+
+/* mdc, mdio */
+static const int mt7987_2p5g_ext_mdc_mdio_pins[] = {23, 24};
+static const int mt7987_2p5g_ext_mdc_mdio_funcs[] = {4, 4};
+
+static const int mt7987_mdc_mdio_pins[] = {39, 40};
+static const int mt7987_mdc_mdio_funcs[] = {1, 1};
+
+/* spi */
+static const int mt7987_spi0_pins[] = {15, 16, 17, 18};
+static const int mt7987_spi0_funcs[] = {1, 1, 1, 1};
+
+static const int mt7987_spi0_wp_hold_pins[] = {19, 20};
+static const int mt7987_spi0_wp_hold_funcs[] = {1, 1};
+
+static const int mt7987_spi1_pins[] = {21, 22, 23, 24};
+static const int mt7987_spi1_funcs[] = {1, 1, 1, 1};
+
+static const int mt7987_spi1_1_pins[] = {46, 47, 48, 49};
+static const int mt7987_spi1_1_funcs[] = {2, 2, 2, 2};
+
+static const int mt7987_spi2_pins[] = {25, 26, 27, 28};
+static const int mt7987_spi2_funcs[] = {1, 1, 1, 1};
+
+static const int mt7987_spi2_wp_hold_pins[] = {29, 30};
+static const int mt7987_spi2_wp_hold_funcs[] = {1, 1};
+
+/* emmc */
+static const int mt7987_emmc_45_pins[] = {14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24};
+static const int mt7987_emmc_45_funcs[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2};
+
+/* sd */
+static const int mt7987_sd_pins[] = {15, 16, 17, 18, 23, 24};
+static const int mt7987_sd_funcs[] = {2, 2, 2, 2, 2, 2};
+
+/* i2c */
+static const int mt7987_i2c0_0_pins[] = {29, 30};
+static const int mt7987_i2c0_0_funcs[] = {2, 2};
+
+static const int mt7987_i2c0_1_pins[] = {39, 40};
+static const int mt7987_i2c0_1_funcs[] = {2, 2};
+
+static const int mt7987_i2c0_2_pins[] = {43, 44};
+static const int mt7987_i2c0_2_funcs[] = {1, 1};
+
+/* pcie */
+static const int mt7987_pcie0_pereset_pins[] = {33};
+static const int mt7987_pcie0_pereset_funcs[] = {1};
+
+static const int mt7987_pcie0_clkreq_pins[] = {34};
+static const int mt7987_pcie0_clkreq_funcs[] = {1};
+
+static const int mt7987_pcie0_wake_pins[] = {35};
+static const int mt7987_pcie0_wake_funcs[] = {1};
+
+static const int mt7987_pcie1_pereset_pins[] = {36};
+static const int mt7987_pcie1_pereset_funcs[] = {1};
+
+static const int mt7987_pcie1_clkreq_pins[] = {37};
+static const int mt7987_pcie1_clkreq_funcs[] = {1};
+
+static const int mt7987_pcie1_wake_pins[] = {38};
+static const int mt7987_pcie1_wake_funcs[] = {1};
+
+static const int mt7987_pcie_phy_i2c_pins[] = {43, 44};
+static const int mt7987_pcie_phy_i2c_funcs[] = {3, 3};
+
+/* snfi */
+static const int mt7987_snfi_pins[] = {25, 26, 27, 28, 29, 30};
+static const int mt7987_snfi_funcs[] = {3, 3, 3, 3, 3, 3};
+
+/*
+ * - int hsgmii :
+ *	For pin41 and pin46, they now can only be used as gpio mode for polling
+ *	event. Hence, there's no need to open their pinctrl setting.
+ * - dfd, udi :
+ *	Due to dfd & udi functions are only used as detection pins for cpu during
+ *      dvt testing stage, we also remove their pinctrl setting.
+ */
+
+//static mt7987_hsgmii_pins[] = {};
+//static mt7987_hsgmii_functs[] = {};
+//static mt7987_dfd_pins[] = {};
+//static mt7987_dfd_functs[] = {};
+//static mt7987_udi_pins[] = {};
+//static mt7987_udi_functs[] = {};
+
+static const struct group_desc mt7987_groups[] = {
+	PINCTRL_PIN_GROUP("watchdog", mt7987_watchdog),
+	PINCTRL_PIN_GROUP("jtag", mt7987_jtag),
+	PINCTRL_PIN_GROUP("pcm0_0", mt7987_pcm0_0),
+	PINCTRL_PIN_GROUP("pcm0_1", mt7987_pcm0_1),
+	PINCTRL_PIN_GROUP("uart0", mt7987_uart0),
+	PINCTRL_PIN_GROUP("uart1_0", mt7987_uart1_0),
+	PINCTRL_PIN_GROUP("uart1_1", mt7987_uart1_1),
+	PINCTRL_PIN_GROUP("uart1_2", mt7987_uart1_2),
+	PINCTRL_PIN_GROUP("uart2_0", mt7987_uart2_0),
+	PINCTRL_PIN_GROUP("uart2_1", mt7987_uart2_1),
+	PINCTRL_PIN_GROUP("pwm0", mt7987_pwm0),
+	PINCTRL_PIN_GROUP("pwm1_0", mt7987_pwm1_0),
+	PINCTRL_PIN_GROUP("pwm1_1", mt7987_pwm1_1),
+	PINCTRL_PIN_GROUP("pwm2_0", mt7987_pwm2_0),
+	PINCTRL_PIN_GROUP("pwm2_1", mt7987_pwm2_1),
+	PINCTRL_PIN_GROUP("drv_vbus_p1", mt7987_drv_vbus_p1),
+	PINCTRL_PIN_GROUP("drv_vbus", mt7987_drv_vbus),
+	PINCTRL_PIN_GROUP("2p5gbe_led0", mt7987_2p5gbe_led0),
+	PINCTRL_PIN_GROUP("2p5gbe_led1_0", mt7987_2p5gbe_led1_0),
+	PINCTRL_PIN_GROUP("2p5gbe_led1_1", mt7987_2p5gbe_led1_1),
+	PINCTRL_PIN_GROUP("2p5g_ext_mdc_mdio", mt7987_2p5g_ext_mdc_mdio),
+	PINCTRL_PIN_GROUP("mdc_mdio", mt7987_mdc_mdio),
+	PINCTRL_PIN_GROUP("spi0", mt7987_spi0),
+	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7987_spi0_wp_hold),
+	PINCTRL_PIN_GROUP("spi1", mt7987_spi1),
+	PINCTRL_PIN_GROUP("spi1_1", mt7987_spi1_1),
+	PINCTRL_PIN_GROUP("spi2", mt7987_spi2),
+	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7987_spi2_wp_hold),
+	PINCTRL_PIN_GROUP("emmc_45", mt7987_emmc_45),
+	PINCTRL_PIN_GROUP("sd", mt7987_sd),
+	PINCTRL_PIN_GROUP("i2c0_0", mt7987_i2c0_0),
+	PINCTRL_PIN_GROUP("i2c0_1", mt7987_i2c0_1),
+	PINCTRL_PIN_GROUP("i2c0_2", mt7987_i2c0_2),
+	PINCTRL_PIN_GROUP("pcie0_pereset", mt7987_pcie0_pereset),
+	PINCTRL_PIN_GROUP("pcie0_clkreq", mt7987_pcie0_clkreq),
+	PINCTRL_PIN_GROUP("pcie0_wake", mt7987_pcie0_wake),
+	PINCTRL_PIN_GROUP("pcie1_pereset", mt7987_pcie1_pereset),
+	PINCTRL_PIN_GROUP("pcie1_clkreq", mt7987_pcie1_clkreq),
+	PINCTRL_PIN_GROUP("pcie1_wake", mt7987_pcie1_wake),
+	PINCTRL_PIN_GROUP("pcie1_pcie_phy_i2c", mt7987_pcie_phy_i2c),
+	PINCTRL_PIN_GROUP("snfi", mt7987_snfi),
+};
+
+static const char *const mt7987_wdt_groups[] = {"watchdog",};
+static const char *const mt7987_jtag_groups[] = {"jtag",};
+static const char *const mt7987_pcm_groups[] = {"pcm0_0", "pcm0_1"};
+static const char *const mt7987_uart_groups[] = {"uart0", "uart1_0", "uart1_1",
+						 "uart1_2", "uart2_0", "uart2_1",};
+static const char *const mt7987_pwm_groups[] = {"pwm0", "pwm1_0", "pwm1_1", "pwm2_0",
+					       "pwm2_1",};
+static const char *const mt7987_usb_groups[] = {"drv_vbus_p1", "drv_vbus",};
+static const char *const mt7987_led_groups[] = {"2p5gbe_led0", "2p5gbe_led1_0",
+					       "2p5gbe_led1_1",};
+static const char *const mt7987_ethernet_groups[] = {"2p5g_ext_mdc_mdio", "mdc_mdio",};
+static const char *const mt7987_spi_groups[] = {"spi0", "spi0_wp_hold", "spi1",
+						"spi1_1", "spi2", "spi2_wp_hold",};
+static const char *const mt7987_flash_groups[] = {"emmc_45", "snfi", "sd"};
+static const char *const mt7987_i2c_groups[] = {"i2c0_0", "i2c0_1", "i2c0_2",};
+static const char *const mt7987_pcie_groups[] = {"pcie_phy_i2c", "pcie0_pereset",
+						 "pcie0_clkreq", "pcie0_wake",
+						 "pcie1_pereset", "pcie1_clkreq",
+						 "pcie1_wake",};
+static const char *const mt7987_i2s_groups[] = {"pcm0_0", "pcm0_1"};
+
+
+static const struct function_desc mt7987_functions[] = {
+	{"wdt", mt7987_wdt_groups, ARRAY_SIZE(mt7987_wdt_groups)},
+	{"jtag", mt7987_jtag_groups, ARRAY_SIZE(mt7987_jtag_groups)},
+	{"pcm", mt7987_pcm_groups, ARRAY_SIZE(mt7987_pcm_groups)},
+	{"uart", mt7987_uart_groups, ARRAY_SIZE(mt7987_uart_groups)},
+	{"pwm", mt7987_pwm_groups, ARRAY_SIZE(mt7987_pwm_groups)},
+	{"usb", mt7987_usb_groups, ARRAY_SIZE(mt7987_usb_groups)},
+	{"led", mt7987_led_groups, ARRAY_SIZE(mt7987_led_groups)},
+	{"ethernet", mt7987_ethernet_groups, ARRAY_SIZE(mt7987_ethernet_groups)},
+	{"spi", mt7987_spi_groups, ARRAY_SIZE(mt7987_spi_groups)},
+	{"flash", mt7987_flash_groups, ARRAY_SIZE(mt7987_flash_groups)},
+	{"i2c", mt7987_i2c_groups, ARRAY_SIZE(mt7987_i2c_groups)},
+	{"pcie", mt7987_pcie_groups, ARRAY_SIZE(mt7987_pcie_groups)},
+	{"i2s", mt7987_i2s_groups, ARRAY_SIZE(mt7987_i2s_groups)},
+};
+
+
+static const struct mtk_eint_hw mt7987_eint_hw = {
+	.port_mask = 7,
+	.ports = 7,
+	.ap_num = ARRAY_SIZE(mt7987_pins),
+	.db_cnt = 16,
+};
+
+static const char * const mt7987_pinctrl_register_base_names[] = {
+	"gpio_base", "iocfg_rb_base", "iocfg_lb_base", "iocfg_rt1_base",
+	"iocfg_rt2_base", "iocfg_tl_base",
+};
+
+static struct mtk_pin_soc mt7987_data = {
+	.reg_cal = mt7987_reg_cals,
+	.pins = mt7987_pins,
+	.npins = ARRAY_SIZE(mt7987_pins),
+	.grps = mt7987_groups,
+	.ngrps = ARRAY_SIZE(mt7987_groups),
+	.funcs = mt7987_functions,
+	.nfuncs = ARRAY_SIZE(mt7987_functions),
+	.eint_hw = &mt7987_eint_hw,
+	.gpio_m = 0,
+	.ies_present = false,
+	.base_names = mt7987_pinctrl_register_base_names,
+	.nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names),
+	.bias_disable_set = mtk_pinconf_bias_disable_set,
+	.bias_disable_get = mtk_pinconf_bias_disable_get,
+	.bias_set = mtk_pinconf_bias_set,
+	.bias_get = mtk_pinconf_bias_get,
+	.pull_type = mt7987_pull_type,
+	.bias_set_combo = mtk_pinconf_bias_set_combo,
+	.bias_get_combo = mtk_pinconf_bias_get_combo,
+	.drive_set = mtk_pinconf_drive_set_rev1,
+	.drive_get = mtk_pinconf_drive_get_rev1,
+	.adv_pull_get = mtk_pinconf_adv_pull_get,
+	.adv_pull_set = mtk_pinconf_adv_pull_set,
+};
+
+static const struct of_device_id mt7987_pinctrl_of_match[] = {
+	{
+		.compatible = "mediatek,mt7987-pinctrl",
+	},
+	{}
+};
+
+static int mt7987_pinctrl_probe(struct platform_device *pdev)
+{
+	return mtk_moore_pinctrl_probe(pdev, &mt7987_data);
+}
+
+static struct platform_driver mt7987_pinctrl_driver = {
+	.driver = {
+		.name = "mt7987-pinctrl",
+		.of_match_table = mt7987_pinctrl_of_match,
+	},
+	.probe = mt7987_pinctrl_probe,
+};
+
+static int __init mt7987_pinctrl_init(void)
+{
+	return platform_driver_register(&mt7987_pinctrl_driver);
+}
+arch_initcall(mt7987_pinctrl_init);
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/include/dt-bindings/clock/mt7987-clk.h b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/include/dt-bindings/clock/mt7987-clk.h
new file mode 100644
index 0000000..f9edd37
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/include/dt-bindings/clock/mt7987-clk.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) 2024 MediaTek Inc.
+ * Author: Lu Tang <Lu.Tang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7987_H
+#define _DT_BINDINGS_CLK_MT7987_H
+
+/* INFRACFG_AO */
+
+#define CK_INFRA_CK_F26M		0
+#define CK_INFRA_PWM_O			1
+#define CK_INFRA_INFRA_F32K		2
+#define CK_INFRA_PCIE_OCC_P0		3
+#define CK_INFRA_PCIE_OCC_P1		4
+#define CK_INFRA_133M_HCK		5
+#define CK_INFRA_133M_PHCK		6
+#define CK_INFRA_66M_PHCK		7
+#define CK_INFRA_FAUD_L_O		8
+#define CK_INFRA_FAUD_AUD_O		9
+#define CK_INFRA_FAUD_EG2_O		10
+#define CK_INFRA_I2C_O			11
+#define CK_INFRA_UART_O0		12
+#define CK_INFRA_UART_O1		13
+#define CK_INFRA_UART_O2		14
+#define CK_INFRA_NFI_O			15
+#define CK_INFRA_SPI0_O			16
+#define CK_INFRA_SPI1_O			17
+#define CK_INFRA_SPI2_O			18
+#define CK_INFRA_LB_MUX_FRTC		19
+#define CK_INFRA_FRTC			20
+#define CK_INFRA_FMSDC200_SRC_O		21
+#define CK_INFRA_FMSDC400_O		22
+#define CK_INFRA_FMSDC2_HCK_OCC		23
+#define CK_INFRA_PERI_133M		24
+#define CK_INFRA_USB_O_P1		25
+#define CK_INFRA_USB_FRMCNT_O_P1	26
+#define CK_INFRA_USB_XHCI_O_P1		27
+#define CK_INFRA_USB_PIPE_O_P1		28
+#define CK_INFRA_USB_UTMI_O_P1		29
+#define CK_INFRA_PCIE_PIPE_OCC_P0	30
+#define CK_INFRA_PCIE_PIPE_OCC_P1	31
+#define CK_INFRA_F26M_O0		32
+#define CK_INFRA_F26M_O1		33
+#define CK_INFRA_133M_MCK		34
+#define CK_INFRA_66M_MCK		35
+#define CK_INFRA_PERI_66M_O		36
+#define CK_INFRA_USB_SYS_O_P1		37
+#define CK_INFRA_MUX_UART0_SEL		38
+#define CK_INFRA_MUX_UART1_SEL		39
+#define CK_INFRA_MUX_UART2_SEL		40
+#define CK_INFRA_MUX_SPI0_SEL		41
+#define CK_INFRA_MUX_SPI1_SEL		42
+#define CK_INFRA_MUX_SPI2_BCK_SEL	43
+#define CK_INFRA_PWM_BCK_SEL		44
+#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 45
+#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 46
+#define CK_INFRA_66M_GPT_BCK		47
+#define CK_INFRA_66M_PWM_HCK		48
+#define CK_INFRA_66M_PWM_BCK		49
+#define CK_INFRA_133M_CQDMA_BCK		50
+#define CK_INFRA_66M_AUD_SLV_BCK	51
+#define CK_INFRA_AUD_26M		52
+#define CK_INFRA_AUD_L			53
+#define CK_INFRA_AUD_AUD		54
+#define CK_INFRA_AUD_EG2		55
+#define CK_INFRA_DRAMC_F26M		56
+#define CK_INFRA_133M_DBG_ACKM		57
+#define CK_INFRA_66M_AP_DMA_BCK		58
+#define CK_INFRA_MSDC200_SRC		59
+#define CK_INFRA_66M_SEJ_BCK		60
+#define CK_INFRA_PRE_CK_SEJ_F13M	61
+#define CK_INFRA_66M_TRNG		62
+#define CK_INFRA_26M_THERM_SYSTEM	63
+#define CK_INFRA_I2C_BCK		64
+#define CK_INFRA_66M_UART0_PCK		65
+#define CK_INFRA_66M_UART1_PCK		66
+#define CK_INFRA_66M_UART2_PCK		67
+#define CK_INFRA_52M_UART0_CK		68
+#define CK_INFRA_52M_UART1_CK		69
+#define CK_INFRA_52M_UART2_CK		70
+#define CK_INFRA_NFI			71
+#define CK_INFRA_66M_NFI_HCK		72
+#define CK_INFRA_104M_SPI0		73
+#define CK_INFRA_104M_SPI1		74
+#define CK_INFRA_104M_SPI2_BCK		75
+#define CK_INFRA_66M_SPI0_HCK		76
+#define CK_INFRA_66M_SPI1_HCK		77
+#define CK_INFRA_66M_SPI2_HCK		78
+#define CK_INFRA_66M_FLASHIF_AXI	79
+#define CK_INFRA_RTC			80
+#define CK_INFRA_26M_ADC_BCK		81
+#define CK_INFRA_RC_ADC			82
+#define CK_INFRA_MSDC400		83
+#define CK_INFRA_MSDC2_HCK		84
+#define CK_INFRA_133M_MSDC_0_HCK	85
+#define CK_INFRA_66M_MSDC_0_HCK		86
+#define CK_INFRA_133M_CPUM_BCK		87
+#define CK_INFRA_BIST2FPC		88
+#define CK_INFRA_I2C_X16W_MCK_CK_P1	89
+#define CK_INFRA_I2C_X16W_PCK_CK_P1	90
+#define CK_INFRA_133M_USB_HCK		91
+#define CK_INFRA_133M_USB_HCK_CK_P1	92
+#define CK_INFRA_66M_USB_HCK		93
+#define CK_INFRA_66M_USB_HCK_CK_P1	94
+#define CK_INFRA_USB_SYS_CK_P1		95
+#define CK_INFRA_USB_CK_P1		96
+#define CK_INFRA_USB_FRMCNT_CK_P1	97
+#define CK_INFRA_USB_PIPE_CK_P1		98
+#define CK_INFRA_USB_UTMI_CK_P1		99
+#define CK_INFRA_USB_XHCI_CK_P1		100
+#define CK_INFRA_PCIE_GFMUX_TL_P0	101
+#define CK_INFRA_PCIE_GFMUX_TL_P1	102
+#define CK_INFRA_PCIE_PIPE_P0		103
+#define CK_INFRA_PCIE_PIPE_P1		104
+#define CK_INFRA_133M_PCIE_CK_P0	105
+#define CK_INFRA_133M_PCIE_CK_P1	106
+#define CK_INFRA_PCIE_PERI_26M_CK_P0	107
+#define CK_INFRA_PCIE_PERI_26M_CK_P1	108
+#define CLK_INFRA_NR_CLK		109
+
+/* TOPCKGEN */
+
+#define CK_TOP_CB_M_D2		   0
+#define CK_TOP_CB_M_D3		   1
+#define CK_TOP_M_D3_D2		   2
+#define CK_TOP_CB_M_D4		   3
+#define CK_TOP_CB_M_D8		   4
+#define CK_TOP_M_D8_D2		   5
+#define CK_TOP_CB_APLL2_196M	   6
+#define CK_TOP_CB_APLL2_D4	   7
+#define CK_TOP_CB_NET1_D3	   8
+#define CK_TOP_CB_NET1_D4	   9
+#define CK_TOP_CB_NET1_D5	   10
+#define CK_TOP_NET1_D5_D2	   11
+#define CK_TOP_NET1_D5_D4	   12
+#define CK_TOP_CB_NET1_D7	   13
+#define CK_TOP_NET1_D7_D2	   14
+#define CK_TOP_NET1_D7_D4	   15
+#define CK_TOP_NET1_D8_D2	   16
+#define CK_TOP_NET1_D8_D4	   17
+#define CK_TOP_NET1_D8_D8	   18
+#define CK_TOP_NET1_D8_D16	   19
+#define CK_TOP_CB_NET2_800M	   20
+#define CK_TOP_CB_NET2_D2	   21
+#define CK_TOP_CB_NET2_D4	   22
+#define CK_TOP_NET2_D4_D4	   23
+#define CK_TOP_NET2_D4_D8	   24
+#define CK_TOP_CB_NET2_D6	   25
+#define CK_TOP_NET2_D7_D2	   26
+#define CK_TOP_CB_NET2_D8	   27
+#define CK_TOP_CB_WEDMCU_208M	   28
+#define CK_TOP_CB_SGM_325M	   29
+#define CK_TOP_CB_MSDC_416M	   30
+#define CK_TOP_MSDC_D2		   31
+#define CK_TOP_CB_CKSQ_40M	   32
+#define CK_TOP_CKSQ_40M_D2	   33
+#define CK_TOP_CB_RTC_32K	   34
+#define CK_TOP_CB_RTC_32P7K	   35
+#define CK_TOP_NETSYS_500m		36
+#define CK_TOP_NETSYS_2X		37
+#define CK_TOP_EMMC_250M		38
+#define CK_TOP_EMMC_400M		39
+#define CK_TOP_NFI_BCK			40
+#define CK_TOP_I2C_BCK			41
+#define CK_TOP_USB_SYS_P1		42
+#define CK_TOP_USB_XHCI_P1		43
+#define CK_TOP_AUD			44
+#define CK_TOP_A1SYS			45
+#define CK_TOP_AUD_L			46
+#define CK_TOP_A_TUNER			47
+#define CK_TOP_SYSAXI			48
+#define CK_TOP_INFRA_F26M		49
+#define CK_TOP_EMMC_200M		50
+#define CK_TOP_USB_FRMCNT_P1		51
+#define CK_TOP_USB_CK_P1		52
+#define CK_TOP_NETSYS_SEL		53
+#define CK_TOP_NETSYS_500M_SEL		54
+#define CK_TOP_NETSYS_2X_SEL		55
+#define CK_TOP_ETH_GMII_SEL		56
+#define CK_TOP_EIP_SEL			57
+#define CK_TOP_AXI_INFRA_SEL		58
+#define CK_TOP_UART_SEL			59
+#define CK_TOP_EMMC_250M_SEL		60
+#define CK_TOP_EMMC_400M_SEL		61
+#define CK_TOP_SPI_SEL			62
+#define CK_TOP_SPIM_MST_SEL		63
+#define CK_TOP_NFI_SEL			64
+#define CK_TOP_PWM_SEL			65
+#define CK_TOP_I2C_SEL			66
+#define CK_TOP_PCIE_MBIST_250M_SEL	67
+#define CK_TOP_PEXTP_TL_SEL		68
+#define CK_TOP_PEXTP_TL_P1_SEL		69
+#define CK_TOP_USB_SYS_P1_SEL		70
+#define CK_TOP_USB_XHCI_P1_SEL		71
+#define CK_TOP_AUD_SEL			72
+#define CK_TOP_A1SYS_SEL		73
+#define CK_TOP_AUD_L_SEL		74
+#define CK_TOP_A_TUNER_SEL		75
+#define CK_TOP_USB_PHY_SEL		76
+#define CK_TOP_SGM_0_SEL		77
+#define CK_TOP_SGM_SBUS_0_SEL		78
+#define CK_TOP_SGM_1_SEL		79
+#define CK_TOP_SGM_SBUS_1_SEL		80
+#define CK_TOP_SYSAXI_SEL		81
+#define CK_TOP_SYSAPB_SEL		82
+#define CK_TOP_ETH_REFCK_50M_SEL	83
+#define CK_TOP_ETH_SYS_200M_SEL		84
+#define CK_TOP_ETH_SYS_SEL		85
+#define CK_TOP_ETH_XGMII_SEL		86
+#define CK_TOP_DRAMC_SEL		87
+#define CK_TOP_DRAMC_MD32_SEL		88
+#define CK_TOP_INFRA_F26M_SEL		89
+#define CK_TOP_PEXTP_P0_SEL		90
+#define CK_TOP_PEXTP_P1_SEL		91
+#define CK_TOP_DA_XTP_GLB_P0_SEL	92
+#define CK_TOP_DA_XTP_GLB_P1_SEL	93
+#define CK_TOP_CKM_SEL			94
+#define CK_TOP_DA_CKM_XTAL_SEL		95
+#define CK_TOP_PEXTP_SEL		96
+#define CK_TOP_ETH_MII_SEL		97
+#define CK_TOP_EMMC_200M_SEL		98
+#define CK_TOP_AUD_I2S_M		99
+#define CLK_TOP_NR_CLK			100
+
+/* APMIXEDSYS */
+
+#define CK_APMIXED_MPLL	     0
+#define CK_APMIXED_APLL2     1
+#define CK_APMIXED_NET1PLL   2
+#define CK_APMIXED_NET2PLL   3
+#define CK_APMIXED_WEDMCUPLL 4
+#define CK_APMIXED_SGMPLL    5
+#define CK_APMIXED_ARM_LL    6
+#define CK_APMIXED_MSDCPLL   7
+#define CLK_APMIXED_NR_CLK   8
+
+/* SGMIISYS_0 */
+
+#define CK_SGM0_TX_EN	  0
+#define CK_SGM0_RX_EN	  1
+#define CLK_SGMII0_NR_CLK 2
+
+/* SGMIISYS_1 */
+
+#define CK_SGM1_TX_EN	  0
+#define CK_SGM1_RX_EN	  1
+#define CLK_SGMII1_NR_CLK 2
+
+/* ETHDMA */
+
+#define CK_ETHDMA_FE_EN			0
+#define CK_ETHDMA_GP2_EN		1
+#define CK_ETHDMA_GP1_EN		2
+#define CK_ETHDMA_GP3_EN		3
+#define CLK_ETHDMA_NR_CLK		4
+
+#endif /* _DT_BINDINGS_CLK_MT7987_H */
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7987.cfg b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7987.cfg
new file mode 100644
index 0000000..24850c5
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7987.cfg
@@ -0,0 +1,545 @@
+CONFIG_64BIT=y
+CONFIG_AHCI_MTK=y
+CONFIG_AIROHA_AN8801_PHY=y
+# CONFIG_AIROHA_EN8801SC_PHY is not set
+CONFIG_AIROHA_EN8811H_PHY=m
+CONFIG_AIROHA_EN8811H_PHY_DEBUGFS=y
+CONFIG_AN8855_GSW=y
+CONFIG_AQUANTIA_PHY=y
+# CONFIG_AQUANTIA_PHY_FW_DOWNLOAD is not set
+CONFIG_AQUANTIA_PHY_FW_FILE="AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld"
+CONFIG_AQUANTIA_PHY_FW_FILE_AQR113C="Rhe-05.06-Candidate7-AQR_Mediatek_23B_StartOff_ID45623_VER36657.cld"
+CONFIG_AQUANTIA_PHY_FW_FILE_CUX3410="AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2148.cld"
+# CONFIG_AQUANTIA_PHY_MIB is not set
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_CONT_SHIFT=4
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1418040=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_SSBD=y
+CONFIG_ARM64_SVE=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_UAO=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM64_VHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+# CONFIG_ARMV8_DEPRECATED is not set
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_MEDIATEK_CPUFREQ=y
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ASN1 is not set
+CONFIG_ATA=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_BLK_DEV_DM_BUILTIN=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLK_SCSI_REQUEST=y
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BT=y
+CONFIG_BT_BCM=y
+CONFIG_BT_BREDR=y
+CONFIG_BT_DEBUGFS=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_BCM=y
+# CONFIG_BT_HCIUART_INTEL is not set
+# CONFIG_BT_HCIUART_NOKIA is not set
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_BT_HCIUART_SERDEV=y
+CONFIG_BT_HCIVHCI=y
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_MTKUART=y
+CONFIG_BT_QCA=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MEDIATEK=y
+CONFIG_COMMON_CLK_MT2712=y
+# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
+# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
+# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
+# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
+# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
+# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
+# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
+# CONFIG_COMMON_CLK_MT6779 is not set
+# CONFIG_COMMON_CLK_MT6797 is not set
+CONFIG_COMMON_CLK_MT7622=y
+CONFIG_COMMON_CLK_MT7622_AUDSYS=y
+CONFIG_COMMON_CLK_MT7622_ETHSYS=y
+CONFIG_COMMON_CLK_MT7622_HIFSYS=y
+CONFIG_COMMON_CLK_MT7981=y
+CONFIG_COMMON_CLK_MT7986=y
+CONFIG_COMMON_CLK_MT7987=y
+CONFIG_COMMON_CLK_MT7988=y
+# CONFIG_COMMON_CLK_MT8173 is not set
+# CONFIG_COMMON_CLK_MT8183 is not set
+# CONFIG_COMMON_CLK_MT8516 is not set
+CONFIG_COMPAT=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+# CONFIG_CRYPTO_CAVP_TEST is not set
+CONFIG_CRYPTO_CMAC=y
+# CONFIG_CRYPTO_CPU_JITTERENTROPY_DEBUG is not set
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_MISC=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DM_BUFIO=y
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
+CONFIG_DM_INIT=y
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_SNAPSHOT is not set
+CONFIG_DM_VERITY=y
+# CONFIG_DM_VERITY_FEC is not set
+# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
+CONFIG_DPS310=y
+CONFIG_DRM_RCAR_WRITEBACK=y
+CONFIG_DTC=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EINT_MTK=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPY211_PHY=y
+CONFIG_GRO_CELLS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HOLES_IN_ZONE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+# CONFIG_HW_NAT is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_HZ=250
+CONFIG_HZ_250=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MT65XX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_LEDS_CLASS_MULTICOLOR is not set
+# CONFIG_LEDS_UBNT_LEDBAR is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MARVELL_10G_PHY=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MAXLINEAR_GPHY=y
+CONFIG_MD=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_I2C=y
+CONFIG_MEDIATEK_2P5GE_PHY=y
+CONFIG_MEDIATEK_GE_PHY=y
+CONFIG_MEDIATEK_GE_SOC_PHY=y
+CONFIG_MEDIATEK_MT6577_AUXADC=y
+# CONFIG_MEDIATEK_NETSYS_V2 is not set
+CONFIG_MEDIATEK_NETSYS_V3=y
+CONFIG_MEDIATEK_WATCHDOG=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_MTK=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MT753X_GSW=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_MTK=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+# CONFIG_MTK_CMDQ is not set
+# CONFIG_MTK_CQDMA is not set
+CONFIG_MTK_EFUSE=y
+CONFIG_MTK_HSDMA=y
+CONFIG_MTK_ICE_DEBUG=y
+CONFIG_MTK_INFRACFG=y
+CONFIG_MTK_NET_PHYLIB=y
+CONFIG_MTK_PMIC_WRAP=y
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_SOC_THERMAL_LVTS=y
+CONFIG_MTK_SPI_NAND=y
+# CONFIG_MTK_THERMAL is not set
+CONFIG_MTK_TIMER=y
+# CONFIG_MTK_UART_APDMA is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_AN8855=y
+CONFIG_NET_DSA_MT7530=y
+# CONFIG_NET_DSA_MXL862 is not set
+CONFIG_NET_DSA_TAG_AIROHA=y
+CONFIG_NET_DSA_TAG_MTK=y
+# CONFIG_NET_DSA_TAG_MXL862 is not set
+# CONFIG_NET_DSA_TAG_MXL862_8021Q is not set
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NLS=y
+CONFIG_NMBM=y
+# CONFIG_NMBM_LOG_LEVEL_DEBUG is not set
+# CONFIG_NMBM_LOG_LEVEL_EMERG is not set
+# CONFIG_NMBM_LOG_LEVEL_ERR is not set
+CONFIG_NMBM_LOG_LEVEL_INFO=y
+# CONFIG_NMBM_LOG_LEVEL_NONE is not set
+# CONFIG_NMBM_LOG_LEVEL_WARN is not set
+CONFIG_NMBM_MTD=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PADATA=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+# CONFIG_PCIEASPM_DEFAULT is not set
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+CONFIG_PCIEASPM_POWER_SUPERSAVE=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIE_MEDIATEK is not set
+CONFIG_PCIE_MEDIATEK_GEN3=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_EVENTS=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_MTK_TPHY=y
+# CONFIG_PHY_MTK_UFS is not set
+CONFIG_PHY_MTK_XSPHY=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_MT2712 is not set
+# CONFIG_PINCTRL_MT6765 is not set
+# CONFIG_PINCTRL_MT6797 is not set
+# CONFIG_PINCTRL_MT7622 is not set
+# CONFIG_PINCTRL_MT7981 is not set
+CONFIG_PINCTRL_MT7986=y
+CONFIG_PINCTRL_MT7987=y
+CONFIG_PINCTRL_MT7988=y
+# CONFIG_PINCTRL_MT8173 is not set
+# CONFIG_PINCTRL_MT8183 is not set
+CONFIG_PINCTRL_MT8516=y
+CONFIG_PINCTRL_MTK=y
+CONFIG_PINCTRL_MTK_MOORE=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PSTORE=y
+# CONFIG_PSTORE_842_COMPRESS is not set
+CONFIG_PSTORE_CONSOLE=y
+# CONFIG_PSTORE_DEFLATE_COMPRESS is not set
+# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
+# CONFIG_PSTORE_LZ4_COMPRESS is not set
+# CONFIG_PSTORE_LZO_COMPRESS is not set
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+# CONFIG_PSTORE_ZSTD_COMPRESS is not set
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PWM=y
+# CONFIG_PWM_GPIO is not set
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_MT6380=y
+CONFIG_REGULATOR_RT5190A=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RICHTEK_RTQ6056=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MT7622=y
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RTL8367S_GSW is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
+# CONFIG_SENSORS_DRIVETEMP is not set
+CONFIG_SENSORS_PWM_FAN=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SFP=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT65XX=y
+# CONFIG_SPI_MTK_NOR is not set
+CONFIG_SPI_MTK_SNFI=y
+CONFIG_SRCU=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+# CONFIG_TEST_DHRY is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UCLAMP_TASK is not set
+# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_NET_AX88179_178A=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_RTL8152=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UAS=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_XHCI_MTK_DEBUGFS=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_VMAP_STACK=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_XPS=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZTS8032=y
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/999-2014-clk-mtk-add-mt7987-support.patch.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/999-2014-clk-mtk-add-mt7987-support.patch.patch
new file mode 100644
index 0000000..5591e1e
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/999-2014-clk-mtk-add-mt7987-support.patch.patch
@@ -0,0 +1,31 @@
+diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
+index cf3a53e..be40a84 100644
+--- a/drivers/clk/mediatek/Kconfig
++++ b/drivers/clk/mediatek/Kconfig
+@@ -275,6 +275,14 @@ config COMMON_CLK_MT7981
+ 	  This driver supports MediaTek MT7981 basic clocks and clocks
+ 	  required for various periperals found on MediaTek.
+ 
++config COMMON_CLK_MT7987
++	bool "Clock driver for MediaTek MT7987"
++	depends on ARCH_MEDIATEK || COMPILE_TEST
++	select COMMON_CLK_MEDIATEK
++	---help---
++	  This driver supports MediaTek MT7987 basic clocks and clocks
++	  required for various periperals found on MediaTek.
++
+ config COMMON_CLK_MT7988
+ 	bool "Clock driver for MediaTek MT7988"
+ 	depends on ARCH_MEDIATEK || COMPILE_TEST
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 43ca85d..bd452d6 100644
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -41,6 +41,7 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
+ obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986.o
+ obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981.o
++obj-$(CONFIG_COMMON_CLK_MT7987) += clk-mt7987.o
+ obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988.o
+ obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+ obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/999-2024-pinctrl-add-mt7987-driver.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/999-2024-pinctrl-add-mt7987-driver.patch
new file mode 100644
index 0000000..7b98588
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/999-2024-pinctrl-add-mt7987-driver.patch
@@ -0,0 +1,26 @@
+--- a/drivers/pinctrl/mediatek/Kconfig
++++ b/drivers/pinctrl/mediatek/Kconfig
+@@ -112,6 +112,13 @@ config PINCTRL_MT7986
+ 	default ARM64 && ARCH_MEDIATEK
+ 	select PINCTRL_MTK_MOORE
+ 
++config PINCTRL_MT7987
++        bool "Mediatek MT7987 pin control"
++        depends on OF
++        depends on ARM64 || COMPILE_TEST
++        default ARM64 && ARCH_MEDIATEK
++        select PINCTRL_MTK_MOORE
++
+ config PINCTRL_MT7988
+         bool "Mediatek MT7988 pin control"
+         depends on OF
+--- a/drivers/pinctrl/mediatek/Makefile
++++ b/drivers/pinctrl/mediatek/Makefile
+@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-
+ obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
+ obj-$(CONFIG_PINCTRL_MT7981)	+= pinctrl-mt7981.o
+ obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
++obj-$(CONFIG_PINCTRL_MT7987)    += pinctrl-mt7987.o
+ obj-$(CONFIG_PINCTRL_MT7988)    += pinctrl-mt7988.o
+ obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
+ obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc
index 31ffdf1..47dfb49 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc
@@ -107,10 +107,12 @@
     file://999-2011-clk-mtk-add-mt7981-support.patch \
     file://999-2012-clk-mtk-add-mt7988-support.patch \
     file://999-2013-clk-mtk-add-chg-shift-control.patch \
+    file://999-2014-clk-mtk-add-mt7987-support.patch.patch \
     file://999-2020-pinctrl-add-mt7986-driver.patch \
     file://999-2021-pinctrl-enable-mt7988-pinctrl-config.patch \
     file://999-2022-pinctrl-add-mt7981-driver.patch \
     file://999-2023-pinctrl-add-mt7988-pd-pulltype-support.patch \
+    file://999-2024-pinctrl-add-mt7987-driver.patch \
     file://999-2040-powerdomain-add-mt7988-support.patch \
     file://999-2050-watchdog-add-mt7986-assert.patch \
     file://999-2100-mt7986-trng-add-rng-support.patch \
diff --git a/recipes-kernel/linux/linux-mediatek_5.4.bb b/recipes-kernel/linux/linux-mediatek_5.4.bb
index ef926bc..e558eb8 100644
--- a/recipes-kernel/linux/linux-mediatek_5.4.bb
+++ b/recipes-kernel/linux/linux-mediatek_5.4.bb
@@ -33,6 +33,9 @@
 SRC_URI_append_mt7986 += " \
     file://mediatek/mt7986.cfg \
 "
+SRC_URI_append_mt7987 += " \
+    file://mediatek/mt7987.cfg \
+"
 SRC_URI_append_mt7986-32bit += " \
     file://mediatek/patches-32bit-5.4/mt7986-32bit.cfg \
     file://mediatek/patches-32bit-5.4/401-pinctrl-add-mt7986-driver-32bit.patch \
@@ -133,3 +136,4 @@
 addtask filogic_patches after do_patch before do_compile
 
 KERNEL_MODULE_AUTOLOAD += "${@bb.utils.contains('DISTRO_FEATURES','logan','mtkhnat nf_flow_table_hw','',d)}"
+KERNEL_MODULE_AUTOLOAD_mt7987 += "air_en8811h "
\ No newline at end of file