// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "mt7988.dtsi"

/ {
	model = "MediaTek MT7988 GSW 10G SPIM-NAND 4PCIe RFB";
	compatible = "mediatek,mt7988a-gsw-10g-spim-snand-4pcie",
		     /* Reserve this for DVFS if creating new dts */
		     "mediatek,mt7988";

	chosen {
		bootargs = "console=ttyS0,115200n1 loglevel=8  \
			    earlycon=uart8250,mmio32,0x11000000 \
			    pci=pcie_bus_perf";
	};

	gsw: gsw@0 {
		compatible = "mediatek,mt753x";
		mediatek,sysctrl = <&ethwarp>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	memory {
		reg = <0 0x40000000 0 0x10000000>;
	};

	nmbm_spim_nand {
		compatible = "generic,nmbm";

		#address-cells = <1>;
		#size-cells = <1>;

		lower-mtd-device = <&spi_nand>;
		forced-create;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "BL2";
				reg = <0x00000 0x0100000>;
				read-only;
			};

			partition@100000 {
				label = "u-boot-env";
				reg = <0x0100000 0x0080000>;
			};

			factory: partition@180000 {
				label = "Factory";
				reg = <0x180000 0x0400000>;
			};

			partition@580000 {
				label = "FIP";
				reg = <0x580000 0x0200000>;
			};

			partition@780000 {
				label = "ubi";
				reg = <0x780000 0x7080000>;
			};
		};
	};

	wsys_adie: wsys_adie@0 {
	// fpga cases need to manual change adie_id / sku_type for dvt only
		compatible = "mediatek,rebb-mt7988-adie";
		adie_id = <7976>;
		sku_type = <3000>;
	};
};

&fan {
	pwms = <&pwm 0 50000>;
	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";

	rt5190a_64: rt5190a@64 {
		compatible = "richtek,rt5190a";
		reg = <0x64>;
		/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
		vin2-supply = <&rt5190_buck1>;
		vin3-supply = <&rt5190_buck1>;
		vin4-supply = <&rt5190_buck1>;

		regulators {
			rt5190_buck1: buck1 {
				regulator-name = "rt5190a-buck1";
				regulator-min-microvolt = <5090000>;
				regulator-max-microvolt = <5090000>;
				regulator-allowed-modes =
				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
				regulator-boot-on;
			};
			buck2 {
				regulator-name = "vcore";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
			};
			buck3 {
				regulator-name = "proc";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
			};
			buck4 {
				regulator-name = "rt5190a-buck4";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <850000>;
				regulator-allowed-modes =
				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
				regulator-boot-on;
			};
			ldo {
				regulator-name = "rt5190a-ldo";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-boot-on;
			};
		};
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";
};

&pwm {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_flash_pins>;
	status = "okay";

	spi_nand: spi_nand@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-nand";
		spi-cal-enable;
		spi-cal-mode = "read-data";
		spi-cal-datalen = <7>;
		spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
		spi-cal-addrlen = <5>;
		spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
		reg = <0>;
		spi-max-frequency = <52000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&spi1 {
	pinctrl-names = "default";
	/* pin shared with snfi */
	pinctrl-0 = <&spic_pins>;
	status = "disabled";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>;
	status = "okay";
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie1_pins>;
	wifi-reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
	wifi-reset-msleep = <100>;
	status = "okay";
};

&pcie2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie2_pins>;
	status = "okay";
};

&pcie3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie3_pins>;
	status = "okay";
};

&pio {
	mdio0_pins: mdio0-pins {
		mux {
			function = "mdio";
			groups = "mdc_mdio0";
		};

		conf {
			groups = "mdc_mdio0";
			drive-strength = <MTK_DRIVE_10mA>;
		};
	};

	gbe0_led0_pins: gbe0-pins {
		mux {
			function = "led";
			groups = "gbe0_led0";
		};
	};

	gbe1_led0_pins: gbe1-pins {
		mux {
			function = "led";
			groups = "gbe1_led0";
		};
	};

	gbe2_led0_pins: gbe2-pins {
		mux {
			function = "led";
			groups = "gbe2_led0";
		};
	};

	gbe3_led0_pins: gbe3-pins {
		mux {
			function = "led";
			groups = "gbe3_led0";
		};
	};

	i2c0_pins: i2c0-pins-g0 {
		mux {
			function = "i2c";
			groups = "i2c0_1";
		};
	};

	i2c1_pins: i2c1-pins-g0 {
		mux {
			function = "i2c";
			groups = "i2c1_0";
		};
	};

	pcie0_pins: pcie0-pins {
		mux {
			function = "pcie";
			groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0";
		};
	};

	pcie1_pins: pcie1-pins {
		mux {
			function = "pcie";
			groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
				 "pcie_wake_n1_0";
		};
	};

	pcie2_pins: pcie2-pins {
		mux {
			function = "pcie";
			groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
				 "pcie_wake_n2_0";
		};
	};

	pcie3_pins: pcie3-pins {
		mux {
			function = "pcie";
			groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
				 "pcie_wake_n3_0";
		};
	};

	spi0_flash_pins: spi0-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};
	};

	spic_pins: spi1-pins {
		mux {
			function = "spi";
			groups = "spi1";
		};
	};
};

&watchdog {
	status = "disabled";
};

&xhci0 {
	status = "disabled";
};

&eth {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins>;
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		mac-type = "xgdm";
		phy-mode = "10gbase-kr";

		fixed-link {
			speed = <10000>;
			full-duplex;
			pause;
		};
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		mac-type = "xgdm";
		phy-mode = "usxgmii";
		phy-handle = <&phy0>;
	};

	gmac2: mac@2 {
		compatible = "mediatek,eth-mac";
		reg = <2>;
		mac-type = "xgdm";
		phy-mode = "usxgmii";
		phy-handle = <&phy1>;
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <10500000>;

		phy0: ethernet-phy@0 {
			reg = <0>;
			compatible = "ethernet-phy-ieee802.3-c45";
			reset-gpios = <&pio 72 1>;
			reset-assert-us = <100000>;
			reset-deassert-us = <221000>;
			mdi-reversal = /bits/ 16 <1>;
		};

		phy1: ethernet-phy@8 {
			reg = <8>;
			compatible = "ethernet-phy-ieee802.3-c45";
			reset-gpios = <&pio 71 1>;
			reset-assert-us = <100000>;
			reset-deassert-us = <221000>;
			mdi-reversal = /bits/ 16 <1>;
		};
	};
};

&hnat {
	mtketh-wan = "eth1";
	mtketh-lan = "eth0";
	mtketh-lan2 = "eth2";
	mtketh-max-gmac = <3>;
	mtketh-ppe-num = <3>;
	status = "okay";
};

&gsw {
	mediatek,mdio = <&mdio>;
	mediatek,portmap = "llllw";
	mediatek,mdio_master_pinmux = <1>;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	status = "okay";

	port6: port@6 {
		compatible = "mediatek,mt753x-port";
		mediatek,ssc-on;
		phy-mode = "10gbase-kr";
		reg = <6>;
		fixed-link {
			speed = <10000>;
			full-duplex;
		};
	};

	mdio1: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		gsw_phy0: ethernet-phy@0 {
			compatible = "ethernet-phy-id03a2.9481";
			reg = <0>;
			pinctrl-names = "gbe-led";
			pinctrl-0 = <&gbe0_led0_pins>;
			nvmem-cells = <&phy_calibration_p0>;
			nvmem-cell-names = "phy-cal-data";
		};

		gsw_phy1: ethernet-phy@1 {
			compatible = "ethernet-phy-id03a2.9481";
			reg = <1>;
			pinctrl-names = "gbe-led";
			pinctrl-0 = <&gbe1_led0_pins>;
			nvmem-cells = <&phy_calibration_p1>;
			nvmem-cell-names = "phy-cal-data";
		};

		gsw_phy2: ethernet-phy@2 {
			compatible = "ethernet-phy-id03a2.9481";
			reg = <2>;
			pinctrl-names = "gbe-led";
			pinctrl-0 = <&gbe2_led0_pins>;
			nvmem-cells = <&phy_calibration_p2>;
			nvmem-cell-names = "phy-cal-data";
		};

		gsw_phy3: ethernet-phy@3 {
			compatible = "ethernet-phy-id03a2.9481";
			reg = <3>;
			pinctrl-names = "gbe-led";
			pinctrl-0 = <&gbe3_led0_pins>;
			nvmem-cells = <&phy_calibration_p3>;
			nvmem-cell-names = "phy-cal-data";
		};
	};
};