[rdkb][common][bsp][Refactor and sync kernel from openwrt]
[Description]
cff021a [mt7981/mt7988][eth][phy: mediatek-ge: Fix conflict default settings]
ee7b1f5 [mt7988][clk][Fix usb3 phy reference clock]
f2135aa [mt7981/mt7988][eth][phy: mediatek-ge: Change and enable CONFIG_MEDIATEK_GE_PHY_SOC for 81/88 at default]
392e5be [7988][kernel][arm64][dts][Change nor dts to enable quad mode]
f85f221 [kernel][mt7981/mt7988][eth][phy: mediatek-ge: Fix code alignment]
c8006b9 [kernel][mt7981][emmc][Fix the code format]
c81e287 [kernel][mt7981][eth][phy: mediatek-ge: Remove TX-AMP redundant settings]
db2c53e [kernel][mt7981/mt7988][eth][phy: mediatek-ge: Fix TX-VCM calibration pre-setting]
cabec19 [kernel][mt7981/mt7988][eth][phy: mediatek-ge: Change and derive common part from mt7981 & mt7988's fine-tuning]
4eb8fd2 [kernel][mt7981/mt7988][eth][phy: mediatek-ge: Add mt7981's V7 & mt7988's V3 enhancement & EEE settings]
e46198d [kernel][mt7981/mt7988][eth][phy: mediatek-ge: Change and settle down calibration mode for each calibration item]
118b7ff [kernel][mt7988][eth][phy: mediatek-ge: Remove LED polarity settings]
6ff1172 [kernel][mt7981/mt7988][eth][phy: mediatek-ge: Add MTK EPHY ID macros]
b865e62 [kernel][mt7981/mt7988][eth][phy: mediatek-ge: Refactor and change to upstream style]
f2c7000 [kernel][mt7981/mt7988][eth][phy: mediatek-ge: Change patches' sequence and get ready for upstream]
e97770c [kernel][mt7988][eth][i2.5Gphy: Add 20230328 version firmware]
[Release-log]
Change-Id: I9213cbeb6a32b16030895f759a636218b46c526f
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/011-kbuild-export-SUBARCH.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/011-kbuild-export-SUBARCH.patch
index 60defa3..59f7a90 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/011-kbuild-export-SUBARCH.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/011-kbuild-export-SUBARCH.patch
@@ -10,7 +10,7 @@
--- a/Makefile
+++ b/Makefile
-@@ -493,7 +493,7 @@ KBUILD_LDFLAGS :=
+@@ -500,7 +500,7 @@ KBUILD_LDFLAGS :=
GCC_PLUGINS_CFLAGS :=
CLANG_FLAGS :=
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch
index 02b5b57..34686f8 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch
@@ -18,7 +18,7 @@
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -6326,15 +6326,10 @@ void netif_napi_del(struct napi_struct *
+@@ -6328,15 +6328,10 @@ void netif_napi_del(struct napi_struct *
}
EXPORT_SYMBOL(netif_napi_del);
@@ -35,7 +35,7 @@
weight = n->weight;
/* This NAPI_STATE_SCHED test is for avoiding a race
-@@ -6352,7 +6347,7 @@ static int napi_poll(struct napi_struct
+@@ -6354,7 +6349,7 @@ static int napi_poll(struct napi_struct
WARN_ON_ONCE(work > weight);
if (likely(work < weight))
@@ -44,7 +44,7 @@
/* Drivers must not modify the NAPI state if they
* consume the entire weight. In such cases this code
-@@ -6361,7 +6356,7 @@ static int napi_poll(struct napi_struct
+@@ -6363,7 +6358,7 @@ static int napi_poll(struct napi_struct
*/
if (unlikely(napi_disable_pending(n))) {
napi_complete(n);
@@ -53,7 +53,7 @@
}
if (n->gro_bitmask) {
-@@ -6379,12 +6374,29 @@ static int napi_poll(struct napi_struct
+@@ -6381,12 +6376,29 @@ static int napi_poll(struct napi_struct
if (unlikely(!list_empty(&n->poll_list))) {
pr_warn_once("%s: Budget exhausted after napi rescheduled\n",
n->dev ? n->dev->name : "backlog");
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch
index 1ece7cf..c890240 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch
@@ -30,7 +30,7 @@
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -347,6 +347,7 @@ struct napi_struct {
+@@ -349,6 +349,7 @@ struct napi_struct {
struct list_head dev_list;
struct hlist_node napi_hash_node;
unsigned int napi_id;
@@ -38,7 +38,7 @@
};
enum {
-@@ -357,6 +358,7 @@ enum {
+@@ -359,6 +360,7 @@ enum {
NAPI_STATE_HASHED, /* In NAPI hash (busy polling possible) */
NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */
NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */
@@ -46,7 +46,7 @@
};
enum {
-@@ -367,6 +369,7 @@ enum {
+@@ -369,6 +371,7 @@ enum {
NAPIF_STATE_HASHED = BIT(NAPI_STATE_HASHED),
NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL),
NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL),
@@ -54,7 +54,7 @@
};
enum gro_result {
-@@ -511,20 +514,7 @@ bool napi_hash_del(struct napi_struct *n
+@@ -513,20 +516,7 @@ bool napi_hash_del(struct napi_struct *n
*/
void napi_disable(struct napi_struct *n);
@@ -76,7 +76,7 @@
/**
* napi_synchronize - wait until NAPI is not running
-@@ -1790,6 +1780,8 @@ enum netdev_ml_priv_type {
+@@ -1792,6 +1782,8 @@ enum netdev_ml_priv_type {
*
* @wol_enabled: Wake-on-LAN is enabled
*
@@ -85,7 +85,7 @@
* FIXME: cleanup struct net_device such that network protocol info
* moves out.
*/
-@@ -2082,6 +2074,7 @@ struct net_device {
+@@ -2084,6 +2076,7 @@ struct net_device {
struct lock_class_key addr_list_lock_key;
bool proto_down;
unsigned wol_enabled:1;
@@ -131,7 +131,7 @@
static int __dev_open(struct net_device *dev, struct netlink_ext_ack *extack)
{
const struct net_device_ops *ops = dev->netdev_ops;
-@@ -3889,6 +3911,21 @@ int gro_normal_batch __read_mostly = 8;
+@@ -3891,6 +3913,21 @@ int gro_normal_batch __read_mostly = 8;
static inline void ____napi_schedule(struct softnet_data *sd,
struct napi_struct *napi)
{
@@ -153,7 +153,7 @@
list_add_tail(&napi->poll_list, &sd->poll_list);
__raise_softirq_irqoff(NET_RX_SOFTIRQ);
}
-@@ -6280,6 +6317,12 @@ void netif_napi_add(struct net_device *d
+@@ -6282,6 +6319,12 @@ void netif_napi_add(struct net_device *d
set_bit(NAPI_STATE_NPSVC, &napi->state);
list_add_rcu(&napi->dev_list, &dev->napi_list);
napi_hash_add(napi);
@@ -166,7 +166,7 @@
}
EXPORT_SYMBOL(netif_napi_add);
-@@ -6296,9 +6339,28 @@ void napi_disable(struct napi_struct *n)
+@@ -6298,9 +6341,28 @@ void napi_disable(struct napi_struct *n)
hrtimer_cancel(&n->timer);
clear_bit(NAPI_STATE_DISABLE, &n->state);
@@ -195,7 +195,7 @@
static void flush_gro_hash(struct napi_struct *napi)
{
int i;
-@@ -6323,6 +6385,11 @@ void netif_napi_del(struct napi_struct *
+@@ -6325,6 +6387,11 @@ void netif_napi_del(struct napi_struct *
flush_gro_hash(napi);
napi->gro_bitmask = 0;
@@ -207,7 +207,7 @@
}
EXPORT_SYMBOL(netif_napi_del);
-@@ -6402,6 +6469,51 @@ static int napi_poll(struct napi_struct
+@@ -6404,6 +6471,51 @@ static int napi_poll(struct napi_struct
return work;
}
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch
index 93a8559..05c40a9 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch
@@ -46,7 +46,7 @@
+ == ==================================
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -505,6 +505,8 @@ static inline bool napi_complete(struct
+@@ -507,6 +507,8 @@ static inline bool napi_complete(struct
*/
bool napi_hash_del(struct napi_struct *napi);
@@ -57,7 +57,7 @@
* @n: NAPI context
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -3915,8 +3915,9 @@ static inline void ____napi_schedule(str
+@@ -3917,8 +3917,9 @@ static inline void ____napi_schedule(str
if (test_bit(NAPI_STATE_THREADED, &napi->state)) {
/* Paired with smp_mb__before_atomic() in
@@ -69,7 +69,7 @@
* wake_up_process() when it's not NULL.
*/
thread = READ_ONCE(napi->thread);
-@@ -6294,6 +6295,49 @@ static void init_gro_hash(struct napi_st
+@@ -6296,6 +6297,49 @@ static void init_gro_hash(struct napi_st
napi->gro_bitmask = 0;
}
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch
index 30a795d..103ed57 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch
@@ -27,7 +27,7 @@
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -359,6 +359,7 @@ enum {
+@@ -361,6 +361,7 @@ enum {
NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */
NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */
NAPI_STATE_THREADED, /* The poll is performed inside its own thread*/
@@ -35,7 +35,7 @@
};
enum {
-@@ -370,6 +371,7 @@ enum {
+@@ -372,6 +373,7 @@ enum {
NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL),
NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL),
NAPIF_STATE_THREADED = BIT(NAPI_STATE_THREADED),
@@ -45,7 +45,7 @@
enum gro_result {
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -3922,6 +3922,8 @@ static inline void ____napi_schedule(str
+@@ -3924,6 +3924,8 @@ static inline void ____napi_schedule(str
*/
thread = READ_ONCE(napi->thread);
if (thread) {
@@ -54,7 +54,7 @@
wake_up_process(thread);
return;
}
-@@ -6082,7 +6084,8 @@ bool napi_complete_done(struct napi_stru
+@@ -6084,7 +6086,8 @@ bool napi_complete_done(struct napi_stru
WARN_ON_ONCE(!(val & NAPIF_STATE_SCHED));
@@ -64,7 +64,7 @@
/* If STATE_MISSED was set, leave STATE_SCHED set,
* because we will call napi->poll() one more time.
-@@ -6515,16 +6518,25 @@ static int napi_poll(struct napi_struct
+@@ -6517,16 +6520,25 @@ static int napi_poll(struct napi_struct
static int napi_thread_wait(struct napi_struct *napi)
{
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch
index a60763d..a025973 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch
@@ -34,7 +34,7 @@
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -6522,7 +6522,7 @@ static int napi_thread_wait(struct napi_
+@@ -6524,7 +6524,7 @@ static int napi_thread_wait(struct napi_
set_current_state(TASK_INTERRUPTIBLE);
@@ -43,7 +43,7 @@
/* Testing SCHED_THREADED bit here to make sure the current
* kthread owns this napi and could poll on this napi.
* Testing SCHED bit is not enough because SCHED bit might be
-@@ -6540,6 +6540,7 @@ static int napi_thread_wait(struct napi_
+@@ -6542,6 +6542,7 @@ static int napi_thread_wait(struct napi_
set_current_state(TASK_INTERRUPTIBLE);
}
__set_current_state(TASK_RUNNING);
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch
index aeb22f5..b063efb 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/backport-5.4/700-v5.5-net-core-allow-fast-GRO-for-skbs-with-Ethernet-heade.patch
@@ -66,7 +66,7 @@
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -5476,8 +5476,7 @@ static inline void skb_gro_reset_offset(
+@@ -5478,8 +5478,7 @@ static inline void skb_gro_reset_offset(
NAPI_GRO_CB(skb)->frag0 = NULL;
NAPI_GRO_CB(skb)->frag0_len = 0;
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/defconfig b/recipes-kernel/linux/linux-mediatek-5.4/generic/defconfig
index ec37e51..be025d2 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/defconfig
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/defconfig
@@ -3470,7 +3470,6 @@
# CONFIG_NET_CLS_ROUTE4 is not set
# CONFIG_NET_CLS_RSVP is not set
# CONFIG_NET_CLS_RSVP6 is not set
-# CONFIG_NET_CLS_TCINDEX is not set
# CONFIG_NET_CLS_U32 is not set
CONFIG_NET_CORE=y
# CONFIG_NET_DEVLINK is not set
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/221-module_exports.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/221-module_exports.patch
index 446bf53..e8b775e 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/221-module_exports.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/221-module_exports.patch
@@ -56,9 +56,9 @@
} \
\
/* __*init sections */ \
-@@ -905,6 +915,8 @@
- EXIT_TEXT \
- EXIT_DATA \
+@@ -917,6 +927,8 @@
+ /DISCARD/ : { \
+ EXIT_DISCARDS \
EXIT_CALL \
+ SYMTAB_DISCARD \
+ SYMTAB_DISCARD_GPL \
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/721-phy_packets.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/721-phy_packets.patch
index 9dfeaa2..3df66bc 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/721-phy_packets.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/721-phy_packets.patch
@@ -15,7 +15,7 @@
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -1547,6 +1547,7 @@ enum netdev_priv_flags {
+@@ -1549,6 +1549,7 @@ enum netdev_priv_flags {
IFF_FAILOVER_SLAVE = 1<<28,
IFF_L3MDEV_RX_HANDLER = 1<<29,
IFF_LIVE_RENAME_OK = 1<<30,
@@ -23,7 +23,7 @@
};
#define IFF_802_1Q_VLAN IFF_802_1Q_VLAN
-@@ -1579,6 +1580,7 @@ enum netdev_priv_flags {
+@@ -1581,6 +1582,7 @@ enum netdev_priv_flags {
#define IFF_FAILOVER_SLAVE IFF_FAILOVER_SLAVE
#define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER
#define IFF_LIVE_RENAME_OK IFF_LIVE_RENAME_OK
@@ -31,7 +31,7 @@
/* Specifies the type of the struct net_device::ml_priv pointer */
enum netdev_ml_priv_type {
-@@ -1889,6 +1891,11 @@ struct net_device {
+@@ -1891,6 +1893,11 @@ struct net_device {
const struct tlsdev_ops *tlsdev_ops;
#endif
@@ -43,7 +43,7 @@
const struct header_ops *header_ops;
unsigned int flags;
-@@ -1971,6 +1978,10 @@ struct net_device {
+@@ -1973,6 +1980,10 @@ struct net_device {
struct mpls_dev __rcu *mpls_ptr;
#endif
@@ -101,7 +101,7 @@
help
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -3221,10 +3221,20 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3223,10 +3223,20 @@ static int xmit_one(struct sk_buff *skb,
if (dev_nit_active(dev))
dev_queue_xmit_nit(skb, dev);
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/902-debloat_proc.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/902-debloat_proc.patch
index afde1e8..44423db 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/902-debloat_proc.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/hack-5.4/902-debloat_proc.patch
@@ -330,7 +330,7 @@
--- a/net/core/sock.c
+++ b/net/core/sock.c
-@@ -3641,6 +3641,8 @@ static __net_initdata struct pernet_oper
+@@ -3657,6 +3657,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void)
{
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
index c670010..b21daea 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
@@ -8,7 +8,7 @@
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
-@@ -1161,6 +1161,73 @@ static struct mtd_info * __init open_mtd
+@@ -1168,6 +1168,73 @@ static struct mtd_info * __init open_mtd
return mtd;
}
@@ -82,7 +82,7 @@
static int __init ubi_init(void)
{
int err, i, k;
-@@ -1244,6 +1311,12 @@ static int __init ubi_init(void)
+@@ -1251,6 +1318,12 @@ static int __init ubi_init(void)
}
}
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/613-netfilter_optional_tcp_window_check.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/613-netfilter_optional_tcp_window_check.patch
deleted file mode 100644
index f6a3a82..0000000
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/613-netfilter_optional_tcp_window_check.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Subject: netfilter: optional tcp window check
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- net/netfilter/nf_conntrack_proto_tcp.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/net/netfilter/nf_conntrack_proto_tcp.c
-+++ b/net/netfilter/nf_conntrack_proto_tcp.c
-@@ -31,6 +31,9 @@
- #include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
- #include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
-
-+/* Do not check the TCP window for incoming packets */
-+static int nf_ct_tcp_no_window_check __read_mostly = 1;
-+
- /* "Be conservative in what you do,
- be liberal in what you accept from others."
- If it's non-zero, we mark only out of window RST segments as INVALID. */
-@@ -476,6 +479,9 @@ static bool tcp_in_window(const struct n
- s32 receiver_offset;
- bool res, in_recv_win;
-
-+ if (nf_ct_tcp_no_window_check)
-+ return true;
-+
- /*
- * Get the required data from the packet.
- */
-@@ -1139,7 +1145,7 @@ int nf_conntrack_tcp_packet(struct nf_co
- IP_CT_TCP_FLAG_DATA_UNACKNOWLEDGED &&
- timeouts[new_state] > timeouts[TCP_CONNTRACK_UNACK])
- timeout = timeouts[TCP_CONNTRACK_UNACK];
-- else if (ct->proto.tcp.last_win == 0 &&
-+ else if (!nf_ct_tcp_no_window_check && ct->proto.tcp.last_win == 0 &&
- timeouts[new_state] > timeouts[TCP_CONNTRACK_RETRANS])
- timeout = timeouts[TCP_CONNTRACK_RETRANS];
- else
---- a/net/netfilter/nf_conntrack_standalone.c
-+++ b/net/netfilter/nf_conntrack_standalone.c
-@@ -25,6 +25,9 @@
- #include <net/netfilter/nf_conntrack_timestamp.h>
- #include <linux/rculist_nulls.h>
-
-+/* Do not check the TCP window for incoming packets */
-+static int nf_ct_tcp_no_window_check __read_mostly = 1;
-+
- static bool enable_hooks __read_mostly;
- MODULE_PARM_DESC(enable_hooks, "Always enable conntrack hooks");
- module_param(enable_hooks, bool, 0000);
-@@ -649,6 +652,7 @@ enum nf_ct_sysctl_index {
- NF_SYSCTL_CT_PROTO_TIMEOUT_GRE_STREAM,
- #endif
-
-+ NF_SYSCTL_CT_PROTO_TCP_NO_WINDOW_CHECK,
- __NF_SYSCTL_CT_LAST_SYSCTL,
- };
-
-@@ -969,6 +973,13 @@ static struct ctl_table nf_ct_sysctl_tab
- .proc_handler = proc_dointvec_jiffies,
- },
- #endif
-+ [NF_SYSCTL_CT_PROTO_TCP_NO_WINDOW_CHECK] = {
-+ .procname = "nf_conntrack_tcp_no_window_check",
-+ .data = &nf_ct_tcp_no_window_check,
-+ .maxlen = sizeof(unsigned int),
-+ .mode = 0644,
-+ .proc_handler = proc_dointvec,
-+ },
- {}
- };
-
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
index f46dc94..96aa2fd 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -185,7 +185,7 @@
cfg->fc_flags |= RTF_REJECT;
if (rtm->rtm_type == RTN_LOCAL)
-@@ -6091,6 +6122,8 @@ static int ip6_route_dev_notify(struct n
+@@ -6092,6 +6123,8 @@ static int ip6_route_dev_notify(struct n
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.ip6_prohibit_entry->dst.dev = dev;
net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@@ -194,7 +194,7 @@
net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
#endif
-@@ -6102,6 +6135,7 @@ static int ip6_route_dev_notify(struct n
+@@ -6103,6 +6136,7 @@ static int ip6_route_dev_notify(struct n
in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@@ -202,7 +202,7 @@
in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
#endif
}
-@@ -6294,6 +6328,8 @@ static int __net_init ip6_route_net_init
+@@ -6295,6 +6329,8 @@ static int __net_init ip6_route_net_init
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
net->ipv6.fib6_has_custom_rules = false;
@@ -211,7 +211,7 @@
net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
sizeof(*net->ipv6.ip6_prohibit_entry),
GFP_KERNEL);
-@@ -6304,11 +6340,21 @@ static int __net_init ip6_route_net_init
+@@ -6305,11 +6341,21 @@ static int __net_init ip6_route_net_init
ip6_template_metrics, true);
INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
@@ -234,7 +234,7 @@
net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
ip6_template_metrics, true);
-@@ -6332,6 +6378,8 @@ out:
+@@ -6333,6 +6379,8 @@ out:
return ret;
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
@@ -243,7 +243,7 @@
out_ip6_prohibit_entry:
kfree(net->ipv6.ip6_prohibit_entry);
out_ip6_null_entry:
-@@ -6351,6 +6399,7 @@ static void __net_exit ip6_route_net_exi
+@@ -6352,6 +6400,7 @@ static void __net_exit ip6_route_net_exi
kfree(net->ipv6.ip6_null_entry);
#ifdef CONFIG_IPV6_MULTIPLE_TABLES
kfree(net->ipv6.ip6_prohibit_entry);
@@ -251,7 +251,7 @@
kfree(net->ipv6.ip6_blk_hole_entry);
#endif
dst_entries_destroy(&net->ipv6.ip6_dst_ops);
-@@ -6434,6 +6483,9 @@ void __init ip6_route_init_special_entri
+@@ -6435,6 +6484,9 @@ void __init ip6_route_init_special_entri
init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
index 614ac76..bec6787 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
@@ -11,7 +11,7 @@
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -1934,6 +1934,8 @@ struct net_device {
+@@ -1936,6 +1936,8 @@ struct net_device {
struct netdev_hw_addr_list mc;
struct netdev_hw_addr_list dev_addrs;
@@ -32,7 +32,7 @@
__u16 tc_index; /* traffic control index */
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -5542,6 +5542,9 @@ static enum gro_result dev_gro_receive(s
+@@ -5544,6 +5544,9 @@ static enum gro_result dev_gro_receive(s
int same_flow;
int grow;
@@ -42,7 +42,7 @@
if (netif_elide_gro(skb->dev))
goto normal;
-@@ -7485,6 +7488,48 @@ static void __netdev_adjacent_dev_unlink
+@@ -7487,6 +7490,48 @@ static void __netdev_adjacent_dev_unlink
&upper_dev->adj_list.lower);
}
@@ -91,7 +91,7 @@
static int __netdev_upper_dev_link(struct net_device *dev,
struct net_device *upper_dev, bool master,
void *upper_priv, void *upper_info,
-@@ -7535,6 +7580,7 @@ static int __netdev_upper_dev_link(struc
+@@ -7537,6 +7582,7 @@ static int __netdev_upper_dev_link(struc
if (ret)
return ret;
@@ -99,7 +99,7 @@
ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
&changeupper_info.info);
ret = notifier_to_errno(ret);
-@@ -7628,6 +7674,7 @@ void netdev_upper_dev_unlink(struct net_
+@@ -7630,6 +7676,7 @@ void netdev_upper_dev_unlink(struct net_
__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
@@ -107,7 +107,7 @@
call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
&changeupper_info.info);
-@@ -8358,6 +8405,7 @@ int dev_set_mac_address(struct net_devic
+@@ -8360,6 +8407,7 @@ int dev_set_mac_address(struct net_devic
if (err)
return err;
dev->addr_assign_type = NET_ADDR_SET;
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/pending-5.4.inc b/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/pending-5.4.inc
index 3ac355f..2412fc7 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/pending-5.4.inc
+++ b/recipes-kernel/linux/linux-mediatek-5.4/generic/pending-5.4/pending-5.4.inc
@@ -73,7 +73,6 @@
file://610-netfilter_match_bypass_default_checks.patch \
file://611-netfilter_match_bypass_default_table.patch \
file://612-netfilter_match_reduce_memory_access.patch \
- file://613-netfilter_optional_tcp_window_check.patch \
file://620-net_sched-codel-do-not-defer-queue-length-update.patch \
file://630-packet_socket_type.patch \
file://655-increase_skb_pad.patch \
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-emmc-rfb.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-emmc-rfb.dts
index 3c801b3..f8a8566 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-emmc-rfb.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-emmc-rfb.dts
@@ -6,8 +6,7 @@
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11002000 \
- root=PARTLABEL=rootfs rootwait \
- rootfstype=squashfs,f2fs";
+ root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
};
memory {
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-fpga-emmc.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-fpga-emmc.dts
index d90a9bf..b5b094a 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-fpga-emmc.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-fpga-emmc.dts
@@ -6,8 +6,7 @@
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11002000 \
- root=PARTLABEL=rootfs rootwait \
- rootfstype=squashfs,f2fs";
+ root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
};
memory {
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-fpga-sd.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-fpga-sd.dts
index 4bf50ce..ea2c13c 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-fpga-sd.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-fpga-sd.dts
@@ -6,8 +6,7 @@
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11002000 \
- root=PARTLABEL=rootfs rootwait \
- rootfstype=squashfs,f2fs";
+ root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
};
memory {
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-sd-rfb.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-sd-rfb.dts
index 0c8620b..c181aba 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-sd-rfb.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-sd-rfb.dts
@@ -6,8 +6,7 @@
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11002000 \
- root=PARTLABEL=rootfs rootwait \
- rootfstype=squashfs,f2fs";
+ root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
};
memory {
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
index 3700f9e..cdc7c90 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
@@ -68,6 +68,8 @@
spi-cal-addr = /bits/ 32 <0x0>;
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
partition@00000 {
label = "BL2";
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts
index 3c06b94..7878c52 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts
@@ -68,6 +68,8 @@
spi-cal-addr = /bits/ 32 <0x0>;
reg = <0>;
spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
partition@00000 {
label = "BL2";
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c
index 93585ce..9520ab8 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/clk/mediatek/clk-mt7988.c
@@ -138,8 +138,9 @@
FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", "usb_xhci", 1, 1),
FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1", "usb_xhci_p1", 1,
1),
- FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", "clkxtal", 1, 1),
- FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", "clkxtal", 1, 1),
+ FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", "sspxtp_sel", 1, 1),
+ FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", "usb_phy_sel", 1,
+ 1),
FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", "clkxtal", 1, 1),
FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", "clkxtal", 1, 1),
FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
index 8b7fbf8..2140945 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
@@ -6,33 +6,38 @@
#include <linux/of_platform.h>
#include <linux/phy.h>
-#define ANALOG_INTERNAL_OPERATION_MAX_US (20)
-#define ZCAL_CTRL_MIN (0)
-#define ZCAL_CTRL_MAX (63)
-#define TXRESERVE_MIN (0)
-#define TXRESERVE_MAX (7)
-
+#define MTK_GPHY_ID_MT7530 0x03a29412
+#define MTK_GPHY_ID_MT7531 0x03a29441
+#ifdef CONFIG_MEDIATEK_GE_PHY_SOC
+#define MTK_GPHY_ID_MT7981 0x03a29461
+#define MTK_GPHY_ID_MT7988 0x03a29481
+#endif
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
#define MTK_PHY_PAGE_EXTENDED 0x0001
#define MTK_PHY_PAGE_EXTENDED_2 0x0002
#define MTK_PHY_PAGE_EXTENDED_3 0x0003
-
/* Registers on Page 3 */
#define MTK_PHY_LPI_REG_14 (0x14)
-#define MTK_PHY_LPI_WAKE_TIMER_1000 GENMASK(8, 0)
+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
#define MTK_PHY_LPI_REG_1c (0x1c)
-#define MTK_PHY_SMI_DET_ON_THRESH GENMASK(13, 8)
+#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
/*******************************/
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
-#define MTK_PHY_ANARG_RG (0x10)
-#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
-
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
+#define ANALOG_INTERNAL_OPERATION_MAX_US (20)
+#define ZCAL_CTRL_MIN (0)
+#define ZCAL_CTRL_MAX (63)
+#define TXRESERVE_MIN (0)
+#define TXRESERVE_MAX (7)
+
+#define MTK_PHY_ANARG_RG (0x10)
+#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
+
/* Registers on MDIO_MMD_VEND1 */
enum {
MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TO1 = 0,
@@ -50,80 +55,75 @@
MTK_PHY_TX_MLT3_END,
};
-#define MTK_PHY_TXVLD_DA_RG (0x12)
+#define MTK_PHY_TXVLD_DA_RG (0x12)
#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
-#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 (0x16)
+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 (0x16)
#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
-#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 (0x17)
+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 (0x17)
#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
-#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 (0x18)
+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 (0x18)
#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
-#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 (0x19)
+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 (0x19)
#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
-#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 (0x20)
+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 (0x20)
#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
-#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 (0x21)
+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 (0x21)
#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
-#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 (0x22)
+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 (0x22)
#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
+#define MTK_PHY_TANA_CAL_MODE (0xc1)
+#define MTK_PHY_TANA_CAL_MODE_SHIFT (8)
-#define MTK_PHY_RESERVE_RG_0 (0x27)
-#define MTK_PHY_RESERVE_RG_1 (0x28)
-
-#define MTK_PHY_RG_ANA_TEST_POWERUP_TX (0x3b)
-#define MTK_PHY_TANA_CAL_MODE (0xc1)
-#define MTK_PHY_TANA_CAL_MODE_SHIFT (8)
-
-#define MTK_PHY_RXADC_CTRL_RG7 (0xc6)
+#define MTK_PHY_RXADC_CTRL_RG7 (0xc6)
#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
-#define MTK_PHY_RXADC_CTRL_RG9 (0xc8)
-#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
-#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
-#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
-#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
+#define MTK_PHY_RXADC_CTRL_RG9 (0xc8)
+#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
+#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
+#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
+#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
-#define MTK_PHY_LDO_OUTPUT_V (0xd7)
+#define MTK_PHY_LDO_OUTPUT_V (0xd7)
-#define MTK_PHY_RG_ANA_CAL_RG0 (0xdb)
-#define MTK_PHY_RG_CAL_CKINV BIT(12)
-#define MTK_PHY_RG_ANA_CALEN BIT(8)
-#define MTK_PHY_RG_REXT_CALEN BIT(4)
-#define MTK_PHY_RG_ZCALEN_A BIT(0)
+#define MTK_PHY_RG_ANA_CAL_RG0 (0xdb)
+#define MTK_PHY_RG_CAL_CKINV BIT(12)
+#define MTK_PHY_RG_ANA_CALEN BIT(8)
+#define MTK_PHY_RG_REXT_CALEN BIT(4)
+#define MTK_PHY_RG_ZCALEN_A BIT(0)
-#define MTK_PHY_RG_ANA_CAL_RG1 (0xdc)
-#define MTK_PHY_RG_ZCALEN_B BIT(12)
-#define MTK_PHY_RG_ZCALEN_C BIT(8)
-#define MTK_PHY_RG_ZCALEN_D BIT(4)
-#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
+#define MTK_PHY_RG_ANA_CAL_RG1 (0xdc)
+#define MTK_PHY_RG_ZCALEN_B BIT(12)
+#define MTK_PHY_RG_ZCALEN_C BIT(8)
+#define MTK_PHY_RG_ZCALEN_D BIT(4)
+#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
-#define MTK_PHY_RG_ANA_CAL_RG2 (0xdd)
-#define MTK_PHY_RG_TXG_CALEN_A BIT(12)
-#define MTK_PHY_RG_TXG_CALEN_B BIT(8)
-#define MTK_PHY_RG_TXG_CALEN_C BIT(4)
-#define MTK_PHY_RG_TXG_CALEN_D BIT(0)
+#define MTK_PHY_RG_ANA_CAL_RG2 (0xdd)
+#define MTK_PHY_RG_TXG_CALEN_A BIT(12)
+#define MTK_PHY_RG_TXG_CALEN_B BIT(8)
+#define MTK_PHY_RG_TXG_CALEN_C BIT(4)
+#define MTK_PHY_RG_TXG_CALEN_D BIT(0)
-#define MTK_PHY_RG_ANA_CAL_RG5 (0xe0)
-#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
-#define MTK_PHY_RG_ZCAL_CTRL_MASK GENMASK(5, 0)
+#define MTK_PHY_RG_ANA_CAL_RG5 (0xe0)
+#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
+#define MTK_PHY_RG_ZCAL_CTRL_MASK GENMASK(5, 0)
-#define MTK_PHY_RG_TX_FILTER (0xfe)
+#define MTK_PHY_RG_TX_FILTER (0xfe)
#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 (0x120)
#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
@@ -135,87 +135,79 @@
#define MTK_PHY_RG_TESTMUX_ADC_CTRL (0x144)
#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
-#define MTK_PHY_RG_DEV1E_REG172 (0x172)
+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B (0x172)
#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
-#define MTK_PHY_RG_DEV1E_REG173 (0x173)
+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D (0x173)
#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
-#define MTK_PHY_RG_DEV1E_REG174 (0x174)
-#define MTK_PHY_RSEL_TX_A_MASK GENMASK(14, 8)
-#define MTK_PHY_RSEL_TX_B_MASK GENMASK(6, 0)
-
-#define MTK_PHY_RG_DEV1E_REG175 (0x175)
-#define MTK_PHY_RSEL_TX_C_MASK GENMASK(14, 8)
-#define MTK_PHY_RSEL_TX_D_MASK GENMASK(6, 0)
-
-#define MTK_PHY_RG_DEV1E_REG17A (0x17a)
-#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
+#define MTK_PHY_RG_AD_CAL_COMP (0x17a)
+#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
-#define MTK_PHY_RG_DEV1E_REG17B (0x17b)
-#define MTK_PHY_DA_CAL_CLK BIT(0)
+#define MTK_PHY_RG_AD_CAL_CLK (0x17b)
+#define MTK_PHY_DA_CAL_CLK BIT(0)
-#define MTK_PHY_RG_DEV1E_REG17C (0x17c)
-#define MTK_PHY_DA_CALIN_FLAG BIT(0)
+#define MTK_PHY_RG_AD_CALIN (0x17c)
+#define MTK_PHY_DA_CALIN_FLAG BIT(0)
-#define MTK_PHY_RG_DEV1E_REG17D (0x17d)
-#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
+#define MTK_PHY_RG_DASN_DAC_IN0_A (0x17d)
+#define MTK_PHY_FORCE_DASN_DAC_IN0_A BIT(15)
-#define MTK_PHY_RG_DEV1E_REG17E (0x17e)
-#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
+#define MTK_PHY_RG_DASN_DAC_IN0_B (0x17e)
+#define MTK_PHY_FORCE_DASN_DAC_IN0_B BIT(15)
-#define MTK_PHY_RG_DEV1E_REG17F (0x17f)
-#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
+#define MTK_PHY_RG_DASN_DAC_IN0_C (0x17f)
+#define MTK_PHY_FORCE_DASN_DAC_IN0_C BIT(15)
-#define MTK_PHY_RG_DEV1E_REG180 (0x180)
-#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
+#define MTK_PHY_RG_DASN_DAC_IN0_D (0x180)
+#define MTK_PHY_FORCE_DASN_DAC_IN0_D BIT(15)
-#define MTK_PHY_RG_DEV1E_REG181 (0x181)
-#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
+#define MTK_PHY_RG_DASN_DAC_IN1_A (0x181)
+#define MTK_PHY_FORCE_DASN_DAC_IN1_A BIT(15)
-#define MTK_PHY_RG_DEV1E_REG182 (0x182)
-#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
+#define MTK_PHY_RG_DASN_DAC_IN1_B (0x182)
+#define MTK_PHY_FORCE_DASN_DAC_IN1_B BIT(15)
-#define MTK_PHY_RG_DEV1E_REG183 (0x183)
-#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
+#define MTK_PHY_RG_DASN_DAC_IN1_C (0x183)
+#define MTK_PHY_FORCE_DASN_DAC_IN1_C BIT(15)
-#define MTK_PHY_RG_DEV1E_REG184 (0x180)
-#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
+#define MTK_PHY_RG_DASN_DAC_IN1_D (0x184)
+#define MTK_PHY_FORCE_DASN_DAC_IN1_D BIT(15)
#define MTK_PHY_RG_DEV1E_REG19b (0x19b)
#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
-#define MTK_PHY_RG_LP_IIR2_K1_L (0x22a)
-#define MTK_PHY_RG_LP_IIR2_K1_U (0x22b)
-#define MTK_PHY_RG_LP_IIR2_K2_L (0x22c)
-#define MTK_PHY_RG_LP_IIR2_K2_U (0x22d)
-#define MTK_PHY_RG_LP_IIR2_K3_L (0x22e)
-#define MTK_PHY_RG_LP_IIR2_K3_U (0x22f)
-#define MTK_PHY_RG_LP_IIR2_K4_L (0x230)
-#define MTK_PHY_RG_LP_IIR2_K4_U (0x231)
-#define MTK_PHY_RG_LP_IIR2_K5_L (0x232)
-#define MTK_PHY_RG_LP_IIR2_K5_U (0x233)
+#define MTK_PHY_RG_LP_IIR2_K1_L (0x22a)
+#define MTK_PHY_RG_LP_IIR2_K1_U (0x22b)
+#define MTK_PHY_RG_LP_IIR2_K2_L (0x22c)
+#define MTK_PHY_RG_LP_IIR2_K2_U (0x22d)
+#define MTK_PHY_RG_LP_IIR2_K3_L (0x22e)
+#define MTK_PHY_RG_LP_IIR2_K3_U (0x22f)
+#define MTK_PHY_RG_LP_IIR2_K4_L (0x230)
+#define MTK_PHY_RG_LP_IIR2_K4_U (0x231)
+#define MTK_PHY_RG_LP_IIR2_K5_L (0x232)
+#define MTK_PHY_RG_LP_IIR2_K5_U (0x233)
-#define MTK_PHY_RG_DEV1E_REG234 (0x234)
-#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
-#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
-#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
+#define MTK_PHY_RG_DEV1E_REG234 (0x234)
+#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
+#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
+#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
-#define MTK_PHY_RG_LPF_CNT_VAL (0x235)
+#define MTK_PHY_RG_LPF_CNT_VAL (0x235)
#define MTK_PHY_RG_DEV1E_REG238 (0x238)
#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
#define MTK_PHY_RG_DEV1E_REG239 (0x239)
-#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
-#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
+#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
+#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
-#define MTK_PHY_RG_DEV1E_REG27C (0x27c)
+#define MTK_PHY_RG_DEV1E_REG27C (0x27c)
#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
-#define MTK_PHY_RG_DEV1E_REG27D (0x27d)
+#define MTK_PHY_RG_DEV1E_REG27D (0x27d)
#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
#define MTK_PHY_RG_DEV1E_REG2C7 (0x2c7)
@@ -224,9 +216,9 @@
#define MTK_PHY_RG_DEV1E_REG2D1 (0x2d1)
#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
-#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
-#define MTK_PHY_LPI_TR_READY BIT(9)
-#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
+#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
+#define MTK_PHY_LPI_TR_READY BIT(9)
+#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
#define MTK_PHY_RG_DEV1E_REG323 (0x323)
#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
@@ -243,90 +235,76 @@
#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
-#define MTK_PHY_LDO_PUMP_EN_PAIRAB (0x502)
-#define MTK_PHY_LDO_PUMP_EN_PAIRCD (0x503)
-
-#define MTK_PHY_RG_DEV1E_REG53D (0x53d)
-#define MTK_PHY_DA_TX_R50_A_NORMAL_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_R50_A_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_RG_DEV1E_REG53E (0x53e)
-#define MTK_PHY_DA_TX_R50_B_NORMAL_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_R50_B_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_RG_DEV1E_REG53F (0x53f)
-#define MTK_PHY_DA_TX_R50_C_NORMAL_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_R50_C_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_RG_DEV1E_REG540 (0x540)
-#define MTK_PHY_DA_TX_R50_D_NORMAL_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_R50_D_TBT_MASK GENMASK(5, 0)
+#define MTK_PHY_LDO_PUMP_EN_PAIRAB (0x502)
+#define MTK_PHY_LDO_PUMP_EN_PAIRCD (0x503)
+#define MTK_PHY_DA_TX_R50_PAIR_A (0x53d)
+#define MTK_PHY_DA_TX_R50_PAIR_B (0x53e)
+#define MTK_PHY_DA_TX_R50_PAIR_C (0x53f)
+#define MTK_PHY_DA_TX_R50_PAIR_D (0x540)
/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL (0x24)
+#define MTK_PHY_LED0_ON_CTRL (0x24)
#define MTK_PHY_LED0_ON_MASK GENMASK(6, 0)
-#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
-#define MTK_PHY_LED0_ON_LINK100 BIT(1)
-#define MTK_PHY_LED0_ON_LINK10 BIT(2)
-#define MTK_PHY_LED0_ON_LINKDOWN BIT(3)
-#define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */
-#define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */
-#define MTK_PHY_LED0_FORCE_ON BIT(6)
-#define MTK_PHY_LED0_POLARITY BIT(14)
-#define MTK_PHY_LED0_ENABLE BIT(15)
+#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
+#define MTK_PHY_LED0_ON_LINK100 BIT(1)
+#define MTK_PHY_LED0_ON_LINK10 BIT(2)
+#define MTK_PHY_LED0_ON_LINKDOWN BIT(3)
+#define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */
+#define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */
+#define MTK_PHY_LED0_FORCE_ON BIT(6)
+#define MTK_PHY_LED0_POLARITY BIT(14)
+#define MTK_PHY_LED0_ENABLE BIT(15)
-#define MTK_PHY_LED0_BLINK_CTRL (0x25)
-#define MTK_PHY_LED0_1000TX BIT(0)
-#define MTK_PHY_LED0_1000RX BIT(1)
-#define MTK_PHY_LED0_100TX BIT(2)
-#define MTK_PHY_LED0_100RX BIT(3)
-#define MTK_PHY_LED0_10TX BIT(4)
-#define MTK_PHY_LED0_10RX BIT(5)
-#define MTK_PHY_LED0_COLLISION BIT(6)
-#define MTK_PHY_LED0_RX_CRC_ERR BIT(7)
-#define MTK_PHY_LED0_RX_IDLE_ERR BIT(8)
-#define MTK_PHY_LED0_FORCE_BLINK BIT(9)
+#define MTK_PHY_LED0_BLINK_CTRL (0x25)
+#define MTK_PHY_LED0_1000TX BIT(0)
+#define MTK_PHY_LED0_1000RX BIT(1)
+#define MTK_PHY_LED0_100TX BIT(2)
+#define MTK_PHY_LED0_100RX BIT(3)
+#define MTK_PHY_LED0_10TX BIT(4)
+#define MTK_PHY_LED0_10RX BIT(5)
+#define MTK_PHY_LED0_COLLISION BIT(6)
+#define MTK_PHY_LED0_RX_CRC_ERR BIT(7)
+#define MTK_PHY_LED0_RX_IDLE_ERR BIT(8)
+#define MTK_PHY_LED0_FORCE_BLINK BIT(9)
-#define MTK_PHY_ANA_TEST_BUS_CTRL_RG (0x100)
+#define MTK_PHY_ANA_TEST_BUS_CTRL_RG (0x100)
#define MTK_PHY_ANA_TEST_MODE_MASK GENMASK(15, 8)
-#define MTK_PHY_RG_DEV1F_REG110 (0x110)
-#define MTK_PHY_RG_TST_DMY2_MASK GENMASK(5, 0)
-#define MTK_PHY_RG_TANA_RESERVE_MASK GENMASK(13, 8)
+#define MTK_PHY_RG_DASN_TXT_DMY2 (0x110)
+#define MTK_PHY_TST_DMY2_MASK GENMASK(5, 0)
-#define MTK_PHY_RG_DEV1F_REG115 (0x115)
-#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
+#define MTK_PHY_RG_BG_RASEL (0x115)
+#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
-/*
- * These macro privides efuse parsing for internal phy.
- */
-#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
-#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
-#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
-#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
+/* These macro privides efuse parsing for internal phy. */
+#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
+#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
+#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
+#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
+#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
+#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
+#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
+#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
+#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
+#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_A_10M(x) (((x) >> 12) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_B_10M(x) (((x) >> 18) & GENMASK(5, 0))
+#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
+#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
+#define EFS_DA_TX_R50_A_10M(x) (((x) >> 12) & GENMASK(5, 0))
+#define EFS_DA_TX_R50_B_10M(x) (((x) >> 18) & GENMASK(5, 0))
-#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
-#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
+#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
+#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
-typedef enum {
+enum {
+ NO_PAIR,
PAIR_A,
PAIR_B,
PAIR_C,
PAIR_D,
-} phy_cal_pair_t;
+};
enum {
GPHY_PORT0,
@@ -335,6 +313,24 @@
GPHY_PORT3,
};
+enum calibration_mode {
+ EFUSE_K,
+ SW_K
+};
+
+enum CAL_ITEM {
+ REXT,
+ TX_OFFSET,
+ TX_AMP,
+ TX_R50,
+ TX_VCM
+};
+
+enum CAL_MODE {
+ EFUSE_M,
+ SW_M
+};
+
const u8 mt798x_zcal_to_r50[64] = {
7, 8, 9, 9, 10, 10, 11, 11,
12, 13, 13, 14, 14, 15, 16, 16,
@@ -348,103 +344,97 @@
const char pair[4] = {'A', 'B', 'C', 'D'};
-#define CAL_NO_PAIR(cal_item, cal_mode, ...) \
- cal_ret = cal_item##_cal_##cal_mode(phydev, ##__VA_ARGS__);
+static int mtk_gephy_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+}
-#define CAL_PAIR_A_TO_A(cal_item, cal_mode, ...) \
- for(i=PAIR_A; i<=PAIR_A; i++) { \
- cal_ret = cal_item##_cal_##cal_mode(phydev, ##__VA_ARGS__, i);\
- if(cal_ret) break; \
- }
+static int mtk_gephy_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
+}
-#define CAL_PAIR_A_TO_D(cal_item, cal_mode, ...) \
- for(i=PAIR_A; i<=PAIR_D; i++) { \
- cal_ret = cal_item##_cal_##cal_mode(phydev, ##__VA_ARGS__, i);\
- if(cal_ret) break; \
- }
+static void mtk_gephy_config_init(struct phy_device *phydev)
+{
+ /* Disable EEE */
+ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
-#define SW_CAL(cal_item, cal_mode_get, pair_mode) \
- if(ret || (!ret && strcmp("sw", cal_mode_get) == 0)) { \
- CAL_##pair_mode(cal_item, sw) \
- }
+ /* Enable HW auto downshift */
+ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
-#define SW_EFUSE_CAL(cal_item, cal_mode_get, pair_mode,...) \
- if ((efs_valid && ret) || \
- (efs_valid && !ret && strcmp("efuse", cal_mode_get) == 0)) { \
- CAL_##pair_mode(cal_item, efuse, ##__VA_ARGS__) \
- } else if ((!efs_valid && ret) || \
- (!ret && strcmp("sw", cal_mode_get) == 0)) { \
- CAL_##pair_mode(cal_item, sw) \
- }
+ /* Increase SlvDPSready time */
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ __phy_write(phydev, 0x10, 0xafae);
+ __phy_write(phydev, 0x12, 0x2f);
+ __phy_write(phydev, 0x10, 0x8fae);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-#define EFUSE_CAL(cal_item, cal_mode_get, pair_mode, ...) \
- if ((efs_valid && ret) || \
- (efs_valid && !ret && strcmp("efuse", cal_mode_get) == 0)) {\
- CAL_##pair_mode(cal_item, efuse, ##__VA_ARGS__) \
- }
+ /* Adjust 100_mse_threshold */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
-#define CAL_FLOW(cal_item, cal_mode, cal_mode_get, pair_mode,...) \
- ret = of_property_read_string(phydev->mdio.dev.of_node, \
- #cal_item, &cal_mode_get); \
- cal_mode##_CAL(cal_item, cal_mode_get, pair_mode, ##__VA_ARGS__)\
- else { \
- dev_info(&phydev->mdio.dev, "%s cal mode %s%s," \
- " use default value," \
- " efs-valid: %s", \
- #cal_item, \
- ret? "" : cal_mode_get, \
- ret? "not specified" : " not supported", \
- efs_valid? "yes" : "no"); \
- } \
- if(cal_ret) { \
- dev_err(&phydev->mdio.dev, "%s cal failed\n", #cal_item);\
- ret = -EIO; \
- goto out; \
- }
+ /* Disable mcc */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
+}
-static int mtk_gephy_read_page(struct phy_device *phydev)
+static int mt7530_phy_config_init(struct phy_device *phydev)
{
- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+ mtk_gephy_config_init(phydev);
+
+ /* Increase post_update_timer */
+ phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
+
+ return 0;
}
-static int mtk_gephy_write_page(struct phy_device *phydev, int page)
+static int mt7531_phy_config_init(struct phy_device *phydev)
{
- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
+ mtk_gephy_config_init(phydev);
+
+ /* PHY link down power saving enable */
+ phy_set_bits(phydev, 0x17, BIT(4));
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
+
+ /* Set TX Pair delay selection */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
+
+ return 0;
}
-/*
- * One calibration cycle consists of:
+#ifdef CONFIG_MEDIATEK_GE_PHY_SOC
+/* One calibration cycle consists of:
* 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
* until AD_CAL_COMP is ready to output calibration result.
* 2.Wait until DA_CAL_CLK is available.
* 3.Fetch AD_CAL_COMP_OUT.
*/
static int cal_cycle(struct phy_device *phydev, int devad,
- u32 regnum, u16 mask, u16 cal_val)
+ u32 regnum, u16 mask, u16 cal_val)
{
unsigned long timeout;
int reg_val;
int ret;
phy_modify_mmd(phydev, devad, regnum,
- mask, cal_val);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17C,
- MTK_PHY_DA_CALIN_FLAG);
+ mask, cal_val);
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
+ MTK_PHY_DA_CALIN_FLAG);
timeout = jiffies + usecs_to_jiffies(ANALOG_INTERNAL_OPERATION_MAX_US);
- do{
- reg_val = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17B);
- } while(time_before(jiffies, timeout) && !(reg_val & BIT(0)));
+ do {
+ reg_val = phy_read_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_AD_CAL_CLK);
+ } while (time_before(jiffies, timeout) && !(reg_val & BIT(0)));
- if(!(reg_val & BIT(0))) {
+ if (!(reg_val & BIT(0))) {
dev_err(&phydev->mdio.dev, "Calibration cycle timeout\n");
return -ETIMEDOUT;
}
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17C,
- MTK_PHY_DA_CALIN_FLAG);
- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17A) >>
- MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
+ MTK_PHY_DA_CALIN_FLAG);
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
+ MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
dev_dbg(&phydev->mdio.dev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
return ret;
@@ -453,9 +443,9 @@
static int rext_fill_result(struct phy_device *phydev, u16 *buf)
{
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG115,
- MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
+ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
+ MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
return 0;
}
@@ -471,85 +461,15 @@
return 0;
}
-static int rext_cal_sw(struct phy_device *phydev)
-{
- u8 rg_zcal_ctrl_def;
- u8 zcal_lower, zcal_upper, rg_zcal_ctrl;
- u8 lower_ret, upper_ret;
- u16 rext_cal_val[2];
- int ret;
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG,
- MTK_PHY_ANA_TEST_MODE_MASK, MTK_PHY_TANA_CAL_MODE << 8);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_TXVOS_CALEN);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN | MTK_PHY_RG_REXT_CALEN);
- phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG110,
- MTK_PHY_RG_TST_DMY2_MASK, 0x1);
-
- rg_zcal_ctrl_def = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5) &
- MTK_PHY_RG_ZCAL_CTRL_MASK;
- zcal_lower = ZCAL_CTRL_MIN;
- zcal_upper = ZCAL_CTRL_MAX;
-
- dev_dbg(&phydev->mdio.dev, "Start REXT SW cal.\n");
- while((zcal_upper-zcal_lower) > 1) {
- rg_zcal_ctrl = DIV_ROUND_CLOSEST(zcal_lower+zcal_upper, 2);
- ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl);
- if(ret == 1) {
- zcal_upper = rg_zcal_ctrl;
- upper_ret = ret;
- } else if(ret == 0) {
- zcal_lower = rg_zcal_ctrl;
- lower_ret = ret;
- } else
- goto restore;
- }
-
- if(zcal_lower == ZCAL_CTRL_MIN) {
- ret = lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_lower);
- } else if(zcal_upper == ZCAL_CTRL_MAX) {
- ret = upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_upper);
- }
- if (ret < 0)
- goto restore;
-
- ret = upper_ret-lower_ret;
- if (ret == 1) {
- rext_cal_val[0] = zcal_upper;
- rext_cal_val[1] = zcal_upper >> 3;
- rext_fill_result(phydev, rext_cal_val);
- dev_info(&phydev->mdio.dev, "REXT SW cal result: 0x%x\n", zcal_upper);
- ret = 0;
- } else
- ret = -EINVAL;
-
-restore:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG,
- MTK_PHY_ANA_TEST_MODE_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN | MTK_PHY_RG_REXT_CALEN);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG110,
- MTK_PHY_RG_TST_DMY2_MASK);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl_def);
-
- return ret;
-}
-
static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
{
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG172,
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG172,
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG173,
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG173,
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
return 0;
@@ -573,43 +493,51 @@
{
int i;
int bias[16] = {0};
- switch(phydev->drv->phy_id) {
- case 0x03a29461:
- {
- /* We add some calibration to efuse values
- * due to board level influence.
- * GBE: +7, TBT: +1, HBT: +4, TST: +7
- */
- int tmp[16] = { 7, 1, 4, 7,
- 7, 1, 4, 7,
- 7, 1, 4, 7,
- 7, 1, 4, 7 };
- memcpy(bias, (const void *)tmp, sizeof(bias));
- break;
- }
- case 0x03a29481:
- {
- int tmp[16] = { 10, 6, 6, 10,
- 10, 6, 6, 10,
- 10, 6, 6, 10,
- 10, 6, 6, 10 };
- memcpy(bias, (const void *)tmp, sizeof(bias));
- break;
+ const int vals_9461[16] = { 7, 1, 4, 7,
+ 7, 1, 4, 7,
+ 7, 1, 4, 7,
+ 7, 1, 4, 7 };
+ const int vals_9481[16] = { 10, 6, 6, 10,
+ 10, 6, 6, 10,
+ 10, 6, 6, 10,
+ 10, 6, 6, 10 };
+
+ switch (phydev->drv->phy_id) {
+ case MTK_GPHY_ID_MT7981:
+ /* We add some calibration to efuse values
+ * due to board level influence.
+ * GBE: +7, TBT: +1, HBT: +4, TST: +7
+ */
+ memcpy(bias, (const void *)vals_9461, sizeof(bias));
+ for (i = 0; i <= 12; i += 4) {
+ if (likely(buf[i >> 2] + bias[i] >= 32)) {
+ bias[i] -= 13;
+ } else {
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+ 0x5c, 0x7 << i, bias[i] << i);
+ bias[i + 1] += 13;
+ bias[i + 2] += 13;
+ bias[i + 3] += 13;
+ }
}
- default:
- break;
+ break;
+ case MTK_GPHY_ID_MT7988:
+ memcpy(bias, (const void *)vals_9481, sizeof(bias));
+ break;
+ default:
+ break;
}
/* Prevent overflow */
for (i = 0; i < 12; i++) {
- if (buf[i>>2] + bias[i] > 63) {
- buf[i>>2] = 63;
+ if (buf[i >> 2] + bias[i] > 63) {
+ buf[i >> 2] = 63;
bias[i] = 0;
- } else if (buf[i>>2] + bias[i] < 0) {
+ } else if (buf[i >> 2] + bias[i] < 0) {
/* Bias caused by board design may change in the future.
* So check negative cases, too.
*/
- buf[i>>2] = 0;
+ buf[i >> 2] = 0;
bias[i] = 0;
}
}
@@ -666,241 +594,177 @@
return 0;
}
-static int tx_r50_fill_result(struct phy_device *phydev, u16 *buf,
- phy_cal_pair_t txg_calen_x)
+static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
+ u8 txg_calen_x)
{
- int bias[4] = {0};
- int i;
- switch(phydev->drv->phy_id) {
- case 0x03a29481:
- {
- int tmp[16] = { -2, -2, -2, -2 };
- memcpy(bias, (const void *)tmp, sizeof(bias));
- break;
- }
- /* 0x03a29461 enters default case */
- default:
- break;
- }
+ int bias = 0;
+ u16 reg, val;
- for (i = 0; i < 4; i++) {
- if (buf[i>>2] + bias[i] > 63) {
- buf[i>>2] = 63;
- bias[i] = 0;
- } else if (buf[i>>2] + bias[i] < 0) {
- buf[i>>2] = 0;
- bias[i] = 0;
- }
+ switch (phydev->drv->phy_id) {
+ case MTK_GPHY_ID_MT7988:
+ {
+ bias = -2;
+ break;
}
- switch(txg_calen_x) {
- case PAIR_A:
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53D,
- MTK_PHY_DA_TX_R50_A_NORMAL_MASK, (buf[0] + bias[0]) << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53D,
- MTK_PHY_DA_TX_R50_A_TBT_MASK, (buf[0]) + bias[0]);
- break;
- case PAIR_B:
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53E,
- MTK_PHY_DA_TX_R50_B_NORMAL_MASK, (buf[0] + bias[1])<< 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53E,
- MTK_PHY_DA_TX_R50_B_TBT_MASK, (buf[0] + bias[1]));
- break;
- case PAIR_C:
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53F,
- MTK_PHY_DA_TX_R50_C_NORMAL_MASK, (buf[0] + bias[2])<< 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG53F,
- MTK_PHY_DA_TX_R50_C_TBT_MASK, (buf[0] + bias[2]));
- break;
- case PAIR_D:
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG540,
- MTK_PHY_DA_TX_R50_D_NORMAL_MASK, (buf[0] + bias[3])<< 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG540,
- MTK_PHY_DA_TX_R50_D_TBT_MASK, (buf[0] + bias[3]));
- break;
+ /* MTK_GPHY_ID_MT7981 enters default case */
+ default:
+ break;
}
- return 0;
-}
-static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
- phy_cal_pair_t txg_calen_x)
-{
- u16 tx_r50_cal_val[1];
+ val = clamp_val(bias + tx_r50_cal_val, 0, 63);
- switch(txg_calen_x) {
- case PAIR_A:
- tx_r50_cal_val[0] = EFS_DA_TX_R50_A(buf[1]);
- break;
- case PAIR_B:
- tx_r50_cal_val[0] = EFS_DA_TX_R50_B(buf[1]);
- break;
- case PAIR_C:
- tx_r50_cal_val[0] = EFS_DA_TX_R50_C(buf[2]);
- break;
- case PAIR_D:
- tx_r50_cal_val[0] = EFS_DA_TX_R50_D(buf[2]);
- break;
+ switch (txg_calen_x) {
+ case PAIR_A:
+ reg = MTK_PHY_DA_TX_R50_PAIR_A;
+ break;
+ case PAIR_B:
+ reg = MTK_PHY_DA_TX_R50_PAIR_B;
+ break;
+ case PAIR_C:
+ reg = MTK_PHY_DA_TX_R50_PAIR_C;
+ break;
+ case PAIR_D:
+ reg = MTK_PHY_DA_TX_R50_PAIR_D;
+ break;
}
- tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
return 0;
}
-static int tx_r50_cal_sw(struct phy_device *phydev, phy_cal_pair_t txg_calen_x)
+static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
+ u8 txg_calen_x)
{
- u8 rg_zcal_ctrl_def;
- u8 zcal_lower, zcal_upper, rg_zcal_ctrl;
- u8 lower_ret, upper_ret;
- u16 tx_r50_cal_val[1];
- int ret;
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG,
- MTK_PHY_ANA_TEST_MODE_MASK, MTK_PHY_TANA_CAL_MODE << 8);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_TXVOS_CALEN);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG2,
- BIT(txg_calen_x * 4));
- phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG110,
- MTK_PHY_RG_TST_DMY2_MASK, 0x1);
-
- rg_zcal_ctrl_def = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5) &
- MTK_PHY_RG_ZCAL_CTRL_MASK;
- zcal_lower = ZCAL_CTRL_MIN;
- zcal_upper = ZCAL_CTRL_MAX;
-
- dev_dbg(&phydev->mdio.dev, "Start TX-R50 Pair%c SW cal.\n", pair[txg_calen_x]);
- while((zcal_upper-zcal_lower) > 1) {
- rg_zcal_ctrl = DIV_ROUND_CLOSEST(zcal_lower+zcal_upper, 2);
- ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl);
- if(ret==1) {
- zcal_upper = rg_zcal_ctrl;
- upper_ret = ret;
- } else if(ret==0) {
- zcal_lower = rg_zcal_ctrl;
- lower_ret = ret;
- } else
- goto restore;
- }
+ u16 tx_r50_cal_val;
- if(zcal_lower == ZCAL_CTRL_MIN) {
- ret = lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_lower);
- } else if(zcal_upper == ZCAL_CTRL_MAX) {
- ret = upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_upper);
+ switch (txg_calen_x) {
+ case PAIR_A:
+ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
+ break;
+ case PAIR_B:
+ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
+ break;
+ case PAIR_C:
+ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
+ break;
+ case PAIR_D:
+ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
+ break;
}
- if (ret < 0)
- goto restore;
-
- ret = upper_ret-lower_ret;
- if (ret == 1) {
- tx_r50_cal_val[0] = mt798x_zcal_to_r50[zcal_upper];
- tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
- dev_info(&phydev->mdio.dev, "TX-R50 Pair%c SW cal result: 0x%x\n",
- pair[txg_calen_x], zcal_lower);
- ret = 0;
- } else
- ret = -EINVAL;
-
-restore:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG,
- MTK_PHY_ANA_TEST_MODE_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG2,
- BIT(txg_calen_x * 4));
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DEV1F_REG110,
- MTK_PHY_RG_TST_DMY2_MASK);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl_def);
+ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
- return ret;
+ return 0;
}
-static int tx_vcm_cal_sw(struct phy_device *phydev, phy_cal_pair_t rg_txreserve_x)
+static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
{
u8 lower_idx, upper_idx, txreserve_val;
u8 lower_ret, upper_ret;
int ret;
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_ANA_CALEN);
+ MTK_PHY_RG_ANA_CALEN);
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_CAL_CKINV);
+ MTK_PHY_RG_CAL_CKINV);
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_TXVOS_CALEN);
+ MTK_PHY_RG_TXVOS_CALEN);
- switch(rg_txreserve_x) {
- case PAIR_A:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17D,
- MTK_PHY_DASN_DAC_IN0_A_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG181,
- MTK_PHY_DASN_DAC_IN1_A_MASK);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_ZCALEN_A);
- break;
- case PAIR_B:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17E,
- MTK_PHY_DASN_DAC_IN0_B_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG182,
- MTK_PHY_DASN_DAC_IN1_B_MASK);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_ZCALEN_B);
- break;
- case PAIR_C:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG17F,
- MTK_PHY_DASN_DAC_IN0_C_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG183,
- MTK_PHY_DASN_DAC_IN1_C_MASK);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_ZCALEN_C);
- break;
- case PAIR_D:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG180,
- MTK_PHY_DASN_DAC_IN0_D_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG184,
- MTK_PHY_DASN_DAC_IN1_D_MASK);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_ZCALEN_D);
- break;
- default:
- ret = -EINVAL;
- goto restore;
+ /* Also clear bit[9:0] for MTK_PHY_RG_DASN_DAC_IN0/1_A/B/C/D */
+ switch (rg_txreserve_x) {
+ case PAIR_A:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_DASN_DAC_IN0_A,
+ MTK_PHY_FORCE_DASN_DAC_IN0_A);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_DASN_DAC_IN1_A,
+ MTK_PHY_FORCE_DASN_DAC_IN1_A);
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_ANA_CAL_RG0,
+ MTK_PHY_RG_ZCALEN_A);
+ break;
+ case PAIR_B:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_DASN_DAC_IN0_B,
+ MTK_PHY_FORCE_DASN_DAC_IN0_B);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_DASN_DAC_IN1_B,
+ MTK_PHY_FORCE_DASN_DAC_IN1_B);
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_ANA_CAL_RG1,
+ MTK_PHY_RG_ZCALEN_B);
+ break;
+ case PAIR_C:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_DASN_DAC_IN0_C,
+ MTK_PHY_FORCE_DASN_DAC_IN0_C);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_DASN_DAC_IN1_C,
+ MTK_PHY_FORCE_DASN_DAC_IN1_C);
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_ANA_CAL_RG1,
+ MTK_PHY_RG_ZCALEN_C);
+ break;
+ case PAIR_D:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_DASN_DAC_IN0_D,
+ MTK_PHY_FORCE_DASN_DAC_IN0_D);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_DASN_DAC_IN1_D,
+ MTK_PHY_FORCE_DASN_DAC_IN1_D);
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_ANA_CAL_RG1,
+ MTK_PHY_RG_ZCALEN_D);
+ break;
+ default:
+ ret = -EINVAL;
+ goto restore;
}
lower_idx = TXRESERVE_MIN;
upper_idx = TXRESERVE_MAX;
dev_dbg(&phydev->mdio.dev, "Start TX-VCM SW cal.\n");
- while((upper_idx-lower_idx) > 1) {
- txreserve_val = DIV_ROUND_CLOSEST(lower_idx+upper_idx, 2);
+ while ((upper_idx - lower_idx) > 1) {
+ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK,
+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
+ MTK_PHY_DA_RX_PSBN_LP_MASK,
txreserve_val << 12 | txreserve_val << 8 |
txreserve_val << 4 | txreserve_val);
- if(ret==1) {
+ if (ret == 1) {
upper_idx = txreserve_val;
upper_ret = ret;
- } else if(ret==0) {
+ } else if (ret == 0) {
lower_idx = txreserve_val;
lower_ret = ret;
- } else
+ } else {
goto restore;
+ }
}
- if(lower_idx == TXRESERVE_MIN) {
- ret = lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK,
- lower_idx << 12 | lower_idx << 8 | lower_idx << 4 | lower_idx);
- } else if(upper_idx == TXRESERVE_MAX) {
- ret = upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK,
- upper_idx << 12 | upper_idx << 8 | upper_idx << 4 | upper_idx);
+ if (lower_idx == TXRESERVE_MIN) {
+ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RXADC_CTRL_RG9,
+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
+ MTK_PHY_DA_RX_PSBN_LP_MASK,
+ lower_idx << 12 | lower_idx << 8 |
+ lower_idx << 4 | lower_idx);
+ ret = lower_ret;
+ } else if (upper_idx == TXRESERVE_MAX) {
+ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RXADC_CTRL_RG9,
+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
+ MTK_PHY_DA_RX_PSBN_LP_MASK,
+ upper_idx << 12 | upper_idx << 8 |
+ upper_idx << 4 | upper_idx);
+ ret = upper_ret;
}
if (ret < 0)
goto restore;
@@ -908,146 +772,284 @@
/* We calibrate TX-VCM in different logic. Check upper index and then
* lower index. If this calibration is valid, apply lower index's result.
*/
- ret = upper_ret-lower_ret;
+ ret = upper_ret - lower_ret;
if (ret == 1) {
ret = 0;
/* Make sure we use upper_idx in our calibration system */
cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK,
- upper_idx << 12 | upper_idx << 8 | upper_idx << 4 | upper_idx);
- dev_info(&phydev->mdio.dev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
- } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && lower_ret == 1) {
+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
+ MTK_PHY_DA_RX_PSBN_LP_MASK,
+ upper_idx << 12 | upper_idx << 8 |
+ upper_idx << 4 | upper_idx);
+ dev_info(&phydev->mdio.dev, "TX-VCM SW cal result: 0x%x\n",
+ upper_idx);
+ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
+ lower_ret == 1) {
ret = 0;
cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK,
- lower_idx << 12 | lower_idx << 8 | lower_idx << 4 | lower_idx);
- dev_warn(&phydev->mdio.dev, "TX-VCM SW cal result at low margin 0x%x\n", lower_idx);
- } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && lower_ret == 0) {
+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
+ MTK_PHY_DA_RX_PSBN_LP_MASK,
+ lower_idx << 12 | lower_idx << 8 |
+ lower_idx << 4 | lower_idx);
+ dev_warn(&phydev->mdio.dev,
+ "TX-VCM SW cal result at low margin 0x%x\n",
+ lower_idx);
+ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
+ lower_ret == 0) {
ret = 0;
- dev_warn(&phydev->mdio.dev, "TX-VCM SW cal result at high margin 0x%x\n", upper_idx);
- } else
+ dev_warn(&phydev->mdio.dev,
+ "TX-VCM SW cal result at high margin 0x%x\n",
+ upper_idx);
+ } else {
ret = -EINVAL;
+ }
restore:
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_ANA_CALEN);
+ MTK_PHY_RG_ANA_CALEN);
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_TXVOS_CALEN);
+ MTK_PHY_RG_TXVOS_CALEN);
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_ZCALEN_A);
+ MTK_PHY_RG_ZCALEN_A);
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | MTK_PHY_RG_ZCALEN_D);
+ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
+ MTK_PHY_RG_ZCALEN_D);
return ret;
}
-static void mtk_gephy_config_init(struct phy_device *phydev)
+static inline void mt798x_phy_common_finetune(struct phy_device *phydev)
{
- /* Disable EEE */
- phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
-
- /* Enable HW auto downshift */
- phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
+ u32 i;
- /* Increase SlvDPSready time */
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- __phy_write(phydev, 0x10, 0xafae);
- __phy_write(phydev, 0x12, 0x2f);
- __phy_write(phydev, 0x10, 0x8fae);
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+ /* EnabRandUpdTrig = 1 */
+ __phy_write(phydev, 0x11, 0x2f00);
+ __phy_write(phydev, 0x12, 0xe);
+ __phy_write(phydev, 0x10, 0x8fb0);
- /* Adjust 100_mse_threshold */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
+ /* NormMseLoThresh = 85 */
+ __phy_write(phydev, 0x11, 0x55a0);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x83aa);
- /* Disable mcc */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
-}
+ /* SSTrKp1000Slv = 5 */
+ __phy_write(phydev, 0x11, 0xbaef);
+ __phy_write(phydev, 0x12, 0x2e);
+ __phy_write(phydev, 0x10, 0x968c);
-static int mt7530_phy_config_init(struct phy_device *phydev)
-{
- mtk_gephy_config_init(phydev);
+ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
+ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
+ */
+ __phy_write(phydev, 0x11, 0xd10a);
+ __phy_write(phydev, 0x12, 0x34);
+ __phy_write(phydev, 0x10, 0x8f82);
- /* Increase post_update_timer */
- phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
+ /* VcoSlicerThreshBitsHigh */
+ __phy_write(phydev, 0x11, 0x5555);
+ __phy_write(phydev, 0x12, 0x55);
+ __phy_write(phydev, 0x10, 0x8ec0);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
- return 0;
-}
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-static int mt7531_phy_config_init(struct phy_device *phydev)
-{
- if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
- return -EINVAL;
+ /* rg_tr_lpf_cnt_val = 512 */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
- mtk_gephy_config_init(phydev);
+ /* IIR2 related */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
- /* PHY link down power saving enable */
- phy_set_bits(phydev, 0x17, BIT(4));
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
+ /* FFE peaking */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
+ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
+ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
- /* Set TX Pair delay selection */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
+ /* TX shape */
+ /* 10/100/1000 TX shaper is enabled by default */
+ for (i = 0x202; i < 0x230; i += 2) {
+ if (i == 0x20c || i == 0x218 || i == 0x224)
+ continue;
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, i + 1, 0x23);
+ }
- return 0;
+ /* Disable LDO pump */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
+ /* Adjust LDO output voltage */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
+}
+
+static inline void mt7981_phy_finetune(struct phy_device *phydev)
+{
+ /* 100M eye finetune:
+ * Keep middle level of TX MLT3 shapper as default.
+ * Only change TX MLT3 overshoot level here.
+ */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1,
+ 0x1ce);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1,
+ 0x1c1);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0,
+ 0x20f);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0,
+ 0x202);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1,
+ 0x3d0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1,
+ 0x3c0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0,
+ 0x13);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0,
+ 0x5);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
+ __phy_write(phydev, 0x11, 0xc71);
+ __phy_write(phydev, 0x12, 0xc);
+ __phy_write(phydev, 0x10, 0x8fae);
+
+ /* TrFreeze = 0 */
+ __phy_write(phydev, 0x11, 0x0);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x9686);
+
+ /* ResetSyncOffset = 6 */
+ __phy_write(phydev, 0x11, 0x600);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x8fc0);
+
+ /* VgaDecRate = 1 */
+ __phy_write(phydev, 0x11, 0x4c2a);
+ __phy_write(phydev, 0x12, 0x3e);
+ __phy_write(phydev, 0x10, 0x8fa4);
+
+ /* FfeUpdGainForce = 4 */
+ __phy_write(phydev, 0x11, 0x240);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x9680);
+
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
}
+static inline void mt7988_phy_finetune(struct phy_device *phydev)
+{
+ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
+ 0x020d, 0x0206, 0x0384, 0x03d0,
+ 0x03c6, 0x030a, 0x0011, 0x0005 };
+ int i;
+
+ for (i = 0; i < MTK_PHY_TX_MLT3_END; i++)
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
+
+ /* TCT finetune */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
+
+ /* Disable TX power saving */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+
+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
+ __phy_write(phydev, 0x11, 0x671);
+ __phy_write(phydev, 0x12, 0xc);
+ __phy_write(phydev, 0x10, 0x8fae);
+
+ /* ResetSyncOffset = 5 */
+ __phy_write(phydev, 0x11, 0x500);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x8fc0);
+
+ /* VgaDecRate is 1 at default on mt7988 */
+
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
+ /* TxClkOffset = 2 */
+ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
+ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+}
+
static inline void mt798x_phy_eee(struct phy_device *phydev)
{
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
- MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
- MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
- FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
- FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
+ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
+ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
- MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
+ 0xff));
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_TESTMUX_ADC_CTRL, MTK_PHY_RG_TXEN_DIG_MASK);
+ MTK_PHY_RG_TESTMUX_ADC_CTRL,
+ MTK_PHY_RG_TXEN_DIG_MASK);
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
+ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
+ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
- MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | MTK_PHY_LPI_SLV_SEND_TX_EN,
- FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
+ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
+ MTK_PHY_LPI_SLV_SEND_TX_EN,
+ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
- MTK_PHY_LPI_SEND_LOC_TIMER_MASK | MTK_PHY_LPI_TXPCS_LOC_RCV,
- FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
+ MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
+ MTK_PHY_LPI_TXPCS_LOC_RCV,
+ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
- MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
- FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
- FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
+ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
+ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
+ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
- MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
- FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 0x33) |
- MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
- MTK_PHY_LPI_VCO_EEE_STG0_EN);
+ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
+ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
+ 0x33) |
+ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
+ MTK_PHY_LPI_VCO_EEE_STG0_EN);
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
- MTK_PHY_EEE_WAKE_MAS_INT_DC | MTK_PHY_EEE_WAKE_SLV_INT_DC);
+ MTK_PHY_EEE_WAKE_MAS_INT_DC |
+ MTK_PHY_EEE_WAKE_SLV_INT_DC);
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
- MTK_PHY_SMI_DETCNT_MAX_MASK,
- FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
- MTK_PHY_SMI_DET_MAX_EN);
+ MTK_PHY_SMI_DETCNT_MAX_MASK,
+ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
+ MTK_PHY_SMI_DET_MAX_EN);
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
- MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
- MTK_PHY_TREC_UPDATE_ENAB_CLR |
- MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
- MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
+ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
+ MTK_PHY_TREC_UPDATE_ENAB_CLR |
+ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
+ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
/* Regsigdet_sel_1000 = 0 */
@@ -1086,278 +1088,111 @@
__phy_write(phydev, 0x10, 0x96ca);
/* DfeTailEnableVgaThresh1000 = 27 */
- __phy_write(phydev, 0x11, 0x36);
+ /* InhibitDisableDfeTail1000 = 1 */
+ __phy_write(phydev, 0x11, 0x37);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x8f80);
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
- __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000,
- FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000, 0x19c));
+ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
+ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
- __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH,
- FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH, 0xc));
+ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
+ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
- MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
}
-static inline void mt7981_phy_finetune(struct phy_device *phydev)
+static inline int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
+ u8 start_pair, u8 end_pair)
{
- u32 i;
- /* 100M eye finetune:
- * Keep middle level of TX MLT3 shapper as default.
- * Only change TX MLT3 overshoot level here.
- */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1, 0x1ce);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1, 0x1c1);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0, 0x20f);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0, 0x202);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1, 0x3d0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1, 0x3c0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0, 0x13);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0, 0x5);
-
- /* TX-AMP finetune:
- * 100M +4, 1000M +6 to default value.
- * If efuse values aren't valid, TX-AMP uses the below values.
- */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 0x9824);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 0x9026);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 0x2624);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 0x2426);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 0x2624);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 0x2426);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 0x2624);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 0x2426);
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* EnabRandUpdTrig = 1 */
- __phy_write(phydev, 0x11, 0x2f00);
- __phy_write(phydev, 0x12, 0xe);
- __phy_write(phydev, 0x10, 0x8fb0);
-
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
- __phy_write(phydev, 0x11, 0xc71);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
- /* NormMseLoThresh = 85 */
- __phy_write(phydev, 0x11, 0x55a0);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x83aa);
-
- /* InhibitDisableDfeTail1000 = 1 */
- __phy_write(phydev, 0x11, 0x2b);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8f80);
-
- /* SSTrKp1000Slv = 5 */
- __phy_write(phydev, 0x11, 0xbaef);
- __phy_write(phydev, 0x12, 0x2e);
- __phy_write(phydev, 0x10, 0x968c);
-
- /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
- * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
- */
- __phy_write(phydev, 0x11, 0xd10a);
- __phy_write(phydev, 0x12, 0x34);
- __phy_write(phydev, 0x10, 0x8f82);
-
- /* TrFreeze = 0 */
- __phy_write(phydev, 0x11, 0x0);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9686);
-
- /* VcoSlicerThreshBitsHigh */
- __phy_write(phydev, 0x11, 0x5555);
- __phy_write(phydev, 0x12, 0x55);
- __phy_write(phydev, 0x10, 0x8ec0);
-
- /* ResetSyncOffset = 6 */
- __phy_write(phydev, 0x11, 0x600);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8fc0);
-
- /* VgaDecRate = 1 */
- __phy_write(phydev, 0x11, 0x4c2a);
- __phy_write(phydev, 0x12, 0x3e);
- __phy_write(phydev, 0x10, 0x8fa4);
-
- /* FfeUpdGainForce = 4 */
- __phy_write(phydev, 0x11, 0x240);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9680);
-
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-
- /* rg_tr_lpf_cnt_val = 512 */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
-
- /* IIR2 related */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
-
- /* FFE peaking */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
- MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
- MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
+ u8 pair_n;
+ int ret;
- /* TX shape */
- /* 10/100/1000 TX shaper is enabled by default */
- for (i = 0x202; i < 0x230; i += 2) {
- if (i == 0x20c || i == 0x218 || i == 0x224)
- continue;
- phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219);
- phy_write_mmd(phydev, MDIO_MMD_VEND2, i+1, 0x23);
+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
+ /* TX_OFFSET & TX_AMP have no SW calibration. */
+ switch (cal_item) {
+ case TX_VCM:
+ ret = tx_vcm_cal_sw(phydev, pair_n);
+ break;
+ default:
+ return -EINVAL;
+ }
+ if (ret)
+ return ret;
}
-
- /* Disable LDO pump */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
-
- /* Adjust LDO output voltage */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
-
- mt798x_phy_eee(phydev);
+ return 0;
}
-static inline void mt7988_phy_finetune(struct phy_device *phydev)
+static inline int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
+ u8 start_pair, u8 end_pair, u32 *buf)
{
- int i;
- u16 val[12] = {0x0187, 0x01cd, 0x01c8, 0x0182,
- 0x020d, 0x0206, 0x0384, 0x03d0,
- 0x03c6, 0x030a, 0x0011, 0x0005};
+ u8 pair_n;
+ int ret;
- for(i=0; i<MTK_PHY_TX_MLT3_END; i++) {
- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
+ /* TX_VCM has no efuse calibration. */
+ switch (cal_item) {
+ case REXT:
+ ret = rext_cal_efuse(phydev, buf);
+ break;
+ case TX_OFFSET:
+ ret = tx_offset_cal_efuse(phydev, buf);
+ break;
+ case TX_AMP:
+ ret = tx_amp_cal_efuse(phydev, buf);
+ break;
+ case TX_R50:
+ ret = tx_r50_cal_efuse(phydev, buf, pair_n);
+ break;
+ default:
+ return -EINVAL;
+ }
+ if (ret)
+ return ret;
}
- /* TCT finetune */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
-
- /* Disable TX power saving */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* EnabRandUpdTrig = 1 */
- __phy_write(phydev, 0x11, 0x2f00);
- __phy_write(phydev, 0x12, 0xe);
- __phy_write(phydev, 0x10, 0x8fb0);
-
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
- __phy_write(phydev, 0x11, 0x671);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
- /* NormMseLoThresh = 85 */
- __phy_write(phydev, 0x11, 0x55a0);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x83aa);
-
- /* InhibitDisableDfeTail1000 = 1 */
- __phy_write(phydev, 0x11, 0x2b);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8f80);
-
- /* SSTr related */
- __phy_write(phydev, 0x11, 0xbaef);
- __phy_write(phydev, 0x12, 0x2e);
- __phy_write(phydev, 0x10, 0x968c);
-
- /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
- * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
- */
- __phy_write(phydev, 0x11, 0xd10a);
- __phy_write(phydev, 0x12, 0x34);
- __phy_write(phydev, 0x10, 0x8f82);
-
- /* VcoSlicerThreshBitsHigh */
- __phy_write(phydev, 0x11, 0x5555);
- __phy_write(phydev, 0x12, 0x55);
- __phy_write(phydev, 0x10, 0x8ec0);
-
- /* ResetSyncOffset = 5 */
- __phy_write(phydev, 0x11, 0x500);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8fc0);
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
- /* TxClkOffset = 2 */
- __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
- FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-
- /* rg_tr_lpf_cnt_val = 512 */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
-
- /* IIR2 related */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
+ return 0;
+}
- /* FFE peaking */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
- MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
- MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
+static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
+ enum CAL_MODE cal_mode, u8 start_pair,
+ u8 end_pair, u32 *buf)
+{
+ int ret;
+ char cal_prop[5][20] = { "mediatek,rext", "mediatek,tx_offset",
+ "mediatek,tx_amp", "mediatek,tx_r50",
+ "mediatek,tx_vcm" };
- /* TX shape */
- /* 10/100/1000 TX shaper is enabled by default */
- for (i = 0x202; i < 0x230; i += 2) {
- if (i == 0x20c || i == 0x218 || i == 0x224)
- continue;
- phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219);
- phy_write_mmd(phydev, MDIO_MMD_VEND2, i+1, 0x23);
+ switch (cal_mode) {
+ case EFUSE_M:
+ ret = cal_efuse(phydev, cal_item, start_pair,
+ end_pair, buf);
+ break;
+ case SW_M:
+ ret = cal_sw(phydev, cal_item, start_pair, end_pair);
+ break;
+ default:
+ return -EINVAL;
}
- /* Disable LDO pump */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
-
- /* Adjust LDO output voltage */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
+ if (ret) {
+ dev_err(&phydev->mdio.dev, "[%s]cal failed\n", cal_prop[cal_item]);
+ return -EIO;
+ }
- mt798x_phy_eee(phydev);
+ return 0;
}
static int mt798x_phy_calibration(struct phy_device *phydev)
{
- const char *cal_mode_from_dts;
- int i, ret;
- int cal_ret = 0;
+ int ret = 0;
u32 *buf;
- bool efs_valid = true;
size_t len;
struct nvmem_cell *cell;
@@ -1376,21 +1211,27 @@
return PTR_ERR(buf);
nvmem_cell_put(cell);
- if(!buf[0] && !buf[1] && !buf[2] && !buf[3])
- efs_valid = false;
-
- if (len < 4 * sizeof(u32)) {
- dev_err(&phydev->mdio.dev, "invalid calibration data\n");
+ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
+ dev_err(&phydev->mdio.dev, "invalid efuse data\n");
ret = -EINVAL;
goto out;
}
- CAL_FLOW(rext, SW_EFUSE, cal_mode_from_dts, NO_PAIR, buf)
- CAL_FLOW(tx_offset, EFUSE, cal_mode_from_dts, NO_PAIR, buf)
- CAL_FLOW(tx_amp, EFUSE, cal_mode_from_dts, NO_PAIR, buf)
- CAL_FLOW(tx_r50, SW_EFUSE, cal_mode_from_dts, PAIR_A_TO_D, buf)
- CAL_FLOW(tx_vcm, SW, cal_mode_from_dts, PAIR_A_TO_A)
- ret = 0;
+ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
+ if (ret)
+ goto out;
+ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
+ if (ret)
+ goto out;
+ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
+ if (ret)
+ goto out;
+ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
+ if (ret)
+ goto out;
+ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
+ if (ret)
+ goto out;
out:
kfree(buf);
@@ -1399,54 +1240,26 @@
static int mt7981_phy_probe(struct phy_device *phydev)
{
+ mt798x_phy_common_finetune(phydev);
mt7981_phy_finetune(phydev);
+ mt798x_phy_eee(phydev);
return mt798x_phy_calibration(phydev);
}
static int mt7988_phy_probe(struct phy_device *phydev)
{
- struct device_node *np;
- void __iomem *boottrap;
- u32 reg;
- int port;
-
- /* Setup LED polarity according to boottrap's polarity */
- np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap");
- if (!np)
- return -ENOENT;
- boottrap = of_iomap(np, 0);
- if (!boottrap)
- return -ENOMEM;
- reg = readl(boottrap);
- port = phydev->mdio.addr;
- if ((port == GPHY_PORT0 && reg & BIT(8)) ||
- (port == GPHY_PORT1 && reg & BIT(9)) ||
- (port == GPHY_PORT2 && reg & BIT(10)) ||
- (port == GPHY_PORT3 && reg & BIT(11))) {
- phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
- MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_ON_LINK10 |
- MTK_PHY_LED0_ON_LINK100 | MTK_PHY_LED0_ON_LINK1000);
- } else {
- phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
- MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY |
- MTK_PHY_LED0_ON_LINK10 | MTK_PHY_LED0_ON_LINK100 |
- MTK_PHY_LED0_ON_LINK1000);
- }
- phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
- MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX |
- MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX |
- MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX);
-
+ mt798x_phy_common_finetune(phydev);
mt7988_phy_finetune(phydev);
+ mt798x_phy_eee(phydev);
return mt798x_phy_calibration(phydev);
}
+#endif
static struct phy_driver mtk_gephy_driver[] = {
-#if 0
{
- PHY_ID_MATCH_EXACT(0x03a29412),
+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530),
.name = "MediaTek MT7530 PHY",
.config_init = mt7530_phy_config_init,
/* Interrupts are handled by the switch, not the PHY
@@ -1460,7 +1273,7 @@
.write_page = mtk_gephy_write_page,
},
{
- PHY_ID_MATCH_EXACT(0x03a29441),
+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531),
.name = "MediaTek MT7531 PHY",
.config_init = mt7531_phy_config_init,
/* Interrupts are handled by the switch, not the PHY
@@ -1473,14 +1286,11 @@
.read_page = mtk_gephy_read_page,
.write_page = mtk_gephy_write_page,
},
-#endif
+#ifdef CONFIG_MEDIATEK_GE_PHY_SOC
{
- PHY_ID_MATCH_EXACT(0x03a29461),
+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
.name = "MediaTek MT7981 PHY",
.probe = mt7981_phy_probe,
- /* Interrupts are handled by the switch, not the PHY
- * itself.
- */
.config_intr = genphy_no_config_intr,
.handle_interrupt = genphy_no_ack_interrupt,
.suspend = genphy_suspend,
@@ -1489,12 +1299,9 @@
.write_page = mtk_gephy_write_page,
},
{
- PHY_ID_MATCH_EXACT(0x03a29481),
+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
.name = "MediaTek MT7988 PHY",
.probe = mt7988_phy_probe,
- /* Interrupts are handled by the switch, not the PHY
- * itself.
- */
.config_intr = genphy_no_config_intr,
.handle_interrupt = genphy_no_ack_interrupt,
.suspend = genphy_suspend,
@@ -1502,6 +1309,7 @@
.read_page = mtk_gephy_read_page,
.write_page = mtk_gephy_write_page,
},
+#endif
};
module_phy_driver(mtk_gephy_driver);
@@ -1512,6 +1320,8 @@
};
MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
+MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
MODULE_LICENSE("GPL");
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7986.cfg b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7986.cfg
index 4d7fe1d..80d5d9f 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7986.cfg
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7986.cfg
@@ -302,6 +302,7 @@
CONFIG_MDIO_DEVICE=y
# CONFIG_MEDIATEK_2P5GE_PHY is not set
# CONFIG_MEDIATEK_GE_PHY is not set
+# CONFIG_MEDIATEK_GE_PHY_SOC is not set
CONFIG_MEDIATEK_MT6577_AUXADC=y
CONFIG_MEDIATEK_NETSYS_V2=y
# CONFIG_MEDIATEK_NETSYS_V3 is not set
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7988.cfg b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7988.cfg
index 02e863d..4c7e962 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7988.cfg
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/mt7988.cfg
@@ -272,6 +272,7 @@
CONFIG_MDIO_I2C=y
CONFIG_MEDIATEK_2P5GE_PHY=y
CONFIG_MEDIATEK_GE_PHY=y
+CONFIG_MEDIATEK_GE_PHY_SOC=y
CONFIG_MEDIATEK_MT6577_AUXADC=y
# CONFIG_MEDIATEK_NETSYS_V2 is not set
CONFIG_MEDIATEK_NETSYS_V3=y
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/nf_hnat/640-netfilter-nf_flow_table-add-hardware-offload-support.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/nf_hnat/640-netfilter-nf_flow_table-add-hardware-offload-support.patch
index 5767b41..88d2cb1 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/nf_hnat/640-netfilter-nf_flow_table-add-hardware-offload-support.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/nf_hnat/640-netfilter-nf_flow_table-add-hardware-offload-support.patch
@@ -23,7 +23,7 @@
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -929,6 +929,13 @@ struct devlink;
+@@ -931,6 +931,13 @@ struct devlink;
struct tlsdev_ops;
@@ -37,7 +37,7 @@
/*
* This structure defines the management hooks for network devices.
* The following hooks can be defined; unless noted otherwise, they are
-@@ -1161,6 +1168,10 @@ struct tlsdev_ops;
+@@ -1163,6 +1170,10 @@ struct tlsdev_ops;
* int (*ndo_bridge_dellink)(struct net_device *dev, struct nlmsghdr *nlh,
* u16 flags);
*
@@ -48,7 +48,7 @@
* int (*ndo_change_carrier)(struct net_device *dev, bool new_carrier);
* Called to change device carrier. Soft-devices (like dummy, team, etc)
* which do not represent real hardware may define this to allow their
-@@ -1408,6 +1419,8 @@ struct net_device_ops {
+@@ -1410,6 +1421,8 @@ struct net_device_ops {
int (*ndo_bridge_dellink)(struct net_device *dev,
struct nlmsghdr *nlh,
u16 flags);
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/nf_hnat/641-netfilter-nf_flow_table-support-hw-offload-through-v.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/nf_hnat/641-netfilter-nf_flow_table-support-hw-offload-through-v.patch
index 7cb79f7..d766ca9 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/nf_hnat/641-netfilter-nf_flow_table-support-hw-offload-through-v.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/nf_hnat/641-netfilter-nf_flow_table-support-hw-offload-through-v.patch
@@ -15,7 +15,7 @@
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -930,6 +930,7 @@ struct tlsdev_ops;
+@@ -932,6 +932,7 @@ struct tlsdev_ops;
struct flow_offload;
@@ -23,7 +23,7 @@
enum flow_offload_type {
FLOW_OFFLOAD_ADD = 0,
-@@ -1168,8 +1169,15 @@ enum flow_offload_type {
+@@ -1170,8 +1171,15 @@ enum flow_offload_type {
* int (*ndo_bridge_dellink)(struct net_device *dev, struct nlmsghdr *nlh,
* u16 flags);
*
@@ -40,7 +40,7 @@
* Adds/deletes flow entry to/from net device flowtable.
*
* int (*ndo_change_carrier)(struct net_device *dev, bool new_carrier);
-@@ -1419,8 +1427,11 @@ struct net_device_ops {
+@@ -1421,8 +1429,11 @@ struct net_device_ops {
int (*ndo_bridge_dellink)(struct net_device *dev,
struct nlmsghdr *nlh,
u16 flags);
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0308-dts-mt7622-add-snand-support.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0308-dts-mt7622-add-snand-support.patch
index b287780..9f37e3d 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0308-dts-mt7622-add-snand-support.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0308-dts-mt7622-add-snand-support.patch
@@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -554,6 +554,19 @@
+@@ -555,6 +555,19 @@
status = "disabled";
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0310-dts-add-wmac-support-for-mt7622-rfb1.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0310-dts-add-wmac-support-for-mt7622-rfb1.patch
index 84aed89..f6e437b 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0310-dts-add-wmac-support-for-mt7622-rfb1.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0310-dts-add-wmac-support-for-mt7622-rfb1.patch
@@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -716,6 +716,17 @@
+@@ -717,6 +717,17 @@
status = "disabled";
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
index 3c5558b..4fe0e0f 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
@@ -281,7 +281,7 @@
&pio {
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -794,45 +794,41 @@
+@@ -795,45 +795,41 @@
#reset-cells = <1>;
};
@@ -344,7 +344,7 @@
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
-@@ -844,15 +840,39 @@
+@@ -845,15 +841,39 @@
#interrupt-cells = <1>;
};
};
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/743-add-mediatek-ge-gphy-support.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/743-add-mediatek-ge-gphy-support.patch
deleted file mode 100644
index 718f324..0000000
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/743-add-mediatek-ge-gphy-support.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -512,6 +512,11 @@ config MESON_GXL_PHY
- ---help---
- Currently has a driver for the Amlogic Meson GXL Internal PHY
-
-+config MEDIATEK_GE_PHY
-+ tristate "MediaTek Gigabit Ethernet PHYs"
-+ help
-+ Supports the MediaTek Gigabit Ethernet PHYs.
-+
- config MICREL_PHY
- tristate "Micrel PHYs"
- ---help---
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -93,6 +93,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c
- obj-$(CONFIG_LXT_PHY) += lxt.o
- obj-$(CONFIG_MARVELL_PHY) += marvell.o
- obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
-+obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
- obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
- obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
- obj-$(CONFIG_MICREL_PHY) += micrel.o
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/746-add-mediatek-2p5ge-phy-support.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/746-add-mediatek-2p5ge-phy-support.patch
index a102660..efbec08 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/746-add-mediatek-2p5ge-phy-support.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/746-add-mediatek-2p5ge-phy-support.patch
@@ -1,8 +1,8 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -522,6 +522,11 @@ config MEDIATEK_GE_PHY
- help
- Supports the MediaTek Gigabit Ethernet PHYs.
+@@ -522,6 +522,11 @@ config MESON_GXL_PHY
+ ---help---
+ Currently has a driver for the Amlogic Meson GXL Internal PHY
+config MEDIATEK_2P5GE_PHY
+ tristate "MediaTek 2.5Gb Ethernet PHYs"
@@ -14,10 +14,10 @@
---help---
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -95,6 +95,7 @@ obj-$(CONFIG_LXT_PHY) += lxt.o
+@@ -95,6 +95,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c
+ obj-$(CONFIG_LXT_PHY) += lxt.o
obj-$(CONFIG_MARVELL_PHY) += marvell.o
obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
- obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
+obj-$(CONFIG_MEDIATEK_2P5GE_PHY)+= mediatek-2p5ge.o
obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch
index 26bef5f..9f2ecc4 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch
@@ -1,8 +1,6 @@
-diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
-index e0f724a..1f74ff2 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -511,6 +511,12 @@ config MARVELL_10G_PHY
+@@ -516,6 +516,12 @@ config MARVELL_10G_PHY
---help---
Support for the Marvell Alaska MV88X3310 and compatible PHYs.
@@ -15,21 +13,16 @@
config MESON_GXL_PHY
tristate "Amlogic Meson GXL Internal PHY"
depends on ARCH_MESON || COMPILE_TEST
-diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
-index e3c411f..7b44a98 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -94,6 +94,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
+@@ -95,6 +95,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c
obj-$(CONFIG_LXT_PHY) += lxt.o
obj-$(CONFIG_MARVELL_PHY) += marvell.o
obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
+obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
- obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
+ obj-$(CONFIG_MEDIATEK_2P5GE_PHY)+= mediatek-2p5ge.o
obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
-diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c
-new file mode 100644
-index 0000000..7304278
--- /dev/null
+++ b/drivers/net/phy/mxl-gpy.c
@@ -0,0 +1,738 @@
@@ -771,8 +764,6 @@
+MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
+MODULE_AUTHOR("Xu Liang");
+MODULE_LICENSE("GPL");
-diff --git a/include/linux/phy.h b/include/linux/phy.h
-index 19444cd..34bdd16 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -21,6 +21,7 @@
@@ -783,7 +774,7 @@
#include <linux/atomic.h>
-@@ -711,6 +712,18 @@ static inline int phy_read(struct phy_device *phydev, u32 regnum)
+@@ -711,6 +712,18 @@ static inline int phy_read(struct phy_de
return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
}
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/755-net-phy-sfp-add-rollball-support.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/755-net-phy-sfp-add-rollball-support.patch
index 6233046..65698d9 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/755-net-phy-sfp-add-rollball-support.patch
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/755-net-phy-sfp-add-rollball-support.patch
@@ -1,16 +1,14 @@
-diff --git a/drivers/net/phy/mdio-i2c.c b/drivers/net/phy/mdio-i2c.c
-index 0746e2c..81c8fe7 100644
--- a/drivers/net/phy/mdio-i2c.c
+++ b/drivers/net/phy/mdio-i2c.c
-@@ -11,6 +11,7 @@
- */
+@@ -12,6 +12,7 @@
#include <linux/i2c.h>
+ #include <linux/mdio/mdio-i2c.h>
#include <linux/phy.h>
+#include <linux/sfp.h>
- #include "mdio-i2c.h"
-
-@@ -29,7 +30,7 @@ static unsigned int i2c_mii_phy_addr(int phy_id)
+ /*
+ * I2C bus addresses 0x50 and 0x51 are normally an EEPROM, which is
+@@ -28,7 +29,7 @@ static unsigned int i2c_mii_phy_addr(int
return phy_id + 0x40;
}
@@ -19,7 +17,7 @@
{
struct i2c_adapter *i2c = bus->priv;
struct i2c_msg msgs[2];
-@@ -63,7 +64,8 @@ static int i2c_mii_read(struct mii_bus *bus, int phy_id, int reg)
+@@ -62,7 +63,8 @@ static int i2c_mii_read(struct mii_bus *
return data[0] << 8 | data[1];
}
@@ -29,7 +27,7 @@
{
struct i2c_adapter *i2c = bus->priv;
struct i2c_msg msg;
-@@ -92,9 +94,288 @@ static int i2c_mii_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
+@@ -91,9 +93,288 @@ static int i2c_mii_write(struct mii_bus
return ret < 0 ? ret : 0;
}
@@ -319,7 +317,7 @@
if (!i2c_check_functionality(i2c, I2C_FUNC_I2C))
return ERR_PTR(-EINVAL);
-@@ -105,10 +386,28 @@ struct mii_bus *mdio_i2c_alloc(struct device *parent, struct i2c_adapter *i2c)
+@@ -104,10 +385,28 @@ struct mii_bus *mdio_i2c_alloc(struct de
snprintf(mii->id, MII_BUS_ID_SIZE, "i2c:%s", dev_name(parent));
mii->parent = parent;
@@ -350,8 +348,6 @@
return mii;
}
EXPORT_SYMBOL_GPL(mdio_i2c_alloc);
-diff --git a/include/linux/mdio/mdio-i2c.h b/include/linux/mdio/mdio-i2c.h
-index 751dab2..1c21140 100644
--- a/include/linux/mdio/mdio-i2c.h
+++ b/include/linux/mdio/mdio-i2c.h
@@ -11,6 +11,14 @@ struct device;
@@ -370,11 +366,9 @@
+ enum mdio_i2c_proto protocol);
#endif
-diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
-index f360d92..67f34ed 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
-@@ -483,62 +483,105 @@ static void phylink_resolve(struct work_struct *w)
+@@ -483,62 +483,105 @@ static void phylink_resolve(struct work_
struct phylink *pl = container_of(w, struct phylink, resolve);
struct phylink_link_state link_state;
struct net_device *ndev = pl->netdev;
@@ -504,8 +498,6 @@
mod_timer(&pl->link_poll, jiffies + HZ);
if (pl->phydev)
phy_start(pl->phydev);
-diff --git a/drivers/net/phy/sfp-bus.c b/drivers/net/phy/sfp-bus.c
-index 42f0441..0d5ac2a 100644
--- a/drivers/net/phy/sfp-bus.c
+++ b/drivers/net/phy/sfp-bus.c
@@ -10,12 +10,6 @@
@@ -609,7 +601,7 @@
/**
* sfp_parse_port() - Parse the EEPROM base ID, setting the port type
* @bus: a pointer to the &struct sfp_bus structure for the sfp module
-@@ -359,7 +272,7 @@ void sfp_parse_support(struct sfp_bus *bus, const struct sfp_eeprom_id *id,
+@@ -359,7 +272,7 @@ void sfp_parse_support(struct sfp_bus *b
phylink_set(modes, 1000baseX_Full);
}
@@ -618,7 +610,7 @@
bus->sfp_quirk->modes(id, modes);
bitmap_or(support, support, modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
-@@ -734,12 +647,13 @@ void sfp_link_down(struct sfp_bus *bus)
+@@ -737,12 +650,13 @@ void sfp_link_down(struct sfp_bus *bus)
}
EXPORT_SYMBOL_GPL(sfp_link_down);
@@ -634,11 +626,9 @@
if (ops && ops->module_insert)
ret = ops->module_insert(bus->upstream, id);
-diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c
-index 3253366..8d95f49 100644
--- a/drivers/net/phy/sfp.c
+++ b/drivers/net/phy/sfp.c
-@@ -165,6 +165,7 @@ static const enum gpiod_flags gpio_flags[] = {
+@@ -165,6 +165,7 @@ static const enum gpiod_flags gpio_flags
* on board (for a copper SFP) time to initialise.
*/
#define T_WAIT msecs_to_jiffies(50)
@@ -646,7 +636,7 @@
#define T_START_UP msecs_to_jiffies(300)
#define T_START_UP_BAD_GPON msecs_to_jiffies(60000)
-@@ -204,8 +205,11 @@ static const enum gpiod_flags gpio_flags[] = {
+@@ -204,8 +205,11 @@ static const enum gpiod_flags gpio_flags
/* SFP modules appear to always have their PHY configured for bus address
* 0x56 (which with mdio-i2c, translates to a PHY address of 22).
@@ -686,7 +676,7 @@
#if IS_ENABLED(CONFIG_HWMON)
struct sfp_diag diag;
-@@ -303,6 +313,136 @@ static const struct of_device_id sfp_of_match[] = {
+@@ -303,6 +313,136 @@ static const struct of_device_id sfp_of_
};
MODULE_DEVICE_TABLE(of, sfp_of_match);
@@ -823,7 +813,7 @@
static unsigned long poll_jiffies;
static unsigned int sfp_gpio_get_state(struct sfp *sfp)
-@@ -414,9 +553,6 @@ static int sfp_i2c_write(struct sfp *sfp, bool a2, u8 dev_addr, void *buf,
+@@ -414,9 +554,6 @@ static int sfp_i2c_write(struct sfp *sfp
static int sfp_i2c_configure(struct sfp *sfp, struct i2c_adapter *i2c)
{
@@ -833,7 +823,7 @@
if (!i2c_check_functionality(i2c, I2C_FUNC_I2C))
return -EINVAL;
-@@ -424,7 +560,15 @@ static int sfp_i2c_configure(struct sfp *sfp, struct i2c_adapter *i2c)
+@@ -424,7 +561,15 @@ static int sfp_i2c_configure(struct sfp
sfp->read = sfp_i2c_read;
sfp->write = sfp_i2c_write;
@@ -850,7 +840,7 @@
if (IS_ERR(i2c_mii))
return PTR_ERR(i2c_mii);
-@@ -442,6 +586,12 @@ static int sfp_i2c_configure(struct sfp *sfp, struct i2c_adapter *i2c)
+@@ -442,6 +587,12 @@ static int sfp_i2c_configure(struct sfp
return 0;
}
@@ -863,7 +853,7 @@
/* Interface */
static int sfp_read(struct sfp *sfp, bool a2, u8 addr, void *buf, size_t len)
{
-@@ -487,17 +637,18 @@ static void sfp_soft_set_state(struct sfp *sfp, unsigned int state)
+@@ -487,17 +638,18 @@ static void sfp_soft_set_state(struct sf
static void sfp_soft_start_poll(struct sfp *sfp)
{
const struct sfp_eeprom_id *id = &sfp->id;
@@ -891,7 +881,7 @@
if (sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT) &&
!sfp->need_poll)
-@@ -511,10 +662,11 @@ static void sfp_soft_stop_poll(struct sfp *sfp)
+@@ -511,10 +663,11 @@ static void sfp_soft_stop_poll(struct sf
static unsigned int sfp_get_state(struct sfp *sfp)
{
@@ -906,7 +896,7 @@
state |= sfp_soft_get_state(sfp);
return state;
-@@ -1448,12 +1600,12 @@ static void sfp_sm_phy_detach(struct sfp *sfp)
+@@ -1448,12 +1601,12 @@ static void sfp_sm_phy_detach(struct sfp
sfp->mod_phy = NULL;
}
@@ -921,7 +911,7 @@
if (phy == ERR_PTR(-ENODEV))
return PTR_ERR(phy);
if (IS_ERR(phy)) {
-@@ -1548,6 +1700,14 @@ static void sfp_sm_fault(struct sfp *sfp, unsigned int next_state, bool warn)
+@@ -1548,6 +1701,14 @@ static void sfp_sm_fault(struct sfp *sfp
}
}
@@ -936,7 +926,7 @@
/* Probe a SFP for a PHY device if the module supports copper - the PHY
* normally sits at I2C bus address 0x56, and may either be a clause 22
* or clause 45 PHY.
-@@ -1563,19 +1723,23 @@ static int sfp_sm_probe_for_phy(struct sfp *sfp)
+@@ -1563,19 +1724,23 @@ static int sfp_sm_probe_for_phy(struct s
{
int err = 0;
@@ -969,7 +959,7 @@
return err;
}
-@@ -1819,11 +1983,33 @@ static int sfp_sm_mod_probe(struct sfp *sfp, bool report)
+@@ -1819,11 +1984,33 @@ static int sfp_sm_mod_probe(struct sfp *
if (ret < 0)
return ret;
@@ -1007,7 +997,7 @@
return 0;
}
-@@ -1936,7 +2122,8 @@ static void sfp_sm_module(struct sfp *sfp, unsigned int event)
+@@ -1936,7 +2123,8 @@ static void sfp_sm_module(struct sfp *sf
break;
/* Report the module insertion to the upstream device */
@@ -1017,7 +1007,7 @@
if (err < 0) {
sfp_sm_mod_next(sfp, SFP_MOD_ERROR, 0);
break;
-@@ -1995,6 +2182,8 @@ static void sfp_sm_main(struct sfp *sfp, unsigned int event)
+@@ -1995,6 +2183,8 @@ static void sfp_sm_main(struct sfp *sfp,
sfp_module_stop(sfp->sfp_bus);
if (sfp->mod_phy)
sfp_sm_phy_detach(sfp);
@@ -1026,7 +1016,7 @@
sfp_module_tx_disable(sfp);
sfp_soft_stop_poll(sfp);
sfp_sm_next(sfp, SFP_S_DOWN, 0);
-@@ -2018,9 +2207,10 @@ static void sfp_sm_main(struct sfp *sfp, unsigned int event)
+@@ -2018,9 +2208,10 @@ static void sfp_sm_main(struct sfp *sfp,
/* We need to check the TX_FAULT state, which is not defined
* while TX_DISABLE is asserted. The earliest we want to do
@@ -1039,7 +1029,7 @@
break;
case SFP_S_WAIT:
-@@ -2034,8 +2224,8 @@ static void sfp_sm_main(struct sfp *sfp, unsigned int event)
+@@ -2034,8 +2225,8 @@ static void sfp_sm_main(struct sfp *sfp,
* deasserting.
*/
timeout = sfp->module_t_start_up;
@@ -1050,7 +1040,7 @@
else
timeout = 1;
-@@ -2057,6 +2247,12 @@ static void sfp_sm_main(struct sfp *sfp, unsigned int event)
+@@ -2057,6 +2248,12 @@ static void sfp_sm_main(struct sfp *sfp,
sfp->sm_fault_retries == N_FAULT_INIT);
} else if (event == SFP_E_TIMEOUT || event == SFP_E_TX_CLEAR) {
init_done:
@@ -1063,7 +1053,7 @@
sfp->sm_phy_retries = R_PHY_RETRY;
goto phy_probe;
}
-@@ -2409,6 +2605,8 @@ static int sfp_probe(struct platform_device *pdev)
+@@ -2409,6 +2606,8 @@ static int sfp_probe(struct platform_dev
return PTR_ERR(sfp->gpio[i]);
}
@@ -1072,8 +1062,6 @@
sfp->get_state = sfp_gpio_get_state;
sfp->set_state = sfp_gpio_set_state;
-diff --git a/drivers/net/phy/sfp.h b/drivers/net/phy/sfp.h
-index b83f705..ef06d35 100644
--- a/drivers/net/phy/sfp.h
+++ b/drivers/net/phy/sfp.h
@@ -6,6 +6,13 @@
@@ -1090,7 +1078,7 @@
struct sfp_socket_ops {
void (*attach)(struct sfp *sfp);
void (*detach)(struct sfp *sfp);
-@@ -20,7 +27,8 @@ int sfp_add_phy(struct sfp_bus *bus, struct phy_device *phydev);
+@@ -20,7 +27,8 @@ int sfp_add_phy(struct sfp_bus *bus, str
void sfp_remove_phy(struct sfp_bus *bus);
void sfp_link_up(struct sfp_bus *bus);
void sfp_link_down(struct sfp_bus *bus);
@@ -1100,8 +1088,6 @@
void sfp_module_remove(struct sfp_bus *bus);
int sfp_module_start(struct sfp_bus *bus);
void sfp_module_stop(struct sfp_bus *bus);
-diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
-index 512f27b..daed73a 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -32,6 +32,15 @@
@@ -1165,7 +1151,7 @@
#ifdef CONFIG_HWMON
static umode_t mv3310_hwmon_is_visible(const void *data,
enum hwmon_sensor_types type,
-@@ -155,13 +188,6 @@ static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
+@@ -155,13 +188,6 @@ static int mv3310_hwmon_config(struct ph
MV_V2_TEMP_CTRL_MASK, val);
}
@@ -1179,7 +1165,7 @@
static int mv3310_hwmon_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
-@@ -185,10 +211,6 @@ static int mv3310_hwmon_probe(struct phy_device *phydev)
+@@ -185,10 +211,6 @@ static int mv3310_hwmon_probe(struct phy
if (ret)
return ret;
@@ -1190,7 +1176,7 @@
priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
priv->hwmon_name, phydev,
&mv3310_hwmon_chip_info, NULL);
-@@ -262,6 +284,11 @@ static int mv3310_probe(struct phy_device *phydev)
+@@ -262,6 +284,11 @@ static int mv3310_probe(struct phy_devic
return phy_sfp_probe(phydev, &mv3310_sfp_ops);
}
@@ -1202,7 +1188,7 @@
static int mv3310_suspend(struct phy_device *phydev)
{
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
-@@ -297,8 +324,84 @@ static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
+@@ -297,8 +324,84 @@ static bool mv3310_has_pma_ngbaset_quirk
MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
}
@@ -1287,7 +1273,7 @@
/* Check that the PHY interface type is compatible */
if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
-@@ -307,6 +410,16 @@ static int mv3310_config_init(struct phy_device *phydev)
+@@ -307,6 +410,16 @@ static int mv3310_config_init(struct phy
phydev->interface != PHY_INTERFACE_MODE_10GKR)
return -ENODEV;
@@ -1304,7 +1290,7 @@
return 0;
}
-@@ -384,6 +497,23 @@ static int mv3310_aneg_done(struct phy_device *phydev)
+@@ -384,6 +497,23 @@ static int mv3310_aneg_done(struct phy_d
static void mv3310_update_interface(struct phy_device *phydev)
{
@@ -1327,8 +1313,8 @@
+
if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
- phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
-@@ -499,11 +629,22 @@ static int mv3310_read_status(struct phy_device *phydev)
+ phydev->interface == PHY_INTERFACE_MODE_5GBASER ||
+@@ -503,11 +633,22 @@ static int mv3310_read_status(struct phy
return 0;
}
@@ -1351,7 +1337,7 @@
.get_features = mv3310_get_features,
.soft_reset = genphy_no_soft_reset,
.config_init = mv3310_config_init,
-@@ -513,11 +654,13 @@ static struct phy_driver mv3310_drivers[] = {
+@@ -517,11 +658,13 @@ static struct phy_driver mv3310_drivers[
.config_aneg = mv3310_config_aneg,
.aneg_done = mv3310_aneg_done,
.read_status = mv3310_read_status,
@@ -1365,7 +1351,7 @@
.probe = mv3310_probe,
.suspend = mv3310_suspend,
.resume = mv3310_resume,
-@@ -526,6 +669,7 @@ static struct phy_driver mv3310_drivers[] = {
+@@ -530,6 +673,7 @@ static struct phy_driver mv3310_drivers[
.config_aneg = mv3310_config_aneg,
.aneg_done = mv3310_aneg_done,
.read_status = mv3310_read_status,
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/756-net-phy-mediatek-ge-add-mt798x-support.patch b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/756-net-phy-mediatek-ge-add-mt798x-support.patch
new file mode 100644
index 0000000..aee8abf
--- /dev/null
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/756-net-phy-mediatek-ge-add-mt798x-support.patch
@@ -0,0 +1,36 @@
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -582,6 +582,23 @@ config MEDIATEK_2P5GE_PHY
+ ---help---
+ Supports MediaTek internal 2.5Gb Ethernet PHYs.
+
++config MEDIATEK_GE_PHY
++ tristate "MediaTek Gigabit Ethernet PHYs"
++ help
++ Supports the MediaTek Gigabit Ethernet PHYs.
++
+++config MEDIATEK_GE_PHY_SOC
++ bool "MediaTek SoC Ethernet PHYs"
++ depends on (ARM64 && ARCH_MEDIATEK && MEDIATEK_GE_PHY) || COMPILE_TEST
++ select NVMEM_MTK_EFUSE
++ help
++ Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
++
++ Include support for built-in Ethernet PHYs which are present in
++ the MT7981 and MT7988 SoCs. These PHYs need calibration data
++ present in the SoCs efuse and will dynamically calibrate VCM
++ (common-mode voltage) during startup.
++
+ config MICREL_PHY
+ tristate "Micrel PHYs"
+ ---help---
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -100,6 +100,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
+ obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
+ obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
+ obj-$(CONFIG_MEDIATEK_2P5GE_PHY)+= mediatek-2p5ge.o
++obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
+ obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
+ obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
+ obj-$(CONFIG_MICREL_PHY) += micrel.o
diff --git a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc
index 6ece5b2..c5f5cc8 100644
--- a/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc
+++ b/recipes-kernel/linux/linux-mediatek-5.4/mediatek/patches-5.4/patches-5.4.inc
@@ -105,7 +105,6 @@
file://740-add-gpy211-phy-support.patch \
file://741-add-default-setting-to-dsa-unused-port.patch \
file://742-net-dsa-add-MT7531-Gigabit-Ethernet-PHY-setting.patch \
- file://743-add-mediatek-ge-gphy-support.patch \
file://744-en8811h-2p5gphy-support.patch \
file://745-en8801sc-gphy-support.patch \
file://745-mdiobus-add-c45.patch \
@@ -120,6 +119,7 @@
file://753-net-mt753x-phy-coverity-scan.patch;apply=no \
file://754-net-phy-add-5GBASER.patch \
file://755-net-phy-sfp-add-rollball-support.patch \
+ file://756-net-phy-mediatek-ge-add-mt798x-support.patch \
file://8000-PATCH-1-4-tphy-support-type-switch-by-pericfg.patch \
file://8001-PATCH-2-4-dt-bindings-phy-Add-PHY_TYPE_DP-definition.patch \
file://8002-PATCH-3-4-dt-bindings-phy-Add-PHY_TYPE_XPCS-definition.patch \
diff --git a/recipes-kernel/linux/linux-mediatek_5.4.bb b/recipes-kernel/linux/linux-mediatek_5.4.bb
index 1b0f51c..47c79c0 100644
--- a/recipes-kernel/linux/linux-mediatek_5.4.bb
+++ b/recipes-kernel/linux/linux-mediatek_5.4.bb
@@ -8,8 +8,8 @@
KBRANCH ?= "linux-5.4.y"
-LINUX_VERSION ?= "5.4.231"
-SRCREV_machine ?= "59342376e8f0c704299dc7a2c14fed07ffb962e2"
+LINUX_VERSION ?= "5.4.238"
+SRCREV_machine ?= "6849d8c4a61a93bb3abf2f65c84ec1ebfa9a9fb6"
KMETA = "kernel-meta"
SRCREV_meta ?= "feeb59687bc0f054af837a5061f8d413ec7c93e9"