blob: 7b8fcf9e3affa912599138e3a3fa63fa584e484e [file] [log] [blame]
From 0fce899e41f4a9056720548ab96a567a193a991b Mon Sep 17 00:00:00 2001
From: "sujuan.chen" <sujuan.chen@mediatek.com>
Date: Wed, 19 Jul 2023 10:55:09 +0800
Subject: [PATCH 056/193] mtk: mt76: find rx token by physical address
The token id in RxDMAD may be incorrect when it is not the last frame in
WED HW. Lookup correct token id by physical address in sdp0.
Add len == 0 check to drop garbage frames
Change-Id: I4cd90294ad24990826075e92a710cc4e301dcbb7
Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
---
dma.c | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/dma.c b/dma.c
index e5be891..1021b3e 100644
--- a/dma.c
+++ b/dma.c
@@ -446,9 +446,32 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
mt76_dma_should_drop_buf(drop, ctrl, buf1, desc_info);
if (mt76_queue_is_wed_rx(q)) {
+ u32 id, find = 0;
u32 token = FIELD_GET(MT_DMA_CTL_TOKEN, buf1);
- struct mt76_rxwi_cache *r = mt76_rx_token_release(dev, token);
+ struct mt76_rxwi_cache *r;
+
+ if (*more) {
+ spin_lock_bh(&dev->rx_token_lock);
+
+ idr_for_each_entry(&dev->rx_token, r, id) {
+ if (r->dma_addr == le32_to_cpu(desc->buf0)) {
+ find = 1;
+ token = id;
+
+ /* Write correct id back to DMA*/
+ u32p_replace_bits(&buf1, id,
+ MT_DMA_CTL_TOKEN);
+ WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
+ break;
+ }
+ }
+ spin_unlock_bh(&dev->rx_token_lock);
+ if (!find)
+ return NULL;
+ }
+
+ r = mt76_rx_token_release(dev, token);
if (!r)
return NULL;
@@ -902,7 +925,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
if (!data)
break;
- if (drop)
+ if (drop || (len == 0))
goto free_frag;
if (q->rx_head)
--
2.45.2