- 677ed8a refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init by Boyan Karatotev · 1 year, 4 months ago
- 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 1 year, 6 months ago
- 0824b45 feat(bl2): add support to separate no-loadable sections by Jiafei Pan · 2 years, 3 months ago
- b0d69e8 fix(pie): invalidate data cache in the entire image range if PIE is enabled by Zelalem Aweke · 2 years, 8 months ago
- 8ce3394 feat(trf): initialize trap settings of trace filter control registers access by Manish V Badarkhe · 2 years, 11 months ago
- f7ee064 feat(sys_reg_trace): initialize trap settings of trace system registers access by Manish V Badarkhe · 2 years, 11 months ago
- 514e59c Add PIE support for AARCH32 by Yann Gautier · 3 years, 8 months ago
- e57bce8 Avoid the use of linker *_SIZE__ macros by Yann Gautier · 3 years, 10 months ago
- f3a4c54 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · 3 years, 6 months ago
- c241b57 el3_entrypoint_common: avoid overwriting arg3 by Yann Gautier · 4 years, 4 months ago
- d2f21b8 Add missing support for BL2_AT_EL3 in XIP memory by Lionel Debieve · 5 years ago
- 9074dea AArch32: Disable Secure Cycle Counter by Alexei Fedorov · 4 years, 10 months ago
- 457c64e aarch32: Allow compiling with soft-float toolchain by Manish Pandey · 5 years ago
- 404184d Merge pull request #1831 from antonio-nino-diaz-arm/an/sccd by Antonio Niño Díaz · 5 years ago
- 078e66f plat/arm: Support for Cortex A5 in FVP Versatile Express platform by Usama Arif · 5 years ago
- 3fbd3f5 Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · 5 years ago
- 8d1ade6 Reorganize architecture-dependent header files by Antonio Nino Diaz · 5 years ago[Renamed from include/common/aarch32/el3_common_macros.S]
- 0f3a004 Merge pull request #1731 from miyatsu/doc-fix-20181225 by Antonio Niño Díaz · 5 years ago