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git01.mediatek.com / filogic / atf / f9da1343f865a2fb9b0cb34d99fde50921507552 / plat / xilinx / zynqmp / include / platform_def.h
  1. afa91db Arm platforms: Rename PLAT_ARM_NS_IMAGE_OFFSET by Sandrine Bailleux · Thu Jan 31 15:01:32 2019 +0100
  2. 16fe5ab plat: xilinx: zynqmp: Move zynqmp_def.h to include directory by Jolly Shah · Tue Jan 08 11:16:16 2019 -0800
  3. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  4. 6f3ccc5 PSCI: Fix types of definitions by Antonio Nino Diaz · Fri Jul 20 09:17:26 2018 +0100
  5. ee1a114 plat: xilinx: zynqmp: Build for DDR if SPD is enabled by Siva Durga Prasad Paladugu · Wed Jun 20 17:01:13 2018 +0530
  6. efd431b zynqmp: Add wdt timeout restart functionality by Siva Durga Prasad Paladugu · Mon Apr 30 20:12:12 2018 +0530
  7. 8f5ddb3 zynqmp: Use DDR memory when DEBUG is enabled by Jolly Shah · Tue Jan 30 11:31:53 2018 -0800
  8. c150312 Update ULL() macro and instances of ull to comply with MISRA by David Cunado · Fri Feb 16 21:12:58 2018 +0000
  9. 9bde130 zynqmp: Migrate to using interrupt properties by Jeenu Viswambharan · Fri Sep 29 11:15:18 2017 +0100
  10. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  11. 6a9e03e zynqmp: Migrate to new address space macros by Soren Brinkmann · Fri Jan 06 11:07:00 2017 -0800
  12. 1209b26 zynqmp: Remove dead code by Soren Brinkmann · Wed Nov 16 15:50:14 2016 -0800
  13. 7ac746c zynqmp: Increase MAX_XLAT_TABLES by Soren Brinkmann · Mon Jul 25 10:33:53 2016 -0700
  14. 802ba1d zynqmp: Change default BL31 address space by Soren Brinkmann · Fri Jul 15 06:23:37 2016 -0700
  15. 6d1ba58 zynqmp: Separate code and rodata by Soren Brinkmann · Fri Jul 08 14:45:14 2016 -0700
  16. 845cd5c zynqmp: Reduce mapped memory area by Soren Brinkmann · Fri Apr 22 10:02:46 2016 -0700
  17. 4a9ca04 zynqmp: Revise memory configuration options by Soren Brinkmann · Thu Apr 14 10:27:00 2016 -0700
  18. 76fcae3 Add support for Xilinx Zynq UltraScale+ MPSOC by Soren Brinkmann · Sun Mar 06 20:16:27 2016 -0800