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git01.mediatek.com / filogic / atf / f860f273567903e1280bb15055ebbbc157ca87a8 / plat / rockchip / rk3399 / drivers / dram / dfs.c
  1. 7d0e3ba Enable -Wshadow always by Justin Chadwell · Tue Sep 17 15:21:50 2019 +0100
  2. 2b558a6 Update rockchip platform to not rely on undefined overflow behaviour by Justin Chadwell · Wed Jul 03 14:11:28 2019 +0100
  3. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  4. 00960ba rockchip/rk3399: Split M0 binary into two by Lin Huang · Fri Apr 20 15:55:21 2018 +0800
  5. ff957ed plat: fix switch statements to comply with MISRA rules by Jonathan Wright · Wed Mar 14 15:24:00 2018 +0000
  6. e363146 Fix order of remaining platform #includes by Isla Mitchell · Fri Jul 14 10:46:32 2017 +0100
  7. e22d31a rockchip/rk3399: fix DRAM gate training issue by Lin Huang · Wed Feb 22 18:24:55 2017 +0800
  8. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  9. 509f379 rockchip/rk3399: changed printf/tf_printf for console output by Caesar Wang · Thu Apr 06 08:40:24 2017 +0800
  10. be2a895 rockchip: rk3399: Use tFC value instead of tRFC value by Derek Basehore · Thu Feb 09 22:08:48 2017 -0800
  11. b07dfeb rockchip: rk3399: Fix CAS latency setting by Derek Basehore · Thu Feb 09 22:02:42 2017 -0800
  12. 035d6d6 rockchip: rk3399: disable training modules after DDR DFS by Xing Zheng · Thu Feb 09 14:51:38 2017 +0800
  13. 397046c rockchip: rk3399: Move DQS drive strength setting to M0 by Derek Basehore · Wed Feb 01 18:09:13 2017 -0800
  14. b734ba5 rockchip: rk3399: Remove dram dfs optimization by Derek Basehore · Tue Jan 31 16:37:01 2017 -0800
  15. b4a7676 rockchip: rk3399: improve the m0 enable flow by Lin Huang · Mon Dec 12 15:18:08 2016 +0800
  16. 52512c2 rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0 by Lin Huang · Thu Dec 15 15:08:47 2016 +0800
  17. dc8e82e rockchip: rk3399: enable CA training when do ddr dfs by Lin Huang · Fri Dec 16 13:59:07 2016 +0800
  18. 0e8909d rockchip: rk3399: Enable per CS training at 666MHz by Derek Basehore · Wed Nov 09 18:28:19 2016 -0800
  19. e13bc54 rockchip: rk3399: add support for ddrfreq suspend/resume by Derek Basehore · Fri Feb 24 14:31:36 2017 +0800
  20. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · Wed Oct 26 21:25:26 2016 +0800
  21. b106512 rk3399: dram: making phy into dll bypass mode at low frequency by Derek Basehore · Thu Oct 20 22:09:22 2016 -0700
  22. ff461d0 rockchip: rk3399: dram: remove dram_init and dts_timing_receive function by Derek Basehore · Thu Oct 20 20:46:43 2016 -0700
  23. 8bc1667 rockchip: Change dmc register accesses to ATF style for rk3399 by Caesar Wang · Thu Oct 27 01:12:47 2016 +0800
  24. a845690 rockchip: Break out common dram code for rk3399 by Caesar Wang · Thu Oct 27 01:12:34 2016 +0800