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git01.mediatek.com / filogic / atf / f5ec500b32e086a7df447a67a4a869f06c030bac / plat / nvidia / tegra / common / tegra_sip_calls.c
  1. 5ac9d96 Fix pointer type mismatch of handlers by Masahiro Yamada · 7 years ago
  2. e363146 Fix order of remaining platform #includes by Isla Mitchell · 7 years ago
  3. a59a7c5 Tegra: memctrl: check GPU reset state from common place by Varun Wadekar · 8 years ago
  4. fa3cf0b Use SPDX license identifiers by dp-arm · 8 years ago
  5. 14f3957 Tegra186: Support AARCH32/64 encoding for MCE calls by Varun Wadekar · 8 years ago
  6. b4a7294 Tegra: Add support for fake system suspend by Vignesh Radhakrishnan · 8 years ago
  7. e0f3dfd Tegra: SiP: 64-bit address for Video Memory base by Harvey Hsieh · 8 years ago
  8. dc79930 Tegra: implement FIQ interrupt handler by Varun Wadekar · 9 years ago
  9. 2330edd Tegra: allow SiP smc calls from Secure World by Wayne Lin · 9 years ago
  10. 923d04a Tegra: handlers for common and SoC-specific SiP calls by Varun Wadekar · 9 years ago[Renamed (82%) from plat/nvidia/tegra/soc/t210/plat_sip_calls.c]
  11. 3acb2b0 Merge pull request #845 from vwadekar/tegra-changes-from-downstream-v1 by davidcunado-arm · 8 years ago