1. 851dc7e Add ISR_EL1 to crash report by Gerald Lejeune · Tue Mar 22 11:11:46 2016 +0100
  2. 52b1ba6 Extend memory attributes to map non-cacheable memory by Sandrine Bailleux · Tue Mar 01 14:01:03 2016 +0000
  3. 92712a5 Add ARM GICv3 driver without support for legacy operation by Achin Gupta · Thu Sep 03 14:18:02 2015 +0100
  4. 94efd1f Add missing RES1 bit in SCTLR_EL1 by Vikram Kanigiri · Wed Jul 22 11:53:52 2015 +0100
  5. 0cdebbd Remove use of PLATFORM_CACHE_LINE_SIZE by Dan Handley · Mon Mar 30 17:15:16 2015 +0100
  6. 4e97e54 Use ARM CCI driver on FVP and Juno platforms by Vikram Kanigiri · Thu Feb 26 15:25:58 2015 +0000
  7. e2b2d8f Fix the array size of mpidr_aff_map_nodes_t. by Soby Mathew · Thu Dec 04 14:14:12 2014 +0000
  8. c088433 Apply errata workarounds only when major/minor revisions match. by Soby Mathew · Mon Sep 22 12:11:36 2014 +0100
  9. c93c9df Initialize SCTLR_EL1 based on MODE_RW bit by Jens Wiklander · Thu Sep 04 10:23:27 2014 +0200
  10. 798140d Juno: Implement initial platform port by Sandrine Bailleux · Thu Jul 17 16:06:39 2014 +0100
  11. 802f865 Add support for selected Cortex-A57 errata workarounds by Soby Mathew · Thu Aug 14 16:19:29 2014 +0100
  12. 38b4bc9 Add CPU specific crash reporting handlers by Soby Mathew · Thu Aug 14 13:36:41 2014 +0100
  13. 8e2f287 Add CPU specific power management operations by Soby Mathew · Thu Aug 14 12:49:05 2014 +0100
  14. c704cbc Introduce framework for CPU specific operations by Soby Mathew · Thu Aug 14 11:33:56 2014 +0100
  15. 9f09835 Simplify management of SCTLR_EL3 and SCTLR_EL1 by Achin Gupta · Fri Jul 18 18:38:28 2014 +0100
  16. 741a382 Calculate TCR bits based on VA and PA by Lin Ma · Fri Jun 27 16:56:30 2014 -0700
  17. 4e12607 Initialise CPU contexts from entry_point_info by Andrew Thoelke · Wed Jun 04 21:10:52 2014 +0100
  18. 3f78dc3 Make system register functions inline assembly by Andrew Thoelke · Mon Jun 02 15:44:43 2014 +0100
  19. ed6ff95 Split platform.h into separate headers by Dan Handley · Wed May 14 17:44:19 2014 +0100
  20. 405406d Use secure timer to generate S-EL1 interrupts by Achin Gupta · Fri May 09 12:00:17 2014 +0100
  21. 27b895e Add context library API to change a bit in SCR_EL3 by Achin Gupta · Sun May 04 18:38:28 2014 +0100
  22. 9851e42 Introduce macros to manipulate the SPSR by Vikram Kanigiri · Tue May 13 14:42:08 2014 +0100
  23. 2bd4ef2 Reduce deep nesting of header files by Dan Handley · Wed Apr 09 13:14:54 2014 +0100
  24. bcd60ba Separate BL functions out of arch.h by Dan Handley · Thu Apr 17 18:53:42 2014 +0100
  25. a70615f Move include and source files to logical locations by Dan Handley · Wed Apr 09 12:48:25 2014 +0100[Renamed from include/aarch64/arch.h]
  26. 992dc07 Merge pull request #50 from vikramkanigiri/vk/tf-issues#26 by achingupta · Thu May 01 13:16:33 2014 +0100