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git01.mediatek.com / filogic / atf / f4a70f26f26bffabb8a9d3da8ed1942149da3f65 / plat / nvidia / tegra / soc
  1. c2c3a2a Tegra186: support for the latest platform port handlers by Varun Wadekar · 9 years ago
  2. 38020c9 Tegra186: implement prepare_system_reset handler by Varun Wadekar · 9 years ago
  3. a64806a Tegra186: implement CPU_OFF handler by Varun Wadekar · 9 years ago
  4. 20c9429 Tegra186: update SYSCNT_FREQ to 31.25MHz by Varun Wadekar · 9 years ago
  5. 94d8532 Tegra186: relocate bl31.bin to the SYSRAM by Varun Wadekar · 9 years ago
  6. 782c83d Tegra186: implement prepare_system_off handler by Varun Wadekar · 8 years ago
  7. abd153c Tegra186: power on/off secondary CPUs by Varun Wadekar · 9 years ago
  8. 59c3aa0 Tegra186: SiP calls to interact with the MCE driver by Varun Wadekar · 9 years ago
  9. a0352ab Tegra186: mce: driver for the CPU complex power manager block by Varun Wadekar · 8 years ago
  10. 921b906 Tegra186: platform support for Tegra "T186" SoC by Varun Wadekar · 9 years ago
  11. 1108fc6 plat/tegra: Enable Cortex-A53 erratum 855873 workaround by Andre Przywara · 8 years ago
  12. ed3c62b Tegra210: enable errata for Cortex-A57 and Cortex-A53 CPUs by Varun Wadekar · 8 years ago
  13. 20e9fef Tegra210: assert if afflvl0/1 have incorrect state-ids by Harvey Hsieh · 8 years ago
  14. 1edb882 Tegra210: new TZDRAM base address by Varun Wadekar · 8 years ago
  15. dba8007 Tegra210: set core power state during cluster power down by Varun Wadekar · 8 years ago
  16. b7b4575 Tegra: GIC: enable FIQ interrupt handling by Varun Wadekar · 9 years ago
  17. 6eec6d6 Tegra: allow individual SoCs to restore their settings by Varun Wadekar · 9 years ago
  18. d43583c cpus: denver: disable DCO operations from platform code by Varun Wadekar · 9 years ago
  19. 6077dce Tegra: enable PSCI extended state ID processing by Varun Wadekar · 9 years ago
  20. 923d04a Tegra: handlers for common and SoC-specific SiP calls by Varun Wadekar · 9 years ago
  21. d2014c6 Tegra: init normal/crash console for platforms by Varun Wadekar · 9 years ago
  22. 7a9a285 Tegra: Memory Controller Driver (v1) by Varun Wadekar · 9 years ago
  23. b24dea9 Tegra: enable processor retention and L2/CPUECTLR access by Varun Wadekar · 9 years ago
  24. 97f2490 Tegra: define MAX_XLAT_TABLES and MAX_MMAP_REGIONS per-platform by Varun Wadekar · 9 years ago
  25. cbdace1 Tegra: SoC specific SiP handlers by Varun Wadekar · 9 years ago
  26. a1176ba Tegra: include flowctlr driver from SoC specific makefiles by Varun Wadekar · 9 years ago
  27. e82e29c Implement plat_get_syscnt_freq2 on platforms by Antonio Nino Diaz · 8 years ago
  28. 3c0087a Move `plat_get_syscnt_freq()` to arm_common.c by Yatharth Kochar · 9 years ago
  29. a78bb1b Tegra: remove support for legacy platform APIs by Varun Wadekar · 9 years ago
  30. 8b82fae Tegra: introduce per-soc system reset handler by Varun Wadekar · 9 years ago
  31. 4e9c231 Tegra210: wait for 512 timer ticks before retention entry by Varun Wadekar · 9 years ago
  32. e98a146 Tegra132: set TZDRAM_BASE to 0xF5C00000 by Varun Wadekar · 9 years ago
  33. bc78744 Tegra210: enable WRAP to INCR burst type conversions by Varun Wadekar · 9 years ago
  34. 0f3baa0 Tegra: Support for Tegra's T132 platforms by Varun Wadekar · 9 years ago
  35. 254441d Tegra: implement per-SoC validate_power_state() handler by Varun Wadekar · 9 years ago
  36. 5f4e643 Tegra: T210: include CPU files from SoC's platform.mk by Varun Wadekar · 9 years ago
  37. d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · 9 years ago
  38. 6cab707 Tegra210: lock PMC registers holding CPU vector addresses by Varun Wadekar · 9 years ago
  39. 071b787 Tegra210: deassert CPU reset signals during power on by Varun Wadekar · 9 years ago
  40. 81b1383 Implement get_sys_suspend_power_state() handler for Tegra by Varun Wadekar · 9 years ago
  41. b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · 9 years ago