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git01.mediatek.com / filogic / atf / f40bc2cfe36e4f159daa3cb17f23da318a09ff9d / plat / xilinx / zynqmp / zynqmp_def.h
  1. 1209b26 zynqmp: Remove dead code by Soren Brinkmann · 8 years ago
  2. 836418d zynqmp: Fix UART1 base address by Soren Brinkmann · 8 years ago
  3. cfcb1a2 zynqmp: Do not alter system counter by Soren Brinkmann · 8 years ago
  4. cf4e714 zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1 by Naga Sureshkumar Relli · 8 years ago
  5. 99c0d7b zynqmp: Add option to select between Cadence UARTs by Soren Brinkmann · 8 years ago
  6. 845cd5c zynqmp: Reduce mapped memory area by Soren Brinkmann · 9 years ago
  7. ef8f559 zynqmp: FSBL->ATF handover by Michal Simek · 9 years ago
  8. b43d943 zynqmp: Introduce zynqmp_get_bootmode by Soren Brinkmann · 9 years ago
  9. 4a9ca04 zynqmp: Revise memory configuration options by Soren Brinkmann · 9 years ago
  10. 76fcae3 Add support for Xilinx Zynq UltraScale+ MPSOC by Soren Brinkmann · 9 years ago