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git01.mediatek.com / filogic / atf / f3d9b84303aa9ac4a76c2f44e897808f8ea97ef1 / plat / nvidia / tegra / soc / t186 / plat_secondary.c
  1. f3d9b84 Tegra186: disable PROGRAMMABLE_RESET_ADDRESS by Varun Wadekar · 6 years ago
  2. 186485e Tegra: rename secure scratch register macros by Steven Kao · 7 years ago
  3. 8304fc8 Tegra186: secondary: fix MISRA violations for Rules 8.6, 11.1 by Varun Wadekar · 7 years ago
  4. 5a4ce00 Tegra186: fix defects flagged by MISRA scan by Anthony Zhou · 7 years ago
  5. faad346 Tegra186: secondary: fix MISRA defects by Anthony Zhou · 7 years ago
  6. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  7. 4b32e62 libc: Fix all includes in codebase by Antonio Nino Diaz · 6 years ago
  8. fa3cf0b Use SPDX license identifiers by dp-arm · 7 years ago
  9. d007f76 Tegra186: Update API for reset vector ARI by Krishna Sitaraman · 8 years ago
  10. 93bed2a Tegra186: save/restore BL31 context to/from TZDRAM by Varun Wadekar · 8 years ago
  11. abd153c Tegra186: power on/off secondary CPUs by Varun Wadekar · 9 years ago
  12. 921b906 Tegra186: platform support for Tegra "T186" SoC by Varun Wadekar · 9 years ago