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git01.mediatek.com / filogic / atf / efabaa90e39443bf6f96bdd52b148f9691795b8f / plat / rockchip / rk3399 / drivers / dram / dfs.c
  1. 509f379 rockchip/rk3399: changed printf/tf_printf for console output by Caesar Wang · Thu Apr 06 08:40:24 2017 +0800
  2. be2a895 rockchip: rk3399: Use tFC value instead of tRFC value by Derek Basehore · Thu Feb 09 22:08:48 2017 -0800
  3. b07dfeb rockchip: rk3399: Fix CAS latency setting by Derek Basehore · Thu Feb 09 22:02:42 2017 -0800
  4. 035d6d6 rockchip: rk3399: disable training modules after DDR DFS by Xing Zheng · Thu Feb 09 14:51:38 2017 +0800
  5. 397046c rockchip: rk3399: Move DQS drive strength setting to M0 by Derek Basehore · Wed Feb 01 18:09:13 2017 -0800
  6. b734ba5 rockchip: rk3399: Remove dram dfs optimization by Derek Basehore · Tue Jan 31 16:37:01 2017 -0800
  7. b4a7676 rockchip: rk3399: improve the m0 enable flow by Lin Huang · Mon Dec 12 15:18:08 2016 +0800
  8. 52512c2 rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0 by Lin Huang · Thu Dec 15 15:08:47 2016 +0800
  9. dc8e82e rockchip: rk3399: enable CA training when do ddr dfs by Lin Huang · Fri Dec 16 13:59:07 2016 +0800
  10. 0e8909d rockchip: rk3399: Enable per CS training at 666MHz by Derek Basehore · Wed Nov 09 18:28:19 2016 -0800
  11. e13bc54 rockchip: rk3399: add support for ddrfreq suspend/resume by Derek Basehore · Fri Feb 24 14:31:36 2017 +0800
  12. 93280b7 rk3399: dram: use PMU M0 to do ddr frequency scaling by Xing Zheng · Wed Oct 26 21:25:26 2016 +0800
  13. b106512 rk3399: dram: making phy into dll bypass mode at low frequency by Derek Basehore · Thu Oct 20 22:09:22 2016 -0700
  14. ff461d0 rockchip: rk3399: dram: remove dram_init and dts_timing_receive function by Derek Basehore · Thu Oct 20 20:46:43 2016 -0700
  15. 8bc1667 rockchip: Change dmc register accesses to ATF style for rk3399 by Caesar Wang · Thu Oct 27 01:12:47 2016 +0800
  16. a845690 rockchip: Break out common dram code for rk3399 by Caesar Wang · Thu Oct 27 01:12:34 2016 +0800